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////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// t_sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Testbench for generic sqrt operation
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_sqrt_pipelined();
parameter
INPUT_BITS = 4;
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;
reg [INPUT_BITS-1:0] radicand;
reg clk, start, reset_n;
wire [OUTPUT_BITS-1:0] root;
wire data_valid;
// wire [7:0] root_good;
sqrt_pipelined
#(
.INPUT_BITS(INPUT_BITS)
)
sqrt_pipelined
(
.clk(clk),
.reset_n(reset_n),
.start(start),
.radicand(radicand),
.data_valid(data_valid),
.root(root)
);
initial begin
radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;
#10 reset_n = 0; clk = 0;
#50 reset_n = 1; radicand = 0;
// #40 radicand = 81; start = 1;
// #10 radicand = 16'bx; start = 0;
#10000 $finish;
end
always
#5 clk = ~clk;
always begin
#10 radicand = radicand + 1; start = 1;
#10 start = 0;
end
// always begin
// #80 start = 1;
// #10 start = 0;
// end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// t_sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Testbench for generic sqrt operation
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_sqrt_pipelined();
parameter
INPUT_BITS = 4;
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;
reg [INPUT_BITS-1:0] radicand;
reg clk, start, reset_n;
wire [OUTPUT_BITS-1:0] root;
wire data_valid;
// wire [7:0] root_good;
sqrt_pipelined
#(
.INPUT_BITS(INPUT_BITS)
)
sqrt_pipelined
(
.clk(clk),
.reset_n(reset_n),
.start(start),
.radicand(radicand),
.data_valid(data_valid),
.root(root)
);
initial begin
radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;
#10 reset_n = 0; clk = 0;
#50 reset_n = 1; radicand = 0;
// #40 radicand = 81; start = 1;
// #10 radicand = 16'bx; start = 0;
#10000 $finish;
end
always
#5 clk = ~clk;
always begin
#10 radicand = radicand + 1; start = 1;
#10 start = 0;
end
// always begin
// #80 start = 1;
// #10 start = 0;
// end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// t_sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Testbench for generic sqrt operation
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_sqrt_pipelined();
parameter
INPUT_BITS = 4;
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;
reg [INPUT_BITS-1:0] radicand;
reg clk, start, reset_n;
wire [OUTPUT_BITS-1:0] root;
wire data_valid;
// wire [7:0] root_good;
sqrt_pipelined
#(
.INPUT_BITS(INPUT_BITS)
)
sqrt_pipelined
(
.clk(clk),
.reset_n(reset_n),
.start(start),
.radicand(radicand),
.data_valid(data_valid),
.root(root)
);
initial begin
radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;
#10 reset_n = 0; clk = 0;
#50 reset_n = 1; radicand = 0;
// #40 radicand = 81; start = 1;
// #10 radicand = 16'bx; start = 0;
#10000 $finish;
end
always
#5 clk = ~clk;
always begin
#10 radicand = radicand + 1; start = 1;
#10 start = 0;
end
// always begin
// #80 start = 1;
// #10 start = 0;
// end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// t_sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Testbench for generic sqrt operation
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_sqrt_pipelined();
parameter
INPUT_BITS = 4;
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;
reg [INPUT_BITS-1:0] radicand;
reg clk, start, reset_n;
wire [OUTPUT_BITS-1:0] root;
wire data_valid;
// wire [7:0] root_good;
sqrt_pipelined
#(
.INPUT_BITS(INPUT_BITS)
)
sqrt_pipelined
(
.clk(clk),
.reset_n(reset_n),
.start(start),
.radicand(radicand),
.data_valid(data_valid),
.root(root)
);
initial begin
radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;
#10 reset_n = 0; clk = 0;
#50 reset_n = 1; radicand = 0;
// #40 radicand = 81; start = 1;
// #10 radicand = 16'bx; start = 0;
#10000 $finish;
end
always
#5 clk = ~clk;
always begin
#10 radicand = radicand + 1; start = 1;
#10 start = 0;
end
// always begin
// #80 start = 1;
// #10 start = 0;
// end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// t_sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Testbench for generic sqrt operation
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_sqrt_pipelined();
parameter
INPUT_BITS = 4;
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;
reg [INPUT_BITS-1:0] radicand;
reg clk, start, reset_n;
wire [OUTPUT_BITS-1:0] root;
wire data_valid;
// wire [7:0] root_good;
sqrt_pipelined
#(
.INPUT_BITS(INPUT_BITS)
)
sqrt_pipelined
(
.clk(clk),
.reset_n(reset_n),
.start(start),
.radicand(radicand),
.data_valid(data_valid),
.root(root)
);
initial begin
radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;
#10 reset_n = 0; clk = 0;
#50 reset_n = 1; radicand = 0;
// #40 radicand = 81; start = 1;
// #10 radicand = 16'bx; start = 0;
#10000 $finish;
end
always
#5 clk = ~clk;
always begin
#10 radicand = radicand + 1; start = 1;
#10 start = 0;
end
// always begin
// #80 start = 1;
// #10 start = 0;
// end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/12/2016 06:26:54 PM
// Design Name:
// Module Name: shift_mux_array
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module shift_mux_array
#(parameter SWR=26, parameter LEVEL=5)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
genvar j;
generate for (j=0; j<=SWR-1 ; j=j+1) begin
localparam sh=(2**LEVEL)+j; //value for second mux input. It changes in exponentation by 2 for each level
case (sh>SWR-1)
1'b1:begin
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (bit_shift_i),
.S (Data_o[j])
);
end
1'b0:begin
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (Data_i[sh]),
.S (Data_o[j])
);
end
endcase
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/12/2016 06:26:54 PM
// Design Name:
// Module Name: shift_mux_array
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module shift_mux_array
#(parameter SWR=26, parameter LEVEL=5)
(
input wire [SWR-1:0] Data_i,
input wire select_i,
input wire bit_shift_i,
output wire [SWR-1:0] Data_o
);
genvar j;
generate for (j=0; j<=SWR-1 ; j=j+1) begin
localparam sh=(2**LEVEL)+j; //value for second mux input. It changes in exponentation by 2 for each level
case (sh>SWR-1)
1'b1:begin
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (bit_shift_i),
.S (Data_o[j])
);
end
1'b0:begin
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(select_i),
.D0 (Data_i[j]),
.D1 (Data_i[sh]),
.S (Data_o[j])
);
end
endcase
end
endgenerate
endmodule
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <jepler@unpythonic.net>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, quadA, quadB, quadZ, up, down);
parameter QW=14;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
wire do_tristate;
reg[9:0] real_dout; output [9:0] dout = do_tristate ? 10'bZZZZZZZZZZ : real_dout;
input [7:0] din;
input [3:0] quadA;
input [3:0] quadB;
input [3:0] quadZ;
wire[3:0] real_up; output [3:0] up = do_tristate ? 4'bZZZZ : real_up;
wire[3:0] real_down; output [3:0] down = do_tristate ? 4'bZZZZ : real_down;
reg Zpolarity;
wire [2*QW:0] quad0, quad1, quad2, quad3;
wire do_enable_wdt;
wire pwm_at_top;
wdt w(clk, do_enable_wdt, pwm_at_top, do_tristate);
// PWM stuff
// PWM clock is about 20kHz for clk @ 40MHz, 11-bit cnt
reg [10:0] pwmcnt;
wire [10:0] top = 11'd2046;
assign pwm_at_top = (pwmcnt == top);
reg [15:0] pwm0, pwm1, pwm2, pwm3;
always @(posedge clk) begin
if(pwm_at_top) pwmcnt <= 0;
else pwmcnt <= pwmcnt + 11'd1;
end
wire [10:0] pwmrev = {
pwmcnt[4], pwmcnt[5], pwmcnt[6], pwmcnt[7], pwmcnt[8], pwmcnt[9],
pwmcnt[10], pwmcnt[3:0]};
wire [10:0] pwmcmp0 = pwm0[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp1 = pwm1[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp2 = pwm2[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp3 = pwm3[14] ? pwmrev : pwmcnt;
wire pwmact0 = pwm0[10:0] > pwmcmp0;
wire pwmact1 = pwm1[10:0] > pwmcmp0;
wire pwmact2 = pwm2[10:0] > pwmcmp0;
wire pwmact3 = pwm3[10:0] > pwmcmp0;
assign real_up[0] = pwm0[12] ^ (pwm0[15] ? 1'd0 : pwmact0);
assign real_up[1] = pwm1[12] ^ (pwm1[15] ? 1'd0 : pwmact1);
assign real_up[2] = pwm2[12] ^ (pwm2[15] ? 1'd0 : pwmact2);
assign real_up[3] = pwm3[12] ^ (pwm3[15] ? 1'd0 : pwmact3);
assign real_down[0] = pwm0[13] ^ (~pwm0[15] ? 1'd0 : pwmact0);
assign real_down[1] = pwm1[13] ^ (~pwm1[15] ? 1'd0 : pwmact1);
assign real_down[2] = pwm2[13] ^ (~pwm2[15] ? 1'd0 : pwmact2);
assign real_down[3] = pwm3[13] ^ (~pwm3[15] ? 1'd0 : pwmact3);
// Quadrature stuff
// Quadrature is digitized at 40MHz into 14-bit counters
// Read up to 2^13 pulses / polling period = 8MHz for 1kHz servo period
reg qtest;
wire qr0, qr1, qr2, qr3;
quad q0(clk, qtest ? real_dout[0] : quadA[0], qtest ? real_dout[1] : quadB[0], qtest ? real_dout[2] : quadZ[0]^Zpolarity, qr0, quad0);
quad q1(clk, quadA[1], quadB[1], quadZ[1]^Zpolarity, qr1, quad1);
quad q2(clk, quadA[2], quadB[2], quadZ[2]^Zpolarity, qr2, quad2);
quad q3(clk, quadA[3], quadB[3], quadZ[3]^Zpolarity, qr3, quad3);
// EPP stuff
wire EPP_write = ~nWrite;
wire EPP_read = nWrite;
wire EPP_addr_strobe = ~nAddrStr;
wire EPP_data_strobe = ~nDataStr;
wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe;
wire EPP_wait; assign nWait = ~EPP_wait;
wire [7:0] EPP_datain = pport_data;
wire [7:0] EPP_dataout; assign pport_data = EPP_dataout;
reg [4:0] EPP_strobe_reg;
always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe};
wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01);
// reg led;
assign EPP_wait = EPP_strobe_reg[4];
reg[4:0] addr_reg;
reg[7:0] lowbyte;
always @(posedge clk)
if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin
addr_reg <= EPP_datain[4:0];
end
else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin
if(addr_reg[3:0] == 4'd1) pwm0 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd3) pwm1 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd5) pwm2 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd7) pwm3 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd9) begin
real_dout <= { EPP_datain[1:0], lowbyte };
Zpolarity <= EPP_datain[7];
qtest <= EPP_datain[5];
end
else lowbyte <= EPP_datain;
end
end
reg [31:0] data_buf;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin
if(addr_reg[4:2] == 3'd0) data_buf <= quad0;
else if(addr_reg[4:2] == 3'd1) data_buf <= quad1;
else if(addr_reg[4:2] == 3'd2) data_buf <= quad2;
else if(addr_reg[4:2] == 3'd3) data_buf <= quad3;
else if(addr_reg[4:2] == 3'd4)
data_buf <= {quadA, quadB, quadZ, din};
end
end
// the addr_reg test looks funny because it is auto-incremented in an always
// block so "1" reads the low byte, "2 and "3" read middle bytes, and "0"
// reads the high byte I have a feeling that I'm doing this in the wrong way.
wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] :
(addr_reg[1:0] == 2'd2 ? data_buf[15:8] :
(addr_reg[1:0] == 2'd3 ? data_buf[23:16] :
data_buf[31:24]));
wire [7:0] EPP_data_mux = data_reg;
assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ;
assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
assign qr0 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd0);
assign qr1 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd1);
assign qr2 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd2);
assign qr3 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd3);
assign led = do_tristate ? 1'BZ : (real_up[0] ^ real_down[0]);
assign nConfig = epp_nReset; // 1'b1;
endmodule
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <jepler@unpythonic.net>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, quadA, quadB, quadZ, up, down);
parameter QW=14;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
wire do_tristate;
reg[9:0] real_dout; output [9:0] dout = do_tristate ? 10'bZZZZZZZZZZ : real_dout;
input [7:0] din;
input [3:0] quadA;
input [3:0] quadB;
input [3:0] quadZ;
wire[3:0] real_up; output [3:0] up = do_tristate ? 4'bZZZZ : real_up;
wire[3:0] real_down; output [3:0] down = do_tristate ? 4'bZZZZ : real_down;
reg Zpolarity;
wire [2*QW:0] quad0, quad1, quad2, quad3;
wire do_enable_wdt;
wire pwm_at_top;
wdt w(clk, do_enable_wdt, pwm_at_top, do_tristate);
// PWM stuff
// PWM clock is about 20kHz for clk @ 40MHz, 11-bit cnt
reg [10:0] pwmcnt;
wire [10:0] top = 11'd2046;
assign pwm_at_top = (pwmcnt == top);
reg [15:0] pwm0, pwm1, pwm2, pwm3;
always @(posedge clk) begin
if(pwm_at_top) pwmcnt <= 0;
else pwmcnt <= pwmcnt + 11'd1;
end
wire [10:0] pwmrev = {
pwmcnt[4], pwmcnt[5], pwmcnt[6], pwmcnt[7], pwmcnt[8], pwmcnt[9],
pwmcnt[10], pwmcnt[3:0]};
wire [10:0] pwmcmp0 = pwm0[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp1 = pwm1[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp2 = pwm2[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp3 = pwm3[14] ? pwmrev : pwmcnt;
wire pwmact0 = pwm0[10:0] > pwmcmp0;
wire pwmact1 = pwm1[10:0] > pwmcmp0;
wire pwmact2 = pwm2[10:0] > pwmcmp0;
wire pwmact3 = pwm3[10:0] > pwmcmp0;
assign real_up[0] = pwm0[12] ^ (pwm0[15] ? 1'd0 : pwmact0);
assign real_up[1] = pwm1[12] ^ (pwm1[15] ? 1'd0 : pwmact1);
assign real_up[2] = pwm2[12] ^ (pwm2[15] ? 1'd0 : pwmact2);
assign real_up[3] = pwm3[12] ^ (pwm3[15] ? 1'd0 : pwmact3);
assign real_down[0] = pwm0[13] ^ (~pwm0[15] ? 1'd0 : pwmact0);
assign real_down[1] = pwm1[13] ^ (~pwm1[15] ? 1'd0 : pwmact1);
assign real_down[2] = pwm2[13] ^ (~pwm2[15] ? 1'd0 : pwmact2);
assign real_down[3] = pwm3[13] ^ (~pwm3[15] ? 1'd0 : pwmact3);
// Quadrature stuff
// Quadrature is digitized at 40MHz into 14-bit counters
// Read up to 2^13 pulses / polling period = 8MHz for 1kHz servo period
reg qtest;
wire qr0, qr1, qr2, qr3;
quad q0(clk, qtest ? real_dout[0] : quadA[0], qtest ? real_dout[1] : quadB[0], qtest ? real_dout[2] : quadZ[0]^Zpolarity, qr0, quad0);
quad q1(clk, quadA[1], quadB[1], quadZ[1]^Zpolarity, qr1, quad1);
quad q2(clk, quadA[2], quadB[2], quadZ[2]^Zpolarity, qr2, quad2);
quad q3(clk, quadA[3], quadB[3], quadZ[3]^Zpolarity, qr3, quad3);
// EPP stuff
wire EPP_write = ~nWrite;
wire EPP_read = nWrite;
wire EPP_addr_strobe = ~nAddrStr;
wire EPP_data_strobe = ~nDataStr;
wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe;
wire EPP_wait; assign nWait = ~EPP_wait;
wire [7:0] EPP_datain = pport_data;
wire [7:0] EPP_dataout; assign pport_data = EPP_dataout;
reg [4:0] EPP_strobe_reg;
always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe};
wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01);
// reg led;
assign EPP_wait = EPP_strobe_reg[4];
reg[4:0] addr_reg;
reg[7:0] lowbyte;
always @(posedge clk)
if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin
addr_reg <= EPP_datain[4:0];
end
else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin
if(addr_reg[3:0] == 4'd1) pwm0 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd3) pwm1 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd5) pwm2 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd7) pwm3 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd9) begin
real_dout <= { EPP_datain[1:0], lowbyte };
Zpolarity <= EPP_datain[7];
qtest <= EPP_datain[5];
end
else lowbyte <= EPP_datain;
end
end
reg [31:0] data_buf;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin
if(addr_reg[4:2] == 3'd0) data_buf <= quad0;
else if(addr_reg[4:2] == 3'd1) data_buf <= quad1;
else if(addr_reg[4:2] == 3'd2) data_buf <= quad2;
else if(addr_reg[4:2] == 3'd3) data_buf <= quad3;
else if(addr_reg[4:2] == 3'd4)
data_buf <= {quadA, quadB, quadZ, din};
end
end
// the addr_reg test looks funny because it is auto-incremented in an always
// block so "1" reads the low byte, "2 and "3" read middle bytes, and "0"
// reads the high byte I have a feeling that I'm doing this in the wrong way.
wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] :
(addr_reg[1:0] == 2'd2 ? data_buf[15:8] :
(addr_reg[1:0] == 2'd3 ? data_buf[23:16] :
data_buf[31:24]));
wire [7:0] EPP_data_mux = data_reg;
assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ;
assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
assign qr0 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd0);
assign qr1 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd1);
assign qr2 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd2);
assign qr3 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd3);
assign led = do_tristate ? 1'BZ : (real_up[0] ^ real_down[0]);
assign nConfig = epp_nReset; // 1'b1;
endmodule
|
// This is a component of pluto_step, a hardware step waveform generator
// Copyright 2007 Jeff Epler <jepler@unpythonic.net>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// install ubuntu package "verilog" from universe
// Compile with: iverilog -DTESTING test_stepgen.v stepgen.v
// run with "./a.out | less" and look at output for problems
module test_stepgen();
reg clk;
reg [4:0] vel;
wire [19:0] pos;
wire step, dir;
stepgen #(16,4,16) s(clk, 1, pos, vel, 1, 0, step, dir, 3);
integer q;
reg ost;
initial begin
vel = 5'h8; // two useful test cases:
// vel=5'h8 (max step speed)
// vel=5'h2 (~1 step per repeat)
q = 0;
repeat(50) begin
repeat(50) begin
#20 clk<=1;
#20 clk<=0;
if(step && !ost) begin
if(dir) q = q+1;
else q = q - 1;
end
ost <= step;
$display("%d %d %x %x %d %d %d %d %d",
step, dir, vel, pos, s.state, s.ones, s.pbit, s.timer, q);
end
vel = 6'h20 - vel;
end
end
endmodule
|
// This is a component of pluto_step, a hardware step waveform generator
// Copyright 2007 Jeff Epler <jepler@unpythonic.net>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// install ubuntu package "verilog" from universe
// Compile with: iverilog -DTESTING test_stepgen.v stepgen.v
// run with "./a.out | less" and look at output for problems
module test_stepgen();
reg clk;
reg [4:0] vel;
wire [19:0] pos;
wire step, dir;
stepgen #(16,4,16) s(clk, 1, pos, vel, 1, 0, step, dir, 3);
integer q;
reg ost;
initial begin
vel = 5'h8; // two useful test cases:
// vel=5'h8 (max step speed)
// vel=5'h2 (~1 step per repeat)
q = 0;
repeat(50) begin
repeat(50) begin
#20 clk<=1;
#20 clk<=0;
if(step && !ost) begin
if(dir) q = q+1;
else q = q - 1;
end
ost <= step;
$display("%d %d %x %x %d %d %d %d %d",
step, dir, vel, pos, s.state, s.ones, s.pbit, s.timer, q);
end
vel = 6'h20 - vel;
end
end
endmodule
|
// This is a component of pluto_step, a hardware step waveform generator
// Copyright 2007 Jeff Epler <jepler@unpythonic.net>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// install ubuntu package "verilog" from universe
// Compile with: iverilog -DTESTING test_stepgen.v stepgen.v
// run with "./a.out | less" and look at output for problems
module test_stepgen();
reg clk;
reg [4:0] vel;
wire [19:0] pos;
wire step, dir;
stepgen #(16,4,16) s(clk, 1, pos, vel, 1, 0, step, dir, 3);
integer q;
reg ost;
initial begin
vel = 5'h8; // two useful test cases:
// vel=5'h8 (max step speed)
// vel=5'h2 (~1 step per repeat)
q = 0;
repeat(50) begin
repeat(50) begin
#20 clk<=1;
#20 clk<=0;
if(step && !ost) begin
if(dir) q = q+1;
else q = q - 1;
end
ost <= step;
$display("%d %d %x %x %d %d %d %d %d",
step, dir, vel, pos, s.state, s.ones, s.pbit, s.timer, q);
end
vel = 6'h20 - vel;
end
end
endmodule
|
/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: fifo_generator_vlog_beh.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_vlog_beh.v
* |
* +-fifo_generator_v13_1_3_bhv_ver_as
* |
* +-fifo_generator_v13_1_3_bhv_ver_ss
* |
* +-fifo_generator_v13_1_3_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
wire wr_rst_busy_o;
wire wr_rst_busy_ntve;
wire wr_rst_busy_axis;
wire wr_rst_busy_wach;
wire wr_rst_busy_wdch;
wire wr_rst_busy_wrch;
wire wr_rst_busy_rach;
wire wr_rst_busy_rdch;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o;
assign wr_rst_busy = wr_rst_busy_o;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
fifo_generator_v13_1_3_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v13_1_3_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy_o (wr_rst_busy_o),
.wr_rst_busy (wr_rst_busy_i),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
reg [3:0] axi_rst = 4'h0 ;
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
axi_rst <= 4'hf;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
axi_rst <= #`TCQ {axi_rst[2:0],1'b0};
end
end
assign axi_rs_rst = axi_rst[3];//rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //fifo_generator_v13_1_3
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module fifo_generator_v13_1_3_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_INTERFACE_TYPE = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex7", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR,
output wr_rst_busy_o,
output wr_rst_busy,
output rd_rst_busy,
output wr_rst_i_out,
output rd_rst_i_out
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg empty_fb ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
wire empty_p0_out;
always @* rst_delayed <= #`TCQ RST ;
always @* empty_fb <= #`TCQ empty_p0_out ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 0;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
reg rd_rst_asreg_d3 = 0;
reg rd_rst_reg = 0;
wire rd_rst_comb;
reg wr_rst_d0 = 0;
reg wr_rst_d1 = 0;
reg wr_rst_d2 = 0;
reg rd_rst_d0 = 0;
reg rd_rst_d1 = 0;
reg rd_rst_d2 = 0;
reg rd_rst_d3 = 0;
reg wrrst_done = 0;
reg rdrst_done = 0;
reg wr_rst_asreg = 0;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
reg wr_rst_asreg_d3 = 0;
reg rd_rst_wr_d0 = 0;
reg rd_rst_wr_d1 = 0;
reg rd_rst_wr_d2 = 0;
reg wr_rst_reg = 0;
reg rst_active_i = 1'b1;
reg rst_delayed_d1 = 1'b1;
reg rst_delayed_d2 = 1'b1;
wire wr_rst_comb;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 0;
reg srst_asreg = 0;
wire rst_asreg_d1;
wire rst_asreg_d2;
reg srst_asreg_d1 = 0;
reg srst_asreg_d2 = 0;
reg rst_reg = 0;
reg srst_reg = 0;
wire rst_comb;
wire srst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}};
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire fifo_empty_fb;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
wire inject_sbit_err;
wire inject_dbit_err;
wire safety_ckt_wr_rst;
wire safety_ckt_rd_rst;
reg sckt_wr_rst_i_q = 1'b0;
wire w_fab_read_data_valid_i;
wire w_read_data_valid_i;
wire w_ram_valid_i;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
assign wr_rst_i_out = wr_rst_i;
assign rd_rst_i_out = rd_rst_i;
assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];
generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o
wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;
always @ (posedge clk_i)
sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy};
end endgenerate
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1
//Common Clock Behavioral Model
fifo_generator_v13_1_3_bhv_ver_ss
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.CLK (CLK),
.RST (rst_i),
.SRST (srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.USER_EMPTY_FB (empty_fb),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.fab_read_data_valid_i (w_fab_read_data_valid_i),
.read_data_valid_i (w_read_data_valid_i),
.ram_valid_i (w_ram_valid_i),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v13_1_3_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
//wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.fab_read_data_valid_i_o (w_fab_read_data_valid_i),
.read_data_valid_i_o (w_read_data_valid_i),
.ram_valid_i_o (w_ram_valid_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= 1;
ALMOSTEMPTY_P0_OUT_Q <= 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= 0;
end else begin
//if (srst_delayed && (C_HAS_SRST == 1) ) begin
if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed | wr_rst_busy | rd_rst_busy)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate // gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST | wr_rst_busy | rd_rst_busy) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30_both
endgenerate
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
end //block_ic_both
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3_both
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;
localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE :
(C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2;
reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}};
reg [1:0] wrst_cc = {2{1'b0}};
reg [1:0] rrst_cc = {2{1'b0}};
generate
if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt
reg[1:0] rst_d1_safety =1;
reg[1:0] rst_d2_safety =1;
reg[1:0] rst_d3_safety =1;
reg[1:0] rst_d4_safety =1;
reg[1:0] rst_d5_safety =1;
reg[1:0] rst_d6_safety =1;
reg[1:0] rst_d7_safety =1;
always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst
if (rst_2_sync_safety == 1'b1) begin
rst_d1_safety <= 1'b1;
rst_d2_safety <= 1'b1;
rst_d3_safety <= 1'b1;
rst_d4_safety <= 1'b1;
rst_d5_safety <= 1'b1;
rst_d6_safety <= 1'b1;
rst_d7_safety <= 1'b1;
end
else begin
rst_d1_safety <= #`TCQ 1'b0;
rst_d2_safety <= #`TCQ rst_d1_safety;
rst_d3_safety <= #`TCQ rst_d2_safety;
rst_d4_safety <= #`TCQ rst_d3_safety;
rst_d5_safety <= #`TCQ rst_d4_safety;
rst_d6_safety <= #`TCQ rst_d5_safety;
rst_d7_safety <= #`TCQ rst_d6_safety;
end //if
end //prst
always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety
if(rst_d7_safety == 1 && WR_EN == 1) begin
$display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.");
end //if
end //always
end // grst_safety_ckt
endgenerate
// if (C_EN_SAFET_CKT == 1)
// assertion:the reset shud be atleast 3 cycles wide.
generate
reg safety_ckt_wr_rst_i = 1'b0;
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
// end : gnrst_sync
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
reg fifo_wrst_done = 1'b0;
reg fifo_rrst_done = 1'b0;
reg sckt_wrst_i = 1'b0;
reg sckt_wrst_i_q = 1'b0;
reg rd_rst_active = 1'b0;
reg rd_rst_middle = 1'b0;
reg sckt_rd_rst_d1 = 1'b0;
reg [1:0] rst_delayed_ic_w = 2'h0;
wire rst_delayed_ic_w_i;
reg [1:0] rst_delayed_ic_r = 2'h0;
wire rst_delayed_ic_r_i;
wire arst_sync_rst;
wire fifo_rst_done;
wire fifo_rst_active;
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed_ic_w_i;
assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1];
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0;
assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done;
assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1];
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_w <= 2'b11;
else
rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0};
end
assign rst_delayed_ic_w_i = rst_delayed_ic_w[1];
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_r <= 2'b11;
else
rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0};
end
assign rst_delayed_ic_r_i = rst_delayed_ic_r[1];
always @(posedge WR_CLK) begin
sckt_wrst_i_q <= #`TCQ sckt_wrst_i;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q;
if (arst_sync_rst && ~fifo_rst_active)
sckt_wrst_i <= #`TCQ 1'b1;
else if (sckt_wrst_i && fifo_rst_done)
sckt_wrst_i <= #`TCQ 1'b0;
else
sckt_wrst_i <= #`TCQ sckt_wrst_i;
if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1])
fifo_rrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_rrst_done <= #`TCQ 1'b0;
else
fifo_rrst_done <= #`TCQ fifo_rrst_done;
if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1])
fifo_wrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_wrst_done <= #`TCQ 1'b0;
else
fifo_wrst_done <= #`TCQ fifo_wrst_done;
end
always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin
if (rst_delayed_ic_w_i == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg};
wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst};
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i};
end
assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin
if (rst_delayed_ic_r_i == 1'b1) begin
rd_rst_asreg <= 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg};
rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2};
sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst;
if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin
rd_rst_active <= #`TCQ 1'b1;
rd_rst_middle <= #`TCQ 1'b1;
end else if (safety_ckt_rd_rst)
rd_rst_active <= #`TCQ 1'b0;
else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst)
rd_rst_middle <= #`TCQ 1'b0;
end
assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2];
assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1];
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0;
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_ic_rst
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
reg [1:0] rst_delayed_cc = 2'h0;
wire rst_delayed_cc_i;
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed_cc_i;
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
rst_delayed_cc <= 2'b11;
else
rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0};
end
assign rst_delayed_cc_i = rst_delayed_cc[1];
always @(posedge CLK or posedge rst_delayed_cc_i) begin
if (rst_delayed_cc_i == 1'b1) begin
rst_asreg <= 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg};
wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]};
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q;
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i};
end
assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_cc_rst
end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
always @* rst_full_ff_i <= rst_reg;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
// end : g8s_cc_rst
end else begin
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
assign safety_ckt_wr_rst = 1'b0;
assign safety_ckt_rd_rst = 1'b0;
end
endgenerate
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
reg rst_d5 = 1'b0;
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b1;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b1;
end else begin
rst_d1 <= #`TCQ wr_rst_busy;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
always @* rst_full_gen_i <= rst_d3;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1
endmodule //fifo_generator_v13_1_3_conv_ver
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v13_1_3_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input SAFETY_CKT_WR_RST,
input SAFETY_CKT_RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
input fab_read_data_valid_i,
input read_data_valid_i,
input ram_valid_i,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg EMPTY_FB = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
generate
if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin
EMPTY <= 1'b1;
ALMOST_EMPTY <= 1'b1;
rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)
EMPTY_FB <= #`TCQ 1'b1;
else if (empty_int)
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ 1'b0;
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF) begin
FULL <= C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= C_FULL_FLAGS_RST_VAL;
end else begin
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
always @ (posedge WR_CLK or posedge wr_rst_i)
begin
if (wr_rst_i) begin
wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= 0;
stage2_valid <= 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out1;
wire valid_out2;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
reg valid_d2 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_d2 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Safety-ckt logic with embedded reg/fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d1;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end
end
endgenerate
//***************************************************************************
// Safety-ckt logic with embedded reg + fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else begin
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end
endgenerate
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
valid_d1: valid_i;
assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
valid_d2: valid_i;
assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3) begin
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;
// assign diff_rd_wr_1 = diff_rd_wr +2'h2;
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
//if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b0;
//else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b1;
//else
rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
end
end
end
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_d2 <= 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
valid_d2 <= #`TCQ valid_d1;
end
// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
// valid_d2 <= #`TCQ valid_d1;
// end
end
end
endgenerate
//Capture delayed version of dout
/**************************************************************************
*embedded/fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG < 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
endgenerate
/**************************************************************************
*embedded + fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG == 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)
wr_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)
wr_pntr <= #`TCQ 0;
end
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= 0;
next_num_wr_bits = 0;
wr_ptr <= C_WR_DEPTH - 1;
rd_ptr_wrclk <= C_RD_DEPTH - 1;
ideal_wr_ack <= 0;
ideal_wr_count <= 0;
tmp_wr_listsize = 0;
rd_ptr_wrclk_next <= 0;
wr_pntr_rd1 <= 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
ideal_prog_full <= C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= 0;
ideal_prog_empty <= 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
rd_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)
rd_pntr <= #`TCQ 0;
end
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i) begin
num_rd_bits <= 0;
next_num_rd_bits = 0;
rd_ptr <= C_RD_DEPTH -1;
rd_pntr_wr1 <= 0;
wr_ptr_rdclk <= C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= 1'b0;
ideal_rd_count <= 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always gen_fifo_r_as
endmodule // fifo_generator_v13_1_3_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v13_1_3_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input SAFETY_CKT_WR_RST,
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RD_EN_USER,
input USER_EMPTY_FB,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input WR_RST_BUSY,
input RD_RST_BUSY,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output reg EMPTY_FB = 1'b1,
output FULL,
output OVERFLOW,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
//localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
//localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}};
localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}};
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_reg = 1'b0;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
wire srst_rrst_busy;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = C_FULL_FLAGS_RST_VAL;
reg full_i_temp = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
reg valid_both = 0;
reg valid_d2 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
//reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
//reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_dout_both = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_both = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK) begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
assign srst_wrst_busy = srst_i;
assign srst_rrst_busy = srst_i;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_both <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ ram_empty_comb;
end
end // always
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input SAFETY_CKT_RD_RST,
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_sckt = 1'b1;
reg sckt_rrst_q = 1'b0;
reg sckt_rrst_done = 1'b0;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
reg [C_DOUT_WIDTH-1:0] userdata_both;
wire uservalid_both;
wire uservalid_one;
reg user_sbiterr_both = 1'b0;
reg user_dbiterr_both = 1'b0;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
userdata_both = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
user_sbiterr_both = 1'b0;
user_dbiterr_both = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
reg sckt_rd_rst_fwft = 1'b0;
reg fwft_rst_done_i = 1'b0;
wire fwft_rst_done;
assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
always @ (posedge RD_CLK) begin
sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
fwft_rst_done_i <= 1'b0;
else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
fwft_rst_done_i <= #`TCQ 1'b1;
end
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
ram_valid_i <= #`TCQ next_state;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
curr_state <= 1'b0;
end else if (srst_i) begin
curr_state <= #`TCQ 1'b0;
end else begin
curr_state <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_sckt <= #`TCQ 1'b1;
sckt_rrst_q <= #`TCQ 1'b0;
sckt_rrst_done <= #`TCQ 1'b0;
end else begin
sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
sckt_rrst_done <= #`TCQ 1'b1;
end else if (sckt_rrst_done) begin
// rising clock edge
empty_sckt <= #`TCQ 1'b0;
end
end
end //always
// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin
if (fwft_rst_done) begin
if (ram_regout_en) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK) begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end //always
end //if
endgenerate
endmodule //fifo_generator_v13_1_3_bhv_ver_preload0
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: fifo_generator_vlog_beh.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_vlog_beh.v
* |
* +-fifo_generator_v13_1_3_bhv_ver_as
* |
* +-fifo_generator_v13_1_3_bhv_ver_ss
* |
* +-fifo_generator_v13_1_3_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
wire wr_rst_busy_o;
wire wr_rst_busy_ntve;
wire wr_rst_busy_axis;
wire wr_rst_busy_wach;
wire wr_rst_busy_wdch;
wire wr_rst_busy_wrch;
wire wr_rst_busy_rach;
wire wr_rst_busy_rdch;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o;
assign wr_rst_busy = wr_rst_busy_o;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
fifo_generator_v13_1_3_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v13_1_3_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy_o (wr_rst_busy_o),
.wr_rst_busy (wr_rst_busy_i),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
reg [3:0] axi_rst = 4'h0 ;
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
axi_rst <= 4'hf;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
axi_rst <= #`TCQ {axi_rst[2:0],1'b0};
end
end
assign axi_rs_rst = axi_rst[3];//rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //fifo_generator_v13_1_3
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module fifo_generator_v13_1_3_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_INTERFACE_TYPE = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex7", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR,
output wr_rst_busy_o,
output wr_rst_busy,
output rd_rst_busy,
output wr_rst_i_out,
output rd_rst_i_out
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg empty_fb ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
wire empty_p0_out;
always @* rst_delayed <= #`TCQ RST ;
always @* empty_fb <= #`TCQ empty_p0_out ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 0;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
reg rd_rst_asreg_d3 = 0;
reg rd_rst_reg = 0;
wire rd_rst_comb;
reg wr_rst_d0 = 0;
reg wr_rst_d1 = 0;
reg wr_rst_d2 = 0;
reg rd_rst_d0 = 0;
reg rd_rst_d1 = 0;
reg rd_rst_d2 = 0;
reg rd_rst_d3 = 0;
reg wrrst_done = 0;
reg rdrst_done = 0;
reg wr_rst_asreg = 0;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
reg wr_rst_asreg_d3 = 0;
reg rd_rst_wr_d0 = 0;
reg rd_rst_wr_d1 = 0;
reg rd_rst_wr_d2 = 0;
reg wr_rst_reg = 0;
reg rst_active_i = 1'b1;
reg rst_delayed_d1 = 1'b1;
reg rst_delayed_d2 = 1'b1;
wire wr_rst_comb;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 0;
reg srst_asreg = 0;
wire rst_asreg_d1;
wire rst_asreg_d2;
reg srst_asreg_d1 = 0;
reg srst_asreg_d2 = 0;
reg rst_reg = 0;
reg srst_reg = 0;
wire rst_comb;
wire srst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}};
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire fifo_empty_fb;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
wire inject_sbit_err;
wire inject_dbit_err;
wire safety_ckt_wr_rst;
wire safety_ckt_rd_rst;
reg sckt_wr_rst_i_q = 1'b0;
wire w_fab_read_data_valid_i;
wire w_read_data_valid_i;
wire w_ram_valid_i;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
assign wr_rst_i_out = wr_rst_i;
assign rd_rst_i_out = rd_rst_i;
assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];
generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o
wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;
always @ (posedge clk_i)
sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy};
end endgenerate
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1
//Common Clock Behavioral Model
fifo_generator_v13_1_3_bhv_ver_ss
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.CLK (CLK),
.RST (rst_i),
.SRST (srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.USER_EMPTY_FB (empty_fb),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.fab_read_data_valid_i (w_fab_read_data_valid_i),
.read_data_valid_i (w_read_data_valid_i),
.ram_valid_i (w_ram_valid_i),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v13_1_3_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
//wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.fab_read_data_valid_i_o (w_fab_read_data_valid_i),
.read_data_valid_i_o (w_read_data_valid_i),
.ram_valid_i_o (w_ram_valid_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= 1;
ALMOSTEMPTY_P0_OUT_Q <= 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= 0;
end else begin
//if (srst_delayed && (C_HAS_SRST == 1) ) begin
if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed | wr_rst_busy | rd_rst_busy)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate // gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST | wr_rst_busy | rd_rst_busy) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30_both
endgenerate
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
end //block_ic_both
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3_both
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;
localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE :
(C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2;
reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}};
reg [1:0] wrst_cc = {2{1'b0}};
reg [1:0] rrst_cc = {2{1'b0}};
generate
if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt
reg[1:0] rst_d1_safety =1;
reg[1:0] rst_d2_safety =1;
reg[1:0] rst_d3_safety =1;
reg[1:0] rst_d4_safety =1;
reg[1:0] rst_d5_safety =1;
reg[1:0] rst_d6_safety =1;
reg[1:0] rst_d7_safety =1;
always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst
if (rst_2_sync_safety == 1'b1) begin
rst_d1_safety <= 1'b1;
rst_d2_safety <= 1'b1;
rst_d3_safety <= 1'b1;
rst_d4_safety <= 1'b1;
rst_d5_safety <= 1'b1;
rst_d6_safety <= 1'b1;
rst_d7_safety <= 1'b1;
end
else begin
rst_d1_safety <= #`TCQ 1'b0;
rst_d2_safety <= #`TCQ rst_d1_safety;
rst_d3_safety <= #`TCQ rst_d2_safety;
rst_d4_safety <= #`TCQ rst_d3_safety;
rst_d5_safety <= #`TCQ rst_d4_safety;
rst_d6_safety <= #`TCQ rst_d5_safety;
rst_d7_safety <= #`TCQ rst_d6_safety;
end //if
end //prst
always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety
if(rst_d7_safety == 1 && WR_EN == 1) begin
$display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.");
end //if
end //always
end // grst_safety_ckt
endgenerate
// if (C_EN_SAFET_CKT == 1)
// assertion:the reset shud be atleast 3 cycles wide.
generate
reg safety_ckt_wr_rst_i = 1'b0;
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
// end : gnrst_sync
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
reg fifo_wrst_done = 1'b0;
reg fifo_rrst_done = 1'b0;
reg sckt_wrst_i = 1'b0;
reg sckt_wrst_i_q = 1'b0;
reg rd_rst_active = 1'b0;
reg rd_rst_middle = 1'b0;
reg sckt_rd_rst_d1 = 1'b0;
reg [1:0] rst_delayed_ic_w = 2'h0;
wire rst_delayed_ic_w_i;
reg [1:0] rst_delayed_ic_r = 2'h0;
wire rst_delayed_ic_r_i;
wire arst_sync_rst;
wire fifo_rst_done;
wire fifo_rst_active;
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed_ic_w_i;
assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1];
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0;
assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done;
assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1];
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_w <= 2'b11;
else
rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0};
end
assign rst_delayed_ic_w_i = rst_delayed_ic_w[1];
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_r <= 2'b11;
else
rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0};
end
assign rst_delayed_ic_r_i = rst_delayed_ic_r[1];
always @(posedge WR_CLK) begin
sckt_wrst_i_q <= #`TCQ sckt_wrst_i;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q;
if (arst_sync_rst && ~fifo_rst_active)
sckt_wrst_i <= #`TCQ 1'b1;
else if (sckt_wrst_i && fifo_rst_done)
sckt_wrst_i <= #`TCQ 1'b0;
else
sckt_wrst_i <= #`TCQ sckt_wrst_i;
if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1])
fifo_rrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_rrst_done <= #`TCQ 1'b0;
else
fifo_rrst_done <= #`TCQ fifo_rrst_done;
if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1])
fifo_wrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_wrst_done <= #`TCQ 1'b0;
else
fifo_wrst_done <= #`TCQ fifo_wrst_done;
end
always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin
if (rst_delayed_ic_w_i == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg};
wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst};
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i};
end
assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin
if (rst_delayed_ic_r_i == 1'b1) begin
rd_rst_asreg <= 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg};
rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2};
sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst;
if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin
rd_rst_active <= #`TCQ 1'b1;
rd_rst_middle <= #`TCQ 1'b1;
end else if (safety_ckt_rd_rst)
rd_rst_active <= #`TCQ 1'b0;
else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst)
rd_rst_middle <= #`TCQ 1'b0;
end
assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2];
assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1];
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0;
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_ic_rst
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
reg [1:0] rst_delayed_cc = 2'h0;
wire rst_delayed_cc_i;
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed_cc_i;
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
rst_delayed_cc <= 2'b11;
else
rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0};
end
assign rst_delayed_cc_i = rst_delayed_cc[1];
always @(posedge CLK or posedge rst_delayed_cc_i) begin
if (rst_delayed_cc_i == 1'b1) begin
rst_asreg <= 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg};
wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]};
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q;
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i};
end
assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_cc_rst
end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
always @* rst_full_ff_i <= rst_reg;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
// end : g8s_cc_rst
end else begin
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
assign safety_ckt_wr_rst = 1'b0;
assign safety_ckt_rd_rst = 1'b0;
end
endgenerate
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
reg rst_d5 = 1'b0;
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b1;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b1;
end else begin
rst_d1 <= #`TCQ wr_rst_busy;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
always @* rst_full_gen_i <= rst_d3;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1
endmodule //fifo_generator_v13_1_3_conv_ver
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v13_1_3_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input SAFETY_CKT_WR_RST,
input SAFETY_CKT_RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
input fab_read_data_valid_i,
input read_data_valid_i,
input ram_valid_i,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg EMPTY_FB = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
generate
if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin
EMPTY <= 1'b1;
ALMOST_EMPTY <= 1'b1;
rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)
EMPTY_FB <= #`TCQ 1'b1;
else if (empty_int)
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ 1'b0;
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF) begin
FULL <= C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= C_FULL_FLAGS_RST_VAL;
end else begin
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
always @ (posedge WR_CLK or posedge wr_rst_i)
begin
if (wr_rst_i) begin
wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= 0;
stage2_valid <= 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out1;
wire valid_out2;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
reg valid_d2 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_d2 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Safety-ckt logic with embedded reg/fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d1;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end
end
endgenerate
//***************************************************************************
// Safety-ckt logic with embedded reg + fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else begin
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end
endgenerate
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
valid_d1: valid_i;
assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
valid_d2: valid_i;
assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3) begin
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;
// assign diff_rd_wr_1 = diff_rd_wr +2'h2;
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
//if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b0;
//else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b1;
//else
rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
end
end
end
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_d2 <= 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
valid_d2 <= #`TCQ valid_d1;
end
// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
// valid_d2 <= #`TCQ valid_d1;
// end
end
end
endgenerate
//Capture delayed version of dout
/**************************************************************************
*embedded/fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG < 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
endgenerate
/**************************************************************************
*embedded + fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG == 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)
wr_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)
wr_pntr <= #`TCQ 0;
end
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= 0;
next_num_wr_bits = 0;
wr_ptr <= C_WR_DEPTH - 1;
rd_ptr_wrclk <= C_RD_DEPTH - 1;
ideal_wr_ack <= 0;
ideal_wr_count <= 0;
tmp_wr_listsize = 0;
rd_ptr_wrclk_next <= 0;
wr_pntr_rd1 <= 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
ideal_prog_full <= C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= 0;
ideal_prog_empty <= 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
rd_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)
rd_pntr <= #`TCQ 0;
end
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i) begin
num_rd_bits <= 0;
next_num_rd_bits = 0;
rd_ptr <= C_RD_DEPTH -1;
rd_pntr_wr1 <= 0;
wr_ptr_rdclk <= C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= 1'b0;
ideal_rd_count <= 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always gen_fifo_r_as
endmodule // fifo_generator_v13_1_3_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v13_1_3_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input SAFETY_CKT_WR_RST,
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RD_EN_USER,
input USER_EMPTY_FB,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input WR_RST_BUSY,
input RD_RST_BUSY,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output reg EMPTY_FB = 1'b1,
output FULL,
output OVERFLOW,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
//localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
//localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}};
localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}};
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_reg = 1'b0;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
wire srst_rrst_busy;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = C_FULL_FLAGS_RST_VAL;
reg full_i_temp = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
reg valid_both = 0;
reg valid_d2 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
//reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
//reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_dout_both = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_both = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK) begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
assign srst_wrst_busy = srst_i;
assign srst_rrst_busy = srst_i;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_both <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ ram_empty_comb;
end
end // always
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input SAFETY_CKT_RD_RST,
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_sckt = 1'b1;
reg sckt_rrst_q = 1'b0;
reg sckt_rrst_done = 1'b0;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
reg [C_DOUT_WIDTH-1:0] userdata_both;
wire uservalid_both;
wire uservalid_one;
reg user_sbiterr_both = 1'b0;
reg user_dbiterr_both = 1'b0;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
userdata_both = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
user_sbiterr_both = 1'b0;
user_dbiterr_both = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
reg sckt_rd_rst_fwft = 1'b0;
reg fwft_rst_done_i = 1'b0;
wire fwft_rst_done;
assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
always @ (posedge RD_CLK) begin
sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
fwft_rst_done_i <= 1'b0;
else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
fwft_rst_done_i <= #`TCQ 1'b1;
end
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
ram_valid_i <= #`TCQ next_state;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
curr_state <= 1'b0;
end else if (srst_i) begin
curr_state <= #`TCQ 1'b0;
end else begin
curr_state <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_sckt <= #`TCQ 1'b1;
sckt_rrst_q <= #`TCQ 1'b0;
sckt_rrst_done <= #`TCQ 1'b0;
end else begin
sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
sckt_rrst_done <= #`TCQ 1'b1;
end else if (sckt_rrst_done) begin
// rising clock edge
empty_sckt <= #`TCQ 1'b0;
end
end
end //always
// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin
if (fwft_rst_done) begin
if (ram_regout_en) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK) begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end //always
end //if
endgenerate
endmodule //fifo_generator_v13_1_3_bhv_ver_preload0
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: fifo_generator_vlog_beh.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_vlog_beh.v
* |
* +-fifo_generator_v13_1_3_bhv_ver_as
* |
* +-fifo_generator_v13_1_3_bhv_ver_ss
* |
* +-fifo_generator_v13_1_3_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
wire wr_rst_busy_o;
wire wr_rst_busy_ntve;
wire wr_rst_busy_axis;
wire wr_rst_busy_wach;
wire wr_rst_busy_wdch;
wire wr_rst_busy_wrch;
wire wr_rst_busy_rach;
wire wr_rst_busy_rdch;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o;
assign wr_rst_busy = wr_rst_busy_o;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
fifo_generator_v13_1_3_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v13_1_3_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy_o (wr_rst_busy_o),
.wr_rst_busy (wr_rst_busy_i),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
reg [3:0] axi_rst = 4'h0 ;
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
axi_rst <= 4'hf;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
axi_rst <= #`TCQ {axi_rst[2:0],1'b0};
end
end
assign axi_rs_rst = axi_rst[3];//rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //fifo_generator_v13_1_3
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module fifo_generator_v13_1_3_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_INTERFACE_TYPE = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex7", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR,
output wr_rst_busy_o,
output wr_rst_busy,
output rd_rst_busy,
output wr_rst_i_out,
output rd_rst_i_out
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg empty_fb ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
wire empty_p0_out;
always @* rst_delayed <= #`TCQ RST ;
always @* empty_fb <= #`TCQ empty_p0_out ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 0;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
reg rd_rst_asreg_d3 = 0;
reg rd_rst_reg = 0;
wire rd_rst_comb;
reg wr_rst_d0 = 0;
reg wr_rst_d1 = 0;
reg wr_rst_d2 = 0;
reg rd_rst_d0 = 0;
reg rd_rst_d1 = 0;
reg rd_rst_d2 = 0;
reg rd_rst_d3 = 0;
reg wrrst_done = 0;
reg rdrst_done = 0;
reg wr_rst_asreg = 0;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
reg wr_rst_asreg_d3 = 0;
reg rd_rst_wr_d0 = 0;
reg rd_rst_wr_d1 = 0;
reg rd_rst_wr_d2 = 0;
reg wr_rst_reg = 0;
reg rst_active_i = 1'b1;
reg rst_delayed_d1 = 1'b1;
reg rst_delayed_d2 = 1'b1;
wire wr_rst_comb;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 0;
reg srst_asreg = 0;
wire rst_asreg_d1;
wire rst_asreg_d2;
reg srst_asreg_d1 = 0;
reg srst_asreg_d2 = 0;
reg rst_reg = 0;
reg srst_reg = 0;
wire rst_comb;
wire srst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}};
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire fifo_empty_fb;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
wire inject_sbit_err;
wire inject_dbit_err;
wire safety_ckt_wr_rst;
wire safety_ckt_rd_rst;
reg sckt_wr_rst_i_q = 1'b0;
wire w_fab_read_data_valid_i;
wire w_read_data_valid_i;
wire w_ram_valid_i;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
assign wr_rst_i_out = wr_rst_i;
assign rd_rst_i_out = rd_rst_i;
assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];
generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o
wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;
always @ (posedge clk_i)
sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy};
end endgenerate
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1
//Common Clock Behavioral Model
fifo_generator_v13_1_3_bhv_ver_ss
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.CLK (CLK),
.RST (rst_i),
.SRST (srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.USER_EMPTY_FB (empty_fb),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.fab_read_data_valid_i (w_fab_read_data_valid_i),
.read_data_valid_i (w_read_data_valid_i),
.ram_valid_i (w_ram_valid_i),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v13_1_3_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
//wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.fab_read_data_valid_i_o (w_fab_read_data_valid_i),
.read_data_valid_i_o (w_read_data_valid_i),
.ram_valid_i_o (w_ram_valid_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= 1;
ALMOSTEMPTY_P0_OUT_Q <= 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= 0;
end else begin
//if (srst_delayed && (C_HAS_SRST == 1) ) begin
if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed | wr_rst_busy | rd_rst_busy)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate // gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST | wr_rst_busy | rd_rst_busy) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30_both
endgenerate
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
end //block_ic_both
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3_both
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;
localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE :
(C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2;
reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}};
reg [1:0] wrst_cc = {2{1'b0}};
reg [1:0] rrst_cc = {2{1'b0}};
generate
if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt
reg[1:0] rst_d1_safety =1;
reg[1:0] rst_d2_safety =1;
reg[1:0] rst_d3_safety =1;
reg[1:0] rst_d4_safety =1;
reg[1:0] rst_d5_safety =1;
reg[1:0] rst_d6_safety =1;
reg[1:0] rst_d7_safety =1;
always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst
if (rst_2_sync_safety == 1'b1) begin
rst_d1_safety <= 1'b1;
rst_d2_safety <= 1'b1;
rst_d3_safety <= 1'b1;
rst_d4_safety <= 1'b1;
rst_d5_safety <= 1'b1;
rst_d6_safety <= 1'b1;
rst_d7_safety <= 1'b1;
end
else begin
rst_d1_safety <= #`TCQ 1'b0;
rst_d2_safety <= #`TCQ rst_d1_safety;
rst_d3_safety <= #`TCQ rst_d2_safety;
rst_d4_safety <= #`TCQ rst_d3_safety;
rst_d5_safety <= #`TCQ rst_d4_safety;
rst_d6_safety <= #`TCQ rst_d5_safety;
rst_d7_safety <= #`TCQ rst_d6_safety;
end //if
end //prst
always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety
if(rst_d7_safety == 1 && WR_EN == 1) begin
$display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.");
end //if
end //always
end // grst_safety_ckt
endgenerate
// if (C_EN_SAFET_CKT == 1)
// assertion:the reset shud be atleast 3 cycles wide.
generate
reg safety_ckt_wr_rst_i = 1'b0;
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
// end : gnrst_sync
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
reg fifo_wrst_done = 1'b0;
reg fifo_rrst_done = 1'b0;
reg sckt_wrst_i = 1'b0;
reg sckt_wrst_i_q = 1'b0;
reg rd_rst_active = 1'b0;
reg rd_rst_middle = 1'b0;
reg sckt_rd_rst_d1 = 1'b0;
reg [1:0] rst_delayed_ic_w = 2'h0;
wire rst_delayed_ic_w_i;
reg [1:0] rst_delayed_ic_r = 2'h0;
wire rst_delayed_ic_r_i;
wire arst_sync_rst;
wire fifo_rst_done;
wire fifo_rst_active;
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed_ic_w_i;
assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1];
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0;
assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done;
assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1];
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_w <= 2'b11;
else
rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0};
end
assign rst_delayed_ic_w_i = rst_delayed_ic_w[1];
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_r <= 2'b11;
else
rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0};
end
assign rst_delayed_ic_r_i = rst_delayed_ic_r[1];
always @(posedge WR_CLK) begin
sckt_wrst_i_q <= #`TCQ sckt_wrst_i;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q;
if (arst_sync_rst && ~fifo_rst_active)
sckt_wrst_i <= #`TCQ 1'b1;
else if (sckt_wrst_i && fifo_rst_done)
sckt_wrst_i <= #`TCQ 1'b0;
else
sckt_wrst_i <= #`TCQ sckt_wrst_i;
if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1])
fifo_rrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_rrst_done <= #`TCQ 1'b0;
else
fifo_rrst_done <= #`TCQ fifo_rrst_done;
if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1])
fifo_wrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_wrst_done <= #`TCQ 1'b0;
else
fifo_wrst_done <= #`TCQ fifo_wrst_done;
end
always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin
if (rst_delayed_ic_w_i == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg};
wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst};
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i};
end
assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin
if (rst_delayed_ic_r_i == 1'b1) begin
rd_rst_asreg <= 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg};
rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2};
sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst;
if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin
rd_rst_active <= #`TCQ 1'b1;
rd_rst_middle <= #`TCQ 1'b1;
end else if (safety_ckt_rd_rst)
rd_rst_active <= #`TCQ 1'b0;
else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst)
rd_rst_middle <= #`TCQ 1'b0;
end
assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2];
assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1];
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0;
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_ic_rst
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
reg [1:0] rst_delayed_cc = 2'h0;
wire rst_delayed_cc_i;
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed_cc_i;
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
rst_delayed_cc <= 2'b11;
else
rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0};
end
assign rst_delayed_cc_i = rst_delayed_cc[1];
always @(posedge CLK or posedge rst_delayed_cc_i) begin
if (rst_delayed_cc_i == 1'b1) begin
rst_asreg <= 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg};
wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]};
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q;
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i};
end
assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_cc_rst
end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
always @* rst_full_ff_i <= rst_reg;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
// end : g8s_cc_rst
end else begin
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
assign safety_ckt_wr_rst = 1'b0;
assign safety_ckt_rd_rst = 1'b0;
end
endgenerate
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
reg rst_d5 = 1'b0;
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b1;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b1;
end else begin
rst_d1 <= #`TCQ wr_rst_busy;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
always @* rst_full_gen_i <= rst_d3;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1
endmodule //fifo_generator_v13_1_3_conv_ver
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v13_1_3_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input SAFETY_CKT_WR_RST,
input SAFETY_CKT_RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
input fab_read_data_valid_i,
input read_data_valid_i,
input ram_valid_i,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg EMPTY_FB = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
generate
if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin
EMPTY <= 1'b1;
ALMOST_EMPTY <= 1'b1;
rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)
EMPTY_FB <= #`TCQ 1'b1;
else if (empty_int)
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ 1'b0;
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF) begin
FULL <= C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= C_FULL_FLAGS_RST_VAL;
end else begin
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
always @ (posedge WR_CLK or posedge wr_rst_i)
begin
if (wr_rst_i) begin
wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= 0;
stage2_valid <= 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out1;
wire valid_out2;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
reg valid_d2 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_d2 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Safety-ckt logic with embedded reg/fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d1;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end
end
endgenerate
//***************************************************************************
// Safety-ckt logic with embedded reg + fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else begin
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end
endgenerate
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
valid_d1: valid_i;
assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
valid_d2: valid_i;
assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3) begin
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;
// assign diff_rd_wr_1 = diff_rd_wr +2'h2;
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
//if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b0;
//else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b1;
//else
rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
end
end
end
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_d2 <= 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
valid_d2 <= #`TCQ valid_d1;
end
// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
// valid_d2 <= #`TCQ valid_d1;
// end
end
end
endgenerate
//Capture delayed version of dout
/**************************************************************************
*embedded/fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG < 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
endgenerate
/**************************************************************************
*embedded + fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG == 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)
wr_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)
wr_pntr <= #`TCQ 0;
end
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= 0;
next_num_wr_bits = 0;
wr_ptr <= C_WR_DEPTH - 1;
rd_ptr_wrclk <= C_RD_DEPTH - 1;
ideal_wr_ack <= 0;
ideal_wr_count <= 0;
tmp_wr_listsize = 0;
rd_ptr_wrclk_next <= 0;
wr_pntr_rd1 <= 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
ideal_prog_full <= C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= 0;
ideal_prog_empty <= 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
rd_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)
rd_pntr <= #`TCQ 0;
end
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i) begin
num_rd_bits <= 0;
next_num_rd_bits = 0;
rd_ptr <= C_RD_DEPTH -1;
rd_pntr_wr1 <= 0;
wr_ptr_rdclk <= C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= 1'b0;
ideal_rd_count <= 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always gen_fifo_r_as
endmodule // fifo_generator_v13_1_3_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v13_1_3_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input SAFETY_CKT_WR_RST,
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RD_EN_USER,
input USER_EMPTY_FB,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input WR_RST_BUSY,
input RD_RST_BUSY,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output reg EMPTY_FB = 1'b1,
output FULL,
output OVERFLOW,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
//localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
//localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}};
localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}};
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_reg = 1'b0;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
wire srst_rrst_busy;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = C_FULL_FLAGS_RST_VAL;
reg full_i_temp = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
reg valid_both = 0;
reg valid_d2 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
//reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
//reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_dout_both = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_both = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK) begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
assign srst_wrst_busy = srst_i;
assign srst_rrst_busy = srst_i;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_both <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ ram_empty_comb;
end
end // always
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input SAFETY_CKT_RD_RST,
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_sckt = 1'b1;
reg sckt_rrst_q = 1'b0;
reg sckt_rrst_done = 1'b0;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
reg [C_DOUT_WIDTH-1:0] userdata_both;
wire uservalid_both;
wire uservalid_one;
reg user_sbiterr_both = 1'b0;
reg user_dbiterr_both = 1'b0;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
userdata_both = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
user_sbiterr_both = 1'b0;
user_dbiterr_both = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
reg sckt_rd_rst_fwft = 1'b0;
reg fwft_rst_done_i = 1'b0;
wire fwft_rst_done;
assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
always @ (posedge RD_CLK) begin
sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
fwft_rst_done_i <= 1'b0;
else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
fwft_rst_done_i <= #`TCQ 1'b1;
end
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
ram_valid_i <= #`TCQ next_state;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
curr_state <= 1'b0;
end else if (srst_i) begin
curr_state <= #`TCQ 1'b0;
end else begin
curr_state <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_sckt <= #`TCQ 1'b1;
sckt_rrst_q <= #`TCQ 1'b0;
sckt_rrst_done <= #`TCQ 1'b0;
end else begin
sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
sckt_rrst_done <= #`TCQ 1'b1;
end else if (sckt_rrst_done) begin
// rising clock edge
empty_sckt <= #`TCQ 1'b0;
end
end
end //always
// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin
if (fwft_rst_done) begin
if (ram_regout_en) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK) begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end //always
end //if
endgenerate
endmodule //fifo_generator_v13_1_3_bhv_ver_preload0
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: fifo_generator_vlog_beh.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_vlog_beh.v
* |
* +-fifo_generator_v13_1_3_bhv_ver_as
* |
* +-fifo_generator_v13_1_3_bhv_ver_ss
* |
* +-fifo_generator_v13_1_3_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
wire wr_rst_busy_o;
wire wr_rst_busy_ntve;
wire wr_rst_busy_axis;
wire wr_rst_busy_wach;
wire wr_rst_busy_wdch;
wire wr_rst_busy_wrch;
wire wr_rst_busy_rach;
wire wr_rst_busy_rdch;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o;
assign wr_rst_busy = wr_rst_busy_o;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
fifo_generator_v13_1_3_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v13_1_3_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy_o (wr_rst_busy_o),
.wr_rst_busy (wr_rst_busy_i),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
reg [3:0] axi_rst = 4'h0 ;
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
axi_rst <= 4'hf;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
axi_rst <= #`TCQ {axi_rst[2:0],1'b0};
end
end
assign axi_rs_rst = axi_rst[3];//rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //fifo_generator_v13_1_3
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module fifo_generator_v13_1_3_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_INTERFACE_TYPE = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex7", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR,
output wr_rst_busy_o,
output wr_rst_busy,
output rd_rst_busy,
output wr_rst_i_out,
output rd_rst_i_out
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg empty_fb ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
wire empty_p0_out;
always @* rst_delayed <= #`TCQ RST ;
always @* empty_fb <= #`TCQ empty_p0_out ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 0;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
reg rd_rst_asreg_d3 = 0;
reg rd_rst_reg = 0;
wire rd_rst_comb;
reg wr_rst_d0 = 0;
reg wr_rst_d1 = 0;
reg wr_rst_d2 = 0;
reg rd_rst_d0 = 0;
reg rd_rst_d1 = 0;
reg rd_rst_d2 = 0;
reg rd_rst_d3 = 0;
reg wrrst_done = 0;
reg rdrst_done = 0;
reg wr_rst_asreg = 0;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
reg wr_rst_asreg_d3 = 0;
reg rd_rst_wr_d0 = 0;
reg rd_rst_wr_d1 = 0;
reg rd_rst_wr_d2 = 0;
reg wr_rst_reg = 0;
reg rst_active_i = 1'b1;
reg rst_delayed_d1 = 1'b1;
reg rst_delayed_d2 = 1'b1;
wire wr_rst_comb;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 0;
reg srst_asreg = 0;
wire rst_asreg_d1;
wire rst_asreg_d2;
reg srst_asreg_d1 = 0;
reg srst_asreg_d2 = 0;
reg rst_reg = 0;
reg srst_reg = 0;
wire rst_comb;
wire srst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}};
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire fifo_empty_fb;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
wire inject_sbit_err;
wire inject_dbit_err;
wire safety_ckt_wr_rst;
wire safety_ckt_rd_rst;
reg sckt_wr_rst_i_q = 1'b0;
wire w_fab_read_data_valid_i;
wire w_read_data_valid_i;
wire w_ram_valid_i;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
assign wr_rst_i_out = wr_rst_i;
assign rd_rst_i_out = rd_rst_i;
assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];
generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o
wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;
always @ (posedge clk_i)
sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy};
end endgenerate
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1
//Common Clock Behavioral Model
fifo_generator_v13_1_3_bhv_ver_ss
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.CLK (CLK),
.RST (rst_i),
.SRST (srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.USER_EMPTY_FB (empty_fb),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.fab_read_data_valid_i (w_fab_read_data_valid_i),
.read_data_valid_i (w_read_data_valid_i),
.ram_valid_i (w_ram_valid_i),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v13_1_3_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
//wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.fab_read_data_valid_i_o (w_fab_read_data_valid_i),
.read_data_valid_i_o (w_read_data_valid_i),
.ram_valid_i_o (w_ram_valid_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= 1;
ALMOSTEMPTY_P0_OUT_Q <= 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= 0;
end else begin
//if (srst_delayed && (C_HAS_SRST == 1) ) begin
if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed | wr_rst_busy | rd_rst_busy)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate // gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST | wr_rst_busy | rd_rst_busy) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30_both
endgenerate
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
end //block_ic_both
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3_both
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;
localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE :
(C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2;
reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}};
reg [1:0] wrst_cc = {2{1'b0}};
reg [1:0] rrst_cc = {2{1'b0}};
generate
if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt
reg[1:0] rst_d1_safety =1;
reg[1:0] rst_d2_safety =1;
reg[1:0] rst_d3_safety =1;
reg[1:0] rst_d4_safety =1;
reg[1:0] rst_d5_safety =1;
reg[1:0] rst_d6_safety =1;
reg[1:0] rst_d7_safety =1;
always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst
if (rst_2_sync_safety == 1'b1) begin
rst_d1_safety <= 1'b1;
rst_d2_safety <= 1'b1;
rst_d3_safety <= 1'b1;
rst_d4_safety <= 1'b1;
rst_d5_safety <= 1'b1;
rst_d6_safety <= 1'b1;
rst_d7_safety <= 1'b1;
end
else begin
rst_d1_safety <= #`TCQ 1'b0;
rst_d2_safety <= #`TCQ rst_d1_safety;
rst_d3_safety <= #`TCQ rst_d2_safety;
rst_d4_safety <= #`TCQ rst_d3_safety;
rst_d5_safety <= #`TCQ rst_d4_safety;
rst_d6_safety <= #`TCQ rst_d5_safety;
rst_d7_safety <= #`TCQ rst_d6_safety;
end //if
end //prst
always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety
if(rst_d7_safety == 1 && WR_EN == 1) begin
$display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.");
end //if
end //always
end // grst_safety_ckt
endgenerate
// if (C_EN_SAFET_CKT == 1)
// assertion:the reset shud be atleast 3 cycles wide.
generate
reg safety_ckt_wr_rst_i = 1'b0;
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
// end : gnrst_sync
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
reg fifo_wrst_done = 1'b0;
reg fifo_rrst_done = 1'b0;
reg sckt_wrst_i = 1'b0;
reg sckt_wrst_i_q = 1'b0;
reg rd_rst_active = 1'b0;
reg rd_rst_middle = 1'b0;
reg sckt_rd_rst_d1 = 1'b0;
reg [1:0] rst_delayed_ic_w = 2'h0;
wire rst_delayed_ic_w_i;
reg [1:0] rst_delayed_ic_r = 2'h0;
wire rst_delayed_ic_r_i;
wire arst_sync_rst;
wire fifo_rst_done;
wire fifo_rst_active;
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed_ic_w_i;
assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1];
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0;
assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done;
assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1];
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_w <= 2'b11;
else
rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0};
end
assign rst_delayed_ic_w_i = rst_delayed_ic_w[1];
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_r <= 2'b11;
else
rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0};
end
assign rst_delayed_ic_r_i = rst_delayed_ic_r[1];
always @(posedge WR_CLK) begin
sckt_wrst_i_q <= #`TCQ sckt_wrst_i;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q;
if (arst_sync_rst && ~fifo_rst_active)
sckt_wrst_i <= #`TCQ 1'b1;
else if (sckt_wrst_i && fifo_rst_done)
sckt_wrst_i <= #`TCQ 1'b0;
else
sckt_wrst_i <= #`TCQ sckt_wrst_i;
if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1])
fifo_rrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_rrst_done <= #`TCQ 1'b0;
else
fifo_rrst_done <= #`TCQ fifo_rrst_done;
if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1])
fifo_wrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_wrst_done <= #`TCQ 1'b0;
else
fifo_wrst_done <= #`TCQ fifo_wrst_done;
end
always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin
if (rst_delayed_ic_w_i == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg};
wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst};
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i};
end
assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin
if (rst_delayed_ic_r_i == 1'b1) begin
rd_rst_asreg <= 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg};
rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2};
sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst;
if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin
rd_rst_active <= #`TCQ 1'b1;
rd_rst_middle <= #`TCQ 1'b1;
end else if (safety_ckt_rd_rst)
rd_rst_active <= #`TCQ 1'b0;
else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst)
rd_rst_middle <= #`TCQ 1'b0;
end
assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2];
assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1];
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0;
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_ic_rst
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
reg [1:0] rst_delayed_cc = 2'h0;
wire rst_delayed_cc_i;
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed_cc_i;
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
rst_delayed_cc <= 2'b11;
else
rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0};
end
assign rst_delayed_cc_i = rst_delayed_cc[1];
always @(posedge CLK or posedge rst_delayed_cc_i) begin
if (rst_delayed_cc_i == 1'b1) begin
rst_asreg <= 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg};
wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]};
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q;
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i};
end
assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_cc_rst
end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
always @* rst_full_ff_i <= rst_reg;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
// end : g8s_cc_rst
end else begin
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
assign safety_ckt_wr_rst = 1'b0;
assign safety_ckt_rd_rst = 1'b0;
end
endgenerate
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
reg rst_d5 = 1'b0;
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b1;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b1;
end else begin
rst_d1 <= #`TCQ wr_rst_busy;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
always @* rst_full_gen_i <= rst_d3;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1
endmodule //fifo_generator_v13_1_3_conv_ver
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v13_1_3_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input SAFETY_CKT_WR_RST,
input SAFETY_CKT_RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
input fab_read_data_valid_i,
input read_data_valid_i,
input ram_valid_i,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg EMPTY_FB = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
generate
if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin
EMPTY <= 1'b1;
ALMOST_EMPTY <= 1'b1;
rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)
EMPTY_FB <= #`TCQ 1'b1;
else if (empty_int)
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ 1'b0;
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF) begin
FULL <= C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= C_FULL_FLAGS_RST_VAL;
end else begin
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
always @ (posedge WR_CLK or posedge wr_rst_i)
begin
if (wr_rst_i) begin
wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= 0;
stage2_valid <= 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out1;
wire valid_out2;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
reg valid_d2 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_d2 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Safety-ckt logic with embedded reg/fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d1;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end
end
endgenerate
//***************************************************************************
// Safety-ckt logic with embedded reg + fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else begin
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end
endgenerate
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
valid_d1: valid_i;
assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
valid_d2: valid_i;
assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3) begin
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;
// assign diff_rd_wr_1 = diff_rd_wr +2'h2;
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
//if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b0;
//else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b1;
//else
rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
end
end
end
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_d2 <= 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
valid_d2 <= #`TCQ valid_d1;
end
// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
// valid_d2 <= #`TCQ valid_d1;
// end
end
end
endgenerate
//Capture delayed version of dout
/**************************************************************************
*embedded/fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG < 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
endgenerate
/**************************************************************************
*embedded + fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG == 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)
wr_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)
wr_pntr <= #`TCQ 0;
end
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= 0;
next_num_wr_bits = 0;
wr_ptr <= C_WR_DEPTH - 1;
rd_ptr_wrclk <= C_RD_DEPTH - 1;
ideal_wr_ack <= 0;
ideal_wr_count <= 0;
tmp_wr_listsize = 0;
rd_ptr_wrclk_next <= 0;
wr_pntr_rd1 <= 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
ideal_prog_full <= C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= 0;
ideal_prog_empty <= 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
rd_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)
rd_pntr <= #`TCQ 0;
end
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i) begin
num_rd_bits <= 0;
next_num_rd_bits = 0;
rd_ptr <= C_RD_DEPTH -1;
rd_pntr_wr1 <= 0;
wr_ptr_rdclk <= C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= 1'b0;
ideal_rd_count <= 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always gen_fifo_r_as
endmodule // fifo_generator_v13_1_3_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v13_1_3_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input SAFETY_CKT_WR_RST,
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RD_EN_USER,
input USER_EMPTY_FB,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input WR_RST_BUSY,
input RD_RST_BUSY,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output reg EMPTY_FB = 1'b1,
output FULL,
output OVERFLOW,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
//localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
//localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}};
localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}};
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_reg = 1'b0;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
wire srst_rrst_busy;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = C_FULL_FLAGS_RST_VAL;
reg full_i_temp = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
reg valid_both = 0;
reg valid_d2 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
//reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
//reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_dout_both = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_both = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK) begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
assign srst_wrst_busy = srst_i;
assign srst_rrst_busy = srst_i;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_both <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ ram_empty_comb;
end
end // always
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input SAFETY_CKT_RD_RST,
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_sckt = 1'b1;
reg sckt_rrst_q = 1'b0;
reg sckt_rrst_done = 1'b0;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
reg [C_DOUT_WIDTH-1:0] userdata_both;
wire uservalid_both;
wire uservalid_one;
reg user_sbiterr_both = 1'b0;
reg user_dbiterr_both = 1'b0;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
userdata_both = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
user_sbiterr_both = 1'b0;
user_dbiterr_both = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
reg sckt_rd_rst_fwft = 1'b0;
reg fwft_rst_done_i = 1'b0;
wire fwft_rst_done;
assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
always @ (posedge RD_CLK) begin
sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
fwft_rst_done_i <= 1'b0;
else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
fwft_rst_done_i <= #`TCQ 1'b1;
end
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
ram_valid_i <= #`TCQ next_state;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
curr_state <= 1'b0;
end else if (srst_i) begin
curr_state <= #`TCQ 1'b0;
end else begin
curr_state <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_sckt <= #`TCQ 1'b1;
sckt_rrst_q <= #`TCQ 1'b0;
sckt_rrst_done <= #`TCQ 1'b0;
end else begin
sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
sckt_rrst_done <= #`TCQ 1'b1;
end else if (sckt_rrst_done) begin
// rising clock edge
empty_sckt <= #`TCQ 1'b0;
end
end
end //always
// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin
if (fwft_rst_done) begin
if (ram_regout_en) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK) begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end //always
end //if
endgenerate
endmodule //fifo_generator_v13_1_3_bhv_ver_preload0
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: fifo_generator_vlog_beh.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_vlog_beh.v
* |
* +-fifo_generator_v13_1_3_bhv_ver_as
* |
* +-fifo_generator_v13_1_3_bhv_ver_ss
* |
* +-fifo_generator_v13_1_3_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
wire wr_rst_busy_o;
wire wr_rst_busy_ntve;
wire wr_rst_busy_axis;
wire wr_rst_busy_wach;
wire wr_rst_busy_wdch;
wire wr_rst_busy_wrch;
wire wr_rst_busy_rach;
wire wr_rst_busy_rdch;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o;
assign wr_rst_busy = wr_rst_busy_o;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
fifo_generator_v13_1_3_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v13_1_3_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy_o (wr_rst_busy_o),
.wr_rst_busy (wr_rst_busy_i),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
reg [3:0] axi_rst = 4'h0 ;
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
axi_rst <= 4'hf;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
axi_rst <= #`TCQ {axi_rst[2:0],1'b0};
end
end
assign axi_rs_rst = axi_rst[3];//rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //fifo_generator_v13_1_3
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module fifo_generator_v13_1_3_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_INTERFACE_TYPE = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex7", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR,
output wr_rst_busy_o,
output wr_rst_busy,
output rd_rst_busy,
output wr_rst_i_out,
output rd_rst_i_out
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg empty_fb ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
wire empty_p0_out;
always @* rst_delayed <= #`TCQ RST ;
always @* empty_fb <= #`TCQ empty_p0_out ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 0;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
reg rd_rst_asreg_d3 = 0;
reg rd_rst_reg = 0;
wire rd_rst_comb;
reg wr_rst_d0 = 0;
reg wr_rst_d1 = 0;
reg wr_rst_d2 = 0;
reg rd_rst_d0 = 0;
reg rd_rst_d1 = 0;
reg rd_rst_d2 = 0;
reg rd_rst_d3 = 0;
reg wrrst_done = 0;
reg rdrst_done = 0;
reg wr_rst_asreg = 0;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
reg wr_rst_asreg_d3 = 0;
reg rd_rst_wr_d0 = 0;
reg rd_rst_wr_d1 = 0;
reg rd_rst_wr_d2 = 0;
reg wr_rst_reg = 0;
reg rst_active_i = 1'b1;
reg rst_delayed_d1 = 1'b1;
reg rst_delayed_d2 = 1'b1;
wire wr_rst_comb;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 0;
reg srst_asreg = 0;
wire rst_asreg_d1;
wire rst_asreg_d2;
reg srst_asreg_d1 = 0;
reg srst_asreg_d2 = 0;
reg rst_reg = 0;
reg srst_reg = 0;
wire rst_comb;
wire srst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}};
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire fifo_empty_fb;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
wire inject_sbit_err;
wire inject_dbit_err;
wire safety_ckt_wr_rst;
wire safety_ckt_rd_rst;
reg sckt_wr_rst_i_q = 1'b0;
wire w_fab_read_data_valid_i;
wire w_read_data_valid_i;
wire w_ram_valid_i;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
assign wr_rst_i_out = wr_rst_i;
assign rd_rst_i_out = rd_rst_i;
assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];
generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o
wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;
always @ (posedge clk_i)
sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy};
end endgenerate
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1
//Common Clock Behavioral Model
fifo_generator_v13_1_3_bhv_ver_ss
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.CLK (CLK),
.RST (rst_i),
.SRST (srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.USER_EMPTY_FB (empty_fb),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.fab_read_data_valid_i (w_fab_read_data_valid_i),
.read_data_valid_i (w_read_data_valid_i),
.ram_valid_i (w_ram_valid_i),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v13_1_3_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
//wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.fab_read_data_valid_i_o (w_fab_read_data_valid_i),
.read_data_valid_i_o (w_read_data_valid_i),
.ram_valid_i_o (w_ram_valid_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= 1;
ALMOSTEMPTY_P0_OUT_Q <= 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= 0;
end else begin
//if (srst_delayed && (C_HAS_SRST == 1) ) begin
if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed | wr_rst_busy | rd_rst_busy)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate // gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST | wr_rst_busy | rd_rst_busy) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30_both
endgenerate
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
end //block_ic_both
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3_both
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;
localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE :
(C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2;
reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}};
reg [1:0] wrst_cc = {2{1'b0}};
reg [1:0] rrst_cc = {2{1'b0}};
generate
if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt
reg[1:0] rst_d1_safety =1;
reg[1:0] rst_d2_safety =1;
reg[1:0] rst_d3_safety =1;
reg[1:0] rst_d4_safety =1;
reg[1:0] rst_d5_safety =1;
reg[1:0] rst_d6_safety =1;
reg[1:0] rst_d7_safety =1;
always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst
if (rst_2_sync_safety == 1'b1) begin
rst_d1_safety <= 1'b1;
rst_d2_safety <= 1'b1;
rst_d3_safety <= 1'b1;
rst_d4_safety <= 1'b1;
rst_d5_safety <= 1'b1;
rst_d6_safety <= 1'b1;
rst_d7_safety <= 1'b1;
end
else begin
rst_d1_safety <= #`TCQ 1'b0;
rst_d2_safety <= #`TCQ rst_d1_safety;
rst_d3_safety <= #`TCQ rst_d2_safety;
rst_d4_safety <= #`TCQ rst_d3_safety;
rst_d5_safety <= #`TCQ rst_d4_safety;
rst_d6_safety <= #`TCQ rst_d5_safety;
rst_d7_safety <= #`TCQ rst_d6_safety;
end //if
end //prst
always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety
if(rst_d7_safety == 1 && WR_EN == 1) begin
$display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.");
end //if
end //always
end // grst_safety_ckt
endgenerate
// if (C_EN_SAFET_CKT == 1)
// assertion:the reset shud be atleast 3 cycles wide.
generate
reg safety_ckt_wr_rst_i = 1'b0;
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
// end : gnrst_sync
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
reg fifo_wrst_done = 1'b0;
reg fifo_rrst_done = 1'b0;
reg sckt_wrst_i = 1'b0;
reg sckt_wrst_i_q = 1'b0;
reg rd_rst_active = 1'b0;
reg rd_rst_middle = 1'b0;
reg sckt_rd_rst_d1 = 1'b0;
reg [1:0] rst_delayed_ic_w = 2'h0;
wire rst_delayed_ic_w_i;
reg [1:0] rst_delayed_ic_r = 2'h0;
wire rst_delayed_ic_r_i;
wire arst_sync_rst;
wire fifo_rst_done;
wire fifo_rst_active;
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed_ic_w_i;
assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1];
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0;
assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done;
assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1];
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_w <= 2'b11;
else
rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0};
end
assign rst_delayed_ic_w_i = rst_delayed_ic_w[1];
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_r <= 2'b11;
else
rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0};
end
assign rst_delayed_ic_r_i = rst_delayed_ic_r[1];
always @(posedge WR_CLK) begin
sckt_wrst_i_q <= #`TCQ sckt_wrst_i;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q;
if (arst_sync_rst && ~fifo_rst_active)
sckt_wrst_i <= #`TCQ 1'b1;
else if (sckt_wrst_i && fifo_rst_done)
sckt_wrst_i <= #`TCQ 1'b0;
else
sckt_wrst_i <= #`TCQ sckt_wrst_i;
if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1])
fifo_rrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_rrst_done <= #`TCQ 1'b0;
else
fifo_rrst_done <= #`TCQ fifo_rrst_done;
if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1])
fifo_wrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_wrst_done <= #`TCQ 1'b0;
else
fifo_wrst_done <= #`TCQ fifo_wrst_done;
end
always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin
if (rst_delayed_ic_w_i == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg};
wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst};
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i};
end
assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin
if (rst_delayed_ic_r_i == 1'b1) begin
rd_rst_asreg <= 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg};
rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2};
sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst;
if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin
rd_rst_active <= #`TCQ 1'b1;
rd_rst_middle <= #`TCQ 1'b1;
end else if (safety_ckt_rd_rst)
rd_rst_active <= #`TCQ 1'b0;
else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst)
rd_rst_middle <= #`TCQ 1'b0;
end
assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2];
assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1];
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0;
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_ic_rst
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
reg [1:0] rst_delayed_cc = 2'h0;
wire rst_delayed_cc_i;
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed_cc_i;
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
rst_delayed_cc <= 2'b11;
else
rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0};
end
assign rst_delayed_cc_i = rst_delayed_cc[1];
always @(posedge CLK or posedge rst_delayed_cc_i) begin
if (rst_delayed_cc_i == 1'b1) begin
rst_asreg <= 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg};
wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]};
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q;
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i};
end
assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_cc_rst
end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
always @* rst_full_ff_i <= rst_reg;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
// end : g8s_cc_rst
end else begin
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
assign safety_ckt_wr_rst = 1'b0;
assign safety_ckt_rd_rst = 1'b0;
end
endgenerate
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
reg rst_d5 = 1'b0;
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b1;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b1;
end else begin
rst_d1 <= #`TCQ wr_rst_busy;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
always @* rst_full_gen_i <= rst_d3;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1
endmodule //fifo_generator_v13_1_3_conv_ver
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v13_1_3_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input SAFETY_CKT_WR_RST,
input SAFETY_CKT_RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
input fab_read_data_valid_i,
input read_data_valid_i,
input ram_valid_i,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg EMPTY_FB = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
generate
if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin
EMPTY <= 1'b1;
ALMOST_EMPTY <= 1'b1;
rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)
EMPTY_FB <= #`TCQ 1'b1;
else if (empty_int)
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ 1'b0;
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF) begin
FULL <= C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= C_FULL_FLAGS_RST_VAL;
end else begin
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
always @ (posedge WR_CLK or posedge wr_rst_i)
begin
if (wr_rst_i) begin
wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= 0;
stage2_valid <= 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out1;
wire valid_out2;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
reg valid_d2 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_d2 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Safety-ckt logic with embedded reg/fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d1;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end
end
endgenerate
//***************************************************************************
// Safety-ckt logic with embedded reg + fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else begin
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end
endgenerate
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
valid_d1: valid_i;
assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
valid_d2: valid_i;
assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3) begin
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;
// assign diff_rd_wr_1 = diff_rd_wr +2'h2;
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
//if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b0;
//else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b1;
//else
rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
end
end
end
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_d2 <= 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
valid_d2 <= #`TCQ valid_d1;
end
// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
// valid_d2 <= #`TCQ valid_d1;
// end
end
end
endgenerate
//Capture delayed version of dout
/**************************************************************************
*embedded/fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG < 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
endgenerate
/**************************************************************************
*embedded + fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG == 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)
wr_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)
wr_pntr <= #`TCQ 0;
end
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= 0;
next_num_wr_bits = 0;
wr_ptr <= C_WR_DEPTH - 1;
rd_ptr_wrclk <= C_RD_DEPTH - 1;
ideal_wr_ack <= 0;
ideal_wr_count <= 0;
tmp_wr_listsize = 0;
rd_ptr_wrclk_next <= 0;
wr_pntr_rd1 <= 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
ideal_prog_full <= C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= 0;
ideal_prog_empty <= 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
rd_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)
rd_pntr <= #`TCQ 0;
end
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i) begin
num_rd_bits <= 0;
next_num_rd_bits = 0;
rd_ptr <= C_RD_DEPTH -1;
rd_pntr_wr1 <= 0;
wr_ptr_rdclk <= C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= 1'b0;
ideal_rd_count <= 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always gen_fifo_r_as
endmodule // fifo_generator_v13_1_3_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v13_1_3_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input SAFETY_CKT_WR_RST,
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RD_EN_USER,
input USER_EMPTY_FB,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input WR_RST_BUSY,
input RD_RST_BUSY,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output reg EMPTY_FB = 1'b1,
output FULL,
output OVERFLOW,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
//localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
//localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}};
localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}};
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_reg = 1'b0;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
wire srst_rrst_busy;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = C_FULL_FLAGS_RST_VAL;
reg full_i_temp = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
reg valid_both = 0;
reg valid_d2 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
//reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
//reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_dout_both = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_both = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK) begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
assign srst_wrst_busy = srst_i;
assign srst_rrst_busy = srst_i;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_both <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ ram_empty_comb;
end
end // always
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input SAFETY_CKT_RD_RST,
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_sckt = 1'b1;
reg sckt_rrst_q = 1'b0;
reg sckt_rrst_done = 1'b0;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
reg [C_DOUT_WIDTH-1:0] userdata_both;
wire uservalid_both;
wire uservalid_one;
reg user_sbiterr_both = 1'b0;
reg user_dbiterr_both = 1'b0;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
userdata_both = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
user_sbiterr_both = 1'b0;
user_dbiterr_both = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
reg sckt_rd_rst_fwft = 1'b0;
reg fwft_rst_done_i = 1'b0;
wire fwft_rst_done;
assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
always @ (posedge RD_CLK) begin
sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
fwft_rst_done_i <= 1'b0;
else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
fwft_rst_done_i <= #`TCQ 1'b1;
end
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
ram_valid_i <= #`TCQ next_state;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
curr_state <= 1'b0;
end else if (srst_i) begin
curr_state <= #`TCQ 1'b0;
end else begin
curr_state <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_sckt <= #`TCQ 1'b1;
sckt_rrst_q <= #`TCQ 1'b0;
sckt_rrst_done <= #`TCQ 1'b0;
end else begin
sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
sckt_rrst_done <= #`TCQ 1'b1;
end else if (sckt_rrst_done) begin
// rising clock edge
empty_sckt <= #`TCQ 1'b0;
end
end
end //always
// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin
if (fwft_rst_done) begin
if (ram_regout_en) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK) begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end //always
end //if
endgenerate
endmodule //fifo_generator_v13_1_3_bhv_ver_preload0
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
//-----------------------------------------------------------------------------
//-- Divisor de reloj
//-- Señal de periodo igual al indicado
//-- El ancho del pulso positivo es de 1 ciclo de reloj
//--
//-- (c) BQ. September 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`include "divider.vh"
//-- ENTRADAS:
//-- -clk: Senal de reloj del sistema (12 MHZ en la iceStick)
//
//-- SALIDAS:
//-- - clk_out. Señal de salida para lograr la velocidad en baudios indicada
//-- Anchura de 1 periodo de clk. SALIDA NO REGISTRADA
module dividerp1(input wire clk,
output wire clk_out);
//-- Valor por defecto de la velocidad en baudios
parameter M = `T_100ms;
//-- Numero de bits para almacenar el divisor de baudios
localparam N = $clog2(M);
//-- Registro para implementar el contador modulo M
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk)
divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1;
//-- Sacar un pulso de anchura 1 ciclo de reloj si el generador
assign clk_out = (divcounter == 0) ? 1 : 0;
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// DUC block
module duc(input clock,
input reset,
input enable,
input [3:0] rate1,
input [3:0] rate2,
output strobe,
input [31:0] freq,
input [15:0] i_in,
input [15:0] q_in,
output [15:0] i_out,
output [15:0] q_out
);
parameter bw = 16;
parameter zw = 16;
wire [15:0] i_interp_out, q_interp_out;
wire [31:0] phase;
wire strobe1, strobe2;
reg [3:0] strobe_ctr1,strobe_ctr2;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr2 <= #1 4'd0;
else if(strobe2)
strobe_ctr2 <= #1 4'd0;
else
strobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr1 <= #1 4'd0;
else if(strobe1)
strobe_ctr1 <= #1 4'd0;
else if(strobe2)
strobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
assign strobe2 = enable & ( strobe_ctr2 == rate2 );
assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
assign strobe = strobe1;
function [2:0] log_ceil;
input [3:0] val;
log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1;
endfunction
wire [2:0] shift1 = log_ceil(rate1);
wire [2:0] shift2 = log_ceil(rate2);
cordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
cordic(.clock(clock), .reset(reset), .enable(enable),
.xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]),
.xo(i_out), .yo(q_out), .zo() );
cic_interp_2stage #(.bw(bw),.N(4))
interp_i(.clock(clock),.reset(reset),.enable(enable),
.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
.signal_in(i_in),.signal_out(i_interp_out));
cic_interp_2stage #(.bw(bw),.N(4))
interp_q(.clock(clock),.reset(reset),.enable(enable),
.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
.signal_in(q_in),.signal_out(q_interp_out));
phase_acc #(.resolution(32))
nco (.clk(clock),.reset(reset),.enable(enable),
.freq(freq),.phase(phase));
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// DUC block
module duc(input clock,
input reset,
input enable,
input [3:0] rate1,
input [3:0] rate2,
output strobe,
input [31:0] freq,
input [15:0] i_in,
input [15:0] q_in,
output [15:0] i_out,
output [15:0] q_out
);
parameter bw = 16;
parameter zw = 16;
wire [15:0] i_interp_out, q_interp_out;
wire [31:0] phase;
wire strobe1, strobe2;
reg [3:0] strobe_ctr1,strobe_ctr2;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr2 <= #1 4'd0;
else if(strobe2)
strobe_ctr2 <= #1 4'd0;
else
strobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
always @(posedge clock)
if(reset | ~enable)
strobe_ctr1 <= #1 4'd0;
else if(strobe1)
strobe_ctr1 <= #1 4'd0;
else if(strobe2)
strobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
assign strobe2 = enable & ( strobe_ctr2 == rate2 );
assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
assign strobe = strobe1;
function [2:0] log_ceil;
input [3:0] val;
log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1;
endfunction
wire [2:0] shift1 = log_ceil(rate1);
wire [2:0] shift2 = log_ceil(rate2);
cordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
cordic(.clock(clock), .reset(reset), .enable(enable),
.xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]),
.xo(i_out), .yo(q_out), .zo() );
cic_interp_2stage #(.bw(bw),.N(4))
interp_i(.clock(clock),.reset(reset),.enable(enable),
.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
.signal_in(i_in),.signal_out(i_interp_out));
cic_interp_2stage #(.bw(bw),.N(4))
interp_q(.clock(clock),.reset(reset),.enable(enable),
.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
.signal_in(q_in),.signal_out(q_interp_out));
phase_acc #(.resolution(32))
nco (.clk(clock),.reset(reset),.enable(enable),
.freq(freq),.phase(phase));
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Addr Decoder
// Each received address is compared to base and high address pairs for each
// of a set of decode targets.
// The matching target's index (if any) is output combinatorially.
// If the decode is successful (matches any target), the MATCH output is asserted.
// For each target, a set of alternative address ranges may be specified.
// The base and high address pairs are formatted as a pair of 2-dimensional arrays,
// alternative address ranges iterate within each target.
// The alternative range which matches the address is also output as REGION.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// addr_decoder
// comparator_static
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_addr_decoder #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16]
parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS)
parameter integer C_NUM_RANGES = 1, // Number of alternative ranges that
// can match each target [1:16]
parameter integer C_ADDR_WIDTH = 32, // Width of decoder operand and of
// each base and high address [2:64]
parameter integer C_TARGET_ENC = 0, // Enable encoded target output
parameter integer C_TARGET_HOT = 1, // Enable 1-hot target output
parameter integer C_REGION_ENC = 0, // Enable REGION output
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}},
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}},
parameter [C_NUM_TARGETS:0] C_TARGET_QUAL = {C_NUM_TARGETS{1'b1}},
// Indicates whether each target has connectivity.
// Format: C_NUM_TARGETS{Bit1}.
parameter integer C_RESOLUTION = 0,
// Number of low-order ADDR bits that can be ignored when decoding.
parameter integer C_COMPARATOR_THRESHOLD = 6
// Number of decoded ADDR bits above which will implement comparator_static.
)
(
input wire [C_ADDR_WIDTH-1:0] ADDR, // Decoder input operand
output wire [C_NUM_TARGETS-1:0] TARGET_HOT, // Target matching address (1-hot)
output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC, // Target matching address (encoded)
output wire MATCH, // Decode successful
output wire [3:0] REGION // Range within target matching address (encoded)
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
genvar target_cnt;
genvar region_cnt;
/////////////////////////////////////////////////////////////////////////////
// Function to detect addrs is in the addressable range.
// Only compare 4KB page address (ignore low-order 12 bits)
function decode_address;
input [C_ADDR_WIDTH-1:0] base, high, addr;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page;
begin
addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin
decode_address = 1'b0;
end else begin
mask = base_page ^ high_page;
if ( (base_page & ~mask) == (addr_page & ~mask) ) begin
decode_address = 1'b1;
end else begin
decode_address = 1'b0;
end
end
end
endfunction
// Generates a binary coded from onehotone encoded
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
wire [C_NUM_TARGETS-1:0] TARGET_HOT_I; // Target matching address (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT; // For address hit (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG; // For address hit (1-hot).
wire [C_NUM_RANGES-1:0] REGION_HOT; // Reginon matching address (1-hot).
wire [3:0] TARGET_ENC_I; // Internal version of encoded hit.
/////////////////////////////////////////////////////////////////////////////
// Generate detection per region per target.
generate
for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target
for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region
// Detect if this is an address hit (including used region decoding).
if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static
if (C_TARGET_QUAL[target_cnt] &&
((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) ||
(C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range
generic_baseblocks_v2_1_comparator_static #
(
.C_FAMILY("rtl"),
.C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]),
.C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION)
) addr_decode_comparator
(
.CIN(1'b1),
.A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] &
~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])),
.COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt])
);
end else begin : gen_null_range
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0;
end
end else begin : gen_no_comparator_static
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ?
decode_address(
C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
ADDR)
: 1'b0;
end // gen_comparator_static
assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt];
assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS];
end // gen_region
// All regions are non-overlapping
// => Or all the region detections for this target to determine if it is a hit.
assign TARGET_HOT_I[target_cnt] = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES];
end // gen_target
endgenerate
/////////////////////////////////////////////////////////////////////////////
// All regions are non-overlapping
// => Or all the target hit detections if it is a match.
assign MATCH = | TARGET_HOT_I;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
generate
if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT
assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1;
end else begin : NO_TARGET_ONEHOT
assign TARGET_HOT = {C_NUM_TARGETS{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED
assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I);
assign TARGET_ENC = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0];
end else begin : NO_TARGET_ENCODED
assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded region output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED
assign REGION = f_hot2enc(REGION_HOT);
end else begin : NO_REGION_ENCODED
assign REGION = 4'b0;
end
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Addr Decoder
// Each received address is compared to base and high address pairs for each
// of a set of decode targets.
// The matching target's index (if any) is output combinatorially.
// If the decode is successful (matches any target), the MATCH output is asserted.
// For each target, a set of alternative address ranges may be specified.
// The base and high address pairs are formatted as a pair of 2-dimensional arrays,
// alternative address ranges iterate within each target.
// The alternative range which matches the address is also output as REGION.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// addr_decoder
// comparator_static
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_addr_decoder #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16]
parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS)
parameter integer C_NUM_RANGES = 1, // Number of alternative ranges that
// can match each target [1:16]
parameter integer C_ADDR_WIDTH = 32, // Width of decoder operand and of
// each base and high address [2:64]
parameter integer C_TARGET_ENC = 0, // Enable encoded target output
parameter integer C_TARGET_HOT = 1, // Enable 1-hot target output
parameter integer C_REGION_ENC = 0, // Enable REGION output
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}},
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}},
parameter [C_NUM_TARGETS:0] C_TARGET_QUAL = {C_NUM_TARGETS{1'b1}},
// Indicates whether each target has connectivity.
// Format: C_NUM_TARGETS{Bit1}.
parameter integer C_RESOLUTION = 0,
// Number of low-order ADDR bits that can be ignored when decoding.
parameter integer C_COMPARATOR_THRESHOLD = 6
// Number of decoded ADDR bits above which will implement comparator_static.
)
(
input wire [C_ADDR_WIDTH-1:0] ADDR, // Decoder input operand
output wire [C_NUM_TARGETS-1:0] TARGET_HOT, // Target matching address (1-hot)
output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC, // Target matching address (encoded)
output wire MATCH, // Decode successful
output wire [3:0] REGION // Range within target matching address (encoded)
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
genvar target_cnt;
genvar region_cnt;
/////////////////////////////////////////////////////////////////////////////
// Function to detect addrs is in the addressable range.
// Only compare 4KB page address (ignore low-order 12 bits)
function decode_address;
input [C_ADDR_WIDTH-1:0] base, high, addr;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page;
begin
addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin
decode_address = 1'b0;
end else begin
mask = base_page ^ high_page;
if ( (base_page & ~mask) == (addr_page & ~mask) ) begin
decode_address = 1'b1;
end else begin
decode_address = 1'b0;
end
end
end
endfunction
// Generates a binary coded from onehotone encoded
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
wire [C_NUM_TARGETS-1:0] TARGET_HOT_I; // Target matching address (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT; // For address hit (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG; // For address hit (1-hot).
wire [C_NUM_RANGES-1:0] REGION_HOT; // Reginon matching address (1-hot).
wire [3:0] TARGET_ENC_I; // Internal version of encoded hit.
/////////////////////////////////////////////////////////////////////////////
// Generate detection per region per target.
generate
for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target
for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region
// Detect if this is an address hit (including used region decoding).
if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static
if (C_TARGET_QUAL[target_cnt] &&
((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) ||
(C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range
generic_baseblocks_v2_1_comparator_static #
(
.C_FAMILY("rtl"),
.C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]),
.C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION)
) addr_decode_comparator
(
.CIN(1'b1),
.A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] &
~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])),
.COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt])
);
end else begin : gen_null_range
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0;
end
end else begin : gen_no_comparator_static
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ?
decode_address(
C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
ADDR)
: 1'b0;
end // gen_comparator_static
assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt];
assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS];
end // gen_region
// All regions are non-overlapping
// => Or all the region detections for this target to determine if it is a hit.
assign TARGET_HOT_I[target_cnt] = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES];
end // gen_target
endgenerate
/////////////////////////////////////////////////////////////////////////////
// All regions are non-overlapping
// => Or all the target hit detections if it is a match.
assign MATCH = | TARGET_HOT_I;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
generate
if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT
assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1;
end else begin : NO_TARGET_ONEHOT
assign TARGET_HOT = {C_NUM_TARGETS{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED
assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I);
assign TARGET_ENC = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0];
end else begin : NO_TARGET_ENCODED
assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded region output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED
assign REGION = f_hot2enc(REGION_HOT);
end else begin : NO_REGION_ENCODED
assign REGION = 4'b0;
end
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Addr Decoder
// Each received address is compared to base and high address pairs for each
// of a set of decode targets.
// The matching target's index (if any) is output combinatorially.
// If the decode is successful (matches any target), the MATCH output is asserted.
// For each target, a set of alternative address ranges may be specified.
// The base and high address pairs are formatted as a pair of 2-dimensional arrays,
// alternative address ranges iterate within each target.
// The alternative range which matches the address is also output as REGION.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// addr_decoder
// comparator_static
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_addr_decoder #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_TARGETS = 2, // Number of decode targets = [1:16]
parameter integer C_NUM_TARGETS_LOG = 1, // Log2(C_NUM_TARGETS)
parameter integer C_NUM_RANGES = 1, // Number of alternative ranges that
// can match each target [1:16]
parameter integer C_ADDR_WIDTH = 32, // Width of decoder operand and of
// each base and high address [2:64]
parameter integer C_TARGET_ENC = 0, // Enable encoded target output
parameter integer C_TARGET_HOT = 1, // Enable 1-hot target output
parameter integer C_REGION_ENC = 0, // Enable REGION output
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b1}},
parameter [C_NUM_TARGETS*C_NUM_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_TARGETS*C_NUM_RANGES*64{1'b0}},
parameter [C_NUM_TARGETS:0] C_TARGET_QUAL = {C_NUM_TARGETS{1'b1}},
// Indicates whether each target has connectivity.
// Format: C_NUM_TARGETS{Bit1}.
parameter integer C_RESOLUTION = 0,
// Number of low-order ADDR bits that can be ignored when decoding.
parameter integer C_COMPARATOR_THRESHOLD = 6
// Number of decoded ADDR bits above which will implement comparator_static.
)
(
input wire [C_ADDR_WIDTH-1:0] ADDR, // Decoder input operand
output wire [C_NUM_TARGETS-1:0] TARGET_HOT, // Target matching address (1-hot)
output wire [C_NUM_TARGETS_LOG-1:0] TARGET_ENC, // Target matching address (encoded)
output wire MATCH, // Decode successful
output wire [3:0] REGION // Range within target matching address (encoded)
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
genvar target_cnt;
genvar region_cnt;
/////////////////////////////////////////////////////////////////////////////
// Function to detect addrs is in the addressable range.
// Only compare 4KB page address (ignore low-order 12 bits)
function decode_address;
input [C_ADDR_WIDTH-1:0] base, high, addr;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] mask;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] addr_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] base_page;
reg [C_ADDR_WIDTH-C_RESOLUTION-1:0] high_page;
begin
addr_page = addr[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
base_page = base[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
high_page = high[C_RESOLUTION+:C_ADDR_WIDTH-C_RESOLUTION];
if (base[C_ADDR_WIDTH-1] & ~high[C_ADDR_WIDTH-1]) begin
decode_address = 1'b0;
end else begin
mask = base_page ^ high_page;
if ( (base_page & ~mask) == (addr_page & ~mask) ) begin
decode_address = 1'b1;
end else begin
decode_address = 1'b0;
end
end
end
endfunction
// Generates a binary coded from onehotone encoded
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
wire [C_NUM_TARGETS-1:0] TARGET_HOT_I; // Target matching address (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT; // For address hit (1-hot).
wire [C_NUM_TARGETS*C_NUM_RANGES-1:0] ADDRESS_HIT_REG; // For address hit (1-hot).
wire [C_NUM_RANGES-1:0] REGION_HOT; // Reginon matching address (1-hot).
wire [3:0] TARGET_ENC_I; // Internal version of encoded hit.
/////////////////////////////////////////////////////////////////////////////
// Generate detection per region per target.
generate
for (target_cnt = 0; target_cnt < C_NUM_TARGETS; target_cnt = target_cnt + 1) begin : gen_target
for (region_cnt = 0; region_cnt < C_NUM_RANGES; region_cnt = region_cnt + 1) begin : gen_region
// Detect if this is an address hit (including used region decoding).
if ((C_ADDR_WIDTH - C_RESOLUTION) > C_COMPARATOR_THRESHOLD) begin : gen_comparator_static
if (C_TARGET_QUAL[target_cnt] &&
((C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] == 0) ||
(C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH] != 0))) begin : gen_addr_range
generic_baseblocks_v2_1_comparator_static #
(
.C_FAMILY("rtl"),
.C_VALUE(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION]),
.C_DATA_WIDTH(C_ADDR_WIDTH-C_RESOLUTION)
) addr_decode_comparator
(
.CIN(1'b1),
.A(ADDR[C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] &
~(C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION] ^
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64+C_RESOLUTION +: C_ADDR_WIDTH-C_RESOLUTION])),
.COUT(ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt])
);
end else begin : gen_null_range
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = 1'b0;
end
end else begin : gen_no_comparator_static
assign ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt] = C_TARGET_QUAL[target_cnt] ?
decode_address(
C_BASE_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
C_HIGH_ADDR[(target_cnt*C_NUM_RANGES+region_cnt)*64 +: C_ADDR_WIDTH],
ADDR)
: 1'b0;
end // gen_comparator_static
assign ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS+target_cnt] = ADDRESS_HIT[target_cnt*C_NUM_RANGES + region_cnt];
assign REGION_HOT[region_cnt] = | ADDRESS_HIT_REG[region_cnt*C_NUM_TARGETS +: C_NUM_TARGETS];
end // gen_region
// All regions are non-overlapping
// => Or all the region detections for this target to determine if it is a hit.
assign TARGET_HOT_I[target_cnt] = | ADDRESS_HIT[target_cnt*C_NUM_RANGES +: C_NUM_RANGES];
end // gen_target
endgenerate
/////////////////////////////////////////////////////////////////////////////
// All regions are non-overlapping
// => Or all the target hit detections if it is a match.
assign MATCH = | TARGET_HOT_I;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
generate
if (C_TARGET_HOT == 1) begin : USE_TARGET_ONEHOT
assign TARGET_HOT = MATCH ? TARGET_HOT_I : 1;
end else begin : NO_TARGET_ONEHOT
assign TARGET_HOT = {C_NUM_TARGETS{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_TARGET_ENCODED
assign TARGET_ENC_I = f_hot2enc(TARGET_HOT_I);
assign TARGET_ENC = TARGET_ENC_I[C_NUM_TARGETS_LOG-1:0];
end else begin : NO_TARGET_ENCODED
assign TARGET_ENC = {C_NUM_TARGETS_LOG{1'b0}};
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded region output signal.
generate
if (C_TARGET_ENC == 1) begin : USE_REGION_ENCODED
assign REGION = f_hot2enc(REGION_HOT);
end else begin : NO_REGION_ENCODED
assign REGION = 4'b0;
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:15:08 08/27/2015
// Design Name:
// Module Name: Tenth_Phase
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Tenth_Phase
//Module Parameters
/***SINGLE PRECISION***/
// W = 32
// EW = 8
// SW = 23
/***DOUBLE PRECISION***/
// W = 64
// EW = 11
// SW = 52
# (parameter W = 32, parameter EW = 8, parameter SW = 23)
// # (parameter W = 64, parameter EW = 11, parameter SW = 52)
(
//INPUTS
input wire clk, //Clock Signal
input wire rst, //Reset Signal
input wire load_i,
input wire sel_a_i, //Overflow/add/subt result's mux's selector
input wire sel_b_i, //underflow/add/subt result's mux's selector
input wire sign_i, //Sign of the largest Operand
input wire [EW-1:0] exp_ieee_i, //Final Exponent
input wire [SW-1:0] sgf_ieee_i,//Final Significand
//OUTPUTS
output wire [W-1:0] final_result_ieee_o //Final Result
);
//Wire Connection signals
wire [SW-1:0] Sgf_S_mux;
wire [EW-1:0] Exp_S_mux;
wire Sign_S_mux;
wire [W-1:0] final_result_reg;
wire overunder;
wire [EW-1:0] exp_mux_D1;
wire [SW-1:0] sgf_mux_D1;
//////////////////////////////////////////////////////////
assign overunder = sel_a_i | sel_b_i;
Mux_3x1 #(.W(1)) Sign_Mux (
.ctrl({sel_a_i,sel_b_i}),
.D0(sign_i),
.D1(1'b1),
.D2(1'b0),
.S(Sign_S_mux)
);
Multiplexer_AC #(.W(EW)) Exp_Mux (
.ctrl(overunder),
.D0(exp_ieee_i),
.D1(exp_mux_D1),
.S(Exp_S_mux)
);
Multiplexer_AC #(.W(SW)) Sgf_Mux (
.ctrl(overunder),
.D0(sgf_ieee_i),
.D1(sgf_mux_D1),
.S(Sgf_S_mux)
);
/////////////////////////////////////////////////////////
generate
if(W == 32) begin
assign exp_mux_D1 =8'hff;
assign sgf_mux_D1 =23'd0;
end
else begin
assign exp_mux_D1 =11'hfff;
assign sgf_mux_D1 =52'd0;
end
endgenerate
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
RegisterAdd #(.W(W)) Final_Result_IEEE (
.clk(clk),
.rst(rst),
.load(load_i),
.D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}),
.Q(final_result_ieee_o)
);
endmodule
|
//IEEE Floating Point Adder (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [31:0] a, b, z;
reg [26:0] a_m, b_m;
reg [23:0] z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [27:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[22 : 0], 3'd0};
b_m <= {b[22 : 0], 3'd0};
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
z[31] <= a_s & b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= b_s;
z[30:23] <= b_e[7:0] + 127;
z[22:0] <= b_m[26:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s;
z[30:23] <= a_e[7:0] + 127;
z[22:0] <= a_m[26:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[26] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[26] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= a_m + b_m;
z_s <= a_s;
end else begin
if (a_m >= b_m) begin
sum <= a_m - b_m;
z_s <= a_s;
end else begin
sum <= b_m - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[27]) begin
z_m <= sum[27:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[26:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Divider (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
//
module divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [50:0] quotient, divisor, dividend, remainder;
reg [5:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf and b is inf return NaN
end else if ((a_e == 128) && (b_e == 128)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is inf return zero
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is zero return inf
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 27;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[50];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 49) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[26:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0 && $signed(z_e) > -126) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Multiplier (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
input [31:0] input_b;
input input_b_stb;
output input_b_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [31:0] a, b, z;
reg [23:0] a_m, b_m, z_m;
reg [9:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [49:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[22 : 0];
b_m <= b[22 : 0];
a_e <= a[30 : 23] - 127;
b_e <= b[30 : 23] - 127;
a_s <= a[31];
b_s <= b[31];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -127) && (b_m == 0)) begin
z[31] <= 1;
z[30:23] <= 255;
z[22] <= 1;
z[21:0] <= 0;
state <= put_z;
end
//if b is inf return inf
end else if (b_e == 128) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 255;
z[22:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -127) && (a_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
//if b is zero return zero
end else if (($signed(b_e) == -127) && (b_m == 0)) begin
z[31] <= a_s ^ b_s;
z[30:23] <= 0;
z[22:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -127) begin
a_e <= -126;
end else begin
a_m[23] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -127) begin
b_e <= -126;
end else begin
b_m[23] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[23]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[23]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[49:26];
guard <= product[25];
round_bit <= product[24];
sticky <= (product[23:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[23] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -126) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e[7:0] + 127;
z[31] <= z_s;
if ($signed(z_e) == -126 && z_m[23] == 0) begin
z[30 : 23] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 127) begin
z[22 : 0] <= 0;
z[30 : 23] <= 255;
z[31] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Divider (Double Precision)
//Copyright (C) Jonathan P Dawson 2014
//2014-01-11
//
module double_divider(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
divide_0 = 4'd6,
divide_1 = 4'd7,
divide_2 = 4'd8,
divide_3 = 4'd9,
normalise_1 = 4'd10,
normalise_2 = 4'd11,
round = 4'd12,
pack = 4'd13,
put_z = 4'd14;
reg [63:0] a, b, z;
reg [52:0] a_m, b_m, z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [108:0] quotient, divisor, dividend, remainder;
reg [6:0] count;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[51 : 0];
b_m <= b[51 : 0];
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf and b is inf return NaN
end else if ((a_e == 1024) && (b_e == 1024)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is inf return zero
end else if (b_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is zero return inf
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[52] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[52] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[52]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[52]) begin
state <= divide_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
divide_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e - b_e;
quotient <= 0;
remainder <= 0;
count <= 0;
dividend <= a_m << 56;
divisor <= b_m;
state <= divide_1;
end
divide_1:
begin
quotient <= quotient << 1;
remainder <= remainder << 1;
remainder[0] <= dividend[108];
dividend <= dividend << 1;
state <= divide_2;
end
divide_2:
begin
if (remainder >= divisor) begin
quotient[0] <= 1;
remainder <= remainder - divisor;
end
if (count == 107) begin
state <= divide_3;
end else begin
count <= count + 1;
state <= divide_1;
end
end
divide_3:
begin
z_m <= quotient[55:3];
guard <= quotient[2];
round_bit <= quotient[1];
sticky <= quotient[0] | (remainder != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0 && $signed(z_e) > -1022) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[10:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Multiplier (Double Precision)
//Copyright (C) Jonathan P Dawson 2014
//2014-01-10
module double_multiplier(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
normalise_a = 4'd4,
normalise_b = 4'd5,
multiply_0 = 4'd6,
multiply_1 = 4'd7,
normalise_1 = 4'd8,
normalise_2 = 4'd9,
round = 4'd10,
pack = 4'd11,
put_z = 4'd12;
reg [63:0] a, b, z;
reg [52:0] a_m, b_m, z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [107:0] product;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= a[51 : 0];
b_m <= b[51 : 0];
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is zero return NaN
if ($signed(b_e == -1023) && (b_m == 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
end
//if b is inf return inf
end else if (b_e == 1024) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if a is zero return zero
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
//if b is zero return zero
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s ^ b_s;
z[62:52] <= 0;
z[51:0] <= 0;
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[52] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[52] <= 1;
end
state <= normalise_a;
end
end
normalise_a:
begin
if (a_m[52]) begin
state <= normalise_b;
end else begin
a_m <= a_m << 1;
a_e <= a_e - 1;
end
end
normalise_b:
begin
if (b_m[52]) begin
state <= multiply_0;
end else begin
b_m <= b_m << 1;
b_e <= b_e - 1;
end
end
multiply_0:
begin
z_s <= a_s ^ b_s;
z_e <= a_e + b_e + 1;
product <= a_m * b_m * 4;
state <= multiply_1;
end
multiply_1:
begin
z_m <= product[107:55];
guard <= product[54];
round_bit <= product[53];
sticky <= (product[52:0] != 0);
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[11:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point Adder (Double Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module double_adder(
input_a,
input_b,
input_a_stb,
input_b_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack,
input_b_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
input [63:0] input_b;
input input_b_stb;
output input_b_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [3:0] state;
parameter get_a = 4'd0,
get_b = 4'd1,
unpack = 4'd2,
special_cases = 4'd3,
align = 4'd4,
add_0 = 4'd5,
add_1 = 4'd6,
normalise_1 = 4'd7,
normalise_2 = 4'd8,
round = 4'd9,
pack = 4'd10,
put_z = 4'd11;
reg [63:0] a, b, z;
reg [55:0] a_m, b_m;
reg [52:0] z_m;
reg [12:0] a_e, b_e, z_e;
reg a_s, b_s, z_s;
reg guard, round_bit, sticky;
reg [56:0] sum;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= get_b;
end
end
get_b:
begin
s_input_b_ack <= 1;
if (s_input_b_ack && input_b_stb) begin
b <= input_b;
s_input_b_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m <= {a[51 : 0], 3'd0};
b_m <= {b[51 : 0], 3'd0};
a_e <= a[62 : 52] - 1023;
b_e <= b[62 : 52] - 1023;
a_s <= a[63];
b_s <= b[63];
state <= special_cases;
end
special_cases:
begin
//if a is NaN or b is NaN return NaN
if ((a_e == 1024 && a_m != 0) || (b_e == 1024 && b_m != 0)) begin
z[63] <= 1;
z[62:52] <= 2047;
z[51] <= 1;
z[50:0] <= 0;
state <= put_z;
//if a is inf return inf
end else if (a_e == 1024) begin
z[63] <= a_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if b is inf return inf
end else if (b_e == 1024) begin
z[63] <= b_s;
z[62:52] <= 2047;
z[51:0] <= 0;
state <= put_z;
//if a is zero return b
end else if ((($signed(a_e) == -1023) && (a_m == 0)) && (($signed(b_e) == -1023) && (b_m == 0))) begin
z[63] <= a_s & b_s;
z[62:52] <= b_e[10:0] + 1023;
z[51:0] <= b_m[55:3];
state <= put_z;
//if a is zero return b
end else if (($signed(a_e) == -1023) && (a_m == 0)) begin
z[63] <= b_s;
z[62:52] <= b_e[10:0] + 1023;
z[51:0] <= b_m[55:3];
state <= put_z;
//if b is zero return a
end else if (($signed(b_e) == -1023) && (b_m == 0)) begin
z[63] <= a_s;
z[62:52] <= a_e[10:0] + 1023;
z[51:0] <= a_m[55:3];
state <= put_z;
end else begin
//Denormalised Number
if ($signed(a_e) == -1023) begin
a_e <= -1022;
end else begin
a_m[55] <= 1;
end
//Denormalised Number
if ($signed(b_e) == -1023) begin
b_e <= -1022;
end else begin
b_m[55] <= 1;
end
state <= align;
end
end
align:
begin
if ($signed(a_e) > $signed(b_e)) begin
b_e <= b_e + 1;
b_m <= b_m >> 1;
b_m[0] <= b_m[0] | b_m[1];
end else if ($signed(a_e) < $signed(b_e)) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
a_m[0] <= a_m[0] | a_m[1];
end else begin
state <= add_0;
end
end
add_0:
begin
z_e <= a_e;
if (a_s == b_s) begin
sum <= {1'd0, a_m} + b_m;
z_s <= a_s;
end else begin
if (a_m > b_m) begin
sum <= {1'd0, a_m} - b_m;
z_s <= a_s;
end else begin
sum <= {1'd0, b_m} - a_m;
z_s <= b_s;
end
end
state <= add_1;
end
add_1:
begin
if (sum[56]) begin
z_m <= sum[56:4];
guard <= sum[3];
round_bit <= sum[2];
sticky <= sum[1] | sum[0];
z_e <= z_e + 1;
end else begin
z_m <= sum[55:3];
guard <= sum[2];
round_bit <= sum[1];
sticky <= sum[0];
end
state <= normalise_1;
end
normalise_1:
begin
if (z_m[52] == 0 && $signed(z_e) > -1022) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= guard;
guard <= round_bit;
round_bit <= 0;
end else begin
state <= normalise_2;
end
end
normalise_2:
begin
if ($signed(z_e) < -1022) begin
z_e <= z_e + 1;
z_m <= z_m >> 1;
guard <= z_m[0];
round_bit <= guard;
sticky <= sticky | round_bit;
end else begin
state <= round;
end
end
round:
begin
if (guard && (round_bit | sticky | z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'h1fffffffffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e[10:0] + 1023;
z[63] <= z_s;
if ($signed(z_e) == -1022 && z_m[52] == 0) begin
z[62 : 52] <= 0;
end
//if overflow occurs, return inf
if ($signed(z_e) > 1023) begin
z[51 : 0] <= 0;
z[62 : 52] <= 2047;
z[63] <= z_s;
end
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_input_b_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign input_b_ack = s_input_b_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//Integer to IEEE Floating Point Converter (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module int_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [2:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
convert_1 = 3'd2,
convert_2 = 3'd3,
round = 3'd4,
pack = 3'd5,
put_z = 3'd6;
reg [31:0] a, z, value;
reg [23:0] z_m;
reg [7:0] z_r;
reg [7:0] z_e;
reg z_s;
reg guard, round_bit, sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
if ( a == 0 ) begin
z_s <= 0;
z_m <= 0;
z_e <= -127;
state <= pack;
end else begin
value <= a[31] ? -a : a;
z_s <= a[31];
state <= convert_1;
end
end
convert_1:
begin
z_e <= 31;
z_m <= value[31:8];
z_r <= value[7:0];
state <= convert_2;
end
convert_2:
begin
if (!z_m[23]) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= z_r[7];
z_r <= z_r << 1;
end else begin
guard <= z_r[7];
round_bit <= z_r[6];
sticky <= z_r[5:0] != 0;
state <= round;
end
end
round:
begin
if (guard && (round_bit || sticky || z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 24'hffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[22 : 0] <= z_m[22:0];
z[30 : 23] <= z_e + 127;
z[31] <= z_s;
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point to Integer Converter (Single Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module float_to_int(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg [2:0] state;
parameter get_a = 3'd0,
special_cases = 3'd1,
unpack = 3'd2,
convert = 3'd3,
put_z = 3'd4;
reg [31:0] a_m, a, z;
reg [8:0] a_e;
reg a_s;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m[31:8] <= {1'b1, a[22 : 0]};
a_m[7:0] <= 0;
a_e <= a[30 : 23] - 127;
a_s <= a[31];
state <= special_cases;
end
special_cases:
begin
if ($signed(a_e) == -127) begin
z <= 0;
state <= put_z;
end else if ($signed(a_e) > 31) begin
z <= 32'h80000000;
state <= put_z;
end else begin
state <= convert;
end
end
convert:
begin
if ($signed(a_e) < 31 && a_m) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
end else begin
if (a_m[31]) begin
z <= 32'h80000000;
end else begin
z <= a_s ? -a_m : a_m;
end
state <= put_z;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//Integer to IEEE Floating Point Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module long_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [2:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
convert_1 = 3'd2,
convert_2 = 3'd3,
round = 3'd4,
pack = 3'd5,
put_z = 3'd6;
reg [63:0] a, z, value;
reg [52:0] z_m;
reg [10:0] z_r;
reg [10:0] z_e;
reg z_s;
reg guard, round_bit, sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
if ( a == 0 ) begin
z_s <= 0;
z_m <= 0;
z_e <= -1023;
state <= pack;
end else begin
value <= a[63] ? -a : a;
z_s <= a[63];
state <= convert_1;
end
end
convert_1:
begin
z_e <= 63;
z_m <= value[63:11];
z_r <= value[10:0];
state <= convert_2;
end
convert_2:
begin
if (!z_m[52]) begin
z_e <= z_e - 1;
z_m <= z_m << 1;
z_m[0] <= z_r[10];
z_r <= z_r << 1;
end else begin
guard <= z_r[10];
round_bit <= z_r[9];
sticky <= z_r[8:0] != 0;
state <= round;
end
end
round:
begin
if (guard && (round_bit || sticky || z_m[0])) begin
z_m <= z_m + 1;
if (z_m == 53'h1fffffffffffff) begin
z_e <=z_e + 1;
end
end
state <= pack;
end
pack:
begin
z[51 : 0] <= z_m[51:0];
z[62 : 52] <= z_e + 1023;
z[63] <= z_s;
state <= put_z;
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point to Integer Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2014
//2014-01-11
module double_to_long(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg [2:0] state;
parameter get_a = 3'd0,
special_cases = 3'd1,
unpack = 3'd2,
convert = 3'd3,
put_z = 3'd4;
reg [63:0] a_m, a, z;
reg [11:0] a_e;
reg a_s;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
a_m[63:11] <= {1'b1, a[51 : 0]};
a_m[10:0] <= 0;
a_e <= a[62 : 52] - 1023;
a_s <= a[63];
state <= special_cases;
end
special_cases:
begin
if ($signed(a_e) == -1023) begin
//zero
z <= 0;
state <= put_z;
end else if ($signed(a_e) == 1024 && a[51:0] != 0) begin
//nan
z <= 64'h8000000000000000;
state <= put_z;
end else if ($signed(a_e) > 63) begin
//too big
if (a_s) begin
z <= 64'h8000000000000000;
end else begin
z <= 64'h0000000000000000;
end
state <= put_z;
end else begin
state <= convert;
end
end
convert:
begin
if ($signed(a_e) < 63 && a_m) begin
a_e <= a_e + 1;
a_m <= a_m >> 1;
end else begin
if (a_m[63] && a_s) begin
z <= 64'h8000000000000000;
end else begin
z <= a_s ? -a_m : a_m;
end
state <= put_z;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//Integer to IEEE Floating Point Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2013
//2013-12-12
module float_to_double(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [31:0] input_a;
input input_a_stb;
output input_a_ack;
output [63:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [63:0] s_output_z;
reg s_input_a_ack;
reg s_input_b_ack;
reg [1:0] state;
parameter get_a = 3'd0,
convert_0 = 3'd1,
normalise_0 = 3'd2,
put_z = 3'd3;
reg [63:0] z;
reg [10:0] z_e;
reg [52:0] z_m;
reg [31:0] a;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= convert_0;
end
end
convert_0:
begin
z[63] <= a[31];
z[62:52] <= (a[30:23] - 127) + 1023;
z[51:0] <= {a[22:0], 29'd0};
if (a[30:23] == 255) begin
z[62:52] <= 2047;
end
state <= put_z;
if (a[30:23] == 0) begin
if (a[23:0]) begin
state <= normalise_0;
z_e <= 897;
z_m <= {1'd0, a[22:0], 29'd0};
end
z[62:52] <= 0;
end
end
normalise_0:
begin
if (z_m[52]) begin
z[62:52] <= z_e;
z[51:0] <= z_m[51:0];
state <= put_z;
end else begin
z_m <= {z_m[51:0], 1'd0};
z_e <= z_e - 1;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
//IEEE Floating Point to Integer Converter (Double Precision)
//Copyright (C) Jonathan P Dawson 2014
//2014-01-11
module double_to_float(
input_a,
input_a_stb,
output_z_ack,
clk,
rst,
output_z,
output_z_stb,
input_a_ack);
input clk;
input rst;
input [63:0] input_a;
input input_a_stb;
output input_a_ack;
output [31:0] output_z;
output output_z_stb;
input output_z_ack;
reg s_output_z_stb;
reg [31:0] s_output_z;
reg s_input_a_ack;
reg [1:0] state;
parameter get_a = 3'd0,
unpack = 3'd1,
denormalise = 3'd2,
put_z = 3'd3;
reg [63:0] a;
reg [31:0] z;
reg [10:0] z_e;
reg [23:0] z_m;
reg guard;
reg round;
reg sticky;
always @(posedge clk)
begin
case(state)
get_a:
begin
s_input_a_ack <= 1;
if (s_input_a_ack && input_a_stb) begin
a <= input_a;
s_input_a_ack <= 0;
state <= unpack;
end
end
unpack:
begin
z[31] <= a[63];
state <= put_z;
if (a[62:52] == 0) begin
z[30:23] <= 0;
z[22:0] <= 0;
end else if (a[62:52] < 897) begin
z[30:23] <= 0;
z_m <= {1'd1, a[51:29]};
z_e <= a[62:52];
guard <= a[28];
round <= a[27];
sticky <= a[26:0] != 0;
state <= denormalise;
end else if (a[62:52] == 2047) begin
z[30:23] <= 255;
z[22:0] <= 0;
if (a[51:0]) begin
z[22] <= 1;
end
end else if (a[62:52] > 1150) begin
z[30:23] <= 255;
z[22:0] <= 0;
end else begin
z[30:23] <= (a[62:52] - 1023) + 127;
if (a[28] && (a[27] || a[26:0])) begin
z[22:0] <= a[51:29] + 1;
end else begin
z[22:0] <= a[51:29];
end
end
end
denormalise:
begin
if (z_e == 897 || (z_m == 0 && guard == 0)) begin
state <= put_z;
z[22:0] <= z_m;
if (guard && (round || sticky)) begin
z[22:0] <= z_m + 1;
end
end else begin
z_e <= z_e + 1;
z_m <= {1'd0, z_m[23:1]};
guard <= z_m[0];
round <= guard;
sticky <= sticky | round;
end
end
put_z:
begin
s_output_z_stb <= 1;
s_output_z <= z;
if (s_output_z_stb && output_z_ack) begin
s_output_z_stb <= 0;
state <= get_a;
end
end
endcase
if (rst == 1) begin
state <= get_a;
s_input_a_ack <= 0;
s_output_z_stb <= 0;
end
end
assign input_a_ack = s_input_a_ack;
assign output_z_stb = s_output_z_stb;
assign output_z = s_output_z;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// sign_extender.v
// Created: 5.16.2012
// Modified: 5.16.2012
//
// Generic sign extension module
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sign_extender
#(
parameter
INPUT_WIDTH = 8,
OUTPUT_WIDTH = 16
)
(
input [INPUT_WIDTH-1:0] original,
output reg [OUTPUT_WIDTH-1:0] sign_extended_original
);
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;
generate
genvar i;
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
sign_extended_original = {sign_extend,original};
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// sign_extender.v
// Created: 5.16.2012
// Modified: 5.16.2012
//
// Generic sign extension module
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sign_extender
#(
parameter
INPUT_WIDTH = 8,
OUTPUT_WIDTH = 16
)
(
input [INPUT_WIDTH-1:0] original,
output reg [OUTPUT_WIDTH-1:0] sign_extended_original
);
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;
generate
genvar i;
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
sign_extended_original = {sign_extend,original};
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// sign_extender.v
// Created: 5.16.2012
// Modified: 5.16.2012
//
// Generic sign extension module
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sign_extender
#(
parameter
INPUT_WIDTH = 8,
OUTPUT_WIDTH = 16
)
(
input [INPUT_WIDTH-1:0] original,
output reg [OUTPUT_WIDTH-1:0] sign_extended_original
);
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;
generate
genvar i;
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
sign_extended_original = {sign_extend,original};
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// sign_extender.v
// Created: 5.16.2012
// Modified: 5.16.2012
//
// Generic sign extension module
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sign_extender
#(
parameter
INPUT_WIDTH = 8,
OUTPUT_WIDTH = 16
)
(
input [INPUT_WIDTH-1:0] original,
output reg [OUTPUT_WIDTH-1:0] sign_extended_original
);
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;
generate
genvar i;
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
sign_extended_original = {sign_extend,original};
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// sign_extender.v
// Created: 5.16.2012
// Modified: 5.16.2012
//
// Generic sign extension module
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sign_extender
#(
parameter
INPUT_WIDTH = 8,
OUTPUT_WIDTH = 16
)
(
input [INPUT_WIDTH-1:0] original,
output reg [OUTPUT_WIDTH-1:0] sign_extended_original
);
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;
generate
genvar i;
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
sign_extended_original = {sign_extend,original};
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// sign_extender.v
// Created: 5.16.2012
// Modified: 5.16.2012
//
// Generic sign extension module
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sign_extender
#(
parameter
INPUT_WIDTH = 8,
OUTPUT_WIDTH = 16
)
(
input [INPUT_WIDTH-1:0] original,
output reg [OUTPUT_WIDTH-1:0] sign_extended_original
);
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;
generate
genvar i;
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
sign_extended_original = {sign_extend,original};
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// sign_extender.v
// Created: 5.16.2012
// Modified: 5.16.2012
//
// Generic sign extension module
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sign_extender
#(
parameter
INPUT_WIDTH = 8,
OUTPUT_WIDTH = 16
)
(
input [INPUT_WIDTH-1:0] original,
output reg [OUTPUT_WIDTH-1:0] sign_extended_original
);
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;
generate
genvar i;
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
sign_extended_original = {sign_extend,original};
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// sign_extender.v
// Created: 5.16.2012
// Modified: 5.16.2012
//
// Generic sign extension module
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sign_extender
#(
parameter
INPUT_WIDTH = 8,
OUTPUT_WIDTH = 16
)
(
input [INPUT_WIDTH-1:0] original,
output reg [OUTPUT_WIDTH-1:0] sign_extended_original
);
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;
generate
genvar i;
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
sign_extended_original = {sign_extend,original};
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// sign_extender.v
// Created: 5.16.2012
// Modified: 5.16.2012
//
// Generic sign extension module
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sign_extender
#(
parameter
INPUT_WIDTH = 8,
OUTPUT_WIDTH = 16
)
(
input [INPUT_WIDTH-1:0] original,
output reg [OUTPUT_WIDTH-1:0] sign_extended_original
);
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;
generate
genvar i;
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
sign_extended_original = {sign_extend,original};
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// sign_extender.v
// Created: 5.16.2012
// Modified: 5.16.2012
//
// Generic sign extension module
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sign_extender
#(
parameter
INPUT_WIDTH = 8,
OUTPUT_WIDTH = 16
)
(
input [INPUT_WIDTH-1:0] original,
output reg [OUTPUT_WIDTH-1:0] sign_extended_original
);
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;
generate
genvar i;
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
sign_extended_original = {sign_extend,original};
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// sign_extender.v
// Created: 5.16.2012
// Modified: 5.16.2012
//
// Generic sign extension module
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sign_extender
#(
parameter
INPUT_WIDTH = 8,
OUTPUT_WIDTH = 16
)
(
input [INPUT_WIDTH-1:0] original,
output reg [OUTPUT_WIDTH-1:0] sign_extended_original
);
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;
generate
genvar i;
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
sign_extended_original = {sign_extend,original};
end
endmodule
|
`include "lo_read.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_32
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_32
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:46 12/20/2010
// Design Name:
// Module Name: clk_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3B_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NAND3B_PP_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3B_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSTP_BLACKBOX_V
`define SKY130_FD_SC_MS__DFSTP_BLACKBOX_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfstp (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSTP_BLACKBOX_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:58:22 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21,
n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35,
n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49,
n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63,
n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77,
n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91,
n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104,
n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115,
n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126,
n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137,
n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148,
n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159,
n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170,
n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181,
n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192,
n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203,
n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214,
n215, n216, n217, n218, n219, n220, n221, n222, n223, n224, n225,
n226, n227, n228, n229, n230, n231, n232, n233, n234, n235, n236,
n237, n238, n239, n240, n241, n242, n243, n244, n245, n246, n247,
n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, n258,
n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, n269,
n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280,
n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291,
n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302,
n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313,
n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324,
n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335,
n336, n337, n338, n339, n340, n341, n342, n343, n344, n345, n346,
n347, n348, n349, n350, n351, n352, n353, n354, n355, n356, n357,
n358;
XNOR2X1TS U42 ( .A(n227), .B(n226), .Y(res[29]) );
NAND2X1TS U43 ( .A(n59), .B(n237), .Y(n238) );
NAND2X1TS U44 ( .A(n233), .B(n232), .Y(n234) );
NAND2XLTS U45 ( .A(n58), .B(n296), .Y(n298) );
NAND2X1TS U46 ( .A(n64), .B(n210), .Y(n207) );
NAND2X1TS U47 ( .A(n225), .B(n224), .Y(n226) );
NAND2X1TS U48 ( .A(n241), .B(n240), .Y(n242) );
NAND2XLTS U49 ( .A(n61), .B(n282), .Y(n283) );
NAND2XLTS U50 ( .A(n286), .B(n285), .Y(n287) );
NAND2XLTS U51 ( .A(n269), .B(n268), .Y(n270) );
NAND2XLTS U52 ( .A(n278), .B(n277), .Y(n279) );
NAND2X1TS U53 ( .A(n258), .B(n257), .Y(n259) );
NAND2X1TS U54 ( .A(n265), .B(n264), .Y(n266) );
NAND2XLTS U55 ( .A(n251), .B(n250), .Y(n252) );
NAND2X6TS U56 ( .A(n222), .B(n11), .Y(n56) );
OAI21X1TS U57 ( .A0(n9), .A1(n310), .B0(n311), .Y(n309) );
OAI21X1TS U58 ( .A0(n288), .A1(n275), .B0(n274), .Y(n280) );
OA21XLTS U59 ( .A0(n314), .A1(n111), .B0(n44), .Y(n9) );
INVX4TS U60 ( .A(n244), .Y(n271) );
INVX2TS U61 ( .A(n290), .Y(n297) );
NAND2X2TS U62 ( .A(n219), .B(in1[31]), .Y(n221) );
CLKBUFX2TS U63 ( .A(n289), .Y(n290) );
CLKMX2X2TS U64 ( .A(in2[31]), .B(n218), .S0(n217), .Y(n219) );
NOR2X1TS U65 ( .A(n215), .B(in2[30]), .Y(n216) );
NOR2X4TS U66 ( .A(n230), .B(n231), .Y(n198) );
NAND2X1TS U67 ( .A(n178), .B(in1[25]), .Y(n250) );
NAND2X2TS U68 ( .A(n176), .B(in1[23]), .Y(n264) );
NAND2X2TS U69 ( .A(n177), .B(in1[24]), .Y(n257) );
CLKMX2X2TS U70 ( .A(in2[29]), .B(n202), .S0(n201), .Y(n203) );
NAND2X2TS U71 ( .A(n194), .B(in1[27]), .Y(n237) );
OR2X4TS U72 ( .A(n154), .B(in1[20]), .Y(n61) );
NAND2BX2TS U73 ( .AN(in2[29]), .B(n204), .Y(n215) );
XNOR2X1TS U74 ( .A(n200), .B(in2[24]), .Y(n165) );
INVX2TS U75 ( .A(in2[23]), .Y(n168) );
OR2X1TS U76 ( .A(n190), .B(in2[27]), .Y(n199) );
NOR2X2TS U77 ( .A(n171), .B(n170), .Y(n172) );
NOR2X2TS U78 ( .A(n200), .B(n190), .Y(n188) );
XNOR2X1TS U79 ( .A(n131), .B(in2[17]), .Y(n132) );
NAND2X1TS U80 ( .A(n187), .B(n186), .Y(n190) );
NAND2X1TS U81 ( .A(n143), .B(in2[19]), .Y(n144) );
XNOR2X1TS U82 ( .A(n141), .B(in2[18]), .Y(n133) );
XOR2X2TS U83 ( .A(n171), .B(n149), .Y(n148) );
INVX2TS U84 ( .A(in2[26]), .Y(n186) );
NOR2X2TS U85 ( .A(in2[25]), .B(in2[24]), .Y(n187) );
NAND2X6TS U86 ( .A(n161), .B(n160), .Y(n200) );
INVX12TS U87 ( .A(n18), .Y(n160) );
OR2X6TS U88 ( .A(n107), .B(in1[11]), .Y(n62) );
INVX2TS U89 ( .A(n316), .Y(n109) );
INVX2TS U90 ( .A(n110), .Y(n317) );
NOR2X4TS U91 ( .A(n320), .B(n110), .Y(n45) );
NAND2X2TS U92 ( .A(n91), .B(in1[9]), .Y(n330) );
NOR2X6TS U93 ( .A(n117), .B(in1[14]), .Y(n305) );
NAND2X6TS U94 ( .A(n107), .B(in1[11]), .Y(n320) );
NAND2X2TS U95 ( .A(n108), .B(in1[12]), .Y(n316) );
OR2X2TS U96 ( .A(in2[21]), .B(in2[20]), .Y(n170) );
NAND2X4TS U97 ( .A(n33), .B(n32), .Y(n60) );
AND2X2TS U98 ( .A(n119), .B(n124), .Y(n12) );
NOR2X1TS U99 ( .A(in2[19]), .B(in2[18]), .Y(n146) );
XNOR2X2TS U100 ( .A(n104), .B(in2[10]), .Y(n87) );
NOR2X2TS U101 ( .A(in2[17]), .B(in2[16]), .Y(n147) );
CLKINVX6TS U102 ( .A(n77), .Y(n33) );
BUFX12TS U103 ( .A(n217), .Y(n201) );
INVX2TS U104 ( .A(in2[14]), .Y(n119) );
NOR2X2TS U105 ( .A(n95), .B(in2[8]), .Y(n88) );
INVX4TS U106 ( .A(n46), .Y(n70) );
NAND2X2TS U107 ( .A(n10), .B(n113), .Y(n114) );
NOR2X4TS U108 ( .A(n104), .B(in2[10]), .Y(n105) );
NAND2X4TS U109 ( .A(n46), .B(n31), .Y(n30) );
INVX6TS U110 ( .A(n143), .Y(n217) );
AO22X2TS U111 ( .A0(add_sub), .A1(n69), .B0(n67), .B1(in2[5]), .Y(n68) );
NAND3X2TS U112 ( .A(n37), .B(n72), .C(n348), .Y(n65) );
INVX4TS U113 ( .A(add_sub), .Y(n83) );
INVX4TS U114 ( .A(in2[8]), .Y(n86) );
NAND2X4TS U115 ( .A(n41), .B(n69), .Y(n79) );
INVX4TS U116 ( .A(n118), .Y(n28) );
CLKINVX3TS U117 ( .A(in2[9]), .Y(n90) );
NOR2X4TS U118 ( .A(n28), .B(n111), .Y(n27) );
MXI2X2TS U119 ( .A(n127), .B(n126), .S0(n201), .Y(n128) );
MXI2X2TS U120 ( .A(n152), .B(n151), .S0(n143), .Y(n157) );
INVX2TS U121 ( .A(n240), .Y(n196) );
NAND2X2TS U122 ( .A(n154), .B(in1[20]), .Y(n282) );
NAND2X1TS U123 ( .A(n197), .B(in1[28]), .Y(n232) );
INVX4TS U124 ( .A(add_sub), .Y(n143) );
OAI21XLTS U125 ( .A0(n333), .A1(n329), .B0(n330), .Y(n328) );
NAND2X1TS U126 ( .A(n293), .B(n292), .Y(n294) );
NOR2X4TS U127 ( .A(n25), .B(n24), .Y(n23) );
NAND2X4TS U128 ( .A(n317), .B(n62), .Y(n111) );
MX2X2TS U129 ( .A(in2[15]), .B(n122), .S0(add_sub), .Y(n123) );
XNOR2X2TS U130 ( .A(n65), .B(in2[6]), .Y(n66) );
NOR4X2TS U131 ( .A(n159), .B(n170), .C(in2[23]), .D(in2[22]), .Y(n161) );
NOR2X4TS U132 ( .A(n197), .B(in1[28]), .Y(n231) );
NAND2X1TS U133 ( .A(n63), .B(n299), .Y(n300) );
NOR2X4TS U134 ( .A(n141), .B(in2[18]), .Y(n142) );
NOR3X4TS U135 ( .A(n200), .B(in2[28]), .C(n199), .Y(n204) );
NOR2X2TS U136 ( .A(n200), .B(n199), .Y(n191) );
NAND2X1TS U137 ( .A(n307), .B(n306), .Y(n308) );
NAND2X1TS U138 ( .A(n317), .B(n316), .Y(n318) );
NAND2X1TS U139 ( .A(n16), .B(n303), .Y(n304) );
NAND2X6TS U140 ( .A(n19), .B(n12), .Y(n18) );
NOR2X4TS U141 ( .A(n108), .B(in1[12]), .Y(n110) );
INVX6TS U142 ( .A(n125), .Y(n19) );
INVX2TS U143 ( .A(in1[6]), .Y(n31) );
INVX2TS U144 ( .A(in1[7]), .Y(n32) );
INVX4TS U145 ( .A(n236), .Y(n241) );
OR2X4TS U146 ( .A(n219), .B(in1[31]), .Y(n11) );
INVX2TS U147 ( .A(n263), .Y(n265) );
INVX2TS U148 ( .A(n249), .Y(n251) );
NAND2X4TS U149 ( .A(n193), .B(in1[26]), .Y(n240) );
OR2X4TS U150 ( .A(n206), .B(in1[30]), .Y(n64) );
NOR2X4TS U151 ( .A(n157), .B(in1[21]), .Y(n276) );
NAND2X4TS U152 ( .A(n153), .B(in1[19]), .Y(n285) );
INVX2TS U153 ( .A(n292), .Y(n137) );
NOR2X4TS U154 ( .A(n178), .B(in1[25]), .Y(n249) );
NAND2X4TS U155 ( .A(n135), .B(in1[17]), .Y(n296) );
XNOR2X1TS U156 ( .A(n216), .B(in2[31]), .Y(n218) );
XOR2X2TS U157 ( .A(n150), .B(in2[21]), .Y(n152) );
OR2X4TS U158 ( .A(n128), .B(in1[16]), .Y(n63) );
XOR2X2TS U159 ( .A(n163), .B(n162), .Y(n164) );
INVX2TS U160 ( .A(n305), .Y(n307) );
NAND2X4TS U161 ( .A(n116), .B(in1[13]), .Y(n311) );
NAND2X4TS U162 ( .A(n123), .B(in1[15]), .Y(n303) );
NAND2X4TS U163 ( .A(n92), .B(in1[10]), .Y(n325) );
NAND2X4TS U164 ( .A(n353), .B(n69), .Y(n47) );
NOR2X4TS U165 ( .A(in2[13]), .B(in2[12]), .Y(n120) );
XOR2X1TS U166 ( .A(n295), .B(n294), .Y(res[18]) );
INVX4TS U167 ( .A(n198), .Y(n8) );
NAND2X4TS U168 ( .A(n241), .B(n59), .Y(n230) );
NAND2X2TS U169 ( .A(n11), .B(n221), .Y(n220) );
AOI21X2TS U170 ( .A0(n64), .A1(n212), .B0(n211), .Y(n213) );
XOR2X1TS U171 ( .A(n302), .B(n304), .Y(res[15]) );
NAND2X4TS U172 ( .A(n64), .B(n225), .Y(n214) );
INVX2TS U173 ( .A(n237), .Y(n195) );
OAI21X2TS U174 ( .A0(n249), .A1(n257), .B0(n250), .Y(n179) );
NOR2X4TS U175 ( .A(n249), .B(n256), .Y(n180) );
NAND2X4TS U176 ( .A(n58), .B(n293), .Y(n140) );
XOR2X1TS U177 ( .A(n319), .B(n318), .Y(res[12]) );
NAND2X2TS U178 ( .A(n206), .B(in1[30]), .Y(n210) );
NAND2X4TS U179 ( .A(n203), .B(in1[29]), .Y(n224) );
NAND2X4TS U180 ( .A(n175), .B(in1[22]), .Y(n268) );
INVX2TS U181 ( .A(n256), .Y(n258) );
NAND2X2TS U182 ( .A(n157), .B(in1[21]), .Y(n277) );
XOR2X1TS U183 ( .A(n9), .B(n313), .Y(res[13]) );
MX2X2TS U184 ( .A(in2[30]), .B(n205), .S0(n217), .Y(n206) );
NOR2X4TS U185 ( .A(n203), .B(in1[29]), .Y(n209) );
OR2X6TS U186 ( .A(n135), .B(in1[17]), .Y(n58) );
OR2X6TS U187 ( .A(n194), .B(in1[27]), .Y(n59) );
MX2X2TS U188 ( .A(in2[27]), .B(n189), .S0(n217), .Y(n194) );
XNOR2X2TS U189 ( .A(n184), .B(in2[26]), .Y(n185) );
MX2X2TS U190 ( .A(in2[25]), .B(n164), .S0(n201), .Y(n178) );
XOR2X1TS U191 ( .A(n333), .B(n332), .Y(res[9]) );
XNOR2X2TS U192 ( .A(n188), .B(in2[27]), .Y(n189) );
INVX2TS U193 ( .A(n200), .Y(n183) );
NOR2X2TS U194 ( .A(n130), .B(in2[16]), .Y(n131) );
INVX4TS U195 ( .A(n339), .Y(n78) );
NAND2X6TS U196 ( .A(n29), .B(n342), .Y(n340) );
NOR2X4TS U197 ( .A(n91), .B(in1[9]), .Y(n329) );
NAND2X6TS U198 ( .A(n343), .B(n30), .Y(n29) );
NAND3X6TS U199 ( .A(n68), .B(n48), .C(n47), .Y(n46) );
OAI21XLTS U200 ( .A0(n355), .A1(n83), .B0(n354), .Y(res[5]) );
MXI2X4TS U201 ( .A(n66), .B(n71), .S0(n83), .Y(n343) );
OAI21XLTS U202 ( .A0(n358), .A1(n83), .B0(n357), .Y(res[4]) );
OAI21XLTS U203 ( .A0(n350), .A1(n83), .B0(n349), .Y(res[2]) );
OAI21XLTS U204 ( .A0(n347), .A1(n83), .B0(n346), .Y(res[3]) );
AND2X4TS U205 ( .A(n100), .B(n99), .Y(n101) );
OAI21XLTS U206 ( .A0(n352), .A1(n143), .B0(n351), .Y(res[1]) );
NAND2X2TS U207 ( .A(n147), .B(n146), .Y(n159) );
AND2X4TS U208 ( .A(n98), .B(n97), .Y(n99) );
NAND2X4TS U209 ( .A(n86), .B(n90), .Y(n96) );
OR2X1TS U210 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
INVX8TS U211 ( .A(n356), .Y(n82) );
AND2X6TS U212 ( .A(n60), .B(n340), .Y(n13) );
NOR2X8TS U213 ( .A(n85), .B(in1[8]), .Y(n334) );
NOR2X6TS U214 ( .A(n263), .B(n261), .Y(n255) );
INVX6TS U215 ( .A(n79), .Y(n37) );
INVX6TS U216 ( .A(n273), .Y(n288) );
NOR2X4TS U217 ( .A(n324), .B(n329), .Y(n94) );
NOR2X4TS U218 ( .A(n153), .B(in1[19]), .Y(n281) );
XNOR2X4TS U219 ( .A(n142), .B(in2[19]), .Y(n145) );
NOR2X4TS U220 ( .A(n356), .B(in2[4]), .Y(n353) );
AOI21X2TS U221 ( .A0(n356), .A1(n15), .B0(n49), .Y(n48) );
MXI2X4TS U222 ( .A(n134), .B(n133), .S0(n201), .Y(n136) );
NOR2X8TS U223 ( .A(n50), .B(n57), .Y(n223) );
MXI2X4TS U224 ( .A(n86), .B(n84), .S0(n217), .Y(n85) );
NOR2X4TS U225 ( .A(n200), .B(in2[24]), .Y(n163) );
INVX16TS U226 ( .A(in2[5]), .Y(n69) );
NAND2BX4TS U227 ( .AN(n159), .B(n160), .Y(n171) );
NOR2X4TS U228 ( .A(n175), .B(in1[22]), .Y(n261) );
MXI2X4TS U229 ( .A(n90), .B(n89), .S0(n201), .Y(n91) );
XOR2X4TS U230 ( .A(n88), .B(in2[9]), .Y(n89) );
CLKINVX12TS U231 ( .A(n95), .Y(n102) );
NOR2X4TS U232 ( .A(n171), .B(in2[20]), .Y(n150) );
NAND2X4TS U233 ( .A(n160), .B(n147), .Y(n141) );
NOR2X2TS U234 ( .A(n275), .B(n276), .Y(n158) );
OAI21X2TS U235 ( .A0(n274), .A1(n276), .B0(n277), .Y(n36) );
NAND3X4TS U236 ( .A(n72), .B(n14), .C(n71), .Y(n73) );
INVX2TS U237 ( .A(in2[6]), .Y(n71) );
XOR2X1TS U238 ( .A(n86), .B(n95), .Y(n84) );
MXI2X4TS U239 ( .A(n97), .B(n87), .S0(n201), .Y(n92) );
MX2X4TS U240 ( .A(in2[17]), .B(n132), .S0(add_sub), .Y(n135) );
NAND2X4TS U241 ( .A(n85), .B(in1[8]), .Y(n335) );
INVX2TS U242 ( .A(n323), .Y(n333) );
INVX2TS U243 ( .A(n314), .Y(n322) );
NAND2X4TS U244 ( .A(n128), .B(in1[16]), .Y(n299) );
NOR2X4TS U245 ( .A(n176), .B(in1[23]), .Y(n263) );
NOR2X4TS U246 ( .A(n177), .B(in1[24]), .Y(n256) );
NOR2X4TS U247 ( .A(n193), .B(in1[26]), .Y(n236) );
INVX2TS U248 ( .A(n209), .Y(n225) );
NAND2X4TS U249 ( .A(n198), .B(n54), .Y(n51) );
INVX2TS U250 ( .A(n96), .Y(n100) );
INVX2TS U251 ( .A(in2[15]), .Y(n124) );
CLKINVX6TS U252 ( .A(in2[4]), .Y(n41) );
CLKAND2X2TS U253 ( .A(in2[5]), .B(add_sub), .Y(n15) );
INVX2TS U254 ( .A(in1[5]), .Y(n49) );
NAND2X1TS U255 ( .A(in2[4]), .B(add_sub), .Y(n67) );
INVX2TS U256 ( .A(in2[10]), .Y(n97) );
NAND2X2TS U257 ( .A(n180), .B(n255), .Y(n182) );
NAND2X4TS U258 ( .A(n34), .B(n76), .Y(n77) );
NAND2X1TS U259 ( .A(n83), .B(in2[7]), .Y(n76) );
NAND2X4TS U260 ( .A(n75), .B(n74), .Y(n34) );
MXI2X4TS U261 ( .A(n119), .B(n112), .S0(n201), .Y(n117) );
INVX4TS U262 ( .A(n44), .Y(n43) );
NOR2X2TS U263 ( .A(n305), .B(n311), .Y(n25) );
INVX2TS U264 ( .A(n306), .Y(n24) );
NOR2X4TS U265 ( .A(n136), .B(in1[18]), .Y(n138) );
INVX2TS U266 ( .A(n299), .Y(n129) );
INVX2TS U267 ( .A(n182), .Y(n54) );
INVX2TS U268 ( .A(n224), .Y(n212) );
INVX2TS U269 ( .A(n210), .Y(n211) );
NOR2X2TS U270 ( .A(n214), .B(n8), .Y(n55) );
INVX2TS U271 ( .A(n57), .Y(n20) );
NAND2X2TS U272 ( .A(n77), .B(in1[7]), .Y(n339) );
NAND2X2TS U273 ( .A(n117), .B(in1[14]), .Y(n306) );
NAND2X2TS U274 ( .A(n136), .B(in1[18]), .Y(n292) );
INVX2TS U275 ( .A(n138), .Y(n293) );
INVX2TS U276 ( .A(n281), .Y(n286) );
INVX2TS U277 ( .A(n282), .Y(n155) );
INVX2TS U278 ( .A(n285), .Y(n156) );
NAND2X2TS U279 ( .A(n286), .B(n61), .Y(n275) );
CLKBUFX2TS U280 ( .A(n272), .Y(n273) );
INVX2TS U281 ( .A(n261), .Y(n269) );
INVX2TS U282 ( .A(n268), .Y(n262) );
OAI21X1TS U283 ( .A0(n246), .A1(n256), .B0(n257), .Y(n247) );
NOR2X1TS U284 ( .A(n245), .B(n256), .Y(n248) );
INVX2TS U285 ( .A(n255), .Y(n245) );
NOR2XLTS U286 ( .A(n38), .B(in2[2]), .Y(n345) );
NAND2X1TS U287 ( .A(n30), .B(n342), .Y(n344) );
XNOR2X1TS U288 ( .A(n341), .B(n340), .Y(res[7]) );
NAND2X1TS U289 ( .A(n60), .B(n339), .Y(n341) );
NAND2X1TS U290 ( .A(n336), .B(n335), .Y(n337) );
INVX2TS U291 ( .A(n334), .Y(n336) );
NAND2X1TS U292 ( .A(n331), .B(n330), .Y(n332) );
INVX2TS U293 ( .A(n329), .Y(n331) );
NAND2X1TS U294 ( .A(n326), .B(n325), .Y(n327) );
INVX2TS U295 ( .A(n324), .Y(n326) );
NAND2X1TS U296 ( .A(n62), .B(n320), .Y(n321) );
AOI21X1TS U297 ( .A0(n322), .A1(n62), .B0(n315), .Y(n319) );
INVX2TS U298 ( .A(n320), .Y(n315) );
NAND2X1TS U299 ( .A(n312), .B(n311), .Y(n313) );
INVX2TS U300 ( .A(n310), .Y(n312) );
AOI21X1TS U301 ( .A0(n58), .A1(n297), .B0(n291), .Y(n295) );
INVX2TS U302 ( .A(n296), .Y(n291) );
XOR2XLTS U303 ( .A(n288), .B(n287), .Y(res[19]) );
XNOR2X1TS U304 ( .A(n284), .B(n283), .Y(res[20]) );
OAI21X1TS U305 ( .A0(n288), .A1(n281), .B0(n285), .Y(n284) );
XNOR2X1TS U306 ( .A(n280), .B(n279), .Y(res[21]) );
INVX2TS U307 ( .A(n276), .Y(n278) );
XNOR2X1TS U308 ( .A(n271), .B(n270), .Y(res[22]) );
XOR2X1TS U309 ( .A(n243), .B(n242), .Y(res[26]) );
INVX2TS U310 ( .A(n231), .Y(n233) );
NAND2X8TS U311 ( .A(n40), .B(n39), .Y(n38) );
OR2X4TS U312 ( .A(n95), .B(n96), .Y(n104) );
OR2X8TS U313 ( .A(n244), .B(n182), .Y(n35) );
AND2X4TS U314 ( .A(n37), .B(n348), .Y(n14) );
INVX12TS U315 ( .A(n38), .Y(n348) );
OAI21X4TS U316 ( .A0(n223), .A1(n209), .B0(n224), .Y(n208) );
AND2X8TS U317 ( .A(n102), .B(n101), .Y(n10) );
INVX2TS U318 ( .A(n22), .Y(n302) );
INVX2TS U319 ( .A(n42), .Y(n314) );
OR2X4TS U320 ( .A(n123), .B(in1[15]), .Y(n16) );
NAND3X8TS U321 ( .A(n17), .B(n23), .C(n26), .Y(n22) );
NAND2X8TS U322 ( .A(n27), .B(n42), .Y(n17) );
MX2X4TS U323 ( .A(in2[13]), .B(n115), .S0(add_sub), .Y(n116) );
OA21X4TS U324 ( .A0(n20), .A1(n214), .B0(n213), .Y(n52) );
NAND2X8TS U325 ( .A(n21), .B(n303), .Y(n301) );
NAND2X8TS U326 ( .A(n16), .B(n22), .Y(n21) );
NAND2X4TS U327 ( .A(n43), .B(n118), .Y(n26) );
NOR2X8TS U328 ( .A(n78), .B(n13), .Y(n338) );
NAND2X8TS U329 ( .A(n35), .B(n181), .Y(n228) );
AOI21X4TS U330 ( .A0(n272), .A1(n158), .B0(n36), .Y(n244) );
OAI21X4TS U331 ( .A0(n289), .A1(n140), .B0(n139), .Y(n272) );
INVX16TS U332 ( .A(in2[1]), .Y(n39) );
INVX16TS U333 ( .A(in2[0]), .Y(n40) );
NAND2X4TS U334 ( .A(n56), .B(n221), .Y(res[32]) );
NOR2X4TS U335 ( .A(in2[7]), .B(in2[6]), .Y(n80) );
MX2X4TS U336 ( .A(in2[11]), .B(n106), .S0(n201), .Y(n107) );
XOR2X4TS U337 ( .A(n172), .B(in2[22]), .Y(n173) );
XNOR2X4TS U338 ( .A(n167), .B(n168), .Y(n169) );
MXI2X4TS U339 ( .A(n166), .B(n165), .S0(n217), .Y(n177) );
AO21X4TS U340 ( .A0(n323), .A1(n94), .B0(n93), .Y(n42) );
NOR2X8TS U341 ( .A(n45), .B(n109), .Y(n44) );
NAND2X8TS U342 ( .A(n348), .B(n72), .Y(n356) );
NOR2X8TS U343 ( .A(in2[3]), .B(in2[2]), .Y(n72) );
OAI22X4TS U344 ( .A0(n51), .A1(n244), .B0(n181), .B1(n8), .Y(n50) );
NAND2X8TS U345 ( .A(n53), .B(n52), .Y(n222) );
NAND2X8TS U346 ( .A(n228), .B(n55), .Y(n53) );
OAI21X4TS U347 ( .A0(n229), .A1(n231), .B0(n232), .Y(n57) );
XOR2X1TS U348 ( .A(n253), .B(n252), .Y(res[25]) );
XOR2X1TS U349 ( .A(n267), .B(n266), .Y(res[23]) );
XOR2X1TS U350 ( .A(n260), .B(n259), .Y(res[24]) );
XNOR2X1TS U351 ( .A(n344), .B(n343), .Y(res[6]) );
XNOR2X4TS U352 ( .A(in2[14]), .B(n125), .Y(n112) );
XNOR2X1TS U353 ( .A(n301), .B(n300), .Y(res[16]) );
XNOR2X4TS U354 ( .A(n105), .B(in2[11]), .Y(n106) );
XOR2XLTS U355 ( .A(n338), .B(n337), .Y(res[8]) );
XOR2X4TS U356 ( .A(n10), .B(in2[12]), .Y(n103) );
NAND2X4TS U357 ( .A(n70), .B(in1[6]), .Y(n342) );
INVX2TS U358 ( .A(n83), .Y(n74) );
XOR2X4TS U359 ( .A(n73), .B(in2[7]), .Y(n75) );
NOR2BX4TS U360 ( .AN(n80), .B(n79), .Y(n81) );
NAND2X8TS U361 ( .A(n82), .B(n81), .Y(n95) );
OAI21X4TS U362 ( .A0(n338), .A1(n334), .B0(n335), .Y(n323) );
NOR2X8TS U363 ( .A(n92), .B(in1[10]), .Y(n324) );
OAI21X4TS U364 ( .A0(n324), .A1(n330), .B0(n325), .Y(n93) );
INVX2TS U365 ( .A(in2[11]), .Y(n98) );
INVX2TS U366 ( .A(in2[12]), .Y(n113) );
MXI2X4TS U367 ( .A(n103), .B(n113), .S0(n83), .Y(n108) );
NAND2X8TS U368 ( .A(n10), .B(n120), .Y(n125) );
XOR2X4TS U369 ( .A(n114), .B(in2[13]), .Y(n115) );
NOR2X8TS U370 ( .A(n116), .B(in1[13]), .Y(n310) );
NOR2X8TS U371 ( .A(n305), .B(n310), .Y(n118) );
NAND3X1TS U372 ( .A(n120), .B(n10), .C(n119), .Y(n121) );
XOR2X1TS U373 ( .A(n121), .B(in2[15]), .Y(n122) );
INVX2TS U374 ( .A(in2[16]), .Y(n127) );
XOR2X1TS U375 ( .A(in2[16]), .B(n160), .Y(n126) );
AOI21X4TS U376 ( .A0(n301), .A1(n63), .B0(n129), .Y(n289) );
INVX2TS U377 ( .A(n160), .Y(n130) );
INVX2TS U378 ( .A(in2[18]), .Y(n134) );
AOI2BB1X4TS U379 ( .A0N(n296), .A1N(n138), .B0(n137), .Y(n139) );
OAI2BB1X4TS U380 ( .A0N(add_sub), .A1N(n145), .B0(n144), .Y(n153) );
INVX2TS U381 ( .A(in2[20]), .Y(n149) );
MXI2X4TS U382 ( .A(n149), .B(n148), .S0(n217), .Y(n154) );
INVX2TS U383 ( .A(in2[21]), .Y(n151) );
AOI21X4TS U384 ( .A0(n156), .A1(n61), .B0(n155), .Y(n274) );
INVX2TS U385 ( .A(in2[25]), .Y(n162) );
INVX2TS U386 ( .A(in2[24]), .Y(n166) );
NOR3X4TS U387 ( .A(n171), .B(in2[22]), .C(n170), .Y(n167) );
MXI2X4TS U388 ( .A(n169), .B(n168), .S0(n83), .Y(n176) );
INVX2TS U389 ( .A(in2[22]), .Y(n174) );
MXI2X4TS U390 ( .A(n174), .B(n173), .S0(n201), .Y(n175) );
OAI21X4TS U391 ( .A0(n263), .A1(n268), .B0(n264), .Y(n254) );
AOI21X4TS U392 ( .A0(n254), .A1(n180), .B0(n179), .Y(n181) );
NAND2X2TS U393 ( .A(n183), .B(n187), .Y(n184) );
MXI2X4TS U394 ( .A(n186), .B(n185), .S0(n201), .Y(n193) );
XNOR2X1TS U395 ( .A(n191), .B(in2[28]), .Y(n192) );
MX2X4TS U396 ( .A(in2[28]), .B(n192), .S0(n217), .Y(n197) );
AOI21X4TS U397 ( .A0(n196), .A1(n59), .B0(n195), .Y(n229) );
XNOR2X1TS U398 ( .A(n204), .B(in2[29]), .Y(n202) );
XOR2X1TS U399 ( .A(n215), .B(in2[30]), .Y(n205) );
XNOR2X2TS U400 ( .A(n208), .B(n207), .Y(res[30]) );
XNOR2X4TS U401 ( .A(n222), .B(n220), .Y(res[31]) );
INVX2TS U402 ( .A(n223), .Y(n227) );
INVX12TS U403 ( .A(n228), .Y(n243) );
OAI21X4TS U404 ( .A0(n243), .A1(n230), .B0(n229), .Y(n235) );
XNOR2X4TS U405 ( .A(n235), .B(n234), .Y(res[28]) );
OAI21X4TS U406 ( .A0(n243), .A1(n236), .B0(n240), .Y(n239) );
XNOR2X4TS U407 ( .A(n239), .B(n238), .Y(res[27]) );
INVX2TS U408 ( .A(n254), .Y(n246) );
AOI21X4TS U409 ( .A0(n271), .A1(n248), .B0(n247), .Y(n253) );
AOI21X4TS U410 ( .A0(n271), .A1(n255), .B0(n254), .Y(n260) );
AOI21X4TS U411 ( .A0(n271), .A1(n269), .B0(n262), .Y(n267) );
XNOR2X1TS U412 ( .A(n298), .B(n297), .Y(res[17]) );
XNOR2X1TS U413 ( .A(n309), .B(n308), .Y(res[14]) );
XNOR2X1TS U414 ( .A(n322), .B(n321), .Y(res[11]) );
XNOR2X1TS U415 ( .A(n328), .B(n327), .Y(res[10]) );
XOR2X1TS U416 ( .A(n345), .B(in2[3]), .Y(n347) );
AOI21X1TS U417 ( .A0(n143), .A1(in2[3]), .B0(in1[3]), .Y(n346) );
XOR2X1TS U418 ( .A(in2[2]), .B(n348), .Y(n350) );
AOI21X1TS U419 ( .A0(n143), .A1(in2[2]), .B0(in1[2]), .Y(n349) );
XNOR2X1TS U420 ( .A(in2[0]), .B(in2[1]), .Y(n352) );
AOI21X1TS U421 ( .A0(n83), .A1(in2[1]), .B0(in1[1]), .Y(n351) );
XOR2X1TS U422 ( .A(n353), .B(in2[5]), .Y(n355) );
AOI21X1TS U423 ( .A0(n143), .A1(in2[5]), .B0(in1[5]), .Y(n354) );
XNOR2X1TS U424 ( .A(in2[4]), .B(n356), .Y(n358) );
AOI21X1TS U425 ( .A0(n143), .A1(in2[4]), .B0(in1[4]), .Y(n357) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_LOALPL6_syn.sdf");
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Mon Oct 24 15:17:36 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.2 2005/10/24 15:50:24 wig Exp $
// $Date: 2005/10/24 15:50:24 $
// $Log: ent_ba.v,v $
// Revision 1.2 2005/10/24 15:50:24 wig
// added 'reg detection to ::out column
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.64 2005/10/20 17:28:26 lutscher Exp
//
// Generator: mix_0.pl Revision: 1.38 , wilfried.gaensheimer@micronas.com
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No `defines in this module
module ent_ba
//
// Generated module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:04:29 02/22/2015
// Design Name:
// Module Name: NormaliseSum
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module NormaliseSum(
input [1:0] idle_AddState,
input [31:0] sout_AddState,
input [1:0] modeout_AddState,
input operationout_AddState,
input NatLogFlagout_AddState,
input [27:0] sum_AddState,
input [7:0] InsTag_AddState,
input clock,
output reg [1:0] idle_NormaliseSum,
output reg [31:0] sout_NormaliseSum,
output reg [1:0] modeout_NormaliseSum,
output reg operationout_NormaliseSum,
output reg NatLogFlagout_NormaliseSum,
output reg [27:0] sum_NormaliseSum,
output reg [7:0] InsTag_NormaliseSum
);
parameter mode_circular =2'b01,
mode_linear =2'b00,
mode_hyperbolic=2'b11;
parameter no_idle = 2'b00,
allign_idle = 2'b01,
put_idle = 2'b10;
wire [7:0] s_exponent;
assign s_exponent = sout_AddState[30:23];
always @ (posedge clock)
begin
InsTag_NormaliseSum <= InsTag_AddState;
idle_NormaliseSum <= idle_AddState;
modeout_NormaliseSum <= modeout_AddState;
operationout_NormaliseSum <= operationout_AddState;
NatLogFlagout_NormaliseSum <= NatLogFlagout_AddState;
if (idle_AddState != put_idle) begin
sout_NormaliseSum[31] <= sout_AddState[31];
sout_NormaliseSum[22:0] <= sout_AddState[22:0];
if (sum_AddState[27] == 1'b1) begin
sout_NormaliseSum[30:23] <= s_exponent + 1;
sum_NormaliseSum <= sum_AddState >> 1;
end
else if(sum_AddState[26:3] == 24'h000000) begin
sout_NormaliseSum[30:23] <= 10'h382;
end
else if (sum_AddState[26:4] == 23'h000000) begin
sout_NormaliseSum[30:23] <= s_exponent - 23;
sum_NormaliseSum <= sum_AddState << 23;
end
else if (sum_AddState[26:5] == 22'h000000) begin
sout_NormaliseSum[30:23] <= s_exponent - 22;
sum_NormaliseSum <= sum_AddState << 22;
end
else if (sum_AddState[26:6] == 21'h000000) begin
sout_NormaliseSum[30:23] <= s_exponent - 21;
sum_NormaliseSum <= sum_AddState << 21;
end
else if (sum_AddState[26:7] == 20'h00000) begin
sout_NormaliseSum[30:23] <= s_exponent - 20;
sum_NormaliseSum <= sum_AddState << 20;
end
else if (sum_AddState[26:8] == 19'h00000) begin
sout_NormaliseSum[30:23] <= s_exponent - 19;
sum_NormaliseSum <= sum_AddState << 19;
end
else if (sum_AddState[26:9] == 18'h00000) begin
sout_NormaliseSum[30:23] <= s_exponent - 18;
sum_NormaliseSum <= sum_AddState << 18;
end
else if (sum_AddState[26:10] == 17'h00000) begin
sout_NormaliseSum[30:23] <= s_exponent - 17;
sum_NormaliseSum <= sum_AddState << 17;
end
else if (sum_AddState[26:11] == 16'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 16;
sum_NormaliseSum <= sum_AddState << 16;
end
else if (sum_AddState[26:12] == 15'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 15;
sum_NormaliseSum <= sum_AddState << 15;
end
else if (sum_AddState[26:13] == 14'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 14;
sum_NormaliseSum <= sum_AddState << 14;
end
else if (sum_AddState[26:14] == 13'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 13;
sum_NormaliseSum <= sum_AddState << 13;
end
else if (sum_AddState[26:15] == 12'h000) begin
sout_NormaliseSum[30:23] <= s_exponent - 12;
sum_NormaliseSum <= sum_AddState << 12;
end
else if (sum_AddState[26:16] == 11'h000) begin
sout_NormaliseSum[30:23] <= s_exponent - 11;
sum_NormaliseSum <= sum_AddState << 11;
end
else if (sum_AddState[26:17] == 10'h000) begin
sout_NormaliseSum[30:23] <= s_exponent - 10;
sum_NormaliseSum <= sum_AddState << 10;
end
else if (sum_AddState[26:18] == 9'h0000) begin
sout_NormaliseSum[30:23] <= s_exponent - 9;
sum_NormaliseSum <= sum_AddState << 9;
end
else if (sum_AddState[26:19] == 8'h00) begin
sout_NormaliseSum[30:23] <= s_exponent - 8;
sum_NormaliseSum <= sum_AddState << 8;
end
else if (sum_AddState[26:20] == 7'h00) begin
sout_NormaliseSum[30:23] <= s_exponent - 7;
sum_NormaliseSum <= sum_AddState << 7;
end
else if (sum_AddState[26:21] == 6'h00) begin
sout_NormaliseSum[30:23] <= s_exponent - 6;
sum_NormaliseSum <= sum_AddState << 6;
end
else if (sum_AddState[26:22] == 5'h00) begin
sout_NormaliseSum[30:23] <= s_exponent - 5;
sum_NormaliseSum <= sum_AddState << 5;
end
else if (sum_AddState[26:23] == 4'h0) begin
sout_NormaliseSum[30:23] <= s_exponent - 4;
sum_NormaliseSum <= sum_AddState << 4;
end
else if (sum_AddState[26:24] == 3'h0) begin
sout_NormaliseSum[30:23] <= s_exponent - 3;
sum_NormaliseSum <= sum_AddState << 3;
end
else if (sum_AddState[26:25] == 2'h0) begin
sout_NormaliseSum[30:23] <= s_exponent - 2;
sum_NormaliseSum <= sum_AddState << 2;
end
else if (sum_AddState[26] == 1'h0) begin
sout_NormaliseSum[30:23] <= s_exponent - 1;
sum_NormaliseSum <= sum_AddState << 1;
end
else begin
sout_NormaliseSum[30:23] <= s_exponent;
sum_NormaliseSum <= sum_AddState;
end
end
else begin
sout_NormaliseSum <= sout_AddState;
sum_NormaliseSum <= 0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFBUF_PP_SYMBOL_V
`define SKY130_FD_SC_HS__BUFBUF_PP_SYMBOL_V
/**
* bufbuf: Double buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__bufbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFBUF_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__SDFRTN_BEHAVIORAL_PP_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk , CLK_N_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTN_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__EDFXBP_BEHAVIORAL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__edfxbp (
Q ,
Q_N,
CLK,
D ,
DE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EDFXBP_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3_SYMBOL_V
`define SKY130_FD_SC_LP__AND3_SYMBOL_V
/**
* and3: 3-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3_SYMBOL_V
|
`define bsg_dff_reset_macro(bits) \
if (harden_p && width_p==bits) \
begin: macro \
bsg_rp_tsmc_40_dff_nreset_s1_b``bits dff(.clk_i \
,.data_i \
,.nreset_i(~reset_i) \
,.data_o); \
end
module bsg_dff_reset #(width_p=-1, harden_p=1)
(input clk_i
,input reset_i
,input [width_p-1:0] data_i
,output [width_p-1:0] data_o
);
`bsg_dff_reset_macro(90)
else `bsg_dff_reset_macro(89)
else `bsg_dff_reset_macro(88)
else `bsg_dff_reset_macro(87)
else `bsg_dff_reset_macro(86)
else `bsg_dff_reset_macro(85)
else `bsg_dff_reset_macro(84)
else `bsg_dff_reset_macro(83)
else `bsg_dff_reset_macro(82)
else `bsg_dff_reset_macro(81)
else `bsg_dff_reset_macro(80)
else `bsg_dff_reset_macro(79)
else `bsg_dff_reset_macro(78)
else `bsg_dff_reset_macro(77)
else `bsg_dff_reset_macro(76)
else `bsg_dff_reset_macro(75)
else `bsg_dff_reset_macro(74)
else `bsg_dff_reset_macro(73)
else `bsg_dff_reset_macro(72)
else `bsg_dff_reset_macro(71)
else `bsg_dff_reset_macro(70)
else `bsg_dff_reset_macro(69)
else `bsg_dff_reset_macro(68)
else `bsg_dff_reset_macro(67)
else `bsg_dff_reset_macro(66)
else `bsg_dff_reset_macro(65)
else `bsg_dff_reset_macro(64)
else `bsg_dff_reset_macro(63)
else `bsg_dff_reset_macro(62)
else `bsg_dff_reset_macro(61)
else `bsg_dff_reset_macro(60)
else `bsg_dff_reset_macro(59)
else `bsg_dff_reset_macro(58)
else `bsg_dff_reset_macro(57)
else `bsg_dff_reset_macro(56)
else `bsg_dff_reset_macro(55)
else `bsg_dff_reset_macro(54)
else `bsg_dff_reset_macro(53)
else `bsg_dff_reset_macro(52)
else `bsg_dff_reset_macro(51)
else `bsg_dff_reset_macro(50)
else `bsg_dff_reset_macro(49)
else `bsg_dff_reset_macro(48)
else `bsg_dff_reset_macro(47)
else `bsg_dff_reset_macro(46)
else `bsg_dff_reset_macro(45)
else `bsg_dff_reset_macro(44)
else `bsg_dff_reset_macro(43)
else `bsg_dff_reset_macro(42)
else `bsg_dff_reset_macro(41)
else `bsg_dff_reset_macro(40)
else `bsg_dff_reset_macro(39)
else `bsg_dff_reset_macro(38)
else `bsg_dff_reset_macro(37)
else `bsg_dff_reset_macro(36)
else `bsg_dff_reset_macro(35)
else `bsg_dff_reset_macro(34)
else `bsg_dff_reset_macro(33)
else `bsg_dff_reset_macro(32)
else `bsg_dff_reset_macro(31)
else `bsg_dff_reset_macro(30)
else `bsg_dff_reset_macro(29)
else `bsg_dff_reset_macro(28)
else `bsg_dff_reset_macro(27)
else `bsg_dff_reset_macro(26)
else `bsg_dff_reset_macro(25)
else `bsg_dff_reset_macro(24)
else `bsg_dff_reset_macro(23)
else `bsg_dff_reset_macro(22)
else `bsg_dff_reset_macro(21)
else `bsg_dff_reset_macro(20)
else `bsg_dff_reset_macro(19)
else `bsg_dff_reset_macro(18)
else `bsg_dff_reset_macro(17)
else `bsg_dff_reset_macro(16)
else `bsg_dff_reset_macro(15)
else `bsg_dff_reset_macro(14)
else `bsg_dff_reset_macro(13)
else `bsg_dff_reset_macro(12)
else `bsg_dff_reset_macro(11)
else `bsg_dff_reset_macro(10)
else `bsg_dff_reset_macro(9)
else `bsg_dff_reset_macro(8)
else `bsg_dff_reset_macro(7)
else `bsg_dff_reset_macro(6)
else `bsg_dff_reset_macro(5)
else `bsg_dff_reset_macro(4)
else `bsg_dff_reset_macro(3)
else
begin: notmacro_dff_reset
reg [width_p-1:0] data_r;
assign data_o = data_r;
always @(posedge clk_i)
begin
if (reset_i)
data_r <= width_p ' (0);
else
data_r <= data_i;
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_dff_reset)
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 15:17:23 10/24/2016
// Module Name: BOTTOM_MUX_tb
// Project Name: MIPS
// Description: Testing MIPS 2-to-1 5-bit MUX implementation in verilog.
//
// Dependencies: BOTTOM_MUX.v
//
////////////////////////////////////////////////////////////////////////////////
module BOTTOM_MUX_tb;
// Inputs
reg [4:0] a;
reg [4:0] b;
reg sel;
// Outputs
wire [4:0] y;
// Instantiate the module.
BOTTOM_MUX mux(.a(a), .b(b), .sel(sel), .y(y));
initial begin
a = 5'b01010;
b = 5'b10101;
sel = 1'b1;
#100;
a = 5'b00000;
#10;
sel = 1'b1;
#10;
b = 5'b11111;
#5;
a = 5'b00101;
#5;
sel = 1'b0;
b = 5'b11101;
#5;
sel = 1'bx;
end
always @ *
#1 $display("t = %0d sel =%b a = %b b = %b y = %b",
$time, sel, a, b, y);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BAI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O21BAI_PP_SYMBOL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21bai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BAI_PP_SYMBOL_V
|
`include "instr_decode_defines.vh"
module instr_decoder_tb();
//Instructions
localparam ADDI = 0;
localparam ORI = 1;
localparam XORI = 2;
localparam ANDI = 3;
localparam SLTI = 4;
localparam SLTUI = 5;
localparam SLLI = 6;
localparam SRLI = 7;
localparam SRAI = 8;
localparam LUI = 9;
localparam AUIPC = 10;
localparam ADD = 11;
localparam SUB = 12;
localparam OR = 13;
localparam XOR = 14;
localparam AND = 15;
localparam SLT = 16;
localparam SLTU = 17;
localparam SLL = 18;
localparam SRL = 19;
localparam SRA = 20;
localparam JALR = 21;
localparam JAL = 22;
localparam SB = 23;
localparam SH = 24;
localparam SW = 25;
localparam LB = 26;
localparam LH = 27;
localparam LW = 28;
localparam LBU = 29;
localparam LHU = 30;
localparam BEQ = 31;
localparam BNE = 32;
localparam BLT = 33;
localparam BLTU = 34;
localparam BGE = 35;
localparam BGEU = 36;
localparam NUM_INSTRS = 37;
localparam OPCODE_IMM = 7'b0010011;
localparam OPCODE_LUI = 7'b0110111;
localparam OPCODE_AUIPC = 7'b0010111;
localparam OPCODE_OP = 7'b0110011;
localparam OPCODE_JAL = 7'b1101111;
localparam OPCODE_JALR = 7'b1100111;
localparam OPCODE_BRANCH = 7'b1100011;
localparam OPCODE_LOAD = 7'b0000011;
localparam OPCODE_STORE = 7'b0100011;
localparam OPCODE_MISC_MEM = 7'b0001111;
localparam OPCODE_SYSTEM = 7'b1110011;
localparam INSTR_ADD = 10'b0000000000;
localparam INSTR_SUB = 10'b0100000000;
localparam INSTR_OR = 10'b0000000110;
localparam INSTR_XOR = 10'b0000000100;
localparam INSTR_AND = 10'b0000000111;
localparam INSTR_SLT = 10'b0000000010;
localparam INSTR_SLTU = 10'b0000000011;
localparam INSTR_SLL = 10'b0000000001;
localparam INSTR_SRL = 10'b0000000101;
localparam INSTR_SRA = 10'b0100000101;
//MEM
localparam INSTR_LB = 3'b000;
localparam INSTR_LH = 3'b001;
localparam INSTR_LW = 3'b010;
localparam INSTR_LBU = 3'b100;
localparam INSTR_LHU = 3'b101;
localparam INSTR_SB = 3'b000;
localparam INSTR_SH = 3'b001;
localparam INSTR_SW = 3'b010;
//Branch
localparam INSTR_BEQ = 3'b000;
localparam INSTR_BNE = 3'b001;
localparam INSTR_BLT = 3'b100;
localparam INSTR_BGE = 3'b101;
localparam INSTR_BLTU = 3'b110;
localparam INSTR_BGEU = 3'b111;
//JALR
localparam INSTR_JALR = 3'b000;
task get_function_and_opcode(input integer instr_enum,
output [9:0] funct,
output [6:0] opcode);
begin
case (instr_enum)
ADDI : {funct, opcode} = {INSTR_ADD, OPCODE_IMM};
ORI : {funct, opcode} = {INSTR_OR, OPCODE_IMM};
XORI : {funct, opcode} = {INSTR_XOR, OPCODE_IMM};
ANDI : {funct, opcode} = {INSTR_AND, OPCODE_IMM};
SLTI : {funct, opcode} = {INSTR_SLT, OPCODE_IMM};
SLTUI: {funct, opcode} = {INSTR_SLTU, OPCODE_IMM};
SLLI : {funct, opcode} = {INSTR_SLL, OPCODE_IMM};
SRLI : {funct, opcode} = {INSTR_SRL, OPCODE_IMM};
SRAI : {funct, opcode} = {INSTR_SRA, OPCODE_IMM};
LUI : {funct, opcode} = {10'b0, OPCODE_LUI};
AUIPC: {funct, opcode} = {10'b0, OPCODE_AUIPC};
ADD : {funct, opcode} = {INSTR_ADD, OPCODE_OP};
SUB : {funct, opcode} = {INSTR_SUB, OPCODE_OP};
OR : {funct, opcode} = {INSTR_OR, OPCODE_OP};
XOR : {funct, opcode} = {INSTR_XOR, OPCODE_OP};
AND : {funct, opcode} = {INSTR_AND, OPCODE_OP};
SLT : {funct, opcode} = {INSTR_SLT, OPCODE_OP};
SLTU : {funct, opcode} = {INSTR_SLTU, OPCODE_OP};
SLL : {funct, opcode} = {INSTR_SLL, OPCODE_OP};
SRL : {funct, opcode} = {INSTR_SRL, OPCODE_OP};
SRA : {funct, opcode} = {INSTR_SRA, OPCODE_OP};
JALR : {funct, opcode} = {INSTR_JALR, OPCODE_JALR};
JAL : {funct, opcode} = {10'b0, OPCODE_JAL};
SB : {funct, opcode} = {INSTR_SB , OPCODE_STORE};
SH : {funct, opcode} = {INSTR_SH , OPCODE_STORE};
SW : {funct, opcode} = {INSTR_SW , OPCODE_STORE};
LB : {funct, opcode} = {INSTR_LB , OPCODE_LOAD};
LH : {funct, opcode} = {INSTR_LH , OPCODE_LOAD};
LW : {funct, opcode} = {INSTR_LW , OPCODE_LOAD};
LBU : {funct, opcode} = {INSTR_LBU , OPCODE_LOAD};
LHU : {funct, opcode} = {INSTR_LHU , OPCODE_LOAD};
BEQ : {funct, opcode} = {INSTR_BEQ , OPCODE_BRANCH};
BNE : {funct, opcode} = {INSTR_BNE , OPCODE_BRANCH};
BLT : {funct, opcode} = {INSTR_BLT , OPCODE_BRANCH};
BLTU : {funct, opcode} = {INSTR_BLTU, OPCODE_BRANCH};
BGE : {funct, opcode} = {INSTR_BGE , OPCODE_BRANCH};
BGEU : {funct, opcode} = {INSTR_BGEU, OPCODE_BRANCH};
endcase
end
endtask
function [31:0] sign_extend_imm (input integer high, low, input [31:0] data);
integer i;
reg sign_bit;
begin
sign_bit = data[high];
for (i = 0; i < 32; i = i + 1) begin
if (i < low)
sign_extend_imm[i] = 0;
else if (i > high)
sign_extend_imm[i] = sign_bit;
else
sign_extend_imm[i] = data[i];
end
end
endfunction
task generate_instruction(output [31:0] instr,
output integer instr_enum,
output [4:0] rsj, rsk, rsd,
output [31:0] immediate);
reg [31:0] rand_val;
reg [7:0] opcode;
reg [9:0] funct_l;
integer instr_enum_l;
reg [31:0] imm;
begin
rsj = 0;
rsk = 0;
rsd = 0;
immediate = 0;
instr_enum_l = $urandom % NUM_INSTRS;
get_function_and_opcode(instr_enum_l, funct_l, opcode);
instr_enum = instr_enum_l;
//rand_val = $urandom;
instr[6:0] = opcode;
case (opcode)
OPCODE_IMM : begin
rsj = $urandom % (1<<5);
rsd = $urandom % (1<<5);
imm = $urandom % (1<<12);
instr[11:7] = rsd;
instr[19:15] = rsj;
if (instr_enum_l == SRLI || instr_enum_l == SRAI || instr_enum_l == SRLI) begin
imm = imm & 'h1f;
instr[14:12] = funct_l[2:0];
instr[24:20] = imm[4:0];
instr[31:25] = funct_l[9:3];
end
else begin
instr[14:12] = funct_l[2:0];
instr[31:20] = imm[11:0];
end
immediate = sign_extend_imm(11, 0, imm);
end
OPCODE_LUI,
OPCODE_AUIPC : begin
rsd = $urandom % (1<<5);
imm = $urandom % (1<<20);
instr[11:7] = rsd;
instr[31:12] = imm[19:0];
immediate = sign_extend_imm(31, 12, imm);
end
OPCODE_OP : begin
rsk = $urandom % (1<<5);
rsj = $urandom % (1<<5);
rsd = $urandom % (1<<5);
instr[11:7] = rsd;
instr[14:12] = funct_l[2:0];
instr[19:15] = rsj;
instr[24:20] = rsk;
instr[31:25] = funct_l[9:3];
end
OPCODE_JAL : begin
rsd = $urandom % (1<<5);
imm = $urandom % (1<<20);
imm = imm << 1;
instr[11:7] = rsd;
instr[19:12] = imm[19:12];
instr[20] = imm[11];
instr[30:21] = imm[10:1];
instr[31] = imm[20];
immediate = sign_extend_imm(20, 1, imm);
end
OPCODE_JALR : begin
rsd = $urandom % (1<<5);
rsj = $urandom % (1<<5);
imm = $urandom % (1<<12);
instr[11:7] = rsd;
instr[14:12] = funct_l[2:0];
instr[19:15] = rsj;
instr[31:20] = imm[11:0];
immediate = sign_extend_imm(11, 0, imm);
end
OPCODE_BRANCH : begin
rsk = $urandom % (1<<5);
rsj = $urandom % (1<<5);
imm = $urandom % (1<<11);
imm = imm << 1;
instr[14:12] = funct_l[2:0];
instr[19:15] = rsj;
instr[24:20] = rsk;
instr[7] = imm[11];
instr[11:8] = imm[4:1];
instr[30:25] = imm[10:5];
instr[31] = imm[12];
immediate = sign_extend_imm(12, 1, imm);
end
OPCODE_LOAD : begin
rsd = $urandom % (1<<5);
rsj = $urandom % (1<<5);
imm = $urandom % (1<<12);
instr[11:7] = rsd;
instr[14:12] = funct_l[2:0];
instr[19:15] = rsj;
instr[31:20] = imm[11:0];
immediate = sign_extend_imm(11, 0, imm);
end
OPCODE_STORE : begin
rsk = $urandom % (1<<5);
rsj = $urandom % (1<<5);
imm = $urandom % (1<<12);
instr[11:7] = imm[4:0];
instr[14:12] = funct_l[2:0];
instr[19:15] = rsj;
instr[24:20] = rsj;
instr[31:25] = imm[11:5];
immediate = sign_extend_imm(11, 0, imm);
end
endcase
end
endtask
reg [31:0] instr;
integer instr_enum;
reg [4:0] rsj, rsk, rsd;
reg [31:0] immediate;
initial begin
repeat (100) begin
generate_instruction(instr, instr_enum, rsj, rsk, rsd, immediate);
$display("instr : %x instr_enum : %x rsj :%x rsk :%x rsd : %x immediate : %x",
instr, instr_enum, rsj, rsk, rsd, immediate);
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 32-Deep by 8-bit Wide Multi Port RAM
// /___/ /\ Filename : RAM32M.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 03/21/06 - Initial version.
// 12/01/06 - Fix cut/past error for port C and D (CR 430051)
// 05/07/08 - Add negative setup/hold support (CR468872)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/18/13 - PR683925 - add invertible pin support.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RAM32M #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT_A = 64'h0000000000000000,
parameter [63:0] INIT_B = 64'h0000000000000000,
parameter [63:0] INIT_C = 64'h0000000000000000,
parameter [63:0] INIT_D = 64'h0000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output [1:0] DOA,
output [1:0] DOB,
output [1:0] DOC,
output [1:0] DOD,
input [4:0] ADDRA,
input [4:0] ADDRB,
input [4:0] ADDRC,
input [4:0] ADDRD,
input [1:0] DIA,
input [1:0] DIB,
input [1:0] DIC,
input [1:0] DID,
input WCLK,
input WE
);
// define constants
localparam MODULE_NAME = "RAM32M";
reg trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire IS_WCLK_INVERTED_BIN;
wire [4:0] ADDRD_in;
wire [1:0] DIA_in;
wire [1:0] DIB_in;
wire [1:0] DIC_in;
wire [1:0] DID_in;
wire WCLK_in;
wire WE_in;
`ifdef XIL_TIMING
wire [4:0] ADDRD_dly;
wire [1:0] DIA_dly;
wire [1:0] DIB_dly;
wire [1:0] DIC_dly;
wire [1:0] DID_dly;
wire WCLK_dly;
wire WE_dly;
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_we_clk_en_p;
wire sh_we_clk_en_n;
assign ADDRD_in = ADDRD_dly;
assign DIA_in = DIA_dly;
assign DIB_in = DIB_dly;
assign DIC_in = DIC_dly;
assign DID_in = DID_dly;
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE_dly; // rv 1
`else
assign ADDRD_in = ADDRD;
assign DIA_in = DIA;
assign DIB_in = DIB;
assign DIC_in = DIC;
assign DID_in = DID;
assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE; // rv 1
`endif
assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((INIT_A < 64'h0000000000000000) || (INIT_A > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-101] INIT_A attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_A);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_B < 64'h0000000000000000) || (INIT_B > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-102] INIT_B attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_B);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_C < 64'h0000000000000000) || (INIT_C > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-103] INIT_C attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_C);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_D < 64'h0000000000000000) || (INIT_D > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-104] INIT_D attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT_D);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_WCLK_INVERTED !== 1'b0) && (IS_WCLK_INVERTED !== 1'b1))) begin
$display("Error: [Unisim %s-109] IS_WCLK_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_WCLK_INVERTED);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
reg [63:0] mem_a, mem_b, mem_c, mem_d;
reg [5:0] addr_in2, addr_in1;
initial begin
mem_a = INIT_A;
mem_b = INIT_B;
mem_c = INIT_C;
mem_d = INIT_D;
end
always @(ADDRD_in) begin
addr_in2 = 2 * ADDRD_in;
addr_in1 = 2 * ADDRD_in + 1;
end
always @(posedge WCLK_in)
if (WE_in) begin
mem_a[addr_in2] <= #100 DIA_in[0];
mem_a[addr_in1] <= #100 DIA_in[1];
mem_b[addr_in2] <= #100 DIB_in[0];
mem_b[addr_in1] <= #100 DIB_in[1];
mem_c[addr_in2] <= #100 DIC_in[0];
mem_c[addr_in1] <= #100 DIC_in[1];
mem_d[addr_in2] <= #100 DID_in[0];
mem_d[addr_in1] <= #100 DID_in[1];
end
assign DOA[0] = mem_a[2*ADDRA];
assign DOA[1] = mem_a[2*ADDRA + 1];
assign DOB[0] = mem_b[2*ADDRB];
assign DOB[1] = mem_b[2*ADDRB + 1];
assign DOC[0] = mem_c[2*ADDRC];
assign DOC[1] = mem_c[2*ADDRC + 1];
assign DOD[0] = mem_d[2*ADDRD_in];
assign DOD[1] = mem_d[2*ADDRD_in + 1];
`ifdef XIL_TIMING
always @(notifier) begin
mem_a[addr_in2] <= 1'bx;
mem_a[addr_in1] <= 1'bx;
mem_b[addr_in2] <= 1'bx;
mem_b[addr_in1] <= 1'bx;
mem_c[addr_in2] <= 1'bx;
mem_c[addr_in1] <= 1'bx;
mem_d[addr_in2] <= 1'bx;
mem_d[addr_in1] <= 1'bx;
end
assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN;
assign sh_clk_en_n = IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN;
specify
(WCLK => DOA[0]) = (0:0:0, 0:0:0);
(WCLK => DOA[1]) = (0:0:0, 0:0:0);
(WCLK => DOB[0]) = (0:0:0, 0:0:0);
(WCLK => DOB[1]) = (0:0:0, 0:0:0);
(WCLK => DOC[0]) = (0:0:0, 0:0:0);
(WCLK => DOC[1]) = (0:0:0, 0:0:0);
(WCLK => DOD[0]) = (0:0:0, 0:0:0);
(WCLK => DOD[1]) = (0:0:0, 0:0:0);
(ADDRA *> DOA[0]) = (0:0:0, 0:0:0);
(ADDRA *> DOA[1]) = (0:0:0, 0:0:0);
(ADDRB *> DOB[0]) = (0:0:0, 0:0:0);
(ADDRB *> DOB[1]) = (0:0:0, 0:0:0);
(ADDRC *> DOC[0]) = (0:0:0, 0:0:0);
(ADDRC *> DOC[1]) = (0:0:0, 0:0:0);
(ADDRD *> DOD[0]) = (0:0:0, 0:0:0);
(ADDRD *> DOD[1]) = (0:0:0, 0:0:0);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, negedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[0]);
$setuphold (negedge WCLK, negedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[1]);
$setuphold (negedge WCLK, negedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[2]);
$setuphold (negedge WCLK, negedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[3]);
$setuphold (negedge WCLK, negedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[4]);
$setuphold (negedge WCLK, negedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[0]);
$setuphold (negedge WCLK, negedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[1]);
$setuphold (negedge WCLK, negedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[0]);
$setuphold (negedge WCLK, negedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[1]);
$setuphold (negedge WCLK, negedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[0]);
$setuphold (negedge WCLK, negedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[1]);
$setuphold (negedge WCLK, negedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[0]);
$setuphold (negedge WCLK, negedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[1]);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, posedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[0]);
$setuphold (negedge WCLK, posedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[1]);
$setuphold (negedge WCLK, posedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[2]);
$setuphold (negedge WCLK, posedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[3]);
$setuphold (negedge WCLK, posedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRD_dly[4]);
$setuphold (negedge WCLK, posedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[0]);
$setuphold (negedge WCLK, posedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly[1]);
$setuphold (negedge WCLK, posedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[0]);
$setuphold (negedge WCLK, posedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly[1]);
$setuphold (negedge WCLK, posedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[0]);
$setuphold (negedge WCLK, posedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly[1]);
$setuphold (negedge WCLK, posedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[0]);
$setuphold (negedge WCLK, posedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly[1]);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[0]);
$setuphold (posedge WCLK, negedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[1]);
$setuphold (posedge WCLK, negedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[2]);
$setuphold (posedge WCLK, negedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[3]);
$setuphold (posedge WCLK, negedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[4]);
$setuphold (posedge WCLK, negedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[0]);
$setuphold (posedge WCLK, negedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[1]);
$setuphold (posedge WCLK, negedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[0]);
$setuphold (posedge WCLK, negedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[1]);
$setuphold (posedge WCLK, negedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[0]);
$setuphold (posedge WCLK, negedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[1]);
$setuphold (posedge WCLK, negedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[0]);
$setuphold (posedge WCLK, negedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[1]);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, posedge ADDRD[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[0]);
$setuphold (posedge WCLK, posedge ADDRD[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[1]);
$setuphold (posedge WCLK, posedge ADDRD[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[2]);
$setuphold (posedge WCLK, posedge ADDRD[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[3]);
$setuphold (posedge WCLK, posedge ADDRD[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRD_dly[4]);
$setuphold (posedge WCLK, posedge DIA[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[0]);
$setuphold (posedge WCLK, posedge DIA[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly[1]);
$setuphold (posedge WCLK, posedge DIB[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[0]);
$setuphold (posedge WCLK, posedge DIB[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly[1]);
$setuphold (posedge WCLK, posedge DIC[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[0]);
$setuphold (posedge WCLK, posedge DIC[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly[1]);
$setuphold (posedge WCLK, posedge DID[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[0]);
$setuphold (posedge WCLK, posedge DID[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly[1]);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
module mcm(
clk,rst,
i_valid,
inverse,
i_transize,
tq_sel_i,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
o_valid,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk;
input rst;
input i_valid;
input inverse;
input [1:0] i_transize;
input [1:0] tq_sel_i;
input signed [18:0] i_0;
input signed [18:0] i_1;
input signed [18:0] i_2;
input signed [18:0] i_3;
input signed [18:0] i_4;
input signed [18:0] i_5;
input signed [18:0] i_6;
input signed [18:0] i_7;
input signed [18:0] i_8;
input signed [18:0] i_9;
input signed [18:0] i_10;
input signed [18:0] i_11;
input signed [18:0] i_12;
input signed [18:0] i_13;
input signed [18:0] i_14;
input signed [18:0] i_15;
input signed [18:0] i_16;
input signed [18:0] i_17;
input signed [18:0] i_18;
input signed [18:0] i_19;
input signed [18:0] i_20;
input signed [18:0] i_21;
input signed [18:0] i_22;
input signed [18:0] i_23;
input signed [18:0] i_24;
input signed [18:0] i_25;
input signed [18:0] i_26;
input signed [18:0] i_27;
input signed [18:0] i_28;
input signed [18:0] i_29;
input signed [18:0] i_30;
input signed [18:0] i_31;
output reg o_valid;
output reg signed [27:0] o_0;
output reg signed [27:0] o_1;
output reg signed [27:0] o_2;
output reg signed [27:0] o_3;
output reg signed [27:0] o_4;
output reg signed [27:0] o_5;
output reg signed [27:0] o_6;
output reg signed [27:0] o_7;
output reg signed [27:0] o_8;
output reg signed [27:0] o_9;
output reg signed [27:0] o_10;
output reg signed [27:0] o_11;
output reg signed [27:0] o_12;
output reg signed [27:0] o_13;
output reg signed [27:0] o_14;
output reg signed [27:0] o_15;
output reg signed [27:0] o_16;
output reg signed [27:0] o_17;
output reg signed [27:0] o_18;
output reg signed [27:0] o_19;
output reg signed [27:0] o_20;
output reg signed [27:0] o_21;
output reg signed [27:0] o_22;
output reg signed [27:0] o_23;
output reg signed [27:0] o_24;
output reg signed [27:0] o_25;
output reg signed [27:0] o_26;
output reg signed [27:0] o_27;
output reg signed [27:0] o_28;
output reg signed [27:0] o_29;
output reg signed [27:0] o_30;
output reg signed [27:0] o_31;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [18:0] in_0;
wire signed [18:0] in_1;
wire signed [18:0] in_2;
wire signed [18:0] in_3;
wire signed [18:0] in_4;
wire signed [18:0] in_5;
wire signed [18:0] in_6;
wire signed [18:0] in_7;
wire signed [18:0] in_8;
wire signed [18:0] in_9;
wire signed [18:0] in_10;
wire signed [18:0] in_11;
wire signed [18:0] in_12;
wire signed [18:0] in_13;
wire signed [18:0] in_14;
wire signed [18:0] in_15;
wire signed [18:0] in_16;
wire signed [18:0] in_17;
wire signed [18:0] in_18;
wire signed [18:0] in_19;
wire signed [18:0] in_20;
wire signed [18:0] in_21;
wire signed [18:0] in_22;
wire signed [18:0] in_23;
wire signed [18:0] in_24;
wire signed [18:0] in_25;
wire signed [18:0] in_26;
wire signed [18:0] in_27;
wire signed [18:0] in_28;
wire signed [18:0] in_29;
wire signed [18:0] in_30;
wire signed [18:0] in_31;
wire signed [27:0] oms00_0;
wire signed [27:0] oms00_1;
wire signed [27:0] oms00_2;
wire signed [27:0] oms00_3;
wire signed [27:0] oms01_0;
wire signed [27:0] oms01_1;
wire signed [27:0] oms01_2;
wire signed [27:0] oms01_3;
wire signed [27:0] oms02_0;
wire signed [27:0] oms02_1;
wire signed [27:0] oms02_2;
wire signed [27:0] oms02_3;
wire signed [27:0] oms03_0;
wire signed [27:0] oms03_1;
wire signed [27:0] oms03_2;
wire signed [27:0] oms03_3;
wire signed [27:0] om00_0;
wire signed [27:0] om00_1;
wire signed [27:0] om00_2;
wire signed [27:0] om00_3;
wire signed [27:0] om01_0;
wire signed [27:0] om01_1;
wire signed [27:0] om01_2;
wire signed [27:0] om01_3;
wire signed [27:0] om02_0;
wire signed [27:0] om02_1;
wire signed [27:0] om02_2;
wire signed [27:0] om02_3;
wire signed [27:0] om03_0;
wire signed [27:0] om03_1;
wire signed [27:0] om03_2;
wire signed [27:0] om03_3;
wire signed [27:0] om40_0;
wire signed [27:0] om40_1;
wire signed [27:0] om40_2;
wire signed [27:0] om40_3;
wire signed [27:0] om41_0;
wire signed [27:0] om41_1;
wire signed [27:0] om41_2;
wire signed [27:0] om41_3;
wire signed [27:0] om42_0;
wire signed [27:0] om42_1;
wire signed [27:0] om42_2;
wire signed [27:0] om42_3;
wire signed [27:0] om43_0;
wire signed [27:0] om43_1;
wire signed [27:0] om43_2;
wire signed [27:0] om43_3;
wire signed [27:0] om80_0;
wire signed [27:0] om80_1;
wire signed [27:0] om80_2;
wire signed [27:0] om80_3;
wire signed [27:0] om80_4;
wire signed [27:0] om80_5;
wire signed [27:0] om80_6;
wire signed [27:0] om80_7;
wire signed [27:0] om81_0;
wire signed [27:0] om81_1;
wire signed [27:0] om81_2;
wire signed [27:0] om81_3;
wire signed [27:0] om81_4;
wire signed [27:0] om81_5;
wire signed [27:0] om81_6;
wire signed [27:0] om81_7;
wire signed [27:0] om160_0 ;
wire signed [27:0] om160_1 ;
wire signed [27:0] om160_2 ;
wire signed [27:0] om160_3 ;
wire signed [27:0] om160_4 ;
wire signed [27:0] om160_5 ;
wire signed [27:0] om160_6 ;
wire signed [27:0] om160_7 ;
wire signed [27:0] om160_8 ;
wire signed [27:0] om160_9 ;
wire signed [27:0] om160_10;
wire signed [27:0] om160_11;
wire signed [27:0] om160_12;
wire signed [27:0] om160_13;
wire signed [27:0] om160_14;
wire signed [27:0] om160_15;
// *********************************************
//
// REG DECLARATION
//
// **********************************************
reg i_valid_1;
reg signed [18:0] ims00_0;
reg signed [18:0] ims00_1;
reg signed [18:0] ims00_2;
reg signed [18:0] ims00_3;
reg signed [18:0] ims01_0;
reg signed [18:0] ims01_1;
reg signed [18:0] ims01_2;
reg signed [18:0] ims01_3;
reg signed [18:0] ims02_0;
reg signed [18:0] ims02_1;
reg signed [18:0] ims02_2;
reg signed [18:0] ims02_3;
reg signed [18:0] ims03_0;
reg signed [18:0] ims03_1;
reg signed [18:0] ims03_2;
reg signed [18:0] ims03_3;
reg signed [18:0] im00_0;
reg signed [18:0] im00_1;
reg signed [18:0] im00_2;
reg signed [18:0] im00_3;
reg signed [18:0] im01_0;
reg signed [18:0] im01_1;
reg signed [18:0] im01_2;
reg signed [18:0] im01_3;
reg signed [18:0] im02_0;
reg signed [18:0] im02_1;
reg signed [18:0] im02_2;
reg signed [18:0] im02_3;
reg signed [18:0] im03_0;
reg signed [18:0] im03_1;
reg signed [18:0] im03_2;
reg signed [18:0] im03_3;
reg signed [18:0] im40_0;
reg signed [18:0] im40_1;
reg signed [18:0] im40_2;
reg signed [18:0] im40_3;
reg signed [18:0] im41_0;
reg signed [18:0] im41_1;
reg signed [18:0] im41_2;
reg signed [18:0] im41_3;
reg signed [18:0] im42_0;
reg signed [18:0] im42_1;
reg signed [18:0] im42_2;
reg signed [18:0] im42_3;
reg signed [18:0] im43_0;
reg signed [18:0] im43_1;
reg signed [18:0] im43_2;
reg signed [18:0] im43_3;
reg signed [17:0] im80_0;
reg signed [17:0] im80_1;
reg signed [17:0] im80_2;
reg signed [17:0] im80_3;
reg signed [17:0] im80_4;
reg signed [17:0] im80_5;
reg signed [17:0] im80_6;
reg signed [17:0] im80_7;
reg signed [17:0] im81_0;
reg signed [17:0] im81_1;
reg signed [17:0] im81_2;
reg signed [17:0] im81_3;
reg signed [17:0] im81_4;
reg signed [17:0] im81_5;
reg signed [17:0] im81_6;
reg signed [17:0] im81_7;
reg signed [16:0] im160_0 ;
reg signed [16:0] im160_1 ;
reg signed [16:0] im160_2 ;
reg signed [16:0] im160_3 ;
reg signed [16:0] im160_4 ;
reg signed [16:0] im160_5 ;
reg signed [16:0] im160_6 ;
reg signed [16:0] im160_7 ;
reg signed [16:0] im160_8 ;
reg signed [16:0] im160_9 ;
reg signed [16:0] im160_10;
reg signed [16:0] im160_11;
reg signed [16:0] im160_12;
reg signed [16:0] im160_13;
reg signed [16:0] im160_14;
reg signed [16:0] im160_15;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign in_0=i_valid?i_0:'b0;
assign in_1=i_valid?i_1:'b0;
assign in_2=i_valid?i_2:'b0;
assign in_3=i_valid?i_3:'b0;
assign in_4=i_valid?i_4:'b0;
assign in_5=i_valid?i_5:'b0;
assign in_6=i_valid?i_6:'b0;
assign in_7=i_valid?i_7:'b0;
assign in_8=i_valid?i_8:'b0;
assign in_9=i_valid?i_9:'b0;
assign in_10=i_valid?i_10:'b0;
assign in_11=i_valid?i_11:'b0;
assign in_12=i_valid?i_12:'b0;
assign in_13=i_valid?i_13:'b0;
assign in_14=i_valid?i_14:'b0;
assign in_15=i_valid?i_15:'b0;
assign in_16=i_valid?i_16:'b0;
assign in_17=i_valid?i_17:'b0;
assign in_18=i_valid?i_18:'b0;
assign in_19=i_valid?i_19:'b0;
assign in_20=i_valid?i_20:'b0;
assign in_21=i_valid?i_21:'b0;
assign in_22=i_valid?i_22:'b0;
assign in_23=i_valid?i_23:'b0;
assign in_24=i_valid?i_24:'b0;
assign in_25=i_valid?i_25:'b0;
assign in_26=i_valid?i_26:'b0;
assign in_27=i_valid?i_27:'b0;
assign in_28=i_valid?i_28:'b0;
assign in_29=i_valid?i_29:'b0;
assign in_30=i_valid?i_30:'b0;
assign in_31=i_valid?i_31:'b0;
always@(*)
case(i_transize)
2'b00: if(!tq_sel_i[1])
begin
im00_0='b0;im00_1='b0;im00_2='b0;im00_3='b0;
im01_0='b0;im01_1='b0;im01_2='b0;im01_3='b0;
im02_0='b0;im02_1='b0;im02_2='b0;im02_3='b0;
im03_0='b0;im03_1='b0;im03_2='b0;im03_3='b0;
im40_0='b0;im40_1='b0;im40_2='b0;im40_3='b0;
im41_0='b0;im41_1='b0;im41_2='b0;im41_3='b0;
im42_0='b0;im42_1='b0;im42_2='b0;im42_3='b0;
im43_0='b0;im43_1='b0;im43_2='b0;im43_3='b0;
im80_0='b0;im80_1='b0;im80_2='b0;im80_3='b0;
im80_4='b0;im80_5='b0;im80_6='b0;im80_7='b0;
im81_0='b0;im81_1='b0;im81_2='b0;im81_3='b0;
im81_4='b0;im81_5='b0;im81_6='b0;im81_7='b0;
im160_0 ='b0;im160_1 ='b0;im160_2 ='b0;im160_3 ='b0;
im160_4 ='b0;im160_5 ='b0;im160_6 ='b0;im160_7 ='b0;
im160_8 ='b0;im160_9 ='b0;im160_10='b0;im160_11='b0;
im160_12='b0;im160_13='b0;im160_14='b0;im160_15='b0;
ims00_0=in_0 ;
ims00_1=in_1 ;
ims00_2=in_2 ;
ims00_3=in_3 ;
ims01_0=in_8 ;
ims01_1=in_9 ;
ims01_2=in_10;
ims01_3=in_11;
ims02_0=in_16;
ims02_1=in_17;
ims02_2=in_18;
ims02_3=in_19;
ims03_0=in_24;
ims03_1=in_25;
ims03_2=in_26;
ims03_3=in_27;
o_0 =oms00_0;
o_1 =oms00_1;
o_2 =oms00_2;
o_3 =oms00_3;
o_4=28'b0;
o_5=28'b0;
o_6=28'b0;
o_7=28'b0;
o_8 =oms01_0;
o_9 =oms01_1;
o_10 =oms01_2;
o_11 =oms01_3;
o_12=28'b0;
o_13=28'b0;
o_14=28'b0;
o_15=28'b0;
o_16=oms02_0;
o_17=oms02_1;
o_18=oms02_2;
o_19=oms02_3;
o_20=28'b0;
o_21=28'b0;
o_22=28'b0;
o_23=28'b0;
o_24=oms03_0;
o_25=oms03_1;
o_26=oms03_2;
o_27=oms03_3;
o_28=28'b0;
o_29=28'b0;
o_30=28'b0;
o_31=28'b0;
end
else begin
ims00_0='b0;ims00_1='b0;ims00_2='b0;ims00_3='b0;
ims01_0='b0;ims01_1='b0;ims01_2='b0;ims01_3='b0;
ims02_0='b0;ims02_1='b0;ims02_2='b0;ims02_3='b0;
ims03_0='b0;ims03_1='b0;ims03_2='b0;ims03_3='b0;
im40_0='b0;im40_1='b0;im40_2='b0;im40_3='b0;
im41_0='b0;im41_1='b0;im41_2='b0;im41_3='b0;
im42_0='b0;im42_1='b0;im42_2='b0;im42_3='b0;
im43_0='b0;im43_1='b0;im43_2='b0;im43_3='b0;
im80_0='b0;im80_1='b0;im80_2='b0;im80_3='b0;
im80_4='b0;im80_5='b0;im80_6='b0;im80_7='b0;
im81_0='b0;im81_1='b0;im81_2='b0;im81_3='b0;
im81_4='b0;im81_5='b0;im81_6='b0;im81_7='b0;
im160_0 ='b0;im160_1 ='b0;im160_2 ='b0;im160_3 ='b0;
im160_4 ='b0;im160_5 ='b0;im160_6 ='b0;im160_7 ='b0;
im160_8 ='b0;im160_9 ='b0;im160_10='b0;im160_11='b0;
im160_12='b0;im160_13='b0;im160_14='b0;im160_15='b0;
im00_0=in_0 ;
im00_1=in_1 ;
im00_2=in_2 ;
im00_3=in_3 ;
im01_0=in_8 ;
im01_1=in_9 ;
im01_2=in_10;
im01_3=in_11;
im02_0=in_16;
im02_1=in_17;
im02_2=in_18;
im02_3=in_19;
im03_0=in_24;
im03_1=in_25;
im03_2=in_26;
im03_3=in_27;
o_0 =om00_0;
o_1 =om00_1;
o_2 =om00_2;
o_3 =om00_3;
o_4=28'b0;
o_5=28'b0;
o_6=28'b0;
o_7=28'b0;
o_8 =om01_0;
o_9 =om01_1;
o_10 =om01_2;
o_11 =om01_3;
o_12=28'b0;
o_13=28'b0;
o_14=28'b0;
o_15=28'b0;
o_16=om02_0;
o_17=om02_1;
o_18=om02_2;
o_19=om02_3;
o_20=28'b0;
o_21=28'b0;
o_22=28'b0;
o_23=28'b0;
o_24=om03_0;
o_25=om03_1;
o_26=om03_2;
o_27=om03_3;
o_28=28'b0;
o_29=28'b0;
o_30=28'b0;
o_31=28'b0;
end
2'b01:begin
im00_0=in_0;
im00_1=in_1;
im00_2=in_2;
im00_3=in_3;
im40_0=in_4;
im40_1=in_5;
im40_2=in_6;
im40_3=in_7;
im01_0=in_8 ;
im01_1=in_9 ;
im01_2=in_10;
im01_3=in_11;
im41_0=in_12;
im41_1=in_13;
im41_2=in_14;
im41_3=in_15;
im02_0=in_16;
im02_1=in_17;
im02_2=in_18;
im02_3=in_19;
im42_0=in_20;
im42_1=in_21;
im42_2=in_22;
im42_3=in_23;
im03_0=in_24;
im03_1=in_25;
im03_2=in_26;
im03_3=in_27;
im43_0=in_28;
im43_1=in_29;
im43_2=in_30;
im43_3=in_31;
ims00_0='b0;ims00_1='b0;ims00_2='b0;ims00_3='b0;
ims01_0='b0;ims01_1='b0;ims01_2='b0;ims01_3='b0;
ims02_0='b0;ims02_1='b0;ims02_2='b0;ims02_3='b0;
ims03_0='b0;ims03_1='b0;ims03_2='b0;ims03_3='b0;
im80_0='b0;im80_1='b0;im80_2='b0;im80_3='b0;
im80_4='b0;im80_5='b0;im80_6='b0;im80_7='b0;
im81_0='b0;im81_1='b0;im81_2='b0;im81_3='b0;
im81_4='b0;im81_5='b0;im81_6='b0;im81_7='b0;
im160_0 ='b0;im160_1 ='b0;im160_2 ='b0;im160_3 ='b0;
im160_4 ='b0;im160_5 ='b0;im160_6 ='b0;im160_7 ='b0;
im160_8 ='b0;im160_9 ='b0;im160_10='b0;im160_11='b0;
im160_12='b0;im160_13='b0;im160_14='b0;im160_15='b0;
o_0=om00_0;
o_1=om00_1;
o_2=om00_2;
o_3=om00_3;
o_4=om40_0;
o_5=om40_1;
o_6=om40_2;
o_7=om40_3;
o_8 =om01_0;
o_9 =om01_1;
o_10=om01_2;
o_11=om01_3;
o_12=om41_0;
o_13=om41_1;
o_14=om41_2;
o_15=om41_3;
o_16=om02_0;
o_17=om02_1;
o_18=om02_2;
o_19=om02_3;
o_20=om42_0;
o_21=om42_1;
o_22=om42_2;
o_23=om42_3;
o_24=om03_0;
o_25=om03_1;
o_26=om03_2;
o_27=om03_3;
o_28=om43_0;
o_29=om43_1;
o_30=om43_2;
o_31=om43_3;
end
2'b10:begin
ims00_0='b0;ims00_1='b0;ims00_2='b0;ims00_3='b0;
ims01_0='b0;ims01_1='b0;ims01_2='b0;ims01_3='b0;
ims02_0='b0;ims02_1='b0;ims02_2='b0;ims02_3='b0;
ims03_0='b0;ims03_1='b0;ims03_2='b0;ims03_3='b0;
im02_0='b0;im02_1='b0;im02_2='b0;im02_3='b0;
im03_0='b0;im03_1='b0;im03_2='b0;im03_3='b0;
im42_0='b0;im42_1='b0;im42_2='b0;im42_3='b0;
im43_0='b0;im43_1='b0;im43_2='b0;im43_3='b0;
im160_0 ='b0;im160_1 ='b0;im160_2 ='b0;im160_3 ='b0;
im160_4 ='b0;im160_5 ='b0;im160_6 ='b0;im160_7 ='b0;
im160_8 ='b0;im160_9 ='b0;im160_10='b0;im160_11='b0;
im160_12='b0;im160_13='b0;im160_14='b0;im160_15='b0;
im00_0=in_0 ;
im00_1=in_1 ;
im00_2=in_2 ;
im00_3=in_3 ;
im40_0=in_4 ;
im40_1=in_5 ;
im40_2=in_6 ;
im40_3=in_7 ;
im80_0=in_8 ;
im80_1=in_9 ;
im80_2=in_10;
im80_3=in_11;
im80_4=in_12;
im80_5=in_13;
im80_6=in_14;
im80_7=in_15;
im01_0=in_16;
im01_1=in_17;
im01_2=in_18;
im01_3=in_19;
im41_0=in_20;
im41_1=in_21;
im41_2=in_22;
im41_3=in_23;
im81_0=in_24;
im81_1=in_25;
im81_2=in_26;
im81_3=in_27;
im81_4=in_28;
im81_5=in_29;
im81_6=in_30;
im81_7=in_31;
o_0 =om00_0;
o_1 =om00_1;
o_2 =om00_2;
o_3 =om00_3;
o_4 =om40_0;
o_5 =om40_1;
o_6 =om40_2;
o_7 =om40_3;
o_8 =om80_0;
o_9 =om80_1;
o_10=om80_2;
o_11=om80_3;
o_12=om80_4;
o_13=om80_5;
o_14=om80_6;
o_15=om80_7;
o_16=om01_0;
o_17=om01_1;
o_18=om01_2;
o_19=om01_3;
o_20=om41_0;
o_21=om41_1;
o_22=om41_2;
o_23=om41_3;
o_24=om81_0;
o_25=om81_1;
o_26=om81_2;
o_27=om81_3;
o_28=om81_4;
o_29=om81_5;
o_30=om81_6;
o_31=om81_7;
end
2'b11:begin
ims00_0='b0;ims00_1='b0;ims00_2='b0;ims00_3='b0;
ims01_0='b0;ims01_1='b0;ims01_2='b0;ims01_3='b0;
ims02_0='b0;ims02_1='b0;ims02_2='b0;ims02_3='b0;
ims03_0='b0;ims03_1='b0;ims03_2='b0;ims03_3='b0;
im01_0='b0;im01_1='b0;im01_2='b0;im01_3='b0;
im02_0='b0;im02_1='b0;im02_2='b0;im02_3='b0;
im03_0='b0;im03_1='b0;im03_2='b0;im03_3='b0;
im41_0='b0;im41_1='b0;im41_2='b0;im41_3='b0;
im42_0='b0;im42_1='b0;im42_2='b0;im42_3='b0;
im43_0='b0;im43_1='b0;im43_2='b0;im43_3='b0;
im81_0='b0;im81_1='b0;im81_2='b0;im81_3='b0;
im81_4='b0;im81_5='b0;im81_6='b0;im81_7='b0;
im00_0=in_0 ;
im00_1=in_1 ;
im00_2=in_2 ;
im00_3=in_3 ;
im40_0=in_4 ;
im40_1=in_5 ;
im40_2=in_6 ;
im40_3=in_7 ;
im80_0=in_8 ;
im80_1=in_9 ;
im80_2=in_10;
im80_3=in_11;
im80_4=in_12;
im80_5=in_13;
im80_6=in_14;
im80_7=in_15;
im160_0=in_16;
im160_1=in_17;
im160_2=in_18;
im160_3=in_19;
im160_4=in_20;
im160_5=in_21;
im160_6=in_22;
im160_7=in_23;
im160_8=in_24;
im160_9=in_25;
im160_10=in_26;
im160_11=in_27;
im160_12=in_28;
im160_13=in_29;
im160_14=in_30;
im160_15=in_31;
o_0 =om00_0;
o_1 =om00_1;
o_2 =om00_2;
o_3 =om00_3;
o_4 =om40_0;
o_5 =om40_1;
o_6 =om40_2;
o_7 =om40_3;
o_8 =om80_0;
o_9 =om80_1;
o_10=om80_2;
o_11=om80_3;
o_12=om80_4;
o_13=om80_5;
o_14=om80_6;
o_15=om80_7;
o_16=om160_0 ;
o_17=om160_1 ;
o_18=om160_2 ;
o_19=om160_3 ;
o_20=om160_4 ;
o_21=om160_5 ;
o_22=om160_6 ;
o_23=om160_7 ;
o_24=om160_8 ;
o_25=om160_9 ;
o_26=om160_10;
o_27=om160_11;
o_28=om160_12;
o_29=om160_13;
o_30=om160_14;
o_31=om160_15;
end
endcase
// ********************************************
//
// Sequence Logic
//
// ********************************************
always@(posedge clk or negedge rst)
if(!rst)
i_valid_1<=1'b0;
else
i_valid_1<=i_valid;
always@(posedge clk or negedge rst)
if(!rst)
o_valid<=1'b0;
else
o_valid<=i_valid_1;
// ********************************************
//
// Sub Modules
//
// ********************************************
dst dst_0(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(ims00_0),
.i_1(ims00_1),
.i_2(ims00_2),
.i_3(ims00_3),
.o_0(oms00_0),
.o_1(oms00_1),
.o_2(oms00_2),
.o_3(oms00_3)
);
dst dst_1(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(ims01_0),
.i_1(ims01_1),
.i_2(ims01_2),
.i_3(ims01_3),
.o_0(oms01_0),
.o_1(oms01_1),
.o_2(oms01_2),
.o_3(oms01_3)
);
dst dst_2(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(ims02_0),
.i_1(ims02_1),
.i_2(ims02_2),
.i_3(ims02_3),
.o_0(oms02_0),
.o_1(oms02_1),
.o_2(oms02_2),
.o_3(oms02_3)
);
dst dst_3(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(ims03_0),
.i_1(ims03_1),
.i_2(ims03_2),
.i_3(ims03_3),
.o_0(oms03_0),
.o_1(oms03_1),
.o_2(oms03_2),
.o_3(oms03_3)
);
mcm_0 m0_0(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im00_0),
.i_1(im00_1),
.i_2(im00_2),
.i_3(im00_3),
.o_0(om00_0),
.o_1(om00_1),
.o_2(om00_2),
.o_3(om00_3)
);
mcm_0 m0_1(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im01_0),
.i_1(im01_1),
.i_2(im01_2),
.i_3(im01_3),
.o_0(om01_0),
.o_1(om01_1),
.o_2(om01_2),
.o_3(om01_3)
);
mcm_0 m0_2(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im02_0),
.i_1(im02_1),
.i_2(im02_2),
.i_3(im02_3),
.o_0(om02_0),
.o_1(om02_1),
.o_2(om02_2),
.o_3(om02_3)
);
mcm_0 m0_3(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im03_0),
.i_1(im03_1),
.i_2(im03_2),
.i_3(im03_3),
.o_0(om03_0),
.o_1(om03_1),
.o_2(om03_2),
.o_3(om03_3)
);
mcm_4 m4_0(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im40_0),
.i_1(im40_1),
.i_2(im40_2),
.i_3(im40_3),
.m1_0(om40_0),
.m1_1(om40_1),
.m1_2(om40_2),
.m1_3(om40_3)
);
mcm_4 m4_1(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im41_0),
.i_1(im41_1),
.i_2(im41_2),
.i_3(im41_3),
.m1_0(om41_0),
.m1_1(om41_1),
.m1_2(om41_2),
.m1_3(om41_3)
);
mcm_4 m4_2(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im42_0),
.i_1(im42_1),
.i_2(im42_2),
.i_3(im42_3),
.m1_0(om42_0),
.m1_1(om42_1),
.m1_2(om42_2),
.m1_3(om42_3)
);
mcm_4 m4_3(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im43_0),
.i_1(im43_1),
.i_2(im43_2),
.i_3(im43_3),
.m1_0(om43_0),
.m1_1(om43_1),
.m1_2(om43_2),
.m1_3(om43_3)
);
mcm_8 m8_0(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im80_0),
.i_1(im80_1),
.i_2(im80_2),
.i_3(im80_3),
.i_4(im80_4),
.i_5(im80_5),
.i_6(im80_6),
.i_7(im80_7),
.m2_0(om80_0),
.m2_1(om80_1),
.m2_2(om80_2),
.m2_3(om80_3),
.m2_4(om80_4),
.m2_5(om80_5),
.m2_6(om80_6),
.m2_7(om80_7)
);
mcm_8 m8_1(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im81_0),
.i_1(im81_1),
.i_2(im81_2),
.i_3(im81_3),
.i_4(im81_4),
.i_5(im81_5),
.i_6(im81_6),
.i_7(im81_7),
.m2_0(om81_0),
.m2_1(om81_1),
.m2_2(om81_2),
.m2_3(om81_3),
.m2_4(om81_4),
.m2_5(om81_5),
.m2_6(om81_6),
.m2_7(om81_7)
);
mcm_16 m16_0(
.clk(clk),
.rst(rst),
.inverse(inverse),
.i_0(im160_0),
.i_1(im160_1),
.i_2(im160_2),
.i_3(im160_3),
.i_4(im160_4),
.i_5(im160_5),
.i_6(im160_6),
.i_7(im160_7),
.i_8(im160_8),
.i_9(im160_9),
.i_10(im160_10),
.i_11(im160_11),
.i_12(im160_12),
.i_13(im160_13),
.i_14(im160_14),
.i_15(im160_15),
.m3_0(om160_0),
.m3_1(om160_1),
.m3_2(om160_2),
.m3_3(om160_3),
.m3_4(om160_4),
.m3_5(om160_5),
.m3_6(om160_6),
.m3_7(om160_7),
.m3_8(om160_8),
.m3_9(om160_9),
.m3_10(om160_10),
.m3_11(om160_11),
.m3_12(om160_12),
.m3_13(om160_13),
.m3_14(om160_14),
.m3_15(om160_15)
);
endmodule |
/*
* This file is part of the DSLogic-hdl project.
*
* Copyright (C) 2014 DreamSourceLab <support@dreamsourcelab.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
`timescale 1ns/100ps
`define D #1
module mem_ctrl (
// -- Clock & Reset
input sdram_clk,
input sdram_rst_,
// -- dwrite
input wr_req,
output wr_valid,
input [31:0] wr_addr,
input [15:0] wr_data,
// -- dread
input rd_req,
output rd_valid,
input [31:0] rd_addr,
output rd_rdy,
output [15:0] rd_data,
output sd_init_done,
// -- SDRAM Signals
output [12:0] sdram_addr,
output [1:0] sdram_ba,
inout [15:0] sdram_dq,
output sdram_ras_,
output sdram_cas_,
output sdram_we_,
output sdram_dqml,
output sdram_dqmh,
output sdram_cke,
output sdram_cs_
);
// --
// internal signals definition
// --
wire [15:0] sdram_dqo;
wire [15:0] sdram_dqi;
wire [15:0] sdram_dq_oe;
wire STOP_CLK;
wire PAA;
wire SET_MODE;
wire [2:0] BLK_SIZE; // Burst Length
// 3'b000: 1, 3'b001: 2, 3'b010: 4, 3'b011: 8
// if IS_SEQ == 1'b0, 3'b111: full page
wire IS_SEQ; // Burst Type
// 1'b0: Sequential, 1'b1: Interleaved
wire MODULE_BK_NUM; // Not Used
wire [1:0] ROW_SIZE; // 2'b00 : A0-A10, 2'b01 : A0-A11, 2'b10 : A0-A12
wire [1:0] BIT_SIZE; // 2'b00 : 4, 2'b01 : 8, 2'b10 : 16, 2'b11 : 32
wire BK_SIZE; // 1'b0 : B0, 1'b1 : B0-B1
wire [2:0] COL_SIZE; // 3'b000: A0-A7 3'b001: A0-A8 3'b010: A0-A9
// 3'b011: A0-A9,A11 3'b100: A0-A9, A11, A12
wire [1:0] tRCD;
wire [1:0] tCAS;
wire [1:0] tRP;
wire [2:0] tRAS;
wire [11:0] tREF;
wire [3:0] tRC;
wire [31:0] sys_addr;
wire sys_rd;
wire sys_wr;
wire [15:0] sys_wdata;
wire [15:0] sys_rdata;
wire sys_rd_rdy;
wire sys_burst_rdy;
wire [12:0] isdram_addr;
wire [1:0] isdram_ba;
wire [15:0] isdram_dqi;
wire [15:0] isdram_dqo;
wire isdram_dq_oe;
wire isdram_ras_;
wire isdram_cas_;
wire isdram_we_;
wire isdram_dqm;
wire isdram_cke;
wire isdram_cs_;
assign sd_init_done = PAA;
// --
// dwrite/dread access mux
// --
assign sys_addr = wr_req ? wr_addr : rd_addr;
assign sys_rd = rd_req;
assign sys_wr = wr_req;
assign sys_wdata = wr_data;
assign rd_data = sys_rdata;
assign wr_valid = wr_req & sys_burst_rdy;
assign rd_valid = rd_req & sys_burst_rdy;
assign rd_rdy = sys_rd_rdy;
// --
// sdram_clk output
// --
assign sdram_dq[0] = sdram_dq_oe[0] ? sdram_dqo[0] : 1'Hz;
assign sdram_dq[1] = sdram_dq_oe[1] ? sdram_dqo[1] : 1'Hz;
assign sdram_dq[2] = sdram_dq_oe[2] ? sdram_dqo[2] : 1'Hz;
assign sdram_dq[3] = sdram_dq_oe[3] ? sdram_dqo[3] : 1'Hz;
assign sdram_dq[4] = sdram_dq_oe[4] ? sdram_dqo[4] : 1'Hz;
assign sdram_dq[5] = sdram_dq_oe[5] ? sdram_dqo[5] : 1'Hz;
assign sdram_dq[6] = sdram_dq_oe[6] ? sdram_dqo[6] : 1'Hz;
assign sdram_dq[7] = sdram_dq_oe[7] ? sdram_dqo[7] : 1'Hz;
assign sdram_dq[8] = sdram_dq_oe[8] ? sdram_dqo[8] : 1'Hz;
assign sdram_dq[9] = sdram_dq_oe[9] ? sdram_dqo[9] : 1'Hz;
assign sdram_dq[10] = sdram_dq_oe[10] ? sdram_dqo[10] : 1'Hz;
assign sdram_dq[11] = sdram_dq_oe[11] ? sdram_dqo[11] : 1'Hz;
assign sdram_dq[12] = sdram_dq_oe[12] ? sdram_dqo[12] : 1'Hz;
assign sdram_dq[13] = sdram_dq_oe[13] ? sdram_dqo[13] : 1'Hz;
assign sdram_dq[14] = sdram_dq_oe[14] ? sdram_dqo[14] : 1'Hz;
assign sdram_dq[15] = sdram_dq_oe[15] ? sdram_dqo[15] : 1'Hz;
assign sdram_dqi = sdram_dq;
// --
// sdram parameter
// --
assign STOP_CLK = 1'b0; // Never Stop Clock
assign BLK_SIZE = 3'b000; // Burst length = 8
assign IS_SEQ = 1'b0; // Sequential
assign MODULE_BK_NUM = 1'b1;
assign ROW_SIZE = 2'b10; // A0-A12
assign BIT_SIZE = 2'b10; // 16
assign BK_SIZE = 1'b1; // B0-B1
assign COL_SIZE = 3'b001; // A0-A8
assign tRCD = 2'b10; // tRCD - 1
assign tCAS = 2'b11;
assign tRP = 2'b11;
assign tRAS = 3'b110;
assign tREF = 12'd257;
assign tRC = 4'b1000;
// --
// instant
// --
sdram_init sdram_init_x(
.sdram_clk(sdram_clk), .sdram_rst_(sdram_rst_),
//.CKE_IN(CKE), .CKE_OUT(CKE_OUT),
.PAA(PAA), .SET_MODE(SET_MODE)
);
sdram_ctl sdram_ctl(
.CLK(sdram_clk), .RST_(sdram_rst_),
// REG interface
.STOP_CLK(STOP_CLK), .PAA(PAA), .SET_MODE(SET_MODE), .BLK_SIZE(BLK_SIZE), .IS_SEQ(IS_SEQ),
.MODULE_BK_NUM(MODULE_BK_NUM), .ROW_SIZE(ROW_SIZE), .COL_SIZE(COL_SIZE[1:0]), .BK_SIZE(BK_SIZE), .BIT_SIZE(BIT_SIZE),
.tRCD(tRCD), .tCAS(tCAS), .tRAS(tRAS), .tRP(tRP),
.tREF(tREF), .tRC(tRC), //note: tRC minus 1
// from/to host side
.ADDR(sys_addr), .RD(sys_rd), .WR(sys_wr), .DAT_I(sys_wdata), .DAT_O(sys_rdata),
.RD_DAT_RDY(sys_rd_rdy), .BURST_RDY(sys_burst_rdy), .RW(),
.CPU_GNT_(1'b0), .MUX_EN(),
// from/to DIMM
.CKE(isdram_cke), .CS_(isdram_cs_),
.RAS_(isdram_ras_), .CAS_(isdram_cas_), .WE_(isdram_we_), .DQM(isdram_dqm),
.BA(isdram_ba), .DIMM_ADDR(isdram_addr),
.DQ_I(isdram_dqi), .DQ_O(isdram_dqo), .DQ_OE(isdram_dq_oe)
// .CKE(sdram_cke), .CS_(sdram_cs_),
// .RAS_(sdram_ras_), .CAS_(sdram_cas_), .WE_(sdram_we_), .DQM(sdram_dqm),
// .BA(sdram_ba), .DIMM_ADDR(sdram_addr),
// .DQ_I(sdram_dqi), .DQ_O(sdram_dqo), .DQ_OE(sdram_dq_oe)
);
sdram_io sdram_io(
// -- Clock
.sdram_clk(sdram_clk),
// -- From/to Internal Signals
.sdram_addr(isdram_addr), .sdram_ba(isdram_ba), .sdram_dqo(isdram_dqo),
.sdram_dqi(isdram_dqi), .sdram_dq_oe(isdram_dq_oe), .sdram_ras_(isdram_ras_),
.sdram_cas_(isdram_cas_), .sdram_we_(isdram_we_), .sdram_dqm(isdram_dqm),
.sdram_cke(isdram_cke), .sdram_cs_(isdram_cs_),
// -- From/to SDRAM Signals
.pad_addr(sdram_addr), .pad_ba(sdram_ba), .pad_dqo(sdram_dqo),
.pad_dqi(sdram_dqi), .pad_dq_oe(sdram_dq_oe), .pad_ras_(sdram_ras_),
.pad_cas_(sdram_cas_), .pad_we_(sdram_we_), .pad_dqml(sdram_dqml), .pad_dqmh(sdram_dqmh),
.pad_cke(sdram_cke), .pad_cs_(sdram_cs_)
);
endmodule /* module mem_ctrl (*/
|
`timescale 1ns / 1ps
`include "../src/axis_scaler.v"
module test();
localparam RANDOMOUTPUT = 1;
localparam RANDOMINPUT = 1;
localparam integer C_REALDATA = 1;
localparam integer C_PIXEL_WIDTH = (C_REALDATA ? 8 : 16);
localparam integer C_SH_WIDTH = 12;
localparam integer C_SW_WIDTH = 12;
localparam integer C_MH_WIDTH = 12;
localparam integer C_MW_WIDTH = 12;
localparam integer C_CH0_WIDTH = 8;
localparam integer C_CH1_WIDTH = 0;
localparam integer C_CH2_WIDTH = 0;
/// 10ms / 5ns
localparam integer C_FSYNC_INTERVAL = 10 * 1000 * 1000 / 5;
wire[C_PIXEL_WIDTH-1:0] m_axis_tdata_tb ;
wire m_axis_tlast_tb ;
reg m_axis_tready_tb;
wire m_axis_tuser_tb ;
wire m_axis_tvalid_tb;
wire[C_PIXEL_WIDTH-1:0] s_axis_tdata_tb ;
wire s_axis_tlast_tb ;
wire s_axis_tready_tb;
wire s_axis_tuser_tb ;
reg s_axis_tvalid_tb;
reg[C_SH_WIDTH-1:0] s_height_tb = 10;
reg[C_SW_WIDTH-1:0] s_width_tb = 10;
reg resetn_tb;
reg[C_MH_WIDTH-1:0] m_height_tb = 240;
reg[C_MW_WIDTH-1:0] m_width_tb = 320;
integer fileR, picType, dataPosition, grayDepth;
reg[80*8:0] outputFileName;
reg[11:0] outputFileIdx = 0;
integer fileW = 0;
initial begin
if (C_REALDATA) begin
fileR=$fopen("a.pgm", "r");
$fscanf(fileR, "P%d\n%d %d\n%d\n", picType, s_width_tb, s_height_tb, grayDepth);
dataPosition=$ftell(fileR);
$display("header: %dx%d, %d", s_width_tb, s_height_tb, grayDepth);
m_height_tb = s_height_tb / 2;
m_width_tb = s_width_tb / 2;
$display("header: %dx%d, %d, %0dx%0d", s_width_tb, s_height_tb, grayDepth, m_width_tb, m_height_tb);
end
else begin
s_width_tb = 10;
s_height_tb = 10;
m_height_tb = 60;
m_width_tb = 60;
end
end
reg clk;
reg fsync_tb = 0;
initial begin
clk <= 1'b1;
forever #2.5 clk <= ~clk;
end
initial begin
m_axis_tready_tb <= 1'b0;
#0.2 m_axis_tready_tb <= 1'b1;
forever begin
#5 m_axis_tready_tb <= (RANDOMOUTPUT ? {$random}%2 : 1);
end
end
initial begin
resetn_tb <= 1'b0;
repeat (5) #5 resetn_tb <= 1'b0;
forever #5 resetn_tb <= 1'b1;
end
initial begin
fsync_tb <= 0;
repeat (10) #5 fsync_tb <= 0;
forever begin
repeat (1) #5 fsync_tb <= 1;
repeat (C_FSYNC_INTERVAL - 1) #5 fsync_tb <= 0;
end
end
reg[23:0] outcnt = 0;
reg[11:0] outline = 0;
////////////////////////////////////////////////////////////////////////// input
reg [C_SH_WIDTH-1:0] s_ridx;
reg [C_SW_WIDTH-1:0] s_cidx;
wire s_rlast;
wire s_clast;
assign s_rlast = (s_ridx == s_height_tb - 1);
assign s_clast = (s_cidx == s_width_tb - 1);
assign s_axis_tuser_tb = (s_ridx == 0 && s_cidx == 0);
assign s_axis_tlast_tb = (s_cidx == s_width_tb - 1);
always @ (posedge clk) begin
if (resetn_tb == 1'b0) begin
s_ridx <= 0;
s_cidx <= 0;
end
else if (s_axis_tvalid_tb && s_axis_tready_tb) begin
if (~s_clast) begin
s_cidx <= s_cidx + 1;
s_ridx <= s_ridx;
end
else if (~s_rlast) begin
s_cidx <= 0;
s_ridx <= s_ridx + 1;
end
else begin
s_cidx <= 0;
s_ridx <= 0;
end
end
end
////////////////////////// enable input ////////////////////////////////////////
reg frm_done;
wire en_input;
wire trans_frm_last;
assign trans_frm_last = (s_ridx == (s_height_tb - 1)
&& s_cidx == s_width_tb - 1
&& s_axis_tvalid_tb);
always @ (posedge clk) begin
if (resetn_tb == 0)
frm_done <= 1;
else if (trans_frm_last)
frm_done <= 1;
else if (fsync_tb)
frm_done <= 0;
end
reg randomresult;
always @ (posedge clk) begin
randomresult <= (RANDOMINPUT ? {$random}%2 : 1);
end
assign en_input = (~trans_frm_last && ~frm_done && randomresult);
always @ (posedge clk) begin
if (resetn_tb == 1'b0)
s_axis_tvalid_tb <= 1'b0;
else if (~s_axis_tvalid_tb || s_axis_tready_tb) begin
s_axis_tvalid_tb <= en_input;
end
end
generate
if (C_REALDATA) begin
reg [C_PIXEL_WIDTH-1:0] s_axis_tdata_tb_r ;
assign s_axis_tdata_tb = s_axis_tdata_tb_r;
always @ (posedge clk) begin
if (fsync_tb)
$fseek(fileR, dataPosition, 0);
end
always @ (posedge clk) begin
if (resetn_tb == 1'b0) begin
s_axis_tdata_tb_r <= 0;
end
else if ((~s_axis_tvalid_tb || s_axis_tready_tb)
&& en_input) begin
s_axis_tdata_tb_r <= $fgetc(fileR);
end
end
end
else begin
assign s_axis_tdata_tb = (s_ridx * 256 + s_cidx);
end
endgenerate
///////////////////////////////////////////////////// output
always @(posedge clk) begin
if (resetn_tb == 1'b0 || (outcnt >= m_height_tb * m_width_tb && m_axis_tready_tb)) begin
if (fileW == 0) begin
outputFileIdx <= outputFileIdx + 1;
$sformat(outputFileName, "output%0d.pgm", outputFileIdx);
fileW=$fopen(outputFileName, "w");
$display("outputFileName: %s - %0d", outputFileName, fileW);
$fwrite(fileW, "P%0d\n%0d %0d\n%0d\n", picType, m_width_tb, m_height_tb, grayDepth);
end
if (outcnt > 0) $display ("new output!");
outcnt <= 0;
outline <= 0;
end
else if (m_axis_tready_tb && m_axis_tvalid_tb) begin
//$display("output data to %s", outputFileName);
$fwrite(fileW, "%c", m_axis_tdata_tb);
if (m_axis_tuser_tb != (outcnt == 0)) begin
$display("error sof %t", $time);
end
if (m_axis_tlast_tb != ((outcnt+1) % m_width_tb == 0)) begin
$display("error eol %t", $time);
end
$write("%h ", m_axis_tdata_tb);
if (m_axis_tlast_tb) begin
$write(outline+1, " time: %t\n", $time);
outline <= outline + 1;
end
outcnt <= outcnt + 1;
if (outcnt == m_height_tb * m_width_tb - 1) begin
$fclose(fileW);
fileW = 0;
end
end
end
axis_scaler # (
.C_PIXEL_WIDTH(C_PIXEL_WIDTH),
.C_SH_WIDTH (C_SH_WIDTH ),
.C_SW_WIDTH (C_SW_WIDTH ),
.C_MH_WIDTH (C_MH_WIDTH ),
.C_MW_WIDTH (C_MW_WIDTH ),
.C_CH0_WIDTH (C_CH0_WIDTH ),
.C_CH1_WIDTH (C_CH1_WIDTH ),
.C_CH2_WIDTH (C_CH2_WIDTH )
) uut (
.m_axis_tdata(m_axis_tdata_tb),
.m_axis_tlast(m_axis_tlast_tb),
.m_axis_tready(m_axis_tready_tb),
.m_axis_tuser(m_axis_tuser_tb),
.m_axis_tvalid(m_axis_tvalid_tb),
.s_axis_tdata(s_axis_tdata_tb),
.s_axis_tlast(s_axis_tlast_tb),
.s_axis_tready(s_axis_tready_tb),
.s_axis_tuser(s_axis_tuser_tb),
.s_axis_tvalid(s_axis_tvalid_tb),
.clk(clk),
.resetn(resetn_tb),
.fsync(fsync_tb),
.s_height(s_height_tb),
.s_width(s_width_tb),
.m_height(m_height_tb),
.m_width(m_width_tb)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_BLACKBOX_V
`define SKY130_FD_SC_HVL__SCHMITTBUF_BLACKBOX_V
/**
* schmittbuf: Schmitt Trigger Buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__schmittbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SCHMITTBUF_BLACKBOX_V
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy (dave.mccoy@cospandesign.com)
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`include "pcie_defines.v"
`include "nysa_pcie_defines.v"
module pcie_ingress (
input clk,
input rst,
//AXI Stream Host 2 Device
output reg o_axi_ingress_ready,
input [31:0] i_axi_ingress_data,
input [3:0] i_axi_ingress_keep,
input i_axi_ingress_last,
input i_axi_ingress_valid,
//Parsed out control data
output reg [31:0] o_write_a_addr,
output reg [31:0] o_write_b_addr,
output reg [31:0] o_read_a_addr,
output reg [31:0] o_read_b_addr,
output reg [31:0] o_status_addr,
output reg [31:0] o_buffer_size,
output reg [31:0] o_ping_value,
output reg o_update_buf_stb,
output reg [1:0] o_update_buf,
output reg [31:0] o_dev_addr,
//Bar Hit
input [6:0] i_bar_hit,
input [31:0] i_control_addr_base,
output reg o_enable_config_read,
input i_finished_config_read,
//Ingress Data Path
output reg o_reg_write_stb,
//Commands
output reg o_cmd_rst_stb,
output reg o_cmd_wr_stb,
output reg o_cmd_rd_stb,
output reg o_cmd_ping_stb,
output reg o_cmd_rd_cfg_stb,
output reg o_cmd_unknown_stb,
output reg o_cmd_flg_fifo_stb,
output reg o_cmd_flg_sel_per_stb,
output reg o_cmd_flg_sel_mem_stb,
output reg o_cmd_flg_sel_dma_stb,
//Command Interface
output reg [31:0] o_cmd_data_count,
output reg [31:0] o_cmd_data_address,
//Flow Control
output reg o_cplt_pkt_stb,
output reg [9:0] o_cplt_pkt_cnt,
//Buffer Manager
//output reg [7:0] o_cplt_pkt_tag,
output [7:0] o_cplt_pkt_tag,
//output reg [6:0] o_cplt_pkt_lwr_addr,
output [6:0] o_cplt_pkt_lwr_addr,
//Buffer Interface
input [12:0] i_buf_offset,
output reg o_buf_we,
output reg [10:0] o_buf_addr,
output reg [31:0] o_buf_data,
output [3:0] o_state,
output reg [7:0] o_ingress_count,
output reg [7:0] o_ingress_ri_count,
output reg [7:0] o_ingress_ci_count,
output reg [31:0] o_ingress_addr,
output reg [31:0] o_ingress_cmplt_count,
output reg [2:0] o_cplt_sts,
output reg o_unknown_tlp_stb,
output reg o_unexpected_end_stb
);
//local parameters
localparam IDLE = 4'h0;
localparam READY = 4'h1;
localparam READ_HDR = 4'h2;
localparam WRITE_REG_CMD = 4'h3;
localparam READ_ADDR = 4'h4;
localparam READ_CMPLT = 4'h5;
localparam READ_CMPLT_DATA = 4'h6;
localparam GET_CMPLT_ADDR = 4'h7;
localparam SEND_DATA = 4'h8;
localparam READ_BAR_ADDR = 4'h9;
localparam FLUSH = 4'hA;
//Commands
localparam CMD_MEM_READ = 8'h00;
localparam CMD_MEM_READ_LOCK = 8'h01;
localparam CMD_MEM_WRITE = 8'h02;
localparam CMD_IO_READ = 8'h03;
localparam CMD_IO_WRITE = 8'h04;
localparam CMD_CONFIG_READD0 = 8'h05;
localparam CMD_CONFIG_WRITE0 = 8'h06;
localparam CMD_CONFIG_READ1 = 8'h07;
localparam CMD_CONFIG_WRITE1 = 8'h08;
localparam CMD_TCFGRD = 8'h09;
localparam CMD_TCFGWR = 8'h0A;
localparam CMD_MESSAGE = 8'h0B;
localparam CMD_MESSAGE_DATA = 8'h0C;
localparam CMD_COMPLETE = 8'h0D;
localparam CMD_COMPLETE_DATA = 8'h0E;
localparam CMD_COMPLETE_LOCK = 8'h0F;
localparam CMD_COMPLETE_DATA_LOCK = 8'h10;
localparam CMD_FETCH_ADD = 8'h11;
localparam CMD_SWAP = 8'h12;
localparam CMD_COMPARE_AND_SWAP = 8'h13;
localparam CMD_LPRF = 8'h14;
localparam CMD_EPRF = 8'h15;
localparam CMD_UNKNOWN = 8'h16;
//registes/wires
reg [3:0] state;
reg [23:0] r_data_count;
reg [3:0] r_hdr_index;
reg [31:0] r_hdr [0:3];
reg [2:0] r_hdr_size;
reg [7:0] r_hdr_cmd;
wire [9:0] w_pkt_data_size;
wire [31:0] w_pkt_addr;
wire [31:0] w_buf_pkt_addr_base;
wire [31:0] w_reg_addr;
wire w_cmd_en;
reg [31:0] r_buf_cnt;
wire [6:0] w_cmplt_lower_addr;
reg r_config_space_done;
wire [7:0] w_cplt_pkt_tag;
wire [6:0] w_cplt_pkt_lwr_addr;
wire [31:0] w_hdr0;
wire [31:0] w_hdr1;
wire [31:0] w_hdr2;
wire [31:0] w_hdr3;
assign w_hdr0 = r_hdr[0];
assign w_hdr1 = r_hdr[1];
assign w_hdr2 = r_hdr[2];
assign w_hdr3 = r_hdr[3];
assign o_state = state;
//submodules
//asynchronous logic
//Get Header Size
always @ (*) begin
case (r_hdr[0][`PCIE_FMT_RANGE])
`PCIE_FMT_3DW_NO_DATA: r_hdr_size = 3;
`PCIE_FMT_4DW_NO_DATA: r_hdr_size = 4;
`PCIE_FMT_3DW_DATA: r_hdr_size = 3;
`PCIE_FMT_4DW_DATA: r_hdr_size = 4;
default: r_hdr_size = 0;
endcase
end
always @ (*) begin
casex (r_hdr[0][`PCIE_TYPE_RANGE])
`PCIE_MRD: r_hdr_cmd = CMD_MEM_READ;
`PCIE_MRDLK: r_hdr_cmd = CMD_MEM_READ_LOCK;
`PCIE_MWR: r_hdr_cmd = CMD_MEM_WRITE;
`PCIE_IORD: r_hdr_cmd = CMD_IO_READ;
`PCIE_IOWR: r_hdr_cmd = CMD_IO_WRITE;
`PCIE_CFGRD0: r_hdr_cmd = CMD_CONFIG_READD0;
`PCIE_CFGWR0: r_hdr_cmd = CMD_CONFIG_WRITE0;
`PCIE_CFGRD1: r_hdr_cmd = CMD_CONFIG_READ1;
`PCIE_CFGWR1: r_hdr_cmd = CMD_CONFIG_WRITE1;
`PCIE_TCFGRD: r_hdr_cmd = CMD_TCFGRD;
`PCIE_TCFGWR: r_hdr_cmd = CMD_TCFGWR;
`PCIE_MSG: r_hdr_cmd = CMD_MESSAGE;
`PCIE_MSG_D: r_hdr_cmd = CMD_MESSAGE_DATA;
`PCIE_CPL: r_hdr_cmd = CMD_COMPLETE;
`PCIE_CPL_D: r_hdr_cmd = CMD_COMPLETE_DATA;
`PCIE_CPLLK: r_hdr_cmd = CMD_COMPLETE_LOCK;
`PCIE_CPLDLK: r_hdr_cmd = CMD_COMPLETE_DATA_LOCK;
`PCIE_FETCH_ADD: r_hdr_cmd = CMD_FETCH_ADD;
`PCIE_SWAP: r_hdr_cmd = CMD_SWAP;
`PCIE_CAS: r_hdr_cmd = CMD_COMPARE_AND_SWAP;
`PCIE_LPRF: r_hdr_cmd = CMD_LPRF;
`PCIE_EPRF: r_hdr_cmd = CMD_EPRF;
default: r_hdr_cmd = CMD_UNKNOWN;
endcase
end
assign w_pkt_data_size = r_hdr[0][`PCIE_DWORD_PKT_CNT_RANGE];
assign w_pkt_addr = {r_hdr[2][31:2], 2'b00};
assign w_cmplt_lower_addr = r_hdr[2][`CMPLT_LOWER_ADDR_RANGE];
assign w_reg_addr = (i_control_addr_base >= 0) ? ((w_pkt_addr - i_control_addr_base) >> 2): 32'h00;
assign w_cmd_en = (w_reg_addr >= `CMD_OFFSET);
//assign w_buf_pkt_addr_base = i_buf_offset - (w_pkt_addr + w_cmplt_lower_addr);
//assign w_buf_pkt_addr_base = i_buf_offset - w_cmplt_lower_addr;
assign w_buf_pkt_addr_base = i_buf_offset;
assign w_cplt_pkt_tag = (r_hdr_cmd == CMD_COMPLETE_DATA) ? r_hdr[2][15:8] : 8'h00;
//assign o_cplt_pkt_byte_count = (r_hdr_cmd == CMD_COMPLETE_DATA) ? r_hdr[1][11:0] : 12'h00;
assign w_cplt_pkt_lwr_addr = (r_hdr_cmd == CMD_COMPLETE_DATA) ? r_hdr[2][6:0] : 7'h0;
assign w_cplt_sts = r_hdr[1][15:13];
assign o_cplt_pkt_tag = w_cplt_pkt_tag;
assign o_cplt_pkt_lwr_addr = w_cplt_pkt_lwr_addr;
integer i;
//synchronous logic
always @ (posedge clk) begin
o_reg_write_stb <= 0;
o_buf_we <= 0;
o_cmd_rst_stb <= 0;
o_cmd_wr_stb <= 0;
o_cmd_rd_stb <= 0;
o_cmd_ping_stb <= 0;
o_cmd_rd_cfg_stb <= 0;
o_cmd_unknown_stb <= 0;
o_cmd_flg_fifo_stb <= 0;
o_cmd_flg_sel_per_stb <= 0;
o_cmd_flg_sel_mem_stb <= 0;
o_cmd_flg_sel_dma_stb <= 0;
o_update_buf_stb <= 0;
o_cplt_pkt_stb <= 0;
o_unknown_tlp_stb <= 0;
o_unexpected_end_stb <= 0;
if (rst) begin
state <= IDLE;
//Registers
o_write_a_addr <= 0;
o_write_b_addr <= 0;
o_read_a_addr <= 0;
o_read_b_addr <= 0;
o_status_addr <= 0;
o_update_buf <= 0;
o_ping_value <= 0;
o_buffer_size <= 0;
o_dev_addr <= 0;
//Command Registers
o_cmd_data_count <= 0;
o_cmd_data_address <= 0;
//Counts
r_data_count <= 0;
r_hdr_index <= 0;
//Buffer Interface
r_buf_cnt <= 0;
o_buf_addr <= 0;
o_buf_data <= 0;
o_axi_ingress_ready <= 0;
o_enable_config_read <= 0;
r_config_space_done <= 0;
o_ingress_count <= 0;
o_ingress_ri_count <= 0;
o_ingress_ci_count <= 0;
o_ingress_cmplt_count <= 0;
o_ingress_addr <= 0;
//o_cplt_pkt_tag <= 0;
//o_cplt_pkt_lwr_addr <= 0;
//Complete
o_cplt_pkt_cnt <= 0;
o_cplt_sts <= 0;
for (i = 0; i < 4; i = i + 1) begin
r_hdr[i] <= 0;
end
end
else begin
case (state)
IDLE: begin
r_buf_cnt <= 0;
o_buf_addr <= 0;
r_data_count <= 0;
r_hdr_index <= 0;
o_enable_config_read <= 0;
if (i_axi_ingress_valid) begin
if (!r_config_space_done && (i_bar_hit != 0)) begin
state <= READ_BAR_ADDR;
end
else begin
//This is a config register or a new command
state <= READY;
end
end
end
READY: begin
o_ingress_count <= o_ingress_count + 1;
o_axi_ingress_ready <= 1;
//r_hdr[r_hdr_index] <= i_axi_ingress_data;
//r_hdr_index <= r_hdr_index + 1;
state <= READ_HDR;
end
READ_HDR: begin
r_hdr[r_hdr_index] <= i_axi_ingress_data;
r_hdr_index <= r_hdr_index + 1;
if (r_hdr_index + 1 >= r_hdr_size) begin
case (r_hdr_cmd)
CMD_MEM_WRITE: begin
state <= WRITE_REG_CMD;
end
CMD_COMPLETE: begin
state <= READ_CMPLT;
end
CMD_COMPLETE_DATA: begin
o_cplt_pkt_cnt <= w_pkt_data_size;
state <= READ_CMPLT_DATA;
end
default: begin
o_unknown_tlp_stb <= 1;
state <= FLUSH;
end
endcase
end
end
WRITE_REG_CMD: begin
o_ingress_addr <= w_reg_addr;
if (w_cmd_en) begin
o_update_buf <= 2'b00;
//o_update_buf_stb <= 1;
o_cmd_data_count <= i_axi_ingress_data;
o_cmd_flg_sel_per_stb <= 0;
o_cmd_flg_sel_mem_stb <= 0;
o_cmd_flg_sel_dma_stb <= 0;
case (w_reg_addr)
`PCIE_COMMAND_RESET: begin
r_config_space_done <= 0;
o_cmd_rst_stb <= 1;
end
`PERIPHERAL_WRITE: begin
o_ingress_cmplt_count <= 0;
o_cplt_sts <= 0;
o_cmd_flg_sel_per_stb <= 1;
o_cmd_wr_stb <= 1;
end
`PERIPHERAL_WRITE_FIFO: begin
o_cmd_flg_sel_per_stb <= 1;
o_cmd_wr_stb <= 1;
o_cmd_flg_fifo_stb <= 1;
end
`PERIPHERAL_READ: begin
o_cmd_flg_sel_per_stb <= 1;
o_cmd_rd_stb <= 1;
end
`PERIPHERAL_READ_FIFO: begin
o_cmd_flg_sel_per_stb <= 1;
o_cmd_rd_stb <= 1;
o_cmd_flg_fifo_stb <= 1;
end
`MEMORY_WRITE: begin
o_cmd_flg_sel_mem_stb <= 1;
o_cmd_wr_stb <= 1;
end
`MEMORY_READ: begin
o_cmd_flg_sel_mem_stb <= 1;
o_cmd_rd_stb <= 1;
end
`DMA_WRITE: begin
o_cmd_flg_sel_dma_stb <= 1;
o_cmd_wr_stb <= 1;
end
`DMA_READ: begin
o_cmd_flg_sel_dma_stb <= 1;
o_cmd_rd_stb <= 1;
end
`PING: begin
o_cmd_ping_stb <= 1;
o_ping_value <= i_axi_ingress_data;
end
`READ_CONFIG: begin
o_cmd_rd_cfg_stb <= 1;
end
default: begin
o_cmd_unknown_stb <= 1;
o_ingress_ci_count <= o_ingress_ci_count + 1;
end
endcase
end
else begin
case (w_reg_addr)
`HDR_STATUS_BUF_ADDR: begin
o_status_addr <= i_axi_ingress_data;
end
`HDR_BUFFER_READY: begin
o_update_buf <= i_axi_ingress_data[1:0];
o_update_buf_stb <= 1;
end
`HDR_AUX_BUFFER_READY: begin
o_update_buf <= i_axi_ingress_data[1:0];
o_update_buf_stb <= 1;
end
`HDR_WRITE_BUF_A_ADDR: begin
o_write_a_addr <= i_axi_ingress_data;
end
`HDR_WRITE_BUF_B_ADDR: begin
o_write_b_addr <= i_axi_ingress_data;
end
`HDR_READ_BUF_A_ADDR: begin
o_read_a_addr <= i_axi_ingress_data;
end
`HDR_READ_BUF_B_ADDR: begin
o_read_b_addr <= i_axi_ingress_data;
end
`HDR_BUFFER_SIZE: begin
o_buffer_size <= i_axi_ingress_data;
end
`HDR_DEV_ADDR: begin
o_dev_addr <= i_axi_ingress_data;
o_cmd_data_address <= i_axi_ingress_data;
end
default: begin
o_ingress_ri_count <= o_ingress_ri_count + 1;
end
endcase
o_reg_write_stb <= 1;
end
state <= FLUSH;
end
READ_ADDR: begin
o_cmd_data_address <= i_axi_ingress_data;
state <= FLUSH;
end
READ_CMPLT: begin
if (w_cplt_sts != 0) begin
o_cplt_sts <= w_cplt_sts;
end
state <= FLUSH;
end
READ_CMPLT_DATA: begin
o_buf_addr <= w_buf_pkt_addr_base;
if (w_cplt_sts != 0) begin
o_cplt_sts <= w_cplt_sts;
end
o_buf_we <= 1;
o_buf_data <= i_axi_ingress_data;
r_buf_cnt <= r_buf_cnt + 1;
o_ingress_cmplt_count <= o_ingress_cmplt_count + 1;
//o_cplt_pkt_tag <= w_cplt_pkt_tag;
//o_cplt_pkt_lwr_addr <= w_cplt_pkt_lwr_addr;
//state <= GET_CMPLT_ADDR;
state <= SEND_DATA;
end
GET_CMPLT_ADDR: begin
state <= SEND_DATA;
end
SEND_DATA: begin
//The Buffer is available
if (r_buf_cnt < w_pkt_data_size) begin
//o_buf_addr <= w_buf_pkt_addr_base + r_buf_cnt;
o_buf_addr <= o_buf_addr + 1;
r_buf_cnt <= r_buf_cnt + 1;
o_buf_data <= i_axi_ingress_data;
o_buf_we <= 1;
end
else begin
o_cplt_pkt_stb <= 1;
state <= FLUSH;
end
//Sort of an out of band signal... but need to see if this is a problem
if ((r_buf_cnt < w_pkt_data_size) && !o_axi_ingress_ready) begin
o_unexpected_end_stb <= 1;
state <= IDLE;
end
end
FLUSH: begin
if (!o_axi_ingress_ready) begin
state <= IDLE;
end
if (!i_axi_ingress_valid) begin
o_axi_ingress_ready <= 0;
end
end
READ_BAR_ADDR: begin
o_enable_config_read <= 1;
if (i_finished_config_read) begin
r_config_space_done <= 1;
o_enable_config_read <= 0;
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
//if (i_axi_ingress_last) begin
// o_axi_ingress_ready <= 0;
//end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 14:28:13 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mul8_16_sim_netlist.v
// Design : mul8_16
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "mul8_16,mult_gen_v12_0_12,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(CLK,
A,
B,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
(* x_interface_info = "xilinx.com:signal:data:1.0 a_intf DATA" *) input [7:0]A;
(* x_interface_info = "xilinx.com:signal:data:1.0 b_intf DATA" *) input [15:0]B;
(* x_interface_info = "xilinx.com:signal:data:1.0 p_intf DATA" *) output [15:0]P;
wire [7:0]A;
wire [15:0]B;
wire CLK;
wire [15:0]P;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "8" *)
(* C_B_TYPE = "0" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "16" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "8" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintexu" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12 U0
(.A(A),
.B(B),
.CE(1'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* C_A_TYPE = "1" *) (* C_A_WIDTH = "8" *) (* C_B_TYPE = "0" *)
(* C_B_VALUE = "10000001" *) (* C_B_WIDTH = "16" *) (* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_HAS_CE = "0" *) (* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_LATENCY = "3" *) (* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *) (* C_OPTIMIZE_GOAL = "1" *) (* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "8" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *) (* C_XDEVICEFAMILY = "kintexu" *) (* downgradeipidentifiedwarnings = "yes" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [7:0]A;
input [15:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [15:0]P;
output [47:0]PCASC;
wire \<const0> ;
wire [7:0]A;
wire [15:0]B;
wire CLK;
wire [15:0]P;
wire [47:0]NLW_i_mult_PCASC_UNCONNECTED;
wire [1:0]NLW_i_mult_ZERO_DETECT_UNCONNECTED;
assign PCASC[47] = \<const0> ;
assign PCASC[46] = \<const0> ;
assign PCASC[45] = \<const0> ;
assign PCASC[44] = \<const0> ;
assign PCASC[43] = \<const0> ;
assign PCASC[42] = \<const0> ;
assign PCASC[41] = \<const0> ;
assign PCASC[40] = \<const0> ;
assign PCASC[39] = \<const0> ;
assign PCASC[38] = \<const0> ;
assign PCASC[37] = \<const0> ;
assign PCASC[36] = \<const0> ;
assign PCASC[35] = \<const0> ;
assign PCASC[34] = \<const0> ;
assign PCASC[33] = \<const0> ;
assign PCASC[32] = \<const0> ;
assign PCASC[31] = \<const0> ;
assign PCASC[30] = \<const0> ;
assign PCASC[29] = \<const0> ;
assign PCASC[28] = \<const0> ;
assign PCASC[27] = \<const0> ;
assign PCASC[26] = \<const0> ;
assign PCASC[25] = \<const0> ;
assign PCASC[24] = \<const0> ;
assign PCASC[23] = \<const0> ;
assign PCASC[22] = \<const0> ;
assign PCASC[21] = \<const0> ;
assign PCASC[20] = \<const0> ;
assign PCASC[19] = \<const0> ;
assign PCASC[18] = \<const0> ;
assign PCASC[17] = \<const0> ;
assign PCASC[16] = \<const0> ;
assign PCASC[15] = \<const0> ;
assign PCASC[14] = \<const0> ;
assign PCASC[13] = \<const0> ;
assign PCASC[12] = \<const0> ;
assign PCASC[11] = \<const0> ;
assign PCASC[10] = \<const0> ;
assign PCASC[9] = \<const0> ;
assign PCASC[8] = \<const0> ;
assign PCASC[7] = \<const0> ;
assign PCASC[6] = \<const0> ;
assign PCASC[5] = \<const0> ;
assign PCASC[4] = \<const0> ;
assign PCASC[3] = \<const0> ;
assign PCASC[2] = \<const0> ;
assign PCASC[1] = \<const0> ;
assign PCASC[0] = \<const0> ;
assign ZERO_DETECT[1] = \<const0> ;
assign ZERO_DETECT[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "8" *)
(* C_B_TYPE = "0" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "16" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "23" *)
(* C_OUT_LOW = "8" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintexu" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mult_gen_v12_0_12_viv i_mult
(.A(A),
.B(B),
.CE(1'b0),
.CLK(CLK),
.P(P),
.PCASC(NLW_i_mult_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_i_mult_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64)
`pragma protect key_block
fPF16TcpNgM9dNC6nyb4WjUK+7bY8P+I62AEEiiM/KOMhIKuPOHBoWeWL2UjxSNO68WLeYIZp8lA
I7rHN/CieA==
`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
E6OKJxjnDRUVVFwAhrQMAtoyRVVpuMKsXlca4m9CcIt6QI8vnYN0tf7gH3uVuxZ90322B7kUeFw5
Pu0UeqAoBaSyysHuDqXazxHy7oyk4BIWChvcrp7LULlVLcL76obtSwsXi1ORVmpdTi5b+AcD+WUo
OP1PSFj5jpodG+LwXm4=
`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
x+agogSsgbiI6PGyBpMY8RQCDzLctIr3EaG23mH5kJHlNmNKNolnP54yJ8Y7nIFi6yl6tlyOLMoF
/kxU0pyFmIj8QM0/MArMxPTiemXbDLS2VKtonyK9dDH7VbjFnRWwzK0Ngkas0+nbW3TqGPAY98x3
251QPjQoZCw3A7W9PDc=
`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
KNs7hA49BKKrboRSEkqIGldOa3ndCnhjRkSn8lL1xFfKUn+p+Wbc09ogKV6YYnPU/RaF1LbzyoE4
udPSNea4bST+08IjO5GAxXqUugcig44J+hzpGKmh7oO0TuyNbYq1CnYcsZXaD9vsmNYz8fBDoW2S
VK/mYa21mBKTOuTdQ1yp3wi73aJ1G9N6Ngt7ovDUrjyd5oNxxNlvWU8JkJDinbEnci0qjZ3Wu9Wg
y44pHUXf6xqwFYJpZ1ZcGRKl83P8p74+pLzt19lw9TPlTfKI++IowVjb6wo36ztNDJS0QjQE5Riv
hwbPU/Bt3S82MVCY5NAA6bKC/8NnoWMbmX8Wiw==
`pragma protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
QaRubtGbYrmCghuFdQuTgTEtoVYYLcPnD5z0C7mo18fwCG17qy0y8mj8xWiwE6bo49IP1/JXSIw7
rTBwHFOVrmbm926sWNrF1r3IHB83C5cstprQ1om7vnkw9XX87SjkscphhkrHmi08jjzW4qX96m61
/ymclz5TlAocMQJGz/jwscvIMOrrbuH4SkWQOLQnRfx9GIOv5Y7PM+w/wuDSeFXsAXz7Ahq3/qmU
cylNfSufW7/zfN4RZB4u+d28AXsuFe03aSF1dpW+uBK1xtNZccvj9h9NMN0cuwxt8ZUlLJw8l6e2
hqRfTTZl1F4qnnrJu6w8h8uEGrmgnQG1AW0epg==
`pragma protect key_keyowner="Xilinx", key_keyname="xilinx_2016_05", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
XXj6Nc59BeA5Kznlx14IKravf7ohERw7h0fbO7pT7/HsiPDCWh2DlTGpFUcnbNZslPN2RfE0nJNX
WMzLQtaHK4Bm6kxY71OsXEKm7MAIjEdLwOMtJTtlZrbm7chBbSxcW6sjWvI36jk5De3Yct9Ao1py
DpQ9NICUtRTwGG8SAiRkAXRh2Jv3rKvnookQrlVxIkNRSBMSgbwuTbq1ze/KMUZebBWwJNUVIC9r
RV/i9wjYXBOeCCUk+cGDC5uSpwdLXYV9ZxhQUU6C1ufAaK2m4OIUeBqPc2ski2O0qQYQ67c35k50
ynO8H9PTEROPEOn5c37S7feU+36OcOOAsVBTBA==
`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`pragma protect encoding = (enctype="base64", line_length=76, bytes=256)
`pragma protect key_block
bm6MtD3HcAdFXHkDUZC6bckYOnzqNC/yHMgCWJcxRrqmVjeJt9tnMjEZtQIoB1Zq7VfnT8Y0f7RR
n0uBIdVXBxW6Y5rIVoXb8kq4xR/XM3NERPWUDI0/YAPPeGCTHc4KBycqSSANzNAKMhF5/pBn4OlV
JLZUPpFqtLNN2xoR21EDR2mep2PtN9YfybuUtWffT1PiGr6zBBzNe8TMG1UiOHMh/dX4LWmqXXah
zPoH7a+a+ta0p6776z+9ha7L/aS2hplxV+JRBce0z2NCk0nke9zeHN/9dLs40uNBtvBIF9rDiG1o
8ApPLWtExfhAJ/pO+imEXgRG5Id1bPf+ipRrgg==
`pragma protect key_keyowner="Synplicity", key_keyname="SYNP05_001", key_method="rsa"
`pragma protect encoding = (enctype="base64", line_length=76, bytes=256)
`pragma protect key_block
kdHlWuvDdlTgBWbNhy91uGSrqxmi9lipkiIWu9ONL/bJcwSs0rBMOW40RQi8X2OVqVeH/8o02ncs
uwTYumYpSY8fqDE0sZiC5JMRN0pdStVWmvx3aVs06GxgQJCDfXtDY+PhxFsaLg4XJ7HhOWcDBROF
0MbzlLovngTjRg8MGfcJBgV0IvAR8BrkW8Um8xVm6QHcPt5Uwrb0m43yJWIm7jgT2uk76JvznP8z
HJ+RVk7nnKL76832Yk+BTDmIFLkWCt3W9b54H2Le65HZeCSNFKeJwROp6r0jxu8i6/veY44T6X2c
bXgtEbMQOZddCN0XH3UNMMD6ec9FH57mdL0MqQ==
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 153312)
`pragma protect data_block
EwCT3Cr+wp/qrkeNP4uw2AnUfxSnj72/YDI6oyUuYBkAX800c/PDkNFXZbQ55l0PbFFoq8IO3/iO
CxQJnUT4o108xqXnmFbARXPEQxd5MEcVacmtv5htaOvHFOBEwOnjGU6VcE3YWH8JIW15Pr6331dy
0SkH/pj6D9ZG7ZU7n+3V/h5im1ZleOeGeaAQS7CV3ijIpccOipzK3T15W4+faYEy2ZWpsQEhzTU3
7dUMHg/Oh+Zgg9pOfAP+3kPdgNsv7jNX/Omh0ran3i+O8Rfczy8FvRjudRMw4TV3X9jbriEo38ye
BB5XG1fzULjXVxeqzAcafkl2nnHPf2xpAWWwwwmHXh/wQC/mzjrvsb5Lo8QS54lOIIfsKCmwW1C6
Oa7OppX0Ken2bjzS47pBfIFTnnIw5OCt4e6ChllTJHlfLKXK5k0FvkvI0aztI82bazzmXGqfHhbS
fV73zQQtZzjUxwdyJt6K1iyZl6eL4aP1gUHELogyXy3JcH2bue+qkFkoUrfbPOvyzeWNMD+EPVYt
tiDkiYDc2pUnU/nIA+qOYD5giOuX8imXUU0EzITbR2zL7ZE/OZSwkjrx4r6oIiarsnhF3/zXGGkx
54LPXRD/glKL3FTpLSkIiw8p23Lv/36NSDtH5Zf9ud+C8t6Pj3A0Zv9g+LLEt9kAF0W1ESUUFO4w
aDTBzL3xl3c7SdMbOq+pUZYwpTgJkUmv0PJJBUTw76VO0qQb7bbmrGnQ6MWxvjAo2ONdiGWadXtB
OYMhDV6f5FA1RKqE1j7Q+UC2Ot9cEoE6EAxYEkuPk+ShAVN7eM6MazxS6evZH05K3Cml1cuouJkZ
lA1gP9kWHpw9e/Tf725gahk3lhjOe2Zfsaws91Ee0F8XGJe2u17swV14cg0Nz5nvaMUJE1lc+TqT
Xf+/6EDj911DxeX6PNTJWmOJUU17Tg/KcstGe4P9I1KhT9M+dEXYT2UaNdOi9fq6Ki6hzIN4MiNu
qa1m0A2umOD/BeeHHT3clKnilcoeoW/Qg35i2ygL6Ti2N2P0ZDvlueIKy+0z0oVBLeENNkrqypL7
hppArt06Q/UUfiltpw8knVmNS0i1BY06peTyxMRTbxHvpayn59t7yrHk1V1S5kV0ewYAsenDOYYW
oTf74DqS7nBX0OI22O0/OCc/4O8DUOfnLLkbXufhCZ6mpC/I0bYNs3coRlIqR/4MZ33bE/azk4C6
LeIXk0tPxbtfj+jZkswQJVGGZ6Dnt4zPJkO9RJpVX5OCaulQZpK4jjmyJ1xW7Ar6aHut0GnILdxX
VWBGCnrDuR+GFwZIQhBpP14vEH6BZCc4DUPmPwa30kFo5RlFbc5C2UmbyAmECL39Zgnbl5fhn3B3
rKVRMBKvNHS6YeELIT1zsGfOfvdiQA43TNBmKbr7ENolPewgdGgtiXRA/bRaVnR29WjThSgbcXjB
sVdVCWoAnzn7pXLWWpaorhPDrR3mzxiAa4IG/CWPpvgzpHWmReE/QvyP7vykSQ1bozqevppokT9D
GveICLcLRT17Lkl73U4RE6rG58Qfj3iui3Vmi9k7cPN4roR7Q/rseDM0CdDoBp+03IfrcDOYQXIu
5+DYojIIwvNrWmrJDv6ErFSzc5QM9wPyk2wG1Vi3biKIdhosZspMku1neVpPB4jbIkOGyACd/I8q
3twLSqfjh+6Tw1oUnvXCwu+xyx+eUsfL9iTCTw9QQo/8M5OQCJ4ZHyxRttjZw9p1VFQ0vD4QW7pR
QhWS5lLaYyvcf1VREWKETG1Jfldu0FMPq9iuPiANBdq2EALUEhA1dVr3M+Oh9xe2QZje44lSdr/K
/NphFCvXMZAxUpd9/l936Ku9hQSZ8Vm0Gm1LJVuzWSzRcLys//tFrLxiXBLqYjbYfdSJiWq8d/p1
dZOovAGqahnHqeihxc1E+WpMJXaqvK1vIAkbfITiWWEwX/gHc3JLysC8eLqbWC9CpBgmMwgyZpgH
D0JXVsb1/U2U8uRs0BiXqpg/0b6NQieBMTuxzd5oXVICVdaT4DA6/J4zBbdvaKsSF6go4CP2YyMY
0kTjuCv65yXcrPuiCkc61gJCzVaqzT7Eqq1zwrfQusa34wnN+FMCfNwih3SfxhEVZlDhU/34hHn2
WQeu1A+pigBn3zSJpC62lrGZfoQUKfgNR0FGEsC1NnHpxEKrq4zgTrW8BzsRSQzTQ2U4ZTkkXAmk
rPf8WWiKrw/5MCILD6i62/IPFCUDwX0w8v97CP5KjIcLXoj5dGPmAejmRRMjAmIguYW2IPcG8Y68
6hV5PO5fPU7vIQjwYwegZmblNX1AeuWIS497wHWkteIGQdvEwAHNsgGzpz0CpnqitonD7Due0X8O
DqlwXLGzAf/oytKwjCirNpy1mtIyhmbQbd/LXNXf2Vy9MB0/8ls41XSZlzDXsY4J/Gc4dky2iir9
zmHMeZZkJTTvWG62sA8v2HwbHHCxugi7oQXOBH2u+vVNt5Hjbe38tUFHjp82FX96hoA7nibyAzdC
Y+D0SPpd7ENrR1MgbiCC+3hdHywvwXyBK+82a2LlVjLd1/x+FzOqSycq6VgwQf2/OwmSy/or1BsF
q4O/+mmVoBofbAF3bKsJmRqlFsrBEMxXXmfUxMPqZxidjZGGH+zmlNToFgsVL3UFewUZX+C0s41R
kFGkm9nx9hNZWJyrAKN6iWV02+TMSgdlHiTNTbXPUrtJX3Z/MYm1KCEISEAWYecAB3VzqjxE5Pqt
62lh+eKJa8wb1Vkd4CLFIMJECl2ZwfnUwI6qDj6HyAu7XnrSxt/uhor3VaMmtq3zotGO+kc+EDw+
C1a/bN9bCph/FzOgejmaUn+Kptc83IQDekhszGlFa9OKCOwtw8lq8tnNskKL9h4+YFDl6iC7h8tU
xQW46gxCrCGfvf+fkxUv0J3b1qTRkV0LPo9LTRHxIibsZohKT8nPlEE+b6rMvnRA9psZe5pavzim
vP8Da5gWEXVeg5YOsSgVFEhce2q5Ib566+XLdZ9RMN8tWXsXZRCaDBZFyiBAIMiyUrE4hE98GWHc
pCEtwxNB3AEqNt1LQLd3XSpHxqPXJ6elbYr2bNRe9KM0E1kwcauNmJ/2L55SA4gt0VpL2vbbKKbI
ZrBJ8UXnb3o+s2T4CFfhgoxBM7G+B//BfsF91KGWw/Bz46m8JEybOyolRrqIE/RlvMatR2D15hwK
iomQ9bISykzia7Y8fugSjylmcb2Ol0mxNuuqEA3gDxgKaDhpbUDJlkhyyLNQPJQAMJM2US7YUNSn
OtaVRNk1iie75DULTZhhzGKskp9PJ2ONV4ofE8yL9cgwvwKBlNz3v7+/S7jo5mmucIDZl2hotV4y
x9P/rcZO5bfev5OV7JwzhqaZZcjt5PiVd8c2WKUlqSu5++uC+6ulwx3c2hVag6Z14VGQug2Gg+cG
rWZo+b/BkMWnM+kv8VoHcTxxWLCs7gEOVgJPLkoQssYfMSRrcxM4jGXFDX57y5PpxANsRw4a9OJu
cpUluzkY8QsrtcKNnLtGeDzJVMh6IqOkKlA6PFNqgQoauQBpRjH8MR1oM/4tvsERw1JWAn5PuYQk
IibW5jkrI9oJof90jgbnuhtoEFW/cNdVGkVIbrT0Ue1R273PeiguDdCwMvqbaFC/eOO3HZS0/nYo
045vNPnFlR7B+RV0qBF0zTtd9R4GqKqbFtwLtQIv10MmpE4ZgMq7KNXmTLdbCKr7a5Y9ALOOGqi1
ll5BHuoAmjctzD2HD8vK8iyHmrkuGq8Ek4/+Jwym+URpgXDpDK1g1d/t42cNw9plFY8ljTvrPe5T
Yrf2YLxFpEYu1wWMgkBdw2Tc1piRFNaRoFG64WsAscfe3JugoYYVoqEk6sqY4NP47tFbFLvNfsuM
Cbk9QrX5qtXpxNgcHZEzcmHOgoTkM6aw5Y0I76B+tJYhsERNdzHCnci1+F8CnL6gFEogpea/J0+E
XbMcYdTFYbzWZilqWGJGIqtGSx83VwYwrIbcBCwzOzHO14Y3izv/JHFY0rXifKSW6wbXinWjw3sF
3gVrpZt/hzfFqTe8+WZlCmwfFrIOS480+3aTkMGuJXS1ilhLeK3pOWo1WTPvAU7JjoGA63fABdoc
vhUYfzdfreoDvyixruARmwErpZtTIRi8tgaDVISM9mLjJq3JiVGAO5L+N1Bpmq8Z8lutVQ+G9bHG
W20Li3/TLoexYI8wOOIQNfQ2LcC3C0UvaUiacX5D4tufQEkLfyiu5Y2UoYWefpVO4bMIijIySVO6
XmFbienrMo8Z1mgNXrlmUVUdzIPyUvCseITPz+NIdmn2/NHmsJrrCYzB1zxEkeJ5lwLMvDw4sAzS
Z5eJaewH8HV403ReJkuqtUGG5lPr8nywpJFU6f/q5gzR4osHG1CjYy5qqbEszlENsdWlz27x6686
8Quywe70awLjG/0uQ6+f+GUQ3G+DynnHbbkuFVpfOHIV6Ka7zv2oMRo+6eZJwvx4F7FJ0W/DxTgU
YmiNqrCB5uYjCJAPEAutpwVlCLI14AB1wXw+eQgW9khsukM3I6SN3F6GSSvjIW+hYAB4Vg9ps3gt
OStpiJycFMqD2w/YfqFv04t6m+0e0d3bRnkW73GBIkKEbZn6WmIvytj3jutEewy0+vsl5Lc5iHOm
L5qlJPAyf2dD28uxeJTko3nnIk2eA1Vm8N+Vt8gr+As+yVA+lmWP3c5SWMuDXh6AK+eu5NFcGtLr
u7hTaDsy7MfasDkCniHXO2B9thrkP0KiNTiHQPghgGg1e8NOAy+/FqNpnLOE1KlF0/Al1+KY4CHo
+6eDEJudtrBrqrAhJTz59cKE44G4cvLwu9Bc8AdRtDX1lkGX7JFUrNk6Rf0cwF+ZSDgQlbfsEYF5
ALXgq342fLwYBswKjZdpDBYpB5E0LHHoku+OcBCVSkfXDntDNzBWBa0kmdxa3o1ONEv7QcXQWnyO
Sy0F226vZalh+o2mwHpu0y+nIs7G7qyUL6EO9gB2wrRD7Br3nLAmjrAnwWiL1cVlO/b94b1d6Q81
kKyLY37vDKxn1MQ3q+a4NjEwKGwsUO7YZ03zBC0bNvHD7aUcQzu2y+7/2PIb+824mNXXggakszwv
Z6N5HeAK/5P/kvW+VW6LteUXZZeXH81adKgcxKlV8ZlA9HS/qMTp/OyEa7L95LC4d5HM4JlWMdo1
YegEpCvsfV5MN346WuAlAgnnZBGICjiITIDXKvRaoa99lkOX5s2dku6eXsTBxtHNo+a5U/fjYg/N
/73zjqhkQNAxSfa8OGC9hJDubM3WothYGj5d+Ui9fMqjraYUqXsJ9W4wpISIkeJVjrt6YdbuD63/
PYBvitlHeMl9msXi9dTrC1drV2N4Et8TmxzZQdBbmfVvdSEmZB02Y341rvWzMt8TIr91mHBlPwEH
NFtbLJ8d54g6bi8rZuu6dzsiKW9Z61tyVJw3k/Ma8RVqa+2INQATmpkdRmKKRqleg0nhyVkt6joz
W726oQex5ikMdL4shZNxstqMJ1TY+/evtOK0UOcHVWB0DgEDR+AvrYqnVbp4Q474X/Z3XNwDWsgw
WS8jy1xXW/nyDm0AwtxS/GtmHMZuq5mT/VxH3usZY0rnsPS1gUg9NLAk+JF2yv+v0/oP8H68g1O0
WlrvhupscigkwrXWQUtIfRXOHAKz0oETSWXI9NefqrrXafz4P9EsC3dnO6gm+0fVvjw8aeTqzq/o
88pgHgKo9zPvway+nbX4oR7ZEQ1rj0D2PmJJ6m5cj2GG8G9p4sU0+r1uQSFx4wEmUPMQTPB+PNI4
RM783qP8sWBatpXPsERYOWam5iYgVqL3W8sTT1+uTH1B2dhQ7/D8hFu18l0ahtZhl2l80eck30k2
HRU9MDghAFP7flf+9gJnPb7o39gJXahxSnxg40ypOCZgYb9E4yLSs0TCiMIg3sCg/B9WQjYzmFte
2QrM18aqh829YUsKjD45KWhY+ndsmM6HB8d7Bufh+1AZHSl6oKvVlOkkPab/HWhFoMCYaXsq0Pt9
7w7Q/XZcUYbl00O/H5g9fqh1BuARQ1H/QAmPp3M3IuVMJCWjpynJxJcA4sgmg2Acm/j3yzIBHt7a
gScH9pPCsIn/2+ZhAgScIxVu4AfMyLrwGe9kyGkRL3q8nv25twX08/7DCTojYnHuhM+k2DYYtHFU
77mWHCYLM2DSK4gpTT6qWfEP7nmql4BTU+dneNdhyRQlrJOrU/7YOyw3eWG3LUDVSZH6117YC7N0
oYf3YNTIt8qbZpN6Dl8VQxyX7jNE8ReA7PvZG62wqP41Omxxv8bsUVVYhdpR6kLRFjX311Lp0ArE
SeHgTAmm/kvFAWUQhQlg++zlZNSUG5MNsA0N3GxKznE7srllLOfZNINRyI5N8HLlBJZ05LkFm5FW
6DEt4+VtL5+IwlEc4zWTZ9A2H/8oigM5b9B3PbPRlOCQbbzivvJZeYhucCoZ4d5BFioVAEoV0iMd
UUe/Ia0ucVcYLgVUfnwObZkiYXENZO5PbNROyT+1AL4KBLIxaVIh4jGuhz0U+t7js9DiChsUAH4u
MMIHylrUdJ4RmprSKyBCBm/VoXBnel32efmeFvfOq1doct+D+UTZxG+eI50luWN0QX+1BLRQQxiR
luQUA3gB5KGrqFAhuxRH233Ujzevbp3ocJUefaYjD0lCrYZEbanH60jL2/AJB7/NdY0IWP0p8Nfo
4ENxpZM7ZOqFNcS/bwNS1YmRvSq86OenSVHWY2zd87DQcI+8HkHNMMRaxZtAcZExt/Hporgc2ODj
c9Gu2jh+oUdINPG1P2yoLxqjoOcgkbyXrWUzeqw+2WAhCXSQ7j5vj7L6oR7NFpTSZaIfVjyg8cc/
0vR/R243tRIXr1Momrk/AzwiinyZHm39odBnrUDx/6i1g+2xIK69Xmq2PdpltihM2BbpvHS/VQAF
3S9irVsoy1lq5F0eDRRiESBbVryWyfQtkwukEgvSQMKZyadGP7hPLUJuA/hyj/CwepxTeWI38iZr
ElSYNkPYEqHQpWU5EtM4tny+CcTDxfAZGXECGGXrqq4XOokjmbzIR8oPQC+Jmng66j6x7q/I1KOd
rgN7CHKlSfKfcNPh5H3e3CP7Xee1NiZ4PiTE1Yrr7DjfXbohdak6FUJ6zFMz353sqRsML5SkjMmw
LRY1oZB0mOGwUWrpyDU0l1a2zcmQVJGS2FylzU0bzTd7lDbTfQ7CzUHl4OO/mnKrH5EcPn4mDzb2
2KUqVOySSeO6ZTPtS4/U0+BJEsPRBd7+18BJf9giDyso0vS07Gh9zQpZ1o3Lm9oDTq2P4fi77R0f
QKtxVOJmtmV3jYaTzkR2Wt1qk8PsYi8vnov76jHbGvT0oxySKcEMh7nsyfXRZVzf0HkWg9vmngOH
bIR/8FkFFs4j8Vvg/dyvMKCKmiI/S/KpwaJoKIkDn47T6soe0kwhFpaJdoLDXjxNBZm1JXA23vF+
N0s70sbo69Wt988Q8Tb8HltrxIobMrP7Un5vGK55bYRQFsFHrDOXDe5JCAgxkxyZt3pnLkNTZTWP
8ZkJA6Py1IciXGFCQFkTmeVR21Fk/0OmQ2NO6/cnwTvCkwHa+w9J0LRrb8jTrtnDxPDuKaoRbDff
xm+KnayGsats5OS/JnE8NJXmEGkvRLdR0VSSaLC0mLO5xUlJg6dGROQZhJfAKYCc5Ax7P52wF2NZ
7+H7a7Ba+K7dwlFFctFL/c9hR6Xt7Cr9Z2Vw0o32Tqu18YxMFqGKcMHLjfNJFpTyewigXwHBwp+1
vlAiVdoSDMkWPe9nr5V5TknZ7/Jhh2I6WknLtBqQP7nA+zJ1AVjwiLEF/bf8A042+qsOqOLjUIvz
+/pBB1jVjVxi2LUmwkIIt7JXoXgwAgTcruXaXWjOruM0VmYzCsVbDqNRoxLzx/TVmhPQZWyRHpTR
W5ro7hgajlDX5Sn9/djH/ym+pLW1vqeWWMfIIU9hul81cly+6vHQ3ANdmJDgkSFiYlhDOdgsVgQ8
qWvle2XYJP5TlYrjZYmvGIWAwTewTwNqIRHR0deBuFx3xolrAZerj8lGRb/GZS+UW9AOSd/RAzqd
RrzfhJDTNUPknLoqtqSaL6dUoNdB0RtK/2/mlzgptJim0xQzMOift2vEvQCkkXqcBCEkW3NwDdzU
U8BpRqrk6PgWTszvoBa+KVuu5uUeZMmwcKPKvP7fjc+yTATCUUphjF7xqxx4JnBkpY22sJGF74b7
sPerR6kH0D8J6m5k6xxrZt6MTDryNn7MFlGM+WuCw0Ivm4uFm3m2k0fPfsMgJm3W1t8WCvhyR05O
4AU4L5SmLK0GsGyUJzi+m5DpPAoog3i7wsPSTuQJJgbkkkTaTMY87wjbdUPKgIl26tVqLALOm7yq
dgeNAdx3CjMmkWSlaJ80wa7A/eNAUxZZtXCrUqFPS1df7LMGTE8gllkKioMq2L692qRJY57ao2W5
f2l3qyu+V88XTWozI66X4MDVp9j/nR10Oqen3iAhoZ6nlY6feSVYayUYspKcGaSFbBVLGUJ5mefT
G5Wwg4UfL7qL0Jqj+Cn0NdVgFaZwOWy8+2lUixkqiJoR9VPnFKYqYOYm1ZWZX+xBWiiCiGA8uctX
Po1tqHW3ssrlnp7oR5J7nEq4WP5bHplBfvMtJuJqp+mkHfCnwBIZJL6rxabzdCwGSrVmjnxO2upM
aYZ5scRkmzRH1ckbQXXCqHaye+tET0hS0MQnmcyZTU18yEQnzHHP8LBl/r649q+WaqvgurhBl2Ct
TAfZaFEAek2KMv+6O0IL3i+EH2AhOUyZw9tlNMqqg9Yg3RSLNns9op1gx/IPBsu1NSinfJmkOojF
AKRu+wz5HQyQhHxep/ldX2UpsN4UazcqVE2UvFQ2Sqj5IRnggiZ0iUiDbRgv781uzcnPVDeglWBY
JLYYfFWkUC/peZGLvOWsBJAM5qm5KDAii7CjYq0844+ZzRf+TmTYhx7Jw2mnUzpAhr5mTy/ggLQZ
z9Ny6LXLEp24wVXfrXaADmW08fLtbEO4IJRMqvYbYwiSNHZYNFb+rpSHK9LghZgoI32/tVTP1cFh
wUdhs9wc29ZKE/XYrXGqkKqFEhSnkiHp2pERqJfbvt0que/HN+aafEh7kMQMMpG4l3JQ1uAW17Rl
fBXnhkpuRnOPn0v6VzIBjJdim0bWpu/lnl5Gqxg/21MBOstJn8haYnPxEnxk+8vPjx+POGuVowR1
CqDzpzdiUEz9o6ad5tD4A5KMIyr+1OS9fBl1Zj4aQLMs2cJT+djkgSyMeNIau7VgkyZ7V7upJGON
u8mh8KQw57b/bs/FPLHBewI5FXdRRyLkjXR44XREtW+7pXpdYLRSdlgGy2fj2wp68OMjcNxU0v+E
f5Sv0umvMgIfA5CdBd3acRkvMfsbNypfUTS3CXPqGC1KMH+C0dP2DMXNIILu2lC+Zzosa1iC0boV
AZQUzQIPihEFO/rhjNHEqq0VthNIKGNmTEKHy4E1a+IK8ZLovPDLUZfyEGHmb/xV79LFNPJYiDLg
U9Rhfjrbqgwb9wpVI1+PDLDzGddNO/qZAi5ObieZuEGT+NccN5jNDqeA3YIb8KZaya+Yd+ENeqOa
vVQi0bQDr02GKXBlyoVWNnVEVy+xO5FiaUutvZCmqWxvQYJHO6aZdj3hirS52Mdo8Mnx05tuMjrP
OshAtbKHU2n4HhDNb9sgFgtsRxmCHnupSFD2QRO+KCLaCyxVMbkHT2xl82ndPXAXAs3DnOuvEyVc
snKbl2etZfeJP/04tdcUUZ6eIPpNRkgxViTFG4OmFHqYIEYHa5Jg6IOIhpyRq4LWXqI2TM4oE5U7
cJn+K9sBJpEEKmzYoqAY/Ynqsg9tgpl5NhdEGnvBq0Grg5hA7SPWfxZD3Mq1KZIMSvuKelU4TuVa
m2tKA6cwMR5Gmo5oWzEs5sj7dfuN7EWxFu59GPzNL9MdQUWHRdbVLuPouFc19s5DTJIZAzegbhfN
UJhKHKGYUpW0Ojjz3fAptUlaDGZHUwOeXZ1UD4qIlWCzaLEYmOU2rk+mZxQ94jVGSAecLvdpnPhU
5EofdinkSwP6Ql38mDJeuQ03LoGsbH/9XV6A7wfeIr66SQ0cZ6+HBhKobhOw2VXs4c2kGXNIhJwf
9oXDXKp1RNtSAFyc50UkoaxDAuuTzJDvk/dNpRUp/YuW3xsgZHWp8KPbAHahpLHia+0Q1gL99yQB
kXobkiisnZK/qL0fJJItU5RRjR+LxukEPETJopbTM2g/0akh3BL+Kpwyma05L++4WkzE7xeVeeIa
oUAQCppqtW1Vvq350TyZeRbLNMPsYFhR3zZkfe2b6TkP9HuJ+ekooNqkBXT2cnNJ26as+KCEbTcv
yCPAIGRTdLmRTOfbcFFA2j28ABInQOGuWOxFsSwwN2vNUXKQWiLqEpM4ZVOSC2EoXCrna8g+eyrx
qiv0Vrnb1Qrsg23gA0eJfkk8HUCsh9TWKfXbfc34fwwbp/LiQ3OgC95Si++nbp+nu0VI0AbGx3S3
hFcLbDXU8Tk1U9+L00VXPxgPMz1ENC8tY68tkB5IaonZwDwJy/Kc6IL2Rxrd/YO2lXuqCEU5tLkX
lxEdgnN1qaGk3jLATELgyuNbZquOpQ2b8ruvfVTAkxD23r2ecEQ6cAReSiyCaJLvvzI9Xi8L0BBD
TGwSwKiCTm1rV1j5ZIVTmIqCNcFhPMoeyfJi2Q1lxmPeCJSm5AsGnPI2T1m41ZSeeZ47Z9rjQvaR
/TPzcNsACvXBs8nly1YY9Fe84/NgfuMHcGyb/DQagtmoHoOGZetImimVguqmrZWXyi+1nHg5LBJg
gRtKSe8hLsiLGLWHYINS8mHb/xY/ZGmWHkUMrFNI6K/OwzazWUhNxETWrE9MvZj0P+4QhyZ2dhy4
txTYLxoSafl9Ku93tQMPxBhESmG0FMHl/KfXutmDHH8WDu38njeYAVhi1oA6JntWuR4m4JvoR3R7
7spT/fcgHNCSV0ecL5Xxxg9p67GFJYXzifPBFLC+a9gTaAxW/EzAHBM8KkTjubST6QplftjTRf+I
ILG673vHob9J36JI6rF/H/MgWYvcO6qSKD2qN67rdcZXkB/wNcwfixanMr1Q6TFBRCxUbQ0O4GV6
nOSrx2K6WWl6ONcC+jfI0Ouvl1GQbslVmylBySk4VfXs9gkfYzXArQKU9tlp4BiWLYq+8dagRRpN
OMut9cANqc3MLOt3u3wiftZgeAbPcdoQLDCmEh5Rs9ZO6geBqvZIXBYgqqcOC1hNPOjW0Pne1i36
uM2hcq+0QQGqCW06aqKFGduKgVxkO7kqFn486QmgekXM150yvv9kjoIa5EmIKXuJBOEDcgmNRrNW
n3PHFTBZoQNSGYNSaT9RRzjBOWbU/GuGuNmUyeVgsg1LTygKqpK88mc5iVO3St8DqfTdVucRwrM2
xbcEXgtJKhPv0Dsjx2mGnJXzCSD05Er4pKs/l7XmVvsljFEwstsfxEABuOnRXk1ysl5dLEBEz6W4
ca0h7PKinn4UfMgSoCuh4EGoF4ScoYLuTbd8LQDmgs8bCaz/BU9ziLy8Hw7hY3QhVesjV0/04s3K
nhDBt8v7orsZOyLY6XEsX6iL17qkJsfgQzNLOv9x2Z9QWYI/jvSIm1bBZn6bvfz2KjK8WQhr9YL0
S+NX1mL0ehRRZrfESdxuXMOJrwyq35udSc0+TucrS+rYMWVNabssPZYS1DSPVYpBXnMvHIFZ5ZnN
k2D9vFNdyfbEeu/gDXN+ryCkfNtAjCl+7b0K0fPmKphQt7253k1p06nBBKY+rU7E3IekyGq5BzSK
bVXUi9k69U2cg54hhZfmINb31XCLrnJE0seJOFjVuLuyFTJRxuRNp2uj7ZDEvuVtYpqQdIkHqnQw
9HQ8NCHAN0z7Pne+n1kYm2OcolFimuldOLdSl8ErKpwBUqj4uSimgj7juPHCtY6aNTNaWbDcfGSY
aTtdn7lTnKV/sPDOPiY+BtJopt1IqknccHSj1GFLSHDBlt0gWIBaO2Vm/1KNC7hrP2GZC+QzkvsB
zT8tP0l90b9FEBPxIkWuFIBTIiK//ovLLZdbk8t2Q6doEaA1u24qA1Q67yM36qEYMPGwGjy1RS+g
b024LN3gOVeKobkqpB5EVGku/SveLuzaY8lMLs8uubYgHyc9mzErNUoDNvYSd17BE94MeSfL4idx
6ePfTpnoXbu5AvVTekfmD39Obs9iyu/EJ+BDWImTxeX93mn4qhHoxTcgSAmf1TYlSEwse/kwg4+i
3+I+1fJMsGzVw34nK5okJUMfKKn1ZIn4WBu7xwoYAlNPmb5YVs6eQK3abJ0o4z+MwlO/9+NfM5GH
TuGIlH7jDZD8RXXwTfwyUnj/aMAbgxvkAnUuou7JvQVEf0QxtCr/fODSmEc1s9nkWWM3KoMxgGTN
bfmb0+DbZ5IOwda2t5S6FtR9572zKeYLC7FsFL9mkUf0D55MDKKe/P6pp/VMNpylnfGh4/aJLBQI
BQzRDgwPjMfX1hWavvlMnzwtk6olNhfwJ7pxhzyd+FhsIQSRgfggDAv5Wee+pNifH7Go1JHwsc9V
IH9unoOFkCYDGa9ghhtAiVqLQ2K5SVcElb9zZ+/j589UTOsE5eJVgA7au6C8f6fPnqAbAyw0xNwJ
oB4Nq3mmo5zezV9dGKaVjme2+STLt/p4YuMXnn6jvg1BraMG3lsq5tmgRbXEhfN/kUnU04Pcr50j
G5zooiCNeL0gDFqEKMUVjIWt4ULZoe7bhahfzY0/+Mvhcg0a8NJJsIdo4RFUILQd8td0NvssA90y
tZuv5R64BgZyvGSy9cqX3NkaBpja1UcepaYHD2S21FFsDepT6cZw18YUf6r+9VNAL+prEfmQii2z
OC7lHNlpOWyTwOpjaOnNrCvG+cVHI9fULsWl1ff74/yijkx4ZRT7rF7az21HPSc3Lof5OKuca2uU
B+9E+gE3fUmbE4iw9/XscaeuAB7ttrXcA9pZUr4WCsBnZzFGyXsYzPDcDM5XNg3WI+Wstzr1yliP
OZOeWB0IYRybIQ85iWhoYt8wXovyJc98TJhJSSDQ9hgswfKqdQ7cGP13np2evdIHn57cySv67ZIb
6+w2KDjLBPUsZfVD/86Au1Qj5N8WJgJJkkZRo1jPYHErXdxPx7x1kjzZMVT8B48njxmT/5m/BquZ
ZFMTn9Jt2+AmjuWNCOrVdsSyjld+lyTb90qBdlv2bHP5g4Nu4xcLqT9ZuX7he/Z8lbt5VdjqCrgb
3TJ2lEy+M1tIBJ9Jk/q/pHy/TNj2PU75tINIHEN1+sKvmFeHB2ZyiApcGxHCfoCo0sYFLlu+UGk3
xzsXuxXSIjrHo8k2C/26O4COIT/AVcdw7NAjFXaW4u/6erv/bnTxHHGsoaFt10qs/VL+5jJGqBti
7OeXfHtURAzAxVD+gCuSEat9Ygt5K+617N72J9pmoujrGDhLxBNtIgQ22X18CYxEAQh6sh23g1qJ
nOaL0uzMX1OD1AS7MLB9wMLLjwxLGzdj+InVmZmqFSfsV0lzkuoQ99RX6wWlwSQF60JioYWvMDNi
oH8KDpcyzVoQLV9Uy0qRdND1RLn5/riO49U2wjOAdfv/uX3sFNk9H4GlCZB9WIxQt/r4arJAC0wY
LMDQEHLlT3Z5rV972I3hINItklYCB9i9R8KKxt0y6Tk0arHbL8pEj1TO10+ynie4m1zgqbptZh2o
hKH8LiKisrKGw5qMEeXhqKSyALxBxwBY0SWsf8bs2ss93kFcnUn3jsokryIV6ebZWjzHMtO63IwX
B+MvIWjrN/0KFhI7wWWcByOuplpoh74RTzBShMu+U7AXC/fCuq2F/I3jgpgCdTW1T4dgIXT5zFRS
pknLWN9aS/jCtj7t3RuZns5i2OxMtwLOTpjxLgMQaPiyJ5RXGfngyVY1dPD5dfwPbe8mwypmhCXb
TfDvyPI6DJYBAi9GHWB8RCKxdFN+M/3VijtBuVGkw8s4Zi8oGdj38c9w/t/EIupMFibizamvIdS8
/PofycwELMvk4KfzclDERcfs0wUYWgIv0OB0FEvVUFpBvFoYKpn0A9r36n3Qy840lmP2GEACPc46
KgGcJYOXdwUNK3vS35jm5aNHzBPrMi/4HRsdhDHuxvllcUz3fLiEM76uV9hOq2csyfDRofGWrmQ7
FnCxRrdm3RyotNYUmj+Nl+drd9W4FU1wTmuRoJuzK3Lop4CC1Fa8B2xSab3v+1WzZGzs5DF9A1Qt
3e9U/H3788yE4R9FMSWgbwlA6X/Dv7F2HvW3RHgJXY7+y3pjnk5uHtHzgwZA7c8dOZ8RvrhjZkja
cecn5Yl25vurrHBT9WHQIsjp0tmiwJYKRBslLdLZ7l2h3NAsqtWpZeebgjOhgYya8+LIRGCWRjaL
iesCyjS6/ie1quClzLMDnLGljkU9e+fPJZTNj2uDpvJG1sAwex+hr2v2nbdbUC54xGElMBvAVPp2
pzQE5KrJrm11hVwBXT0JK2wpZRz4XUrf0OrpPS+7FdAimAhb0XK+C3IFBoQTLCmH9AvdD+7swDHr
joTu2nhGJbtTCPnIsFNBsF8M2aP4zu5cEeBHx8B5/JUYThP/n7N6hPvgaE2LPmL0lJCVwr8Af4yp
JEUWggT+qpUyDR3ug39CXAn8GFfLpJJ3U/1Y0UGUfYDWJK5xGlJRRub/TAs1USFbzns8EbGwL04e
xWQTiDRxKi0QDiGaCWYx4CJj0TJR1GKAt1smp8tbcLoMPHYOdDdGJS8iGzpJg8VzVo1hjP9s6RnI
I3hzDjGnCaz+OAA1MqRAQSkU3CP3HcI/gBYZVtj0lBMf5LnFQgs+gCpyQUexW8nOllUSUfYoFx+b
5wdJbcifJrPQC5cShzJovaoXmzHaxOh4hQSxy+Bk398PDykvz1GilKqnB1qHamHPYPheLbf1EB08
aBT3ucxGByVvBB98JeqVYvixuI7hX57HhoPXJhQZZq2v4NVupkeCsbbTdXQhlGnfsKUEeiz0kFUU
uOC5X0fdOFQ9Smapi2Zdk8th2cChxyVriD1M/nlmKZEmOYSkx16V33fZdzvDUjUGSAt4sDX9K17Q
A4/G8RTE/ta/ph4FQys4NjwF12crATOmyAPPyzHLQiVGt7w5PW1xax5jw6H/Ks6HxtDZDLqiPL0t
A2iSbBQ4qwRuXy1wVN0/Xc9Mi8OnVclM7kVWJYFGai/rr9AMRUMoBxnfXl1cDyuwacHp08QtyyNU
Vo4nTr3kYwKy336uzmBbop35jGb0S1RrR8rkmMz096t6iaunCbAQ1d9uU/1+nafF52odpUZVr8er
lp4DXoIK72K9ikZPfSPuG+09KM+eateheLmZt68KtT2MBXnPHhAPcGXWvfnfKHiCyhGBFqH+Ncyz
LBBHvh4MdJYHzp3OYmFo9It5dtJYu2pY171WYKz6i7R1iSfrzrI7FlPhOr8i9uDfD91bUc72ud7d
+1HGZrqg6Se9uqD7iAPoqpGQ+r6u2HwPD/Rl/SnzTwTzSFI9aUWtypdvDDO0h62sBrs9IRqMJV8p
AR2pq4gl+jOkw7i13WeUsqhv9q8UnS+9t7Vgik0N8noJPLvzyTDiO1xDDsPrcnEz9chvk/TgxMLo
bOpy6fO6RqRfUwalPNMM4R+BfzRPDEcHyBXAybiJMmGua8wkRUmhYwCJepWk8AhVO1lWOd0Z3KKg
oPttACEKwyLFtij0FqEvmBt7D/r1LKQlwaOIdCxbeaSmkOdqMyc4DOZCSZ78QQg1X/zaDTLDgSvv
uF23D/oGRNUyl6bKwO6q+AyB5kihKvsXoa0lKxKoyaQBE9D+kPQEt6eIjTx3SZW8FZCVr58mi1JV
2ef/Mt3Jda9fzd4LQHTTJzGANnhNfsHGjKtxKYkhdqIGesusux2IqAKSl2qTtYHm9qd6LFKTV73C
/Cs+PVbmflWYvBH3C0RrkoVR7PFV+ouz2k71Ok7UTH1F6+Pvx/z08YklxRf5P739tpJPa2ygq/qZ
zpbfJZ+vRAb/Do0q9maHN2l0upbDoDdSY3w4+Cq/pSYXgr3XZDbTWr+WM7a+UTwt/JevbC9QnIIW
SEzznk0osJgnJ9CMNZWg/U2GyV1HPbj5hHuKq3M7Yo2/fiXD/5vQSXQAklg62grhmf9s8VSD7jM2
7meIB4w/kBnnjPop77xlZLsoVP6Z4VhA2KUhVA+z5UkWSbfhkXN/32GiI9kVpV+wMIlHNBWBBL4S
+l4NQ/4M0je57ovoVbv3Y/Wrrr5RuLRo1KypmK5OC72mFFWUQcDmR9ZZIjobQHBX/ZqF0hI57usb
eknHlTgdgJShfle+mEtcX0Edr445IMTU7U+Y6Jicz6wLtdJFV59PBQlyxF7CzXowHBZ069USaGGT
rTX/Dq1q1oeUjGZLM9SlPL899/8Vo8Ts/6LpXOvO3brsDO15W+IDhOQ0E7PJ3Rf7q4gXFnPS36xh
rmL61G9zYwtOGqQK9ELom/I2VkX/Ak9VgMya5G2p3PEFJxOYSQfhiTSnKQMWMujBjwquPdgmItaF
XMC/j/1ZAjtgKgPlVaRBaBVa4exSx/eqbfHiuFnQkWIBXhMeUjAEp5j/D3iJ0GkQJSwaTQx5Omy4
c4A2tbsf41UVuRXRzTMwLt2vW9qB7B0OKQBnUiD/mz5SRPpd2EaQgo5O6qSYhpbd6URxY5DvfOPv
UpVaU/zOd+o/GsyDOawiLXF2RnwK3+orkJyYdKv+95yW02aANPFMD5iqPtdOrB0TOirn78Bqe0jx
9rbmp9g9f7cOG0dBwnG4Me3hdFOJuB8kMiC5GrIVz9DEBq7q2l0buCFOgVYhLPbF1tF1jEfa3zV5
IvJyXT71s6AKkf/KsVuahe+8+jy8m0VBjbIwVrVoLmmvmYMDwNhHZ5dotM4lWcVVuXcNR4Fvb+Lc
Oif1Ngzuczkg1FaREpBV4g2YThGDjTDqM+BujoskM0jJeU5s0BsS4OW8x5nwevMIaRrzeq7RLWwO
vpmXcKs3pF8zQ5T60TaUvDa6WN7Q140ssGTnsa1Ragv/YBPMCQ3nwaZdV9xT31Uy4Gooi6LPaPZT
eMj8nd8t9EBHVhhe/iUu+3+VeR/vEF0yt0vV4VMEvaALdOXUL8paAJvNeuD+COqVdp6df38r/PRO
8j6Zaw4mi3Cy8ZKB7sAdTxAHuGYhSdj5eSTfhvK7DGsuF3vpfH9cUss7zOzx+XkaY8SgWJCVENFh
je/8JS162bCF2pEh7p+aPb8M8LEg0nmrSQ72uDKNLVBqIpTa5ApcXjfqhZ2ArNp/uPjrMkVZv0vp
dwz2XPEffy3bH5wfOEEwBZK+rcHFahEIjmE/GyY0uc1v/k4d/cw2jnVSM2GTzO+2q6j019r02Xbn
PT6/6PvME+RJ+TS1FhQRe1I+u0+EMEPr+n0M5hAri6OGuyHquP9XmMa0FZOQ0fYvGXRyp44uP8MP
31Bhsk/nbF9MzO1LSVt5A8iQWCIZm5k1EfpDjg7rza/PbILpcsn0+mKLTkUskqHW1VvktT9vAx1I
85btXm3qxbVb76sW/450gQzLquTofS8U8fzfvAAvQ9Iwzr9Bg2/ptpdHigvS5L1Pu4dOlI7uVvYB
UomDPpeUPeMQi86/CyCIGQtHuMcUpSpOb91RO3WB8FPVz+kkMpuDvW7tGaC8jtxmNGmgv6td+5Y0
bwLs9j4RPXdWlgQH6BxuZ8EUCrglAvlvtxXlNsy6ptUDUbHbKn0sJFeGGF3QHIAL6KH5oCOKdgSS
wxNpaNei18dUSgacn/cxIoNYxirD7ITUIuG21SXP0/pjG2vImMZwyqpgb5F5298fJtJCVGOyH9Kh
fcFSvECOjb6uWU9ROzePlVjMvwatM3cuqLkra+T6CIsWdR2fTKiGKNggyWXCgIYI8Ln+VYoekBgB
EW5Pats5ckXvFp0z3mwNELQ4WkSo7vfdjTXxb+iB7PTtk7RH62XJ9XGicZhe0Ovvel5olnwawwP5
YUDQxQf6mzJMYvro3sScQGquzSoMNzvG1sF50bG87kYihrCIXjQHOO+hSXxdyo986whPwT1XEVId
wnMaiAzkIR0vkBCuhJN2qf4y+/2+E+Ba2piRr8xTRK+yrY+AIYXphlI1iHBaMzlfT9rY40E2uvc9
1qpWKuw/Eyuc43idRMwBlGTDidC6wT67lnFOqS/Rh6RbWx60v4b5h6al3XqkI0/P/uiboZpago+m
7UYaa4AJFwrdCBOfGSbaNrwhkt1UDqt9+h9RI1Q+Dhhk6TFFNuBYU9NaP6Nw+LkHkH+tfh55T5gf
AqQ6EifdtHJUu6zRes8VxVVl5y0yCjQcoiS7Gdc9ymZmLtvEb8rfGPjjDMOmdikvJz1coFsY4vfE
029roUzKaumehadT/gPj2QpfK9dPhifrrgF6wtJWo9WQbWBTR1ZZ3z1eTHTLx9uH4yyBxEg1qXHn
eWEEXf+CqloyBLMXz3xrSQZ0tcGIttF0y4Ttbyv8E3ke7h64QGGOZXZ4eSEIv9sKNGM+G/B/l5Vc
YQT7u9u0Ro33B5NYYqLeGqVvuWSeug7YVMvs9iQwK59eh0hIRCNZ0GJulixcXspUppPkAgrH9pec
Nim7105KVyeOF4PnTj1sK4Sfkv4ZEjmHlg7Wn8vDUPImtNx1wrOn+KE8KtPVzIuuGzPxoESEwPU+
attlB/o/NzrLFSFqZs0oveHY1wXATD0zm7fhaYO+NYeJsmJXjcAG4aK0kC7fUYZ8QtshGHWnDEQ/
QsS6f57wJJaMSs/FQ1Ee7287oqQQYLJPFZMUB4Z8zq8SBibNUyC12E8V7dz2spXsqCr4cwnwfxFZ
X6zxhsGazgSX4wm3y4AqDY4V5JrzCpo/46N8nXIfqzGfe/9mEGQSlKXzXgvJec3MjWoOlR/9LnwQ
enoGP4wiypCau1u3o5z+Ldj/bKXm4NUROMxVTORrRgt9fxEiZvrzkqfIafz8Z3fbzJaitOxFv/64
PE8krg9wIE7qU6L14benBOcoukEN6LlCBjNp/mVVbAM51zzDPaGNREMUnsYp32gnMW+iNdAmtJda
1jWCux+s10IhDX8LZbbpbKPqi8Q4aS5JzVIm6hUQfDN3WP0LW8tFrwm+DDb65gmhnXgpUcwCKzMJ
WeGGOa9nvbTcIeVMYzRuTUuTPC7SJZHQcxVMyI5triIqfZXzhLOS4W+/I0x5CJ31D39x1+zhwb9J
ZeiXbkmdU4nFll346Dc8jimInwLLRzEwAxhHKsZTjKOYs6H9p1SXKxevhbVA9gHhTKNdxwMWk8Uz
K6JtfZpIa3NTXm3aXTH8XyBLhw0law21nbpn4x0EO0gncWNrymsGGqAVCRMepo/QchJ8cF4dChIh
GB5HYX+WAStkp/4XUQbcrfsMNWlOU4ANGC7knUAu8/5uj5IgF8bt6oVcS4I/wqjDjI7Iju4VZJU4
eblNoT4AdC+74FRwi3jIjVSOZzqCxl+mfHMpPi93QoRfyX/SuqE5fbkixDZfAR0YeXdJOq+vEhBg
0kLgPTCuBX2CBScIAhesJU9lPMuu70RijFUzkEvKuf4rG6Y0GuW5ce9tfZkEXGYx6SSpcQKPtn9A
h/xB8VdvddpSlPnbraC7riZTwH1z+LHabrdD41UJFSN0NcGb6SZ0LUTkNpE7QpRCTSHuxjiQ+Wek
Nrpd1CO7E8ZrGoYsBPBudDUtoNtMoDeyY1YTcGFcpU57sDHLkj1TPCtjO+LG170wwSLPoYUHoh1P
q59rDbI6BGEZzeQXPAI8/6SJXK1zWly7gl89qmTc4eV9gKVzEE5WW2dMe3PPUIuHdBoerp8gU/ES
byTvN6kAu3C7FhPg3R7KughU4S4ukAbp+xRO4kUzvOkTKyZ0EJwGtG9eBfhofUx97cXkbeO6si5O
6L/9wcQEpz74v8jTG7QuEeUreBGJtqQE2IQO+JJFbhoPCVaclCPA5JHr9rurgApQG4NigxuHf6bU
Eq7EaGT3mMWDUDvgZWTBnxBkZjDRblz3sTwC15nuJzy2FytrOUJGm7IEqQvfuPt6QGGidBZdI1e9
DobBbBuXReFnDlxnNWCBsDpfxVZITRznJBYf309qadTyMsFUGVYf9HnyDkeLHTWugejO0r8UVhzU
xg7sBqZohyGSm2FYLdfvtAiaQnYTSzxDsTPDs0dK3+WZRO+eDIRL2ur3wVFtnMrsgpudUJZHpx9r
qLdZVJUnDTOraXem+A/zK0QciZYLR//09S1FN0eL2ESuWo2cEFyzMtj6gbSofKaXbSBtVt2pf6SG
fVwCIQA4ynTdtiEiYoDVGR5+bgTSFq55ez8PUzEgbA6k3qlgRFwBWUE6q8RAP5xfCaguvgxh8OTa
t3nLb1fNId8CvuseLgq7qGDAUncPphK4gUSbMcDP3k+bTM3sqxQY665P8yxbZ1VYaqaFRaaKYaNS
CqkaOoAyNfo4yEKKwi5MVO6tl1ZCzha5K1g5Pj0Q1/pVS/ZFB5ltnNpZK6uQdEW5lXb45hABYkmy
OGE8z5xurKXxv3Z8H57s6hVJraXUnTyyiatT1EbhpQMj68pc55+g4XzYM0fP9CjfYFzk8H+tg7lW
61T5s/6w4xflwTHgS2miYRPeP6uPirP6M4C/M0RqzR2AX4q1De4mmM7UfhwrgRj68y0HQWuHlA+E
BT/fpRMuTEa60Je7B20xe3jYVcae/m1B4q8qqIuhue7v2ZTtlPtC+UShYG8rAekT249UjhoNhSru
Vu3MwfHjvFYVRUVPcIqT5Is9N8GdZXITt5ug0KUhe8y6urZJn+mUAfkM2faON0BuzQfHI7YHAMSu
YYF1mRgUi8lgGFN+SyczgIjc9xFkRPN+iMvSYcrD/xiwN9zIF0UL9U8DmAsMG36j2Xnxkxbt/viq
GjlXRpdmXZY0nCglmqIbAEXLQq4o2T88MS659Pb/t/vx/JuDnxrjRy9JmTcsBqi/tdrrY8q8G5gb
fcIERk6YM8Yv/0o0WrEcUwTd8Wdu8rZ6BmPCeey1bklr2IQS1Sl7ztpMuEKSb5O8IPKcj1+tYpUy
NaF1RRIyAJF2dIg7a+rEWKE3OrOeklXV5SwSrzKD6xCau5mJRXgnVtkGsM+6vCD/gLrQ6HY86KbO
Ow766TAKwZAzxn5KJK4DU7HiqrZXftZUHrT9zWfjuIrqMo05jzraxQPnn4DX4l54LhAQkwTdc4KO
YfoEZIUON+fczIGeG6yVCtEr7bEJph9mrZEjW9h2k5bjLqpiMp9QoEqb5X0dJ9yyxF6BlwXZdPOp
s77ujk+cP0c7Rn0eqnSgsbI4Xw1dptlJdKlwG3siRfqCZYsKxWTPzqNPE84im3JnrxeEwS3VZUH1
vpIWnmB/ya5qpBla4qMUyfcsv2OaVsPk0JppEGR3NOQkElqpPnbGA+vXtgxBp3eIEncwxA/8yyfe
JTPT3RKLEcIYxtyFMVLd6FOetdnMdzLFrfGxCYNvF9ecJTPSmgCCjZ9useuZBuIkNe+WRJWi3gf4
C25yY/hOVFhFn2vjAPY6DPYpiWWA4Ks07AxEgd5jUWo/U1AZ2Soi4U20ZNYc5IEA23Z2a2yt991P
YoLI+O8p+ecMDBEyRKtTRbgrZmkymoAeMB4lY9fxb9qHHAX/iYVRXLkXJkOk9pbF19J45m7Ik6Uo
mSZNGtPCvq6pnt4JRJnDcJif4PUpGmAPkOz5/hU+/Mu1nnqAKtum8g+yOkdQkV7ckYW5nO0cr295
H6ET+US1sqacvvS5itMkFDbdEuzlJpmS8vpe1AIMA9uWDJEc880Sp5GAibmGOuTO+4sbbNAvdYEU
B3MkupPT0v/VO91FPfeAMWJwgyAelICKPRv2I788THD2cfMl81xxfkAo+X1mOKuL5Vk7KU1GPPXp
Er5OaZG1IQWUBlyLoUYuOQoyDX+u1jc5sz4tIS7gHF4tab//sZGXoWpyf2r0AQOfbPkiLKZwcksu
BLdGD23YpV7bs6UT8oy56KxGWV1BJARDKsbvAi/BsVZxaZ2CHgU6t8f0kqJgtx8V5Gct+/bPJVcB
vKUADRDqBJ27tULVRONuy2O/HayO7R5VvSHD6vvR56l/e53bIyMv6YapUygZo+pXLKUcMlB1Ywb5
VkOmEkzUEEEBay9DFPH0UaLNeYSkh0QjUI8uZBl1k/SOvUMugA3GzLKnsgs/iclMhVUBipILMX2i
SYb4KFYFKagpiHp4ye3LThMrn15fE7FMOsHFk5lfYX+DFdTvJMshY5ygF2HlnMlKMe1lJSIbCSNO
F58MXgOJADINXbXePdcZzKjQ9n9hAeWtjtgGnIEfuOENQr3m+cVPfUKQlGbaoVCHqHI1kgEOFy1u
eCsEf0KtJRCGPx5pKF03mQBGnxCkIUnsCsuUgCAEMGYUNbkknj/W3tMxfgNQAUQKTMkmSVe5eXP1
wktPPbh4VdZkHJfzQOuPA1RD4OO1iGolF3XOA+7u/yoYIXO+/f+CK3C0yB5/Bar7uO8OAFT6ycwA
SWw2VIDFd5gl39NolCCOZw18FPPwvGxt6Ml6gmms8z8Tagku+124BmFww7vA+QjlwENGtw5bNf89
OKKtzR2eS9vBhWZ73IzkuIxWQp5kdKgCDj5OkyzS8WulZD40g0wkSvvpDb2AouZDa+DLGKrWRHnY
9ri55rC9UiO0ttvKIrPXZafpEIDrT1VXXJyBpH6yVbhz3RaHU530Xcj5L0D9Y9EltFVGgssg17fR
tspgu3cAA8IXVB/gSHUC+G4qi4uC55s+PMpxC2YvMzIhZkPs2ErIVxPXiWFbaTuzJJJwFHJTS//x
hw4G6trdTIq0N5PHVIYctAlKU+VLLi5V8Eiao4LrsutWz9FiOrEmKfFJ+4NVW3tNskweVQUEm9Nh
citm1Ug5GCkGcJd/JoZ1ZaZm9kA/wIkFrEsxlpyImoikqGsSBt7BVLlgL2xEmyqNERDwjXMWNEfe
alHv+g/IpZaJTZK/Qk+2DGYoOGANxzoUREQjohkO7FUlKGv0K1pPyjTVclcIkOvG5p7+pjeQF4OH
7enakUNnYyIdr1B+UtAcJRE+oDFYBgxOxn29y7qlfSMk4FkvluaoVS98NwKhWaivtx3EOohlcBIX
Y0b6x69IUxm9LHC2bfpJX+q0RK3Hb9mHwMbeSY0P9Nc4+JCIzW2+qstgIpnR3w03Ea1oXtPjjyr/
lyxatsDGsP4Cxm1oOy4dUTSFNNiztsf3TuV2xX7zT+Rtlc1q0i3lLijqtryvHym5zftcrDJ6O7qk
K5gsRiI8LrFO1VluM3UqUZarIf2JgffmW/oxr/SG129N1vbd25pRNcPqqtb+NdbxfvdjTm+/CQqC
ayuLwCr6liZ01FR6YKiNCp4KGB1XiO4QPjDEf7LRmJAkdvuYqrJLSpKNgEsipjSS+yIIKkfAOyHd
w1sclsnWBPTFEnD4OC4QlBXRYmcVKC5Ye9+JrK99nkZ13vN1CCs6PIZAffl/ETngFMKPIAeUJekH
NDNDEhLZFt2C8iWrza/aC0WdXdEZtpslKQkLj6UYGlBPyYpL71LARCgYfbdLDI+SGfiiMbtqwctT
mfgXayfzGKIQulMLrN0uGOymQqyWhNGW2tC4q/L/oqd0AQ7ExPKftslY8Uz8D52w75NxmorDW+Ud
oKh1V4hWj26aaWITFbb9gmB9c/CdI7Rreg3ymuioUf6GUbFI34Gt46PUSoPg9nTi4qPzZlNa+Bcy
U7KWiCkHQeh8xrIuLQpPNVctHiXefzfXN7GzAuClQDzmHvokSb5zQjhECNa6WxUcEgfybD4/RdqJ
5Vg+vGvckfwP4lCq2Tw2NbHX+iquSX9O2cHq9URfU27V+CQpRlMhBTKVUGYfTgQasV42/acRQFWi
0OH8DJOni8y37vYsqCCeGrpfr7VwOhAQZjsHMxadfitbHY93lUEmeqNeJpGa3f9DmSvp22GnNkeU
tG3I0ntCl1yd8kh+2/+j/F08aft083pPy6I0Q/A6daJqgWMQ5xB+nIqqR+0zRlgwHM+lHrL611fa
w5Nv++gAxNFc8tBenoC8a9MCe23URq6jNuPJkFH57QuqXjbq5T64bTAgRvYddbqwV8uZPIWcssBG
nrYuN956OQq9vTPDpmMPGaXUhqQ868LU0v8OdEpx7uiOyefnYhBS9Rij8/Br8i4Nojljdrbkn4oE
8WcuSpWL52CNoOs7Pj/DsImIf4aYCuJIMudotAled4+AMXMFV1yc3s6Z/72hQi7jZdFmldc1l55O
VWRKnE7xBAYrgRNgwj5kpiCt9glFyoXEmRoXtXzEIlN9+ShCcqmKOXK2p4AGelhh71skyEJY2PZA
IvjLOdZ/0NTRhBKAV/duj04O6KgmuREs47ZM4I51J+pa6bQYjm+BxoVRguX5iQO2FKkEaBegjxKQ
gunIP+3p1QLU2ipJZUFdhRPDNY18DaJY/sp1u5g2Vri3lAf2bRY+m2N8ad+QsIFxGr6f04/uLlRt
b5A0W7wA071ofxJ6LG1F/ejzN8JG6nFkAkOfm64SYTJ8xEqASb1JuNiWIebvxdUEa3Kn1r9yo0nf
Ajch7Cam+sUd5jM8/PT+FmOE9YFsCXeijTSQ9O3/LsCt7RgGbE5xWelsNB27ytd5xo+hoJT9XGcR
k5yui8QjuEVQsT3kySL6n5ClTb3H3Zh/z536Ryg3jAuRWeeA2VvjuVZPgqp+QicrnGLDx5NPWn9E
MnaMvt2tiUoKhoM2PLf0iQHiyuMw/a6qOwqDCL6vRPl/OuzsAbZPkhJk7i8gAn0JFIAKiAAQw5wH
G+Bat5mS/LH3l/+mF7vzzNvq0sYwQm4384n/rJZhHThoOS912r5tgtP/93trfbyhBBFkKbboUyiY
kW4cyhzkobWCmBjdSi5HMUVvbkYBzNQneIocNsD+t6cMKZA99NfYrFeAqJ0wQnUFVDi70HO4WkoT
CjUcZGC9TVYqMaiRP2WKni3W86FhVGwnIx++AY2GXn3CpIIZMJQl1PeejRSSdqN0ennUYjUOUJ5S
Fy426u2esmumg29McXjsxWAt4mhC9d5Jxs4obLCCpUS2cnmBn8dwHHf5vg0eV1y/MEcn7hGpMKrk
4N8jI/xXfZGiLPbt74vmhoFyH4cXtoe9UwoFfsF3eZ31v2z+i+lYLLM1lYwPSmKB0WgbU0geLLZy
2OIBDU8im+ouVOwbxrYHwyHeTmSvnktxZdhbtypbBJsiM1rED1WeEqa+HJKvOUC9L0d7i13Gi1qn
saQYiFuPlUPGUz3/UiqzN1ZkIbUgBrjQ3tNsjFjpBdBZkxZlPynQByB6ubE/YZhMG2s/eazeNrDz
xicLDosyrYda5/fCFa8WMEkzWRdWtyyOH+KvKYbACSqJXldUcKuIJRg90qdTjfFMD315p4xyFGus
PMVq8QKDiZjELySl/T1tkiMNaEa+5Rh0qEfKH6huEW0GN5MaE+hZh1K7Uqee6WSccGdfDAFAnktq
vWeEZfaPle5tWcb11kTaNd2XTAlX+aTiMHUndiC98YqbM2csfMKv04v6H7JivzzlEgYQQdSfNBVA
betUv0xVq7R+k76YTBvfjJRRtmr5LDPgVGQ/NauzJQGq2Qs5EugT+W5PS1N56tSsWCP1/KWFvK2G
R0CuR4XxTwLJQl5oXMilJ1Q/X1qeGrED0A1QvMtuZHBbOmRXcv/eeTFZ4KvgsilvxsRtWstMEOpd
/RareIqdAQS3gG2OAK/YzMB8PQW4O7I3haIV4lTJmNY+4Dxde7lCNxhgeJNo9cA8oSLpsW/wUe1/
0z8QSMzNcT2VX995L4JmqFd28vjCOzUVSK/OAnTfxVE3TLtO9Us+E+ARsfkgVTaIrNjSd4GOrdZF
xMai6zKxEEKQNcP9ESVMCAE8yeblDGWtoITmpvXxy6KPuTqIdGKai7TTlRvLEMGvDgzninAxzEsd
bONEh7Ha88rBk7e7Jj0YDP81ErSHpOrOzBq/91OCBwpreDebq2E+4GyT0KJmoZid1lP4qh8Gl/CN
fH0h31ZexSkCGFf9uWb+Wtb7UcAdzgfngvxk7l5UWZszpg46HWaX5D3SqmhL6iKDefOsst0y9BYc
5m5UkMWTGCgTpz3DzSkIWNekQ+NVUyeQndiS7U3pfQxnNt6ScX+5bUDwpa17Xa/UCy229q6VL4pM
VouRHs97VfrtuIaSIerRZH0JdUW5cLDWcNW4m34FX5BPG9pXmec96GOkMY1Pv2J36NCqUA8+ktDH
1JQXF5RiHRUWQRFVfaKn5fcJAN8aQneC3kCgzqxPklsEBWIdhCH2flkMi+SZhUd193Yy0pW8XMZr
wdS3+SFVmC5R+2yikPOC0PT8KjLnAdEQ+Ido3uS/pthpEDqhWkcM7E2iFKub2iF3Wy0vKq2PhM22
exa3rO6tns6pHXv6FKOOj0PJWrtrgUiRh7/u12Lz0zUfT+mtsc3s52cVgzH6blX7X4BSRqmStHwf
JhQfZEeOdEpM/56p6YzyZPDnOgZzYjl/P6SFMVQ3YnsVtgZZjHUL8XhVzc/yYfRqvJXnuGrEXKAQ
t5H1eqUTXRnzsQN1EcZWbavs4gNq3j6h9vQZYSGUbFu4fJdrJfn1K6WtmW0JJNe7Lw74k2leoJ4m
7qVzpyn9QdBxP3XAio8vWQCr/TDsidDWPCBUsWUmubievJNDP4gajB0T/+6sbY7xzH46FaVicSzb
86rVTUXc/pjwBDSD7iVu0vfGtEWPVYBVX7uuj1HbiAXz3xodp3xfKH72vtKZJwoirHXe40mVA5or
JONFwHqcPreKHmi+HydsZWYeNYcJvsbSCWZhaszvluhhyj01jmmwfToH0e0EjcOOsh65r25UsyCi
7pY7x0iyxnCKArfLkY/AZifQQ3uFVM3MI+jIVTqjH4JjuT8GeaLWaD/V4/CDbW+LWE6liLff9IhX
o81nfNXgm2GxBlOGcbiPsQqOSVJbkuSOoLnwm3J3OBwB29rotbABRpsLSMhDZf0mmzSYNUj1bkrn
t2xdj4VLQa4LOHEbtYhGVZDsQl5Cf6AVicP2ogADcjwPwjsEDQ7KgwOovyMe+KLNEv7UwX2BZCXh
7zA7tcVN2vnQ8hbqk097wVOTifegagwN3yo3FGhdz8oam+RW5fR/Gkzoho3a7bEaBNZIVGOeqVjk
WkGHRxNGaAA8S0gsYP3UQRzHBPzPGHANij/0sRx8IwO9E0SxgFrFTVa0c0XTjiUx2KrtaQVfFy13
Jo0DbdxqrDUUWtt9uZxIXsNU/iWtf3QOX3tide45rlCBNiPktmjNLNjyTLGVEck8VeiuLSQIgqK3
zJDnLS+cCuiE83YXglq26Klmvd8IQeWKmyR5W0U2Ykci5kwYhCT6Z9aKtWEp1+ffuoMmZ/9LVM5I
s996BX9ZTkuOrIGgXXgm3YZ39RV426ADePMiI6SE/7Ih6cg0y9oc1enG2CtQ6fi//3Z1of3hdtY4
To0+tfgxstTeJ3pkL5JmyqhYwAKTATiRpf04EUYWskvkCy3HMtW0afothEsvIGUDFnGGRKqoWA2T
lFujQjhdwhnyoq7MWRjPV9xnVSO/VvCNXzgKU7OjKCkeSscj89Ih8HvjyM0Ro+hJ91bxcQ7v8MyG
zeRyBqs+F37onqj2d9v7vQOgKFJB9do+TATDQeyXxTysXpN0r7zH2yWsdBi7GWsYilBuSS0QHH8/
wFr4wo0/ZV5CPZpbwR0wIJib99ByDLNT+IQRWlCL/am2GNRo84PGLbXp3nPphVyqui3ySF6sDgHx
lAkBm93AJnu+tEvTqGy7EYGAZ14ypoulFN7FxnStrEHTzOUCMdP5eVRR7yYrCesuT11/1Bc7btQx
zJ1Kv9cZ88BjOO1mUJwALuS1cyHWWekf4SAGneM1//gE+am278NrsjaSZoqcRsUkQ1fgdAaMX748
FxoMELCOHRUlWsS/Ehl8yoNh4r9EpbCoOWiNEXphlObFHTmi+boB3PLZBnV+juEpboo8XtUBgbSv
FQg5YA4j7ot/n9LN+Dumbsc1sLeCYm2zlFNfYEgh59+aci2X9dj89c2ree6HXwSE36KCvc/e/oAb
HVvz69i9b9eDnE33AzfWQP8sfDyZHxcPL3CzTcOCgG+s1qqzH5DrtRzW0FlmFM8eV5Fkuvqe6c46
xg2ckqu1fPsRmizDFiTS2E8pBGQbQBX1NKptQ4irt3hcrfeqXmbn8oi4jm5QViRWZT7NOymt5G0s
GYzwV1AJpTssd/J/72LO9VlJm2D/iqEg7FBpu7wD3H2dU+1/K+v7FAfy/anIVdDouqMGuNoZQBRu
a3NHeXIfz7V89JWSJE4FKfufVidw4gFzMIPijPChR4fz0eIKgMqDyGMY/YA/t3naUEXheA/OnW7s
QugiVSckC4s0GiB9Nc+HLhrXAUhGIg2qu9HYptBdJLHy2n+EEL2AaAMSDze53300prJ16+3syUrl
TH6Hpl9YkJhmrceYcKv2W+VIa5I1K965/OxYJhWn93iv4UM843UAqEVInArojnmYo4KfFrDd/5zV
wYydQ8xWcDWrdi8Y1yS2qM3T0mXV9u57KQ8+eHrg7BOjdPFh/bS2gD8748BRQxT7CwfolEifjxJT
MXWhOi9iqd0hQOYkmKxyzeV3zoMGHwJ2kdnNWbje5BlTKord07dmXn4bA/Wa1nMfKkHGNDhsKWJy
TkjCgHXuvlT3dZAN44g1eDqqdvFQ+Rf5/GeEsgOQD5KX6XwFAlzj4Fds4MAIjUDxy0SM/4O0P1UG
csGq2M/Y9v6eVIJjnqugxDyqHCiLeUKAgzSt3AggAhaB74Tr1JxXX3ZfOfBXwT/vDnMJhzKUL4ou
iWWnffiHqYSL0ny/zG88WtFkXlK5Slq9jHs/3VPgXXWGUCW5p97w0XSInJmeORoQKLCyukh32rsk
eWy5pFqFknjeCz1pyqgqfpjIzdXI0DObwhZGsmRHCdobae5YaY/4QSJD+XRr8QQJ/wlbW4Tj6bl6
F66d9M55pKQhXUev0qXz20Yl8gba8PekwjsfFQdcHLK8QGwTXBg2IJAq4ngYRClXW3QIowbX7wLQ
NChdw11/vyu1CsOdNBS+luMAdkGqzGkI2Khvl2JP8twIPfB/eeJKUaY+9FyToKXhn8lDCcSGmO+N
ViP9DaCP6d1PxwzHGhqsJTOwhGi8WKEhUvHIi/GHm3RuiUHr/YuaCKi5gjU5Cbm6UQHkVY4OmCqG
wtmSZiZ4+qWrragBSH6288A8aMnhvz2hS53Z6+uCAx9eoq3OW2OnvMJ9+0PD4RFWXZB0GsH/Ziwj
U3kV9Z5V/hkvnD01PeUZEpagvDY04SXnELTFiPxFZsedyeQP2A8j3j31MDDEYfF4t5ps+M06cVDv
dm3d0AZOEiEQCE9s1hHQ5S/sZyoKwSDGJEOCTUf+h3oawyhlQZMUiDSNjMZV4bJDdmF5ttwXyRjS
TlcCDzkP98DkBd+HxylaYNC4F51LPX686t6UA3M+FuOyrS9nhjD+gkuGBi/6B4XVJbklXwOGz7Fl
aeeyV9W9F3AWrb9245UAAX5BU4QwalihG6pjnzJvF5oqQcf5LObL7a56ZjwG+plObPapBUMceXsj
56Qrjk6/4IQhkuhxE7DzpOtLvgG36Yeh0158LZG8Sv78XQNIuJSY0dxWSX68pgy/UjRM//52zgH3
3PsjChJRI8Tc6dungl/a0RezVzEScqU8gQIK/XgIHBtpCctofMu3QvWn0oXF12fHLAsJFfQDtVNI
MjmYgEy+iQuDxMkSfqgeNNXM9hwZ3SFd4FrouPJTSm6326Y28Ex04wlcGULzhV4RIhDglQQsI7LY
hZMqI2qrvG9K/QSunOJdO85pk9Di58+sdpQsJCYUGPWkc/oonOTiFes2EgWEnHmGwe2y9+n6HwiK
2/KlpWf3NDbc4WmBkZtlfiO+wrgQNC1Gu+I/g7MVrlshPn4k3j8Y5xirFg7+wdK7QkqdsHRlIXEq
Q9hkGnJnIcKRypc52QwrDnCIc4VKHzzBuFkY85oAriiJeE6xhtVKgxHR2hMftNjMD2WHfMHhJ6m0
lk+akpHo5Ib3eWvXb9hlpaRIiLR6l8+70JLtxHdx5GFwehJTuxlknC/DmbsaeZphRSdZtVJRF8tz
ij8n5nd60AF4GjBwtTA+fNwinX2Euux/hJ8TnEsyeAUd9Y0KJG5VksUGqAB2tRF6UVJ3PDlRs3WP
3mzFofmwvcnGTCQT7k0/lhCSqThqwCAiuZpPHVoeKGqix5ZGJ75rttZDPDEL5uj/iv/jrakvVeqy
x3vz8uZ8xfpLHa8ahBmnUUjHA9M9em4CCwVxvo0RjIIg0BnWkOLmllQxnZSHgzti8d5vb7Htk8nm
d4/qj/FFdzq3+8QJkQALNUIrtbUHwm532fDrKefn+97YGEN0SzabbKWaZXPj+CS0T8Y6+YkHFnwr
/0UuSG37sSwBDSqnflJntG3//SUL3MLDftJ1o3CNJ7L2mTT3S8aIKAO/ewfRQGKGggG5mjXy7Mow
bhTttEarllnA0vYT77tSz9VkdLe1BJ2wu5x+Us/JaITC67I7Pr5o2e5ya2FPTANeWIpTmlR9fQSY
nTKZzpOOAExApSoNkeMiyfeZi2jZMuPl8J3b7bxtGpWvRywkru0le5K4as6sqoLc02XIq9ezWkNL
/Vasy4yvrCekfVXvBACjSNatifV8XgHUtmHdhspWWq9ROxP1i3vnhRcR808JWWSySVvz03FZpc9l
f9Nyc1qRrBdNGBYLGUy+AkAXN41oP2Hp/lNuWHn1pWLWBLfRbupPrBa+FhtzutIugEIYr7Y7AlbR
5JpynXYH7NmKO8/rYF+oS2Jli4AR5LfU9IUdqgtwXhvgQf894RzzD22ybifuthwsBHrWqzxB478l
YL9CY/C28Tdl1YJXqRKirK1xCLCi6fYV9xEhPB3sOeBbcgiJ9dBKJjIkzgvA9nzUIHeh4BzKyJdo
Aqr9qp8qvR8WL5Plzyy5pro4XsBCtl1ZQTUsbTVSBSjLk285ZmFM8+P7lLFcILouN3VVysiuZ0++
3KTLQP4leMxEx8dvd13KV/L38hEIgekUJgjsVceVHtQDlU3BiFvV2C6DcgCnZ+ntElrO/iAt1Mx7
16PSZQMBa7B4b1Ze8nzMnedGXaOln2e2ICbESe1caAOtM+wJRrngby4R5cCGqVE4Qbq475T2ZI9Y
wF3b1H7BqaVa3DfJ1XmN2hC4P5IfaRT/Opiwj4S1NmVgo38fKxAv2MLL2SDp7NOyXsi7NU4vkS7q
NdZDDGVzHi6k8IgJfPRw2nOC6ZncLo7J6+vrqsZ1amm4tFzPJD5bQ/a4cCw8WtIQNScpDNypOKXk
5k36M8RCf66oOR4lMIkr6ZCHvRisTcuQAQS0ujfvduOuIKZEGSMCVnHko87Nxoz1assmJuVJ7xtp
MaQiIG9UnFjaNBN5xAJ9JAyLeOD5Kl+61hHQk+vp+emnAf26aUqdNfh3xSNRbGnyMxld8tymu3U0
BecO/s1rHkYug57OWD13KLZ2qyHHLyDPnmx+2tYJujL80G14e+PypHSbhoxowyr9Cp22Z1gpsUQ+
5egqF7z45RxdjJb/uGhEU+uTny5dmsIAL+Lo8alZEyUWweXNceu+m1+1m1jDiLOBw/h91OSLyHyV
lD0qcL3RucRasZDCrs1qeXW6j8ObTTKTLZ9ILaFK7edjypQXSKyg5rHs0ZxhP6tVC32djZdMRMKf
qbyqvFFmvwioBXVM+v1VVpMG2hR/ayrEDGnM1W9dRKVVgceFB57MF2vcSavgq/QIWuF0NtscITfx
J4sfcwjKfUZQDYyEoFefNJzqKUksTCBrJNu/II4qCCzeeroG0SLWUVCXyep5pwnBcYtcRijULhjE
gsuFIFQ6WcL3wwDJih8XlPG+q9m39tGbF7no+iNT9kfnoSyENm/7Awui7ybyI2n6YIInqTznqx6K
xa5sYxFGWZ4BNxhy9axOz0H7cWsLRCTaG2UfziKrJMH27cwz5yr0XUQlWnWQ+jM8lLFo7P3F/xnQ
Y+vHChDTDS3v39J84+sqTK2TUcyqtdKKV2lq/GIov/pbHPbZMGISTFUcX6jcP3J2de4NOJBHJaHW
vvfz1CBPNAXBUja2MKeU+k0VafhqhYp7szqjlZgM9Sz2l88F90DMZWS2QCn0S/YuokYT+RMcxKCX
5064FtEtikhsc8PHhrbj1IGSbWeQM5qAfsCgDL9fnlxYXlXcxpua2TPKPXZ5Aj2qMl5I2Z8Ue3VJ
x64rl/fU5+A6k3f4v5m2jjcs2FzbiCh4uiRlmjOn0j3/wLlXD5Sy4uAPu8bpOYiPGHC/Rtm8DKbI
P+6BgOAi9PitMyvuavUWx5RT1n87XVEaKRPje4/E7i8dWDi43XK4xtOhoRXkBBg1A2bsa74ksbVY
iz/1oAzufB3nZpuTlxVDK71vwH+bVjj9QDSA96LEYraXXRlBWSwsccT5sJHal6Xh8fqslnlcj8xF
B+IfzUvp4l3pEv8GNGK9h1M57t8rE+8hKDd2Crn/bR5/6MTW6QsjarUIvUlOjpgF8hMzs3a/2fmU
xisxeF2Ev0YTwyy7hBqixqUQqX9V+vMtsq4my2OHedFaR7rOuSr8QDAQ6SZ7auWRnG1EzThaN7OA
y48Ss/R+HP3+fqGcGgAP+L9nTSe+oafF0R24TteDpHaFgT+0Z2ghGDtCIb6vuhV4eOJoGW/0Pk3T
QUTyWEuljFofYEUxa+CfPfzmfNV+Gq8qHeElfOOvDyJBwdQJetColqhN0lfmoEXeJegMEdxRE5QT
EGcrY8FtVRQNLLSSORGYP1L8TwMl7iBaW2SFOo9PSZI6jXZzHycfU+YTwjsUHmnVX3MzO05ASanH
4xyW0lF6V2YpwakvWaufwP9ZR1d9Y0kFFlvYdrXuzutKrZKm3I+KIh+6ZkMmHZoo2/BTDzJ4zzM9
8rVFFqlUYBVwJqk8LGVWIYv/gin5lJkXZB3N1bST8FdiUpkm6TlxraTgB3kSw02D/RwArtSIeYxS
Thiu4k4MAmmCARX+ZTYnfpy2Ktn1Ia2+UvAMfb0MMZ2VmAwqA+wIcblrxSg62Wl0205ikJz2OpoQ
mNHra5GPZISw+42CdYyMKrpCYB3Zb+qiv+4oIzja92bQZ/CS2Fhs4krg0KaRFfd7CwbcimWUOva8
myYniyEwzdt9DW1UGKOj0Z7YEbji6DFMl6BPyNkDLS4VefrCgJJ8oQIRZMPXkXfiuPLOOW0mNIYk
Jo/CFxJp4zl+M+zQg4Kf6XgkZjMF34EgF2wfPz+vlQCJfzdFeZ8bddhpLkPBucVFl8Pqy5iNwpQi
uMdIaU+GWEYxe8Lh+GqsS7cwFmurAbRpjEwbXng7/o90UF4FJYb3CWk91GI6bYRhtleklLB7zo9P
wOoLBZvZ8KPuY1rG0LsOpUh2+kaWOa/049MFwLSFBPbHl/crvujmMJVE6EaTSQjkzSVSvMZB/ART
vO9OQQziZTcakhst6wNQnIH0o//lD4dDlcsCcLuCRKddwxtZJ1Y0fxiW+fet8fxSJ128cT2SrQuz
+/utroZ7rP/bbPpACon16XFXlOTkUnm0dSPH0RhrV1EDIP2gsGSGKDu/0N7FZvv2fssD/utpNieV
c1SfbpTaHpjN1owUWPDdUZImKhOdzcfejt6zcR+BzingbinmmNDFEBqiv+5SdGY9Kp2VFDQT3xXp
Gen7v5rT0mraz/ISD65kc9jNjCBhwuTnT3IBzVO6mmoUARi5e8KUr9ykoanEl1zjsg1XfNn5q4+G
YzMoxNtw3Tjq8Ysi1XFCmF53MrgIn0Oou0OCpPYPKDCFOKeafjYgbiZ7vdAAOT/NE9ZKwgU+43zF
yVao22kPbrbvWPRGgZxPyNrYlSjO6nzREIdIfPTKmLeoyA1vCZ2+WMAM6txRXt1gnIja1XUgofkG
Whcs6MnQwM2kDAwfV0rElv+OcQS5L3MV/p/CFyxSnJd0x8OWFXF/5fkLx4V+E/J6KnENBY9BUhgM
NGzDw7QQAco8Yxvn89J24GbNL/ojsJ+iPezsPWgsjVaZDY+fhpN2+vkwGI+ftbzjj+P7MvDxaQvg
m0wF6Yg/n0D0tOj2URORJ8dEp0wexaJpIYbFsdUOKdTlW8VWoWd25FAXow7lPzivOYf5ANykhuQc
AbVhyskBtbdAFAobRQmFbADxkmKt90d9klx+4n6VU+GeJyabEx0GbxsZJ8c8d9XIy/o2tiAOoi1L
8SfBaqQoQMH/bf+693rVXA481byzPuFsxGdYcxsVI7oHK+yFa7UZA6fgc9/bmZG3BSBFDit/DZoP
ZBuxh0dSSkcx63dar0kE8ZXRxhvstYmwobxyxtVFkTKLgPi2zQ3yVv6WUK2Qk1+MKI4RMTJI+T32
KFkOudX8w2qgrc/NlFZftoEjs+zttKNijURolMs3na5TJj+lQ+G0mi1E0UuU8GwPZrhOOBg4ibOS
qjtUtwZ4a3OiwZE4YAySK2597T6hDiEJjvjnwKtIu5Lpx2faCjqjqN6knu9beUmVkr3isDJm68L/
RiAt2NqHoN29cB/gyJK2VGpo9aHbjqt79f5LcpSlswyTl99UL2fIC6ghR0F0Q1jNi9BQPA2JN+LY
X+r00QmD1ysA0Ak14AkymQSat60YExz6ROEM+AW2MX4vtjN1R4lXgR9YvcaT5HP0arwDrMcZ8+wF
r4CSB6I23IGyHAdJwAOSCYn/qxCfCcowmDJHHHsGcUUNUoxzpP81wk2S+Sp5nvHWA++eiASarKKx
Emad0VtW/OZMX73jaNJR3I58sX5cKvaVYsXLPhvDjr477sZ4s6UivYnKrrnJJPXk9Q4eeoOnxSoO
hiFIlArDgr3LwckaTJc9tzdBSVs6wUD8kQczrb/YaiPyHbiAhscZFKK6TeI/FnWlSN510rWE4gZO
K+QaeIeG7Jph3vz4dmYPct8LkYaXJiti1RXK7YW537JFwzcCeXE+iXsBjbs1BPEuJH8HgZ8OraPL
2rV+lQjYhx478/4q1TubZTBsCV5qbMAX5c2Pvmssyn+qefLOH9Y38QeEsdGvqugaWxNd4ucrMKK0
5zR9Q3WIS9vfAx8ApGcCqYZCnJwEBsVs4/dzRXNwycY/2250dXYjEyiHQ9twHQkFGFhtRG40btVp
/zdPd1kUTK+tnF8RPJExt3qa5VSPOdQ/RAX4wUhCrYetBcvPHSPXPs7lznNyWegO8lRWyWDekt0G
o9ZPExHdyJPXo10DDKChkrALOVBU5W+lQBxDgLKRdzyImLoGWPm8HPcGfZLm7UTRzJKXYeOuKdok
iTQv+hynw/axeJBtBI1teM2mShA3qljiEB+lz+38Zx4IXaGKiAKg9Q/Azt1s7JetOmA2uFiQSyCr
MOTTDYjiYL4BUE7LnXKMa61nmFvtrSjT6QiJPx3FBmGhY2P1o7x/fPoWMrk8RQEMCOSpWCVgr4xg
gsuxs0vPhjSUubL2EaehZEaEs7ur3CUcQQoCbDuJZCj0mGOzR7W/ILeYL4iFxUik9PdS9qdcmnJa
xkf3y0tmJKRfA8Pnr/znrGe1yGg9RhDzryfeKlk63ltP1THPKpd/LPwXcTf1oKHH8WyGhbGrQblS
2aHCyMNqxGoYxkt5Z8S7Kfyl3c4SXGL7+fG/ebjSa3XrdxNmbmuCCdyepT6BFH8+BU3nkmvR7qlT
87OSq4Pzk7wqt3CyOrQ5SomzYuhQWTZ3+vlBZ4opRuvMt9thrpy/6qCSYEr/9JAVduXL1szlI1By
oQ8q7o9EQ5FlikiuyVW0b/4WA4lQA8nPyXSNRd0n9IstmMUKVvQ+Of+S6PNXPl8qgzEYyveHEQyP
S7DgF4zVJ/4SQ7o0g3jLPZqxdNmstMM7yf0Pd7h8LRm4EiHp4J724wUo+xpDKVYc1xkA0aeUzrz6
r4/GTY5iRVHsjV3sWWP3wx3DAoBKVShzTXhqP72G6Zt3v3IQmrfOH74sndTp7DFljmz8avXWRrYJ
QO90u8M1LO80U2C4eqemph6+Bx7zhldP9wzjH15A5IbFlTxNARmelJhFqCjHdkmIYV0LxTiKAHXE
cZKvMu63NAngJ/Zd0lOxyLdwA3NJAUSQU8rm5yEa7gGHgJCKVCaBrAGEqnetxUIWw/7vN5W5zm9z
6DkOTiRO7C049E79O67Fnnzb1TXvSe0Yul6Cwsqb4Y5D+Kcz8l12EGQxERsGhH4HrVYxlZ2oCbXD
JgIFIqgGAwtwPpGo7KzneT+lHxeaq0+h0UXtMK557QTOrNqTMkMogVrEFw79lOoWpYBpwoZF/Div
ynOFZi8rWfRl/1yYv+gWHvbXOpoCJLA3L1YP7M/AxqHQECDw887dz3rUACzbdwCdtMGjPwFVs+fV
hI6WPR5Zg+iNAhQirpInbIu+UhwmqmMcmhNb17SI+FTt1A4XG9z16rK1LNpFI24Fr3rL9qcqVBlE
xXJSakm4Tqy1agsiu+aytDhXLDGSU72wQ1xM2uW6hrHT9ipowdVsD0N1wP/tU7dJQBRCqGQ4KExz
c085fhA40rQ/iFSSbhY5QN6jhMFmAW2p+6VRdEjZN06RN+4cEPBE3tVUns3MwQoEk3Sh2QovB7u0
o2/aW3sH2oJ0ZrtUoenN8CTldQffO76R9gItSd2kDUdRxHM0Ckqfvk/nZTIgA+gZ24QBwGfsjtU2
YDtCTPn9tauOzqSRnN8j+z/8+GJH2ueXl4lhYfg+T3HGHnWh2bPY8JMwQJFLPlzJU8OkL/vBQG8F
5AFvY8sh49hvzs9mieMt+C7cTYihvoGyt3iTogVFmvYQxLBfQrMAgKqXV2rYHDR8qyd1yaq2SiN9
p+6M74wMB1l2n+Oes4VeM7QLMyeoZl9znid7/c86DzFISZQ6mWpg+HFXxB5II+94K3ZevgfpUDY5
QKPDjZH+qXSGldd0ztQOxHalr4/iK30pyE9lAjGFydB1sZsRYt9LkIwmuVbFLidB3n+22auDN0Qx
pQDDt2hSYw47Irp7GI8ajMPM2UNZKlOm1+ZrkBNLaeQ4u0I8vw9URxYaaH29afWz22y0XamSVFzG
wvBNT82eWl71cFHxmb3NEzQJSlOuplHpnJWLaKT7YJ6EOhHgc4HpfB82Kc0if6k71p7v872o3+8k
1BKABbCk5hh32UurSwtzilLwzJg+AzmF18gbQO0uRzPUTJZ2wcIKXCMasy7169mh1Dp+tBaQ2ltP
064Cr7BTSg8WuJy0FKHusMpTvtv/UHsTSWpbvurpFRsMuzCNLYbDyjiR08R98/4/3JSu3IZKekxR
oOT+LhoAEmrgsEovvDfPscQXF7vltzusPduhqzsoQovIZqvKkXGbe+XckkF5gFFqksgOmhoXPgoW
4hsiszJtFIYk8kb4uQVXpDOBFR8A3V7nG/3mnWRWI5znWALTosm5o1xalx/JrA4dFTp9t3ye1U1L
BEq+fsRe46Ik5QIZYANYuNtxwIrnSJhdcynZLazCtELHwZD7lITKTSncRmvoHLmD7qSRzpKEgELp
JgVJLbQr01m3xLauvExLoIXDTGZepbs0q6H0f9VjgOaIEkeAFj6EZoeF92aAmiD8IEojVQr1sfHC
/sqL4cgyIVyp31POcmGE+vmqjpi0Qrk+xEhRm9BN8qsE1hCmRR51kuiNAQLxNKuUQiJQMTf+u3/I
qvI/rb9v5PHBLESzF3Yte68sdkfwDTg4T57V0WL1Xe6kuaNDy+Ze+vqlBdK5wojbT2zY1JkZFwRA
BiBP+3Je5dQcoFH5C/Jdfpo6EjyM7WrzFUl6/OqCqn7JNrq1HchCwbEJDMXB1Ajv7eh8OnYzh0z/
WKWb48G3UJ/JheryWgESur6C0CSzCeTyqgAcsZOT4MrFQWF71b2nawYWhVrJ1/jy1h3SVwZBhkPA
SyzwCCk9pnIoaBYIW4g9RJqgCkTGNU2CcON436ps0eEhYtPvc6xnwgiToEPgqvls2fCm5f0sMynB
TlShdO9N3q1VSYuxjKRyp3T7SzVNS9LCSbFZemp8Ckt7Y28u4aNJfHWD9ax/jXHR3h7az9o/8CqK
9zebirxwvvppnjWXE2YHAeNfAC/U6Noj3sTp90G0in6aW7kXvxWh6SzdXV1YQkUFgXR9rSpshPsd
MKTygvA+t2JGCiRm+a7BSaxeFMalVDKMaMxhK+0TnuGmaSSqij+hOwyAEC9C8tYt/Gam1FC1bcfm
BgQCyxeBiYhSejNpODn5ugMQCTI9O3AdFCg81I2/qmuyCTzZFp3akVkH+oq5dD6T0zvg8iHkI3pL
WkQjic3jdKVrxQQBvy37pMhDwdXPK9331i7PZt526QCPlWGn2ErkZO1CwEQKNRwP1SSNw+rGBV5n
pKa7tomlw4n3aLPe00oguKaliXf3iulO/GYzsYkU8/oSD1y9vdoUr2XeBR5mxVGFGzpEyWycCVQT
VqyOp4cjl4YpCYk9DOHBJy65fISBBeoBTicy2o59ipjvfmPQa46O45gsvxII+BLZ9BuC5SjdopgH
RTESDKeO21xD58WYFDrIeiupRkEBn2tc64fBToTf/GoQTbmsdS6jzgA0Cnszc5+9MrasJgG/bC+Y
MDr/1dG1mzY1N4hDVxK/H4xFoJS6NFItsgaHLhFJ7x9zBk/Jc5B/NZvhKEGn/XFVc1t1LGFB0qGD
FxGLgDLtWI5x2nZ+43ANrS3iH6UxYONJ8RLs3Gbph7vH0ZZ/S3TuqQBlY16rQbpAwX1BtaShiccC
rVMvrz4x77Gurv7WmR3Lo5M9ZI+8Wtg6cw4q2GnOICtD/z8SbnjaBKCzBSLNKj8se3Td82N5A5pR
IPsepNJ9hc0jJaL8nVBV/7UQwaV+Ee9OMsrz6XizZMuiG8CRtm/cSS91Uc+IxDnmrQgWsJ4u0pXd
i2tcTBi+Z3SAKskuAWtCsaLvtYr66+FXdJBQJb3dZ2QVaPc8g+MYJkbF9mErpSvAv/ZFRB7kEbvz
Cq583pjgOpC730FOuY4Uc8YTHFXYMR6mHWEaSnTSqRBKZnfNRyjcoa7Q062kypS+H93q9H0cihAS
vIPyFOLR5+iIRaCCsNpP6Z14+vUk1XB0A5i6ZhVJMy/+NWXLhK7d3rdU7DGjqHQa/6EB/sKBcS7o
EvfAFx4PLUatOFlgcDPheLOgqyu5qZer68EnPVLX902rLhxOkdOH8RoFWokNPCvg/oZl12czrebb
BGBwqMpn4310kimU9B/mncn2H2vKT62R1xnOQBzvgyt+0aTZn+KMPf6EQDUVnJIhIKc7ykSVPYKC
SLhLy5zwQjQT58p0UtTJ6nAUswT4QdtbpY4s+d/fEoINHwAOhNcVkuKbXCqUppYIPdleD4MM2ddF
hjADI4x7Nfb2bgqIc+V33N2DymT3ZKDYlEVG5Av3xfX3lgNtI1dOwjZQTjvG6SwqDkkPvitd0XN+
MD3xpVa44B4kszKK1jYI1X6BQ5EjqkDpCfiib8rroK8O70n//usWz+Vk9IREGw7vCaU/2BBwhYRt
wdU7x0lx+JT/xrnYkgeN7Pv+7oToFPtR9hf/SFiM/knJRYwvhupDVXwLAh7CiTW2Hno8tgueGQqm
fGZsHbpxpovOAT96X0N9yngNhnZW9aNy6KBUCeqM6NSEgebD9vOgbAfX/uCoNtyevngz/I5EDvL1
PaNLuJy6b8tC6LW0rgs9vzBNzzP8lM0U0mjnpDKp7oJlxyOOa8P9P2u9YsifoLq24Zzj4VrhG6GG
f200yStZEvmK30sO1DM1pkW4OcNMO6gG1b4cAwMviycvHrUdDQZ9Cdpho1wpAisx+0srJLLT6XZa
m8ieWemPv0Kq4sVgTErq9Xp+uX6HWhZBg2MFAjdv5hAfWnFl1/DrHC7nzC4UVbftw58ORDGmPdzY
CMLkzwsyisYVVVOgzhij6pWvZbLlvV9CdiO0nq7LaQbQr6BuDAExmOQl9bBiZWogqfZ955OmGjM4
81WuX76A/fBFR/mS/+5JcAJMyg5MOx0AqsTFrd+gzuQSC5vdMtswB2xHWVf8Y5ZQfPr7u21aN/WC
/cqRKQ2o5RaUsUv/y6biaGgCWdrTHplPjHgE214pX0BfU5igL3+29/rV1usWePTeuVoi7u/b4sU0
2ik4OADCgQMdOrRUrYSPJuL9cSbn8S55yM0crRpaOysq9xjoDRgO1rKgJF28XvXi4DjscgYyyjZJ
YqPHfo5tbby+5IiIcGvAqEf4hy5bCv/hIDV9HfIxqwj/s2dnO//jy/JRAZcnTSct7M/E0mHcuMHI
I966OqHRaLUeWClRUbZN2fPubA6llECD1zL5eHAJzVwNj5OE/0h7ErOJ4OxPZSw9pod6VRCL7lwJ
/0RanPvschEYj6s2fhZeT2mvB4HoOarIck4nnxSvHocrDbIbvSAuzALRrLu3S7G8jmQBz5t8jS/2
3ghrQH5WzvI7nDnZV4QukMpkdRczYN5KkL6II1uDlNsegl+SNhU4HTg+mGcQ15iDuDfVsW6oNZkT
8/ONS7aLj3t1LCkrI+q8bldp8hQEZ6wLzDkajdGnwrDfdvFRnCbpukuXHTMsptU46PCcQiDht8X3
ZjICIrRTwvhGvgbgBsLRs1kAP8ygbfa6jZ2vv9stSp5WFy5FmcjP/sCrSCDPKG0G5AHPJYt8yApJ
o4240LwxqWBJOa9bB74qUQxeqcNtnHTvhBCzOyWedZ5aRLkk91wXkqlEpBzP14wHGB0h1kXj0yTA
U6ofRd3vMvM7namraA0AlATYlSSk7+ro2uN8px+2kLq7FMgsqUddAKWP3I9+TIU34L7l//x9hJQF
cINflrKHVAHYmqXnRtn/7dDNZ0jB+a92tnayxM6Xsg60dQI51LJKXqLMtPh+Yl9HmtWtbY7FWGM0
l4ilZUhcB1MJ7IuaSM8PdlkdmyrTJMCk57AyRypUIXa9h4n5yVxoOWFmpf40eV+8SB4q2Fe05dVV
BMR20CBnEGyWTxGyHhu1NjIGoJciOFuiZJYGurRbZMV97P+U1UGnkYETr7a8lIgq+IanP3u6lMY7
+xI3vOIcHhYIsDr0Z0iqWfiMk0OTvzrxvySq8E2vaLTCQbj8dV4PxQclhT4MOcR7cyY3BFzJnNCz
wJ1yWMI7LNpFQLKNSrFzHUngziCENh2pVpl8hp8bYcTzFiDxveS8YdTh6z5fOR7WmbPm4T9IIt1p
APqJBYBYN9mA+RbN5IBCmFxjMhgmhyA+GYfvmPYNGJ8JZe6bypX86YRvQLUWVTSgHxzpp8X+kSTj
CgXBd0Z3xkQSTKEzxcmx4/fwrLE6EOGnAJtm0qtMmWvz6PpSCdLshF8A9a8IZKF254L8xxEiA5WS
zaedZ2C3JTH92KibjmPYQ5NesMpKV0nX3njySFnVSauVGvG9mZ8jJL1goxr8If++0pObkC1fZ33c
HkLbRekk+KD6jiXs3q16JzMmxcUTjSAqhtOTGiDpREpo9OoKM4BUabRZF/tcYf9weA2wymUqX2F+
ROjO/+yJh8NSqrjkF11tHG/4ohmDOJ7RB0xQIGKxi5KnWNf/2rzEG4sYRajBOe2QfjUnxdw4/Al4
q18EZh82ipPBvTg4K0LyKpsHhvGuo3e4dqBGcHJtXF0Q4FWE2F4mJLQHsljtcN0hW6VVVKgIqYsq
HOEWVvEy7PS5WODsXis+pz+sFgVqIwdxN34aBQjF0L+NRO2D5mdRauYsL0lsICb1NC1k0k56Fha8
5NEQDcJsFlDZzBCzjpkayuOl5n+n5Bi3kDX1eFJZ+kEXa+d81FNappsEBqPpMBtvOWtIUJJUmsQh
m+Ke4yXnLQS/BCxOa5pimnI/fWLdiQoLLuyENmyZHb41MoVtflxPn9cqoVqZV6XQdwn6blqwtGkc
XVHnr0fI48rPc9NirEsIQpL0NuZbRbk2iqRbmEe1vNUYtBDo5pSJlyKgH0KFCIAagimkEC1jq7D7
H9+2dKEUWa5EH8Hgn1OU7nuR8wwxCYDPwCLmBHKQriCl5C/1PaBALEP+CU9YfY8fV3ARSKmeexpf
PPTvmnPJq8JBHafAKqKOZBzs1bV3G+k0sLl0qDnbaXABgQN/hdue06RMRTgpGJgwcMJtlWUKK8w9
0dpekGeFsB1hLThj6jhQiMkg3+NOSOV33hiIY9JjoTDPcyngOTWnkvSK7mfXYV+Rtw8TsaCYhZ0r
7Ulh9KX9WD0tn7MaOPEEaZp9nQwkX+/MWYF/TepB7Vf0lhPOuK9u5nVOXNC0IdFwVDscVIh6bPgK
jQxzLTgTPWlXCdYqGm9jHiNfgm+qfbvA39Y+iTzl0yKto6+56s94qI/AcE2ZcWaL5kl0wD3exlhS
ZwArfxeNwx2Jy+m0ZZ0M8EZlVhq6hYDBtPUq3OqbTIR5Zt/lmYDo01YNKhiKGwJx4PCDTsdbFciD
l1BHeGprmiTI/AoCzXb7Cdl6d4b/DpORj1ttm+Trxyz3MFN2RV4LEjVnVAWuSX2wbMyiCuTXjwG/
QGFeB2BYDB4GmkloaxCdmIE9Rf7LnXcQ6464a24+gqCrU25IZ0uQOk6jRkuRJBHikbRdKZwWHLpW
1peqJajN8j4rLItlmOR/epd6oSSGN3h657QC32MfjVdk72X+Kl1fRngwkO/jetjFv3Ex+Ltv2og6
qvZyNeUFJdEOh0lcoumlWICRPQZyV9cH53MBMnm7hlaz9+E/zUm7be0N6hBgBFwEUdQ/C35z5ncp
jum5AogrcSyhrfwJNTCWKbvNfD6cY9QVgiOl2nMc9TCwlUhj11GcIeoPlbQmpLqgdeaicUIloo24
Ssc/zhyj9VglSU0iEzky2grbnWi4iWGy56mpg3X18yscCSLH646khpBH6YdpdgZaIE8nOeF0QOQL
YNSQBP3MdkFAlXRiVEmbrIGYTDIpGukSkTSL9h0aAq0c/gec4WnCjlGrfBU9cNW4GyC9s0GLcEz+
wm7NHJaAMWvH8dFt25jysgI+1NFY0ygm33AoGrE6Cc8Xz7510LmsQkNyBR+m0OqVIne6DOIbg8Jd
wDOO9TYmuNhka3er6De56cI6CpVvsdZ1oTOSPnR9+IvOFQS6XB6LzkOqyl2BcNWGXvKWOuviA7SM
A+iKRzNR1I1qyBvZ4tl12VnrBBJAeWLf4I/h4Q7OHxe2Ajp2nOGikywhA/hl+1lg4kGb/EvNv6Yf
Lm3nlDVyXCLTq2UZvjTQxXH3Qu/puCMyzaFPI84+699jAbG02D1qy0lt8LyS8gd5uc1ureuTHwTB
Jor0TS3pJaQpHsObfR3VECGhuoZvqZzvkQ8eOWoajFJLupbAh3cQWjWFX8JNalKiS/RKHymgq1AX
RZcqurGAzLY8gh+Gdbd5RTrhzPAaxoOnjw8eT5qbJRMLhpYJ87APLa8R4mWi16JXEKi0RXgvMkTp
1ZfYeHDneIdQzD8SFM87gY6J7cPp2Q4dzsZfPDpcYfCilGdcDRH7mLEKS4s+O5ZcWSllBFU59dhx
hOiSyuotgIU4MsMqy85aU0Yo8/8PLIkR5Zf/1uagFB+oM9OYPme0yACDBYJJIZz/K8tuQbk0iSnh
pBu2NtRQpMg5CVUj6lhXRr5jaJC0cu3zko7+ogA97RZnMbcD/cPEaklHYqpAiFBlIsD/CRy343Hc
1BWjeWRHRKCj8KzST7q39wPZFLF4L8UZo/ckYJA8tZDHLlGocpZG1aHW/BNpReFJJXe/0XWPc6US
aas4eBib/pCwWP896LIxcLE0rhamPz7NGrorzKiuFKskysvgKuUCa3ts8fuDxwbkRcnCyZ3lVjjz
rq1eQnHTeYpBPFBXQXDxuekvQRwMAfIzHxuPyxDc6c7xFow40sCNIkwkw4dnmWarmL6iftts53o3
SsKZNntl9AIR10ESl3tfCr1oCK+uhShC77SvAdEx6JC3RlH/mdspitoP0FWswF+xqYM8vZHIAxZ3
BJuzmFDYT8lX7ucvM9blhO1XcBAw+9CkDYYqZDcPavbiQdMsIYUFv6LwSKbD3mnbeKZUFEQxjeFe
5lQPIyZmKQoIUM9bp2fv81Xw3K2jcqW5dFe3zMbyof/d8g3+DXaYYy7l9sVSXZAv7v/Gi986jnbu
7mVeSKjVTu6932Q4EGwlCor1BXb1bmKGBV0K/Szzo5eTwOI9eK3/f4J5R2cFZitn5A+JT4ejVkyo
Mr1V5MqZDZDGx/KJh7W3CmafXG/2di7Q+ZZJtyangmfXguNDyEJPzbWVscq0RaLuKOrHtbGRMiVT
1Be536ha4FUqLbDYovAdhel3OfAxzaLZg6xN7Gk3Gp1DwyWkeCkR/gm3W7LVoR1ypCV39XHnpNdx
/Mzg/k+E1Yw+LAaAeV7+U3G7CqWI5q0zD3+3latSy3X9EcRNL0BgIjnJcLlTfETgWnhzvHFE5dS0
1xJqVj2wVR2ACxlDxiybt39Qmz+/SjArLq2SzRahn8r6mVDaOrgPfSg6btoAMiYsShi1P6f3tZ2y
tLExnqDLpdz8Kh1dnLOFvR30oU7W059uwqil6+h08+UdxIMmxUOw7Mev7fnZZBpV1cVz/X5nq/C7
OFec7VwYu/XR7i1uuwzbzWdVr36EcTBleuiBJmmyZJdhcXs7SupKwEZm6zuGAkWChiQZAi5Aq+dx
PrwDJq4S27boAiy+92Hnhma+yFCJuLzaIU2YWlSme6y1RIPOcIYvlH9/jReK/yUmb9xOASN9cm3w
uTLM11Orq4795nfoieODLVFiDjvTF4mJvOivoC1c0SRRkNu2eJI5MBBszM42yRZSjUB25bT3Oa+n
OcAQzb4PPME4u83inWmwJkdJe4qVMc6hWmI9QMUzaSnw0tQOq4ILjdHNgdRPlFe3evANFfqQpFV6
n2KNCvA7F2bnmyr74hqRZRCUTiKp9Ym1frNAj5akm+rNOBK6eHeeHA0TrIT61M12LUKTROxgix7Z
2lk26Sf6I8oDFKJ0dTBGUBod2vXVxk+DqaLR8JCDFrO1oyRMjSO1aWYRJfbQvj2mW/hiVUxFNRB+
5fxUyGO6wD0cd60dALzSmqFm3PDyQ8nMLS3kkax74MPaJuecMLYzEi7cgGPpJ5f5x66wTJkNkCD3
cr2CJTRZ0oAFv0JXSrZba5Qm43VgxeaqxsUhdJyx0PRNjoE/HHCeZ93M5Kew6hvr5QWF/sSm7pg8
dohWtEw0DQS0WePdz2aGsaBwJc3QJh427CJw5Au0iqwhA0hc6Y9aZ1HHoUTqHPk5axk3B0ODMah7
69m3AtCwGL4C5ASaIWWHPgnU0h8gBz7stU0U4bF6LwQpwouOCCGCGX/y/DfWJF0XtHo9RvoU9H1S
Wu/qvmxHtuvqeO/BA8cBsJAApxxH5y/uWhlnn+Gv8viRdXi9/z1L6V5T39T3uEQT5ZWmb7zwvvvM
FaaA2tF9lknJNFCOVWKnENDdMVuuDnyv58V3EFCwmpO8gXudBskFyvr8S0syXV0k1wV/4N5EqDRo
qf4v1nfBeYvOBLhSIBnektk7yi8b5kWjSaEOkEI48z+usSG03SvDBcYBRGF8P6HG/xmBqMbIpq1o
LiUnRQZtEAXJ3L5BWLrY6TFOb5FRBwwGImDDi1bG3yO6Gj1gwQFxC16znnTp72oXyT5q00PPR9sG
rXiIZcoOW5RG9Y4PBSQ4tdmqYLsq8VwJz+B449Cke4HqDdUTrycJePe9Gs90PB5OxlzCmLYxwFZR
3DI3Ha7+xHcNvI4zTEMnrwckOraMXLYiPl9g1siYOpMLfz9PMhQmoXAoQEH+0YofZg7FjBT/CpU0
pM25UoZSWfwXD8PcQBj27IZNxQ9iHFxTJPz/IXwZ0kUw+LVGkSn4UGlGgMPlLVHlN+fVpTtVBv0C
uNAdk0kc1U1WrjxAhHC83e0HjLipL0l68boAzOCBmIsfrD0+M5DDxMng6szjYi7kcj1i/tCu7EU6
+jRutfa1CrgMdjLXvZswxEclP/fG9Dn/dQ24Jlac7gwxp4+oDqTKQpsUFdE+gstWYwtdjlbzv2eO
T5J3uwzFHaZB7yB7hZ7jelxqFPy6wrfPn6IYHTZibpyGUiR5HQwu9BPkKzdATXsyTr9GaCl73FCZ
vRAKIykmolpwRptH3fbqC3BpHOX6JFbZJG7zq34jpOLyxzwk8vrgykdAQcYhwaeZjwbcedZdb8H8
HG6XOJyaawfjaTwxS/J0yandnp+ejaKk7V4iycjB+TDUAQ9mwnD9Zj2L9BF0KovCwynb7e3FUrZB
E7oYFh/bcINodWB8IJzW5vx7nztADWBU/vk+uibSawjczY6WuAz4nnzY3tFq8StfDxYXZ4KysaRS
oTusygqnO1mWIdARIDTL0gu+oOvDV6EhUAo1Ry+EoSAk9lz9Q7SwjYXgKCB3YWZKe544oUhKZXVl
5mDr166t4KELoH0xxwc1Z/In9VoOcPhwlMjwfqLWSTlf60rm+i4doTm4A4SBF6D0CXOxgXNU6imz
2dw7AMCoCkZIakngkCJriVkVZ31SYc9/OT4vHEUrXADGKXfSVxwg1W4X/p0UFHYXCslNcIXdyU5m
JkkDZzPokfNtLacGT+6r8GWJ8pSPntSEMHAVE+AIkZuefXkdEjGTCdCHWh95hmlUbtYmxgVWrgWO
NVg9bm7MPVpuKSUT0/gjyooc2839+nkVt5xK4ULCPJeNcg9/FucQUzP6bVigCgu7kl9CG9PLZ2S/
vm46WyqhgrZii71x3jkMBgPBo3bEPIfpFO+/ujrw7nkUEuolfh95SQh9DIijovsugPM2vqk8l7iZ
xvhBdIpIi9VGSnCbZxEDHq5L1JcjWdwxvGFfAvig4yLB+RiQKHkrCXu1CWsdClp5uhLcsSCFKRlc
kYExspGqXx9SAKm7RJFZkdAo4ZwmgbQnS25udkSbvYXAVq5wo9upBdvRjkTU6aYtFkT3sANN+EOq
kLGK3ynuRlZTIIqHqQ0/K/WSF0IiMxS65GM3LwRnlqhTg55rwl3PSWBCOX8mLaxyjv+0BHQuZWur
8M+RQfFhIEZQAJoky/M9reQNE0HQ8mevoyOD6H7H41lULAjKjaBEIs6kbF+YXMVO5IIJf3CJF9Yb
iVpzlNnUK+PIhB3ncO8VUs91ZyrvCR4bqDLlcWS450cUT/Py7R8ky/ZVc2fBJv0Qbhdb5e4hTX2V
6I2lKZ9S8eiNVyOUzdVm8hgA3l0GyfKtMrhcM4KLqcLA313/pjT/jNVPdfUxKj4GPU/gZuKUzm0A
WspsA/xfKXDBGRS0jE6kxFrdKbBT/amI2fcKQiiBP2UM/R1a/ysiDgIJsbXCAkoKr3i44EU7ZEN5
369j9mpB2mRM2JudLo6Bq/pWh0EBaxpAnHchyPiTzHjU3klXFbC0l8kC74UivZawlhr47L4scBCp
y1eor25q0NSXuDsagZh2pIacvzTsdl5zPXw0Tq4Fc3kqOPbBFqAtgVEHVh05xhurbd2nbehm9v4/
Ri21NNSoTBGtzDo3JBqlHlBIV/GUvA/tp6Bjv2YlH209ocolWYh0QG0cU8t6CU6iN4XaErcx1qSy
KpxE2gfB7zRHV38+N/bLdDQtpbE4WieOWhTVyj5pBYBdiB41exuJxmls32o9hwXwalwhgBncRRoO
axxfLirHzwJ1Kb0FokFoYqaWkQhOV6p8gOd/kta2M1d0P0ScEHWydWRXOWqygyu8KvbS1mBy0Ise
tizW5h4r7eOVax2/yj2Zi0gEbLU58WUpNyY5lH99+omCQAYqNe2/YBTpGQU0326QkLte76KGd08N
HlVhIlozMk5+o2qys2CKXaOGUxCvitLJn9pjedjmQF//NuFzRPtR0CUwjfm5iblqylZgH6LgfgJn
SHfZZyVocRmeZgKzQrIl+zgGoJV0ZmFMKkk8AFNwb7QwcZERkFkTIZe8UO4L6vKmufAZ9jartUJP
lcz1F56m7ineomCE7R+xZtI8VAhwradwCBhfmQv2ik9yjEq/54bYCFh11e/SWL6iTqKAVxgpNtKs
VHl2oaWz4Nj6BBgndh8zUJFhXXUawYhxN2qW0A6wWAK5KC83rE76JN+lA6MQ5pc23yQLs3qHs5vH
dVRG2Fg5rajaZ7V/qFBFCGpKdyXXzZVc3UTXUr1DdHyB3fJW6huwIHXEmCabDLQrnImwYP2Qvwrx
Ist/qTm1u+ntIFARLObTo52NNYZ/eImdOjwBcrm6xUZ0PAmTIt8g9HamiBzQYCvIo0YrFARWzZws
cGx71Ww/OHk3bQFMq4lClhopEBW+uXfjdzlhda7+hrgq2biaEcVBR/J3G2071U/oFgC0TKtltIsC
MNC6IZOLb1E8wGM6fU6o9OlJpicZVxT6j5am1kKWCLk5ZrdOx6pM3DyhuTsFimVul1QlDjyIPi3v
cXKCSrlUKW1qFlkAhOw8Ce41HbSOp6DbvNNxZf6wn6OIXqIkczg+VGLzVsogfPGWx81h294tCoa3
+KHL0a1ZGUw5WzUMzkQYO3/Fs2WDVaTcQYvxt+3LLgf5r1o7+KuqOg6+Rs5aXvWZoNPTEKiUbBOo
nyiuWNrq9FOa+4gDVFwEJmcsVOQbsv3K/dXnb3TjRpDRRG3I2JMg02ZOwowC3sxwFwuCmRm8bNmk
ta3u/w/EhfbikPTjP06N+s09Gec+/YKIQhcds1d4GmrUPxRgVq2Wur56NiamRjZoT5GFrz3HzSqb
9BFxHQZuCIoarHdKli/FJ1vIC8xQ10GGxaO79f9P8bpef8OWhPcfmvT9bmwc0c+YUyfy9GP2lN/o
73AfU8PIW2fdCkglgXWjf/NBbTiAKjYNNIwjFfe88c6JJHQv7tnNUKrREfFjfxipKi1D0Bs2s3ki
SLZESXxBIqKSGzHeMbP+PlRryNtcodax+5JHyJsAIHH9RIdoBUY34hNsW0MvHGjaz6SE0zLmsL/A
CIKz5NDzfZIkP9Om2FTRw/2wv2aeGfjLgH6ZuL8nUkz05LOpRPDpZNx04FTvxWZEjjUY1p9IJIEY
ElXXZ6YVtVo3TAVxgvACjc0rS2Pw7CHLfWgGNbwSZxoqbp3GVRJ4iecjbyyqZWK9M+bpIz0qxP4f
aWMOxKDpg5i9wARSWaesggHzgEjW4nQ1GrELE9G+t4560z0oURrqn5umJw1cV8AAt/Hn2CCtotMD
bkPMfMjqf/y1cF4rLpQ8FWguZJG0GZTrrSLIMWmQ836P/CUVlTIkuKK+Z3a1gP7eN17AX2HfLoDB
RN74Qd+R723kKI35ZOJ2j1atAD2VwaNu0VGwnM6rdVxKci0Gg0WvbY92T9ZP4qX4U95HJ5rDYhGr
QSpsGN6ghqnqAxs22J2aKxQ0j17zefxUDUhcOnabgfvkDjYFvHfxaC7ROLlJr/DQo51qh4sOErmQ
3VPmFtpU0O0yFt5tVVOkJkYPQj2bFDSdnbFLPpktKLYL0oc+4Kd2PL/cUj9ndvf/+/22nGCIIZ3J
ELHlakuTNuBGI4KEsv3BK5MPQLgyX72K4Y27JfeBwQY6Q70Ok2ly29RqaQF9gfXkxcVC/S59XQck
mXMHiYuvKKAhH06g0GHA9m516UTFYsGfSCUURqmExWiA/u35V7AjoIGMS1tr3IIICrpVAPZEO2QL
IIAqphJMdgu4/FIIgVt84aDBpXswJdKgl1c9IJEcROQxZdX5gcbecduDlFaaLtA0AbpkBZFnSOc7
Bhh0zvGaLeakBCmj+BDEZvWxMS7qvju9zejjU75i9BKFVn2RTb63LdaDiz1gWaPpsS0MWb7tzs16
Bw+CgNO0TsOUWUZwqB7vSITCZHCGFw0Ek67R/Oi1bhoKawxnnzF5CAgMb2XCGjh6pK1zoyvKztsl
zlDrygdCdDKvAJsgv6n1chwWfDkkOfISDcvGtQz6DqHIJgFrlvDnbYJvx0ZRxhsNhoxA+0YGPT0r
1g2+6y9EJ/g1tPEkGX3zhKKN3C0rCDtoz30AlOas/T3UvQbSoH7ZTOSH0mNtU/LL6R378+gWQ20b
KsMMJe+wzED4XZ8GkCnFmkeNNVBCBkT7QLpQfN6VSInOeXswGOJ/tyTZEP8RUrMm06zd3IkGvKDz
qRhpxKSoIMbrDWlbPnYKTe85mGYKl4ENveJGCiKHrxmUPomLxqd3IWtiArN3PQ4AoafaSLifdK48
KuYL/s7OL2WnUs609aAFskSNRYn/ONbq/apy7hVs0HRUmVl0jOtDkcDtgz1BIBc+pJgBvTY8OBJF
hV8Etj3H+pwMYxas3lD45AH8W8+TGkwSVjIu4fnY7+a8Bo0sdLIARDmfg8pCp+6YT5ogRyRuuAuH
dSKlQEDZillmPxo0IF47fUC8wPPjMaj8KL5ssuNdL4wi5MY0qZ0hS7SHr9vxrEJi68CmUeKizXde
w0W/E7ZmvovZHEfrAhmNDpW5VgK0cTK1uTvWtNWKEBIVXgniuGHIyaL4niI/vd7GAKJlVu/kkEG0
kXWQciY6NvRqoku70LKesw5ZwIAXxe+A/1gA2/c9DtGX+4/PoC9HZbIXQ9/sJnQNgGwUzGhDhyzT
jWcwzBaNGnkXldYHyHXNQw/nlK8soEAzxjFYbQZVib2NiWv6kHHPF9zBIBN3xDM6S2tuXPxtqyj6
NdLuZW8Qsx/68/61MEbq8u1vJSxN83uZufFwAVgKo7LzDZNSYco3qiFb8zyjRWOkqAKbbxK7ntaZ
G7ZFyGlXmsgTDdnw6ByqGC5XtVStE/WGq9uPHU50yHwlXL6n/eaZS3IZNKVX9ESu0aGJWnWFPRiA
U9PqnyQGArfrXi1lJ4jNMKaBL8nrKooMeTcdHnQiStu9TPD1ItsmWgv1bb4WC4OtCJqnAdy2+v4E
Qi901qCVgiUh9kAQuiGWu8diqD2/xh8sAapjYed2a322YO0IaHHzNVtpq9+LqXPE24VOsKkfYPt/
E98TOCpygXrLTSQ4ZphN1ZpX7ZNtmUI+KAPrLcEKRlX91Mml27Q0r37fNRIzBL0o7bJ673yvzAMN
0bouHfJYfZ1ZpqKE9PTBXLswFuv3zOCW06lqhMrOb8yzwUHiTI0+lR9jgs+Vyaq6cLlX1cOMnpll
CjfHYnPoT+1gk6AHlMb17Op9wqiFpHLFMyzz7IgKklGVXrHzhZDoKCodFiIdOqXONcfq5XIcj3Vy
Pu63sjxNOgn97+iuADWsaeK4L7ea/hUjurXJpGNk4AonOHc6nReDMJ2DHeu0z9qAxRQ9LegV/SwR
tPNeQWsgL8WFmvBXi7QWB72eWHoI/Ioq2VRCskuNKBstxsK1PCxC9YrCFQWIKqPNS+jIhAmEXy8z
7lhQoomAg0FiEcrkwIMOUfMar4Ks4r81QKLOwa4Za4JIt/X1n06gnRD48gETpvCtsSYTd9RzZKi7
34tWpwgSgAUZCYZmrmzFKBHkFifas7YPmcVep0g08ACqWQieSb/O36kuDuHe9nNFcbC1AbtDUTLh
vyIH/kVHIdumL5VQufxg9YNiq5ANR2WeG0qfBe7H1Y26uKkVX/LGyhozocR0tjbTSgfGU1XucUBS
ij3yUIvhyQuwHrv8jd/wvpuY9iSImLQlzRvmzWU/NDYElm/pOb4zPb/yGtYvBqJOkEbBN+nCG9lo
irw1/J6ept0EEVDlKdnukdwjgKUw3nR3u5fXtnWKuxtrhUfq96a2q/+xo0hYnY9fAmFl93m4SZa5
b0lFmLXmmr55PQO0dJ3/pa22xmUvM2K8K5GY0bLGGc+y71i7eRc3CoF3sknZgfmTCJghwaowKfLw
8xlaqBtH8tViWKhuzYPP4AYPLJigUtTkj/trNKBsnIpfamkUroGB4LnTlxtTwRrQTtwCU4t6zz2F
s7pF90TK9g6S6hd3kBLKnq62fVwc/L3qS3v/GrEZSvwlwKEF33lFKB9jQYL1C0yeppBOi1d7yatX
blu9aIcMx0qahPwSJik0C+JPki7hWCyW0s/rOU1Kd5Nk9BUijG20PGOr2rBlIR7ehmdvOQbkH+8Z
FXUIx2HlKBZCtVYj01QHqEpfeW66t9xuhenoWOtbznStqljRJLYlckOZLz3feWBHoX4hwTiTYhCo
q+DqyCF65GtzYto4jQnYmQjw60GYoNXSJJXzee6yiUTE4AhPZD9lLoUs95LSRy3qaH2oETNoeQ9n
LW3uISU1Fl5UdEIeTR0YqxJ5JmBbysZSSLMlenNF7BAEpFknu5/MuXnAuC6p9jmq6soJjtXi5WmU
hKNXYeX0i3GNt3rxASEuoTB//hTe7jmERi4BlOfjDm31RfJKn7VwPB8rHPK/fd4xUcQOoyYeMaTI
pjpwlG5/b1+LyQYN8CI/7cBZQmQka5nt7cBy+9XI3oDDn0wXQbbEKGDFSDF/Sh/dLAzhdhaAZQ/8
egYLhcIEccYfQmPn5Yde3tGrFpHEFtQ8sIuX4IZYquE64dj+ltsjW2RQnUjSkuxR4Ds75rxGJcbH
T1TpeYJN3pOpJeuZvEjyl+tXw5Wi17LKf6PVAcrLNuUUvQr/S+1eE8pn++3VMDYl2d1y2Zpwp3TI
u28gGXurYYbF7GJFNTqfkHtxdUJmhdHyUp9yayTq3MYRW6XJ+Hruy/D8kUWskbXtvuf752oth+96
Lhr7gbgnX1ZXLd4IFpgKXE2s3ZRD8KVG4alvv17MVU7eCKIoHB9QKWxm26c7aJTGFIlXLfmwI9Dq
bmiNoWLZyOyDu7jvIO4m3bty3RbCKpSRD4uGvBb622ngggIzVK63NC98kTKyHtikOAlv+Pldwt1y
+Ippd0e6O2/gt8wHznK0nXmxky/4MI/jabxcx8Uy2KO1srLVXQe0U6kq+J+ppbYlY/dRPukEHaIv
VZJqlIMv2Bq4dZUhi1jaDJDBjzDkfNlHKA7GVt2VuSfg7a5mfaR2hRrcAuYSey5YHA9kiVWD3bOg
KhRvV448CGWSMb+v8G8hhvk6wuYYcJ6xk+7gFFAzc4kFZ45Ljuu03rAZyh4bWKzp4XH2WF/5dUXO
GBAGIuO2lXp9JgHDYpe9HIgTn8sZCs9jfnezgT7j10jwzfvsrYl18zlGRRjh1dnuDi7j/bW2zabI
Ly99EetusuU4VH094ExseMtm2otYieWvHp96XiJgkbcKfg94p049n1ADICvyNx8ibp32tclIqOmP
tizyM6P+jaIhH0xmyBYM4ETafLfzyRcmK3gyoAFq2SuF3epRfZpa76lN0ZZBGBuL4oODM90hwMdp
BHCPGv4VZXT41rclUXmW/WDeVw5U6XG2YulpuNrqMvL25ycz1War6AVtJQLUzqbeDPyhV4XWoPVU
cvxbNIhON14HcO7qF5kc6GhfY0ZyViK3K24wXUbTyx3EnMUTCXyZ93iHU+nF9FV43A8TPSy+0V+T
qNYLTpqboHBxZolHiacwunzjxX5Dv1DEK9pY8nJ8Y/FBWrOL1NyGxrc0nEKoKpkiFHe7IldbsMZh
vgwKbyqpvGF3KiCxh9i3RCljV833lq5GxffU2W3QMum58lQ9TArrfOsdq1D6DnvASRoiC0ynO13q
kRVPuA5+C/ByRt/GnWc2VWEQ8n04/apt/Zgf68lNS9w7dBwugjIe92zQj/g5v+jM2NO83vSQmwM9
llELiGUV4IcXLRS8dPuTEjxKpocMBs3qlUAx3ZrrzmuYL225yKX/Mw8fnX2HCqnCjStaY0tRevoy
H0X6kP9AZTB5kiEMEELZPiKG4w8CQXXrIgUl6RnA0diPfmrLjWH3IPqZHVFKbMSN31bthdu/vE8I
TlXaTA9QsJwQw+eq8mAFVT3pULYtJWc+FlWFhv7EcdgmLbjrSYQON42LOaqF4XbURQkExaBaD0ux
YUchSrC+jWTIOZHc9OGzPlpN2kWPM9yjLQvLfNREPZuDK8JHRmGWeMUzUzKItYykaNXcSnj61F4T
vhVD50JWedw4bejlOtFPG1/97KLAMkNTlZh30aOG6WYlWoC1Bbsrr2FAd5ZxhFSunxn5ywZor2TG
hIE956fjriZj2Acal7SqXsnpEoHZQKUyilbhmnfUXq8w2eb3HUOYQhCyOkd37rCb7l2umrE7+NqD
ZxXREnStuP+VmbhWW1o+vYfPSsjBZIpRgBkww2gR6vfU684y0D0dYqN6PsHTqpuSp5dNQJZ/lZki
4PZe2DJX3VMdqrIrJo1D1c4u+KDJXAcRY2v6l/Q9yIIanORZAkj69ni+MKf2NaDwFULQGVsBNWhP
/GvcrBGnxjPIDg8KwkqyGqHCV7AuMgSJU49NwiNuaf+61QjJ1boyMxrGz0fJT/57RKXUi9WivmoK
8fz5k+0pmdykd3zeAsAVXg6tFayaVDsy58ooJV7idsZYnbXfY8er85mKQcj0r3KJy+LnLp0PVyvU
7zZjwqiihdMH6hWBZbMQSJwkfb6SLd/vxnuLjEVDvsvue7/IQEBypEYgub952i5gOoFNDoCZdu46
b4QP1Gg3lzACZMs0oyfD4pg9gqdVfw/dhqZuTm5s/2UYFWjSB3073EnQluP20zHOKiVr3MiD16ls
oI08lOryobYzUY9TSANEB7I7gU8SJNwAPYOaUoLsBGs9RRwt/mBLs+AJ1E7ihIvNBhsz9iA9SmWD
3ScQvwfE8W1uluOkhNeftgAVH6p5ZNRlIvclpHIzVvLgac0uKOKKvPDjc9ip1C/FhCiOOlBcUgcn
amDJTZpHAKpAMlXgzNn8FouqPaillR+j3fg+KWhXkPyx83VET63D1hNc+T6s+2sGLoSdlzC91e77
7jZMgR+mmWAsEquMF1hn7l4kWO3LN9VDyDFZ3txC9A16niAApiyV78YDA+AKN6NtMnoe4hxo9In2
U1jffrDYAbs0T+7Noaq2tnFJ9oy2iUZH7bbwNFUFFXBfH/pErXRia6rZHU7sY5BqlkJmyGsG60fS
zKXTw09AiQ8n272UShysgFWKv7r4JeG7fTnVJXpvyUw0KgwUIsuHXcuhN2oAhkT574l/tPu9UAA8
duxu84T/KEYzBs8Jqs+xrT4jVXbS+SGkTB22n2RImeAbtMgQdUJ46hbFzBs7/uzP7MXzmW2EN9x0
ALCUcfskLjdHmS6bRbfVyRF+1zXnd0nnyshqbHI/NUBpjQUTUiwRwGfSMjdXOxhaGs3VEvS7U1HN
Law4EMFW9rhvrLTWNcTMo0lalF0mgRRTY/QyknrpNJBQlw/d6BdD5lXOcEuarkBOx+Yyik9wNyJD
C8sXKqBSPuMwrLiJwA+hL0wtedsW/FCdE/U9M/tXhcVjYCAeIWg0YHa83sOx3Pjd2RTxUlJzBb9E
TRCHCFUfS2rRu0vTldfFmjjzeI88yxEOI8VaYg3datMTSl09335wmI5YTZlHtGYo6D1fPUstsBuN
53kAeBRpvRT8C4taKevO9OKFAJBq8fkiTfAozBWnd+3VYP3dGw4mq7NLo+IOZFnxXMfHrTxIfW+O
miiC7j9YR6iyElLPMxM9cZcJkE45124QHWyWeP9OhQ+L1IOHH5NqIMd15rfsqx/iftC9stlNQIHI
Cg2ouzNAYH7iUlEGzmWAUQNBOytT5GqXthhvTaiEHKQjlq3emRYcJ8i2rHrnsBchOjpyoSdKz6Ep
LHc8+P1svkl9wap2fwoNyi+uAyo4Ws/4GplAcJEIZFAX10Hb2NQ7hLUL6l7QPYgVAQ3S5Dl1YaEi
oHtJKBHgDmRlt1McoAYSSaeGlNsJGTjHXZfZ06chXu1M+0xgudhp3FGEWHRN9578hIvYzkEDtABh
mKSiM0jjcgGTTVZo7O0dixOdg/nAdaezoE+bUWRbV7ZyqNzrX+hEpa6vmgoWCVniW3ZFmQ/4qB8t
lKwFSpVXX7PABWu5ckwXhcKAvWzSQldkLHH60nty07qPujbTdl6438CV/umZcgY+ZNVRmjwEa12e
gexiLeeL7jLgFSWqyvsB9w+Ihk2kmVSdUnspdkA+IZrrdiywskt8JglRqC2UTTlE9teJzluFRuCG
KfeJvCkB9T3ojNiOCQfmW9fRb1Z3P31RJ/Mb2ArgA/ntuPp/cgHxuQX/r8INtKpoH5iArsCCcXPd
799qIbK6bMi88ZQ5aCl/V/8mOZRIiRncXz0nNjt1cVfTdoZJYK4JUFjsncJqg0GJfVtWNlemFKYL
I/Gd+YYqiPN74IjJxJoRGqpzicIfJubK6yS/p2vGBWw+hHV8CwxhGTSx8loEixXnAo4o5oH5Ykix
AYrSZf7ib39+apUHKoITfLwpJ9RawjSIljFCFwxd72CKUyPWjfv9QjNrDi8xgBiklLuja5RCWtsm
60FPXF1kLSeiqD5uZIIOXzkii8sxYwobshVtlkLrTfLlDfyj7ylYHhuq08vYmKpC4pm1NWZMkdTS
EPzZNfDqp+5fCVoKFJ3DGB7Hy3jvaxWnM0om/5s917w91fal2xnn8rceMtem5U2BI59l10Icuc5o
XgzxrISzABYW5S+aXoyQNngMXMTVhYQ1VX2eKZl3bTABzpJ8ZHRFzKl3XEMOb5lYzznuZvKGqheD
f5F4B/bqCTAABFKuJWzINgT3k6eB8DBl5wHIlAGG15vc6V2TYzGkC1c8yjcPShrAHNSFsiZ2y8nW
CvOY9u+DgRBStDtw0jRaZ2kq1q7kjHbgQt/PnBGa8Gp78t9T8v1hYyYBjK4OmNPKLmFf9J60Jj6R
PBjvmG52mZQerriGSEGSenHhpwf8i2BmAXlVIpqRl1oNE5vKY7ErO55QCnkBFJJHiK3FYuZaOYw2
tJOV5fzfTJVSVy5bTg8rxMBjr8XN4O+itxVOjQRV0MANEzrD4SrPh8s8wvv7ytdLCzBSRV5E2Rgt
OS53ZPn5WCUiuof2s0Cy8JEQAy/YgmdJi5Bwt+NXQwIl0u99HrapdT7bNxIukJqk1HzG0voTWCSp
OtndWf2zFEhBVJX/wzoMLrLXJ2s2Rydpb7xLDkTo/KN8Y2AQyrUJkUknY9WW2LaLlCfXYzZGd7Ry
zWtqfOfkFUQwFZEW1nVoh3ZbbDrbJf03Xc6Fz3tWJ4q0ozGXgS0xeZSrfL+t2zsfyAzbRXKpaZpZ
RxHgUR6PfrHaPvOnj4Uo4P8nqj+fJxRZ8pvtY39Xbybelr3I4HD9u3y9fIg/Am40IKExIKA6RkhV
ALsiypBTN+6QEex4Alc9Wqszctwl3HrEaLMxot+6Ulz39A+IenkuSlZUnGgfeeLIZjxCPArUalE6
Y1HblI55z+0IzUmCuey6cOXj5asL7UCe6Uxb8zMyI00R7mYeg0chLn7gzxrzNbAEU+nvF75BApPM
QV/xmU0uCzVZJ+IrBWIS1GCmI6j+29htgftognAdkYPcuUf2I69Otm3VGxmkjsx8bZjO7TvCVwWZ
tVAGqNJzfURVyFR7Ax5PIppIFTUsjSaJYdttJN3d5XYE4Y+0/5zMP4zFcKgPdIYU1g8D9ZGEErOM
mZXG332ZRyav+epY4zFyrnFwuGovaySV5wG2+ATfq3uu1KvzxDaWAvlgIdXCPvLAcfjJ/tSdh0oE
m2IDjWl451H0sRzVeONGdpOOEb3qftnuLEjdPySnjsuv7no4LKgJodYwGC/tdH8vcr1e939cy3dk
s1zhDaeF73zTWM+jMTESeNlQIDUx7xxjFelb3PyF/kSEgq8h9fvEPHmLUALHKu5D58IaViHOfEPm
t0QT4eweJIevm6mhBUJAocNDyixUako+El2kxc0+jannWbklbROBkJ0wOZyCM54OX2xvt49Vfby/
x0XWSyxQqNIE4Grc8nDLvvO6vA44HDRX8mzyvb5KViZqa2i1F6X0QEqaNKpqdHMLCGCePkF4BTCa
HZvtKO/WN6H09kwT+Q+E3skG/o/Fbsvxq/8NamAxu5DeutDSO9XC/VODzEQvAITCjCpmnEtBLJt4
6H8iSMh/3ApedqQ5jE7kUi/574Ys/rk7PHw9RCTnHFHs/ibgzD1YI4K2yUS3CxGIDRey8otVfKP2
1Omqn8xtrmexHyj0OqGNg3pgs7g55bdeq5jhHfaH+HjuAXuLTyOAKfPTuu0DpnUrLVDAtvVavKfR
20PuEZE26thuT16dLOneh1Ekcl6c4uDDMXbC9tAe7bledmVfa7u4QESfeAFINQ6M1m0832HelvlX
9BJ8Pjj2hc0tdGw2aArq2Qo22QxvybCPH4ebN2Ipowmm1QwDl5Qtlpqj9zL/xjbhNC0IfpbmBXt1
TaTRL/VmhHBxr1dWa9R7+yeZnoiZ02YnbElQHXnK4S0QkHmmpxVaki6jVBNy89FoQ/gfcHCbCSfz
Q2LcTs27IHU7AlE7tXLiJGw7UEaSTWc51K8GEKEk50HAbVe871aGF9/qrPSVL4aBUWzTryx2W7uC
LbwGl8hTg4hy++c1hCen3r/NWUygl17gEOPwtOjdcwhg6Qbm48kFiaToOV1eRX6h6+bs9Dxw+7Nv
HBgBg6ZFJoqNHDN01IzBqs/J988GlUMhFQTUei63Mp5H0cVQOyNVx+5iIdRSfxjBkFN/HJPFIDg8
fCz9aHa7FVvI+Ebnbh/pDv/le8cNucSoPjf50jJFIUgCywXOAP1WTV0PZHoF1RaT3NY8FfGCcPbz
iF/glBDKhz/Wfekxpa31Dwwe5RJ076IbrGmpHbsVcGsunRa9uWkFyviUiFATuw8vFFWFsY7cU9yN
zhzS5uDhllUn6O0Ex6cCeyvfwMKiYkp4u/WPktW6GwXyo9lsfOxRXcd44hi9oQvygQj3jSXUJol9
6JrD828s4VxDyUyM6snGngiazJxxsS7vsV9a6Hhz+GQuFxXxfi7WV4WrSiVuVuH4WxsXzCKZzZEX
u1YAtU9fCrPi8jd5biHw0lO9DBVn9I3evAEAJS41SOR34t86BsQG/dDiQO7GIiMLjfUIMGwxyYAQ
+Ng+5lPuxbG2rYWImSKUwRyQ5e8UjFeM2d+HDJuEUYx3mTEnyigJ6/BqN1owZo+RJ5AgPsT8EJwz
ZQioQeNqsKC3oKlDE+6BTZWLoTtAR37btanH36So/voD7uhFZ7q7EYI0h9zLN+PwqcLZydk2BSVQ
8/9tXS2VQUGb1UfamcxuTKJzafFcVu1uBnqgRbLL0H7ovZcgMA1IaoG08QtxEDAEhtpZZz6+NNFN
+Ls0pgKB9DibRaCu+KtuijDiJkcc2/6nX6rA/m0WEd3aTYBlh7/pt+C3sI+ky8safARIf6VRFpZJ
1jFyFXqRnfTzNU2Yzmv0VkDA0V3uNlfkgmn7/px+hzSfR9FcbFNvIwWt2LGTCNFVkYqVc0fmy7wo
rnHVdOUEV4ZtQ+6efxdb0mNow4yZ7N2dQYGK+2rQRRN4sCdQlPxjyOxG9KbjkIv/SSsz7ARASWj3
N659C/VyGaCoJNGn8gxHWqEuqGDo/eN6va7uZjByBbMVYeCTbR09qTeJGEWr+juS82tIMCypcuWJ
GrdMy1toCkjVTpNUD4EPAfYQWkYQki1XPfzbVH9zANvGURtp6SiyHyf/JXoPW3Yw8owHpDzcBJRu
9R0mL5DL4TJOW70Mlp5BD81P0MiamZst5V/ky84CzqU6rGEVJ3dMBtF7WyyvNoAc3LR0/2kinYsD
pXIirF8zNrIywZB2QV0UU24s59wfFBlI4Pdz0yFONJ6NCnYPjtdxfqvUHrmJauXrZ2ka7LAdyHHV
Nyts9YK4cu9SMFpPpnLmJtes22379fVuLjUZu4h8/KQecGNG0P3gnwNZBeP90Lpt9nLEsOVpS4t8
LSSRrelX5HO63TSKRdSHqhuZUHWX38tve+AQ24CejaMC6eLKUdnb/jzNDkWq22lYUXxx/H1r98mG
Q8PY6/nPMQZrY71M75gHr7nL6Vczj2YJvgvtE2Mv0zRz0y01Ir1x+Eak5p1odbUcAX8U03GkeWWU
vJFb4fmhjLTiDoTAV9DK/TSKcvaskZKUBzBb0WmJAMZYOBE3A5G0M0oeXJwS6YIGHxwzoDK+AdCa
m/yePdachmrmVXVQJCUDWVeJ9pPILakgRnIe4DkXzi7dJT6UEak0HI+IFphleGGGwapUURBJCZdQ
TuXdbqt6GmiUXNfPEE3Up3mcjqg+OVMQug7ieT3zWkLSFUBiTQTUzDm25UuQmHfJ1uny67eV6zQg
5pbO6RrWugygnSTMlX8mIQ3vKkT0QatV0wUx4c49yo/fTuiS5wf2MEQnAj7J9B9VYILfCGX+59r7
PtJ9jDpyfLTJhnoQCBwzOSGzW5YkNwjlInuDZ7mM1Id5Sbm7oRULWlqwPMw28bzWh1xsG01pMViO
d4IrLeWtwafF9DMmVMfCrtVpLs27EIR/NQPOSxV/sKNNdzdO03OpTZi0o9z7Gp/WJ72Brzs0Gb/S
Ko+wCsrERHq00O2gB0a/V8hmjacqJSaeaNyuvdulcXfJqPfy43CUIjJy20qaFcV5QvyVZXIlY1vr
45iboiKGMis3cwIpE5m4gs6CCOy9gOexsE2CmdTGDQXR1b5woqlC4PcckvU7WCsWaRMUvJ2H3Vu6
TBVCqnItJo/vSrkR5AjPOW7v0GUmNhtaTvMDFEnEbyvt1ezE3uEtzjEehqF2xpHPJ0OBIx6XJfpT
BvVhCjYJZEiDR9t/EDOZ2wR6ltPoyqRqUgazxjPryghSKujZz2p5mR/zDNntOYtZejDALbDCPy52
6TcCOvU1ajDQ67ybupjmHkUfGkf2YEB9Jx/BiXb9hZohy3xLaIUMhdzctX5sZBMYXAvRdee8RAo7
tscZAiWD2j4lwCNwS6I4XxFlDenR4XKtxGhlrLBEWqBT/s0PWo23ddaMlLdhOAcPf0ub8u5ulu/+
sVhlsdU/stSnrHLqJcLKP/zVUpi3qIkOkmuSr1LgRVo5YG39ezerGXZhORI/OAUgv/tiQeF6gKnd
91U0UEyTpmbkzkfury35me9dlPGucJh/zR8ZaIXoV8LH/ZndsXHiouy9TgSO5C6dDLnIY/XvZEZv
ihiqc2rg0U2pU+rdjLrPrNNrp0/+t0M131WwP+h/QcRsqUIJUgsODyrCI7tNKpynZQileo+hOVg1
IiPcB1430ko+1Ld7PwvzE8OsYCs9r8K7jJs/sH6Px6env9mCoFrotiMNEuh/Le5QWEAoSBJLYiV+
VY+vy3JS/2sFsBPWqzgjzKs31n3Lv/tq9lRR3MM0deiEvl9NjCyqb+f5wBda8huYAifMX/hpGI5i
mDaXxOcOxB01Ga/825VBDPbomc01ET9Ov/rLuS2jzA37SYXwGIM1G1/Zk5rbDbT9ivaDOfuZYsB+
S9euvmTgZqKdMJTmL03nw8La5WA2amtA3ByCImMzcpUHKzG1oc9rd98VMjxVBfdR10X1ikqJiNuB
mRNbj+EX/m1X88yIGbg1bVx6DPql27VrTnlVQbffCzCnGvgBKl3WChiLOLUoh9hx8kl9n2N7MSUe
Z55zB9SeTVqBtumWwF9ZCSLI/fsJ6GmiIRZx636nOPExd2GNuFfOPzOzgr1qz5on6j9Gow9ubl/g
nc4xjrAkdkZoc6Aj8zTyIv1VCM7hAGpT735p2u0eWARheBs1F6Jkvq15/wg6FgN9jAE6tY2USKpI
uC5mv8RleRhKnp89YbZ9TbWP7hKYb6ZSGBbRZhOWLeFDblZoZtX64kLuSXEWJkS8qyJxXHWubXoZ
BPoI0XGVB84wzgklOCEAlmnQtY+fPitIkG2kIOVu+0ZdsyVNiBGi+d9sECgkpfZTbx/SxlEW3NgX
HAYkeFwIwUx1H0j97OUO6JkbLmnbb97PPHvtQPgJzhjHI4OTAgTbQU336BhWoOxlznMdcek/rJ2I
j1EfnZJLrJ7jtoloPaenRsGStl3nLcJ1uPMk9LA7MZ4JDmoyErlAiUURDPotUd0EBXlsmTYqXYxr
DNVAxSklL/7eCNONCe/CsozQP/xSGcRyyebDIaGqZE0YpehvX5/2TGO06Sdc7aSavSvAcfucTrHL
97fyjJKhcOFBt3e1r2KXwcZa2GRY9wGiKKdmqwXaW907LIY5ioZGuUPlEkDU39N4FlWSAfutmvUW
EaITcDrZluWpiIjnAaXUr4kIevqp/P5OlXmOo1A3AL+ljZtd/pE+J4AkWLAlBPB0NHade8KS3xTd
UVuG6bN2OpZrf3vVbB3s+1AqlZ5NtugiBHsdc8Oqizn5YzIm99KzquJQKEptB8/TCY6Rl5i6Jlr5
QVWDDl25EcLJYzLJAIxB7wwzbkKA2LDsnPDnWyFlJCSSINuD4fiBSaKpfbK0QsZvdNIkheP8+d+K
esnqbfl2eTIwCymkRazVnC4DTswcaTV9XWNJ/9J12nA2WmaYwfQSiyKcGqbBbEsMh63OKunHMTQr
lPcUtGP/AlM5ZZB0XFBPPQxYcX1ulO2Gw9XtIyZI0IimUZ7esLt1d758dTCP+DbDaPHfvVsTL7yO
qe5ATOTcV7gubUM6YSvs13ndsICMAMbt2FBe182bhHHYVdsMPVwoWl0HxD9e0y69KATumM/CCKOp
gO5/giefyK2CqJ/6pp/Dul2TtMGQrkQFhaw9oURFnf+Grmq0rT8Ezo5eqCZnFlVI/h2i1Lrunnu2
y3EvrpSv9SrVLIuDplold/Wp0u6QGjsGuvcX1X+xE2Dxf6vBQ7yjmmo3e6XCGpJtGRfx+qh4YRZ4
WXFqhLPqMMmwEdtQT6r+xDliQfSp35MokQMIKcC997DN9oKAAAIEBPPviyk/mjejwRrKs7LWQD64
CQfvq9gTKUEXtRdbkr45keVF3sVu2VgDMLwaYq7quQ5Ot9/dwGSjG6qAstOx979sBVHiyrCexF51
cjarO9JYZ77qcusfdWjSAyN5pg314CUE9God1RwWp4YhEw+rPg1Ku5/YtHoDdDyS20M4sxyRIc6S
lnMafRSzVn8UOyz0RzmOpDtJ9X/cjU1BuXX4W49FfQRLZQVc9XHOMPrRaD+4Mg2buheRum1M4HmA
AFV+cXCBqfjs4QKgoyhHonKnEgQ+jAcp/VlQ7CI2gWvdTX30Obmft5gzS+mWqvp0GqOPtEHVKHUg
rKZ5Csereth5N3ynzFgTDXsp4Wa1ojnNwtx7ft5FUtYnR166n2GiGlB7wJJnGKvp4N5CD3FbiBrM
c/RFzf47ayiGUmyqQEnYHTnOqorE6rY1ufUFMp4ziBgDm1Y3rZOcbF8T65gLy7CgT7qTSwdYhSGw
iIrfUMi78AntspeJrLKPDDypcupIzDV+M//PoPC0FRbHfjJmLr8aA7+SZRshhx4SrOIOraqKVEpa
PLxicaU/rEUcFEdxIJHvBXDIMdZIem8vVZBvbIDGGK3jgr65Dm2Z7yDCcJ4VnzRnfwUI5YQ4Fc+F
JntjZJDj1/8ng57rjFTyyAPC34zG04kLDP3YOMijzrN1QIfsdY8rq0VCmUZwYB63AEbMcDutvZ86
WxsqBD8cy6uPFPXFtrUjXgo3aZ/1HkUMdeKpSAsKRg9+0wczqC8d79qcErFriMu+zACbQdwaSx6E
lTd9lw205p2P6i7mHu3Hej3symJKk96Mc80rTelSbm2Tz4Hk/vHYAwMT/EumugzbA4oJXyflhB2C
2hDVZEBycd3wHx1wK4qHElIFy5QrR+bx4o0jDtCM7qVzU6kf8EmpB1AJUYmuF+CNrZh1/O/93HeZ
KK9zIpMCf3xqHZjlArmRZ+BNpLGx8OZeg7ZUWXYI+yOYLQP/v5PgTCO/b0pnjg9YCOS3E6bFP9h7
XRen/xfp+UH6VLoPc7Ooa9+5PiXlUK+7vsGzCFRpkQ7eQjf7eK8dMRz6FnrrKnp2GFafNIvdOAbz
Gf0J+qdknLvk4AyZxGqb28zmsDCM0u54YUSsTum7xNjtaA5mukPfCnGqQ5v/rzn1KVUY8LzVfTtD
Ci+KoNueUXlVLt2u8vItuITZOvYbTb8qIEV7hFuniLvB8cEyEPjhL0S5/SxI1z3ah6fzBOtLJbxD
AT13jNOjs95sq4NWs/eDwn9p/Kh9wvpeDn1TgIvGi1f5m91Ex4aIubDV5bdQx6HZvjwx5nKwloF9
nSplRy7YS6Jjylmg35CXlOpO97TQ8RXWxwrqUme+YaNPoeonarW6j1dcccn2B5OrRGbB/UOIvByx
86ZY0SSBAmcwkM6H4tk+afquTw4pSDy3UwbZ1/VgKmBq+PAHDQOzK9mcQ01TFP8lkTv8Yn+XnUhh
dof7bwOeIbk9/w4rr2aN247ChaVy55hMTn+cOCT5lvjLRRQRunxP/tjef6HAVAENj/+OsBeszfQf
dNIOrBU+Zq5EeseITFcwh0XrQgTxe43gU5GVjr+TSmPAP9ud4t1tMZGPKjV9uQMsxn9w08M3v5TY
KYeMcsCnsC18srSPVIwcwWxYmSsVAa39U1r895w6ejWkfw6IpBJEdd9no2TeBrIKXgc+Jgk/l8Tn
CVMR7+r2Xotocke5Bb61AQawg+OXGK7qI54W769Wzzu+a5u8Y3CKKLGAn9VCKeT5TauQ52OwlVXR
c9rSZLwQBZJYBG4vOwpep3Jg5MQk1EHZzc8LWgC0dFukebGGyKkA+ubMgDxciBfa+8bFzT5IWZSQ
UxueFTEI7c1T6ThPya4odcEZFwdrHATPa/VeM/WzytI70tKMKQEUDtsmZT3oAC5hfG7XMYQginyl
zKc2ExAXjSpEtD2k008PtrhpFGpE0J+VhK/LA7Hv1T1teO7yqJhDOKkCzcIDYG1ZqgqoF9Z7VEuV
8auqNwWUEOzHiBIADA4/OFMsk0ngg2fL7LN6KgQZPReVGxKkLQ2HOsVqoSJxpKstuTv8jV4rvpK6
YeTNDx+2DxvtdxkJ4S5vyu16g/PJN9N3tMZayij0RQFaFa/dMSA6HEkus3Nfj2Rc8YV9VDsuUo9l
PU77Q0eARLfE3D2pGYbrwf+TBfW2O/EvLSshxrtr5FkncBAgP0pqeqVXkTD4H/oR44Il2tw8F5ES
OdONvCWoDG3EnyiD56mSjG3PmmdiDVNiGUi434Z3KDaGpMDD7BeDeDY/Qc6iqINeUmTRO3QnNf1c
jsSAeH/ERf9mGkCBQ1Ya6lchc0mVPjUC7/y6oDhuh5nkyzJ/uaOPdsv4qc0mfYAGMnEn7rNyAGXk
1WF3qsPKtc2hjr/tMO0jCbo7EP1IiDSs9fous1V1IWHV2j4KfNUUMN9uALdWjxgBdKNTk+dR7vi6
zZkcKOwniqjaOGwyskkOMa/qSroQYppWpiypQip9agoL76+UQ4QAmlVZiFizElhiipkPhr/MrIi0
Q9y6m0wp0eD4iRBkl/AoOt0D4MFWSMNPLzN39eVj1IdCSgfzuC+J5wXCPfaDfcF6giYhHT3H9NOb
XukujWKaGHb7YB7gaYANhqNGUy8IMBVjPKZIdokE8fkzvtyDz2LVzA3IQdtFMVKy0T/ptdcln+8h
0DLJRzYCX1UgsXdGutHct7xCUhOm3C3pDgQtr+82QAU9T+bGmHPNCMo2ssrKwNXd1T3yedLqb9mD
wYB44eHI+BNFD6eFTEnFFYDWpQS4NaQjhAD5COqhCjT+9v9VePq29+Z0wgW5Z2GpcnkNTCKK6RbT
xVYr97CwnU7a68mLXYQobLBrtIjo1TR25AlaRKwRq/iKumnT+9BDwV1/A5sU0hslvjkiMXRYMJzd
3CBaKmgmRyVp2WWkq4lDYl/kxnZDx3bGE3WBoXpiAVR9YJr1ZL1SpmHkHFZsvCEUGIMnCe5DczoR
oCU6d1LObFbrRaBEjpo6x1nJiTdvqS601O9ZPtiEUQq8W/bvQIyrR3HOsXxi4qWONT8hQkM+GpUu
i/W74lU+8HbnOlhoXamenHnsJ4tUu/jrWeOK/0p+VQGcGCObUYT7Y8BWBZhPB1g2MNmEtPKOMA43
9bs9B0M8FZ4cekNcgFB0PZx8H2jMeL5noQcjcIsM/nqM6BHxKAcGEHfYyiW5RkTQNXx9xLZ/lVDE
DbCegtpgVHM3MgdrXy6+1AhyIhnfMjdqEDskZXUx71GpLU1NPui+ng6KeSYUWWCKL1rAtJw1it//
aon4aSMjh1yfV9bgebqKO4bMy4EY7F491H35J3Y4RZ0SPvU5rmd++TtSGrhCv24bBjV0En/kLF77
raWQqVncEJVj3JgaOOtkuXL58n9MkyN/aABDOM/x2kQJMRU+eLIwIyhCA6S1wF11YlWcMv/90+KW
4kiWD9TS2VzSadllob6gJ5b0vHEiD3ly699oEVMVuekzLrU9GktYmtBGpKd2YQG+OUkGrP/I9y25
IA5wsO4Rm6hrvGoJqhfibQrC7IoK2d/WX/xoNsSXKRJ0zxAAZvhCuJ2LfijGU1FSvwa4Sgi0bioN
6N3DGUmWyuoDcy0f3FJeB0FXpyiwXpOgQeq7e0DLCn4611JeSkuUrpRjYwZG8fjMI0N6QOxHD/aI
3CNZbGEJvRErK1gcTS4zH3PDlSY428mMbIjP6Lebs9X4/aSWJ3xbDJwRsbLO+PMYrwtaJVNsfUfg
YFZn0KhL1mjXb+/M0SNcvTjIeMtHwTr0UM5ORbpwmd3TS0ikP8+qiKteByfqwe/vPkJPWnBJwuQx
4DVIKk6Lg8IS7iMpT356QOBnqJa61qriCO3Oq5dwCbK1689bdP/GILRaJvPR3wFpR8Zblya47pNW
XLNeGygRsqnVWF/bEbAyhf90+BOE6LkcIhN52QTkoaKhtF+5GFU166ozqT9cxW04CZVnV9rZprcV
03WPFSbyS+41W47ld+JvAvrfaaMKVZj1MXP2tHohPYdLQnZIw2dUesmmfu4kMFz8PzyD+CRS62mw
1rZ0bzkWwu9aF4bq+MVoE1l0nT2UXIoLwuR8tnOPfzahnj9oczuHpK9uYSjFCPMs2aDxVlVEwpaD
jCdsEPehGnA/ibcteTwt7nWMRRYCyriGs1GslsnFvBErOXgvsCT44w+jzT5oaG+Z/99FsZDblK44
0Z5338kpYSQwHJuJGYfYV12uL//6NzBfadzR149xcTjk6Cel25OHQ8V9wUTY5naiUmpahr4yo8CP
pYjYMaTADOb6vqwK5wbB+WWMkX8EGvItBnASlXDPzFGtIWfiQr50Apo5UNmhm3LZR/6zuf8Ylk0n
CcCqginZr6gHKzTSp0HVpBl9lhlD+m3crjdOGuF5eJ7MxBsPOwe9NZVI790bY7SM0Pxnr/qpOtMg
Xvav5zNQhGdCQVcpOXe7imXYjzAhh/29IIMQjqrKALwuyqQ66QyT05PKqiB8upEqHwAOY3KOwa2K
hrTmU6+j0AaeOMKI4OvGUumTkv8PS83hh/acORl9YNhJtkYaLLmYGyrrNfVW3rdplCaPozhJ+Nnq
nJVpF66zNNMGnRxkN/JkxDaoVNpYHvRlm6mClod6ChWahA0hzNeq9l5N4ci3kkB26dmpCmi/vmzq
8g2aKmxWBRbCCkFHXz2u9uBq8fLYCaXTuqbYj8pE0NawnQp40TARstbyihEyC0+P7vMjgXLJLoP3
1wdvjT2YcAaGXgOe5wtMLOO2ssDUM/z5y1tLOz0ITNo7L5CyZuWaW7F2JGiRVn5uAwk4AE03HxtL
jxSsAYEueB8SiwaXWGi9B4SPby9DRw2xQV3cHybte+NCEqAxITQW8eEcroxdPTLz55aGcuohOmMb
qrfkSro71EpO235NuPTI10DKk2BjaALG0CkUTSMPat3BBMU5I+p9nOUxot0uOZ/dFKp08scKeHg4
teUs5elLBTAzaK7ztmAfBYyWMTSrla60t77U2sELHOLeng1ZzbF9wHA1dOwatn8ltt8k8bZtThPl
osEopraNkvPXaFlvX4s/yHcGiEPgxR9nue7XWdZO3FD3016YJzBbN0NUA97g8cQ2juc1r4hnuSH+
KXp2Y/XyppcxmZXe3o0dP2/wE8OmQV+tUWkhJcrC1AFoGNysSG4esrJbckY7lW27Frb5xwJQgapg
tXi9dVuUumNppWJTCHn4n/vArdEl9ubwjLP3Q++Kwm5wNnP59Cg/hgtpax6d0y+AA85M5ntz6nnc
Of7Wupd4Ce3VWKwh4M2mP6lisMoXhmRKspysU0J4ELF/CHQu1xAqgUrrJacUu2FnX07ARILOBCo+
aX9nrUy7sdjwz/p8SBvzkbI+tn1iBBYtKztJAC2rN6A8xIoDraYGGMMYX9lGdkrktS1yjn0k3RD/
S0mc1g8+VpVYJcRTkvtiM5q/OHkIVuwiZ58/xVI3BdPzB4FjHxFOWO4tbJYOeCV0vEHBwW9x31v2
sINecLMvvb2YFMgU/OeND2qK3kU1JtH5zrvL60HkuM6iTOCJgKlTCJBP+H2ivyRrrZFPa2ie0dxW
R+iCjgzmK9nPmTLwyWIpEp45y32CBqCe9tVcXLncg0Zkg1/Bjtto+zY228L/BmFzpvzXit68PjDg
EMrnHb9iNU8JE7x7O99MCrM2qunSEHyAFt+7ovZq78FU0Zv31wUfCfpjtsHmnavqVsAfmqexCOmO
jg5x0V9DMeMEp+WEFGquGdw8+Tb9h+Snaupuwg2kFdpfK3DrAIp/cH/mmlWC1Y6vxLmWDDCWaXbO
DtDf0Z+bpv4SBimPBx+gLIIBf+5Ya5DZTo3OtwLBXhojmnY/TIvW/4uhO439h1k0zwYFdZJ/xACP
J6j5+JVkJdNIcIq3JcvOmEsForGLxrRhgLSiak4hMuZqeArUPKxgC1Nw917ySla+HCkk6qbrwMfk
v4T+15X91e14oAvvHZ3SgBeafCiG3rfqjDZsB4gza9/njW4bQovRYjPpR9lFpS68Xlkjtmg9Iv0Z
yKV+kmwXmuZCPNLOW9p0U1Ij7zTJxTBc/EwyhSp+VS0N/Lv0ozLkDEtL4j0BPfx5/Tdt+iQtpa+5
qBxGZ3IgmHP5RqvcN/+0oku2ArcUjEc6GIl3Vb9GNjEj/jC9Mn+cud78SWadJtrz7P6GG25kcdpJ
1bF2rog84SgLz6Um9H39SGpUiMM0SCHAwRDSZxtfMCH6BkzMuOkkG9Io5LDOZlu5MpiKRFM/MQoR
gIrwE5kp9iChnLy27/od5hT/Gr3j0naKQwIv1XDE9pSd4glI0Jq87BpVn7i2xH7nKGiNDUfp2UHl
vV5fSfzGuocBNorQm0ByulXfFPKbw9rhJeLCGPmEpzovl7d7de4s6QQsAOMMGVvMtmB/2+abCflX
UefLfUpdleIzKvSk/MKPb/W+XIqiDwQr7a1vl+1fnp+RFe5RHQ9/YNT6liUjNWLMqfeM+nBJh8ns
GzP0llQ259egjrNeY3E9Y+YimKIU2wX9p2XoO/WChZ+GSSfUn/B0iJclQalvMbGMsN5ArGwJktUM
x+kf24v5Vf7GibLMpeOMiO8/WM740anzNzrjHTu3Mtps8667IlBC+JEYZhH+o3aA4B+EQ75ky/h6
taffq+pbi9y44ThGl3JWJgWRlKnAL48pGrRTOy5zGeHd8NEUyGYAmuYSZgp+lb13lTEV7q60/mwb
3I5w2kGvM93C6yFHz44O6xwSHu0ocjiapJf6ZfxdZEl/85PjwGzrb7V4foYBNHC2Jclc2AbvUNAk
DCIiMb/us2IODUGSF3+lB0buaasa9bGNCALuON3U7NciEl6DzziwQJgmuLfkNPmCX3dCFHosw64Z
uPKxPmv2fAqkN5amRbNUJ2RcADZszRMJ3Wm7hrBmwRiRm3+RJCAcxSD7aoWRBCvIcfFhQyHsx1SY
CUpSJ2XI1b2b6AdWl09sRaqIxyIZP1C2nGQlbLAqV8dnWB/olqo7+YI2dyCAqIMn9sL9LtT70YJk
mdLw2pHw62E/W+kyUx3H5D6qnRbydxGigo8k/YhIJH3SlkV49IN40HG4b5KnVPlDDQHj71xSovV9
6u4kPBmQMkBwXO32px8/zMrM3RCpVrCMNbypv2V4t1qWgAeSX8tVioUlg+2PXVedpRWeDTfUn7b5
+4buvto4pvV63PbbDOeSW5AieqVHoh4JugOfNjipoFHAAvByUeA/P5H1kGg73zlI3COOfGneSaY4
wQwxCNzG2oCqUqCP6lLNbL4At3KPl0Bgnkws9DajEf7O+mex666wUzX3LoMgsGXZRm+bfNaX8Rvq
g/tF/JBsQwqlDBkp6D/zaBkRhd6GFrqhQdmjUTJvG2Oli2JZHrt+bs7oOa/uyXVMerIgd+oZqqxp
6qTbMgqnttVL+xla1zxjssATXWjSzJomIcbsa3KTlrZeHJ/f/JwMZqXfL7yOJkpYQnO/zaXVeJN/
VBMgnVWXOhEsPpdlz8ryA9WmXjTpe48M0m/tItmi98r0yDWYn+ROrC6T8I2BYtdfLAdt3yD4ksYE
gN+H8v7xk6f7PObGh2EvJXr4xQhGfLkRE9Xw77SU0wqobqFWHgTh/vvTCyzS8w+uZzddlefLwJMW
/Mp0iUxGZUuk7xl/HDkvxNy128hea5Ze0bhNjKtsWM7NVYJSRoeuAFlXIEjKvUydr1Q4n1KWzlkJ
PHeHVxWxQVwZ4SKvVAZTIx1BbarGSBwx/Iir4/BN4AA4acPBqVaFe992TD4xa6oJ4jiDQ9lI79lP
Df0tfllYby0Dshjiev3S0gdvUlBnYb9ObiBV4h7ho/fJXxFdCr8+QKRk6u1imJ42nEv7Eib10Ixm
jUeHO2pCYiAq0AbpBR/MJBMOxglbRECfpAqYD5GZeAGkTaATqCVyoZ+xo7D4OrkSkal24KaQuZlV
c1eEu5oIO89n5neQV8pO6IoNdr3hDzXImZlaXTxPuD6uO2jWq5hsHPqoP+8GbWrIUZR4h2e4BZcf
moNhSt/AJB6VEh2c1eu03BUftdq4Dt174ivZulg+371cAQmflB2GRg3gvCSLL3RBt67lfHPVIaeE
C5ogX+aOnYBIlItIQTNAEC+2nyD2U03mp4K6wj5lJ7qxLSZharN1qor0XVTVyIqzyzPEEZc0sKWR
Bxc16ndT/sPTkGZdjnnxlu6ah9kL43wjYj+uxxo6Ls8uyFJ7iJ9RxmlNVFOM6uxp+daHTPDioE//
3mqOY1WDgd5Hoe7no5/nJ7qLUf8NhA1ehFcPNppkEB2GRTUal88/J1yXZRCjbzNHv81modgfI1Eo
yI7T3wAQKsxbpJInbnDjAUKopjLa9ZoPbO+249cGv0n3+KruEEmmfdvApqBOGi+/F1hHN8Gqy37y
Njcza5uBE4vu4flwYmwwX03vjL71XvqVqWI3SaUsV3qmIHxblwfl2mrE2m1y8yq/gfY90DmCeOwQ
gj3jzgN3Pwt5LpDY6/zT9dRhrGyRPUDCeTt/6ycfyV+q3Pryuk87cGHoI+lr5aB7BoYGGFQx7hwD
o7Y1rxcZiYnSrRZMclG+UdZA/W6W2AlvK7cA2zWL3mWQZt6LGx1eOoa55EigyikLmkkj5LGtu1I/
g3P+YBk8iSuF1QHXBNqBAApC0cOuVN0ZbCuj2+ufeUg5vShk7M0eTteB3Wf2auAsiKC95GNEdNpi
X1e70Kj/M0fSkTqJmZfM+XSkX1N1e9PTZvqWuegHTdk7r6a5xlgI2Lrf+VQuSTYI1U+4gTyu38fG
kzYFAxhGMrggqH7JnE/EjX8b4+D9VARCmYxEXVAimjFqDOfzjnHUoABZzPHPYODSMP+Ow/9imLCw
xdlvloCbjlkqG83hMhz5XVWEzl008nZa/eIaSenPEV5rOx444z6et4QsxYvk4DnafX4RzquSv8rl
cdsXfOcy0Ow/Hk3vOEmSa0V+5TRpLpsHJfGl9PbcWFBj9kmiZ0ScPfHySzh84+1QUAEmQc+/KnMa
S6gDURjFhHF5HSgog93X5WWyWn0jYSlAfIkr3GSC8dcvamnm+QGRkHn67ysodZeRJhiHirWFWhId
7p9siVunLQTA2AWNWtY4BtVhf8V/oaHDMRczvOySPnZOzrFVxI8JRfig5gpIfGrEOutj3e5t+d09
pD3Ulkzn5Zz/k/74W8fnoP9H/S4UhU03J+OdFDSRtgOCpZgC52R+Zb0wsrrO5+/dlys7ZaQG7cMX
bxQCWWT9fCHSZNFEC9apsUgB2FeQQ5MrdTie37buTrwVD6GI3stRtTRhM+LYsq1nlT/kp6BFO9y4
UvPqfiWTkhWSFXSZ3tyOvolIN6sz4iXO5F8xmJ5N33it7dzqNmqpEjGdRq57fY34M1jpuN7wMdR1
4FnDi8X/ZF2jec1JRx2KUoc2+w+WLsc7K0HS6YnCNIzwRs1mwoH+MBT4ha6Vu/PXZ0O3eZV17Hee
sy36xcPt2bFCq1xanDtpsr3xOeM5W5NlpOV1DoQMIcRYUWhx5SCO9tBLRKKlras9ulaBokqRGlf/
pKo22JUFMFokY2fco40oJuOThe1pAMrxEfNANOO7q8bqhNaYdST8xtjeIR9mIsjdDKbSfktf7SPy
vlHa3nF5/QVBYaYOJ+L5/9UBxs9VoQKIEi0qBnSENpDCq/780AfAeMKKqcKpH70qsyqijARteay0
FVD7xvRdCjZrJP63f4P7fKn8K5j4jtFPeiknuQnUrYzW6UHY3tk9+La4hJfrbgBm7haVj5l1nBif
ouLo1XFfeCcDmwn+EJ78UYolHhl1+QYtGrbi4QnKROMiU8PfUFjp0EIAIxEesuhHdQa+bFR36JLb
O7ENaolQMAoaRmSodjlSn6WEScuIAQtOXqP3lcGrZqhMf+J5eFUbF/N9gNHznfpWgxmfT22BHzid
MvN6V0J2P0S3Vos6fIvnXif2Lcg6pGE0PYEJZxrjpxAtHq16lIewwlmb7kpa68ysZqVaDfcGdluQ
RUPm3WoKhySJMu/jRkDbqcrzfmXYN6j8ZAX1XkxRVZMyq/a2EUeaHTGuD1aK0LKmjgCwiAKtl3cM
r9ze4nnjg0wju7WnwRMUJJz4qx/Oxd3Dr5turUMtRIfrhg0nnw7Oz9SNWa/9F8JyDHTp+nmPop8i
JdnFhsPUOSow6e0T4PgUAwAV9IQKtH+hmQ9+CIZl5b/RgbP/0oUowfohyCoeumPxn0g6ge5N8bsX
+tf678jElfPtcE0eaDEaxn9OqUuOs6yGeN8HjZQKGhtn9SzP9YMlkFO99MvLb8O1DrqqZkdZb9KM
WYAOzZgD+a4Ds2FFBBIOgHLHB6Do5uQy8YYCf9U37d4M7/Idqfsf7+1uLN7dU9/YtcTVhuY1rmgX
GiL2n3JuBn/SArl2rZ/4pyfJdXvyG+KnTKnqe4HIsfmjaCtP57red2HhdC3hor+CyWmOnXnRgIHZ
Tqcs+Tfx/Cc1Lby+kFHsj1GRqEnd1XWdGaxp+4LoSZhyQmBDEGb1ZAS2J6xSpN2hyFhCQsJRpN5O
ZsoWYqtB5wtWM5XJG5nehDp87bQvyjIGeq/aODYuNO5bYYCd3Pj7UIeRqCYfvlMxdcCGZb686uXp
UQmGKb+RyXol/0PvTBkQup2u+RqvG/X+AOPqpRV40b2Q4SnfPIRxVx4qFhoukco9T452XJiIELSV
d2YW8Gx7lnanYs/Q73GEjXfMLoi596nZLCj+4Libp8nmHPsH/HFypJo/B6lYldCdrLGENSzQxQH4
zu7oy4UoPKwLpSDbte8GpPhtCHmjZNOECCwQKPEATyag6iFl3BnpqJmjfoUbt8Amq1033VWJm87t
w2pEboA40wsVtug+vLIyCdZpC4p07l07CmR18+gab8oCbeSOYnJIDUBJ+Zp5V9qokY3w1ycf+EYR
7Pe2dDeXOkH40kuBhm6jGhOgfBGayH+K16nUQXUoZQaGfoykABdVTT2Q+vtdUXlz7AH9WSqnrhLz
qMK777RoEpYy/dYAXmx+8gyYkDAF9z8hiNFtFjMS1PUoZ5V03n0l8I3YXUCa0/Sae1lBK1M4AHCo
W/ObF2OzIyfKUU5xfxvH6o8Z9zM2qSJDSghooTMXNKAfS0BT6p0ernJO0dYUhUZURhfVYbBVrcXI
4roU6eyLZ5szi3jFfUp/5VdCb7MfdWHBL9wjAsSnfzACdJZnxWvUzO49MQWIW19V2JSAavoJP9q9
TvS1CSihWTPi3u4MHbXuG4T4r7gSCeeWrP0U4q8UBMN+s9op63rgJZfwbQPAdrKAarRXiGMrmpQV
t2JOeNLFz7ezp4K7VO75YfN4dgdcpgMWhy+RhU4XYndqZOnJODvrUPHWBK2TK51s6jXyuCE4/9cQ
0HC/t5NjPr/Wz1tfP97JT3qzpQijTNv96scXvvTEFpV/FH7dyHRUbM5yROgaQP+4eRxTqe3FvqBC
scSKP8YTbu0ROlsdq3+Mo2h+7LJO7cjSpEW3jsyljOnOrIokWVBc75lcKCFDWhEBA1nDHW/m1QUT
OwUY0AoKZJ9BCuhprvMeGm/miE4GJMNx96jKv8uNSs+Ia9Y3ELjXOpWrmyK7dGrW/JOBu39bvRwn
r3MuiPqjbNKmd6YwO4H7jO6MTv37vvzfUo9doOkhkCB2u6NmFBcyU0atEbxkIOjYk86LVlWXa2He
8hyLXWOK6I6/bLMMkeEFf2ulOB8uiGoA92ez5wY+h48RPL3ou/XoMQk5oNnHWwhS3r79nNuok/+U
cbqLfUSNmDW7VVojBxM63S+0NOdpnXuVUW186MDuruNlPfxggqwFtrfhu7MhmPAV/qtpOWMF3bmf
soYwDx/JB6+aQTW1FB1FOHqx2a9K/7jLuPnsz225rahNGuoPTkou5OPv9vXQaAERuC6kGNNYKZ9s
VODnF9L+h4p7x5CmcgTZ38rLnLozH9L7z904/Xq/+W2IAm1j4Am1ZNLw0N4Cd43OEJtXcfgy9VUo
mvJ5EfGqvTnSVptQcXF6JOJ9XHOwQmOis1GswHfC96MXAL7WYFdTXVcvNGJML0wL1CKTPvLxTDvD
/xueHTSb7jCsg6/Po3NEprmN9RnD+TBFa7xajCIfwLt9FT6Z8IatBhu6nv6lYoosblmLIiQSo2Ro
8N8PSnOxNyD6FS6AqT36E8SE6gMd+RHxDHn+ValJ96tQbZ6z0onigG5xaTezPF3bCCJyLE81A8Pv
H3td+hyiBSeyLBuJ5FPlh4Ed0p0WeUzHUjlYzmZfzSVX829eBVXQ/3zJbPXuEfs2Z2t7tothPjwT
ypw/K+SXFKfyboN0adGglyaWzHhXX9N11GX9bmwe8jJUhjDYtjMTCixCazXy1HqPYHhBO4BpOuQ+
LNMG/mB91VqTlW/pgWyjN5CJWrRk1zk5nSEid6rMCKGoQYP1SdIJxECYuNIEu420+OD/sZ31ZfTM
T8FRa4H1XT9kbS1wjB2teu38ZX6w2r6ZNwgETNCJO4I9cTCoDuquzUAvxFP6f7oQfcFnILG4Bs36
kbYZauexMtb8QwvL0lRbeP9RxmupTjFLsHapdjOHQ6Qu5c7Rh0FU+VVOUXBtUzOcPjnSUAFCA7LK
20b0IajEHz+N3fWPlkngTUraAR/Li8IuoAOMr4DJbw7A8TDBiF9s5HEuNhjZzyEpBHrtanFU3MAi
JdRtz3ceads6ydZd5kvQva7Po34xha8TBtsYc7EEjpkGEnnZocAnjAS9Vv7lu4dMOvCC/lbwWn/I
74Hr/es+cCXlRbsQ1ZljJhwr0l01dd7kKbnaYNUq5J7+SEaNVNHmje00EbCow6F6/3EhARJS/o/z
Iu1geMni5tJc7ENiyMF9fbedFTEUpTenhfxu5490JKuKbg6kFOyl+NXvUmAcCRO7Yn8H9XRB98Ma
t+N/VLMCJm1BvdnTSkZlovgitpVqBUEgBqYPg0qJHOzAg5VBZpAFZvJRtrgSYoyOCH7G9mZb5v7Q
AGWfXJNON0jNmE5DtxRJ2R6l8RMK9WXTkas+smLvUiTFtT9wKTYae8RDKEZOPOrMSe5BxJjsnO2o
cdYkIliYrRUTVReas7u7i2/UfSGro0K7dyPSwrnJB8Zu7WLMfs9RLqAUgDuDwITCdKIa6+oqN3nu
uljuvgELychRCAJMLqJAAk4qYEKZEhh0qKtA3EV5TmfHAyez0CA+c5zQA66RGWBAid7LovyBL2c+
3WUfVexRSCRqGxDGXgsC+3G0jMgzbfCaS8GgS8VbpFprxr7ln8bEnLySWS1827gXo1jSX4qaV2xk
2+qZ22zcNu6Af0oAzXuc8VCjs84Tp7brwMpopW3Os7GV99FvbSSt61Cy59cpOJYwIjsqJ05hcWzd
O53Bkh28IF+iziXnPmJs6cxVff+/90U5Fa4Q+m8MZiJWRPQg0fW9sfGg/OZl+PVgBT6Kz+i0aZRk
BmEoc+GUAAox5rMLLmW1w2sP0TLBJmeYSc6YrzT4MjmsTIU+PXKt5zzW/eGaccfQuE23VU3hq+Yx
p5BK0sWF3GuDtdfF6gT8pCbZFdUSrmTiFOVPqZjQmV+qHVr0LosGOHiFsWNt3BGoHsH5sIbkQAgI
UoAlMN9CJFiKFl6IyWWz5MwueNdxTYOHXI4NQ0EJ0d0Qh+hFdRBwdScRzYJBKQtOsvygvL3ZqaDt
b9advdJ65Z578zPJ+Cf3iB6DQDJF659K3h2BrqySbFBloxBknL2LZwv7OK5Fgmupn8sizi6qUKjH
8wDt/7QzW+0mIWC3JpIhAOnUfA/Jy31O4cCh6l+o68Funq32TFE+JCZitYo5QwPrZnlBY0a2qCDV
aIF5qny85erMbQKqre1p9SD+rHn4k4Qe1zx2T2Lyu19B97qmIO1J6KW0+jrloQLQxi6Eabav/9LZ
o0hVlbAgid7eiqy4r7RvWEP1ciwjHs5FrO4kC1LBcroA+elBniRKfO5f5NUsShqmSRF+XRXA08ow
JU64UC6hv9FYUEhGVUfsZloK+bfjlutFgRBGf1a0XnFhGRfZ4UL8eQjdvXqi3DcDwwsbXuvS5W7g
8J5AaMCIDynYjDYJwXoIa3d1f30e+7k1l6yd7tjiKBvLzxQ5Xkakh3QRr/ijUCzqv5P0jlpXhz85
yvZgxjRsAN6HMWEmzulppEH002iKGHKurPYrsO2ueF2YhwGViBr+rhk/GQ3/Nkb3rLA0anAxs+IU
WUuf+ruHG/3N0YNQIHUsI9plQrNiY1wzpFXEjCWBz2vz6f8eRlUB0BHpUWbzK3jgs1bqcGsKfIoT
UP82O4JMd4Va1g6h1jbz8bHI1oib+veMrhBDXZB/9NS3CM/a+QU102LaCWKk3g7tuVukPP/lcstH
pATsTJTDpdbWV3p9GTyu0yEAKGeu4ieioN89ZbNCUfgDVb9AbLB+Ypvkj4y7K8DAyix7/b0EEIwd
EPE8iKhrq3Vg7RmIu/4FwhaTLJliBxDMSmFUTVcjqPZJ0l+aT1GlltGeyBEjd5MZs0G0wHTvAWD7
TlylpWYrUnPsgR5qctRFv60blf/mL/H2PUKHPhwrA1ZbFFt7rWY+YPC381ane70n7tSMN+OsFEN7
iqPYnXGjRhUdCQnS4fpcLJoekL7gagnUJZ8eeOW6t3KLVFIeYeo6xUzOwctZXtXnVEw37RJBfL/T
CwKryodwrlCnnX2QB6SR59R41n2/fVa7zwAf/gcsQafEmR1+MgUJhX65n2djHF2D8B4Ae3FyDVFY
sczSrfsuq4pYfSAjb4+L1XNrHRUSU7CWYWpvVZI9FpCpXkzE0Sc+1eJdixwKUb7jWoW56GjbRHlt
rl38YlQR74krjTdh387hVKSyVDKng3H3wkssBrI3/RhBdrFlCfcorvZuIU25xQymq0sXcrSnBgRg
oQ8/3JorjFwZg01v8H8s3J+7cUSBKb51mG2PORxeEEssjTegxa5rcEjfKPZJPSo6CzK4IRHI4Ymy
BThT1405q89aovS304jKDvE2LDrP0qjrcO3qfqHxZVATxkmJs0BxJ1iijAlsQGrLNXS5Ue4o/l07
L+G/eXYM3q0kx269xG82M/2kFNnsb/b1UGfVk63580OGtzQAkqJNF8ZJFAQslTRKizmoalWyJA20
UU91lN2YZOIUT49cZx7xv+yXANM7avfFmZDBgMGsEOQd2cjnSrMtKeO2dThChnnj+Ih602yqRCu5
mdZ2vpNgvthh7KwgK03Z+j5lzo0E79pEawSGssHfwCkBFNas5GgVuyapmONTo8cfb3vejxFmpgBd
KujWLyEfkHEg0eimg2QsJKOWfNBAu06hpqmy4peChMvN2qlY5DjFOoDxj6KPionSNSgVL+bgE9l8
d4AA+O1N+ZdONkkaDWKJbEUqMenXmtI4WBJk31loM32Y+EZ6Ue2g3WeEE85/rKhv/IHlXzbaG01B
XKkqhEHYW98gEC9d+IBpeH1tPXQwXXDz2VYiQy5JOGQ9sdR921co9GANNgPjQ0N2pPjRGeRvuat1
LYM6f3z9eJ3LytfqKHZlq+b2m76qm/Fccrve2cUCdcKEL+8qvGketISA6BPSXWfQ5w6g0eVf18IH
MhJeFePtUysYjD4tGFsnHaagbrTwW6k7alK5Ujtmd0J/aZY4pCnq17Rai8tH8Wfuc0I0DqyVNB/p
NlTPwH3lyFFh9p7Fv/OnY0MgjHOQRw8nv22Wjrf5oONYcvE9xRshyBXc+ZxzzQwkspZHqQD440ii
vMDk1hK4dmHtB01du4lMFqSGYzY7mBvrFy/qyWeTJEIezULn5l0tf5vQXQ1vw+nb2pp0CcH3GmBC
aOksxdNaoQ5MUZ0GFzMhKeHKnScyF3w7DYwPs+0wMj4sjUFkHkvkrfd5xDiBqdIK6kbZ+Y74v94r
q5gji/HHNETFqMSu+wlr4BRhWg8v4cZl1Lr8ULFITFbvbbDvIt4z72oCn+zWi7W/VN/twHboSRAJ
ATuxjEq1Qc3nnsHzjGbGF3B+OCoAp/HIwe0T3iAhTelRFxr8pLEeGtukBEmQi6tivhnM4x8BjJHW
ww3Y/xLbjGtlOtgDyJRxknAE+8H7ErJJAJKYLZ0cvAH0uMyBkLEyFrmJaoPqSvcelDNZXlw4OYdD
Qus8rO8DmZeksUn/IXDLZHrNEEJBVj3/uJxxKMqxnbDwSrVEovuXABpQ/zu7csP6pswxY+dzyGUi
8A598jseGs1a/s4ah+SwRyeQ4y+7NjUPFKbv+PUVK00YPGq0oOcNy3WF8M1acfkp/WO5LvGl60XQ
cCiwefg2CVUjLWFinJl1nNZUwcoeob2tAjMq2zHDrnhcdAN4JLLrZEjp4fn3zXCvVKLzz+CkjxI8
h5tB58FHDAt/f8Gh4nXLZcmsRlTwfPh1GUIYjDfyZ/6hzzk8uz2zTgiTril3ZEN3KnJq8FSlrVFA
YPkdDJqmE7/UX5A2TapDDbylSH7+XvZXkpUexCfq/GhA57WveNdJbABf1dAvv/mje7hfho+lICR3
VuqvSj4gy3vBN8VV/xQYxEW3MQZjvkLOg9PVYboNmW7BJ1TdOV47vcML87vA3JMP94pHKU7uF32X
VQTH7I7sFporExZgSWqB3o0TSiwoyzM9O6Q+zL6Ewcd3SxUKyxwsh2fn8FXCD66ihvUMJX/swTHk
uKNuh9Zjaz/clwo3tV+yxnPlp9yrdnPCVqlIuZFEGDVNTKYmuDM0FDFFn5L1nuQ+puRteexNwoRt
M/39EcW5Uz8gwrfbrkQIwR18IKwUfwHqlzTR292XdvYLyNIXkcvxCAIzhFXBtYIOiQCEtypc09Oo
pMf/wAdU52sHqyLCCs2kt7zU5X5iZycBiyMpqGzsV5Eb5Rg/oiFKq2KW1PRO0iQkpKP7svqK56cW
bWojOMrUAJPZyYWbOAXhShrp9/myi5bS+nirbv878H46MEMcxtBVSEufybTuZCmyaBLKw8yRJsiO
0YeMNuU4/CibFp5fnE3i3iyBvXlwVJ8xnNuUMEYY/sIofOuUDvgBgjRaUUmOdF9egoWZuaqx3P/Z
68n++V9V6AY2ri2RNgUiPuS3+NdAPBQ63SAJgMrihA+GZv9+H+tjmB2x02PXJ4SxEmHQQaSO/HAd
3Dvae70w7TpNBUDyoBPos4Vm1s1j4J4ibH8/ROHrxMGA82y+kRhsSDkRstyo5stFwkLbOIsHuqNY
vd/8bcGrUfkFgVBHng79c+TSvdAeQvTUvMIN7aLJ9GKjki/z0gMxKbOQoNz4yvif9nrt/QxDBcGV
BVCFWPF10hT/8ZTtUaWCuG5wK1RNd0JINgeOubeZQYtUYcxS9zsTmgMqIci4XuISJlwKzYDhoFWS
qeby+9NUIXM2XHabpROIlHBVNrG/miRCawu97Tsmxd+O6zpKaAKgw+boc14GsGurPRTwGdeQOraK
xvF6GQuAg2xJucZbDxNmPvPeLQNz4wTzgmxDTPydSRLDwPaKz43A5AunxhJ29LkWa0m+IVk4M1jS
iEjPVWiZp8aQtLZ8y5y4iBLdrmmq7ab/iqLGVOUEJv5ZDZg0tdIp7iU4YWI+sVC9qSCl77huP0Qv
ZuARsRNTs55CJK2i2rMyYttn7QAKjl4NbAm9IiHI4quLebKqWs+NznGk8hZnO7e4lHBQ789X5LqU
IMBHodQCjY6efRVlH2NhiwwmQnpWHQ6Pz5om7au/Gwv9BVr/g3R2dB0tTDoyT525HTcIW8V6/puc
tE5T/eNy6EWrtBxCr8wIgfhWa6sRohbmZ94z7etI4PO9BHxo/ZKg635aTaooPqtaHNzd2dlZTOdm
5fcL7Rd1og8CmT4SHZqMUAi6XFbjtcRAnLmJJkXJSsGScicIARmrhgaTnJNK6hOonI1cDRq2rcDn
Z1BbIzgmgyhJsryauJRqPTnLnsj9qKQpg7B8RmRUg/7QpOBTdTM4/gV/I6VVAJ/sG+4wSEMVD7QX
zNWfUmqqYu0QZptAwfZ5w6s9K+Js9i23/ygqzV3ZrYRraAFSgozPcsc+AMQ6mxJBfTtN8rvPTHIk
KHWydvP3JNY1j2r7WyYuStH6u4glkHf5I2fxdflEQs57X5KfWybtFyISkVvIEarnNeK2xKSE4+f4
U47srzK7F/rAAf+hESJQMTgkc9UpW2Nrhluo5MIjgzMXcFbnQfyW+H8O5uAppio/UPRWTZf2CxLm
/6fsXwKB6pj0Q4kyJE1rJSvnMdy43E9hFvRZqW9LliePI95/t88MGIXRCsEYJKx8Ho/38S0L8mYh
loG2wRG+wfmvOqKrzoT6r4cw2EaBoB3Y+iLBvVpPcvecS9uNIhID48zntb5BtwG6UwKlTEdmn/JX
7EVz8WH7l5KCzuT/h1Of8KK2MX3pV80NfkS3UMZSjb7d5+ays4kTs3f3PofRyKXu9Kx22XZ+QjJc
BQKLTYNdaWpdUL4p48rdCNhxchTRfhtJxaIyM38vmhQEICgZS3fZMr/gnRGeK9B1D5tAmG0TqJvb
orvaAxY2ADln/zkbEgGPmA4rlh592K2C/6pcrzCe+J7F7uIpaT3Ns+f2E0o1N3zndxefBQyds5bE
cFo6C/xNowPKVRTF4gz1Dzp66PRNWwUJPAWJONlvNvQC24bOink3wLoFK95eLTYszkcB4EAWzUYS
HdEFJ45UlH24NOduYH2en72vyMEiFdyas0FN7m3cf5e7bT2GN+kf93I6Segn6db/jMOqf80t9tp2
0r9ve+AHPSSPcZNKJwOYnz3BdcyVQNw1hziLZQTpigZVjXRLXjzjGgQ76qhww+LbbGTtQGbskjj/
gASu7v8hjbaj941Jo0+qbEOgJH2MQldQSeO3SdfPoX+d4mVSVdqg/ctqF5Q8A+zZsyKrC9bY039j
0gUI2+iJ4sGRB31GN5+4y4QkhTaAWPikreNpW56KFSx7QwuVntIZcNzhCm/R3qvVASv5KUWSw1B+
iPhlCkwcwCgIAXV3w7ajh9ErPnKeQMX/g7B04GRi3UB1J8LGi/giAQg6aNM3fSykyXtOi13zzH1b
8Fgs0qfIoeHrr7hGs2pRQT7wiqeB1vPi6thj9nzcg75iH15QmjTv7AZ1bwWX3K+f2INN9rlqsrYy
qr137XvtXIr5Qbk8c/w5wHZdIQU0s8r5JCn7SUfWzGERei62X6y2K2GqxiAiYuBkgXB2CJNBjUzF
zhNIrK1BAx//nKbP5Ejho6t4u5bFXA1OYu4mldUKxZi+/Mh37YqiXpI2Y2jAEmvw3K49GpJw7Fyf
AqY4xL2IoGQPnXJtpp8OhQ0Sxci09h/5h2KpY1Ny5OGxP/kCORgS/guU12NjIEuIF/4MFFmXcB9C
d3xY2PCAAKmgGDgo20vvR/1iMjPCQHPO08Rb0M0Rku4Fobs06Np25HlB4GY2QLAXn4Ih5lPqyEhb
vcwENPuyK0/hHBnqtZfMmWo9zcv4BgVp3EQRgNackUrr2P23v3Tt+f9LWuZ4rn/pYDZmsuXJHk2J
5Iix18NfSVKwTGTxXHlJOkUwZuoO+msGZKDu0EIjxmTWr8/hAoyrgQagFLnjXQrNZFfz9C17/F/S
f+3a0veJr9CfzRMzRPPtG3YEzzI8g4av/dVW3IRQwAHEgKFH/d9KVNwrx0ttVMdfnMKqq7BOldbV
f/KnAEIMGNZBAes0N9b2JOY2iktrU3rKCG6JNhGkDqaW4X0jO2sRVNzDYPFpLdAJ1l1U/b3l4uCL
dijZz1IbRgthNge/guRVscyBGJiaqEfOdQzYqnOpMQ3efJMGRvQxOg8MU/wkWS2DAYiyYx4PGS5h
aPncTt0myAlhqRRa7sXKokwHHFfOMBPouYd+WIfZa9ZrGIzWB+B8BLZOs7Bzcnj4ua/cgIsxwfQn
YaufnTzSND/orqmo5FEQsA8JYsMi/yjw8OZCOxmjBgI2YFB2DHOk/8urWL4B88qFP2yjLQGxRgd7
lN2I9v31LhRxPO5FBD7MNrYg79+/ISh9iRseUE0f5fO70ekFNw278SEPyIZpFkKBtavvGZdHzlSg
JYHgAQCMnm0oFcCHGygVFQF1x4EPKurcFB+e0SvcAHkDn23JNmhq8D/OvFzD+9QFa3Yf8EafwuGu
GHqfACO+Jz4jx0VvIBEBBYY1qpu+IRZfd6/HKOg90rTTINfWAyUXJCZiLEAD0N4IEEhAumY1mZxH
lwhXUlMnZlaz2170MjzZK6chM6+VJrmGROvx+SYR40IrpGrCZeu62tL6JA2uSR739PKwT1umPoxg
P5ne8qCgal0VBT/qrwRpZZCX2uZd5f0Jrv4fSryRGNJr5ul1zbad8pjnQwNwzWCqMSZ2WIObMk6f
FhyFBMgNphLXmF3VXj3wu/rGPHz+woS1wqQ0vXtpha6b6ltK5WcmhbyHFOWjEfNxzFq6zLDe5Hx+
lXKexTJagCfMcPhuW+m2Z8hrw7p3g8//+4t3MiBZSPxhNzS9kbKVywZqS4Ty+zTJ0qaE8aZxoFAa
7azmKy0hwxVo4yTHAV+ZNTkbhagbDoqoqHIhwGej9D4qys7Z+FILMwX1fDIlDs7MK47pawQYX8Gn
IQ0Z0UwArjNzgWstQu/v4fmvnKCtZIA1rkXSlFZl890Lt/PKUAa5s966DMt7aLJQsvMAZYCfVBMR
68kFd6NXqMCnIms3I0pBjObaOm/9nOz5p5/uzCDghXXQACBrOO52XFrfFIRdNbYXDSbohzP43wLG
dgXJeo+X7e47o3aDcOVz/f2TEUfWmD4eovalHlTPP4swL5e8y90TuyzqjvIWduP+NeRlTx9jygkM
PcOfZvl+pI5uxbu/SKH6eU5URfCKRGbXmc5pqK0ACLK9eU10JyDYtdQshQh92cM57/IC7P1EaD/2
SfnJYXQStDfxg5WeEDWkpzumQB7bs6ERL12I2VurGVlQH9s8ivWzVNZMTxTOizG9/xIDqgZeG3rk
OWWl4lgsJKIdygVHjU/JiM3PaPleRIAriXqLn06pRhhrQTHX0OQSE+oMoql7NiHg08Ol8idevWd2
640LZ2C0yukn2XTW5IklW7fw+Nq+wBf4JXp8QEHjsTSJVCaxx5LD7vgESRONiqEv7ARnXtRtRTx3
+awklcE+w5tKQyckv1vr9uTv5Txtyho6jjaiQiUfL90VFa4nPvyfG4XBi1koxFhNEd3i1APZz0md
8aHwcDdN5FzpQHXZwDn9vDI0hlMdk5E0X6v4NGP9/16CQS4nGBHHaGMJdaeYDYvR+OfhFCU3AzlJ
yVlIQaD9CqVKURGlLtA5Wr5mXiaJ5RFyhzCxVPKhYG1jhWFLwoSBSkwmBv59BDqZT9BgCZmgjzcb
cm0mUlGZIM72CXaoKugeL7NvFtT/iML82FsfH+ngbz0W+K57u+BYf1xcwPPLKtxOgQHbuajlxSXN
z9J6M9yN24bGiz7YNCZXC3ZN5+KBCrsoGqz/X83B8RZP/uBq+1lNsLXNDUw/xAMgUUcNuLrN1XvB
gzPZIfq6MB/AfMAX7ky+m2y8vcSgvkDsfk57DhMAwJQXtTM/OqBVD+0tDZSt1rq4szsZ5A0ylfpg
RW2AvR/dzKZ+r7hKv5cGaYZs3ZvFS4HsOx5TMqjbTs6FMhvIOWepzVrmQGpd3C2rOuTvo9MIyomL
+8p90+PZkcNrdwGOmgUOskf0sm+redo/H3agjMS/MbRH5M8suKFqVEHxjWvNfwImrPrRZN4lBtJg
RrTANRZ+WOFRBtyP+GGtr00RRRb+pl1ys2lhRWqwGlrNCtEWven/NLd+eBBoE3bu1P2/4ptPtSMK
CkaNzDmP74aVh5VwQf+CkD7p/P+mFPX2AjIRThF8I6UD6vpXL8L9T1Va/AGC3UKeJffi+PPp6XQZ
Q/CUsL8wJDWKFVPJQSNZrmcV/M+N3nQSkiLXi0wLljmq9fg3BV+gLrN8vMOfST1Gk/MmbrGUJypE
xkTP45XiCDKFNSS5nnlJO6usvGd8HfSnnAKORLZJ5n6O1+nWGTOt9mxYAHOYh6YSbs2lZQAFrr+c
C6ZV+JwSmMJfJ+PiDfT8duj4eWaSuhS2ET4VPA4cfG20G/MuHuI24xpYcsgMxc172jhLoktXOQX+
FnaJ1l06Fhwicw/i6Aix5OEP0+JLNGksqQC9f5fKh46Nc+W6LHtFTOvUL6U7+OmaFoYbNNQJE+84
1cBIocUPavySqEeoEeiPnNv4ffl0S4Zh5s3dT/1btGe8Soky1lU+nh7uZXfGaUcQ1U+l7xVgCMKm
pwteDoW3wryqd7DLSCkrX8BaPw2WMJpBvxT/pCsHKtSHYHt8ANUgbROzfy/0n1ahPpnZZR9veUP/
Gv/QyQdjp8Ho4jkqH9YWFflqcnbPVBjPhubXMPZM7xv5k9RuingRAajCRDD+mdvFnHcM2fWSFBBT
kzIpJIhELsCsrvNfpwdv7MiGESq4b5MwBWuxrBTgmO96XnxfArA/pgm9syE6XesbcL0ZxjWWu0Af
eJ/8LD63NaU52+yEd9BcUim5TCG6Ls08Tmy+dc0FjuxkftPfbJMhdxVWIr72NsX1iKVjo6kuz84k
zezflK9qNAnF14+0vDboT/HMZmBNeqcgimGVI5YLLdz8kpLMfOXKp78w4juKQhra7jm5DG4XlHiu
eW3J8BgMVaaNISvkWTm97wdYzKPgKnYWpZPNgOpJJVzZeDzA6UyjOg/09SNzHltnNO5fV5JRUgU0
oNyAr/UGXxtXiQrtj83mpe7u6/tKpyiYGT/sBBtglIimU1EvRbd9C2Bl1xWV6KFq23vTLy4bt8le
Sw1Dz0lNUftm6D+KrF5rTCyL1G/sOnMB/pGHA6i8B37kcgH6w5d+bffZHW0SpDpBPMNMdMlhdheq
KRvb34rkvv0NeLXlma7Fd8QHsrSD2B2GGqLdKIvkQCP2rU0fZVmk3LhgLTiw0249Jg+8lkXgZOZ7
RivV/s2AlkMdUENS/DZ4np5fNwLBsTv8UTpLUo838DOB9/HDva3gUDoEkbpgHzHQ1YFlP4NW7T87
ygwht3ol8EvFhP+f50sNLH871U3vvMo9AxZoJuRsuFt4Z4cg4suEXomJwp+65K752wypAy4usThB
MRyTv4SONx5/alnGMok970nfNIoDVcE80FcuAUsOP4KOUcitRDalYiNalhTIqhOihE3TGr9ITRb3
oRw8D5A0+n+oMDlsUhg4qgae8eFkaPHoqcHKWQ6AaLqiixyxYs2+8klxJdINol0giVJS0EQh0kap
zVzPXWFLvinEoSV3/XAE5vCP6X3Ow+jGvAx7W3SQ4sdr+J27PzYEwLhjJv29DglN8qLZtYdaKmdH
JQEEEGELILvvA2FslxiJJiqTq/PFhQco2xuMPxhBsNn9JRndi7dgOCLhDpuTr9aNOVyjDPSpL88J
TnMWtKsnsqZJ+oly4x7680I6GFb+VTUvs0AuQX4zQ7aU+/1qqJrdh51CYffNZ7ILmEfn2/vuQ0Ms
+TUFkQuDit+p47NPJLvqRUwem/pLENYGMXPR7jWv1OgyRnoOm+hBf4sZ5c0nOQ8/hmssHfHLczHb
OI8+1zU6abalD2Z4PVwODE1hHbdwgmUHKLnEVAirMbqjXg9Q2zaH/73coXTVvqH5HJGAzSPBYzEI
IatekcnwivAQ6yzkf3l3+uPJkRuUM8z9XyelfOISonaOMWbIHUB4jwFLHuhyFhmGaUsHJ8vX+SQv
pDmM61dtKjvzAq/oMjZAuvMS0L6CBSNGThtX6Ezpe80+PPl7s9fxlEc8rEL67LhL3EUcSKbIcGEV
qbnMy9sgsm2fjgWjHrpDd+On0dE0IUEqigRKW0YpGjBDJNrGCbgE+64um4H/O4pDlq3S9tgvoYTp
mnbBSbFzETQtOeGaCM62ftTzkDh1E4viJ3WOgl/djjNaKo4jAPCsB5jC7MOtptZWrgmPD8flmDMI
7hsmcOZeXCusbpOQ2tgXyODp2NNxFqyES0NZ3+RTKcSSSaWVW+lJuA5GOuGQH43zVw/bCL9+K7QR
u2LeVT9bdd+52bxFT/n1nrVg8uxvQDtGlBal/l8ErW1lGJ4NsutsBPtb0OwS3gAXHZu6VBVbN+ui
ZApqaAWuVkKUQaXUdTrFc8mdktMw2OJ4KR2J02IKQcMZbz1ztyuJxkIbG9UW3np7N0c1RftNOau0
IvYooJMVjb0d48OZsdhs7zbFoBEua1qTA9GqtQagLQT/HBre82bIRULPmi3ECfJekdk7ihiMs2T/
cQO6Mt4UMvCsm/fhKiqCQ3JRjmvYW2nSfGbDHLF76nnWNbRYZW62bXAY7nHfd28ZWyAiG9AAkZtz
i2FwgX3uRhOlvkYsM7ciXGj1ffbxdMKQIKtZrPW6t3kNPUvWE0IyiqrLLke1tB7HL0FcnBMqD+Hh
bqq0wLWNcopcp8E7Nzc2dRs8ojnfrDib0/fqSI6w9NnaqfPEqdaLEGxON42vjcbKIylRPOCiFJD9
5N15nAxoDEXSOS9S3H3hysqgvmJphVXjWNfVjn7AD9HbOH8DK/aoG7y5dfTA+PkG8SmpIMNxh4Sm
mGemeTgdniTSbpXGAiX1pIoNkP8MI79YPKZlxkMML4C5WtHpYquo7FQPVgHQtm3b+LvPnIeF7+Ys
zszB6ATQNvYy1fS+vaZaVokXJ+FV4R/Z8R/WcafHnF6ztTk3pC4a9GCKsPmLnXwJLMsQ7KLTR4AM
IaEYnW95hhFajRJVk29sspcM/MogSmrotu325BUR8zd93U4HSJesWk3Ut5hLQ/dEd7ltqxtMVoVy
Y1ik09/zzPbiNbe3CjPk/p449sk7sWPT/I/bkqMatfCEB1iE03WS9foVzK6+SX+HaHKRQ2zGW/kX
AJHc4XqugbaPq/koDFE9VCn1ydd8HR7KRZbdlkS79sZRQ1ComkPh+rjJrxaFUXwyhU4FXmnHkUE+
Ig2YHPaUN84aVJOZFSsFvYZ3/PHD1Uj4xALslODba+bMwpRKFEqNp2B30e8iY9S5IXF9i/40RgNK
cQo0UlwhbzhcBMINs8ChUiqf4V2SRhRNuFC/hH/uBnJTvL46xjxRnEEPK2fT6zEqK+uv3bWRZRXk
qjLL81sP05VSSypyxZNRVSaIQuCzbESBB7ZfSEOWT7sbO5czg1B/r7GQrqwC5U/4ZVwJrC1LUPqV
/p2ZaewRXcmzx4EqeRdw+C3H1bJ0NaX1jK8bZgMwvHNbJBGjlyzhDxKjcd9vvw7mtYerEQhn36YN
m9Ku8Qs/BgurOcywnszr9SGdtNgIFtQZnf6mitn9WHFKHb2iVXZUPmXEhZRfy7I9tHVnjYjd+Xzj
oIjiBoEIu483KKhvJ+3uF7i8verhWMw+zkxnUrswhf7duPEyJ534Isl7yqySTW4WHLJWsNkrxORz
/ybJXKc/aUcxkvvCFWZsBpTj4IcorHFJvL7hIbZZW5YkdDMdVEi9qFhaId7hChd7JnCBLf7LCU2x
i1SN3/LY7sJk3GfQiKXdtsIUT3UCHJHPJLj/mFq7XN0K9tJK/UBvpya5fNAvotEN5MUXqwYwCv5k
sTteZA/GUhWDOKCWZaXxh6oRFWVJfasgD8RBrMMDUeocL0FfbG0gn5x6K/Y2HtVZWwv7Z+OHvfb0
zsH755SuaDNJM7Q2/VLyC5rr2RWQcuH/TsTw/2ZQGmoIPEsnz5xKHedGhOve8HxJ02WbrwLVnJbg
bJFkKgv2u3nK2Z2uzjkLTq0n8Q3oMpivWcbiNWqTyZH7etwHRF6nnYCOdV87j5KJvncUfLv68rgW
GfxI/aYJ9dSCQ9F7sRo110QDjFK0rEqhamfbPXuRdhcRqWoYZsVqoBuEziUWRmUSfTzquwKVPlWf
5LK3bp5KfvAaJpqgcX63FkC8+7UNZL6QmbG1LFlMsjfCBid4oHyHHUoSYxEtNVwx7h5/f++4XJOp
Wzu73Fk/GfG5l0ACSCZEqu2I0MR8Fop3fZ9/FZGkxTt4ZmvhCLQ+wBkT/cSFU6m4dEWd7KXpPEg9
rFLMD7f63BFc3NPTKS+C6INREAQmUrqq+iTJAK21/Yi1aLV/FQvMlrri2TmJifnmUXFumjnQh5h5
n3CH2bJeNyatCZofwU2WEIVQOv3cRv7rjqxayzliOnpUDkMzrqvk7/iCbnRM3/CDg2H7lEwm3nAH
ASNe9fyX5jVWnJCpiaBgRCKO7wtpbZTYzJE0dhAYzU1ztFjBcGNSsW9UPbf1nVThD8Yj20cWKwwO
LVs6IEtnQ7L/zinRS+EH0CDNZLdL/0ChAZvdXtfa5KuS8QwXujKgJi30a8gU77/ALNpioukxeXIS
DSC9bWg9timLG90cmMUV9QHJlKTsOJYJWxtf0m3LiGZR01SUeiN+p4vaYXkC4/TAVEt0FrvA6OgY
LfM3mIbLKvrYdwMvnRNOP2xnc90AZfdmYiu0wpYcQZnRUrD1Wa05G9HmS+ytIAHAiAquJj5nMUc9
mJM1If8Gcs/P2jVT+NTVVW1Y/NIjJHIJJdQwkuju9nXnWJvD2yINcjkXkXcnep2cbgVGW0ZxGkl4
LFh0fB/e/Q75Cnn/tAb04PG1VU8DBIOkvtREMFL/11cDv0qk4/JOVZtYmW+MAPJGFKeDMJ2jfL9V
mAbmS4CENMQses2Fbp49ooh3Hb28Uq1gmiUV7EUCZoWUyYAhXWoTRBsQTGebJTX/ar2ViAcSDR45
WQfOF11mvLn0tdZTZPsM/8ce2XCra8tkxIDxPvtBPbfbFMr4c0v6itqrRsWW5lDZ9XD4OKAAWqS6
MIdB/H4bBn4lfqPEluZ9atbR4sNPZo4auUN/sYhVzAOZ4AGFmCbTXLt6E7aZQ8pOiaoBO79Dtpjg
B8OOcsDA4r0Nk+dpYuWf58nouQbrHe+uOZa3o2p47j6fTzDCl4iuuGukJZZQBSoT5ZRs4CO7sltI
7cYTncoUC/rD34Rjfyn1bu6sY1AKuqQx+U0z5XE7gtuXvCG14rA65fFfIOvdMb7iwR+iUdDPv5ej
YgipUVdEE8P0YK4KiZgSnACZ/c8XXYKUEVVbtVtgqOTke/sCG2cIbYJZKH+kj8DihERAAoJLK4aV
hme9jTmz/zQuwojT0GG53fsTdO9h/Yen4GrQjdPoaGZj20ZJdciMsgeJvnlO11znFYYCuLz2hbvv
IZvRtQCNZrmotRd1jRxF8e2PuPuSi/K3T9MMY2tOegBO8FT6hacMEr6a6wzq3dc1Uxr+yc5wup4e
Ehlyk/g3Kl1hpQ+esWF7+k9xrTZc0eKRIIPWi7R5nhVXqfvycQ6uxaf8+S+3/sGQWyd3BMkw739P
SJzv/LLWDhpW8VSAtb8Qisr4CUlYr4lY6aWNCMXq/Ku4CoLHJdlz+TiA/Lgs+nopIv482Dshcwva
juICnZ2xwj2B6QuCAZShKfhJs27WF09ALQ1pBGQ+PBROk/4zPtrCY1DDD2zzuqgfq61ag08ZFQ+B
3jxmlAVXy8VpMxNoyQeGVms9xOx+td6YcE/sdoCdsUBTWgun/0t0s5L1RS5xuhKx2Zbb8R3Tq1iB
vZCxZtLBtrcg58XpK53jmg0zqtlhypWrwNGP+dTWDpDRDg36pTg45EXE1FgyYE9WvXyGQddQ4nJD
tmlXwKI/y0gUVLwlIoCA738k7aEqblW25QuobCxvJR9/V5ELp4C1Rvry5nvOqOYZquoOKLr6iFQb
JSy9pFZMIO2B/cJ4MWXYeSnLQCPPUDVCC+KWBOtNIU5fyXFjIGQM26awptmPoLgF3JQ0DnBYC/J4
cLo3QNm3QtM27yFFezfRF9rgXVlRGS0VJ3kF+zGYmOSkF5UxwD7qskoO+0/RRF/3I0YuhPLbOnXV
gGK1JDEm0bamGaJgyWgSAlJKqJjOarS8FdBJyT4mSlCufANiSsH+9mU7Rdw3Tt9YHYtd2VFW1oXe
lYc73azo/WBlR/6ru+YZSDVmdSkyAFZ3TK+d3aPe4SyOcalFYbI3KPIWrqUKF7sw/tjL+XGPGxms
GQ/EJxUk2CRJgxtLy+f+5e3OLqzy6xNO3UWYXzx1ICHY0Y4Wra0wqmKeIUkk+wRClb8oQkENTIQC
b8SHtnANGpBc0scltwQZsKj803hZ6ddVMRV1C00Y1eVDphbp8yHsOTMqXkXRurgij1Q40TMARtIZ
z18T9ybsqXcVyAs7pMK8gEq9F66k8XYlIf+LdudAAYtBDP7skTBY6hTtJ1EV4GmOErn9EzGhksMx
iHq3TsI2GHwcVicTT7WWjEziPq/1MfKkV85593JkmCTEB+9kKYRDwfINTJFIkXxilMdhB2EGUCbg
eJS7iMDJ3Zi0wtElx05ko29p0rwvzbwUIT25e+B6twAypDEK1bsV38vDOD8hJ8l5RtC28b2NizWc
PNxtum/aTeprGEym3098CnXPbgxZVIHGRFTzsbdZIXMQgEuVww7exBEv/yss0U5igu01cy3nz+2W
RyEtALdY7Trh3uNfqFutdoWPDshvsM58C7nZiQOqq/1cRqLbiw1Q7Gg5+Hm6GlXVM4+ZDH555ATz
pv1wUQ7FnOAIWaGjHjkaVT0ddf4YRnjS7U0qZlUn8Oyf7tKBNdjKms8BLMFCJEC7xnDho4GA2GSY
1KFHoSR4CJXtXptfGr6ma/Op12WDxMwTzoEwREGCuyl6VwfzDXKNIk03QIYrg2vsChdqUeLefYg9
LzjYb5Y2YRyWsqJMiIrwqs0wdT0rGcRU4YiMsimVNVBJvlgC/g0dPjxYSw2GIZyON5zDLquClieI
wX5E9y86+UM+Llzzsa0li4sLVNqR6OzE206iTs8kETDPtqmjLwsOT68TW1cEJffDYCfJEnOl5l8C
Cv6kTGwGajclAAuS7gCJi1UU+MxC/yo3LZ6CEqDXeJaW9FUht5LNMfFTHDxv8u3EFKwxVtooJV9K
V74OOE124Ms0nFYUyyOnXwgfelCXnH15sJJTZfFKNeX6igG083vafKZSeZRIQ8Vu8+0dhoPEqRZl
GkdbsSD9U8QDt6inQDo2w0if4L+6G1xhbR1J2vzRa2uiIOCw6gnQWUS2vtYfWt0t2YL1Cpf77SS2
7NpqKx/Tn9XkOwjZhmfheXmpnKdF4cQx7rWpfRtqgCwyIE+Cb537Tv3U1fPDQiq+qF39o8ex43n2
CvmTYyCmsXQwKJYm+yRX+e8QF8yCJ8j6bl7z8lYD1LLQBBbmVIG/t2AtFtSoLU7fQ0MbjxweK8Cw
Wviv9tOfs7USNefKeTHZ7QFOZCJ3sH9suJoAYVuRsB7+wDk+XTuE6LMsTdaAalYQ1h+Ql9JbILGA
YcHLRn9uZN1iPgQGH88VkInFgv+2fFH8ZJVDVXpqEo/sOxXthKN+ktYpOhtOq8vRsAixJ7E3GHx+
hgiqFRTf44vAWcLslN65URD2a/J/fA8Sa9DR+YM3XThyTaDdU+4mLGbUT97+QyNkHmgEApkyqXTE
lf0e71RuGj0UFX6Fhr+TzpWdA6LrcaOx8zILTHSn3daFPI8iiKeIfs+YL2m3FhJv6TfzcXfKskHf
o6sqRPnJQoZduEFJTe7fCwmphg37z9/LDF1aSMfvPQVCloALIHIN+6DfQ5q8gaeex7GpFVr5hlKY
qQnP5JiyCKMV2sIXVXYP0FrsMcrToAzHX3oIt34pCZeW2kBACr09XtKTekWjbn9mO4t8q3AUbMCn
yhJ5DxgUSYdGmYtVzEV5EkM6O9zP+VsDe/oCmI029BMrcCMeizP5kvsNdavfVL4lnnE/40IL0Cve
IjoF5Iej86167vEJDcnK5vs21UiGNaGjZhyXDmQPGFpjNo1e6j53NkApYEsvglO8U/nrblfP3dwq
OVzOSAKHeO3FhVGgFdWgPLe+35AEQEkQ3IFkUuhtLP4vzpo6Gr4p/69+qsesinvDB+aG2P9VtZMS
tu7ujtGrRTvgToaxTTS7dIUzAr7xRP3hrX+8Xwv+nkAVHlbACKp/wmbMlAgdgjB/wncg9Hgv1bCj
EAk1cbs4P6yBJUqmAVtYIYKyERKp9wZN1fIdqqe7NSVell8MEfoykTFP9pj/eisQqsqzZK2k7Pfy
kMSht7Q0Ntg2uymJ8gtCIqPRMKdWd3gc3R335YFaTT4Z7YBQ8kp2iuJ2cWHlOBoybLq8AdTTfFZf
2ds7KBDLyGpr65eSf3ZMSoOG5Z2UASTw8sbhdLge7E75WWvAXaNu4PlVoNnrJjSmptJDW5s5JqrE
Xqj5jMSAIYC6UAAGmyJ2SkzLEq5lU8Nndm+1i5hIcARYQZqUcipKOdwE3D8OB/cnrETkDhPqSNMq
D5aihe3gE+yxvO1FzXWZWWJLPEjLRKZe9JDH/HLUvDSvHs5wH4qSD/KaT4CPR5v/bnZ6WVMVF/9u
IFC9jPiuaUkTT8lMOXElAWViM9aUmvkjm++c8lw1XGsGs279RGvuvv36/SnTwEuNQyNtho8IlyUm
o6eFr/oSNJYSfDZ24NyCdJraPhFPmLJh2h4ah3NVAyic+tFZ6TRsWkuTLP/rGvS00i3q1XG9oe2F
cg1orDceRdBsdrgpayuHjwRMlVlZYdV7Nydx+NgEcdI5IFtKpv+badA7nVpP3KCzBAccmnVih+nO
kNVkFLnl3Zh1445tNnmCtzGgxG0Cmat1FS5IrMeig/a7rD9eKojgniWxc5KjVXLov9iBY9gnLp2W
svS+nUWEvqiqAE2/LcVAYhLepSDwRyNllsKv4Y6yE7nejXkOWzHi+Kz1t3iZ7WBgwBDxvZ7u7VQe
47JpPz67xsr9AuhYUpNuWEXtkUgxsFRE5x/kK5PwFZQDIrVVjUHGJo0pzlSHGticxRcdRwhaCz/o
wNxJ3OUt0NdkCfF8lXnrbyL3zaVZNPQj/KTOyzYbLWQyIZDnJSVFXgCfjpKHDvOmLVTPDBjD26im
tiyNJ448FROw9B9ZeOj1WZqQTxpQXKg2unlqZ2T/BldpO4i4t3Ar9Ihuzx17GHDn0DeNCKKrVcJF
pBk3dPkQo7vNa9sATA1ARaZhuoH9Cv4lxgvbXG6qJIYmEfXALz2Z6yxPhgSOi7OcRRSehvykWm3f
DLLz8SBKdpfBNnHuVfFyfY+dT7jHKvwgAJGApMJstTqMawNQScnQ+n4npXqGV8VdXvuKhOneED3o
tQPQG9dQ1dV6hV5iVJbwCLnvaAQxiAuZaDNWxGoquKdf4QwzPMxEOfDAy8qUSlA7hsju5iBw2MhK
Ahyc5unClcJVhgFixVPIXQftyjrAOeyKCj2a6VuejqFVMg8ukb0a4bEdEbW+ezhxaZT26MgC4jV8
xnUEv2QZazBDdb6Jw2Tyl11FkHCXIrqsIrGjuIF8bW1jkpV/lqq4r2OtfhlCB85uIB+imrLoQxtQ
jqdWsvqgDfzfJzy8auuay1wTWvvAr7btRBtPMsFB2T1zg/ViGO8Jd45sQ00/zFbQU09R+Zd7BPgb
yY2Osj1qH0kz4bAma10nVhYZYYwDvFhyUMItzEB14AGbOjPH+MNnGKiKjL2X4WPsRZXxFNmF2n0E
/oEK6UemZDPWdn4razUogxGwbwyUHwICVA4B0cwafGVzxU9/8g21zBvNdzpNYw4zZg00BTudZto0
SAZhDu+4sThDWAO67c/q3Dqim1sOg6GjHNb+xA0Fd5UCGpiIVdZUHJOFTPqd9xDA4ctbTXRApK4m
PVPUxqhj3m2HAS2+9nMwezJDUztaBAC31FXC1Nw1XHoUr7lajlgCHi0XXuJVhIqoiWU2cTzOoJOH
AijelZDBT7Gfr5dageWmZw6d9II5GOpjRMzKjK9MIyc4IK1yl1i6AE8yGPAb2xLWEUwiuihMf1Rx
/CiZ/oWLVhtI6qE/xweWPNfujO39tmN1WrYFPJF9vWCicj9vYbasSSML/oGLsyZVOZtkgqwKnE/1
OYhvABgMUlzUIDPT6pDWJ9a7iy04/QD/HLWZQImKseVvLHuPC0eIgt/k6lJLTszn4ib80STdRVmt
2+cKtyG074df4YC+29AoRj4WY9gFKgCtdIFA28jwZM2lPQop+7nMnt4SKh/g73uuLbDzuOZ1+mlg
zuYpJQeFmj3BRx1z930CoZ5yUC92Ran3nDFfN0gtJ55JxO+AVZM1HemnDd7xa+e8rhDG1RTCDd4t
3lWH0o4Dl8P2gkhy8o90sd7p2s2nPKhYiCClsGBrj6uLt37rSHVgCWpWwnjKvjFAHtWMab9VmYPd
XYlpNIxuiooQx1FQ/VLpp4zWZxbnAZ+XFgh+KRuo9ORXPO7aMY9/k+2MrucAEYW3h4yqA7mpv8jG
pyubz8AgSktrcpb/hMdTApwHOS3IQyxWQ/qtm+zJ6ANxz/t5Sit2NDnE7ItXv5HJJcu55L8vBxLn
0b6D64USML5yAr2mXSc59MCwo0gHJWhWEsyIFrlPM3jtHZirF6vTL36hEFXLhoROBL7M57P3JLmn
vnstGXAkcRO7raWBcJDi1loTZhNQ5zGM/278ZF5uQ5cBSrnJdiXP1oHgipOIRjbwwADc+9m3gGrM
YYc0dYCdKEacV1NWxgdF7xSkQglkZFzAgNJs4yDyyhrGJZI7xAAKNEVh1yWS71RCFSMM+fHI8kLH
J4uwaVrprofNVHi3O+mKkVMbVFwpLgoQJMOUUF97txEqsz/mFNsKWuoC3atpHLbJsiogPOLEf5oc
Cvigpe+odvSZXLNFqYdI2ooTif5qPKQmwt+m/EsO4PdHwOE5BZkCnqm3+JOhyIGZPgTSTpBS3XbI
8bEtw58zCwrDp6AO1QIF5DwUFIEeXZbHPLGQX3XzAmGuerscL3PW8AmOQSeC9z4U731tq4pETTSY
IBNydQpIUf1q4kh7hiQBZGlQw9y4GPAvF5gZ0x2ANvGeDfhpLRXjs1v7LS9msSO9+zBOrfRfrZE4
vZggWYEa1LRIsweVGpu1CBkuey+svTNS3erPU3o33ZjBO9Z8gTx2TnRrY0H8j32rstdQyUlqqQkn
pNFu9uGOf4ncrX0tovQw4+o4a+S2joVOLa/9HYyovx3hwNn/VeSa1z5jz1dUS/OfT+0jW9IzwdgL
yUcho/rftzTSheAngy5orqWmKS5GkrE/vu4JjVauCwOdUZTeYVP1xHWMb/5WQlRiCxdMaN33eN3L
3sDIyD9uNCEmr/I6nkD6LYWvIMJCiZ1e0HXD5Z25r7n89yJRIqaq/IgI8a1ZM5uRw5wTBraLXmmP
Xhc5Z7KwY7vDzm8D9DWWN02QK0lk2vjSU1zUbNAsTtygDXmc19X5sfOSiUP1P2eE47QDRynNEPMt
UmSYA6NpOEDT3IKLwPf5sBjMYdlv+Jp8PQVrBiwgDRsQFxhXvim/cDZCHHVKVbHQ6q9WV17uK4U0
k2x/Hj4sVpohtD1fcVyrOoSNCGfILWD0VpNV0ncKdp8Phh8JaZ/A787JD9e17MRtz8HPuO1PLDji
bXfhkYwn3KGmpLnhNoDf8rzHz8Jqt5ChGaigeC5cjo/3LrpldDcQjrV8C5ws4zRj9qIeklVwziBX
yRthz+Cq1Aklo7KWK3DkTgkW3y4KfEgtZLovdSMwM9S0B/03tpdOoofhUOu0SuvzacIxwgK/mzaR
50Qiq+qtYsLr7cXy6kSHghlQMkyIpdQ3dANbLCPlWUh+J6iwsvRcoZGb0bY49y9B3WSjdtgjT8D9
/SwQTXfAauqqy8L7JoXgpyah+CpgKZ1vyE2y1zL9orxFH49CAgvzMR/Ekil2YUTO3jlRRTr+GoFU
ea5YYfZhFyqLWSkwAmzdD/rQ4VzfX73490Fm6FaHp/XaKfiWHTnFLYPR237+eLrRbIA+mMDEwkhR
iUfpuB8ZPnM0jQeli8zmljlktBhhmruXCO8MXMCla6Wnlus6j+9PbBYZvL9eVMN595s8cLzzjPtJ
v2prBnUrj/CdDeiBEeuqJJ+v3MeYyYiyxU7DqYWCHN4wNXPPVgpvvmmePOj5jbqwRhAZmJ2HNRXT
FmnFhuwN4GHnk7B6fYP0vxeoXVgoghnJU9qFD2L15YGD2Ld3b01OhssH9Xc7WvDpHmWnhz+pPKIj
jCzNQFSwTow62V+8v6Jv8Rfxdlaewolwg6HY+2KqyFgp+Snm9Ke/cyZN7xZd0wAe1ZppstNv3CUK
+m0RYJnF4ouf1BLetq9m0PXlraveTBPpBV9dgKCv+r0MQmfSnUmPsPF9UnyVKn6mbN4/SHyqzaP6
lCGAkpP2v7h1uZAucam6bDh3BHgdFgCtCXfk6nem1UlvwIKrx6zo0i8EQhX4wtvvvfKWdigl118I
riS/q1ck4fI5Ophplr4WlSENMIZUJyIhCUlA7q1hpunRBLvzbdAllTPW4MgOqdVf8SI7kQ9KmE6S
2A1xH0LxA+hQz1JjJKLD/yErN6vv7VaFyQHVjhlf/YeRjFqkiMHTIqZmlTzEn38zoin3J0nlULIX
0XLCDwCk7jABa6BUmxw6PrSH4/ATozvVSMPiM+3DOdv/ZW1K17gnw1MI9jVNauq+Jmm0kwhoB9gF
E/yKurOFCCGVzCovUao7eyK0HXsdc6qr9TZ5+mK0e+XaHro7eetiKgZc0+JRUTn8+Z+zkEzdGBg4
gl8wDAaPFj8xC6uZXTaGc4iZvJoR3xXsAX9cfPXozky378pr368jB+BVwhiUJ0Msn+logAiGgVZm
mZd9iRG9ssa2U3MVP3VsbJTRZObMDX12c3brX62eDvBTzHB/3slKMPiusalWibxY+M/8Z+0INJlO
dI7ClU6mODAhAxOQdl2LwbHQ7ewimXjRLpf1jqS/pk56hskna/wqQR+jo+9dpkTjPyW27o1OfRu/
ZucJvMPfQbDQ+1eVsfmvzqjU8WDY+VsO9TVykhxkOB+XKmmbZ0ZIAptyYja41wA+Rfg7BPY9qATl
Sdew2PtSmyM7YVDmVsD+gT61emCMTt5BsWCQR5NIpEnHz71tNOB727k4e3DTHApfIhhSu5KIsqlE
bpdN8P8PL2TQMQzehpvZ3xQQK4aZk6GJU7ahpsnqXfvgE8jdneuaZixCeZTvdHFtDM/6DAJEnKNJ
SNiExAuEqe4ZT5UUoZAWg/UiYhSG0jmVF8LsBNOCJ5ls6rND5wK3ufu7Iw9D1iE12CtuW3dsT+3O
sI3Ddb0MF5E28pscEnr+7HjICIE75oP3VlTO3kkBIH8XfjmpEZ0gd8Q7H3qAyOU/jPVuVtuPX0cs
i0af1YvYhPtNU7ip1X5kGZ2Bsmbv7GOILRfd5vfxVyY0+7XfIKzMu7kjUSMY0PXy/p8aXBfxmHvw
1A3zj9EvNKge1XOJhvRdWmTsqAaLXP7aGdYxzCEchStV3Liq95L8rzPmFjl/EnN38s6ScBk9AKnJ
WgDszHzCMVDk8a6tJb3GakO6fLw3tFTrylrsMtV8xTKo4yC+yNdJ4dS/t/GN9HEfevyosfEmQiN3
f1yQtU5vb0vAiGodw0zrJcjp1Z3FTyoixzxpQ4WBIv5dc2zyaFpq1oq/etCyt6J06Hpp3jQJKcD7
tks5xGCxzo711++Gm3Jx64UldqUHymCI6yBo/h5lUgw9uFIyfteI3OxXidgidkxjEN+Yvt5a9Xye
0BEmJ81O2/2Nhq0iJrlC+TYBF7PbJBx/XuLHKHS3SpwxlpA9ta8L9SvNEfXxlruOr8OqlfikkUc/
rZALtNvBL2rZ2vmkZ/FHM35o+W1tqIi2P3ht+JtL1PXSR0EpaXlJ4fiJ5yjlQsUv40F9KrPEqUDT
Ga6PjfZ/3ntgh9hP2ThlIZkjQExd5zv5rtBOz6zAQuewqbNPJlF+Yn02E6B7dBIFy4JVAVo3SakS
id+2nfI2R00R5jO45lr3yZzhZOz3QOSHYv9L9mvWPmBQTJ946wbgOJcxUVTAIP1niqfjZfle7/Yu
Pjnr9z4E5LMcsii98G7RHATuya9g4TIHkUj3oFtX+wRJZVJLb62zWw4XaF+PWMnvQIK5ZJGm7/jJ
amoRD85wtNKrpRz3FPNYj+7Nt91d/xP8RQ/zWTdBXUv+CyIi/K7BZVhgrscN5ghTvKkK5+K1yHU3
x24aTu5AvYO22xVgarJPPC2FOIzyFbZ6qWskzH8zrp8PUbEyYv+2mbBh5f85Jf7r4EgYG9Cr1P5C
XaH/Sg8+WNJMI0pjLvmGiUwA/QJ1UdLGN0WHYkhuag6Sf4RiluBOGGOdCbFHhQf/0I3IYYaKNebV
wsBlie5CL3tvjrA1acnfTYJUyw41SUVCrJBFGHhTwLSaKAPCrnknxh/g5+O2thaC2IAgli5wPBDh
p2cnv8/FuoZyH78kGyyiQ9dsmzlBhvi3iRcWNMRpbuBGR1+VFom9sfhIURipbVoSgSAUNrzVE5t7
ECjS8YjMFJ6Dzh7zDURmVo78uyvC8g9xhmOP9fF0iwHLS6vxDjoCRNA3W87PKRDwAqMA9TnsvAyw
a4dQjb+pPW8uxjupf/QJHoHq9+vD1nUePVYoXCiMXZ9I6YPgLKMsbNA/DwK7FtuIU83gyBZgFljS
oEev51V+Q20+kG34+OPpgrVwhPuRL6eFNsinbKwoTSloR9KDvGc7tGabw8qDWq7YI4lFwRvYR/d9
H6ArjRfL5rbHgCU4l70UsMi92Yk1xmiiLDly1TmsswcLj+6r0sd2k3fFJqfmCYCqUbKGs21C3YNp
RDHabrtfgetap9lCowE1wrNdj1AdUNiFpmBoDH+mraVM1JQbwkUa969/0F7XbL+5Endc7F9Qc1XH
N6bWxomppbtRotW1ElzufzcDfMD19gzl0OvXkakO6PTnukkcxtlU/qGKhgUItW0tHEWs/HEezazw
2lyTlAqpieuRRc9eOOmV5Z53lsUQlEBGQpJqQfgA/2/lHU9a47wSo92/IIrZLOjepjPws2gMs2BA
Hj70zkTQ+7E2Dhw6MJ5MiCVVTnASril/CIMxyqrGVh48gRT3nVTPRCrgX/nBqgU1QFazsZvzGabr
EvB4VasezCV0hd74oqU13U/l7Hnn+13zx2BOofK/r6F7lQoSpdkof/GGrnczpLsEXfJcZQQhlIFS
v8diXjnbUGdtngSzrU43W98jHjCIgO8qcB4K4c4wdLFtvToZcgRJ06PNxUfevVBRI7tV4Vnx1L1J
BmejeXHJTH4RcVMPXkQl9uPBmNYId5vbmOgV/GLumL2GwETch70TEWnRa7MRgy3e5G7OtqAvpxHI
SMI3ltGmVaHgXbT5tw0oMRTe9GcHFeIg3CzbeCk1G2mtOnRWtgCxu+QP2NFC/2u7CtG+f0ti+syu
b4pkmeeoG8PoHdDCRh3WTbAe06pR+GV876PuKEsS40tXVZ2aADNabZbNB4+8iBl41cr/ZjltPJgW
N5rhJdF/eN4djaYyCDbaN3QPe3X+vJjfEbOq5DYXVG7wQdeDxYkU2uFs+71w8TNtL7H1kOMH7kuV
7TUhzrGDgd2qqMBuzI/rRl9NIAHz2HcxO8Hy+eNgTjvwMXKUz2zc2vwT0mygreP9i0iWuKdZPM4J
vgoJ1tm/if6Ew/wAkCOU+SiJ8EbqgopuYwDJY45r9PwOnL9LhoKlxaVhLrl6jU93v9FPSE6xVe6I
dLJU3JPQ0mm7dVvu0NHXjN8ZL+2JoWHDoMKIpVrzyHJEL+TUrRvV/L8PrcsKs4AJu1WUcJIpEVt6
qD44cxXF3g30E4LqvdmsV+DMLM5eX/ZWgJ0TMNBced13bIWRHm8l847LgCYsa96dhl1AxWJmnGaD
pbZYmJFmyK/ewxA4UKhFEvU1KckLZSgwQmO8upecmquPRmD31pOZ0R1dznUo7gUYwTxypxTzRSJO
LCsjLfql1oSp1nj1rohWmu93ggDzyWxjdEsDR5sTxio1a0FzzIWAmSC3olxNitIb/lTi5A0KmTV2
WJjMRBN/gYLTCXKl9tzlrzh4WkxV7I2GDX1h0YgW99QHKn5kRWGJC7LxFj0q27oq0jtGWQ5kGkTW
kdMEGxQR4YnbjoNO2NBUP1d4J1PUw51X860ZTyxnjUexrLFjc9t8VEcu2k/EJf1V5sgvC8xVp+UC
3x1//7rHIgTj0zd0u+goYNf53SmHTuPcOKWDySmyhB0l0N668BtndDj1DJJOC/SQ13AUET4tmdOT
fxZiYsm21Zw37xGrOLzbW/ShKTyQMijLaBTP8/WS2m4eZ1XPX1Vy0HJKyQvoiNnnVh38sPOlmcU2
atRUDqiwE9KmzKI/qa2uPxtw+TtI3bWiR3ZYqrknNzFttUX1cwymy3eC7d+txDO7G1AO3cy+unJ9
LPkSLMkN9LlgarAXbyRKhEiFOC8eNwphcFJxSJgmDOXkmBl5OZF2KmDavFG/+GhVHvw9aaOHmrr7
wCsU4bjC3C02fqkcFMQFwIfq5VT7g2j5/+XW/BB8CM3AIm0/0FZn8+1KSAg8Y2KHhPOpgO9UQKLj
tj+bqbidMlByUS1M6dJwCLu9t9BKGnl0h27q1KadFRnbU5nXRviXFOH4trR/HC4XkTkMI9MGlu2Q
esjFGlCDiU68NDK7m39mPTKQZYUC1T/jr3EwAhN1bJVhkrfmThfgyjKx4ahmc4408dZJlyvwgkSc
KcjdTOPU6pLcypjiqlsnDEeywIQrPU6DXPeU1fKRsmQeeXpD1FUl/PuoZ1DPy08mP+mfv3tD9ou9
NHtW6Vy1hIPSVuI7wpePQ1+6OLoss+LLpZFZk3xl0cSBJnlPUisWfIScw6fTw6NxCwer6zvUCB8A
BClYmXyiWinxl4gcGBZPrcItIxGV+QWszeqHqPTdrHBIcovu48I2d7WOm2B06RmjDo2lnYEXw+Ix
JPT5yGZ1qBCcfUN5EbsdeYDjXl3h758pW3Azry3lc5TTCdzyfrTZgH3hrz12J4RH9khxXb7aLZ8y
MlLcUKNCcq1t6xzxY0DPYgIfkjLS/nOjcMBBRReU9LBAOV0ZeuCQWtojupJvnWfy0yGcDOL4y8id
mXO+8Erjia2WtwiDSE/g1Q13zwqC1XbvwC5htMmyvylVSia7BGHFudq3JTVA3FdiyN3ceSmQpufX
LXoFU/tsS3aKSF19pqejcoJJdo4IDx77v/89WVVsl1d74oTGx3nqwUTx0a5fGunjKbRRSTIivDbk
quZFEjL1agzBRWTSb+m+BnFquqNs9Ja795KcCyGjiA6EbQKZFcvKDANMIlYaBea/Yvu3z8+ThXRN
DzPDIpIzSsW0BI6mNpRf63XzHMJbgTrWOgXg6WiNQwL8H/wvj3wqgvlHfzo0ZLJEIuEzummer0zR
1X78EVsMjejn1km0EfVHTiuErohletY7KJVt5PVk+opiwrAq/RwzaqNrBdftrrulb7Hq5M6tGUsB
9FilromsKs+ESJ+qbPsQdgjNj27L1ZbODtHoud8/TyTBVf8euW5CbHArrQASvWqO8k4uXMT4Gixb
1bA5omAWZaFFSZojzwbvH3HmZ9WYxcowdOo3qftIkMDmpcnFN7xcvPEFnn9YSpReyQGy9wOGpkYc
gaCMVJ35XhQEjvINdjqTayeaILacRwSuuV6b9YGVQnQJKP+Ho8ZRL7S4x4zyAbRqwfjwMEy4UMt7
UNFZwkfz0zAEfnrDa6yEDYIrU8LKMoKOZNXIjBfdQyzH5Ua+7E09fdQxLWBZtre7MGqC3hqVAePE
QdGk3MSWUwSfPLu94IvFhQzsaypCRfyvITiXjmt+7amuPaKCJ+Qp4ZHSN5E9jWC9gbYXCZHZlCqC
yqm94KOLP35XAGLvQzfegz/pAbHOC5s4nmQnES92U8xo7VUBf++N9mYr8UVsF6uLWK0K7ruM/cis
Jxfvv0CXhnRhQ5FqAfkvpm0cEJ0n8tdqvtBqJrWb1yB49rNT1tDDVNX/BmlczXBdZsf/MKK9vZ8Z
iN1RRDre6C3GMJLNfJ46+BzU1nlZkBY1BJllo72u0j4JIAPrFwrUHqdSmr3eWOF05FQizTQC5ZNH
exZPvhiugP2X/Wjo+CNYjltpaOKVHhsG7n+CBKI4iYNlUXZPXO6GKHmO365afdPtRFQfCkZTjz2D
o4E8ELShW92G1QyjG/HHIu7nJPKza9PXC7k4tvBywi19o9Zv3bwO7N5YalRnxukMRFW6oMs35HEU
H4R2e9Gn/PKr742YtGEcFWr3Ob/GJFbdmCNU8LqvQ19p2oco+R3c2vIJjlJbBoQtqVrjiLuuLK4J
5X2SMVOzhKiBKqFI2pM98YjGk/HVV5D3Emgz4va5GGdDXqXTneaWlBvlfRKjxnin5awT1r1en4IT
IQ8kFDRmqlXM1z64Dmw2iC+jkNAWK3plijLBwuhg7+c79q3uSQ8djAs0rnBa15HsLLihk9zjpPJL
sXsP0KiF18VKMBsu+inYj68wwLQMuEQu+c2yPM8g1zBika4djwlfCdJ1VXOoVGkIBd6cZMRrYiga
PJ3JLSrQ7b0ecEGj07y/TJLLJMbiTvNvY8tGtjd502ALI1btaz/P78AR/a+9H2yIE8UwbrAUan+d
TyYAv51JOgPZwWOLEIDly5AKPui2N1ThoRigqsJfFn7VmEN0w/cRVOZc0y5+jMKNFN8NBeERdXgd
MDaEEGwrUkPgqwxT+GQRjArQlX+AbJr+X19wjG4xv3IZnMgXUtqz6RQfueqCdlBL5q17lLgE+Lju
hbXPkm9l9wnZuwg3Mp0rwgScRqKGSQVkyC8Adert8RnkNZREJY+Mgfh05Mh57RWVYrovvagl8WG9
fke4s2o3LBf0IjN48wneJ3VKigZinU/4g80brlCxFjWlb/qSLBOYN/nVDK8W+saZLk/Nn51XLhSw
MgD6KD2cuni4MFgNQGwPZmG/rQ5K4BXVsUGJ+FZSTnZaIZSy0uIEdpA4GfCXCc5nKeoyvPBteq1a
H6IQQhkCiBNkzOJTPixMMI/eVHnYrqBybMfY/Nl34+6uCY8UcaMZfv+9LiwQDCm78e3nc5kjNDda
UnxF8j1lPPuXJ4ExcxLqKOjFliJIWCwS9uz6CFd2KpJPjudjCIAaPfJY96B18XTtODjPvDemxxRO
EsJmjIbbqI77OoWqeYTnzTFzcvM2y54a4PJ1Gpsz0/p1ZLcNKh4gF064W+q+FnN9p60r4uuBQnQC
bzTvOtn531+MkpzIp8iMz01k7wWCTXDEI1eXPuGgTwvcTmdfARbra7n8q2+SDvQmFNbL87Z0KPYe
zqWjlcOAocB3oSAbiDndKmoVSM69MlwC0jg7qSTlwafyPHIJa5PtAM9/gSE0Y8USjO/OU0HJ5Usz
nHMhDHhWPSsoa92NQAvS5AZnR0xcyppOxYBIMsrHf4+QRILus0WBqvq86xxbTSe+jjyXdBj7zC/6
Aa8CxYrZCFjh7EY/O1oEI7kq7ZHMWObUgIHrG8DXO1WkTkhGQepuZ54yk/YlckW9smhzecwaez+l
3HRYnwz51PM3SUV+P3zg4wjIO/okyuZADRggXDP88KTXQNWTSUkwUBaEoGFwA281g/XPgVMEsNuT
+bkGuc4EaUbw906GgnO2h3hewluFsIpbjtgv9NnwxbMuO/SbrBZCm1+z5uLLqQdEtUIss7oJIox9
8Sch1vfy6NRUQRLhrAKBvyWvOMjjdEYfHqTOWxxdx1PJKYDD6gNcpNPNVv8zyUGgVu+smA53Pw1w
NAL+BO4x2TutXjwcsDw1UvKVhR62zdL6vXBpVeNQKMrnCRvIgNXVtffc9pLZQOtE0TYob1jiKt2c
Jplr7/gM8kVWUVKtjyE1SxobzQ+LynsnLz9TlukH4cTWiqfF06I+sTppJqJcQYLHZhPfyCdvHg2o
fPfR3gFctmCzPo2Wze4OT5arb2sC8lTNntKHQ4f53lUBQGtpUFpFI4O5DlcUEHzkjgPVmFsmbVvF
K6tfzHQ8piBIJ1AeC5hsbhjJfKQeqaBnez/KGbi74E7aXEOoS1DqhzwWkOJtwbENTzYZI5nmSlET
WOhEr+LWKkUHlhq2o/hVgAq1Js4rXo4A/o0A8kPFVHm9p26oucfooA/7L2CbMKG2GUl6UUL/QqJZ
MeRjTVmlgwgRebrrgJyE0VtLyYACJsHa+noGq89WIBQpO6eHxQGh03mEo9Q3xnZX9Frvh0hBqPhi
QcS7Q722MjF4L4VJWtpEcFlz88bofnrX8p8zOyn2+gdUhBKreOy3cOhqrAqI9yXDgl4uPQTlMgg+
nivtaLyqVn3OSHY6/lwgTaGQ6QOmBf474h8FHieVDwYKWeML2neydINKuMhOsZROGPgk502kIbd/
9lv7/AzfGWCv5PIiD59fvjgzHwDutX6f7bOCpl9hjfhcUHh1hr3aHiXW6+9PLL2VIvj6WKR0jnc0
OlKLDn/qJd2KmyEZ3VYyFZuSmt46bv9Jc4way0Rym3qTCVaYAjExhz+266YTu4fF34Q55HMqiq/W
UVXcUwm4dXjKwXx8PMQEEeW/B5LKGPn6rGBFnp+PMm/tBe6pwLLP6C5dwZXGxNUWZ3G6bJj2yZRL
WBXM62WtUjhsL8tt1wTpBBkteGmuiaMepwujHn7tPNXdsTLHrfMlX9viunMDA1O3uod7o4C6GEon
qax6IPTgOSVkrQRp/eHv/1X3T4PSh6Wq97bPiXG4WF+ccKfRJrBR22QMU7XOINmu6PcRxFUJVo1i
K1jl41iOArYJ7SAq1Ha3gesWwiRTaKax+kx2UbBQLFJGA1FCfu1HS2QrNrSpXbckj57+IP5hEwgv
OqDaWACs6sqgUC/0As/ymA7RIVppTC23A/jJGbUac3VZoJO03S/UGUrB6sgWS7DT9xKYH+FxEaw/
AMQGCZQOffuZoHNzOlr7VVcqLsb9T/epPP05DKCz/SuD1MEFybJEthqkggtRLEZvJofbbZl9qlmo
JZdbCV48JM9LoWoq6pWiKWTJGwPaU3vkJ2EHy9guc+IId9UcwVTc5/yPKp3ZOV9MQZJ71/NAVT67
VZg8jWrUja0oX6bJQMXblbNamM9qCewRzILvhXY4r5iOFVQOQiCcIO6dLdcPqFn2euj9A0XD1dXV
eH2kjxdrhQT7VkQZ3b5D5VeutfBVFdLKpQtqpUab51TpKIiCCCkNAHu2fpg4iYaZI3ZEKAkNGASO
6wTS3E5LE2lWHH/7Xpxc6QW5Bf1WE93w7qLHuFpbZ3e3taERwYmn9W2UzDqZb+UjiK0CUCoM+A9U
tRTzeXxlgQHbzrQ7jLyno2Nyzmc+kz7ETAi9tR+8o1KCPwAqIxBGqJAxBgbD/iyxAECvWXg+Z5pO
5y22spLJIUw2nJaaCjI9/dwZ36xbyNZApLpgRqq4duTABab7j86EIPW+G+0DRo9l0cmzk2+iWZZd
NduBaojdAmwaf5hTBzxoiDvNFiqQwSBou+Nda/7S919d4pyPtxTJSzmrsSWxu8GnNLNaCuTURbYA
tH+Lm/q8+Ck2v3Zo4VEoIgM7vHS31lPmYG7ohZZjfECOoQQpfjVOA8p5K7WcyoRsHT+7bdZccl3s
U3nGZhukMazp9mOxIWSCtHabVolQlH3Gk3avwVLa/E8nLml2HTiwouwUieF+7vNx8V0bpzzPdw99
vlxqr4HgCgW4PMuWyZ+FDpKgr7WubwwPIf8qJiyoZPXaI2qQE5l6rePallcpYMhyFb/kbbwYc34f
C8PHQ46LuaBxv2d/U9S4/FV+Wgg7k2mwZAZFQrq4oRykBpn830xSRLuPdKOFFKNRKMmY2ulq+cgG
ollXh+MQyJHigf1Kf++B+DaHuIx93xXwEMyYGPyOLcjDNuSh750pWFoOLWbeU2/6nstLmhWqiyIi
tj70d/275sotikGzDO3Q1VNR5S2Px3u9EZagJb8NX3DY/yVFBQciCJQPazZ61ed/S492zi9zk1A0
1b0Ztuqf+Cu3zs9h5xI8rfLvoLjYYjMtr0ceufi4UcDA62zOm/2g9SYLmPFdBHw1u0wGYlAceZW3
8mlWRBLhFmHuYndbHGlP15HFjd2fXXQbmj5LeG9q4PySzIPZHo08avp5hx6rURcqzgoNTywJadXq
s59A3tzoTqKKSEPUFrvBrVUn93ha3Y4OckMs+Cw90Vq8mNWXE10KqqseBvPut9IRF4LSfRa8gl2c
btiMPezCDfsbFwh8q07xYlOS9gDr2zeyFTy2AI7BkKbaUWD+3brNUSAF8cOCdtDiS1a7uFc8vddq
S2TIOPJqdlEH2saGtml3X/nJchABVO4uf8ULlsNcJTsXV/pzhqha519pXpwOb2cyQSdvA3ylmnM1
RmsQUIQET1Rk6Df76VBzygGeEpy4jbMK40utCd25elHoshzDMQoD9k1cEsSt/QrYxYrH2fKfAZJF
bLeZlDhifXwtFhn4kve58AKjOZ9MJ6+oCq+pXdezuRDuueppcXERLjxm5gqvUfQECpiGumXZQ55e
oz4tYbrQigl3rQpnYn18MMmC9RJ5TzgLwOA1tsjvnDM4qod5yNYv97wziSD9hs4reNUBL2vy3gyR
opO1bsRt7lVaB9+8e4b0ErQxC7t2epVVwbrprHjJuqUXExNGLYzBzhmR1tB7UOK0bOV2EDjr2AK6
MIrLGoY+0mK0pYgVQjzzCEyLGIv47y6OU3PM/hxCsEXgMYK+wYof/49trqitKqaYTXU7eqA9XSPL
/mLdu7JbSy2ST1sA/CFtJIf8jdwE1WpqwvEKZxODTgIMtRibU9kXioCLOVA6IDMbJergkDujyMY1
cSKKCAOvWE2Cj8wbhFuFPk6ucK8AxBKc3LUow3tSEkCbFR6ZCcmhn/xO2Fg1FJQNE7GhwImoQaSN
uV/Zdu5vu7dhz9Ti4mzTu5ogReFq0fOShe1Qxu4GCp3TUdonl97KK5dJ++gs3ecqPKzpNolSvm81
08X8j28+TG6eRD9mcLbBsEnrXxjonFwKBd1yDt5STqFd8CkrJ2mHDNxKZzEoymCtOZYYYUcgLT42
0rke9K01hhKj7LyYh6RbcRSy4oeVgo8XaV9kR/hJuGy9OpuR7YaqpcK+NTbnNL358aCCHYPOBwCA
1q1qRLiCE+sxDvZjSC865v6/KhiMGDunKguVJ8e0tKB+noF78y1fFWyI/1tzQ5VOCoLXpJAV0g54
o1hKmVZEbyg+Wwh+aggcCdrzVWS+NOWmSxv8II7uadB61s8PhqYryL2mRUJqUw/xWO8RgRVuf5Mj
9CFHK7SUwONFevGWfE15nkZZB+qR0qd4z7nLuDlLeEGYn+YUoaCFFSJeW26W5riCGbw6HQtdjmM3
Cv7km/7kXyjqdJgw3Czgj0f53BbKmC3Ryd9yemJqbJ1wp3+dIPU/nFxuJkms55c+8X28b5F+JkwV
TcQLWrbxfx3PullQn0EwBX1LX/WKltLv4kiBs8bTUo+TR2W2BBOn5Zoxs6aEIBqA9+0gIxNJwxVN
t0B28+USthQe5luubND17I56dL7AYMMIWwPa6bz1XfBDoA0KKbHoOHV/TyHv7WIaJJTklgFDZJvC
tmLSPQ/NoGg+ONEJ65Ho9Ck9h3VsYsYA6TzFlRx1l9yF+M8QmW8AVYJWXKonnrbhA0U0OB9xoEvW
hfHiHEb6jIBJRoUHJ9VQT5nXRN3v9aTH/U3et+ITz3TnB70cvLdOh4H4EoWuNX6rxq9I2JxS2IdV
vuDodmmOTImnSiiZNrnJIMluR5bvboA/cR9lqrD266+59oX3NZWtdZPylA0GPus7S9dYnULyGvkk
gCkMrFEyyw+aYZ+MFv+QgshUEed6FADAJ0PRIQQ25uVdhCuc5a7pK+hxIGxbF1w3/xwRGhSS+gjv
2vIlNHCzCi0SxskdRS2pZtEi1yq+JA0aX4RagTzDNcHPIeC2l+UjtGhTGY25SxZgDW7ziu7w4ez8
ZL9/E3yy2Uw6slzFgO9eR1zvplzImE4r4vbVOlIQwfnJ1qCNmy9hb8UkCk5u8pN9m/enUUOl+tWZ
KfGZE6DcCJbuButyA224hdZgbgK3Z/J5+G84+jRpTyqrs+04ZldxbBTL4wr6Rn9EvNlGuiCOJ46f
tgpQ/4IK8cggqr+Lkd/cxFFo8YdmX/xvLX1ZCZ96OH8ZEUgXDTJVsVdhqya8qvAufMZHAZPsWJ4o
ZGRG+rYwbSpfxRVokQvkAwszIpwOhvQlWhwCMWlOGasXpfAHMY6/RmrVSkBtYwcV76FkN4n7mEiF
ylH88aVodRiErmasbSfoOoPtHFWrqCK2Tjde5iDsm94Iok+/K3kcRlnjidRNzPR5E28NG9NSjzl4
fKeVuyJREGgA/6AWOstvCUCGHcovpMCV1BH1QhkEHLouIf6kU0eNWWeqXOK59oEpAI3b83/Yd1Hv
B8yeTGWN3lwQ/GrGr1T4fhSEV1KROyO7jmgFOpfx/aE/CGByLGw45slfN8S957B7wU7fKXpF7czo
iYskQeW7nUgc+4su13IVZwsTm7ISjDTYzhy9Y3A2rJ+Gc5B1TpRLT+Ibp1v2UU8Iw9ygkPDiiIBL
trrfQjRct6ReRmqeBzst8KohAVYxK6dNe19+CupNMIHVpBaDkufX6JnljOSfPOhM+kh7XmwCtq5C
ilMSRiWwsSDK0PTYNORJ7pKpjI4KED2flPvQ4HgSI1Ax0P30BNyGZLzzPR3v3v6Juv5G4s47dxVX
OaZHJPdyM93UfXAy8LmFqvEGVjFZSxB96807laWYe7hvSXeKOplXlOgYCl1HtlcM9YVDWDBEhImT
LCu43LYHnHLTwN0500DUuRjyGkg9WlLhjd8ddqSiJP/+6smlYLnP+SoCpR+LS5z2R7DfRtqZflBV
CVbNTTmCCUMAt6ypr6ibqOZOrVsl8yXOmISfe9agBjVtvhUbvzEzK2AhGQJN6wVjUoIRWPF4mqk5
maAHTmf/5L1ghA1dkJU56fDYhmagkPuE/ORAnblFMWCPlNvjok/oX5Cm6+ZVXhC7+r9mUCNU5RM0
r10pPPvJLFY8JN8eAKTi7pwTSAqG7K53+dn5wjmwzJdxL3DMh6iJ9ngT+tuIu44X07Qnq2DYCTYo
4JwdR22jLaW9YGIZiA5UbdJfTdxxVYDK+1KB32XMXucUIB2Bylqo7xiZsG42qUsu+4toy3uCiYBr
/nyiZmtdeQOastpcxmh7iS+j4OWw3OWQqy27HMXKIZ4fBbyagBrPXa+80Z5Y8z53wtQqHX1ppi1w
CaYt9OaNU55FvFLEpkycC64pkiBIslhojdFQitCbI3l2LT5Gl3mvJgbX1IRQy6FZNaFJNMUaEXXf
VsdPjPNmqMo05B0HuKIoK5Zw2mKJiSCQJeHiYIJsTuSPbQCirj/sRGmrEpZo0ETRse+7QFzBnxHA
3lVlbg5Vv30v+yzPib3hQFaDkSUElDYagoC64rlrgi7/Fk73Ia27CVzmkOg3QtGh08mmv81p32vh
9ultKCNZpqowrAj500O2p2TW/svCKND9/rnJrF/1l0upX+i15Po0UxDXEsJspFWHRr4w9RnMxtGM
tZhnJ2/XUWZp/FNpLVb9S0pJU4oL/ZpuXK/uz/MabqvQ3X2eYVZLjshz5OPh8/iqlq0JLGQpeXWD
O7ZxKbMOSfjEjmQzgiYjW18pQ6tor6KaAVO8ICTBHp6iNuen1HG98J3MWW1nAYE3bqYuyGRLy801
9BjpJ/4dOsKQZB5ODnGN+sOWNr4sIhnVILI/K94hXdklhIA4sR7U2DFQNDOrQfUTwZkvZlldjD7Y
ZaODbnGROHDClJ5j9QEtgHnXVkBRwO+neZa8DXOPokihyTI3wBpF28lmRJqelwSFVsfp+mZDXqEu
w0OgAo4gSUy1MJmmXXyRcIbA8eBnWGJgACvC2/hBbkHEU7yqkVyNE5Y07+3jD47+FffC9GNDxreO
NbXDdKE8kQBfHeItK6MhSZJWkfoV4HBG3B3FvGx+kzVc6mWaaO6U98C7kEXMTQSjvQ1Z5PBLKZ90
PZJ6Mi37WSuhTY8NCyHyUq0hT1uSrgGtfjyjJkKMcCNaodhSIA61zfBS7wrF5Ehmy0tRZRuWqL12
dy6InO4tUoCS8CFBlR/RBdAg1WuiNIoTVbemEEH8eOkWJuqkP8i5UD6vL5xPVGvXcF+qJy74Jd8D
8YfqFzWlSA1UfPBQi5K82CcpAPI4oBO6kvZrwWMte4fXdVPxXheUZHasibgB3AZgJwBSMya6K9cr
VYf4oht8gC09EziSR+/cUGNdrhIF8VmUzpV3uPbiKIp2s9W30gPoSaspduPWFyPhCCccMyy6yt4U
Gb/BTvMuH9WRSnZWwleJXqYPI1dQb53kcX2ljVixjWQv3y4p/dl3JM6lzAhflMARIB3yKDnlV1FR
ARl0UpPzToLpCr6f0dq4tm9M0ASJN70J9CXYVcOPM92rIKa6w/qrrxZSzaoEilPND7hgQ7YPbJGD
MAlri5wqHCr7mu2U4FrOwqMhT0Ty807xABBEEJqs2OieoCLdf1VjhPd2KeCBhRFTV6OmSWF1ZRYr
SD6PCodKb6e715YvA2qCgZnnOvfUtvwDHHLaxsiCFb3g9nOk84RawDpwvCBM8JfVNTob0XkPFoCp
JYJ1hQ/sUrIAwiLQZAX36mqJ8VvD6CoDR2itoF191+iUwSt02dGNTWwPZtrkQSwaIVfy6mblz2Lq
tncITKDSLSOObyLYZkUKfFtO4Y+XEAHfp3tkp2QxzXtK8I6usFymFugjLBGlVfIkVs/OD1HrgwFB
9pGNCEtRUrUF89eoL0vHi84K448Y3b+TAC/cN5xIonB+DSaWvLhb7CwXEiorN5T/nRfYCvME+I/w
4TkwbSuLGWbiQ3kdT8gsz+ATZCmeueUATkpPeq/kM7lz+3/RbVl6opxEQwB7nzvGVdtyShLAFpeE
//CedFsLvCCOgcO/ixKHNOvw7NMf06qmtE4lOdKmWrNn+Lao4kg/iDlVBvKzc9F90qq7L4G+ZTC7
Kx7mzZCtDsdBK9EwSbKDKxpF+7WdaoHUUot44FzVLhgvg92Jao289bS+7SkuBVCVReCsrmingL4Z
oZKnHl7aJiUGT1qAOV+xFtgPO924YXunJ/l0BpzbRyWCqeqTVBRMGb3NYPXVeYzZLkPeYs36/VBZ
e7xEKrrb98kglgFVTLhAZqxfhmJ/4BtTKiuSG6qu0ROjp8wmyKjIdsTDW5iNjeD+XIK6Sse1wgot
eW+nomzugLxroea2ppMxeZTMfawJa1PdIN3kS9uf/5WKSM0nfw9Ji/0Jrss/d3vQQdVK1MLOO6Fu
DlGL8FkBFXqhBvFVAhhB7fMkSCaBFvxQ/M4QMY9Va7wTqIqDcEcG1kOzcNYJTIs7FZntk3Bn/H9N
Xk71NXGoJufGJcwQ0ySbBQzYGpaAhE9nE2PPIAH3c8YsmNySiShCPxBH8dWPXXbFVrrCLRwDzhH6
ec+Yp3GZGSZO7FqsC2l3QKOoqZecyMn4eEnuuJTuy6o7nd+Hn8/WCqt+iG1MJXTjQgEMsMQsbegU
c6tWZTbc/W88urK0bgCqIhJmf5UBoMCI8J39w8fDdK9MDWVGpUojp4/ZXknfRAtNF/XdsfbJtPW3
2W76KRtoiKASZRWZY3XUS2QXu3mlIQsDbMb1lZTg1F2P4emep95mD56Je4lqiEiASKlBhFULz4lc
nVPvRV/EwR16Is8TQAeTtVjIVxKWIVdPON99GydA2rWfsU8/CpsUpTsgmoqqjCmPfoTFcIRqdqNY
+CdAPA4khzCpzhuKE7keVyoxjKpe0PwhIHfwPTQjQTUZLTkHwkvNuCCfGGR4yvXQf7V3D/VDbSVp
D3jqRaFm/jc0O2kAdGucRtSD3UeAG79XPJUU5zwTsaxUCVxppYtP+seM/V11AkRzor/wbgZvr4Sj
EVrZIDmL1QhJKU/7lKqASRoRvPlcYQLf0TviCaWTsvHY6i6Envv31CAm1mDe0BzikatdWVlrp08U
6kr53cZjOPFLxAKa457PbY+Rt4Ls6kpWh/DPgQB+brvvuvgdL5EjDcbN2gGjbClsADUp1hwscsIN
EdLGIXNIGVpN6aLWGAbZtV95ukgabstg2ZdnkruXHjLKsDkPQm2b9Qzk/vovj2KLhiYA4bWQvKAk
05qGdNs+/HmxRVWKaDNRYUwiOjbJdEp4qqbWJn+Cz5pENHqLsZHEG0XPAhBBt195rCDCeZZDeIlV
V9KWm9tIrDGfCgGY0iFj7Gm8qN/rAXlmgTG2lwTqSLVw9AQ8seqj7j0dFqNo0ri3s55p33yKi5JZ
RQFzwLNiE/KatQFMaRWOi+Fa4vn+Ht7iqNkUeRnRl86roPWXJY0TFx4UtVW603jw3LkHJzW5Ia1z
Y/ULY70q2QauDbRonj2sIgMKsTGSf9maS1HRF4T2D83EwqD5gK8n+t/p7OvKwtUqcaKbbLtVCcEV
kElz272ydzkYWTaUWmkVlHv70x+jzTgyRJRWTQgM/mThxy4JoTmDyW2YhmFC+BgEkpnZrpGvt2Xt
hlcvWkMGgufagygPVgThaErpOWb7bAVqOUg0ws/YYJ3TifFpDOnuGrG67PXNn7IUHuJFDt2C0qXY
N1hw//5DPSWTYpJsegch764FS2JAOaevOPnXpb6pGEkIfvDG9V+X55726fNH92uhiedFUKqIvQFs
wGFeh1xGUT6oCo5EgKlxHcwQ+Jo/C9FlWtCG2c68WNW06x4Up9Q5+oBmSQD+xMui2t2/YMRRUjOe
8ql501sFLWTGp0lcVMZJw4IChZ4sKV0fIquRcOGeRgqhPF+J03RjFuwI0VLW+9gQ5u5wZTi3HAqB
BqJ9ZKgS85mMXlx1e49ARqaoT1rVEHLPmuERuHt05pxY6MxzgObmJg940++A9APVcoHj6Dez388Q
PE9fvnBCP8GYaSA0wrkX0MZSJlfUh6edFX97PDttS8wuceOOhGClHMkgQZaspmqBlb7penSWmbKR
ZnlbpsFV90HVWT0eBLiFLpsZwQTakfyJrVK2EZAH5/8bbs69z1k2OyihoAAwTBH9mLEDy5AgbALt
XxkqRSyHDBJ0dg+cvBCm6F6XysVXdcnbzvuwXgzAvalrBTnnAyFsA4ctXZFdRwSEKBuc1FvItvxh
e6ktVzjUIkDMMPGdhZjVDjBcE42+yUBSyW7X1+I4UVM+INpwgUInPXoC+2O5vmxmr7jflgs70MEO
uj6Fy926Y2RvOyVe/B4daguYnjc2BlEyF4zH9EeJW/jdZyH9FGk9c7AQgUm3zZSe4GXnJiZ9gTzr
gpOrNoHoTNE14RtOQdf+h/DS2mxQeKhRJiQKttvxdz/mgCALQ9m0/1RDZUUBzSowdVxSXAaQ0qMC
2CCyingbTsIni1es0jpyc87H7QxJRZt0kHdwpLiN7FBAAhtkLlyKLrm7yp0N3l4v4hna9EnQTAt3
VxaVGm9cop3Wc0cqzVu/+EPQkBmJR8iX/8SP0h0iN5ENxmWudCtF6o7/czoAmI3GuUdPpBivFBQ1
WZlLwR6EMsmeXPAJoMzRC1giboejIgwMYl9ItB0es9qV1pz8+63qumWKykRz052je2BuNxHYQa7n
FqSqBipmV/TbFGK85XUQoTVHw17O0fu1EduG1Biq+x2Ojgb/UCtQyG6R60GhwLwcdlefllIo/0HN
FXPUM3vwLmH4Y6uvyCNe/dYDEpKX5uMcF6uKf+Q2Cd9UZ9iEZamuLVSF7vKgaMmfSCJbZurZwwNI
ILwbphoR+RjzvL7KQTK8wMdg3vInO/PTBMTeiTHtfRLdQhbemcfPcNnjDLsToeAtOXmqDJJPlOx9
Ny3eMbAGfsLh10OhZpEycvQVWbe4lBl4KMSybL9a8HoVbgnCJgDm4b9wInNCcjMvKuN6IBTiA2fz
QaWlTu1OhMX/uBRc+VBfTjJKZ+UOlms7I7QZSWTlFeYxigm1URwJIks+0lBKkKkgamkh3HhcDp90
pDEAQkCSpoBQSkprckMcsLfAapPXKFJUBlEh+73egWbvqLg70y+/xWDWxT2AvwK85jLqEEFqOWQp
ysFfJPZzkemG3T+CZ3lCIWc5MgN6J1wgA0KQHJzfuN8aJ6vny4E/pyBGkvlDxBZrydLSwZTwf4s2
qfKhA6/9GczW0uLNvl0Kd6yvupJVJsteJqrgDPOb757uKncE34sLmY3BqpFREsUajukM5fdpwlA/
RbUQ0u85X/1ZcIJcdIhxsY8ZEAd8VgU2SKAFfwzR4KoaO3/qjoAAABMdkOG9aqHuEDOAcoLQpwQP
NbgEdNZKRLhmbQwLCnO2/yhXDRj1BCL9Uczk6H+BOFw6gZvwFQ1pLMXhkIi7WXII0UV3aUSxKhC6
y8G2y+CQ4hQpPllhTkIoVicoRxm8q38oinf61nBn8ar1DxURwEAF8TmIjakggxAUxcNIA4wvkCJ4
J2XD0RSoWIKEibDRR5tc/a3p1A88/iHwEc1OEAMcerktdyh+ZwS8rkcpb7fJi2bWIxii9zAnmEVy
eZHF+PEclo9Tt4oIDjUT+foGU+Sfwgddz5PM+sgJ8tmcT5UJc+YWhqFSPi5BV015k1yfGhZZ+BYC
geBXQ+LU1BPZjWtl6dz4VT0hWPCUeqGDFDngowS1axNRF224IwOcmKjRijy53znVOHLN80A4IYRO
QPSvAzjoBXoUHQYCvujhHa20o41qzHJw09CU7oQiTQjsA66yMEVQJpB2rObf0pVZslRgs53f6rOJ
4nI6VynRZArlPbqiIV4x85qG7vcSGA8xbWeBzp7CEk+YCTHUpt6cBkjuMDJZq2VvI4+mRfWUbBKg
jkP6OGyOECrFMsW8h/Rl1nqyQwt8RqypF7uNCBngvFkl1BapjYRzHmi5woAvEukNAR140mDMEsUN
HVmpm4Gr56ngxQBMVQG1mnXTmPvM/s6juivFtw7TW2mRKPgG3LTEJQACTs7nMGnbBSykCX8/ZZ5s
29N0ufAvIauqPKNJGe/DYAoEV0ciiZLdEgk3/7rA0jNsXGiL2kqtpqYN9FIxbI8noY4rX8SLG+bm
fcYINqzIGgh9VE6Evocaow/ixkyo+mA3iVpReXxCFTO3yxmngIrymZSQxv1We4cHTGPYTjHeMown
oa/1bo3eR9jo07wyM+pdsq9jQTaF8bXZfJu+olwtKG1BQ7Itp8rJRfiOQbwjQ0bKUEdr8NhTvhpa
vF7tako5vSD18o/kZaf5JwMp+vZPQLNXR8WYsa3bE+gmFAm7hu+HG7Aqvm9MfAiO8G3LOaMZaPxS
2gzYGN5t0eNI8fAzambXGTTo1u1IckrhWn8aJwbzjtgD8qcnoVlrSoapeJqEJppXB+X11iDjfyly
GZQoAnu9JHgyxF3DDnzAEq5VvrOzMaBMuhsVkbx2rgTQ84+FPylroJgfHYUUl+Dt4iq83tm4b/Cm
Ct3S25NZ2tiQv/QbyrYHJXgVjT3cCLc2l4Y3k6DrUIVJ7vxVkF7k1uR25p1g1Y9/+nVmdaM9hDes
KCqSbruNTI6RHDs8Scc4XH6waFDxKYUz4FT+tqSJbhjfiemUo695qiUr50y2TBPa+rJi4nyTy5Jf
6s2ldn5PC4RUh0K1J6DtRT/1hqn4c8DTIv94FWdiDf2JgJS2Hjxvn8b6ZpGK+gq1ca+ln8xpm3S+
54gEu8MyWJ6CZI2zWCpJS5nwBvzSZNAJSpnC26ojQcYjIfev+0Qt00Ic7hH/iVYby6tEJ03b/Vw3
eFYRd9Xffyz91XKu9eY4MmCHxMfhLfLpygC2KwtbWpW7TlCrDcvAME0a54QXj63+Nby6AKGLp8yK
h6o6Cd71mJZZfpOggdNYygDZvkN8za2FrlaZnbyEG8YTv7RW+jalBG97e0GzECOFBo1wNYApZyaJ
iNGjf0EZfT+rglsmS3CE6bKA0r+NMcFZn3eV8gg0hIMUznKMt1jlsGp/KtGcSoKpSLdl4J2dHG6L
hMruAPP7PFUX4jPjaop6jUs3LSaRBUH+aMutIsQaAg0oVwX/0o2gLs6o9dS41/t+Y9REP+E3M7Rl
JXUkcQcaQNl6T/cfmoPJV+zVdkUt/0b6+vVmDDm+kK7REBJZ0BqU5rZEzL0imOFETEiJIIfydrLu
qRiJpAP3e9mEQ0q3ZGVYeATaTupmKVzeMDEUYwSc7hJwd70E4PIWzfzQO2ubDtxxCcAGkiy6RI2I
g/cLxBJ0zGYGOECKueyE3+pMQqFvq7yJ2GMJFFB532BJjDsj/tDzMZ3yGZdEMtt5ezSj7859m518
ZehrTdvWpeSF8+C9ner01kjAdczLGK7cM9YmYb0gEGAdkN3LJR72OsUiF30R7FvGWwIhZRQr5wht
lswVJVL5LR/meXv82mTK3KGrSoEp0Kj1268AYTYmp0mfNduFBPti5fqkS8gIdCjKV8BS/dOwNQ6V
MviCCMhfk0T5QLilSA858E/S52ldou3BmKSVD19EYqYJXVvOf5cnckqQJuLCbV1owuxN8Jexnsgb
/u4++Zr1MCELIX+L7ANgpYEl4tqD1tdNoe1w2TBABuQ0YZBV04dtyrZYR7QZe3OO1CZntD8VCUdo
m7fd/aiCtYs9T1sc2l7L10wkPhi5TYDoHU6sXPbZ6s8qt+1KhgdtXe+BwJbi9cH0TODGAkNTs0LW
1eQtQGyTrXjuviEKbO4pSoiT+2WO+EGDGLu0Jg0Ypt7vUJiUXrmY7FhQDvwY2onWEIfAYtDLW2gc
h/NP4JvdghANKumqTkDZBoYGyyNfQLDal/9nDSmwmoz+YpebMfYUIDpqUyDFg5/B4tB35UNsURmj
RT3hSXZk8xqThJcmyQT1HS3G9q9LM7SJRnVNjwGrY4Nr1NNBwmh9TIyZpBGv8Jc32NWrWpL9ev7q
8qhWlSPSjvgF/T3P0gUj9I/rEdTW0N4RiH7iaAY0J+XjDqcCiLAevFcymnLNp4k3gURMNP/myYSh
OqjxHjebveeXt8NR3JJymEISO2ZE4q/orsOUbb6aS2GCeXY+ycZKUskovfY8XeixqYQgrkPHYgE4
Z5kIuOHKSXnchqax3J4gL7qfAlVk5s4TmuiGb9DH/A9xqf7EkbMGZ0m4BRWlkR2FISUdiHltvSz6
jY+/K5eLU5AFWgSjxiLNMODvlL3y9F5yPUebTnNDVHl8HGtyoSWhOFvH7Zg+6epTKQsak8xmU7N1
j7bN1DS50AzGkH4b0kAZDpPmtfbnt/Y0YB4gUST4SoEQEWxRP+I4lC4+U68aL4TLavjuLYs04A9N
luA+aK3wnhHILxieyo0VtlXjfO57FGAvnGFS+q/J6r2vJldipCZw1doSGAQN06ei7c7RNpT6cP4j
hFTlV4lyGZc9RAbj1S1w3bJ7YhWUclnRR2QJ81dEPog3TJLMRYjlp9pc7zKd7QAKM5ci3Ya3lurY
+tE//xAeyBakITlG0eHbxlCLFRQ4VCr+qTGzflPis/vkri2v2AtMr7J0G5DAVjYd0cLoW0shfpoV
EXlHfZmLSnb3DPfXujxGWizMsYTLfMYjEn0pfRDz+HHkZ90YyY/xlv7Mz4GMCMxY2RDokTVX15Q5
u7cvLqS8EmmJ8inmY6dCVa6sSgzKffcSXaB6J3YQE/qViTaPowApVXkUo6M5mj1z5/XO8e7ZcpcM
AAHrAVqQsyrul28nx1xQjNZ1Xo3WHCCxOwwXd9MAf8SLCytP2lt/FgyJ/G4HnMmsUB0wWctxNvsD
naZHG/ivlz8Nl1PiqdRRW5HQII0YY4B5EDtaQxJyWRTkLHo4lB02h6kEpPK0lDMgalJG6ND2YaZ0
6/dnFaQLDHjguQUE+mgB/eyfqSdNXA4yfeGjdt+sF08GR3NBL3JbeiSMMdX9itEkjGFCt0bIS+lp
r9u4mFe8IrD6gVbtpBKZ9h6VqI1URguhYY663nstaszH7uoeLJHZRt/Bl/GwpGi3VnBwn5X2XgEL
M9SejdJKdNuIABGC+usMfz38gBIQRfZdNBxwejwCOYUREGRxNm9RuM6yCJDmfQPY6fAlmqyPZBAh
UtXcPXAbd7xmKGlQH2mLQtcaM66RtnNV4/iXWTwiZuJdoWEmUviAzhUvJfGBV1zFuwUI9eUF9H+8
dGKXzQMSuWnmhzsaF1yOsIXf/1uzPl68r/ubK5C4WEaoF39b6vGvUW5zF16RzkzQ+Y0BTvjNOa6K
2L6Ms2NQepzAYSL5sk7kArlZlsyK8k1PIUvP4nqUFZMllbQWMV3/tek8jDwOVYLzQRHuFv0zrGE3
8GyG5xfwk23/gwhorhoQxefKflbzzrmtKNq07RzhuIoRWQkiKs5dfOpg9RdGu+tbb+Mo64IhLv3a
JQ43JuZ/NZezwiBTWgbE1z3m9P/TF/YYZH8gJvHjbwh2NpYFtI2mmAyLzpb3iE8U2PaLf/nhS2nL
1EfJQ9Cu/QJmKOiy7BmBDvpUJ3Zo0+pRKk3Cfbe8BG5xfP64wa6sBwH5+C6kALHug0U46fWSLWyM
VN2ToW2RN17Z+cUjeqOva36zYIfmA1+oHHGa7K1FxZYBnnIllUysrzSCovBYcEc6GS+r8mR/mjRO
KQsy4B8oyO9kuCBVgmi9aXxu+8vsdg9pVFo5g/vhCDbzITknR88Sk3TWwGD6EbgsZgCQr9gOf22f
kFk7cNTmrF/OmjDT3hszMu3VL54w/gsBPrIvIRrOSin+B+CjGN/hZ649kQijhtYftDOxEMjzXwe+
OtByVb9y4g9Fpt5pKQHZTzLh+Avcq+wrLeCsHmnfCw0YUj0hR+c6icyfGadfNEPyHov9T8k1bA8b
MMYfzplPYFw9hqoQVWXPXxRaxyO49mxveiaqrvpE9A8aOFDR5736DELWduTHWEDx7ieT7weKMJ5L
GD0hmCVMbFyLGCts7XOtIwlAiviY0L7DK3kdiUnIVL30tLp0IdCoJABLveOty2yOi+OYVUPF95cL
yO2yXawITculfKnB0owRfnLHhNAG3xgRvtX1YILVuWAh+vlAaBCFQgWjnRW346kU590HPyFSxyTh
N7hQfZprLybTclLcFGJBsORbmeuQ3KJojnZ79tESHeaIChGnwsGUujclRZiELUGamoy7WDOy3Nt6
dTqOD/uoeWZKmhTGdjMix+sOWeCBbVOV3MLZCnI64a2YSNxtJFckMUtR8GZFBfOzggJJ+c5Mc6xC
07xIYY1r1UrbeYQkIHnpUUBx826vUNNIafmBCcumWaibLzApg0DfTpMauvfR2pkrg0zMyGadDlca
U00h2WRc2yjmDfuaXY+YX0CtYgoeKmmELPnqLo+hoAvyUV8prA8GcFD+MWytYr94l2QbV5Z07zSj
Oo9zsgdW0KhV9AaBYFMidZUPySXY9y1UD9EY70ZQYBZtXSIuNcuiNWbcGDBiTKYpG/4F5p1M176w
yc7XAbffa9fk0E9Z8T/KPQgpNgBskTkpUMIU/NXEUp037NP8/fml3AMazvTB+e6VR2d0E9w7vcmp
x75t52tcyMVriDcSvjIbGOiAk1A/oVeZhwsP7XETSJMZ4pemzMrCxot8Smmu7wF8Oe6R1QRuen0E
zlBuUKaTmbHST5BVurMqSWgAuV5cMnFvMxN1FpPpVVZz9B+GNlWPUa7rD14YKCqY6EhIYb/90pat
JfZrPImMKX+GSCc7MFU+i1zKgyczl7/i+6L0hukWLvsozknmWl/lEfb6SrCUEmFZpK37YySuT9XF
7TkO47lDn/M6Dlr2TxzcBfPpCNiTAOA3kdYRuiSk9ttgUMxWQaukgssJnuiyfkn/bUzdBgJJOS2d
fi17wg0UKMzk+o4eLGFoP/vYXc0PcuHZzDvs3tNo32cZgBqGy3tQJzbY837f1/d8ZwFmiLsnpfqU
84RVKRetPAL+IlOH/Z3C8xCtooZ1o6EfmLO7t6ICtklvEhIqEmAaX6pjptTV+cy6NTtw95eKiiC3
/43EQhXHtqsJ8+Nlc+bDHrQAN8hY1tudo49JxCa8iWtVWhw9OaWEHeZXcrXTxmJVdOy7SGlmEL54
X5L2HwIeDbuE8jC2dki09ftEK6oO6hPZIOFlGL6/+vGwPqGgx19IKaNWSD+kSnICoWD5aCRnp7C4
TvYS5cxrLiBzIrtR2VqnKBM9TQs32dCkr0T5GbIH7qaTbgsVbNhW4+zu7Tzi/HvTFykL9g8jJ/uA
tfXeOrZ4J/+VtoBo6frPrG2BwTOCX8MKRiomPNIrgPViwHxjKDbkG3Lkn8qESf7L1rPoCG8eOnkL
h4CHdGP6IYAyPZS/xG0k8Vs+PYOjVJ4YouygVfYhHbLCJM6H/m5b7MkGWe+e8SPE/ledajuFY7g2
G8rHjss1+Y6beqjW0fE38yhKZtDKb0Daa/eqxDGhYF0eXwRjk90pN7aiOf/b4FCQivJadi7HvfS+
KfQDZECq0yMq9koHM/pN3mlZPo/MV9gdFsg3wmFcb2Jss9LcUhLsOnQkbLu+5/ozTS1FfeW1MN5p
wItb4knPPW9V7KBL8N+0ufh+kGfjN5FWVAu0WtH5FvSMKH7+UTs8HqtUzM5yC13kWbbKJiNBT5cS
4FzoMtq8CO/ihJrkuQLGihXTQjdniakAhAACyMn0qor6IbzeGxe+kp6tirKTs/YoCg6bgrZjK7s9
hUC8uelgNCMJsHCP2fRyryZZx6i5T4ZcfGhuCUCRV1BXjhPt1rlglergciRlSRxN26aWmXGBz8oJ
iyyucAcscSV+HUCz8hVqwbP6uE0zQQaOJabP9REa2Jaz7uyZI6f+EF+inqZG6ZKkmEHSC6k22vMv
V6PL8MnsQ9xLHFjPAvHei5x6r02ZW2avhX63sFBOnuETbhN9GNGuNSYRRi1z+twZxeI716Di0py3
XFwTALGMsURxy2AbWX2iD19ZLMvqmtDS0hc/7zF40VmSgwmnw3jH4qf61skH8b1Ll6YAqB1QMBSc
LAyryvwDGD/GYTydKR0cacJTjoU187GsOWkHjw9aVVCappAxEbQsyPfQ1t5EGgRnm8GBtKR8hr7r
Uk8QHtqrLReotjg3vJDJsUsUsU0IZWdKbO7szbNWWPuQfKiumTZtmty5z/6gF9plPLMw4wpbcS2g
3rmbK0vUW3G1MYKqVvPMFaE+eHXoD64Sdyyfy8Dg30yGwjwfSlwY6BxGUdxbo4xCgBnkJGQaK/Dm
bLI6fH/l3Ste3Z4dGfZqunHAOlw2VVPR0F+8hcPB08Y2nedJthyAuh9FI8Nst8m0f+X26WXFf8E2
6IdqAT6xTdrZceivxhl3twOjP0pEJXwl6XmijcDguIs3iXWO3h9y9/+WebQt+WEAbYsBW5CQpRp8
XfGLEh1zFfJrqkreVdP0gQlmLZ07zwot4JQyVAYRkE0BHYPOAcaAwmLobPFKlFZ9AwyMzKqKu13o
k/x6aATDQfxl5M72Ayux55JN5djiNy+Wi6Nw+MIKgbFTQ62EnvogiF0k4RV4F9fqOJ/OFlhn+R51
GjPgNv60RqN2nNEU3waYkD2U5hIgl9AQnxEFBJP7G/R6gTBf8jdMpV2CIiZTYubVsi/nXuCE1i8m
FLQHt/krRxUtToe6AFPXdfXGFD0Nl/nbSPeODXON5cE8hfnkvXVvys/eBbcKaJJZkd93H1FXDqEG
Hi7KGZPoFlrwCFzey8MFlO0PErFv1wRCS4I+m9Pu8bnqcy7Nj5wGugkKDju4BUv/AKVkI3F6poqV
FVLhtFkpmaC71FamP0z/4Gqzt/ADr/0/bSotCFH+9AXYHjAQFKUB2sJaQooiK8Y2bORFX9SwTp3o
DPLUAKgs+wId/gkFSRaQ36OC9cOieQ0WgQ8rOG2m+9yGJKkn8gFFEcCVB4zeoF2ql5og01NVHvtu
sx7ktibXAH5ByLfldYJUY/SWmru1PWXyWE/1BeM9giO+F+7MGoLnQnfeQRSRcQzgWUozMc3fWUNQ
z9KZA+39oLClAp/rkULjWqQ7pnbyAaXmNnun2zFxUsMqeNojErtGLc8rZi2zt9qflvUqEYf4D7iM
aC7XoOY0u360OcM2jV7K07kKkFrIrvZKw5FhxNv7ioI1Ck7ICY0J4rs8lKbKZKABJH85KjoNc6sa
KkxyWQyXPL+29KbCZh3Vw7cRQQoK3gpwkjlbp6YF71lcCFm+Qrt5+R9E4CIIVZ7ISxiypsJe/Y3u
mAgnMbHezd3xbeL4qigMuptvm2mPbTs0Jb2Fd2GdWnH7sdEwghGLtBOZ9YAEU9lzBE6VoZhT7GDR
Kk6kxihaTl6NuRFfhYTO2uVwIJs/nlVQfLs5wrLNjeIufSBqjvmAmjC2zGQzj4HTMxALr9ygWNa/
+HHPv8l9PeYNKTXf3mRuiZIG0hlyhKM8mvrg83zD+C5pYyLANo2CvSiDpk4RVYGDMHiMNTaG86qn
XrpkQjEhzvPS09CZ0x4mTeg8wYZXzJbhHOPPcAv9k887K97msb06JG1M7c5/Mc+Tyk4nN2tcFDRa
MSjB6JhW/p/KyIA4dRcGjEoeewfpYvnooudbN4xQ7tGPwcr25F5ifQhwL6i53aXRQaPbl/9f4Tn8
4ejJ79xcc8aLlusKwUg4Y6E+MLZgYmiZCglShI8lDewz8xQNx08eiiWpxYZlo+DuOclNvNoW2n4H
uMvm2Y9dbaQhodw1W/CCbnM0CEDw6lVSxOpRPJyTTmSXAM+/vWo3Kb3GRmAg/7J/BZrzxS2RNWC2
yNfLvB/BCuD622q1fzqWx8UBzHzJUgfO3hpDKfc4sst9rBgqpJ8V37vhuFR0IvfzrLhDdaQEgaOa
BipcNYQ+Nm17i+v06HPILrHPuXy7WS8AcDzF7qvPNuqC7O+BjkSNdc4p9932NBNgwNFF3j6we1Xp
7V/iq2WOCNB7/YdQdYfl8m2O0/9T6SeXqHBT/DaEX20JhHE6e/WSQtiy8zqf5oB8mGJ+zFQe6kBf
m8BIFxEQDarztqe9hg/8J3HjCf9tasna/0aNjNedlCuGQQJJOxZCnXkW4Q6Jtg6uzriqUX6qXYT/
aNOhN31Mi5z1ugx7wO2S5OAFB3rbpHW1Bjuy4/YAwLWIY1wHWeL9Nr35GaSuC6YZ3iGSTpH9sUrK
yDr/kKka311e1a6dniyp62M4uOsCuK58FEHkbFS8gn9TNCAs5k1XkXEg8QsGp9lRf+MMdvpobpCs
gmnolQUCNJaH15PTQfXtKKCNJQCMLGCzj5fLs3KR7OfD5Wgiba0/q0OIShi/55ig2wiYrO5Jo+8O
CiTlmWklWAakL43A/HxP/l6JkLKOjnwPoXF5RfkUNIlk57awY900EbtxGjAuyZ9L0yoxzvc8Gp3C
NcoL0aPh9aXK5TuR+N88MqvD70XGO729zda/bbYg+YAEt3dCzuMtjSJXjlSTMcnRhLqAqU4h9O7I
Fx5snSvUVQx/jtAuUDoVpBN5ZW/4gawVt8uRESj8brjuhWlySxvAdC/Y+2nkmeVvgbZD982oKUls
dDUVXllbyWEQv8c6xWZ+RWKtJpoBx8Bpj67G3SLyWP7I/epm05C+6guvCyORMZsXN12rJZtg3ljJ
jyVQNfyfYXFP+GKtQ8ku7C0cWfZ9g6C0LoRAxII4v1rtkCHaSccBo4enN5zqEzsFGYnn1GT8K4pK
MFwy/URlhnu8yoNmu2LSIvv0Qs1DDKl0TnsMVg6J+ZsbiQwAehxg3McB1Blxt/ouNFGJh61iJN9n
ixd4g/YDGmhBzZigxW23h/NAORi2UDViUaSiajxrQ9tIUGHMJql3fqwRu6cpfjT5iGHBLs41eyOi
0YBQNNUhhdfcihIvO8Pxv0Oh3UxAbDCGRjUnhiV+QH+rgCltdb1c5o0iFW72tWVA+BgahI6tSiK/
2pQ1JMLk6ScivKGjRjzEACMEpUzFJiHrur//dpNqq+iXqYVyz62ha3wSnkKKJ/jIz48Q/W36FGwY
iLh90QR/jy9VHFc1IBAptmztpqu7dLXZv8B1rrVSyPfN0cyueLPxAGyG6g+PnsY2IiyNylSWZSkB
XbB7NgpvjO/3FvcFHT9e4SjxgVWbOIQ4wtXETLPKft0C42htMHjYKvBG9fqasFDUuaGo4mFKFoWL
Ydradp/t+fjqOFY5g4t7aJxWfE5oLcCi+xvRzHibjfqXj8wYtPqYdYARQKTNao4uKfYAN0JBBTG4
uUE4TlvLpFaUDMJpWynYqI/a3XO9rG4Zbtkt79rs08G93EVKYp3OWoVuQ/qgaXCtsFhjY6NSlEk5
k3EyL8YOFwUCxbuoK+Iw6QVn0hXAZU7b55yX9WpWf1ROyFql7hxx9ih66whX812UFKhVPZPsj6X9
lbtxdDDe9tsYdKiMt6eLH7t/i5kAEXBcNs+On48GmS83e52vEV7MDzunz4m0N0KoH/nJaihXb81e
PcDVHQe48vOTPjXheO3I9LsklglKs60FnXafUjd67kJCGRsr3PFIqS2RmYi+VWQ1+aIbecDL5oBL
MjIHrTjBj2OAWeByjYH6ZdTm0ebZn4bV76AlE/F0paFgM2Be3tkHTZ2Z5dHgU5wp0fQA9UihoW7t
5/fScxQ4c0pCzaE+6GDjOalN14+GWiTs7ACoT3Y4ppiOW/v9bkflbmtUubIxN5LsAMAXYjGTluqy
sVcncP+dCFRjPljTlvpp6CFvdIMSNrOoFyZdnxzVwGoAnPTB9mdXnf233KxhRrBB4Z54/OcR9dkK
kOhsxh+BW/omqAggBaATcInW73OOQ9YAwkhFC0VGiMKcsppY1nD3jeLAjhSj8Rb5wBeJDYawFTHM
pvFNeuphRRTfENR8Hyv+1eXvFzdVujKDTsk3L1d3/S8uCs13LcjGoQJs5iAbhG/CxVTeQbSy1Wf0
TVppVNdrIDrVcZHRa07ygQMJRpHrZlSqN6NtWCfuGjX+IQAwU+ru+3B0M1SxK71MKG7cklNACgRl
1ZigBnHBlW3dwZPIyxPlUe75gmB2rqfdSPAv7OogIWCI6COgSgm6g4beI/5b8YEKYKQi1s1Vt5h3
GvYEs0N6PHKKF82KQCs3bqaabmT9rqfHLeK7t48cPCXwgUNtVYrczUrplzZc/X/OKKdxowUsXVcb
GZHv9H0uew4Lk0VZnNFyVwuY3JNA/fePd+ZjODRQCdh5VB2ifOd875xZ0xzm2Ohn5LcPUF8YF5Zm
bVsD8dGN9UEKlpo6jaPxW8v/LN8M97J8vu6ic+ufW3Vd6GvGqYkkd25oUjziiiZHsXoUK0wPIUxa
9Z7mXbOZIILC0rZb9aYjF68LYXwNqkKUtL8+UIFfTpaA+V0PKlPr5yJr7mHSLA55mtQcWgGFHy5o
QZ3lSUmxgsM0B/wWKeMq4oclp8rKkD3iznV3dHk7zcHHYsgmL75y9dtP+uquB4FdBC3omXiVLoxm
qcZ+NO9tk3ax/s0EDs6dznHHaERp/ZDN1AQhH/nhXmigX4w+LXLz8pkQT82dl6vuQWuTW7TYNmvc
X1HmlUiIW8iRB5ZOMgbl3JujnfXaBGayj52DNvJRp1uVbpSw/vJtEqBSxLzhYd8H8zajrr0oSqTi
87pdeewXtb0/P1XIpRI6NLvnFQRJga5GOgB+1oc4MdcabUd1NmOZep+g01lgkHrMoW8ADOueSurX
7oiKhy7DMyXQGscGuzZNtyx8FMD7li1+5nRkOqZtGw4L9A1QA/fXE5dME0/llSP+SqG789PDG41G
dj1IhdmJqS1LNT4GBqHb2SHCSwyjIYeEGIF5oUlPgZbpjHYR140/Ju+6osZijYvdeoQuHxFqDC37
ohX4BG6AV8PysdiKor+TVJ3mqKbkO99vD+XBG1tjdjkgOzkWevpJqO9C+i2kn2+JbNzEE/ndp4kF
54nA4bM/xeom5fqiTzq9s9Nmes7t3kC3FZfGhSFinPXM7VAPqvmqIlYD/qpebMlLy/1HHbc95dNG
zTMWke9oghStcKzGlXlfCSL1Tr56PIRZH5t8OPxkm0ZDoF5aZqCBYBSbCuN0vkZVD0jgJmyd8WGK
KLZ60V2M0nVvyNBchQKhZ70LiDUwA0vk5ZVnvo1pA+7mzE/PFI8acYtziwtl67753WnO0FmQvYR/
+a0kAZP6g3pzkJTiGKd6zKlrmPV4mlCHBbvHfrxrtlmRc7Lclk736+rHvW5UisCFmlX+XHBFb1sc
oqu+p5XzcTCMjxwtCyCpb+Iumr3CDGbtR7BH4Ve0PPKlvqVooBbBYLJiLALLd2wyiCN6lC6WWbeH
cTNdqDcxGgO1qAzoFMkMMsmmGSe2VACkH5z8K+sy9IbFjxZDyWK9RIaxV7AV/gUg+1gdzaaUPm89
+rtungaGil70wn4suzmB+eNjurPtF00PXVgGq2zgHbptTcoxATu0vz4D/F7czWY34m+uMx2XkEht
Daa6it1JiJGa4dzALq+n8FXByxXEtjg/yfsSieb2MmU53th5Vm0hZmXFe2+Ej5Ip/78KWQl2Dgja
/Y5I3pPHCJjPuwqvTL4aKruOnkJIdY4JClVzfLoxAxl0K7IPAPLylVjolDtXgW/PGOtIBY3wLoFF
SPl35GbZEF72zbUkYbGiM6jbpnMfpvMIi3twwkZwYvwXszdVMRiJ7hd0HRkqh231kfSJPCjHOZ+M
4a50A9kveuEBlRMBZpUDKTvZKFRtYXjcUWEy63GDKVf6TNv/dzU6B0XCP5pOnHxnsPsxkLjbPgst
cCxpy64DkIEwRNiX8w1eIcisnBMWHorGS4Eau2MzSZb9cWY5w0QMg/2JMyTyf2fcAAm6S8CdHrBr
mxkmQ/ATdhCr3YrJ/ckzVvmD/pr9yOCdVNoyaKarBimddbfDLK4OF8fJkNXFv8TGcGYTvukVTjW3
j6/wxHOo11NMjC2EwLvK+Bv3eLqsD/DjM4Jt6tzGDZE5Y8XZa19dmKzOrtOmgn9/37LJv0qymU5k
e36V0B+kuHI5S+mbnk6ijn8dLRCuRlpmStCwz4NtVNNCRPQO5Mk37gShBOGesLTjhXkxcco9W5DC
lM5rftI/qKVziiPzsX/HXhrjgztTO7xRp6mBl1ZS2zkpjJlNzKyhTORC1RK99gnm9OQYxF73MQZa
pzuJbmhLI+sg86Ksuu2nmNL1NcNl77byydj1zh/4acvRnmqGfHWGoEkoc+/CkrRCwv7TO3qQ+86/
O6hYTXofOBZ1QHwyuA2f3X7Kap2Z0z2yq3qJRrwW+HHrN3rit173n7Hnlu0IAqE3Djn6PFOh9Ekk
UtFJFcM48XbSG0B/hgDqfQCddrCDHxW1f+bnOgDQyOsbwu0x9tLfnbR3m36QmTuK045d/D1dO9+5
ejoWRBy0YnWihsnI7bWHNqxV0cP/uwxdwGZ7yZV7mCBSAKikImig/+sMkse1Hf8NaIHTo+HerJ6B
yzT9wBH8AALwXXPxp2/w0mRMCsDqjlJ2Jwdu7VM5xwLNDDJJ/3R5ceUG7uxHG8s7jssVST5Dvuwm
NIH9fdL024B7DVLJF8cawV3mxRocrO4z6hohF4xXwpjp9S8CoZg7knZxtsUXk8Eu4EkmJigVRgxS
RzjDblj3qRrVqdhjPrXf90g3h5GT5/7ZHIcjemcHbOWPiwkTMFGWI/DqQILnIj2aWGZ/04MGGhCr
mcBWwUPeeWWvIz5L7Je8l/JAT6oym36iIYPRdaFkCRPAs8RWMtXyUrxk+wK19EucRZnddzX6Vwk9
wO7WmW3uBDZmz0lym4UPY93O40UFHNO9YHvED3XuTBqknIRqmMqYwHo1zNjzPXwhGHRFrIiKDFGn
FaoIHGyi42mRDztVwFK2Rz3cbdiVuSfeu4VBqG7dLq3f5U9uq2rsaZtCcYtWwkgYVrH3/Fb65JWV
oudTq89VTDDULw78vMMBJtj1hLMyk4PnG83wMRhfsBk05zew5olj8tZKGdnyM4k1qJnEbrD8ix7R
njXMqs5YnbtohYgqI1D7/S+hKg59iP9UC+TnppEQDApl1odFUzMitCQdZ1fbH5FBhPyeE622GYaA
SbwV4tc6tauloZkkjetlqtG2vmGsLU1pyBuQFWWZtcwFo2HqPLvaHgH3XFSoe84LR6xeg00kJrGp
8iUjd9bCSg8Sq9fwAEhgAyewxtBR0EFZhbCF/u1ChLOxIfGMZjrE6SiIDEZ1yhl9oG4/pBC1N5P3
/tB8rmPKIMIHu+UH+1kn7ERWnyTMn9EcKB8RBYvLEqyyOCsi84BSix+9H9E+EuEm1id6woBx6Plh
Io1NYLoIK4rrkpVZFwPXUe5l/cnUbcOkU79Cj+73ALrTkfrQOeVUUHBpk70yc1tPB2D+v6aKEcaH
xP8Jst+dzax72SsGyT52UHyCw2iatDd3sjUX0o/ocGH/E1aHhx6q0Wmq/qQaPM2weg9JrBzpxnj8
YI4AF8mDYNRsVqBsLAMxpGNWzyRh3nxAUeiv7TTVfYxdmBjgbL/+9yf+FcoGHQYTlwTkMFNoGvvQ
5GdXNYLi/5ZfHHfO89eTbcOb6hc6PkRnYIol3vGFL46uDl2XXC80rC8p0xVDlbPUmKgCC8knuAn/
Plt2HR8FBjs+Iof1YH5uCRH6/mjK6lqhlY73O4PhncCLDcDW0PqLO6ob9V0uTx9qdYHF+OBzyXj6
lsNmS2dhlrBhKxr4fVGu/pZau2xmDplqflofkqsTZNjwsKiUsynGmESAB+VYoe5uHkvueH4gRaFL
GZYiOrD6J+okeKd3IejMqWsCPDX6H0tXP2isaaT3S26o+xyk9RH66IaDVrDqHYTHxBxDFqOej4wV
z2FBDkMdQEs1pFAKzOZInjlhVxWSt6Hy/IAXTmfzieqrYcsd7XyWIYGbptvjNMDSEJCjBdXhwbuZ
NjeVMN1EHlPrY3+lZhSVU6uAkiT9KfB74MCeVuCicFrekmyWArAix5zqioatGMQb1Y35eZK+Wafc
CVl6KQH+7mjoKI3yEFOGS8/T838yCIMjDHHBkpMZfM3CEcNdQiDSy9SMiI4jdP1oZuehqQHyj9Rn
orzH7sIp/bbMBzTSwyZmTXGaSgePlfs1XPyl+F1UyUyqbSCJ3SNKoyvyca1ilwYwiohoLTBeqrfd
xUTi6veqF3Fg+L76KpBxmPn5KL286yw2KQMXg7CHM20POwQg99+oV/FBt4fcSKI+4AzR2bXFfk4s
WfWamZw0e42oB6ZNBKY2Qio91boomJ6CvM7YXrsLEU18E5wst/WSFRADAFPeZUZa8znNfLZA0UDe
FF8nB/jBXRrUVNn6hrGxyz6ULax8V925gwNQd+iPpSS4nVXDlnY3re/soZ7m+HZSnJ74IcP/3oZw
T28FTbB9WCHJbrn28b0H9qDBBKF8gKoXj49WuDKombya2A7mp/ek4T2Umoz5Gr2DBwAS6D8E6qtF
6KqG9qr5kp/HG+5Yj+AYWojbWPn9aLiZyZpPGUn19ecT9gIN+vGtVekBvp61tj14j95hM1zLUoMl
4flNQywA6s9qAeRXi1m1YncEjMm5pOi0HwqhR0KkQOm4qtpLE8Fl/pb6yqqvG0R7IfEDZ4bOI3JA
/h4cpEMXkBxfVzXPHGwcRiAWsxSJyHkGNya/iY83cgeYCxzGwl6xaesZ4KgVnKwxyN+I+Gzle/T1
3ZP7x5mg0naZgZLekWhd+Nqa2Z/QFxsomLuBpf11PqpwDyyLdqddDnzn0bUV7Xr9aSpwJNUtV5Et
qXmDwxgjMe3Gc5UaGsUX7fj9271RU118dYcAwiI3+3K6Fw0G5x4nvr/5btJ5jPpMDlCyQuSNKj/g
zuy5AO4NKuJsGy/l3Wa3d8dtQ+LPShl8GhISCiqUMPxlnZJUwpk9ugUR5NWjqQsqRlSR/msP1DMF
2DXDgVvHoMKszVypk+jlvOvykxRW73UKtmvVtyX/x8nrWItRNktbOWnkyGnQts7j8NBCvDOqahUd
uJnALh4SOoyVLsXeNf/elNDbTUGcCM5SKLNgtjNYBKV3AAXwLncEAq0oDMQmIp1wPEbjM1NHSg+3
nJ1kiXVWao+o2uW5JlKHky1tPx1R0rLRl0ORXyVpssfWOgIgWXuexwp70qOb8f07Fngv8w0u65r/
W9iQrd4X950krCpTbYpEJD3QeJa3N5EkifANL/v7xqnCsHp7FLtBf0tKpS6gjuYn85mi2heFU3Yd
oc/kwbieIL8tqXdl6v+QKzjb1vjBgI4d6oJOxttxmCCenHNJSY6C5AdhKSJSwZj/kJi1nKiDoes5
RG8VpTCLkbtKq053MxbGE4ed002p5TNm12uFEdW9U9esT0rKIhhHIch5QMqmN0GdDBAiBAeudCBf
hrYLRKM/adMLbSb89L0Vq6u9q5nAh6iuNLz/smAa6nyx2CdbUGJI+mUalRpUAkWQRJa1hKmnH78a
36aIWpgWhKX2pLLjo1eKH/kCxw5m3u33NYTNeq94d7eB/c+L/2ZSw7g3ujf+jBlL9qxJgvyugVwT
/9ly9MhCzrUEVKYbXFnyqzLGnDPZxF6/SPGa1S2J11LJ5e8lkwRM7ws5wyPK8CKMwL22lh0GJPdT
o30RI4XP/I6Iga91Du/fKWUyv3UCQ0olzEsacUY8VIcz0hWn0VtawV1KpHxGph2yyuFMMqY62dWI
IPLdZMkGzHJw32vUvFvKNwQd+w2UG8mYbPCuTRaNfszoFS4lpeMmAwOnRIyi5rGkgtbQMT16KM34
lsS6ZqaiYxDHSaeKYGvz5e3TKfBR2ZVVOAfHgFNe8vyoOOIAsFSRulop+NFUE82yjhk+umh00nIv
O3ObxLuPCVoApcLPAy4xoDrrHERDTUj1tPXSyD/FloibRJkGd0MqgvxvWyhi6I+NU4DkJIXB6njl
F4KUdw7qoRqgIEx1S3w5UgOf8RHD5URreN82g7u9TjQ8jhcNjP1xg3w6qezCrBiiR9z3E/MxBYpp
5fMLHihw8yWC7zokNZ8DAUWp5yFjPr2rvdALI8ySP8OW9Meki9IOUTCHfEK9wrH0QL7pC1dP3JA/
E6jSGJogHekiM+CMg5z+K8R6yCqHMqKK5lI7umNsI34VZ6vI3akbYrK7LZcvZBm5LdEsdYDGl3Fk
JEhXN+7ZyyefiOVKM5dSkvgT/qJcqwEviS2V/knJ5J+lwgM/Z77ehcqlhIvjSVwjsWYaAns8PL6J
gNuEbQwVdEqDnSrt6sUErEh6Oj6Fof7Va+SE+w5GhzouJ9MCTlHhx9AC4IX3JGe4S6/G/yjdeXAB
iiQBOnrtn1F/kNMUoPcew3ew5Bmw0GIkDNwVMegx61KPntiK7OPDTdd2/lt9lK7lWZkx8YzIq5WD
OcCQvfSpsf/gAELt7E+ABociRif8gcG2l51qkrNfMdhv/uYjuNcOVC4V7k2z0rzbJu01Qg/dmX+r
0VDKcXRKIEwjcKbh55ZaPwqU1uNhXLebOGXbnq6MFczJCRktseQiCBfWTceZWDhMzBTR9Y+7wtpe
TB6bpDwfPy/vzF3jSOWBs/N2m0S9tr8uLCBTipxEhRN0p2AhpSMH0GCfns1CTEVIGyv2YMOlxD/R
HiPWomPgG8OdtpcaLBannWPDqBtu8jAkK6iUyXw3tg/O4sr5RbEunNeP2eRY9yUnAzibTujkMDFS
wYbnA1dlJ3BwAaAGuT0jzLThGfUTPp+vHmyNhvZcwT0G0rQy/W7uGJEqhnPns4FBvIMEeDCPepUh
WOY4B/MkmKOIcy3OCFUrT3biF8raC8Sg1BcZ3pA+rhmRi987bbJTcwFuG8ytarZK93M+f8/utUKZ
Mdv7KpTaAlnqR7jLW6AT1NH4b3ZY8EfRQ4ErdsSFvfvjEH46ny0iCyvuijXP8qIMgOIKO5N9QnaI
OMkjD0uGlRjxCn/3LqE2vQy6kHjt07zJ2aHGomGy5axyDgDaPCX+nlcCR4VoR7aRf8CmBKarH8cq
64w/X7+Ud3Xwacj9rXxlqes2+lHdoTm5+prFM/lvLgwJHKud6q2HVIRg8Ss/92fvEuk2nqqxakfD
J2gbb7rf92h/PPp+oiKNuUOYjk5coQSjVvas2eFx5lSPGzan9kQdVeaSL1W9H6lt1jqTjy8GjGmw
kuLgOkztqp2D/pqGxj/2M2/2MDPwWrC6l7FR7c3Vi7TvH6v/b5IOA6qtlKp34Gk9473EOlBzuOcz
5btJQZTc8kzT9IVPheeVB/+xLn3WIfk+XMlrL76fAunMJXXGymm4aLXM9V6NCVR0f/n4OGeBwiw9
AQXBJDCg3gFNcGG8VH/9oyHmjBNj85lQC5enRK6RkOq7hm1fcSxItseqHQ4pZUhaQ+U5CJRv6rTJ
7IY1orKS0M3IctZAXhyJPpCLtJBBUFzJPbJbOSckrDdTO+xVQxGtosHVaBJyJg8IozszVro5CIR0
dnJRX7PDEHIk3pvggYiVW09mW/RIApO9B59uJMx1+JseDml924M/i4hEO0C0DOUUh0NL+ht27Dip
Uk+CSV2+GfLRLZFJofdn7TY/19hs4m1RMUv2zdaGx9IZcXmMc3nsWvOSTlNR0F1Po3u1DkH6eU/0
+0UHRV7wWgCeOA9/bYjpUNOa+YplIG/n7YmH4kMYc/gQXkHF57m3N2RhCYTY1VwDtnmBWJQQDvzA
u7vBs1HVAvJpbCcI/OC3puR/iSB6ilHagR7xNWNJz5eumdnTR7Z7ad9WO7G78zYgkzfSx2V+g52X
NnvyAfyo0OHqtfNm0a8nBCoW1YDWpJ3CHssa+46Rrxo4Pap4fUt+5x9uqOFjl2X5S4o6e1e8ij6+
Z+GZ9NKopvkBEgCYT6KwUo1VeJfAVLZb8WXHYlqoZk5fE5soKE7dJG891U0RJh4tLKIy2YulUam8
lCl+NzfHNT34HeWw6O2zNLiYyRP9FUOre8dzXIBv9LeayFJhjPmhddaWQAxNFldDzl1qWIEDBheu
LUS2AHIhW7TBqRZszrBQws6wQpZCk6eTwaq2LgVk2b6RRXXFvkIHKFqL+Z22qGuIjXd4xsGSjGI0
x4XwbqrqMCK2tb+0MgwUnqtq0u8YAVkn7BX6gljKzBEM6PDpDtzN/rYEGKt108H2z7wKeeFnqQ1u
K2MYbjMWjbYa/bpzr/rjK7ljGEx327hDnl3LF0wYXmdILOCl1pzCIbCFXCrLRyVPAntuHOaXlJS0
HS4PTErUFPrmN5+6hcF9e90tp8gnbsOth76++KXACSHLGDxzux1xexIQ+SkhhLoNxu26c7ioFU/g
X7EmDBNVJ0epJRKrFM4sFaZIrHPPO8QzA+sEVjeCQZw+KmTVHz2bxznCC96iOU1ssiE39gctmqPv
NGWIa1GySM3KBYrmQEb8ifwbCibuqxf9AgeKDVK7lNfiHxSXdqRI9VB8Q6GN1/86tC7T85R/9tot
2NiCR60+e1ibeme4pcnlHMYFD8ZfkE/TTgwizCMz0pwHb/O4rj4NtSkZlC7SvK5Ge7eSi0UocAJ2
OH8BeeAyD/XatE74tgrajGqz+A63WnInM2G63vSUoqxh3O4fKjlIawbg0Fqz7mKahXcrZk05Wry0
njZVC0+H/FGqAwgHCpAmfQy3az3lxEwmEfhWiZyoh3F5MreZ3LlNn/8UBHExq9XDnnIMohcPeq7L
9K0RbgEoxsdffpGvgKaUPC/saAUAecao4A0gxoRZ/pvb3UH9LIc1ZokP/JkZDdV/9nVaOyYVOHlK
p/Gu5lQ/GzS0lKUtDpThKeO/9lEYB3yh2GuD2wP3sT1n8UJb78pHUhPpvgyPLeEmggBkuWuxT902
xSiHFcAqfMdURWaTwMP3JIjrhnKAm+QlEr4WOdCAUe8gxs+4L3ImlcB5HjXnGm3Tkxfl1oblJzGx
g9KBlR1xYPq97i8oRkY0fhpP0ZpipabUzbfroO1ISiRsiPW8XygPdkVYdAtf0DqphGTg72q4DcG1
L7hl9iicpt4ZokN3JTCRbr+bMZEqpOr6FRm2oxLgG4b3liEBjwldF/WOg/vMMsQYHj7wpRbPleDg
Ctcgc0A3/0rpdmjCz9yPW1GWSciil1qIXqHAERGWrKj6y+4G8jXKk1YmNjZoC7eulJ1lH3Tl0X2X
bskfN1/fqSGmmN2Q/SamwhotJWhaTXnDBN3j7vZ9+Vc5YxGOUpLWH3UBnQrw2PAnsvb86E9YGohw
GWrvqsgI7jpyynS+K23UuoGI1A5la+dLSsuSkhdmo9H7fagv0W7dG3CMOl43//lMmKQTxWzyEjmJ
6mmZ+VB+IosPJDT5l+BD+AK9h6sYgc+SGtxMw19Y7MqAGQ1BqslzxwQ172LFhwMQjXVCqLuppQM7
HCUBK4dM6Xj1or3JkuMG1ImM0QQCIp3jodinWVsEKgojM0AKY9OOu47OeGLFnMj9nXYHy6wnDmzb
WnooyjNk47TOpTp0SBYKuSNjID5IbI32kQbqoIwlUe/kX/tXOvsLpjlZPTtvA9IdhxHMtYxmKVIP
p+Mkaqv4P8RpjmzLTDfxiyMsPiewjEF5/AdiC5q2Zoeby1OzITubsF1cEdNmh4U6plHxV7aM3fAm
OWdovggB6SUG+iUPukkSAtYbUkO1woc6KzeFzCuzdcVrKdw5BSVSWuB/gCTP/jht7vOP3DzbxSV0
XDHs2Ia+F0eWCpR7kBjM4YVu/1xE2NpshwZpcs8ZB4j/w1RJTLIysviAHIyW717VTQGE6pkdfFFv
POfrVByb9PN43kWYdwGCyZCM/co4F235HqmQ2O2Xq0EBB5EO2SqY6Tcvy5Dpg5MEBGS6DJNorJaD
y140/30WbKtlgdh+fpm76UrVVJ6LwZvLe4g02cn/HyhsH4EYzQEBSYtRA/btyRJ71njdYMCcCjW8
kHB2ru69zGqWOMRusHtgw3bCj0+m9fOkKMqPjQAMm933j1Qqs+JZqRz7rOtSHuFOsOHfqdTn9U36
CKX3IIhFt+1IvqIG1ZVODfXwbWidtVaKf8PoJlEKcG/Vh5teS2HPCfYix3rNDA0tlTZLc1nXB21/
b3ul/bkIrYzaNVeYHd7jBJodDipIsXepdnB8UpidZ0610y5fnPFXZq7FAopRAjcfN4RSFSwn6Q1P
JSixROFTrj6t7a9941Kc3IZZNqRT/0JFE8fxjpMM0NIeHJWoxMtlzWklb7WI0w3II3q748HeZjeT
yVmLd5ve5xOvZgl0U1v3NpWtwBBXUoFl7yAPVYsFrGFNbgAbRnelJYL0gKuIgMJ9J3kinrIHAtTd
wif1QjB+EiVCpltYJPVYsMdspe/8vEEbkGOqMz6XY/cKMMpVBJdv9E0z39KQM80LXm/RBE58xZtI
KjCpguA+SCiTaennmn1+RZGzvLFbfvzP3aUB9iLWAdHrP0FSJ4asJzIZEtiH4YTlbTijgKsMmQXV
i4PF9meca8acG7/omy6ERN5qVK3yPgTTsNEuYC5eqqqxx0YkuVP+BGBUBmXfmUJDGVRviiqeNiWU
66C+cZOFh2Ufsn1BiYrF89YyuqqLFd+81w93adNAtooWCzf3HyTDkG2GTjYH1CkSfgLoJNNqMaJh
5u7c4wnT4DM9FnNiOaiKCF0fGi4jFijhZB6lgzzu5zX1lmXN0Ft4uzKUt1A3p2BljyVsktRM8Y31
J6xK6bSDT72/GAqKYl+5/hJrODzuT44lwdrI4eeTlVtW+Zsha77SL0EJ/Xf5+dGQy4bqUPvNENC0
aJzYTWUfEspe9U2T2UxXmsY0WR5wXITMrABqydvV4ALN30PXuaR1/zhlpgB+bZR3slTP3F57oafS
6wu2cbDHufQHDyKhJoYJ4lox8Cmk8pxCA4q7Qp3j3uriOgxxREH5BWJ9/egjuHSxnnwcvfLFsTUl
Ns5V31W3qCNeRDeQUBYFrc4Wo43N2iW6Z94RNwInTq5ZhIbKPEakAH71n0FGpgidxveZGwds6wxc
FMAvtpliQoNOoP3O1fh7Nju6yxWPe3jJ8U4/QT5uriz5YMGsalDe/UzhEttAeGPZ59CofLM0MGSF
PdjWDHlb7v113mn609uJM5FXTWdHJP9ETZNzuy+j69peBdC/XmeMAG9AFX71ihfSwTOScGu6bhu/
Xox1Cifi/DLEUsq9Y45/MC4tPFdBYzxm8KzGZwIWtcbel6Op6u3d0mkhGB1wtM/8eu/TQrcDQMFg
OKWaLyx6fxzIWma9wFEuQZCnn5USDKOadi5blOYyNQbXud8LHheuB6VNAx7wXcsfoLdJZb4ln9Jk
6L8pLf78orvKgJdtsrDbK5yGLhs3Z6qZCYAx684gS0SM8of/E2hk5tble4z+E/hyZ80cowHztc0y
RwtZ3fMoLgdKbXMQfivKffvlvZrRFzdUPo161saDIy5O3fNdfKiF5uli+URic6FfRzUsGIdEAtTc
3QZPO6aBw8TVthLPbRIdb45NU1Ql22NbEZnsHBRPH2mIEsZ0asCtIXzue0Kii9kQvyLVv60bBSIC
ARBNkHLRICeflF8XdzqEPm+EMh4S2X/QqcXW+kLJuYZvhX+eR/0s0kfRAYRuCWAbLNr5GTn0+Gnh
IqO4TU0nPJuQsp5IH1Omzvton5e9P2H54YQVuXPHWlALxnJ8Bv8/tAPPStE2v0cTID+tg9A/BdZ5
QR2Ma2E3MQMljEdUEugMFIqi8SbjgV61QS0Qmz2WgE1zkJr0FES3k8KpnQsNb9+QRfruMcWJ/OQX
kUUqZBbQUI/Ofwsf7p9QCckG8PhiVnGfAPBCtkd+ubqZTO3pLCku7BHKJY76MVD1etGqYtuyCuvK
lSBKeXHtMCozmdv6zqwtiKVAn2EDX0m2Z7ese7HdXA8xtyy8f3e1kkG/w2jMrC51USp3LvMmurEJ
6MOLlLrvI6TSM0fH2g0JPoaIc+s8/WkKqMZYezB3qjnPFaBBwJf5HZMsPYJTREUZ18kLZrpUURfb
6sEO3cicQL2qBTuzBzvzk+aBCnFWE3Pwgu3CbUQgmmoZUSOOEIw3KR80SDiQhhz8bZs29WjJKoyV
ltSDX06MmrjXuS1LIqiyKLyMp/gB4TqeyIeApziH91z1u8qM5Al+HRoMZmZHxrujmFdFm1A9i2yd
IilQN8kA6O62Ls2p43p+u5EGGwKA+xoDEtJ+sG2vB1UeMggbYvN3DeJ5iem/iUstsmX36XRIDbXP
ealGRGV9MJd1MqW8nZfNL6faiAGW7QRuSpasF5WkNWCj4WxtgkWFTeYJWBocU+0HsHBV2l5KBdN0
5U4WWuF2cDI/9KCMGzW9+pdXs8LXwqjLofWZx1qbV0isoKlho/3BYQFuIEKNsp8XCtYdX/8d9qTq
Y8YQkj0Mn2USnNrZedCbNyay6KhfrgT1AztMCE34BIyivuihT9+Rlkec8nd53GXEAiFQLRpTJrhQ
+E3VClfOQApG0MEsmtob9At4P4CfgewYZYoXW0X6YeB/XLMterxA5a7qT8BjrNZqq8/IGOB0NZJ7
BwcCdvkIhL2w2F0X6zAz+PwL6HsMvPKGLTeaFRvIwDs4Uv56Y4ziGd1Iufqs0A8TJnsG978fptoC
VHQ1AnNwuFbRO7oO9QADmJ36X7NU6MwsmLYAey8QFsJAtj6AivBlnoa4a5WqAdXetbwb17sJiNuO
MAKfUugYsIeas/tLNu2sAdHbKDNmC+8xKY4ZPrl/ng+sS14zpw2kJWbA2nJtHcPaBn51tu8VRPXr
bWOqT8e7Tu6DcB1YWClSwslEoZelwxwrdAY9E7ehlYSkj9PmUnp3D2qHNQO0/l8EzsZt+q6AybVO
+DIRW4fYCR0LqfVJrzjOEMf0V/7BD+x9/ll+HxWcPzDj1I/IYntBsJDiRDmp8uTPmGE5facfq+Ct
KAE2R26ZzQvS5Hy5cehQEpb3MgmuK77W7iEcvwUpVKx1Cs1MJ+CLUNxjlSLJgbxL2xJlNwxT9Dn3
IeDILYP1Nj7e1RvKovxggeWpCIC5ADfGoIF3rI+ia8ujjP1w6Jhv2d6RNf0C/AYc77fvTCt1LeRw
9hs0ubnZjTm/PNJo54YMzXmdXbHRzaDCAUSe0d0g0Ga7AWbZ5zcTA5PeKoc08xQS4HEhiyM9/V+V
+1GR67Qg6Db4/mCanSccTwEBc2R6Vs4I1SSr8d+jxkiuI/fA4BXUwF0lo4WdOolWPK3dEe3kYHNe
J5r1V4r9XpPc2/u5Nag5D0AENdYcBIuNM/nsVfuz75L8sTRvZ+Ttl0mDeIPlW9D0GyV1mNEGUjw5
dQUDsCRH4vqnoyG2d5bXxEgnSJqVcvj62D5QbNjlsREdn6VdMPDQge3fx+sXMvJrUTydyb2+Z66k
QKRBs8jhRwP7hctKnzJ7sGxlzgTh2H3ksvrC6vo7QmYB+WLf/smT3XDl0p4XdwXNHyfZTIh5SiUS
5jlRdiFdEeJHb58ttcr/FSHtBZqChANyJzsCoc3ABIzXHoEsGjRb+nmzNKCank/gFmWnMXFtwByy
4FUxV9hyr3Bn7P61UUaxyzJz7vga64rKZi3SDzkXEXruccWdETVaP20c05cMNA3PMoS/Z47it8wC
auhF3DTYHqx0KI3RyT+YSD0g45Oo0Z2r0Z/DBk18OfaD8SOVFIzgANecl+vsNZ81Z4QzKQHKDNWi
EOGA9vYDU3651W59oEMHVwp/lr9DrEYnIwt67Sues4iPhKtfHG+5qMBDkfysgWrr294EQwYSNoOC
PAxWt/eRvHXNhwnw9LgcL8V1hBdI1tWrZDtj9MNmA4ionU4EuPC/tvkVsGMO9OkNgOzl/qHMVg6s
wEPn/ns6fSFUmNW5tgdfgdpm+QV0U3rwF4E+qr29Cz1IyXRG2jU7BtPoJ9Y+m/bCnuWQTVH3GlFN
tueZyDX43t5w/A1rdzwRn5dz+5NoI+0NjTQ3/F8jjLnMfmGZwKuYS3Y1weenyz5ECvb2vbZ6+4gd
rj2aYjbc2I24mzT1FaBP+EYI+aR8rHTASRsniEywBK1Phkd7pQwFbjVFtZoFO3JJt5J9aOVh/4vL
cUgVtmD8PPp9fgAhonMCnk9vRS+o26AqlHR4Zq4CgRWZr6o/YWAmwt+F7UYe6OA/lwKXcuYrKrIi
kepkWxUVMyXo9zbdpWC11lpxhTnkJT69wx20EKWNbPP+Gb2oM778vsEZ1JsX7sxz77d7ahxQ0/Ic
IaVMRkxqVv6R6PilYHIHYfMP/vQLfOb0urrZ0rJuUQvVTrk8XNAWu+Ork0V3BAZEnpYGRuBwREEi
Z/1it7Jgl8ZTc7aVNQ1jcG7t/R+qbLoAWYOB9C7/xIUGRaxf5risqWPrQRv/Y2frMpcnw89cy0Fd
2dpImAhqyWGFeNtmk1coxdQ7kFVBosi9exHb2YAxCCd0FZUDg3wCHwLPCO0mHNdLLyxjuhO/FkGh
1x7oxomqbL7tsASPw0bx7BRshe+AeJDToKFO7qwxn2OBfLcDszRpx8uBtr2RlSJboNgWeUfzh/xd
8SfpW+yvJpQF8hJeNavGRaXPz7O/FynhuQPL5hD9Bt2fzlw4qSr6lVCBZphhJxZZEtEA6Pe7OxMJ
DPv1MURBHTsvmTnCzdZNlqTEHvQ7TRCr+2gW2i51kETYGjuRWWR9T8gBaxQ/e2bm0WkcntwQje2Y
C3rYbGnrjqxyK/kJpDR5s4d2/KDlK+cHin8+PlWq0IRiy1ihm1uE+nh4J8IcVIS47JFsBBYFQ3of
kDtTnxWC5FDDQuiu1ELDcbNmLppiePMSOQZ4K/rcMDFNp4UzG3WRH6uda5yctVFiPrFOOrC66dRy
adcdAOS22jFF4DMV8CWcv9SSeGyCosaKonToOHFUQnqOXM1yDcXfiBj6s8ckj7Th31VlxfUr3Cov
o0Q4iuSKUwZJ+3PLRmEIDX8Q38PGt35MUSrRE3WZOe/EXasA3Yx9aH2D1eNm9ao4A1o+2ycoh6JR
WChiPpSW+8LADoyIhPlNQNxhyISyz6RY+AkBhbzn1ECjpzgHssvBJEmbhx0YoZy6BopaJEsxHfd5
1SrxX8LKLQPIcMzEAFsS91Zd04SLhe/7a1MSmjtT7UJTyF2JB/GkgEF1mlX2b4+aijxdx5P+riV4
Vjr3OMe/9z47amsgkosRYbICKQHG9U4gyowdTJuJfp/lmPCRNxBknqegNrYQKhOyyvJpRVmKOXeZ
/ozn+VIsEXHkWzumRtPWLDlYaG7tsUd/iEqQKhpKsGUyhNSpCHgtNxyDxE9gfH71kwLbfkMZSZAO
9njBwO3YB/4e+oEH+ioYLglyB/Fdq5UpoS+ndpfGXwMelDp68q1KG3h/555/al0U4yUSRIqyiAKn
gKteToLXR7yZOFGmD/Oe6woDaJCxLtQ2coA1Bv/w7Z5hTkiLCERdtBkTs5V0RpvRqOokh/Im8Z93
ADJFsTQUGOhL8aIhZZp5eyuwvy+cdL5MSL7mqPNiE4zIdsSrvI1MC5bYiiltu+Dz3wqW2EGPlzdw
SZl+LVgy/Br+BOtJNjqFWNJ2lfoz49KpJxNaJsnv8wnsRvDokimb8/FiWCgH3UaXW9hz3AwN1n4S
mbW2grGlEzdGHOCs5m1NFYKr4hmgTLn44NLj8hxl/satJ/RiRU5wBIyZI3gKPteHZ2m3/6apHeY1
aIIEpBbRMI7JUs7ppFNNxUqSBdtG5wumHk31Q0THmaU8E7MFsSO33oLPiuC2BHTLWcBdAJkdFjQZ
4UeqZKQMq6r+Oa85xv7/YNPEwapZHDA5B7SZx4BVAW+qv4lZW/kgPxcmWDHSZf5zriqT7FD/fH1e
Zudw+4oVWsp8c74ksLof2WkrtLIa1oZVsgOigD7rnXqrJKJcjXuWD2F/n2YagV5bphAQsKUt7F78
3bTQqXE/z7GXAR7gzs+8dB0+T2UjmDQLcejH9rlCEIcYQb6bJTGDdtPinZteEP++Gf/FsfwXU3+2
PFvBHDkrCCOmclgaJT5JGmKHX/qLVs9sZofSueEFo2OH8OKwtQzu1MVEvj9h/+8BuQ3M9Xs+C++u
RBi8dxPSHh2oxrf4a9nUuDcPjErJVnJGArT3jeLruNI1zuPx/1eLMsCcR/wf79408WTWYXEDkASg
cDnDar+SaBe386UhxL8o2l54mKn7CY7LYJL3EN0CxEmglAwNpQ82QeKQPKtFvbNMHdQcJri5FHnR
RKF6wEy9Sm/WegVlfp6A7I3f4UPsWyK7c52w0pBFeScX8Y/embfMBxi3ot2YdFYbl5jFuqo7A02b
uSkW0FJaocpwKgDxVx/nkMZ185RlbuhdA715aDQU5lOHl/waUFOsijyVlOEtgRyDfVMC/7K57ROX
kPGUPGnaze4WIMqFmzwQzwHC9VPKSYnsuKaHIKlUrPnV32vvPFXqlwmhgVJtxtFcjCuZ6DXAVf/x
3rz2Q418zHfWxhIMT3je8TkmuXSXi7G43u6za8Am141dORYRVQjJzLtD/2s/akKVk7moqbupOV9E
gK2QfXo0x8t3GGZOAz/mlcWONwxdHrI+WHEkCGfbnZIWsOr7zQ8RZGbDncUm5VPSqPRL3IKxoHww
2Bv8WEDnibJbpTNWKFX6btNlz5iIPNTBjqXx5520T2d14UGiCrgfqH8a8AMfy4bdk03H9OTuO01Q
J/9fFzIHmv0fxOZ/V2WjbemX5V8C7JTOXyZOsC2Dg66s0nTJ/RBAE87ZnWvyYvei1kUF3QivRQqs
jrTXQIQdXKp2XZshhxNZYTTF/cbCPdXSZZUPduLSkuukeFG9M5vUAPGQU7YSA19eKWbYa+7BFvwQ
/6u3HYSJl4kxJsgualnMjMK8NweirswM954ooX55LG4phsia9Nb+trxGw3KakWD5g0hAshE4CJK5
dkZ182hSeyrhlSG1Vz3mjj/w5fQfMwYt8YYgkdaq7n6h3/1O6+BxxFwBX9X9XRwNpgqy44oq8U/Q
HIMmjrz1z2/r2SUvXXcLTYzzTqal9w2dLbav2us03AfwR6y2i6hweh8oTL3b3oEfFVs53bb5kFdk
85VZlJoMgZrqc08PCReQsXrXh7KBsANkL9BUUPfpDW2QImHjQXeMY0ZoxLZEjgSQH0JRv/V7v8gL
3lk93E85fq44iq8nRZtD+qgic7UYMQEcRCiiSIIgHJv0GDaiP8QOfVbtssDCTBJiOhs7X4vZy1kE
RD8UVAzjDpgRZUh33DQVQ01+4FxnwCQRguPxmkCOMHyuyQaGf0qRYnO6Xs8fu1Z7xmqiJFl7N6ZV
S1jGzq/e/Hi25xiqU6Q3hJyz5PH3YFbj8dz22vnHLwk8B6tw3W2c+WwpQKuGhvR1T6DrQCdSkwO4
GKjD+YPBSsfOHS3/kXisYPU9IkskgTwpGLL8wj8hyrfIXpTEN97rEyQaQlo+uge3n/O5ZHraHJcJ
87ct24j0lZ4gp/msL/69sz2gVz9n1EVuntX88r0vZ9Tk3nnQScGMV+TBATPmuY7EIBAkpiHm/CgT
TV4NaqSgnmoZxfM1nzJtAWhTMwjhF2ijkfh1c21DZqn8A6gG3YX4UbOT9Sg8DcxGpWNejjjbjX2s
BkR3BWQjzX2Z5JLm7bvACXzi/g7qWxA1Xu1hVcqFQKj3jdZy83/QsLlOrTYeRfY0Xip4JOLo9AXx
ZvUYd0D01eaprrP6YPZczHWDZfxPJcqK8EdHcr4ZWNfJWzu3bKkNFitYGNdIcWWnUyUMDw6s/dK/
Y0+RaFuLtpkH9IYu31E+Ug9sztyR5U50luj1kquKkVRDF4lLJHAMEvLbzWkt5f4P7LUVZJItG0nc
38A1v7LxupKqrE+Oo8rEQzmEHP62RZCpzJieaJycaBXblmRFsRmBO+ufQ/a3eU1HGhOVwuqtroKc
b4R05KXJnPu95sUdS/rWV5JuthDFA0O4t0jdFL4SX0WR/QwOV2RxfjAAC1xbJ9TW3zT4Zr4tvP5c
v2jSyp4CYRHkDZuGjQA1TdPLRuAR4PVBQL4mNKPt/L3XhMIpb+zCT29PVienNbbrEGvEc9Rme3aa
ac0AJBe2EnzbaiAvYuO09GGm06wD1V34brBnhnVGsNxiksTSB4QEWl908/Yc6CCQyb/KgQOcXe5T
PqpGBQxAX7iHpKwkL585MAgzWzao4CPy5Oz3Q3k7Au8O8c8KsS9BRWJ2raBSKj+8xNJTb3tDMmCp
nbbAesVYNmPabgHQQ4+k/khfNaWR09DCLMT3X0WJQrb+Qn1/GwgAzl5E3J2if8NwzAiUZdpaZNzQ
hxH3NSfBH/dxv3V/sBC8Cnas8xr8mtXr2W37mVTUbdy4OMSkcA76o5mBWKv0FvBjxGlyeo4SqiPp
/uoLAIRmW8G0yG8w5NUr4hAdXY4O5aQZ7dpYg6N/eGNTZlzhVN9X7jB8+yMAsud2aecpw/i1tFXY
yyaeCMH5Qk9rEAyrmNtB1Q5FWQX7FgPfAMNRjRAh5fh3qOLcX8B4KucpIHqFruOVzPTpln2l0XKg
7OBd/fRLUPpAxfuB/5sT3AsUyt6U+FpptXqsZsef6Zw/Vr6SQxTtZX64WITvSh64UfLp3xkbWRZP
g7df/Bn+K+sP3Kt8Km1VwNONxJMuVX8xiqBmt7Q+DVDtEJbue8CjKZfWZnq53/RXj7Fi229sZH1l
Sl4EMwpqzm5nRIkD2bsFPAHus0hR4duIBnMloyESbcfxhsxwMFJ9iFIgMYOlm7DxrELowsgAJyeM
MM1/GlDT0WhDYapYzSL/LEX9LqfWLYVSF5HUqGv1t8Lfw5HwkIXt1Rn3fC+4bsEVobRcrlFZXRtO
gGp8xjcRzAWSG1iCKyuqzPDwQoEF+0IKtZ1G+NSDACDocBdxcPvbvqLMsWJlLq2R/QH6MA/3+OP8
vncGN8FtAcxte08w+Yfr5XOMsR9uyyDUgrhvny94cEEnPON3kbFG+tlAnA8SJ1tzOCKqbwc6FIuq
RbFizUb1IW5KowNhg0W3jhBhAXWoag9va6vuubA5wvPK4SfIO4OZxGShfhXqQ79Qy+lhD3QRl2O8
OA/Yi1aV+Qq3ydeLNSns6U+h95es/ABcitOG9s2D7Mxfuq/nmnQ973lYD1VZ3DdKAuVrpfZezu+O
vTu1UCI+ALPXedb6dPTSPhT9W7duYMZQPlrT7D3Mmb4BpnprMIbRwPRIeKdLmfW+g5Qqjydo8Qy7
4ApLtMFkum/LuH8fAP/SHMVCu+qDeFNIpRVTU8C67761yKkua+QDX/uqLxH933zG0hJDV9LuUpkw
FlEppOoiCvAkZTTMRy62eiiY2OeBB/m0Po92pX1q5tzyQdU3K7w8YcAW6jDgolkdrWiEaLxYOruU
zDKgdFir68+8mdx1Vo9ZU774iaZXGJ9fYHolXq4tCt1gIH8DmQk4PieXdp1XGiUfJhQN9wRS3+5D
i2FU697N5O+af+APkGGxtKjFi3BswAzmbkd3IQA6XygLBwn1UXFjojNaS1KyBY1zNQCi7j9gYi03
ohR/0pHRPEJsV/J7el9Kmli/i0e/Aue6UG19kEE0ZV+ySSfakoiYNs9KY5VS0yAY/rVIX9YE2o+M
9pTD5lEpqDKFj10LTp5btJ55xfi4z2NnOTFyLZDCGR+3QkSWHyI6HjIOK3P7wUEGjZFEbP3/Z6Xr
IorpWEOhN3TWrBq15jaLIqtqoJWC+3vfxRdj8c+yYb0s0pGft8+sZxifBULAjiMGFk9zBMiz3yvK
tPXzdf84CKUVPOOR//sbFJwFhhUUB5EXaBaDwdYL+1HPqR85w9/dwRwcVBRW2JsahTTEKotIqovA
EBNUcpgV9sN3LEY70/V5awPwDNR0sIj7laGVALHPkZU3D9eCTvVKhxkL+0G0ERpzt57mAfQYJtfO
cReIg+EU88Owe8YofustCi+iZvUIQ6y0jJKkSuYz5BsF4+qbzhowEWCWE7CR8EBBHMRuGWg1WkIz
6Sp8+svJQdjJQ/eLEkR2B4CS7yuJjEVIEKAzjF92/JWdFLUh7z4GCYXNscIlXns47L6kYm/7Od8O
beDkvbEVmiyE94sofljxrbmMQbNLqpsMbkSega6OVH/VWw0pBalZi2EVNfWD6XxW+gnEiKpshO9D
J4qlWezFm62DvECEdgtHoYo3766Igp9tRRs3DE3tqnbXq3MAdNA0t7fyhwNhafXzd9VPAn+6Zuha
OjH1SBFQU4kcWhkTkOj6LUYSxXT/82ccLvo7OyijyaAut+Iva7JStZAHyPnpxcpAJgyS4utClLiS
nmrNjU7+fpUA2DlMddgVV9r6wW7JXU6FL1PFdXg4j6vr3X9vkZhBYB+zw7QtigxC7jP9RgjSSq+q
XaIU0f3aBq2yMbxAGpmXm7gwncyt/DCERrI/g+tCPnB7l0U00HAyMM3785LYy4N9rUWUa/PR59d7
1yvt0wpoVPiyIgZXkrChGwyPDYODSpYv2zRaoEo0Y3CfuEC+ETeFTwV+MNvbh/XSWwwLPsYAYLnP
mlIElOZhlkyFrj0cgn6sKfS0MnBDvC+FpyNSzKFs+EnJEO/4nSS+GJbe3ce9gwFMXFrvd74DO5Yi
6B9jonr/GhRArDVXMF2TUgNuvAc2fgQ1gnJYJdfD8Qz+G9tBBBDslHqHRqPwm5iPjzli6fqP472E
idpCM0cUAPo97v6SNiDzO/fu2Qp3YmAnY66okDgZgpsH3RjOCZh60LAbHcLvMovu/8jEfwosovP7
JXdqNNvRFtI0MDYb2D9mibHtq+yrZdaMExsydaxoSuKB3BhAzQe+qe/pijVdS9t1V4D/ZVuzzPmf
v4Dpny0zfnitDBh4SiAgJ5Jdiwuoc34JQ7hVDETlbdsaTjRhh4YMlG7Kmgb8k4Y5MiDXpX9v/XRK
LauSr8IA+30ydh7idL6alAd+ZDLIFjKqwK1EEN3Qph4G2IVNXIqdC4kAw7s68CEKoNkIZiNGkafI
rIyxJMM9l2jXl48rv/SJ491EBvMll+NrLq+gOPd6tnh6mo3UxKX4y5kcIRF1V5mAIaRlm36iQ6VE
gv+aARAe7co6hxOR1ZCChrmvO4cc0XqKQ31aPOxAK7oRusBvhXstHOaDpykKofROYDqvaiWJ/q2+
3YO6UY25EcoSLE5QXbk078nCiVB3wgYHNH74aMUJeVg9DQRWnY3s+sOqKte7W13iFnPe1MjzSBKF
/8rKKuuhko/ik9R7m4EHl/ewxoYxmQQykMYbKaWUikrLonlSIVyRngM9rNrdabQuAAjSX2XFg1hf
hoLonyyBINncWo4xsur4GN1whXWCyPimnmGA0vCcjSUKXIDBig4TVsmjJUHvFHUXqpnwR+Qk8ieg
Y8/0sO9YX4tQ4N65Lmb1wJAmwaN5B2E+w9jgWCpAuKkTk5/nfNNBm9GLRK1gqguT1hZg6x/leBaV
TEIO6kl2mIMkzXgG56JnfQhdoS0XBSD4Gg/6AIafnPjTfZOuNmlVBWdIeamfLEnXFTVj+RWtImaT
ydhp5YrQ1NKRHz94CQbuCzF5VfTGVW5wAwHNBBHKFGv0LGDNwvYzb9JikOf/rgcEReKPHPVLwvF0
oecvsCApbqZJ8Zl4gIePjDAVd0Es52LJlkCV4a+sbDrZQXTEO5KHj9VMapOMHrBM3lEeoq8jU/Lc
SzufbMiTPEAzI4c5OOz5MbGYYAsMSGY/BfX1WjReNA1vxHcNlYN6Z2PdMIgeMBBZBK4WN+YGKcrZ
NFbNxUb+QHXEsghlAz7aMHZpuZhE25exaLsYGmeiSVREQ9ibgM7LVqZdIvX/KrL7grjpilhy4jFW
OEl/Cx5nAUPelIBmyXyBkbeP2+tKos7jJLQkGklBFWBuD31LAvybIFkdTrEfpVyh2fivHkuIf9mk
iXD0tm3OYvfl3IhSXkyKjt/P0H7r3DY815M8IPDk5XzFGuCFE0FTtzDsQ7z+SfZPwpR63PXH7hEG
8ffhMddeQwPwWrP1PPUqjcbUwDe7JtfTGL4MnRgCKOd58gZ7bejwWSuBz6lkSEQIc8/3B5u6zDbc
+LnQSEh3WQ8HxyenCq34TbRZZneoPdgkAxRSgv3n/GU+dBlGVZO9N/SxKeDHr/nURMk7dpnKgOIB
p916DwV6SRYUOm+w3u0I2wb6BAISkYuZnd+Pxkt2gZL8EC/Iycuiy9RyUY9XM/BlaHDPHU7sbyke
lqKrbZx5bDWSdU//A0RP1HTu/wv+eYEjbZLHhLXs40UKqHUwws5MhILbJLMMNmGI4rknvrB/VPk6
79U2lF4NI+DErCPpme6r+i5QHVwETLqro8YTrTOIhov2SpSg6n18uqmdHOvNCu9TIPYAWlyc0Lt0
3o3lsF3+q8Gb780K+YDFtBCS5zvicTrqLd08vdaXi3vkaS8PNx9MmGlwpOsnBunYluKsA1hhEHpS
AFjHejSsHrODZsKowfWnYksRse6+8HnoefoTlsnL6TB1sHmZ9cQl4qiFKinJVm3lZg76TEV0xKlo
rQBQfVL5e8PcfD4RdgwwtPOboIv9WOROVQym74Hx693drSm5o4N8CIkJWzumTFG3GYr0O6VWnrXa
lcikx7s0xr/Ra3NA8brK+FJoeU8IGV25V92Bqyxno7j0odKWvyIh55MxccV3M/ymjfu9GW+322n7
g8F0Hg5xbosu2iLPSbnWAAtefzgREjv0L09+mO8yoy+F5DLvYCSX9RfQhWlkbCbmWBwcCUN5b8YT
Ozdn/P2X/nQMVwsfB+5tUaxqsOUlC1To2gaIFwjDwXocZ0RPPNR51u/84snWfondEL93bkbBH/us
VGSIWgUqZvJ32xye/ca8b5iiWNZHCPjg70P4bdE60a+co6O0Qo9HCS8/oO9sCv5xYEIZLSg7FjjD
1pGsAqOHfugPAT0cZuo7/fieVrHd+Z6dSJFcd1YowptIdBYsv4lI2yfkxKRtvHMwedDV4td6xZQy
7qox8cBYFGsmYEm9jzPboOMB7vOlVE5J/9KR3f4kdXnYl9FoJvA8JCnXLlgdT6rCz2HdRp/X16mW
jNTbOdB0rGDhDqcjPq2+YsC+chaPkTVHeo1IJcrNWno9vYJnY0SLieG54nepXYmXZI81zYYYorfP
28geuJcWWH/1dpi6g86/KtcnndLMao8UwooajBBNIK0jy7X74pnZ0fNG2L9PNlgAFx4z0tQzBNKM
c9Ijr5spBAuAJxhROAFbC//kopYK+qs+SLiqtnY/NtSTfYd30jBt53l9xqROocgeqIM9Z4cNFYdJ
eM7LTw/Y0UxbBa84Mzu0vwj84Ps46Qwo0qT+SPguUalVQB1ptgQ4kC6uDn0o/0Ig2G5l9KQmj3rn
ykUJC3kcOn/POXHLXEWISYL9oeX4KlbOEZkGEpbNwZm6/O5uIlgQkLkpJ1Iz14+ey88Gzr0id0QL
F+Et4kEZW3zCKt8rzC7itup5GIrayzOaDTNWc5n1zsuC3Vkf2IHmpU6liknuPB0ejfta5b2fHcJb
xfTPFcD6/yTw3r58UFpq+GJH6b19t2vQZ4+6IBBN+vGbFVwNxJR7XDzwPB9T9FU1uj/KvRZgM4dq
cf6ZWEnJLFhO2gwZW/pbGOhMTIGiS7fpnfThqMtz+PxOym6gopOD89wtkgDP+SpNVC2nLdaSpqjb
chAvMgWeaV0/9By9WXW6Uix8slBOMWEs7rxVMktMM8BZ/AjvlTOc/KuOvNFEqdQjutOSdMhZErWt
PX4pz1m+i1LnwIgq/LrJLzZ8tI+DXGnVN+EeMF/bfGydjikflgeYUrfU7mWlCZSGekNeqnHkuOJX
43UCP23patDswkJUlZojZ1y6sFtfdjbHkHhvz5sSIS+IVngmz2tPJJSZupRj4BOWpCr1nzGTTeKp
npE/LJvsjsP4u62G0R4htnkzBncc3evUQ7jo3anRd10DE3nJa4vvYFf+SxqbsTTFTt7ydf5dPx7k
lDLV5dr7xIzTU58QblVVOBJHSWAugimvbryDu8phHA3/OdU8Hnz+6Ga6pUxZhUGbsUOvlhcL9NeK
ROzU5JY4js0UMezslOuWxIUeKalbQtf5umWT2tjyKu1tx+k5xusU7qs5ggxgiowMdt6O8fg6NdhK
4lpI6yie/KpUcODXVJqZZmJWODPEz8Z9aaPNQ097GSLMH2Xow8KKv0b7IeQ1n3/Z5x/wC+B+qiZw
4q6EtyrAVV6IOKrvdOGT2jeopbtCYidJ7rhZXGagNLnrkJrNkWt5hvMP4GwzJVfQEfIkpRl3syxj
T7s7hWLbVDapkqt7JefsKGN4QlhN+XU3pKaQPWJ8ivqu+eD0L7ZW8f+4vsOfvee/LpJRG6nuJuwE
4kQNeZ/U4Gys3waqEUmaZ4eEOf+D8enOcv190Cluua6ZvVrr8etDD3pJNBoaCaqhq70HgfmYmhzj
HMh/UJ7g5WdvFP80X+CSqMVLSfMh9pef4h1IGc/RAZ+JhcRKL1UC+QdfZDpQMZ5aUQJrpEO73hG5
Vrbwzn+hlw/Ag52mMIaLU5mS3fptwX3LZnF8xNER/5F7xdM2Vb8ZLQ4BBD7UjIf8cg8+i2kSgk+n
npBPsWGi9zVJWPo4/nXk/+3YBzDo9OK5v1AMc8reDZ0uoW1U3fV8aOtbzitu6V7hgrnHFLleV/my
kqkiq9nIc7lLnDZKpQSZluhdmLJx7nXxyBsYZXxXvs2A//dMghs8KryCyMeF+e6dTSu7jKP4m+I4
zZv/65NV0Etfxn1sysyl/L5Zdz2ZDzRDh5Enxri5FdZAGhhjsoHOxMWYQxvAoovm88IjKfU3u0sJ
0Bdsr0KCdzKKROVqRSDaqvZcPl0FUSgI8Lw1VduRkBcNEbwz/XhOqPrr452uI85El1JICH55oz6L
9FnUE4Rx53nMkNSS2TUDeFONtFKvejz8boruTvLFZlDjC1xqN5SmkHSw/HUYLEdijTMbHIdGm9FA
nbncPNkDGm6j494i4wwat7zUq2V8U3c/M9GDNijkQUI4nKBUnw1L5YsmJBt6+nJKoPp2lCvKvEtC
FCa0Bqr7kpMo2YQ9JlDkMZTV6t1F+P5jVx2fl2xdzvkVpqkVsqf34kSDRZxF+W6Z+1KMETbym8Nl
TWWaUISHBOQFsWD4GF+9b3CRxO7Tqn4Xif6phjVgupOYAFV7DObysRqN4RdW5LXY0IwqBvG4NGgs
06LEfMOWoz5LFLyyV6Gw7Q97cvc6zROjTIGILQ1duW+fH+tqG4+Rdw3ovOqTDpi/VKQsEPtAMdTH
wGlikzSsgZVMp/MC3YkbA0/XeAJzUBmXCGw4VyvGgb+wfuaNrgbv/aWYtZzT+gz2pRpGWFwXm4Rt
jYosXGrcWC0mhlXhQApVrKSXkKkSveK8pHKsAz8XXht1Qrzhr6A5kqEIwecgwsmwwgZJBaF7hbsR
plyHz2kwOZw7RGweGojIph/Ca+rjvG2ABx9jWFaUX9gCrAfmh+AI8q+Bm1Ms8JDAXc+t2WOzblXb
/XRElKOQdLNRxJajiJRsdWMqGj2uiraNZnlydGxglG6Nynru13UBHSqA5+AvyJxhzegqvJnp/fyO
Hq7GqYw6xgBBNkW4iXiyptEAdP3SAk11tc5HgARLFG51ORhzotwz2ZTDxE+rPBdZGsARcHtnkGxT
RTATvsmuVu4xjawOYHEvHWVum2e+zUs+FoI9PXY4DBYktYrGgYAM3Z2iwc42ERh+h48Z/iZXagix
PjbFiZ+MJAipaXhxKEaAofKakS3PBFCNymFusGCBUaLfuDtJx6Runjxzfb+Ikpj92fJGXbdkFEWr
MUAkKRWwf+tPNUUSnPUIr/RZim4jUQ6GlfeehzHD/7JAhe9zntJAxSTGMhNPuGN+WpJG0JZkwajo
k2HbhVdVYeWgwpklnmlDSevrKZTFQ8MNW66WIvW03lFpiDBwY/ba5Z1S/YBMVvjc+/5p+K0VfSD3
NjTVA0Qbrx9CAslmYZCfbaXTmSg1ueOrbN+CW6mwoBc8ditsBagb9SLHOZ6WEvVHcxcMhSHF8JOR
FQSF0P71k4WyeO9dWmKAj2lAROGmiOW+hIfbQJni5MR5irw874pECMaKTxIYUzaiPp91jbZtQlQk
GSCtLE821PckQREp7pX+WGw1W+4ZEONl6+t3O+HPDmtsIBTPtnQbVNFUvf+FPqEyd19sqxwmyVOS
kHhqoW2j6IZfyoGnLN/wviW9AUGp0ESJASyO24eFrEEwFWHcOtTnv/3Uq9oLoV9rJfaqe5wXagZe
64tmRfd1TlcbYCLW4x4nRiUm0WwmeqJueo3RFwMkMlIzohsujQGEHA9MA+4p4Pckhp7rhAaDnOun
75b1YJ8VaAaZJqXrnFUQd3NAp6yUyJTsPxSyiG4wllnxSV6/eoKEds8mUZ+dGRWzEM6JSG4JLMMC
xWMjn80UJMrK0HmnEcXkkLxYESJqMDsBauEdwXzf4NfLfT2NOuPSPh2qKplv5l5hpa+90cOtHdJ+
OshvPg70fY5tgA5e7urrreXHXa12yB7p7X+H4ZKWlomGbBk4gtA427xjqudUJqd9nzkBRb0jVgcr
awlmg9Yb3eL/sexziFNmd0tNmBJU2yYtvdVK2DxxbUrK67Oua2NKNid6zvWgKVLFtXF9vktMGqLD
+wyVX4Y8NZyQG7c3Me6DVKUIwhytwLBz4u51Y+hu+9BHbVZfmQKEkmJ9Dwf4lZfwTJSrUwyVNM8J
esTt5T8BcH80Ni9se89ek9yYQMf/Blm7fkYQc42EtuuiTfYH7DUvTt77SIAp2tJAiDFdBKi3x3Wv
3I5DtIq3+SkrwyFBeUpFymqcmAAh6sm19SneBq3mIFptNYqRQAQsxsketSu31z1zMReJ9V8/Q6ny
QtvQ5O6V42cUd479MdObKZ9lgENFIIrLZlMqL/53K/TeroyNZaT2HYx5Y/AJ66+GoLPgWYhr1Dn+
J9RRempEUkFa8pb50abnvbRbvIDRRJw8cwiB0L14xVaw0aUQd2lAtU4BpQMVLpYms5YsZOw1tZTA
AJkTVgoM+YFz6QYLitdZzKxTH7XViv5J6CmjH5c1ZqfnEEqMzQhAMetX7rE/8QPQYmr0TX/HypbQ
f7TbYlZT11tGInAviIJkduVttrmoGc8G26A8GCQO1gK9ksQX7Lhuv4jn4/GtzyuCK6Jbn7KLrn65
OCdJxuoOAJOyjJxog9RXJqzTjcZvD67ngP+yq0X4BAChzXm3dSOL2ZcOQE5tozxyuRcKywZF8t4T
k6mC9O5DGiIV1oYkDFQhMeEIp+tRS3UUvfSx6pFsOkwHDrkGzIVm7RUuoNa0jRpwGjMhJJ8/FI2A
eK4cMao3jcnKTec8iNh+qa5mOnOIOGE6ENmvs922Ma2/mdx4zaqpYR5/9dZMgrIsfMd3OdahDnTY
dX0i41WzmEqwcUl5sF/446TEaQTmrz4XhL9CPk61T77kaxrfWnifj/80F1xCdD21OaVWDgWtnq95
Vatw4IMU0q6aKlazgVemUK1Xg2O8Ht1YOTax6agBOimgb59z2ryAOrSfVMolXlZuyMNf+CEBXDCD
dbWea5mNO0RxZ8NWcR1yK5y/BBcNGXWnNHZrbds9jrF4mE+TPKmL0K8ZlBYP+BsnXBTBVdk04EIj
LmkeLseBr6SLuPu0V3KXW7VyDmfmlkyvIlgE+6cWuRPIVGAwTyNrCs1a3S8tk+d+rJ+eW/X0hU0p
3wYgTmYvhnFEqcs44vuTK9zRt9xi2fvhhAfo8udhRj2NopFrme8GXmPj3q6cnyjsaqECpWPwzKG1
pUBW6ExcUo0UD/kw+PPM/cW5y7P3RtBdIKduMzBLaVR0AgauOeaLnhhscjx1Dte69F5lQeRtKQVU
A62HBzRVRlrpxIe7BzKIeCpwpAf2cVP4iwU22+XAJL4uf2xTPGTbE7JPciQ/ryGTm5xCC5vXfldq
rCUT0jDPzQcPJJxrof3iLyad/bsZ5OI8Eq+iVvgFLNKJNhFgwpdjThqxILluIYCTzA1MuQnI9PDB
03M1S2FnX6Ckph3g5qXfgZc7wONMX9hYcEYGYDDKjhNGe/ahJbi0WW731oWc6/XebPYQBwEnD7h/
WgXCH4R4A9+j81AmvRPUW7wM5FhN73Kg4C1Lpp81qRga+m8PKOQ4fj1LsIqHD6U6c0M5weNVp5GY
FnZYuGi1woO7FFVCkPX410A8aIygd4x25ViYP9tf3t9hTdpmNIVEP19S+hUYjcwGA1Rj6ZvHRg1K
F3mTmfW7raALBD6IzCkLJGqvwsDJxqcbs7S3crWxa70Pf2S3YsFovQcfOYa2ghp93mXgBQQ6IO7O
Y+jlhntXz1p/OJqQ2lCV5MztbICo5rwhZ8yhL48pVmT+FeJV4syabaqB4H/3m1Aw2n2lTNQ3BNrQ
6DtRstWf4c7kXGchiHXUH4H8qHtZMl/PnzgY2Q3zlmYp4bcLk/bGYSMx1gHOd/fEOKP+h1U+eAN1
n9gJNFWwxJ6jBTaQj7eOHD67GjKSM2XwIIBdmXl3xji79UitLVVK0Ax+fCr+tZ7krf8kKqCHo+Cv
zioJbj+KI/1dvt8N4lpi4TkVNc6CpK1rNwi6VONeaGArNm9jSCuszfFV/zyBvgBlBZG8k6oSUgXF
YJpHARSAfHqqFKoYL3oo6f5RVY8WoqtEZMBPzNJuHwJC5wUnju2b5+IMKFNrlMohEV/uHrGRW0jt
GdJ61HTQ0JbChi4enE0g7EnqOkBIxTNOfWERH1nVpLMfKDsFpyOc/hbRK+dSTxZD0Hrc6+VVF5h8
xV4WOy/pjVFbD+gGh8w9rKSUu+r6GXJn6HIhj3JZ/qsiVvX3yAdFRHrMGVKdyw1iQ8tB7SEI5huA
cybE0eW9LwVmxoLX7gCLYcbsBkQ+72tUAp53xzhUcFKxxYP0j9xZ3T8mBAQUae4uRwV47Tuo75H4
QtSPkbo5jKb2Vr9fQRAuxPYiyGMWJ2RjY2kOZL7ccWeLWJe5S3Yi1eV9JDZ4304y/BBfOsqMm4UY
DBRxYSJCmQdaYLsCn0oo6x1vwmt//ZVaHpgzNCzwXirsF2oeyb4pDSeAVObQVCCXdmPi1rkm6B+C
AFaMd/iOhnUXXSoRybG5i8qxh6U/3HfhBgBfpv2BQVQXCstyNO1FOeVYX+rgHQsF1eVuBWrAVXSX
pspwlmvWXn5qmZ0pmuKrNoIhkaNKPG50XHJj+JEAuc4uQ0Y1tx7nmy3iG2Y5FrfI6HYUmqJOP2bi
UdpeHEYPP5qIQwaEpn/Mrwh2RttT314ktP7SZiPW7EWiae9eFpTUUBJOlLXJwNVMSCvP5tSsCIw5
cAO0JoGH8gUUofeIHPy47h1tDkDZJDgr876z/Ikqg3gY8927OmWJwJfxRPPko5dnrgDU2V9Opg8u
OwDKxSI8BGVTN28oQeH1wUP/c1nIDDCEuaUowQa21ZEJIxg/fVr+aXfRBDG2iHlgAuBrmo5rwpoz
G/6sCyVC+yzUIaY8uHqu6gzLiolUAn9rdf1L/ao9CNcBSVHO3GhK9kvgLwf9ucZHxChycJNz9pSB
p5w7mcmDCeLcCayUwFyYXBRx+cbuAAj6V2c2j6vl5jpQccHzVQh4lFLaI7ZySsBJ4OpyWGBgG3Zy
1DrRmGKUbix9tc5aNsdJgAg6IbXit9C2kkA2s8xV4VNzZ7xNKAk618/VJRmMqWqzC9ZqmlfzwqQe
t6Nk44qPDapPyuSjaGy0rQ0H4qTrx0bCelfBiuggi3LnVD8kTxwAgZ1tN5nnSlDY+ldgalGY3u2q
F6dX0fzUe+OfICVpzHGF/RFlvHvkEJmRIRT6hz1K7UVRFt3q0DwJ9ZMGoksj0Y6Cq7ODwadTpSBa
ZgQwNM6mvwfsHexdMWq46O76ksjzBOIJ/nb6NeGV4CLL34drOzrPJD1tnL3QeF3wSPreiDzEIY0g
uuV0yV5XRCbRIhrITGLvVMRqh3EolT4qd/v8DyiZxbO8Sr1w/BHZX6KduCmWpoWe8O+vZxEgWi5B
UPvULEO9jZiBmAXYmPrLyGa68NA0vKLDdBLPb/l+WMyKt0IFT5+3SuAI43mngLJfuQ2T3G+pbG86
eA4vkXZNxNMiz1/b7vnbkN7DFK+6lmh1fLydLvS1msHe/6JbzcPDNhbx7gzhrFQxxuz/7Bh4zndt
j2WZRTqvHAKVUg5LLLMONK/4Q8q3CUWT1dBk/CN8ZZ18pHsR2I9qUxygzW6qx+AYN+5ry2Hh2IHs
fXHsslBj/97QkyjUkdQdqbig2SZ4UyvsO9Lt0Fvwpw7v6D5df/6Tonn5GeWPPpbU/nLy5HWBcQoO
I3dpWTH23g2eJ+f/IWFDiKFXGqUEy5wMTjC00sZsHaPh4Blvlb4sFZ2sTVJVsj7zP409p0THvVho
p6IVUoLD7vk8bwzlSYIliXEXLoVRRr9ezVda/zhlETJJozHMeHkOWS7++m+8RhNppqk20F7pkuxG
n235l5VOUGJzSAaeRIysRO99ReBN70V13394soDwJQM7zBSC69WrnjuFyQdc1i5UtlDc6fk1KnQC
VrwTGpcuCqMZCfzHE4BAsToixKAYpp/U/PJK0wxUpy5yHYl8ejnkIaU5piHpLI4wNFauR+ItisOA
d37TeeH1LwUUWvQ8UnxFjFrunkEJ5UPYwC5OotQz50UinM4SVZ48ifp2s+1sFuzCo2utg1OOXLxk
j111Gj06reP18yhmADwAKlz+P1DYxMJiYvXjIZRA6fG+bkZmvgAsPjzPDU5K5wt/8GfgL7eWND2Q
bY1pesNSjOcFAK08QoHrfpZgWvFSXObYLfT5QXfBaTptr3yf+GAWCoFr1AqjhfGWMa/P9hkDi7j3
e8nMPDHd3d6JJC/jyB9ryzFELwYBMWG1VzYstHQBPHzqSi374oZrruPYLmUnO+pnLLil+RyLJOpx
KDpC5g2kbtNtIy5F9q92VmEW1KC3Vo/6ZpEFMesFLQgR+iCNyp1QCCYagTui43tVn+bTaAxEi8Dx
GIOF5m4MblspNebEK11F2dWK7ix0tdXuO16uZdkU7HfjR+M+00EDo+KiARKzWVr2t8aGvP2/9eEF
yM3VlHJTOjve7/qQRHuMG8Hgj88tUwFCMsQi3UnFekYfmNgExTNJiap89zKEENmCboVGR6MCbIEE
CHBwV4uamiCA5TzQ6rQ0+AsPwjjvszEuFM+gQ6vo9P4t1dVM7+b4/fSUROvGDqjebK+NgikazcHS
89ZGdb1IoqoIHs+aI4o4MczYuQRrscwQC3BsldoJ4AzP4N7Cnlijn380CZT9Rv6pjFRkDK/h5L0J
fDUtPZf+E+S2l3Wb0Y2nMzNCZRFT9aQ3Cw1jtuw+5uLRG58Nd0Z8IyUOBOjpdoMgLSPDodei6rdq
otHiQBGGXhjT50E7IUJLRNmP2mYfRq+08Unj02R2lz85KBA5lzby0PPY9wNZs1sXlX7n9eN86PYf
FGdbYz9k+lf3chwQ6/65gITwAgjCmz29rlpIUXr8kL7bV8vqucFogb8vqGwTJXK1rS8GoUK+UZGI
keuOCKUJ3566RyZy7rYUnIOG8usQ8a8zyfyyLUyh3f2QBUdCoLF2E0k1NPEvmrlBaWsaIoPWxUWs
qAVbAbuArWS+GhceUdIk2BxizieFaBkEzLOUxMM45hEFTmHiWP4qN6JlGNvQKsW/QztVy1GroAYq
6r6HqbxsdR7Hgv3OmBnaLurtIUN0J58hXE2kFn7oVInDeXsSXS4vy/3Gnvg8kktxZ9f/pTyIQkFa
yGc63coHj/ztNxEr9jyYjoChAWVnPtLj0VUYSSuQZDtqiQvg+YXJD52CghFkUJLGZCXyxr4YodKO
SkXZX+jza6i1ieAsS61vbAbB1Lcr0CXvsDyJdHuIr6fafZK8Qebkz07ZEI8mRP+4FiKjnkY6GqMv
XF21QN3ax/8oCmLwEHkETgE2ZoztbjNBQ6n9/CS93+q3Yy36dB+VHMc+0UjRLj9TMHDCcliWgZAt
x92FoZ+S8cVLS0jqI7ahmvwfxfInJKWcTQ+T64pvB9d4HcoNJXbbWaPZkK5D02CHu/cjV+LGpqIX
nC8ITWVPFSzMPx0XK7J9pYAG0pbYKjc3i2iBZgvk7bRbvWyEAbNTbxYJRhQaKvGh+sHZq9xTQj27
keUKJr3AGx//ZX5Nrn4/Mo4FuTy64rPSkVEG+1BpdcnkksLd6FgfahsfzDyJbqwhFk70NKqpYi5N
OIlp0WMdRd28qu93WNuGHc4wkKfIgf2IUbnJT5tsgBZWG93/OwRWS1PHzyE14YMUdGgzmBW5bXL4
QV5K9c/CaLd4mdE8JZq9L47xaN4CexSk3BSPZPmpp5XygmHqOC7M6gmZK2iTUGKS+nL4RVFM3XU6
RI9WaUA5nwdlE12leULuRdFk/FjDmPxU6arP1kLocHvGrrXbdq7HWaAsnbjt4aFd4wzAL0QfG0ia
G56Sgw5KKPPYeJh4caHlP1woNNrK7dnSl9IDAFZjt79S9myUG2TdGscDHeoWvcaAR8XboswojZjo
liGBGC32LDRWFEoqO/PBumH5qZznTIztTmy98uDf7Mq6egFF9OoU+vzS146STDZWpCnAZtteobSW
vT64EkTCuesHML87khJ27F3bwKWS8NGcj0CBJjKdpTae06KLHbzy5RJP2tszZ7hmGPk6tNtPA0qa
Gh3I6+IRsCddT0MsvGIAaQwGUXAugLYrirTrIyH939Gq/Kykg9rnd2MxQ+8aBXk8B2bzxrO490FK
iUCtWOYk0so5FxA58nMFhrXg9kA7HQRczZnH0f4LkbjqQayiQzDcDXfl3axNmzsOP5UeULap0Tkv
amGXsNYrD8nZvHu18ZOGKccIevc7UAe/fhYh033dQaI3V/R+ujI0M5HITTem4S0lYxj1isvLvyT5
xhVvz6/lJ5pKqGJ7e4qs/zFxduitfqjNWD8K83sREhLQEQ5XtRXT6vpCbxRamyIPig98NAJxQbE9
2CFeVsgo5gW8MFWI1skHrwO9jeDVu+1E8rfsUsG/w//9neX9CqzuaPwnqicOtT2tqVz2eQZXGAWF
TGc4Ai/y0+SBNJZYIu2mi0Z/vjPXPchzP9pymU9jzhQ5EcGA1nujwXf53BmEkblk1J4GJbWjZntA
/wBPaZobMG117JWvaPUyviNR8brpuOV9f0idhgzvXriiagvqU4uwaoLTkX469K9ofshzqb5ng2yo
HAftfgwin1uemz/KfhCymKvXaYXcI23WXSGJYy8odzP3WZEFrJ7b/ia5LAk48cau0NqlJPqSyqCK
hS3T0As/96DnFGWWSwXvRkSwX/l9963O24A//DWItnor5Ij19WjlVa7rWJDJVyNK4Gwdf+ac5F16
HevZfBt5czNq8xdQ7Y1ru9QTLg7k/hjPR50L5+1Lap5XzvEUCgdZ/dLfV/a0SLZhNgLRx3CCuOJi
9OFhtlMig+DfaDK9ZYKlKetn0jNtNfCg6OK3x2TNYR8vIYi7MyRDaDDQrGAcOxlsDeDN/Rm4eNf7
o4uJKiJl+YmdMpIxDBk5OcAC5n28IDE83B2HHVssQby/b605WHl6dwvnDLMF3pRRrfUwVdIK7lRJ
VWchw+tMDh3ZvavDoiVLCd40hPAyLQd9O3W4eP+4qgb5bK6hSLQnzKzM60b1mmCFM6doWGjzNW9A
5aroklzNBdLaifkeODObG2jtrZRdYLYNUExoPubDjrglnhmD4tp9vvcmzdcto2vEHonfzRRUd4jN
O2sXOWmRujR7LGg4LS2cGrAOAMFrsnNEIvV4QiFpckyUeE3SRjSPSC/jQ5vgETl/osY3YkE7ot3/
hfno3aLqov9osGtnLp5ZRdBZLGSsP5+kAe3aoFyV8fc5QWJrECIvrVOX0xNbgU0cQAs7zC7Jsowf
9JYB57I1UxMLXXQXw+zvMx8iLPugMk6ecTj6tRlcztvPHgX5laaOMcbb4bbucYw9SjzpfDSY86Xg
GJfFTbKZBrc6eXsUU4OF0yxcSFLYvF2wRVzb6FSv56bN9xhaLQJ61I1WtuEzVwjY6eLB3f/T6E4Z
Q4eaRhnE2LWh5Bz0s0q0W8pJzk667F4gqPePR1dbzLN4T91v48PUwdlzxUFdqqFn5xENsXRgbfAf
RNJbvb3QOOFW4gLU4TvL9CYSRe86bnoSchtA/SpaIfFehPJZ7gvzGoO8RVKTXFo2p1V7wCLKyuFC
YZEmFqFEwKBhtZBsN+Bx4Riwlkq9cRrmKVbee4EZi8+tP3CMCKZ0tk98Htb4ha0Z2Ymaaj4aTCA+
8BsMxRYlKKLktHypGB/hh7n1AgV/1zOYV2teST6A9G7/vxfKUy1UXiaavLswOtKzl1qkKLP7a193
f+QHc1129p3TErj1MVCTyuFmGvFdSEZdWo1FAmmRJq16YlhvDz7OwJmvmmGtzZ2H1bgjt9M71oJK
/d7MJKv0Oyg7Qk1+OeocsIShU1T0e8pRUX8LXf6RLG92LmwXz4gji1bpFeIYa7SIi3Xkmwpjd1GP
6hYy9W6FzVT5j1mIRbLS8TY+9c19WzBPU7qMvysc2XXFJigbUVj+dxp5hRWIaJh8el2Ylyjb3MgK
4E9qP4ZFiKsfENR58rHPiU6TEJWB2xwh9IT3A0verIw++QVC7AqkwlvO2McnJXBe+q3NceZycfKQ
mimEZqHCJVtdr2vofwKRNCi7u1BD0118AcWgR0h3Yg0s6X4k+e9ljSGrclwyaXTt38dJXN23Nbl4
RSQCOtzoEYh7Jvr3qmcyt3quloGP4/c3XUAM68pndv85g7r6AyRInbLqCI4hEHB05ZXtHAp1YKRf
ywKgmpgaFTTzuSCjeBmDDjS/NvowIXt70Z4nHl2AAEZ1jl5uMRSj8zq3aVsLRa1IlNLPAs7MMgkJ
yIsgBFdTpbmW37MgVbQRqJ5azZowiNVFvvgvTZWukEv/j3YvngQG7HH70u32Rbb7ybH9RfrUFIgT
+FzlFV7dZGxK5ceZYNatEK5+Q6AtvYIRTGE0sJgd5kH3fOQrh0JAvqGZ/gaYj5JA6r7kK5f8vN91
AQGLCqxaujntmFKNc0MsvW1ecDAmccLe8EMCHW30rr0y9pQTFzXSI1GiTWc5496cjykF3l0T/yLy
5BUHIIN/Kg8Ev8ClyoBLoCb04y5YozOe61oJuaOidQ9i6gEmY8Sd/wS9fb2eLwRUSsKpzzvXfCph
hO3zYg4eLJILe90OaLWbXoNEmH3Wj38Y20ncYQ9gKEylXuaGoZi6Pu+BPZdFfCWGrzjauuW8GwTf
Kyy5klk9T/IrUTLq7hxtRv3hCpTr8b1TjrTRi4hI80wSiTpIReKZjiysXo9ZwMcE95pMJMlwLuXZ
e8gx6bI+KqXJWSxTt9iCi1bG0PHtW3577c99Da1KVJdv1bErjpq2pgCpmH0G0TJpyPY2UNl2waq6
/3DF6XpBTzPY4xHj0fKglRxw/LHSKFDiQtScOkp8roIemIGrR/+BzaomvyXbJ7iv8iaAjrX/ZmAV
jTqhr1O6mqYfls/LktjGP+9BIREGowXXArQBFoVDx2fdBtGw6laM+YvQXYzQUUKEB9IXf39CuTJM
bJfWMXE58mil4293UgCuW1wR01uTLDjPNbpn/3Ig9mf/+CYxIN6aPrDv9u7Xcl458BAB/KnZOB5P
fCsEjanQYQytyX3Jp865ss7bjTuRX0Rfx5xKzVmqprjIHHLrvdGPJ7QPSn2YyJ6lfab0w7yHjBGe
aQXcq0qpn7Ot2cx/AML51q/trjKhFaOijEfX5u07Ugmc9jycBqUOZSfA0Cb2OhtqSjt5xiHuvymp
+3V1U5zKbW9IVRSDGxnWs8uaPEVEZojjO6yO7SEcDspQkvlCIWpqvDJO7vR0SBNcE+BjZp2IpYVb
3H4eUPeleNPTD8RecO9e2Kbdor8wGch8NBEdlJL0tJ5WCnDjknlswoK2gI2T0LxBmWhls8jOYy7m
hAFwP5g/tQAVC1fu3HasFBX9BtMgbjSsleT5uI+BdOY+QakuoxODDOolPrK09nBIcvi2nWlR4tYA
RnJDC5iE+OwA49Zn4Jz5VfLmHYV6uq9AUPp//khODpUwvH3lCrBf5gpCrzof9pT+B7Ebh5Hp5WSe
pEKhpywqDPXW21Q7tMTWq4x1P88qQKemWhj13Azdt7PfcXkYjQL2eUP3wEAsAtY11VM59XDg5NMf
gWLtjMzD5CpB3DRSKWsAa8LqGJomk9rfjJ+zmeebI+eOp1G/OqajbwNLVlTfXay8lPyTUUizUORS
e72ZV8Es5dWRbFg3VasskuO2RjIxcVhUk5q04/KtWM2b1CkrwGITXibZ4LjNXebZrdeyyqBDMbLa
Pv1bumx+JvotvSYEr/qDZJkwJwksWFq4ZjW21nj1gUXj6EJVB5bbHVgEI6KJ7XS4iobjd1fIrpfe
yUeXLXLEanTaiJHEdezyn7qx9pNfx/E+ATeJWGQ1DIiTX53KjBE3TkTW0f2IcGIiY6+C5ez9PRaX
gbMYGKmDqrGTbh6ZB/r8jG7cbaTIl6tljYJ7zQ8sLKO0ouyRu43gFtQ7SiIyeg0NPtTzaviHWmV/
pouhbOE7r8vS8euLPqB9tXHNQ2dSgL78vCyI5+L/zJb8lceJksBaXh27jh+WaIe0WQ6AMa6HrLji
PUlTTnUY8nieGsolxhV0k7z4bkm3FqTIRhhmkUcJSyEAS67Poryanhic2JbI9hLeIphwd9+1wBwl
JtZqt+z7hUrUYfHBb3IWr1QV80JAKWdLvsZQ0rc/Ssea9iQ9dQEzsbF23simyrTEhOABap24iob8
Vql477bt1vKS1S0cycPC2+rZyQb7FXdTIQnHVsz3og3uS1Mme1DNKVZY3PPyKp2hjCnAnb5/uToS
/kSACDscJegowvZazJHGm27hGFCxStZlAZ/nXejTcr4rw83t5q9SMk9HHk+gjfInpdSiuoFFgYaE
Wq/E4iPqZwCtdmD1+lDhRzJfLsFyOof4ltsehIUjM51lM5sA0lpuw1W+JcCN2eVkCmuEPiyGUqPh
v/7zaWBpO0mzjCSwDenIydo/nEB1oFf5DMtblJrnxCkhfCtj6KS2ifjw7g4AOd81VVVmiiBh5qcb
uWoyscSz9InzpMVQVsQoWTE8al8n2CyE1P4O5xI8AsCZGcdVJQifwMURgenSD6dTFXEw9Qput+XI
HlhXiUK//6BSxq7VBdzmMX0XPfd5qhtDnI6OVrjvd17Gx3ijmr2zjt814tkoEOigsTsBV+GaeS8j
PzZKef5Il8sO3CwmfTlHeeN5DGAYwWYj3Fd+FIfzpUcwRU4OwBTPjZJYRlW31EApvbTnZB+ZWGYl
UEDHogCPe9h24IPkSbKSCFhT9AUSz8Y8XEA1kw5EK0wKSV6OnNzQjyAkV2D4RjlvqnvGWzkqDbmR
UNwzYa08VCLtCn6fdDfD/0+yQXn8GbMmH6eHb23rJqLY0nhQboA1t7bvbLEvNe1KIFM3IamXwCBI
xvC3EPwcZ/Qq9LVRqiL4CoTCeWC/yMPstu8ixrSomE1IDVUvCzyIdo6yOZLbHYYU4E7BmQl13vlg
KPFIvPhlsJNGbyG0Guw/w/lOPqyjCrWS6iPbmK+VBvBCDs2fdGcb+8SfSyyjRAWieWTq2xAG7hDT
1Z+VdFZyfOpHedDYI5mKF5YrxusLJ3T6fXR6PP3VCcoxROPLPp6TIz7PlwU7nK71+jKwgwjYIUsC
DQL2xMJrYr3glwQvhGv4PGc2Zu7lxqT3+dZ+bIiyiOh3oQ4YOmZI+I9dr3mWPSRZoWMP5Hh0AM85
uwXRyrK2kEeZOxF97nBjOEtSESfSeV/qyI6yNLaNOPyfQfYnQMuwsY7kKWUDs3ZgKPx81WPRl8RR
hAcT8xKRiEe+opkpSAEavW8zKLpHQQeDZFeXt7s3OKQ37mlmuS7jZIHIsC8PUjHUAEgvAXnaNIUX
bUZMuA3ybk5wwVe0+F37c4SGziVpPq051Nf3mCw4bIh3RnHoYlH1nv211WHClbphz/BToc37ZS4m
jm3CcFSX8Gbk6j2GeJJ64qATo7DQvo2a0guWBlzC6ANnlaTZXgIsWKSU16K+FevLwoRT9qoWUTTw
vkQvkIgzSDlFDsWb2Ir934q+JGw049YGRifvW/XhH1eX6L0g4FVtbb6B+Sfg6UMY5XsYx0R8yi2L
2jvGUDDdIDtp1VT82cGGNHCJXbUHWXdCrnFgrsBNdKQFgESjysfivOKHp5Tm2vGYCpdLzw9Hhcwf
2bVKuMxX9eF59vPSjgFGVpmT2gnYqQDpXgaDmcnuflgprYjRZTevmePGWtP1Wyq/TbKBS3+jbn43
CciPXBiAiGpJjwkdDufNkSpZ6N2M4uh5pYFjuWinTsextJV2ckqNGXaDQjMUIwKM6Eq6Cfj7KpHa
qnAycBKliSXno1zjOZVUctThT3Iqd/768llcyHT2c3UGMG7ojqbAN68YnrzNmzo5AcajwYBy+RWU
nn/0EFn0JZJSoFaDlq/K1O9GCagjgvyW7ZLetRM9von3zM3Y4rbKUC56hwANET9FH3WMZqMjXTqF
2gND8pIFXb+9vq+Z7p+zL5m7/VzpKXHcKcDc4MHloT1pIgnxB2my+eSe/Clg187d5ym1NrR3itVr
4aRtXOHJysEc2i77keqIspYNsdL++dhmODsi8J7ojhYjv/xRRoosDAAnziLEZTSXy/mbx/+Tt5V8
urhtvVUAHQ9Vvd97MiFOcHNp78hcZF78NwC3oMKturVwIgwQ+48L9wu/8YhYC0x2fYcMSMmuhbq6
6r5Gg3fTcC6nkk6vH4a8AvU1g+ctqULFPZ79BghkVgwIntjXREvHmv7zYEvBcs0mZMrjdxgO+S0U
7GXd0kpdazL2hztR2+fFXLniuib/4q2V8NsBQ7e4nFeETJXtDOwpgbqyeC2HnXo16dbVBeWN9ZHk
CXjs7M18Fetr8dX2xC3zqIdOHPF/jaOE56efuC0sQd6jlR9S/BBR0/RHucfVT5T8qRz0VjPaGaOL
l23sKjpxfX4cpUJ0Ts9fgml+RDJPGs3bu1H5bxR2BIZC4yCTB5alhU4ORt9beubv8vROq3w2A04w
JC8m5e75vg+F46Lbhx9QFXtXACWFcNz+pO/5wb84Mv4BoNBTycvQkyRbIDwcfEnM3MUD6lFS8pwf
uZSAgcjhsdXWSxhELN/SJ6yHjZXER+v2yP0N5m4HGmP4jxTNtbATp7qwznom9+VQXyVBL2HY+BCb
kUi/kfIReYFhtqH6E8WC4XCMx5Ja2V2xSDLSdHA3eSbrG50/9F7X3OPAtCvlJtyVF5aszDx2f/z2
GFJjwUdkdGWw0jKIhNnf5xn3WgHfV8OSMGkMXy41yCMLTbfZFCd9MF2RaD0TtGc7m0kJuFBmL1ak
84naO0q47eyPXF96Kr827IxtzL8r/KKu/801ZlTty9vAJX2lBAor4I3aLBV6hLwgAx5KtJIF9tsA
wxjjobGs4B3b48GZEiVUY4r0MVJ+/NsbRE5JFXnIHcEKeFlf0u8Bm7C6RUXN78T8FdUWEuSdI+GB
XEv+0yPtIr+jOaF1yK8jGxEELGYtVq2dJX+stdG2bFGiSaVqTLUYsud+aq2Dko8G3bL0Cy9FDPh6
rc8GJW0erbZ+jeUeegh+zcbxMzygSdbPLoMy+v8ANUSkGHCFiHXx6O3tRhJIhCt1m5tv0bUsfGM4
gzQs7bxYaT+N7aGapKmJ7UFkDIa4byOArFffgigoTTJwh5zSM5eTT7YSfhl583LeKyExvE3n6Ba9
88yOwyFMIKC0IRfmzT0IPKb7aic22ZPzJmD9o3pqIeT29EpKJOafkoD68wFUFvhowcSECo4Yh+tD
UJSxUaPU5CY4WOPXNejwhiuhNyatZpS1pDN76Gm6ReW8YrHkMS/SpABdlgROYwHWoLnXtAyUjxNh
pF/hWZMh9STwJljbPZJ9cncgwJRp6S7jSIMDJbn6k7KOf6TmpowFMYkFxuPsNct1ZNRu8zIIleav
GWa3+B8eFBm5ut1p3ByQDlEgdtPED6FrbhIaRAOnBOv35WwIuPZWqwb8dsh1XjxRyhpWSs0dU5bL
I5Ub7eg+/AzGZHDrBn55wziEWGDdt/Hb/UEZLNL3d7mzv1dGXBvtWsBF7N7BsEUoToIBrn5BbVIx
5++swmFgG5hDVXtm6lsQJvjl1qXJEig7C42GTAPn8dglMYLz06sXZTv76towgFC9dZD0eZbnJ/N2
kYADR86McaPO4yx9YHYoSoWM+2AvKjmBKQwlcW2YynuPJK43UPZTnsg88G/Lr5kbcg57aejilkMb
gUM6B5GsBbFNNnPL64X2Ppsh59v0bCwCc2c1n56jTjefAW0n7oVuqAk+OqjE77yBYOZUvyh/g+qL
i6DeelXHctgdBvZUb/hCNGJhUAFSdkdNQTsKE1uwt0RLZQzZaCgRh7dw9Uk9P4LetYI5mr8xYLFU
cubt63oanzBFY5B+JSmlrcDQ3UDG5dnBpPUdpYSAe7UrmAwYA0kOWgTnmz41oYAFbWQaSjxJ5pL/
q1BcQ9tiVezbOiis0rbOmtrzpHSG/3kLEoBrqUKSI2gWxAjDUddmXi7zPCMJdN70dO5qXF5uJS0D
U4A0ZNtLA8cP4Ac9hJYrQK21Iam4fP53LlJRoqbTJlPM4arCxoT0TGKGCYjG4/toWoWMN+bkFow5
o4Fqgd9dJAnJdL/Q6h9W4Hty/QXqFesOWhVdgoEN9YBANXwlOeFxdveiICkF3hCbew7L5ydb+qtK
gxF0Hs+GsgiPBk9/XEm50GzHwhzliVUSIgjZ1nhHIqggUYon9ENQap5u3OMSlWkGVL4W2kgblcIw
81IHxbBaBMH88RuuRT/xey2QycQI//5MTsf3AmzKOL3F/2ACHaFU3N7MmDetbidx1JFBRE/soBWh
dhOupBIUvJQ7xi3rHXchUb0n7SCJEbq1tydlRavhKJ4zUr2h8HNlJGnVKgMpCbGJmDdlGhRaDt97
lBGMGqZvB02H/9WuqsxZmOlyYYt89KoMiCuKBTBd1lKxV2c77Tqj+XliOF+/zarQ4TT7JZf1/kgD
9xxiLKY1W89hUwMuxXrdpWkg7jDA8GNAa3XJ3MDk4rYvcAM+hxXfVpjklV/glFssSDnvG2UdEfWZ
VYdtBoCdfqXKHXB1yI5n2Ir6hjHuJyT5D/JJ4UN3ZBWAejjHxdjA8tuPV0aPYgSN04B6PEyH6KYt
52VSzcUsiqz3Wh/V/03vYKGbVgwdkQFckI/JaBeaDFwzG0CEba0uKhZiTLYXr9udxa+6EU8W0Yla
Cr9LpNnt+Yk09PV8vXSzqcV0x/O9x7W+Bwg73R+ic4m/w7eYOKFbXfOmp9T4wKsbVsVTX8DjiUkl
+mVFX3fVdQpJ7/Xd34HAE0+Yt0G9AGxgL+Q2VvuMEZ4b0url+3R1gpEw1B8eitCKmk42HcfgFg2R
YbskWQ0/Mxccl2WolYc11u1MXRrx7mAFV9G09qvr+sRTBFjern4jt+9gcu9pB7Q6NV5gAb5xPWd4
lrpIMAnCd03g7oC+4AGNTBZxqSAzDWphpwCTIRa0s8nqpzAsaEWs8L6P9zaf8cTkoPIklH4E/NRp
sbJ8Tj8XWlNTOaMnDGPxRCic/lOLp57RP32biD6OSqvTlPUG4ombmtrc2czBw2axyZk1CHevyBN0
50duCGYMZ3OKNKLH4fdHrUeuplGyEAQALgg63mcQMjbYb3B2ejhLQx1wd1Im4CDnns0Ld/lObbzX
G+gZVGiz65TyjSCCAQzPlOvDV5tmUp5B9Dios8T9mPun8N7KOWOa/zWfiqimFKwh/Bti1pdJu8eh
b9f+x86vWwYhmSFZsAW5ciTg2UUjgUKZ+Fb2XJx4/C0HInSclthXn099kCbt4mtxIV06wpu9sNkg
sgG1F7o1G7f2FddVE3OAAf4iCYntFAMwIbvfWvhIxw/ycVtGC//XfcfjkToRsYfYcl5ambBHPad9
kCmXmCNeWFfemaKQgyN8aYloym3K5JWfkbrTym5gFU8gWbgtLh7pT5etwoVfh9GfzQkx18sYH0dX
8+Kq1BhXkkZo62cbX1leVqCET1CQ8F10MpCUei9x9dCq43/tcSabkBT4CGUJm21sGS5CvNScEE3/
6s3rCR8ywpka/6xUYuV5PIvQHwESggkmb5wKTiZ4mVYZGYc3HglGPyZU/zwaLggE2HWZQQOk4OWq
TIVup4Ft5nSBfKz7tykMvKie/mBE5tjmxDPrHvX0V956lfaQhFcew8MBrVdmCiJSgZ7f/7to5hqm
ViZ56xNwRGLzil/UGqJU9FR9G2fhglFMI4ok/+grZu9EIU9BVYSJyF/r1Rc3q4kSIhV+AS7XtIbU
3hJGETdIY1mfCdAV0aTuBFJmYNFqUfZ+t7Hl5MLdgiomPG49eHkDG9XsA5QpGS5+tQJeGOCdfmUs
wnuX6n5mhlaI7v8PiNGwhzHgFNdef9CTdjg0NZeGuKzs/rhh7HSro+XaIUFhio4Uj9b0Zo2EYaZ1
onlZGEHq2uPgct+qbhDBExwGUvbdCSZ/DtuEIGeKZCS6XLcJ6EvfyOBfxWB8kxdKWVYt5xrcNGF8
5GefMEJBUvPKDb+wrYm0cEZUjvrBKXuuS2Y78q2xOtUbExeNm3aCpWLvSGS9vKyxxTk9iApHVM9b
sj4Y7qDAEu1u6GkmQhth5qCLHNqWvC3K2UI96XjEO89B1LirVGnRnKmursAx+Wv1yidkVMWy5G59
24r4q0QZpZGCGSNdv8Kex1ErsXYrtdLETDklCS+Qp85IeyOHnQSXZmfBugI6JY9vc/CAXrUi255x
MC4E8OnwLQAKKnFjHPjxUUvCnt38GCg97++vUVSHf3b5YAmqJBU369NzYRaBbovDVQiOADRLUFU2
0o2PL/8ywrMABZgcG5iGoFZ0c4U57upnqLzJcRmj47skHhEePbFpC5XDlcet78Tjm5vSAw6vnJ28
N6b+uSQCNP7T84UPQNwDchV99OfLBWy9oaIgcmXf1QYc+SH789u+rH6zgSM11oQvZDBg/33u6VIg
jdBr6rOMdwoyH9+jsYxM+Bz8/6XcTR/mXeUJ7fQqjZx8KG+syiKWUPKMus273Zchper285SdwM5/
tAiuBKRXJ+OmCPRZFDXYlvS1gF7VR++8lQ+99uV6SmAuhB61Hgggqx5MrgwPWOKsolRYT8XSGQoJ
WlsUB9KBIhv2kluXxPEqwhFG/zuOmpZpo3goGZW63PAwwpc5tD+kh5gHqzPjuhqSlX/bqkYhxHkd
6+6uUa8jOZClB8Rga1dDDEaF6dvgUMYDCyTKybfH0gBN6mxMeaPVwgJqOfmUYhRQss1y0eN2yxFG
PMuYNJEZWq7RL6P7UV1VH95jJcGQAm5lQov8gZV012C70dLD5R7ya0Bw4yNUqL47+ydtxcHTrAuj
5cBMYMyJe7LJ2tFWOPUokpQaC9VsmMFPbAZaNSn4BzBGh6RfzrcAX3adydZ2dWx7s6FcD8N4IXl6
hNuKfi5Oz+Es7Td0R90/rOjEfJUI6MgcEZG9xl8MHg2k4aAeqJH7LVAPMEb0a8Zlv+FnuoQwYp5X
I2Kw8LhvDXRecSyq22Jk0NwSLeesTcJV4RWqP7ELFtMAh+iGszgelnhBl+K7fv1Bm2TgjqzTMU+p
lTXicKyJOXbPJ64i0t/qSia1BZIwLZK4BgNi/0m1vl2cU4RDUv2lQ7tcajOgS97XDzgyFZ59u48P
vqPmYjQbBYMqRVbjGHJHJv7rk+o4GQ2P8nqkY2OHFLRL2VU4/pPY8fZgIObAOT8jG9a4TTrFc0Fh
TUUjuL3GZYwyEcgLdsYHZ3YaI45FkslH9C5pDIT36Z1q4iD2ESXWrpgb7TA+jP934tC55VrFfs2p
dNgdPm94ChcE70kwW5u1+hHzyglnXV6ipI583cktWrBV9JrQ55DbhjgHy2VHRDRPnwmUb5TXgKmG
hdtu2KMCg3u/XLoswFVHJV+mNOxd/RhSPd13gazGP3lxZPMhAlN1wPx/wHci/gjzXCYEjgg5Lrdk
M7GgVuTHRaVJeo5+nyh1kJUGTI6N5l1+xWe4uEAg/7WLbeHQ8ODfMMwrkw17yBgt7mtR8A6OKoIi
gq7XLOIJ5IEXFwyNUsiTIUuzWzQPlpcnRQsoQhoZnG/OHTVG06K0QRNg9Jk0BDBbjuWn+qB29zbD
QmJ8elobY4DWR1Kfm8DJCvFIdqxtYjMlDmd/rmyE5ukMvo82T+cgncTerHQ7wvUjbMNmzzDvFVNK
pDh75QqQ0akhGEK5i+Ym1nB18fZmnowRGqGaT/LvjP7OePjRYBcGPf/DAEC6rU2ZRcVHAFHUv+2C
LQ2CB+JKLViv9AmswUGD24z/gFXPnMFWiq/yCB75SWNkw20kaD4O4YIqKUPfWYBq0aeopt1SpRrs
88iykMdqFd1eEQ71gGz8X31yn+6JXKJZO8ZThvgLj2fFDx1QDgtKMqquThEi8T4vWXATqj09qZWV
m+qnYietrKKe5ft3CN/irwK3cfxSSYptwocaJo3gQg+eu1IG0RwcYgpbfrZedbYJeaUs7AULMkVe
/yZf8coseOfIdh1/Gv5U/RYduaiQLQv6eOWsNVwf8K9ONk2pdgK++gLReRMCsjemrVkiIgDMrzTM
EPVmMn907hwyLq8aKW25INJS579DbTRWzomiCqvl6ThSwIaCLv0PC/V/60SMzK67Q5MDDARSPOfQ
7H2SreDkbXFAObr/gne+ZAFMm5oFDeUh0x0qEUjH453RpqCkiILvSEZ05DmCWjYGk2sBRs5elxC6
B1mVxrUF3yI7iXMl3W+WGx1HKdUcuwpiO0S3aPrBxz/fIfypkDOVSOOxngLAN1Oip+6vNYXBzZCM
7xXer0M/yQ0WCMq7Xyv6k3RRpSabfgsAOArHybpBNbRUTu4KMQkfHDr3Os0ETpLVwVJotTs4veOs
ELaplh0YuncPXKrxsfSxrkhHEpC1nFjEV2MaUvzpBTB3TcJ2JtgNqua7070C/wnV0C43d3aTn4DF
xtrpOs3PB6gd41brcmv6W2L+ylVUyEw8cx5E26AP7DNHGr6Gjj60pSYAhoHc1hs19DQM/fcP8qF1
+yG2vAqe4HR8Vdy4SvddhnJ3VAv0ZRXVSw7wh9KW2IKGNdbv7S1kSzA62KJ0tzcKjM0xLGZHmS4I
WNs9nRTsUiNTj+cdp6yDByyI1MV+WiZm7QztQDukRJIoL+K2QgESw7eyXgAeMlIvumzWs/iEt/fQ
Nsjsk29a5JT5FjYXja3nwjSJCwnnYkFIEqAGHeiS5VU9HdRL3Ks3NicpVkixVoP/94pRcXkUaS5w
E4K0U3s8PDNBihqLTstYoAp/M3h7tRQHAjCMGPlI6wH9eootTgjO0DQx9+Sux5KMaTm9MagGd74J
2zVMjut/zPXuaHGGm+ZhODZFpND8YjXjvgzr+6eEIbcFCJUG/j56O3w4nKyIPqlhu5MViU0YV04z
oramsXoTyAY3DEkcJv8295WGwApsoIlk9M0CpVJZj+HFEFNicFY50HA2XhlwDRJkzBF/l/1BF4vL
hIChADTN/AZoXlEwlImB2lX/gmnXXd+Grqm5+rEKtBUKvqfCTf6f+2AuraQphfW8aeqESCkRc1wU
sUQL3HLjJshg2OjuA7N2VpqZ211RN87d5B6UeGT3hycX+RNlvGriMD/26J2pRUEdSIpLnz7joJWV
R8GsHXIkhm/CDSQgV2lz/IyrpmWqeEXNnubKrHdHiSG7LLAk0BGCLM4IXcTMjsv6zzHci3KmPQSm
aI2+8QUT+CVw0oLXW9rkOD2CJ2+YdE/TG7C1F84prVyoRhXuaYqPJWtlBz2XaYTSv60kqvsmjdwZ
2onMBL/X+NEIm/UOQfYDKMyt5m+7T56PcdUKv3x2gGSMZNwUNePgjnVpjSj9YRf6S0Tk3o9ROyPn
G/3xpjxKGY7nRUga5vGLQ9YCYYe9imtSGb+sFMJuZfxGEP9x2qsrkgCRBmy60L7kfzPH/VlHIqKs
UoRivhdNnojbSgvjLDfZoOibbQ+GgtE/F7YsojpYvpOyXF4J5QTdayGIyXqr2OMPIux+CBNpshz3
iAK3dPbo9z4Zkve7iNz1Cg6MeUfvczcus2Q8mHWHXLErQ/Zt8hS10qofhJwG1p4OCk2/BPr7FK3t
y0n/fjvVquteK0Jtyjkw528xi1J/fp6OBVHryIZOqUlHfPeVYDdMXFp9d92tecbOD2gKeiQlaqR5
lUCgOXGnx0HKzAzN6k7IxbYKfbCnOQP2ubkPSkvY8FvywywaTOXvkp8xhMtsN0XX7JM/KGFgy/mL
gN2ALxUG/lBSMXfJT0G8bl+fqqdx7BITWDK3oeTRmgKj75manvPYXXHwsAa4vxGlizljPfS38D8S
z+8VKUTtW8JGfviRAcIwY48STQzhBzILiopN596YnwwAZMSP7Lr/L1PqveF0PdC+nJPECejcV5ac
rwcDVegiPMPTnRzAPPB1IO8hWC/x3NNuqdZ5bqxeB68Ct8+2cWHZsohJgTIRUXEs1ymvfE7yBbxy
uLSQ9nnDT2NCTXYtpKBmjf2TngixlYeOmJgfVuKFF1G57R9hKEC1P7HpVlG/fzUOZlOlpBKn51jT
n9JnLb+35TyyZEhYtlWXYliZ3PE9L1MxeUWeT5y7CbBSAEt0sCcTURXK1ioCq2R7SLHSiZD4og4u
6Ueia43IikbEkgc00PkVfC6Qe1IkpzDX4CtA3Q5HMstqYtfo8Fnm6GYjfV4wqAI+gmJOWoPes3Iv
KL1NB6Zx8usHmaPWMfjcVGYV7CiogsdfzbAuK1AxeMogwhOqE8gBiHwKS2/gkhhVVP57LQ3R3fyV
WnItek+rwB55Xa+H8CwIrZYum1gpvVFkWvazcIscpbMTWs5HoqbT1dEEBaed+zkJVQoSCscAGOOp
hbstZT37K2M7Lh6l1hOvBpS40B63I/POG4qhgXxyhP8RLabpkK+NLIJnySntD+j6HTOfNHgoaZT3
KNhQdoBQ7MwptfDdchWU9UmVsdAZXlJJsJIqmlkMofFjasKEx6ShOANDrjg+QH0hKecLR/1GIPMU
rgq4Gvn62WHb7Y3wDVQXyrYsQV8lkchPtPp+1htzmHL6kNNQ/r5voqRyz16/5Pp9FjCAEntdX0wA
7L4l/5V5UzjcftWHnuoySnfOqRJzabny5adya1rDpojMqC8xvBUzkyFk9QmzWVWuKO91Ng3qwzqw
Yd+9gZHLqCBdv3Er+mJdGw86PdkR7pbHy+gfSDiMXYivxJRaVNnLz/lNTo+E/fia3mf3o3+wMYBZ
rK0VEJJkMdoA0hApYMwPYmTpMFFrWSV0/770K9/ikaZn2iIbv1KkdOEv2je8vTXiBGvOsf8VXg5M
kk0a/ch4TPBNFBbJDTz4E8G21KgH7pt6M5AcaVsSmkbpOUe505AFk91Xy3PvjEwyj9/U7OIj1UWA
vibH9T1e662QP+s6SgbSAV0/5HO8ztBITPADxEvQ1I29OE2lWV49IDENddsyVTrLfwzkMZ4vj8QL
+/5PPj8SWu5J9/jpBh77BbrEXx8EKNEzvbNEuDZTUW9yjMt4vcN/Ht7Ixqn7a3m+M2AelRApGAKL
9LyM87WFJ9PGvxWtPFnqmkdnkR/Vgx38nVPb/4an4kUh432AK3vDZVlDbswIDP0pITH3JQzZtrJ0
y0+7Dbb9n4kXm3qwdhPBF2tB0wEmJkccjOWh0IaKI0pZ1we6/EWoNXw8IUsXW8EZ83/BjE2066R9
PuH0qvjU/eO4EoOWQpS3tlWKE52HokROq3QVG7eM8v8EBFZJOEbQxSPV9A1nbCZDkz0wGf84IJWE
lZYFQrUwT5KeG7B6LoMCZyvdey12mECUIo2nNOM6wfF/RnSu3Iy4US0espIBb24iYi1uMlvohL0U
3jUw/mCORxPfGrv952NsiY3vCMlOzde96wrT4Xyrp1GAMTNUjLj+cMqjWw5HF4tblqr83CYCiaS6
hgXFxNr1XMdp0Hphj98/8+UhqoOSiZrx717JBEZzUibJ5hW5yT7TQ+/IWHIIegrLGmA03dkEVR2Z
s8xse5EhktkIQN3Ar3PeevHSC1aNI0UsG21aCos7ZVXOjO+SJ1DGlPiQSxfXVovA8+95kQmBcQUx
w9mLtO7sfMfp8jXj/9X92yR6xFli0zKgi2lKofQbHejHJ21myyGjMhoeCtBqdU1Zu0UlYVFYsfvg
OHgCYQ94q4qJcE22osbTjBMrbs9sV9EHZ0vcf2uMhOrxkxfpGYjreo48ABur3T8bMiWcx53hUBO9
qZZjPPff9zoQmHNv5eN9CN5/OXMYcFnqU1Omb9Z6/vGTYCv7TlqtDqEIhZ/upj4bW/W35c4pmAiK
FZTu5aA8lDlEHDAwSCL4WJCLLwsmVklvsxUtywwHflrTlr3uo2QF4CclF6rPBCGACi0TFYnY3UfT
4gMzthjNmWcmMYQzSnYb4vlFyZTmHOlkiVBHkCyyUihITd49LkowQFt9MkHtNBeDEsIOWoBHfwzr
oz0XDW0Zt1rJJkfeoa90FvIcyCDAhydX+GXffnyouEBvbKp9zR8EKA2vyTstuCfKjI3FBg27zplT
Uu7Y18uIfVAFUCqFNZebMyYsdkNnNLUO8k3bMH5BUCauUpSRuy/mjSvFO9JSyXPFqBAfinPcbIQ7
0lmuOn8+5/kX93/mSAOEtxszdEgu5x8FudMpiIKO6fY0m2qXo0bekMXJuw8aboGTfLHkGzDCs0Qd
jWkmg+qJivL/tuESWEie6fUrNRxmMt85QlIrjYRLMywYFIpsq0emuIQNr9VoxD6NZ5gGNPLNdi4Z
ysvs6WiMs3/RSxxjnjHEm1shoLU1k5Y97ETFga8RBwx27gaJ8T3raMsirCPlNc80etyhnyD9ID2L
NKVHAKdRbgfFaoRX0ReiBODccrUwfkCIjgBwRdfmMvjgefKlpJgv9BQN1NQ5Zb3WJy7rZlrSC3gb
RkC6DFihYlZazA8mXRGdbrl6x26VsD6IoOqPTLsbs6UTDQAamJCdKaEmtSB4NoTudgIq7uVesZvh
WptS3iGaqgqHkA2JQBhgdtTrvz/6K9HM4RLG+6VjvWWqXpWX0HAnIporGXcaImvt37tC8DlLR0CY
qSFCRUCdrYhJcMhVifHJfYUzPc20w9dH2glHSiQ7q1d0XsuSnfGOTu3wF3Ek0UHLjqQLLv+wfbqf
Cq5vKxQFD+x5stYuzommNUgpvhgo4a2BDl2YibtAgSST/PI0XYrm2eGiqTNR/F0ESx3lwj3/ylbl
ysf05/jbEhO7G7NMkP/oGt6+F7B3JTQPMOBqWFJHrcUOr7PwHPnmDQtDo7PLc4jQdDR6benujfW6
9O22IhBT03ZbL3BvTI4hZ2dA/AYmHCono58S8TIt0C63MEU1z0kuydlAVq+VY/u2OQMhOKkGpaD9
MsIr4AEisv8Utrf7hRxR7QEPiKNUjabzrdU7S84JkoctPwbKRJUo5UBF3xtbxaK3jP1Os6R8tnA4
k/4gwkVJk9ZLpheaOMWgOWthE0VF4tzLR82elrRY3ThLmfr2547xoTBM3XE28ABFAsbYPpfuW41E
eir1v+vK/+8lhXRplQP5CxMLr8Q2306N9oscvGHD//vlP+MN72eN+fUlxCKzwFEo82PGh9I1vsve
8cGvBrR3Ix5KRe7YloofnB1RBkns0tNzUOSmU8ClVU5PWF1xYgPhrDnz3Xi2gdJkovBhrX9bgeEQ
+dPFWWkzkCi9/BDCh1vxzDpiaPhjllShkx51Xl5OsT7KV7nIQxU3ECO7nlHYJDnS9PpWBF3aGhpc
rybZWBop0Ec6eZetaI0umsHIK0uOGy1OEGpmAQJXQYoYVKyBEWgIPLNhNeen7bdCUXpTBiIxUtPX
ej1iw5tv8+YLKIgpYZ750YaZVQhSiKkmTeIfGAekvzqP32xAZfXp9ZrpBqjscu90zzfi3oSkNLll
7O2FDrDsnobLfufJXs2J5THAaw2YkAlOIZ+KD4x+SNFnaK8PdtyGsPdQbEvb4/FqWI411ZLM5Kra
UWBO8/QiaBV74s+zJcfHFC3ThkIjfjwMVQfYjDBd3RXhORbSmdHB6yfPM8184OdB19FQggk0YqZX
LHkK9ppWLqfiuUDrjUu0WeXbjYjw2q5gRZ6BpgWVLBbAaQbqIqSldu1I+8CwSMSpxMBIPtjOn+xP
LJ/yLTecD/H3jWPP41fHWk0xw4R17F0ldr69x7NPWOKUJARMkcu+9Dzery7lIbWCbYoNcOXZaWii
eiK7hFtVf/NOqbOg1cB/6bGVA8eaJe3fLXAAt+ACfqOMJA52Z+c37tml6ePLbvQbH1E1TQTgGfSp
Jc8ygrckozP0fAxGYRTsxoOwoG0+v3N7ni6U8R5IV9bWyog4+Bc1xsQ3CDAZ73MDW8atnSqvPmsQ
x24XRIwQvCpzMzjMDBBZ//xJzGwXxPEwbJ/q7BqlPfWBMVrxu9Rq+lWQesdKpL3F+5ovY2J+ijcm
220CMzzZMTcgO2yY8m2UO+jK0tBm7MyVIiJSkZty1lYCm0IH8Ja2hrNsdQC+YSFTQa/ql/SiQtfK
WustuZzKp/jdzWvbBJnzvxqLvfM6dZYfBb4zff0nkop68VhiOpdaiDMczyh9Mj+fyWbqeG2JyzyC
KlbDj5cFCQYIVjasGHiHrX9uNcuLxtPJouhtHfn82EO1IjSrC5csMvpqlm/Ncj7BX0Zgl3tINyto
mYXM14l3ZngpyM0Ys7yiQkIU+WMLgIWNYXV48IzGJybirEwizAvcF5CbwtfwhqfoKnwTu8j5Yl1E
3Y3MZAGV+K0UwDXlYtMI+a10O+EHTKzCoxZ8UAmXlr9Qgtl04pWwRgMguLJ5QSEN1tz3H6plb6it
5zfXbBr/+rJ1pnjK1Tdn6x7uX+mMrO7SRVIU7+xUycN4pbFtpusyS8pLNZ4AIJDRIGwNj/n7EOk0
o7ZDm6J1lwg3tqHVtZC/u2F9jMZxvTT5WymT6ST9Pc9/WAy+onuoeiYxQDjqDZqELzfN6lrfBvyz
1fkAarUP9ciEpVlyY1YZSabNcVfMqfHluCQce4NJdUhjW4wObjeClBVc+4FonHmUJEbB2/Fl0R0e
klzebuH8zacBZeJX9GSyp9DvYBrcNZM5dlHc2khqlYUMp6gtWI9ghEmbn/Ef4DfBzD1qhYlF6utB
76kKf1qxeLrl8zzVcAj9snFRlL7DbvUf5rzz0+kLqWu1wXacpzlT/JWipUI5/vMhh2uApCaTOa02
OFFqWO5BBl6gg8KnBqTmPaTdXKEff3kBPNYRktcRIx/+DOzZ5MTymDpUVY0o8SuVRKsKKWOvRv48
Szl1scFT/FmN3Ngv5YctoGRzNMwj4cJxBujG9Lw3nDLwGvuZdFJGjUJxeVq5LnjJNDPcU3BhXdKr
0a3g/+84l4AayUM8ne6/fC+agV33iAInWs/cq4PzZw1AAa51fcmBCOl06zOcy4yIIaO7Q7P+S/H7
l+/H5Y+WoIz+p7dpmk39fZUox824knKNCKkiXHs3EL00n8sQumyWCuRVISw8VYzQlz4OmawYV22Z
d0wZqChXEemYyWTKjv+MUUBRxsKHx8n2/vb81cizPfDDgbiQNbu19hfXv604lJpO/D34zUd4UimS
qVIz9W0n5aUbPyxGlTlOr3mtiAUp2JZoyCc5qj32DqybG+zSRHSOf/nlR9xHiLgiZZuP+5Erg+eh
6Z0LEWUWDU9fjdb2W8NXpRLoNdzODdnITFfDbb5NDwamqZq90EzomUG6le33OEMlNi8YscTDLPuC
TS6Nil/7Rd6dmm8WhEz4oWMW5HYqfvNZwLs+f9xBVR2yEQ6xGdbyyFWHYJ0VvvTcpKodDNLXqRY8
jv/uaHROotKQqKlX4PFkGw43PAjcn6jakdwzU/xOh9jOj/jmdno3Cs+u1t7NTJ4WMjSJczr0srXz
KvUURcUDBQ9hU75uGFnpIOmnRDXYvogn37tSHwo/mxpIEnNe1oDcZD4RNtcrVOK2A0i+dX+aI72F
2RE22XyX3Ohchulw1MPXLc+PRc3XxwMvcUOzgiHIlMryND79e1ryjtUU/TdTCDm1VJlL9A2qRyAN
JSN5zhU0QpwvCR18OVbuTQV0SK0rhxKCn8gMhl6nhkINMBJjcJjKhu8BdBpm1iIjPVKWAuAPdnNK
K4RfbCV/WW+Ir0hUazPgItkjk2AsOBT3OmU5Or4b/f9YMP3Y5yj9tDUmMiMytl0wFPniGkRr9LIR
+nT7sMikncssAXAPt0kchPalmRNWKndl5yQpjv2hVbzMxRnYW0yTkXqhAiKehYeEDRht39UktHnF
HG2i7kP/StY70F9QDK2RkgNKDPzkn9mPOs1hePA4Q12FQqMX+LNO8HWNxZrw5PxXkuE74SLgInW+
NhuvOnspS5U/zSXgI3/Jbba9gAqP5wwvoPvK5uSzj0AQnJesDyaC/8xj6edf+nOMTjYAntXdvIBc
WYBlDb5gyPkVhb57nGK6vYKrI7fbYTMDakX3WaOcIiATVBCJ5FkMTQ844MuHlnl1AgPnqs0qwf0M
hsuTwOcyYcCqeu1e62L46hNO+q9IE239cFTIlOW4Lqt1BwHDIhJhMQroE3IZJwbZAxXwO+pSmG8A
l1NqG4OQk5QA+ZhIbZLiefIIivG1EJawt6ySvvUMw3lZ5H3UB/2326LXxrnG7HgImdJYbWlSAMzE
eM7g9aH5gxwVA00sVIGZ2VrOHw+zk4MnkcSWEOsXFYmTV2KMQeNphxHcSmgDjcROaHRxox/g57BZ
Gz8Kq5F752EGXuninPjpQvdK1njgP2oh61cfndD8ULG29tzjO4d8I1GC0+HhCq3K+8DVF9JpYEAs
rxM7G0I+PQg30jNYRkv7X36U7adF30e1DoNj2cprTD+osbof2v4sWJJMdyvXTINz4L/T2DSYiLuM
OIYiLNjudJ8bZ7K6rP+TN7Mr4J2FS6b8PuRjW1wjQcm3NpYPatBAXVgibJMkAqU3Wi8qOpbmte5g
K+uKtbCpfIEX9vDHcDAQ2bdF6ocNEIgjJDqwjSQbEI21FaJXBd30eppxUMOSHAFMdN9RBpPksAtl
XwSFT9+/2aDziHtQSkLdCzhMK3+/EtbKBULElFiFROPmhOWP7NKORNPnM5d5TIJrwbLZhtX2IVlV
21im2lG3dcJJ5avyNFxaKprxa/sOByn0+dtn1V75gLJHVzQqFef5ALLOAG/afD9ZAGL1wFT0TB8F
Sr0K3qG2/1+6MUJfjsJ4aITqIHKlhtp9HZyi+ZfQLRNaq/muZbXtQ/I1zPMAbQnHfFSI2cJqEa3s
GpEeRiLGJeq2Qaf7wwMOXE6p0sWGEFk77WNmH6+5/zKoUf9SxzE7PpAK+NPUnpYiNFCB2Nl26A6s
03weEhL2wtk1KhFB8TOTzGBxCm9BRP6nf4FxMW2e6Uqdra4sXptbvxl30W5OoyWpu5WZbt1p1Im4
g3v4AnMFHNDa4mRZCdKYQK9NzimMyACFX5czMlTMnEg1Qo3oHQLVyULVI1/QB0PT39OUK4P5gxgI
EuZ3HgGmeAIImNAnkg/SelJL3h0QPzDn6ZODZFyA5jcIbTWB9SPagIwwhEH5/ENl2uzNwscQftFn
ecIr7muBRgCpwG5Pu1RwN2rs0tMUjjvv4WypdlKhjqBM+ctDD5SlsnTJesXh0nhZu1gVJri8YU5E
iwew1lLaxbfqv0sVwk2NDpV6e+qa0olJHrSkkHWNiXIid/w44z5YrLyfFnIjdK36XaCnG6r3KXBf
BJ7SXv+3hXh1FepPViDlo9I5LuIjUQv3uVpF9r0H7YeWkInk+QwLsMZfNy4aYkmYY4jHASYDOCuk
R6q/+CDg8k1CH5kecd2f2NoFNalHUYdH2+XYw/QQA/uScoxvxrVIYYmC2XGOrex3Aga08r0wFyN+
riP8du/S8tjEscTZ6VGfHcG0viY9GNpdiMI+sgsRjlS1R81bEZIR/nygiCcNPYKcA3eIbcKIKVny
A6c7nZ+xSE9ZlANdkPeUFovDkOxzkA6ya6k+ngO3R7lOyPl01OVy5L8sq+o9iDNMfT4Gh2i9TlHs
h4wa4mj5LkAS2Kl9UFlw4Uwnqv+Le7+oVsrltGD6lnPVVkF1RhAcSFBnPD3eB4c2UVO0bLkTXKRb
HSL0J099rwuSkNTRnWZnvYU4R3gbSjldkgL7uVfF8DcUEjhNdFwXzlpPoKWOK4NBLhcDxXzFSShk
ye3JimQjVBs8xgfiysgaS6TwScTzbc7tqyEP6mKNJftXMPwNG9Y58jcDEGF2D9xwL0CpwjRlBGG/
XJ+nv7GSfqpzjrwJCy/ea+6JNlkh9ni28JIunLu7CYy9AwarCMwyvGO4PTd2CjOuHuRcXjsYE5FH
CVQQEqzZ+5GL6HmN5Vnb9oulmr9rgjNtNWEGbN3l6tyOG479crwyKzBuld8ErSEn5066RTc5cZco
28wV8ff7Rycek7JXWqYdEIO7T6DP2R1REWE4B7ShaULdzhuENcDHmMyMZdQEnPJL5OphnvO5V9Xq
P2zqBL+ueOPuzU4tuvYobVD6pTx3OV/MYqYP8UyCi6+l4hAlb86gnSBEd3bq+DqFhQUJDeSk3f+x
GtCS2e6mt4MCzqLgjqvB6zKKFUZg3yIrDnHtU5o45OBwjMihT1XHYRTLqEkaT6SdKEouefRNYsls
1wklblCs4mRKZjfwhwCDy0r6Kow2YlFyKjpYQzXIY6QH+dr3mESB3w01dCFaz2skAwM9Y1YIJkmm
MY5fnrpjXAb0ty4oGuAU+Gz6RqjPwtgMZq+A2oKV5Z3/rgYkWyRRM+Ht6EZ6THqaCMlXXBWlC8nA
8PAimPyo79L7+q1wpViDLajtW629AJZYgF5PA4PjZHzhOe1CwiBXriZii9jBhVHeEMScOOULnQ/h
TYS2lOkQGhA52zMbM5KKYa/DKhIA6HB+wbJXARWyNzMPv8UG8ku9I1uI6C45ijW/WA3syXeebDL1
D2xl6yoVL4YsBP53yMvZJNuaRXtTGq2XIfnfdnv3etU4uezeSEWCSsBQwviF6vPqTM9fQphQ3Hev
y087a0sRMVn6p5GX7t2HlWlwdJnYkfVQ1iWAhidIIm00ROxzSdZSZwFTS4GNljwsQQgY0i+DYZ7S
q9vASyRftmmDpO1eDe9WRW59jjZvHQ8j4bE7KiJS8mpO9n6o+squCr4hbZErh9rpw8rDdBzR+z0W
F9mRY8e5zowg7Ogd+/NY6m+YeXxvX6ffvvc/MF5cZu+lOAZqamzCN/0T7FPkWpU5JFNXMWGpR2KH
NlVqu5YSXtkLZU/3Vuinf6JW3qKiViJum+um/fGCJadnyITLU7vTBxhffJQpGwLbMqtIBhBv90nG
5aZJkk5IQFg41ooo/qjBXYQ4aU5uPJ2IP0FHbJQGdV7Sc72EnNzGIAck8WkW88NOpx0CZE0FUDUD
d1gUZEa9zNUfn3H0LaY+9SYU4JGcBDABdU2ErZmIN6Pp/tmp/D34q1rKvY9Mue8xmP1fYqm5FVNa
7RaeBwHvlvjwd/LD/Cr38tL0g+/TybBe6vtM9Vbe5ZOtuAB+UVPOHu/DM/cGsJTe6wOlwORID3h1
m64/TGPVoXVIpiqjOk3SCtlrpw14pxv43Tm59lUacTE3L+5AJ2y9sDV5ON97dXjm8m2QgP5N6/Rk
Ctz41Qj6cannDOG7kMcjVY71kX5A9zjhY3ZcMLWeTJW/vQutu+m6wmaHrR95zchQAsfE9xh6xJBE
sgbXAIsi+K4wa95xDzjZp2KGRPr0wH36HQpWlCdtvYc+68E30dIKeRpCy0QGE+FLSAnWZBoEK1u8
Xva7gLUseia2re9JswnuWHIusnKdt6Lc/VkiTHg1XjkSVkxFoASxfY0YIJUCsQHNCy4F2G6EAwEE
Dtu5l+YhVvZkvozAaF6IjdM3ll69y14+jEqmuzGSe7aqS74Kbej4JFSlocxuQILBj2MAF3T0HAgb
/Vud4zFHzSYpQIN2Fnr/18c3fDE3ExbT5bxDPJ06j6csBb37csnmafav7Dy9NRv35ohcFTM7AuEK
AA98W0u5ftJr6Pg3tqhNyE+MpL+BiG6gHq+C6WZRdE4kzwxeNxwLjibP3qT5bFmBrcj/oMCnupvl
46tWAKmxGae6RYCOoD4T3Nl3zjRFeqZ6u2hHLbxpZJdcA9MwRvTlIJ/Xxpg2tuOgWPsNfaHoBZ6E
kvF+doAUIfRxHpEVqX5CAAxQg9cuvYNeggoqdXBXdNd+JYVun3JVGWh6OWqgd+w0ug2TkegnmtCV
ztZI7DUqugTbYTKhRsGAo1Z7egfKXx/VhBgmvb5elRviORjjPtLG08TVHp9oOu037uJK2slnKO6d
rFOV1rCWOfpFcD4nH2iJC44LMkkKFOxhU+0+MnlD9oNJRm0AIUmN0rkTHxkrSAZaZN4fZLedLwIU
K0ft1RujkeCx1Nv5B9CKaGvpWYzcgZWXZDwJwo5gtuy/3SecVsE3dDQ1pWskHmLaJq09JQ/6DAPU
OgCI508TObAt2PyAIgdHRNUWwNY0WJCubuBtHXPS4RMhof7PFGuPghjkoVgrhRUYTBOyEHbt22cj
gboRUGX+AL2FBeixvoH41W8Yskf5af9Ja4z6zIg0MQhFNgFvcahUK0Uo+8DTbEKyo1n82TVRwoAs
vrlEUrHjDWxLUKbhP5X2ex5hG4kL2cpb6gWHkoB/9srFoOr48eXKNsp7WtfrUOtOvB+4YNbV4NUM
aujtAyl94GxYYqKDPJqFEBXkiBL/ZKCwSN2+PS7J2SYBnp7XgzZAvNQGbkmGABVWP9PPyJCPFjtN
HYC+OMbduUOsDFxkmMFC5B/KgTrQamDaRAaCeBva5a5iTiwwSGfIpbw5zh3/8rn1FfXXQqPWRkOU
JliUM2bxaDyFJKGhBh1R5msMXOp4jeH92ocdZQVmlI4Qmgca2JXdxK/Ei5n0T+1Uca4vbo/pECxM
Kv42A+l/S2LgpcUVg1K29lNyMVeKZPQRixhEzgHEzaDC12MzLvr74Ykomk3fo6ynyUPDIxPugvAk
aBgjyycWFZoQOLWSWYJL/WMhw0NbblUazgGtZeXVNIGhBp7nyxXmMOyWnHGE44GYBEperE5wBfAK
BgtT1tsXRfCarw9XedTi4NXmOL1xZsoV3DNCKFL3uSzS864MXki1KqIQ+U/caDw+AdBtU84g4GDT
w4rCRpnPo40Zy3hu2XKf3S5pef9ZBx2fqbV8dWd/tbXsTKChEL7cBAXW8T6UYumb3h6w9YcOuOYV
0MU7bUBv0Elfo8i7yKFk7nnli9ZacUHNcTkDPIAFObPYj7H2bLQYuVW+LlaI/6an+/DLjQ0NaPYW
xLNOl1hXcmC614fWYuBmj8c4DmyGrALCHRPTqwWwdxVfaAXL+/P+45K5EWujOVPNlqwiwhpBfULd
075n+K9iS/m0VYLWtokmbQMIW+X7KpXqjqJ2XX6OVzc1X3+UbSP6pRl4S4OYjw8KREf6Lmk4vDDT
fvc5NyQID8Ly5uX4C3Jw76HueurA1Y0/G01mfsgjC4A+/NmMf4iJmF9hLclaJjakNn5wE1eGks5A
v5/XOXqqr3BDluagisDrimcojf2DkXlMqyIAIkPl+pOzWVivWjhPXI86sosrXrUjgGcjx7sMDkDI
T8v6Bh5bskS+G7kYi94KPfSKpgeGFRV3bvPaaihNWhO5h/uTWwoRn7yIxOnZ4gbwp5X+C+t1YFx3
OTt4NxjI51ot7OWmxSuh7N0+9j7IjT/x943F2FVZNn0kXhKNAPL+sk9xES18jW15va2ZbyMxebCo
e88VcV95P3NyWXiumn1SpNX0yFdtCvtfhKcySxnh18TfSQN7CI3lHk5yXYl/F9Ats32/xntivRtZ
8vdbrB5zJDSSQWt6PUQ6Pq8IQUhloavMXa279NJGDQio/s930brLfvIrRVQtXz3ZP9Fx9X4LWzfW
9NsWxzgD70Hgb5Ur6aNL7snzmH69NoY7uoxCxDmJ43MKHoxG7sBGj3XSr678KD9HsSj8QMRk/8rf
uNOhk+qMsdEo3SaiebyAxjLwMJT6rjhyn58dF/2nz72YWN7eh7TD2U+xnCIVNdJ5ib9qynE/SQNj
+Ub+fjzDFt/qvtHPapST6cxIu9NRzO8TkR/GL9A3o3vY8a9CaVjdgdNzPuSEe6W+g4G5DQmQueaQ
+wTISpoY4ngsOm00ozUojmlZOEdPlowfvgCPz71F4Ezj4MObMBUB3qQ1H0ZvaBlTLuLW1hEFlblz
Tbd7ygtARey83UzGLTZfj5k0t/Gb4ZU1+Gjkpuq3y+QCrfFWfo80uFl8VYuZTptqi3byyjAw/50a
bvxOQsrwADn3844HwIu22G5xhOkJLlyp6Rg22ZTYp+vUOPW0gHxuwvp/9ygRnTerqPR6rPY1i5aa
LoTqXq+Qs/huEk29ZdeNYSIzD1rAi10yo554db+nMUtiuc9RHVLIJWPys11QxqhS6s2fe3ynxNei
eu9Q8VD97P/QGfba4FixOXU7f7cyqoF8t0ud0mj9GOWvbS8+Md77xzSsd9q1tPHaCcFVmO0SPmlg
g0HnN1Rm/JMwbNE71WbYeDOxbt3mMBdcBfW21bClAYnyPZerAywYb7Y9jXpSgvx4SqLesJJL3PBk
HZOKc4qaQQGz97xYkak/PA1ogapxusfMWlqtNQefwCwRZscfsLoFnj11KciDGvD5Tk3fKrCFWp5x
YyiTCKiILAkh1Xw2x0xAj/+G81SnAfTHBA5PwLIgswOt/H6NomJSdHDWxUI5zP/+jo7VYvSxJrtw
t6XjGxsUTWV1h0ON8P2+AsbB1sec8/Yq5UqwkjGddBwUKHekOxOrwitYoJTgFCfTXHKG1UH68Ba0
gOTN4YrcfpaAib5CWFaA83+ur760je+tNZqyOJN5vrPXx8APmXZOe0yAJUEsyZwB7/4YouGX+jYQ
6cfxwsJpPIh68qlTgmqLraRe/PSsbOY2KMmwv42mID4N8+6UHsMMrZCPbqgspr/Eyns4qTFDE/fN
jwaec5J3CWKzqPJLfCcG0CS8aO8vdtnifpJMqn9MEOT68VyhWzB3martGzM4xLCSSPvMVYfGEIDQ
1xKZethOrLQ6DmcUe0eSNyztdxtZe42szEw4pCEX0ZXu6JSiDMyTSjnwvqjDurMZw2RNb12vw6XL
LyObDZd8HJjd/GA0MGEnvPy3J4sKkt2Zu1u7boihGVojH/Pl8jGtbkl5yLeWyp34ne9EdLG0NhsV
kk6tQQ7BEgScO8zmpqA5ApNaAVU0j6+SBIXA6bS33egeLTBRFHR4sPCod30zTRPIXvi/CmSrxlH5
++sfV8XoOgO2eJOea+YAHguPTHNYvx5YmDdDmv6O/CarRZ9HDR3iDxqids5yVw7F2m+U3okbtczj
Yj5WUbQvYwbg8cINYTn7F9t1RuGZKCoe9UDUV7A7pUS3NJYMIt/YnkTJmNqsdnA5bgvVTmgYyWXN
mR2mgOrUXnIlRkZgAt/onoOFjxYjc5Df+p5Pai6G3mS7zgXxgrwkenA/3sZTCWpD1l40iHQIEJeH
XcD88HGZKUkaK6Y9J1QJrY+Mul5a+CPr+Fvl9wrVfryXZmAVhhy5COrjeLaFIVuWckFqLWN+gOgf
jSiKxWlhaYmDwh4r/ryoX83QQxtKeG3yzDGrCwOPKcwguUa4sNbttbyvsM9bHZej4QLhR52X7ZuK
W6bsK7qEVDJh/Z+aqMxJ1aJJXlRplSx+vsfM1lVRoRvA0RtS6UEROLbfYZSB8iSis/bS0LaUDkOq
W7L0rrSRoG3kk7TiT8dNyLBlPaSDi/EPUr6x8+CnoYjfDrwYqXngohB9XFR5n7hHlc+u87IwB2g7
wuV7rnAhZ4VqESTXsoaH/5nqS+X+H9LylP50znXxwUSBsQSrWazQQaeaqFlRiFv0G+QTtPxeh6/5
2u8u2flmgHEcOIuXWyrwbfLI/NUqGTCG4pCkIBr3Uxn5jaH4XY4+PUeDG18xwzANYLNT1680wTP0
HiRa3mugFUV7xbqJIluVE/aGq7JAmhleWgj3z26IETnxPw68g7/MFtlm/TMXw+hUf/LSWfwdIWw4
L6f1+GwvP909AeJc6wA3akWTJ+XIuHQTQMocN8laSN70MUQyEq/hRRpHeqQaLpthmrP01mdJqtER
XJj+7FOLmnGNs2AnsdP8Gomtw0IfYwKNXnHk/amjm3HsJ8SfwWCKe3Zb96jUg1kccDpRwm0wZfau
WJG4Y6+sZwapCvchgnTfp8rB+yHu1TtUHUfMZy1ntwjko50RxnPVtheM4Y4EVyHsLV/ldq81gJL8
2GwJs+z+96jQWhx4reDLGPX/QYpLMaCMsMOgIK/pSFX2Kugjbo/wXllv4bBvM+AfRfEoa0I9tc8Z
m6g4Z6RfAnWzXl1Lsb0q1qnFAesOG2jjHjA2R8VtJPSIbmWnHPBXIylHnPR9vOhvN2F/4worX2gx
CNH8jAloBP0o+TEGEkhiESyiWAlwvaUWEwAF/qD7xR527dCNclDWyCwUF7oglfGkMQvbW7JoJUYZ
s0axe6e3Bsf/7nOG3dfYz8gp1LzADyOK2P7jslWGQNNl9juB8ZTRwWS//D/IrA78def777pWdtUB
qTh2qt03zg+qcjdsnLofy5eLU0hIT+AHNWRPjwID9aMRO4EW+z6Kaor1aU/V2QJpSw6i9mwRpHFH
Qu5D/VHpYoj6E58+YNYixVXVPfGvrefdgAKxRC+epR4ZcslZsW6OgZ4lYLofiuRJTBzTrKFs3OqW
QZ+xChkKmp8GJMAUe8ZVeKSPvffKZ3HunLuHoct8NWF/o9k0NJmWAIYjQw3DbO3hw1Hp76UviBnq
6Pj0wa64y6l+XdOxHdKlfsIRnVJyWce6X4t54W6B8IDy+TKEknnfhnmRG64FY+2Y5n8k1P48UcUp
WF/+SkEEOzYOtLSNTBF78xvBsn9kd2B4EXIzMHTEb494J3+3nDfHRFQyTuGt1FW9rjC++ieea90K
9WQcbxqGlP4C+ODDh/awXSs0DHdHfO8NXoZtPC9rgm0B2UeyaLdtyx0BG0LMwu1G9wDx3kjqmymK
jw5a2pCJwI0F0YeE9HqZuxV8AXPhjNLc8KjU+V4lZ/FLmKHd6s9HMUwQ4qsSZMv/kTvlPiwniU4j
HZx9OvdOPXRYM+jq+fSTjr27VjCppF5HVFMSlJK6Gal27YCforIs5KN7Ta/4ZOaLcx5lKuS984P/
jZpLvoapHDLzeyBdeDfmfv0vSQ38xktRNKHztf86aG3L2y7Y0k7dnUbW9xdOV/xUMcVTp/pAruzF
mjc99/YRYSomIR/HEcR/KVjR3h7SukzVLj+NjMLqWX+yOfkgizQgHZAl3ZqB7+xHCRIfB68Yyevb
huX4WUtnbDWn+AOifb91GF7bCTbdMO+CUp/EyVH5DYFEyjmdO7IsZDQ3TuFqThevJsT1vEuybfas
nuPVPSzXIgw2+xhH3nu+SvPsfvCZXAoemOxpJL7zhDK66L+gi4WK+ht2oNbUeoBRzaoKJ/aHr11k
MJ7UmHJzQJI0O1Jh07QFg048bssWkj+iICIzLBsvS9inipev5yVt6QJhPMh5KABtlQ1Pc2rwy7TO
MmR4I1+aatpzm6EJl4PXGWDE2t2iscDLMmCveqDRxvYMLQ7boXgJVp7fEo7KqgOgdMMmzrQi1szb
karB3vpHEVVrPqmk6hYrin58s7t2B9cBcl8LSSVEM7wVia+QZQGS2Zdm5cG28jMY14prSfL5BJRR
h5hYHfqN8ilfLeByLzbi9iro+tIVMNXlM19IVVO+Vy9CBBb+OT4AH0sBR6nMNoCue0QbEAiyojSY
JQyBsrNhSjAxHfp4pVA3QasjKThyrlojb4zPAChq+8YQ/f2p0+rcmgXNLQRaQDMPpnqTsmjDweQ+
5lqowZQNAEa5w2n8eRWPXOlgyPGl0QUUV4zDMX+iGTgowwkNZszLuSX2BjJMHDgxBuT4FPZVsXKi
M0PpVlfkSuwEJRMqONiqAZUY9SmfYYx3zTDG2/cZEsCbnWZd0Q5KWfUKDs6lixyzRtqnX2L1qacX
Onq0LRVoPKBVDAsD8z7JEu01M8B2hFZ+w8zVCmAQBGszY22fDoApOEHDyVmNZaW8WAcYgy82ss0x
Ms6t065rebUoW4X4m+CjOsvdEAWkvrh2FT37uh97voAJvofTtXmN/Ld22YNwcwesQP6sUWIdNKa1
uS1gLdye2nWMfk2tRCFLwn3Xr8dBInfWH/hF6qT5ePdOfBrJ8KgLMOZ212tfMqpII1w1wdhNa8wz
Oh27cE6JvB+XD32ohFcapj5Otd50F53n/+Dq7tLjeCHV6aZwOomJOQu1HJME1Ic8Z1rnuyUwwzIw
J7Jgx6pIr0IhyR6XvKCSPlHC4ZhIwo++307vPljrhAtpbh/Q1tY0BIERO6fbsPh3cNEOeMrrm3fb
Wm85MW6nHhF3bzCWJah/jJ0+nKDxeokvXL6HLu/F19O3DlDC/O6iOuYNvHRMZnPS0QEvxiTFpnKR
OZQWYUo5z0Brk0U1WlUHlViAEyFpkaH9F8uG2+UPD29fB3/o3blJ1GC50TUjKk3hg6pEzaX3RgHZ
OoXgaWzZum1Kduu6WJK3PgNLYYvEdHr2MP/aM+Bls8HJX3E+8/j8Xp6LpH1ttqSmYOfFh9TWt9p0
ocflHm4xpzoP4eb6jlDsEFNKew+27iWWw2CCcZ3box6YIqyyOALKSru30+Vo2/Y/icA44A64QwLy
YSiQw8R1W+NhzPOO8XxzRZdTahvJZejebjI67Rk5FFUhrM/mX4w3gSKFXXvoMGM8nnO7meHuR3fK
+wRY1vlDGcePWRPOb9yBGvEaApMHZaNIkzJJar90Tgaa1tMsEKq9ppVfT4XZkjQkVxCMY5WOwYk+
xBBYnEqCkLRFkbY2HZ8+kCz2b6+AfQratJscldvgdTLxc50ZS8ixX4PdY4v7vgYYZpuzC/ZK4/Cm
Wkv6UW8yrk71XS3S9471Nr5DFGcub4kYMBGuSZOf3yn6X0qQWrICqcf8dNg0QTTCfgVL0c2zSMKJ
6KjL9d5KlBBCHIhGYAQp8Sk+s1C2FsyBEYekFX7O4h7Bk0srJoGaabtGnHXa3uQmSCwAlIZ9G2II
Cpqpem/G96OON51nFyIabNHi+U4EinCu4ryXuk4a8C5KSONSPOoVRcBy5XM97QGN2WBi4YEiqdwV
flFrxYDT7DP3MO/ZwWPGkVRwwxK+uEywmLF5eHN8FZQfZ3XMUXzalknyWAfND6T3T/z0qF1+AC8O
PO+xw5W0ElDwIplXJ+32GhvWyeyaX1ZQwNOcVINvIin6eSP8gDLdwWPiXnkdihznC25zGFXjjFbS
iFhQuaUKaOiXfsQdni/zFkZ65F682i9yrgu7mfpPkYy58ubABK15O/UQUaRyewE5h71d8Jwyte8J
rJCE0xNu3JnH/5V7SVhNJbsh2jTW+kP5Jo2whcRHm9DwlyYUHht9m4LUhKWpv/Dz6vWarPSqZTrk
Zcdd4uaQQB0vDPMkso2JB0yzaKjSRLit6pAYlvRlFJB19C4fo9v9xjAGyj6DuoA0rOU+EYNv/Zgs
y58gWN4i05f8SFwRzNIf/ug0exFnTnZEaT+iTd9NPi54jis6CPol9sM2PL2Uc38W5SUMOKqL3ouv
0v8ThFNPMVl7XrqEamry2+Pr1lfwFEOVPwlBlekqMV+mR6lM4CsrIQ+RXatcVL8j19m2zyq2DZpk
v/dfOnHnmS7fR8KwSL08+dm2fwSOqPNpCpOfRYoa1Az+PorEnhwh7ftIgD5hM1oY+m3rZJCyFK0L
F48LZ1qOCXc3RcqU+CV+dhKmcL1HcWnS5G6dr59UdiF8RSptUh2MdgLvO6xmRwJEYznShpOA+gXr
etYBeL6sqdDUFrTxXbv/O+Gikw1G/qReRrJjOwvVXFijCHIMejL3dpOapR1DDmPPyxdqZRgn3crX
k/kCF3XdBOj1ytU2XwyX4UziROvb0DcoVyVPl+VjBIZWQND7dbrTR0kMSGl+78211ORDbsH6y9wx
JHuJCWm4+2XkCujFWQE5qjwU/mZzWWK37+vNfF2u8onD9MYplWSsik2pxGLqzAtFmcmZzfQGfNi4
f4hHXXdk0vQylVd+nk2xTBedg8nDadS5IjoGrWpMU0V7vuNsi4wyZxt+hOAbWsMBkbfAUHsSH/Qa
a850mXfbaVyD8MJVC4wlbu7ZLgldg4cGd7ipd8ban28Kmg1xFYoEQHdU+WjJJ4/FyD/EMlFda76N
97KiIw8VwJfmMF3NPphOzgV8I8QsRJ/L//1heADBGYSPS+beXLgRWmy84UHECNqCiLuUnA4lXWpO
syHV0OXEEJM2BNuFUN86QuOpYNbPckx1xjm137POb8hZcjHqdcb6xESuce+uhGiizavlYWD6aFz0
CVWxwBZDLUiA6Vv69T8DN4jM/TLVjLNJECgKHdBzC9EvOreVJEEFCQUkN+d2ClBXkAvZ9WnxlTPs
FgYy/bVY6xxoTDhmowWcYCBkJKtEbLgYk4yMPjuzQIWH9Y2Entmo11LwqXL1ebKWOY7jKOtAzBoK
p+wa7ZtoLroIn5uWqL2EghbsXV3aJZv24zhyErgZHRi4qcfdXdH9PCPAySN1zrO+yQRff3PLn1Ue
4YoEYGY5EJl6fJFw0VMEfZryGftz6A67MazmM0o1KRXtkQalsZrqsnJzdFPiTPPL3mXUzHyXhhbS
xgwLIsy/FpdZyDeDyerQCgIPqIzlsx17eFeGfd2iHDuTPU+MfKi4Ifse6F/acxeDc8YTDTmPelT/
P4mfhhE2Xbg9ipHNAJZtLgNyQeeBHleCQ5E5HWZrGBrYwGWsoajziP/meWfIHRzN5cf3lML3sIkU
2M/vjQ9u6S6cpBxpD4k87PPNp3eTnLRzO9t2Xr5Crm4T7Dyb1sPyDdI22OKuHsOuLUBFZM0e/Zju
4Xrc/+HElbNkv+QezuDi0Ltmom/PxE/YrYP9+ekztmhiSajCswPbqYyVDU7uy3vbfeIUkGyDUeRc
MhnysipmaZN7Bbf+jv2RKwSAtANcgV57t2FrNq3vuXGIYfZw9dSiXsPfkw2sbxhURCNMgYelj29e
G1YpUFV5BatFDHnC8suvFlG+Tjytq2YVWbu1lvbRRVEIPwPy7cRq5kNSI/4CYSY1sS4qVXpRI7rK
Vi7KkQi/huKFuD8siZe8sncjzH310ki9nKQXyHqGHKRdvZLeicnMiPeIm2RQtXUxEsbLn4OMciMi
vmqmKhOdBjQWU47XQF90DgOeTV7c3CGwvm9ylyIu5AtNn14yRETtHoP1Kjf/ghbxlQMSGWvK3CMP
Rxo5aIsm+AZa1kG4E9lOXzqD8n7miFE+OHODeHI9/Uasa5ynRxE91p4UMvR9YRPV625E1F4HRqjb
zaolcfbmN0JFxBPfpxqbQV9mPToBPWTmM6SnY1e+cWEPSacjDYOUUXN3un7l9W+f642tXaZNmsUQ
NB4HqWMdAou6nc0F/y43t5Pzi3ERZw/BMOtIZ8ZczSPlL9LbGOaBdG9Dck25sSpfWwRia5rISFfm
vs7nLKJYJdcYVFVzp0BwkTrTfVhsOqtcPydPEXlHEaX/qPJcZa8eXQ87bo9xBe9IDejy4g7KCeY0
J85daD8xeDGjmpPtws+HeXa70kzbmEKvGsudgTfy/zjRiuqb3+Bodx47Ow1xKgJZv1ZFLqg7rkiW
iY0Xh4XAzcgQTRb2DZ/TcAvE9VA51wRMcn1eB4mzsncl4D5hK9bCxJBRCaQlEBl5zGK6ewKsizZm
jvukWwpRg0x1qGkRm1mhnzNS/+/D+5cRL+/SFYs7qTCIa6hA1Ck/AicdHW783xhZLq2aaSIG7lN9
upTjTjXlp/4zSUrXwIZmvlrMzR53vMAU1nWAxXnj2TJ0WUK+D6rUfPOsb526Hnk0t0v+2kg+2cnP
sY4pz9oCQ1DwKQJmWU9gwAAEH+eSJVauKa55FpC/GJevsWWXr3j4xNmhnpEUvxZgzlWszogkI7/6
GwnJb2ngCWjCTYcvbqSFI0NNhJnpibiNZop9dJDVQA8A9gOBXXvuIXOrO0JeKUs9FzRB/sz7twIK
dDF0MfyvV955boygcY3R//PJV4O7nBegtADeWCRrSJ5WbRMxMJ9jy/6riKd1ILXd3FXrrlDUy1bT
kWEJn3a0kEMxAn3e/uAz5l6xVKiH2OQukk+qFXUJTlVdGxI/d/0rsQGfRbkB0sPDyrZz3rieDCXi
7pnuo+a3f8nRQ28ci7bQdpWxTNyFVu8MG7Z1wqfUX3vibNOa7hmen00ClP9E6DdUGrtb/0pX+NNm
eR3BJcjLnGCiJVUH9RVt0v9VJ1/5T4/nG1ugfl71sBn+Kh9uBC/2cc7yRGRXvHZuepiJTcoN8h9n
YqZeX0ulCXtJY0Efbah9wDwQ6PnZsmoFKxCHxPlWt9C7SwB8tJM4kOYnLGYX+85gicjjqP5Fd5OT
muJHngSyRg3b/Zi7itLrBCOlCJ0c6WFanHPmdZ7z3q0Hg66CTDNKOJSWMhU6YEk9wPlPnr7LEtE9
RWTtWmV9cJI/A/BhSgVOL8b8PnSc3XPVFhMbgt6+i0kOIVXEZT4OqEdrayPdHX7AZFxmoOSnTCrk
lfQCu3VBspAGe+0ry9bk7dOJuLcQdHz3GYs/Sx0yf5PcKNh3Cep5fOuw0lJGCQ6KOv82I8/mrkbt
YyRMFJELRFSsRaDYDRA8KE4n04JgkhyrHJNxXrgLMFKL0vEd7rLtr2dVfE0VFqzXljW9JOpfkXpu
U+iHSRFdTTcvPe21Rbpd1zbGM/YAjIj/H/AjVrO1hSbDxYFttDPnJaktAAXBrPy0Htiq/ToAR9AK
DvU+XQrAhVbg9+6VOyvSE6b0A0soO18kiCQ/jE7cd6jiUig4DT3EwzWlWzvwgkCsldUN/xbgmCtA
k8HkreHGu6TtBRbiRfKXBRM2i+FeLgahUeyANHviadJCVA5vP4dl6TQXZ5HxR1/E9D9o9ku9Romg
53Fm/jeb9T2+mDv8r9SrsLl40+uEsYa1CTum7baSk+rclTVNBpVbORmXP4Lu/9ddB7mLFEgbwv/m
l14SAxSNIOEUxCYXO5inNE5AXhuTGG0IVFLzzvVC5mzLp8miDAbF7K9D3Vj5ACntG0BxO4WDoLnw
R+s40JNqXndZ/qxVZx6DiYTxsEMdFoJYdj6Dn5FJtN7od4UaiSH0zhS3bTk1FQX5O0joNgJZHjGj
pa8ZeW8cS0vXDp8d5SPG6yhLsLSj5+dNzECZKEOpgDiQLQDEOLElGonvL/4Gl4df1FS1pFQBgj5U
/pLWAaRQ0CictUQNGusWjYh/eU3usFZtpWQMUyq8+UXNSUyw7Uww0eQk4jOsn/JowK0rGVkT967l
2Cg+fHjLFdCifxdCCBX6JRE8tPc2Kbop8N/t3LCISFfy0a1CSE3r6Z942Ain8SPq6qU1xUmO20st
DXOI1R5eaPwZSRzFJ++QVPQjVunhGYhA2SsoGEuYTcf+ixjFUx5YrTkovPSGcq+sAXsPP2alE61f
AWPJOJrrg2JEahqY2R+RRdqbsHsgPHcqzMhxXJ5KwBuWs1DzYvoWFB5C7O9QPEDPcEPvfZB40ww8
Oem5M4JFgXAo/RySiHm+bVenUVStJFjeW/ofwWQedB4e7lJp3k9ZKbmw8qgVc1hubR/xHU6KzpJY
tZqYNGEHT2x4mLCxNUDCvSjU2LLLoR7lUuz8wBJaeP9StHgDA2QvhFA4NN9VwGqIcx8vz+/t5tfL
OFyQM+jSqv8RNXk3zFtGNWs1TrZe4fDmaCDfRo8bqaOuc5IH4msLwQQnTPicGyeFErN6ZgczmeJv
jz/LeV94KciQeUNeJ8JWXAJaEMGeHd4V2HUOzKQh67vpzA5YNPQ4HttMByIj+8RWE6rCtA3q0M/T
41fFnOjYCYpR5pBNR69h8oz3pnThq75gug7yL+zk3cFo9Irx5Sb1kZ1IMlLzeu9Bya76A5M1jIWF
x56ZK1YhVZowOk9MWcAAjtvpYvkcMU+Y6BFKoAXf2wCz5UgxpReO+7NNnTsxw39GUpqVxaDZyb+y
Ze35pDGB2TwuFXGmhV3tK9mACHgpFY4xwO1tBRDimlg/S6OoMXxcd32aXSFe0mOGCdDhrkcYR6Ov
kXI5BZYhX0hzZ1SBVjtZe7APEKMi7Ty1/wVJ/V4Wjg9K1rTpggU2mC8YSB/2EedG7+CtqUx973ZE
OoYT0HHP94YN29RarTfrkfQ+P5I1rF2AJyiQZC2afcIs3F3srsKn3l3QVhzXRYBXDQIDvJTXoAUK
dV7CHsnO8LZvfRIXYhUIAYpBqJNjbRL2CwiqjDrN1biepGDJl5W88x/KOxhgU3tX1vnSlnpWGDP3
47dOdu+EvKdz8ncOEZaNSvrMssFSLw/Tvfd3rr5rL3x/me6TyqzZxfyDukJ82NWbYxPXFjat/HcK
6t+VGqiv2xyojklf7+him7FOx4iuVpm1T0OZTVXT0ZeoKmzEuB+Vc/ZUAqQOd15zGhYJWpCCciTY
7ePNQ6F+3L32nM8ak51S2jsd/04obs5k2sowQ8Wo/p16SEMfXpn2rqg3eEiPNiMDbxIRQZnpm5WA
Df8OLSol8cS+sT6/q1GTe+dZc0/h7KVX9e1RLkQtQBQP3BxNsban2N/eRlyOnAPdLZFQXiAZ7r/i
qx3sBB2GTrrAbPmYweONAT9dzw/yTjxzIa9HTHPbO3qeupFor2BdXzCbATNgIe0jLbYeml+zUygZ
4wOGI3nXTKK9CwCFdAIuOnHLH/YbxKwWS6r8jDm5HfD1dMJyuEka1bW/MI3VJ0F7hCioABynOvMA
ZZepZwStrgKiIAqvYeScuYlurRvzgbXqrQEIvSZiociozylsmrzyBi7M0+XjcH0/+hnukYIamub0
XL1LFrNZwsP/WqYF39Eva7VS7X7b5mcCcGhup7mGqlRW/LVS7Ilbdo0RsGmwaMRUBw2QrwUf2XvE
0+hWbJIbwNusejERq4Inma8p4asGoR1yo4ir/rlPHqLRih3XO/1FQ1MiaIRy8p8RcxsavQwaklQ1
iTgKMYe5118Qr1u4MShC4qSFO1vvLP8xnGl+4Pl3Di5iXqe0Ri1xainlOwKfHYZxSaaK7wQqylHC
GcCdVAHp4F78EkFQ65egv1zn2izxDvG/uCknE9EAP7gsg5YGYmWQ3j79bgpc03tQIaKRO5wt/AUZ
Qyg7J3Jh1RU6U+epWLvE7uMrjJ9zyhtYNZ/1kFW1ti4gtYBb6evRSMIcmP9XgNqfwk7ABsxczO6c
vKrGLvbVpkUWrvoRbDVAFIfaBqjO7fVuQ3XSOdl8gini4hTaDHEBbiGyQW+K1ykEV/f5nkJx0ZEQ
Xwq/tRTVt7lzm8m5WHAeIPTPaRcSNZPiI4fnFTOcB48gha3H7z9Sa1RylckIc5CLMX2ZXfZrK2na
kVMQckUKEOfCDkUarATi5BPnO8O9Y6NfETbMYtip3RGC75ntrMHNPJ3/O3ZxsFI5r4E0OYWO6Gf5
az5KRIN98+VR0Ta6vx60oJnv9fzjOTcPuahUAebVOXQhfwaitJbA9e+orxqzJwOXPkVnEDMnfsrH
iuO+coW54tj6319fVERFe4WnWFhZfecCWQGaVcgGN9CzfyFUPcypgVVmZUeRCOtfXJ5mneO+LC3H
+R7PE0rIv+b4RGnKE57HrLWlUKqm6x19Z18NCcRqncTNL8Cw0o/b4+jnIdezYfLDkQqPsW7xMhI6
VSAv8/L1fuylY5lAMskX/EZjAPuHqfRDN36/slp8H+7WaiWg9wwfTVTToVHG6DVHNPTlTc8WAe7h
Hx7f2rr9EEVzOXlRdg6x+OvsaLsLkGDQQvg2Djjqm0H53K9uOsSQhlRaq6+YpPRORgCZg6HLiuIg
R3dlOAdjAFtyHuofU3XUahEHjhB1yhwRHLzFMQUm8H/waYofCwizFQyneiqiFjCcNFFT3ZvruF5g
SqQ935MZue/fc1LlrxzqGyH/zDb/SC0QiP4xL/KYJITh5CwtplXLENPiQO/y0KQDwhL7u38jKyo2
ytrdhjUfWq95+iidM5mfSKGZxOo6oTIy/FUutAEEioZ2GpM5FqFBYoVeL1Te+uPj15jFrtAbe1u5
0hiBPB1VdVIpQwQDwmDLIiBi74BO0aWtxZpGa7otR1aKPvE8BtnXKxlpTlCcGxyUgSQvIIWke/5L
6CeIs+NOFm59qNeuujJc3MzULu6rkz4T59MMi0KAyfiUOfvi16KcBj+tk0eQc3Gg6d8aMW1aJzX4
FNJ5KM0TjnodNu4g8PVupCvNgTeeizLe8P19Eyh7WEBfVGnQ0uDkNTYtdeM2k1b6rfLrBj/bPspI
OViIRwWarqKmu36yquoMslunfg9SwDoKzP4rm6vFKL2WHwJS1QLTkmFDCfO5P9qiDJ7geiuRmgzk
J+eyVI9lSBXZt1Q0Padnwx6Fg1Z0+GNaqMZwgKciv9sYK7pV1hnYA4hFhMM07ilbDxizircuYPrj
kwz8Gzl587bHyTHbqCTlgMWICGmtSol3ELOI1eZ9U7z4LOEp3oFeG6MKMw/UiLXMgN2SIBdkKWbi
CY1B+PBGabCwPM9E9pm19C+5us9rMd87+m9PgZgnDTtSCu0pnxjP12aD5CnWbEslcutLf1XKCxq0
JKXBD3PhHgLGsGlSPLabOG/hBY2aQhXIdTOQwLDSx5rZMTtt6/4jhkGtUof0QoMppLmqbVKy1qqM
DuyACE2imCYqhM1VDL9Y9wPZIiyatbPs3Ju9ndRBgUcfR7PkXhgTCcMrtmSeH2j2ff3vWEiIyKzA
pKEjmvmcyr2+8kixc9SHCRzhhT0XriqamoYDY0JaHXcwQaSqVgF39Z9HrBkKqJH+g+m6gzG5l5DX
FzuiFboW6IIqSb2SeaXVeE3fZ0YcyVNT3r+HceS2dRlatO5nwjyMQWzkN2st+LSnB8zNjpx30Gfl
hqMUBw/QWWjWgWxQpaVTJzPC9NF4TJfbO+gCSAIA+6EhpteOQJkfMKoBXBHqLka9wcq9+kSHjs1o
lefcqBCOPJDrYqmZB066u+ijhB6+/u4mWNwIDcbKXKbvw7qLfLiCUUkw1uqjvhBS0Jxx1Wp9Np4x
qlE8HF5aBTKQhAj37u1I8H52J0cNKlWE1Q3gSTb79uZOp66U28HR2cnwizDW/JcYDCQAZknNywsI
RKYFox0XDBan1s7tvA3nhs6Qw4s90s1vRER2lPKxQ4ADJiJU59a2QE2gH4LwjFKtj4K5nfg+rvuC
6qjQ0TJrCzMhUo/SDN4+Iah+PCtXzJyIVCzPaqhZ41aYNjCxRHmwGlgF5HJxs6b1YQEVNI+iisXV
hUYpICBv8tFszuR7J8peWJb6PVfRRg2wsISmOnAqmlllH1+NmYsUYbrxtKkukw8FmQlTeo8O6OE1
phXdmSUziTqjsO4RB/FFhm8Kb0oWDCZjof9w/9dA7LGZO06skowbuH+nh1FlflAATSrravNZgBVw
fLg7uYuO/h9kJgAjvHDfr8tg5dWXUL2EcOrk/rdO+B7YhsaBjHxA8hm1M18UMfvLGYG+qNxPFQ2X
4NI3JNuxK1G49e2Twak4mAIEzxxs7IbkohA8vS/Omm9tiL9eIowyHNETyrJXEq7Suo+ECYCqSP9y
SCXgdcC0FHKrOw6aeD8R625wed1dkyurSxl/OygR8Or8VVmhbMQBs3CNMSV5+/LfPk4Ju49IliNG
vyHmgb98PLmmqVtSvcSH9GjvZJx6WAMSAH7Uge1Jx2jlz3fx/BJjaNMqr70Xki3/LycDF0FAmP2e
JQ1HTb+T8iqnKPwR7jEFxcheeKpthRqBFFODtB9TP2EqZAv5kMR2WD1gWT4wVfK54G8Pgu9EpwUU
WQ0kLa3evr46mgqabvtaByOvz9nTIpozzrlET4/v1ibpaOJM/axi5G758c5r9TTYZhwwDUucE+tV
q1ES39+WNLISZzxvpel0MasW1ZS5enFZ8SGhz+glCOdaw6sU+kz3nPONO9Q735duzWxM62dLxQo5
JIGfinwYGquIDLfujzVMQOqIwrLvO/zfo4tjkDNfIOu/ljsgTWuvD9sqzqBDEDbFLjSf3k/0Whhb
yaWQ2zmFVPIAyFSnW9BKC43/UC8G8SDbsalPMPravlQloNnQd8Yxwy2r4dO0rBnobCY5ZqOFB714
UYtGmyjzyNu0zHjFHLwuRRkD3ORCesW9GnNPxlF/eKqdDCIUXNAEnNHZWXPgh2HFyBUZt4SSTxBD
Q4h6TdNjlbX5bysQVeuEuIGlfZmjfvCafYuHjqOf8wDFSrVJ0JWXpvYAsblmooLbVAIP85f6BP6Z
+EDuVkowYLi8+yv6Qh6sRYMwxqdcjTd49ngoZ94y1C4eS9f+pDkqGVIA/C2ssX9luv4d4eHTAdw1
cC7YLHhURFbKWuK+hmv2w5XPG2T81T+L5eZmQGaPV+GziwL/v2LO/oywY35kMxOYt2HrsXRwgfvk
7qB2iP9SdKbuPakkU0hyWozaZYWXSD6zDQFe3qONiWOZ5g2NjAHjSOZ3Wrd08JFq0T/SwQWAe1DR
Qg5/nlzqERFW8KhjREoE0xYV8O3MA8fRpB4kNsHCP0aWb73qJyZJ49nbbkExyYoUq+Xb775CLv2c
ZHr6Lyx8j4btxfcLoCTC/exuxeTo8VJ3VyokuTNZdSTNsxlXtxdIy+92zAoat/DsU7BhQNaZ7Wff
NnVe6KBWnIH4HjrPNPuRpONGAt2ohSAlz8ZZR/6ggm3seAcQh6QEK+TbHH3i57tZ8aaZx2fLuTCM
UmXOOwUCUJlfKznQTD3fN65z7y2Vo1Bn5SIHQ7ARiwTZn8wl/il5yncamS/8++I6ZG6wl5IUFupo
MTI+Vz08EHC3YST4NZfPFYdSzooYRVsvXaFtKxUrfNBj/5Xgvo6SukBNwJ8R/vnKvB5CnRx8OG5m
RQanTNhC/OcbZ+vlazHYALdVrByiBT5Vyb9E6B1slo9KjkNWSnA4YK5lXVPKJj8KAPgPdtDSu43X
Eia++cSigK1omHToNsUZru44gP99YwKQ/p3zmgYzco+3tVECbx+36z8qjJR2NZZx5FdTG+kbC5eM
2nyA/TjzjBUEkKgVzQFilZp6BqRulXAnhNkP09adtezB3/l6lqJjDZ/NE8VSEQx1Oi0GS8iJLUzX
3dD5u73caMkNTHVzIhuRhIoBz8NCMxEX8gfXWwz9oxzHDUccYYrXgf/F0wUXH5jHqQr2S/JMK2lS
bVQMsQwUkpv2vYbNtHqZRooeVKC1sEhKWjX47shQ3P/PnfWeg3D3yrwo+N9zkxgCebWhIbc/K6NP
maoZCafq+JK9fsmciXfhDy6Cz5zNEx4Ih9AJbPHoeUkimXlAheVT40zE+c8Td1M5K8auW7q8PFl/
ihTBZqUbgbwdHVq1ipUoHrKWbLjSUiRJ+WKbNPn6bYLx+9iZGVwcB7Z88OKRQ+9QBhT8JAoVVaw1
Cip1lSaBIls2zJiOqgB68sn8QaFeJjcUe0i+sLgObE3ijpbefnURtk0ZeVsbjvSg7cQwp+kOKUUN
n6VTg8k4dBv3tWcBlHuIx6ePKa2BX8dTf6hiyZYHETvPc8C/6f1gak/lNkUVQeR62Z+916K3j5vH
6l0t0MslcDFVF4ChwnfNBHq2B5FrDWfWYF5PSDRau+UxUHj9JI5HZ9rCa4ekL8edW4HtW73gIFJU
Tjq14aufUVcEyGYq/f2Yqa6Y8naWYbXE6zBCNPi7oB6BeUgAYNPQRCXQnHyvvNgibmbHxgvJMCRY
mcSCsF1FNl3EhvizHPOET2JQlPFj87ZEzjrnNVUb3cyzfsRI9sGn8y3sBNj9iiW4iRfPurBpaDWm
Dt2+rTr874c7PlYQ/H/AGYewO4PkqG6kAIjPPdAWxz7rzjUfUPPCu0WSsy/auVAAJCYiTi638B44
VyAtCY7JoM/m5eVgAMajI40Vw1vlO3c6fi6P0n3pdaGNzGpfMNkMWJsNv7KclGvlVROt0f5Hbpb4
0PM+sFZDgB18+MHq/F8O53i2QR60cFJrJRUMrSpjqADbe+H9UbaSSBrAL+WSt+5aH3NqVlPZ75ee
ywCshe1cF7x3IVlIQEGsK8tzJvgjg+cldACz5z/viVuA6lZIrdqV3THufKdRSIywF31p+3gxjcdn
AY+ugrkWd+gKelm8vAbSoUCfAeC+Mq4/YPyshALuvO4WxRZqSmid/cODCoPO17u/FICQQKdMAcnJ
FzGj8KGIoZ3Heciy2Idagm5P6mC/dUcU8ORJngagydOrVAJI7JZWPN2cp9X2BD3PgDTxleH0q4NQ
NISf+hIo8qytYur8v7MmFZg2Zt03DmkjgukKj7adWgmVMiWBADYaOPCtnPqIxntUH9bNebeCCu4U
PxQmwp0UXQbjiPQa7ymZxe4LDb/ssn425UTrzru4ZUz8TxRvOerudic+K2NqrCf9XNGVBwgnPZ3u
SaSqxT8ngl6v3bAOi9x0Rva0V/3zQ5eQSSFtGWNGF+54A0aRPXA4F/iYi6MXbQWt13PuWzqmwZy3
dJyggHmT/qS/fp2dv0sMmpkz6lRPoPUvcX8LpBqZFjXh0VfkgW8e4kLU5sPifgkTarsvzBFICtmz
oDQKy6nPQTyVF4V2nhP2YaO93gBo3iCVBX4ZbXZFL8v/BXJp1T10s8kb3y3mui0QsTiucbisD/7B
Kj9DigD//4CsA3ajWYKJtzw/u6e0UWJJscyla65Jy0Ctz+UAhUuR5RNfrbTrziY785whMWi9kaEO
Q6opf+MmJhNqlUZ1SvbrJFcZBYpHwPLwLGMjzpKLXzb6wlMeQqOWmfJby4z59gI3dFhwv7BfjYKS
Wgbu90kPFrYw7me3ar5Mmi6wowOs9+Vab4ZpVgb5iWP6bhMY6++Gi5hrwJXaOyqtQIJJbYZyZQrx
e2BB1Adr+GH/tlcAYqa/tFtVvKL8GOBNMjtEudmpmtVjnZk+y1KjqAaDd1TWYcufoGZVvjv3U/QC
5IyjnFURni8gLPWpUKFBD1dsuU5/24xNSQdqSSOB8S0itwzC7kCsHb/Y9H6rDjZqtW0AVdvJ0wZo
dVbyXCX6oB8bQmLWPenTOsap6t3Zocs7VNVNLuNQM7e4uAVDiuwDSwFQH0Tz+vBhsUDNn1y4qmUa
DAEpK427J7HBgwTXAlD5QtkURFS8KCFJkZ8FpN0p7O2/1qihz9srrigoOLeCZyX59N5PztL010a1
9CNfe84lz9xyJ9BkbWcMQoW7LVbjY0byDnSUb2WG+6LqNX9sUUlCdgsYFr61OlN68OXYTqUw/DKR
epdIpa+2Rrlsq2JQBHEgxcdBylB9vvfeGps1OEVvtBzJe2oEjgutj3N2esdi+Gl2Dyd/adXgflRW
iSS5Ai79i32TWHiRk7UXlLzxDiKPADNjHa7fTisChH+I0hmDJd1J3PT7NDKhUOMAdeACAs3zWZkw
PtAA58U6i3YwZam6ZktUkE3QkCBOFypJbMJtEIy4UzeXYzlXc1XcqcmDFxE2IA4TOAJxIKI5CmdX
p7XURy4izbCTJ6ojjnyuq+I7AeTym2vDe4GMXBoCzdd3fzaWEPCVxs1PWcO9q6y4JcnGFyWrj/8+
eKooqmaYImp/+dRVY0b6xt8pLXEJsVb0eLZna3iPhQj04wwlvSX4xtUD/2yYSAll2QOja5IYrCgJ
gajgdct9m0oEvnI0GdRsGEtytVKP0Wm8j/PjnoFRpdFYiLIsojUg+VWdMC+YVYcLvdjdLdeiIATY
171SJEUMS22b5XP6pSAnhCKBvvVEkA6EyAw1ITH7myo1c9eoOAJpbz3I8edBcua0x9vtcmnOZ/eV
XglXzb/TtSMdRCVwfSsWrmwl2J0fgCMJ8aUGTTL+h6pfzqOM4nURh30E9qdFQmsKgwSd4cLdc7mT
49AgoVmjDISr3ASVEXpzA+7HLdhNEo8tBG0DMj7eFl56DhYfzbp5i1vxx/cOsKJEWEzxLvDKW0fM
NSwQ5l4QlV5IN76Yt5AX46gpLoMjLGyfRdYLlHh9LpyaqFGxzZuV0vt/oz2CxKTGHNs90CdlWnzI
5zrOFajNL9K5Ts1MCjoDqnvM1cPagKkvsmStNTcb2T9h0FGlaqa6BTDXYj71AvKp0pghe0rBA90R
5lt4QSAqW2Ibh9XTYuGcyjknItSUd/2zEjfsu6r9aZIYDGTySAJ/yPY/2nvPnLwqQuzDDmYWl/Fn
MpXbUyzVQNpV02FASyqG67Mjkrt1+r0DnyNtDJNjD+/zfd7gG6z8NUEQ39Y0cWN/JfTy0biry6XP
GTVllGxXHIlbwPcsBzHfdcRhYlZ5ucDuKNUOdI5CvLtBI54Te+XGXRyhiKf5WNTCHunGfUChGjmV
R0T11V9RC59n2Hz97vD3HrBab/+0EnUIRv772jI5Q/rFMrA1gEB19Jy9P8S94HCka4Ua2/3SI9Tu
jOPcZBwWuV/6M7hA95oBeUdSURUlTYrMe5gEr7mZG5qRUqSDj6tBbnZmowP2a9vj9xO3OpO+ULUU
NzhnKQObDYQp/PO03yUL5dN+zEzLOImRDgjG5CjVLT5imKuI3BsC9bM0qI+ULXeyQYOlnSkfJ3Ao
bPPbegW2NbEouUe2ouc9yz5AQwptiu+CRBTT51M9Mj3gc/5fDiFy/1Mo98oXssEbklC0tT+2pG6K
MLwKCdNDxqQg+DJQU4JYT51dT2OnqtwS5Yf/MK105ac1yrLSiM1eGyepzonBC1VpapylWqTao274
n6KUZZcMPogUZSuTM7EwJzwASjHhnWhwQoeQe5yLn5r0bgVOvMHkkNZYc4h2G08PZ+St9N6tTaH2
tvwa3RsdgVY/SfnnUv9J+/HeqqsF2byxuHsyLDsVScwb9HM6FDzyqmsLsU1Y3kemdkLo+eaBV78l
ZNBHIT38Qn/7VMZ9DNNy9BlgiZY6QHSnVMtHVPRLXGr2aw7WQUC7Gonjx6VJeQ7HU5JItVlsx45Z
+RWWr6ipRP0bvD1hc7+oFx6YVZvDkQkkGEvhUByFoR5NAQb9RLv6SVO1OBXgQNsYPp6MfteqlyEs
heasZrv26ncTeqRHDHv8ZGn4QjmvxIfVDuVgLuzk0aHwZUHXaRNZR5rCQDc+AAqEIcWbZKNRrxST
62HiameZyKijVpdrqroHyNd92PJk3KQFQAuMQMGtlFIKRHdnK4F08fkOTpk/6Pok4IYyclZQZmJv
pXmu13Mg+OQNeGjCcah7c8ChRxFALOVoEjUMu6zZW1y4xCdDlEsUJiXgTDzmTGV0mZLDh9sLKmHo
ocr8vg/kn9uGmAtojL1PG/S5IBHRGO3/nIsgZDZNmkupbXfaj3snOOz2wTfJnxJ2+CZ0bFCZp+Qu
eg9I4cBPpBlazcnl7+i3XRQdh1ulIpMmPqW0hk7ElGCYN0XxVTtszzAX42EG9ZmZRh/S56y52pg0
NOacAa2u7fjjPbgWh4k9nk6q09ygpkCQIrLq/h0OdNj0zre5w02APxuIjaIcA+C8SiYpuUE2Vabm
qvPCZnGaKC/gWyGCy3mKLZbSxO1tlFYX+bK0tcTmKzRSGoI9ahe8eak8h9IqIdpEM85n19nyYRrm
oTHkSZepl3RrpwJlKq7/XHf/B3crjqhKXJloB0j93gSc7YHby9Bb95l0MFX054Y2fs9vGwSqYnc1
fA282unN3oXF4XBGm4YZIc5Bpl2uc7jruAXIJmgFAk3bNXRBjQhOzcV6eKVo/zq/R9616muAdLCQ
CvRBJMogUpUTfKY1SRkTfEOZrYENBm88M1rivYy6bWdN9Vkjjc5LxfnizNP541BlNzrE2eSzVBw0
FwYcVduFqf33+yZO/X/V1+qxdJbf16/JuvzRClPPtH/ZP5oz1m6R5dd+oKVtHcqiz5ZrzSeXlFEU
ygioJoGJZdy1SpM9Q/KVkgq6BmrJw+NXByBb4W1lECcjfNWBlYs0f4iaqPM4ckUSujq1SsBOACHj
NDfqETEIT1DJuzgLq56lT+Prxkgn8qFk9zSTKQBvvvBNBFZAdTfh1xj6Il1L8KZlMo2nIzIjDVI+
VtJ86La8B+WPV3u6jejcmDCX44v+tbCgvkFQv9luhPBxNNqjpKB5pitooyjF24u7Rt9YNZcugVLd
XDgdLlbLVjb69TX8zUz24+DwBusAZk8+vAvFOa98q8yJ57ZqNxBVHexAjNjdthnR0mVYSNlssFjd
JxbPupgMd5vZfA5LlJ4yjULRr1PXth7jUFqiItVqSb5yaFzRN4nWGL10ot+siYv3AaSMGsfNV4K9
Iu0yC5htOU20Owzz18y0cjZWZGfSwCSwtl6OIUS0dYcf9d3AjYS3tLFDg6vL8lWOdNuoZ8AF8yMm
NdJcGopr5DUrGAw+EBWRljzf6LZIuj8v5cfLM4/0MNcASJ0YN+691QKQ6SLKpkwuwjetENLza2ok
RIlYvjOFKG44LYYN6lFigsteHM7S59PA0subWxnLlb4ECE0Efj0ODKOTmx86t4n9pBzKcsSxpcTh
LXtd51XvZR75Mr9R86bQWk2ddwtbGMub5AMN5R2nSaR8VceQtWVvghFxQ992nQoMOyjuYy8w/Nii
QHgAkLgBY0wf/u2Rb3XttReE6GHAp8Pjcsk08Plun+sb2sBTVt/ZmvK61wrEvMLbf9Qj7EndUNqV
JNwC+7Xffy7bMuDp3ElfoxUrJk1JzX/Ip4Yt5e9ckR2Ff0sg54F6CrQBZf5ztSfTLvwdZc8lh21w
E1qbBJGLapZGkha3/5Py0y/ffPc8k5n4yuiVS8IDkJEykEQsQyg8XzWnNkzKx6vLSfxOeIgkJqxF
DX1qUv4EQa/wKRkz/ZnAZHbppDwd6L5nZPAu54kETmNDJU/Uo14bYos02onynB16OSJu36nqyPRc
N2oxlX1/nbLTX3qqLHPcZXl3/6Da81ikagpkCazZ8xGsiM6MHB8Z7KPgNb23rId82FhpNkvyt1Oq
M3IcGmtcwW+fbAuGuBCXvPuQRwkEiZAYpnlfyKcginVl64Wu9tLibL2fTiXYdxRXB/0mmnkgblQL
uIUFtZ1rEVSwxfNhdqJ5+DY7tHCO9aldxFBvLPtiTcJLvhMPHeVnqe7ImaxStILgO+rmZN5grTYz
S2H305GMPXk68JBFBIFFSx8U17x9B6HJ8TvyjMpKyoTHdmHiJGgSe+LRFJ1o1dtkLyCkYwusUoJY
OiqvUoTsZxzOuloi7bid1dE2A4MqofPFiUcNo6x7AWniUAfGSGC+HMbShbFUn8nYZrBqPPYAsaEL
9hjeUkDpFtla9LQs2jGc48zhZ6vKgY+FN7QQWr1EpJJd7bj4FZUKOiLu09T6ai1BkvyEPVv967n7
rax1CM8hUEA6WgPutdHHiyuSNuxXCU7MWpllpu+Mv67k14mTHtDEmi2y/qhEnF2U9VbE4J9w0vpe
jE537qGooFAPjJiPbqp6H1BL3Iplxpty2bBwD0RZ7iAoK67YYSenmkcn5zLkcn6oxkH0gtCDATjo
FTqMIebjlcdFwB28cqtDnp9W9imX/o3DBw68rWl3DTV+6QNGdWxAbE5ifgCkpUUtvUc/p1qifnuq
zFqB5KngFuYWyPlZMgYLPcuuQW/+mxeirD7kKw2jCcRQqm98D5B2Tc+Ta2ytFRfll4wqGS1Q1Mjr
3FB69Az4Z36GuDu/LX9rAl4d+Euiy57+whkzebUAKuZXKUcXSRVmSsVQeaC6Q94zBnjZ5xyNlGjL
Xxzv9mwpmYqEts+76mRwIdsMW6RK4h4N7b3dZhJdnWCqNB+OTZoa9xPuTiA8NCBWPyr8gcyFIDdz
QbVle+hYLAS53Xo0lU5tctCi2ie43i4BGlLYh0oxv77+4RtbEAzXCDC7+wdFyHsjgrsE4VIrBKyn
7xuGBgO6voCxVeGjjY6Pyf5DGBGRdZbz4VnRVIi+lmNkvUtjthfBULRuJPrYmetKmg1zrJ8mlqDk
35nMK+DAyj9kLus9vVDqgWw69w5oKIrKD817XYOOPDuiga9WYIWN
`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// MBT 9/3/2016
//
// note: this does a reduction
//
`define bsg_andr_macro(bits) \
if (harden_p && (width_p<=bits)) \
begin: macro \
wire [bits-1:0] widen = bits ' (i); \
bsg_rp_tsmc_250_reduce_and_b``bits andr(.i(widen),.o); \
end
module bsg_reduce #(parameter `BSG_INV_PARAM(width_p )
, parameter xor_p = 0
, parameter and_p = 0
, parameter or_p = 0
, parameter harden_p = 0
)
(input [width_p-1:0] i
, output o
);
// synopsys translate_off
initial
assert( $countones({xor_p & 1'b1, and_p & 1'b1, or_p & 1'b1}) == 1)
else $error("bsg_scan: only one function may be selected\n");
// synopsys translate_on
if (xor_p)
begin: xorr
initial assert(harden_p==0) else $error("## %m unhandled bitstack case");
assign o = ^i;
end:xorr
else if (and_p)
begin: andr
if (width_p < 4)
begin: notmacro
assign o = &i;
end else
`bsg_andr_macro(4) else
`bsg_andr_macro(6) else
`bsg_andr_macro(8) else
`bsg_andr_macro(9) else
`bsg_andr_macro(12) else
`bsg_andr_macro(16) else
begin: notmacro
initial assert(harden_p==0) else $error("## %m unhandled bitstack case");
assign o = &i;
end
end
else if (or_p)
begin: orr
initial assert(harden_p==0) else $error("## %m unhandled bitstack case");
assign o = |i;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_reduce)
|
`include "bsg_defines.v"
// MBT 11/26/2014
//
// bsg_fsb_node_trace_replay
//
// trace format (see enum below)
//
//
// note: this trace replay module essentially
// could be used to replay communication over
// any latency insensitive channel. later, it
// may make sense to rename it.
//
module bsg_fsb_node_trace_replay
#(parameter ring_width_p=80
, parameter rom_addr_width_p=6
, parameter counter_width_p=`BSG_MIN(ring_width_p,16)
, parameter uptime_p=0
)
(input clk_i
, input reset_i
, input en_i
// input channel
, input v_i
, input [ring_width_p-1:0] data_i
, output logic ready_o
// output channel
, output logic v_o
, output logic [ring_width_p-1:0] data_o
, input yumi_i
// connection to rom
// note: asynchronous reads
, output [rom_addr_width_p-1:0] rom_addr_o
, input [ring_width_p+4-1:0] rom_data_i
// true outputs
, output logic done_o
, output logic error_o
);
initial
begin
$display("## WARNING: bsg_fsb_node_trace_replay will be DEPRECATED soon; please discontinue use (%m).");
end
// 0: wait one cycle
// 1: send data
// 2: receive data (and check its value)
// 3: assert done_o; test complete.
// 4: end test; call $finish
// 5: decrement cycle counter; wait for cycle_counter == 0
// 6: initialized cycle counter with 16 bits
// in theory, we could add branching, etc.
// before we know it, we have a processor =)
typedef enum logic [3:0] {
eNop=4'd0,
eSend=4'd1,
eReceive=4'd2,
eDone=4'd3,
eFinish=4'd4,
eCycleDec=4'd5,
eCycleInit=4'd6
} eOp;
logic [counter_width_p-1:0] cycle_ctr_r, cycle_ctr_n;
logic [rom_addr_width_p-1:0] addr_r, addr_n;
logic done_r, done_n;
logic error_r, error_n;
assign rom_addr_o = addr_r;
assign data_o = rom_data_i[0+:ring_width_p];
assign done_o = done_r;
assign error_o = error_r;
always_ff @(posedge clk_i)
begin
if (reset_i)
begin
addr_r <= 0;
done_r <= 0;
error_r <= 0;
cycle_ctr_r <= 16'b1;
end
else
begin
addr_r <= addr_n;
done_r <= done_n;
error_r <= error_n;
cycle_ctr_r <= cycle_ctr_n;
end
end // always_ff @
logic [3:0] op;
assign op = rom_data_i[ring_width_p+:4];
logic instr_completed;
assign addr_n = instr_completed ? (addr_r+1'b1) : addr_r;
// handle outputs
always_comb
begin
// defaults; not sending and not receiving unless done
v_o = 1'b0;
ready_o = done_r;
done_n = done_r;
if (!done_r & en_i & ~reset_i)
begin
case (op)
eSend: v_o = 1'b1;
eReceive: ready_o = 1'b1;
eDone: done_n = 1'b1;
default:
begin
end
endcase
end
end // always_comb
// next instruction logic
always_comb
begin
instr_completed = 1'b0;
error_n = error_r;
cycle_ctr_n = cycle_ctr_r;
if (!done_r & en_i & ~reset_i)
begin
case (op)
eNop: instr_completed = 1'b1;
eSend:
begin
if (yumi_i)
instr_completed = 1'b1;
end
eReceive:
begin
if (v_i)
begin
instr_completed = 1'b1;
if (error_r == 0)
error_n = data_i != data_o;
end
end
eDone: instr_completed = 1'b1;
eFinish: instr_completed = 1'b1;
eCycleDec:
begin
cycle_ctr_n = cycle_ctr_r - 1'b1;
instr_completed = ~(|cycle_ctr_r);
end
eCycleInit:
begin
cycle_ctr_n = rom_data_i[counter_width_p-1:0];
instr_completed = 1;
end
default:
begin
end
endcase // case (op)
end
end
// non-synthesizeable components
always @(negedge clk_i)
begin
if (instr_completed & ~reset_i & ~done_r)
begin
case(op)
eSend:
begin
string localtime;
if (uptime_p)
begin
int fd;
fd=$fopen("/proc/uptime","r");
void'($fscanf(fd,"%s",localtime));
$fclose(fd);
end
else
localtime = "";
$display("### bsg_fsb_node_trace_replay SEND %d'b%b (%m), time=%t uptime=%s", ring_width_p,data_o,$time,localtime);
end
eReceive:
begin
if (data_i !== data_o)
begin
$display("############################################################################");
$display("### bsg_fsb_node_trace_replay RECEIVE unmatched (%m) ");
$display("### ");
$display("### FAIL (trace mismatch) = %h", data_i);
$display("### expected = %h\n", data_o);
$display("### diff = %h\n", data_o ^ data_i);
$display("############################################################################");
$finish();
end
else
begin
$display("### bsg_fsb_node_trace_replay RECEIVE matched %h (%m)", data_o);
end // else: !if(data_i != data_o)
end
eDone:
begin
$display("############################################################################");
$display("###### bsg_fsb_node_trace_replay DONE done_o=1 (trace finished addr=%x) (%m)",rom_addr_o);
$display("############################################################################");
end
eFinish:
begin
$display("############################################################################");
$display("###### bsg_fsb_node_trace_replay FINISH (trace finished; CALLING $finish) (%m)");
$display("############################################################################");
$finish;
end
eCycleDec:
begin
$display("### bsg_fsb_node_trace_replay CYCLE DEC cycle_ctr_r = %x (%m)",cycle_ctr_r);
end
eCycleInit:
begin
$display("### bsg_fsb_node_trace_replay CYCLE INIT = %x (%m)",cycle_ctr_n);
end
default:
begin
end
endcase // case (op)
case (op)
eNop, eSend, eReceive, eDone, eFinish, eCycleDec, eCycleInit:
begin
end
default: $display("### bsg_fsb_node_trace_replay UNKNOWN op %x (%m)\n", op);
endcase // case (op)
end // if (instr_completed & ~reset_i & ~done_r)
end // always @ (negedge clk_i)
endmodule
|
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// Test bench for main module.
`timescale 10 ns / 1 ns
`include "registers.vh"
`include "tile_registers.vh"
module Main_Test;
parameter ADDR_WIDTH=16;
parameter DATA_WIDTH=8;
reg clk; // System clock
reg reset; // System reset
reg rd; // Read enable
reg wr; // Write enable
reg ale; // Address latch enable.
reg [ADDR_WIDTH-1:0] addr; // Address bus
reg [DATA_WIDTH-1:0] data_in; // Data in bus
reg data_valid; // Indicates data-in is valid.
wire [DATA_WIDTH-1:0] data_out; // Data out bus
wire [DATA_WIDTH-1:0] ad;
MainAVR main_avr(._reset(~reset), .clk(clk),
._mpu_rd(~rd), ._mpu_wr(~wr), .mpu_ale(ale),
.mpu_ah(addr[ADDR_WIDTH-1:DATA_WIDTH]), .mpu_ad(ad));
assign data_out = (rd & ~wr & ~ale) ? ad : 'bx;
assign ad = ale ? addr[DATA_WIDTH-1:0] : (data_valid ? data_in : 'bz);
// Generate clock.
always
#1 clk = ~clk;
integer i;
reg [4:0] stage = 0;
initial begin
clk = 0;
reset = 0;
rd = 0;
wr = 0;
addr = 0;
data_in = 0;
data_valid = 0;
// Reset
#5 stage = 1;
#1 reset = 1;
#5 reset = 0;
#1 addr = 'bx;
// Test some writes
#5 stage = 2;
#1 write16(0, 'hdead);
#1 write16(2, 'hbeef);
#1 write16(4, 'hcafe);
#1 write16(8, 'hface);
#1 write16(16, 'hbead);
#1 write16(18, 'hfade);
#1 write16(24, 'hdeaf);
#1 write16(26, 'hface);
#1 write16(28, 'hface);
#1 write16(30, 'hface);
#1 addr = 'bx;
// Test some reads
#5 stage = 3;
#1 read_test();
#1 addr = 'bx;
// Test some byte writes
#5 stage = 4;
for (i = 0; i < 16; i = i + 1)
begin
#1 write8(i * 2, 'h0000);
#1 write8(i * 2 + 1, 'hffff);
end
// Test some reads
#5 stage = 5;
#1 read_test();
// Test some tile reg writes
#5 stage = 6;
for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)
begin
#1 write16((`TILE_REG_ADDR_BASE + i) * 2, ~i);
end
#5 stage = 7;
for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)
begin
#1 read8((`TILE_REG_ADDR_BASE + i) * 2);
#1 read8((`TILE_REG_ADDR_BASE + i) * 2 + 1);
end
// Test some palette writes
#5 stage = 8;
for (i = 0; i < 16; i = i + 1)
begin
#1 write16('h1000 + i * 2, ~i);
end
#5 stage = 9;
for (i = 0; i < 32; i = i + 1)
begin
#1 read8('h1000 + i);
end
end
// Task to write a byte.
task write8;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH-1:0] data_arg;
begin
addr = addr_arg;
data_in = data_arg;
#2 rd = 0; wr = 0; ale = 1; data_valid = 0;
#2 rd = 0; wr = 1; ale = 0; data_valid = 1;
#2 rd = 0; wr = 0; ale = 0; data_valid = 1;
#2 data_valid = 0;
end
endtask
// Task to write a word.
task write16;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH*2-1:0] data_arg;
begin
write8(addr_arg, data_arg[DATA_WIDTH-1:0]);
write8(addr_arg + 1, data_arg[DATA_WIDTH*2-1:DATA_WIDTH]);
end
endtask
// Task to read a byte.
task read8;
input [ADDR_WIDTH-1:0] addr_arg;
begin
addr = addr_arg;
#2 rd = 0; wr = 0; ale = 1;
#2 rd = 1; wr = 0; ale = 0;
#2 rd = 0; wr = 0; ale = 0;
end
endtask
// Readback test for the register
task read_test;
integer i;
begin
// Test some reads
#5
for (i = 0; i < 30; i = i + 1) begin
#1 read8(i);
end
end
endtask
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_channel_gate_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Captures transaction open/close events as well as data
// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can
// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When
// CHNL_TX drops, the channel closes (until the next transaction -- signaled by
// CHNL_TX going up again).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTGATE128_IDLE 2'b00
`define S_TXPORTGATE128_OPENING 2'b01
`define S_TXPORTGATE128_OPEN 2'b10
`define S_TXPORTGATE128_CLOSED 2'b11
`timescale 1ns/1ns
module tx_port_channel_gate_128
#(parameter C_DATA_WIDTH = 9'd128,
// Local parameters
parameter C_FIFO_DEPTH = 8,
parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH + 1)
(input RST,
input RD_CLK, // FIFO read clock
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // FIFO read data
output RD_EMPTY, // FIFO is empty
input RD_EN, // FIFO read enable
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN); // Channel write data has been recieved
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rState=`S_TXPORTGATE128_IDLE, _rState=`S_TXPORTGATE128_IDLE;
reg rFifoWen=0, _rFifoWen=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData=0, _rFifoData=0;
wire wFifoFull;
reg rChnlTx=0, _rChnlTx=0;
reg rChnlLast=0, _rChnlLast=0;
reg [31:0] rChnlLen=0, _rChnlLen=0;
reg [30:0] rChnlOff=0, _rChnlOff=0;
reg rAck=0, _rAck=0;
reg rPause=0, _rPause=0;
reg rClosed=0, _rClosed=0;
reg rOpen=0, _rOpen=0;
assign CHNL_TX_ACK = rAck;
assign CHNL_TX_DATA_REN = (rOpen & !wFifoFull); // S_TXPORTGATE128_OPEN
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CHNL_CLK) begin
rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
rChnlLast <= #1 _rChnlLast;
rChnlLen <= #1 _rChnlLen;
rChnlOff <= #1 _rChnlOff;
end
always @ (*) begin
_rChnlTx = CHNL_TX;
_rChnlLast = CHNL_TX_LAST;
_rChnlLen = CHNL_TX_LEN;
_rChnlOff = CHNL_TX_OFF;
end
// FIFO for temporarily storing data from the channel.
(* RAM_STYLE="DISTRIBUTED" *)
async_fifo
#(.C_WIDTH(C_FIFO_DATA_WIDTH),
.C_DEPTH(C_FIFO_DEPTH))
fifo
(.WR_CLK(CHNL_CLK),
.WR_RST(RST),
.WR_EN(rFifoWen),
.WR_DATA(rFifoData),
.WR_FULL(wFifoFull),
.RD_CLK(RD_CLK),
.RD_RST(RST),
.RD_EN(RD_EN),
.RD_DATA(RD_DATA),
.RD_EMPTY(RD_EMPTY));
// Pass the transaction open event, transaction data, and the transaction
// close event through to the RD_CLK domain via the async_fifo.
always @ (posedge CHNL_CLK) begin
rState <= #1 (RST ? `S_TXPORTGATE128_IDLE : _rState);
rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);
rFifoData <= #1 _rFifoData;
rAck <= #1 (RST ? 1'd0 : _rAck);
rPause <= #1 (RST ? 1'd0 : _rPause);
rClosed <= #1 (RST ? 1'd0 : _rClosed);
rOpen <= #1 (RST ? 1'd0 : _rOpen);
end
always @ (*) begin
_rState = rState;
_rFifoWen = rFifoWen;
_rFifoData = rFifoData;
_rPause = rPause;
_rAck = rAck;
_rClosed = rClosed;
_rOpen = rOpen;
case (rState)
`S_TXPORTGATE128_IDLE: begin // Write the len, off, last
_rPause = 0;
_rClosed = 0;
_rOpen = 0;
if (!wFifoFull) begin
_rAck = rChnlTx;
_rFifoWen = rChnlTx;
_rFifoData = {1'd1, 64'd0, rChnlLen, rChnlOff, rChnlLast};
if (rChnlTx)
_rState = `S_TXPORTGATE128_OPENING;
end
end
`S_TXPORTGATE128_OPENING: begin // Write the len, off, last (again)
_rAck = 0;
// rClosed catches a transfer that opens and subsequently closes
// without writing data
_rClosed = (rClosed | !rChnlTx);
if (!wFifoFull) begin
if (rClosed | !rChnlTx)
_rState = `S_TXPORTGATE128_CLOSED;
else begin
_rState = `S_TXPORTGATE128_OPEN;
_rOpen = CHNL_TX & rChnlTx;
end
end
end
`S_TXPORTGATE128_OPEN: begin // Copy channel data into the FIFO
if (!wFifoFull) begin
// CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
// but the VALID+REN model seem to make this difficult.
_rFifoWen = CHNL_TX_DATA_VALID;
_rFifoData = {1'd0, CHNL_TX_DATA};
end
if (!rChnlTx)
_rState = `S_TXPORTGATE128_CLOSED;
_rOpen = CHNL_TX & rChnlTx;
end
`S_TXPORTGATE128_CLOSED: begin // Write the end marker (twice)
if (!wFifoFull) begin
_rPause = 1;
_rFifoWen = 1;
_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
if (rPause)
_rState = `S_TXPORTGATE128_IDLE;
end
end
endcase
end
endmodule
|
module checker (input clk);
parameter DATASIZE = 8;
parameter BUFFSIZE = 1024;
parameter ADDRSIZE = 10;
parameter STRRSIZE = 8*50;
parameter NOTFULL = 0;
parameter FULL = 1;
parameter ALMOSTFULL = 2;
parameter FILLINGUP = 3;
reg [DATASIZE : 0] got [BUFFSIZE - 1 : 0];
reg [DATASIZE : 0] exp [BUFFSIZE - 1 : 0];
integer nGot;
integer nExp;
reg [ADDRSIZE - 1 : 0] gotRdPtr;
reg [ADDRSIZE - 1 : 0] gotWrPtr;
reg [ADDRSIZE - 1 : 0] expRdPtr;
reg [ADDRSIZE - 1 : 0] expWrPtr;
reg[STRRSIZE : 1] name;
task new(input reg[STRRSIZE : 1] inName);
begin
name = inName;
nGot = 0;
nExp = 0;
gotRdPtr = 0;
gotWrPtr = 0;
expRdPtr = 0;
expWrPtr = 0;
end
endtask
function [1:0] addGot(input reg [DATASIZE - 1 : 0] data);
if(nGot == 1024) begin
addGot = FULL;
end
else if(nGot == 1023) begin
addGot = ALMOSTFULL;
end
else if (nGot == 1014) begin
addGot = FILLINGUP;
end
else begin
got[nGot] = data;
nGot = nGot + 1;
gotWrPtr = gotWrPtr + 1;
addGot = NOTFULL;
end
endfunction
function [1:0] addExp(input reg [DATASIZE - 1 : 0] data);
if(nExp == 1024) begin
addExp = FULL;
end
else if(nExp == 1023) begin
addExp = ALMOSTFULL;
end
else if (nExp == 1014) begin
addExp = FILLINGUP;
end
else begin
exp[nExp] = data;
nExp = nExp + 1;
expWrPtr = expWrPtr + 1;
addExp = NOTFULL;
end
endfunction
task checkAll;
integer i;
begin
if(nGot !== nExp) begin
$write("ERROR: %0s: Count Mismatch Got %0d bytes. Expected $0d\n", name, nGot, nExp);
end
else begin
for(i = 0; i < nGot; i = 0) begin
if(got[i] !== exp[i]) begin
$write("ERROR: %0s: Byte mismatch at index: %0d Got: %0h Expected: %0h", name, i, got[i], exp[i]);
end
end
nGot = 0;
nExp = 0;
gotRdPtr = 0;
gotWrPtr = 0;
expRdPtr = 0;
expWrPtr = 0;
end
end
endtask
task check;
while(1) begin
if(nGot > 0 && nExp > 0) begin
end
end
endtask
endmodule
|
`default_nettype none
`timescale 1ns / 1ps
module joypad_snes_adapter(
input wire clock,
input wire reset,
// to gameboy
input wire [1:0] button_sel,
output wire [3:0] button_data,
output reg [15:0] button_state,
// to controller
input wire controller_data,
output wire controller_latch,
output wire controller_clock
);
////////////////////////////////////////////////////////
// http://www.gamefaqs.com/snes/916396-snes/faqs/5395
//
// Note: This implementation does *not* match the
// timings specified in the documentation above.
// Instead, it uses a much simpler and slower 1KHz
// clock which provides pretty good responsiveness
// to button presses. Also note that the Atlys board
// only provides a 3.3V Vcc instead of the spec'd 5V.
//
// Note: Color of wires on my controller ext. cable
// Vcc (+5V) - Green
// Clock - Blue
// Latch - Yellow
// Data - Red
// Ground - Brown
////////////////////////////////////////////////////////
parameter WAIT_STATE = 0;
parameter LATCH_STATE = 1;
parameter READ_STATE = 2;
reg [1:0] state;
reg [3:0] button_index;
//reg [15:0] button_state;
/**
* State transitions occur on the clock's positive edge.
*/
always @(posedge clock) begin
if (reset)
state <= WAIT_STATE;
else begin
if (state == WAIT_STATE)
state <= LATCH_STATE;
else if (state == LATCH_STATE)
state <= READ_STATE;
else if (state == READ_STATE) begin
if (button_index == 15)
state <= WAIT_STATE;
end
end
end
/**
* Button reading occurs on the negative edge to give
* values from the controller time to settle.
*/
always @(negedge clock) begin
if (reset) begin
button_index <= 4'b0;
button_state <= 16'hFFFF;
end else begin
if (state == WAIT_STATE)
button_index <= 4'b0;
else if (state == READ_STATE) begin
button_state[button_index] <= controller_data;
button_index <= button_index + 1;
end
end
end
assign controller_latch = (state == LATCH_STATE) ? 1'b1 : 1'b0;
assign controller_clock = (state == READ_STATE) ? clock : 1'b1;
// button order is
// B Y SELECT START UP DOWN LEFT RIGHT A X L R - - - -
assign button_data =
button_sel[0] == 1'b0 ? { button_state[7], button_state[6], button_state[4], button_state[5] } :
button_sel[1] == 1'b0 ? { button_state[8], button_state[0], button_state[2], button_state[3] } : 4'b1111;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32AI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O32AI_FUNCTIONAL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o32ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
// Local signals
wire B1 nor0_out ;
wire B1 nor1_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32AI_FUNCTIONAL_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's register file generic memory ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Generic (flip-flop based) register file memory ////
//// ////
//// To Do: ////
//// - nothing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
// $Log: or1200_rfram_generic.v,v $
// Revision 1.3 2004/06/08 18:16:32 lampret
// GPR0 hardwired to zero.
//
// Revision 1.2 2002/09/03 22:28:21 lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.1 2002/06/08 16:23:30 lampret
// Generic flip-flop based memory macro for register file.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_rfram_generic(
// Clock and reset
clk, rst,
// Port A
ce_a, addr_a, do_a,
// Port B
ce_b, addr_b, do_b,
// Port W
ce_w, we_w, addr_w, di_w
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Port A
//
input ce_a;
input [aw-1:0] addr_a;
output [dw-1:0] do_a;
//
// Port B
//
input ce_b;
input [aw-1:0] addr_b;
output [dw-1:0] do_b;
//
// Port W
//
input ce_w;
input we_w;
input [aw-1:0] addr_w;
input [dw-1:0] di_w;
//
// Internal wires and regs
//
reg [aw-1:0] intaddr_a;
reg [aw-1:0] intaddr_b;
reg [32*dw-1:0] mem;
reg [dw-1:0] do_a;
reg [dw-1:0] do_b;
//
// Write port
//
always @(posedge clk or posedge rst)
if (rst) begin
mem <= #1 {512'h0, 512'h0};
end
else if (ce_w & we_w)
case (addr_w) // synopsys parallel_case
5'd00: mem[32*0+31:32*0] <= #1 32'h0000_0000;
5'd01: mem[32*1+31:32*1] <= #1 di_w;
5'd02: mem[32*2+31:32*2] <= #1 di_w;
5'd03: mem[32*3+31:32*3] <= #1 di_w;
5'd04: mem[32*4+31:32*4] <= #1 di_w;
5'd05: mem[32*5+31:32*5] <= #1 di_w;
5'd06: mem[32*6+31:32*6] <= #1 di_w;
5'd07: mem[32*7+31:32*7] <= #1 di_w;
5'd08: mem[32*8+31:32*8] <= #1 di_w;
5'd09: mem[32*9+31:32*9] <= #1 di_w;
5'd10: mem[32*10+31:32*10] <= #1 di_w;
5'd11: mem[32*11+31:32*11] <= #1 di_w;
5'd12: mem[32*12+31:32*12] <= #1 di_w;
5'd13: mem[32*13+31:32*13] <= #1 di_w;
5'd14: mem[32*14+31:32*14] <= #1 di_w;
5'd15: mem[32*15+31:32*15] <= #1 di_w;
5'd16: mem[32*16+31:32*16] <= #1 di_w;
5'd17: mem[32*17+31:32*17] <= #1 di_w;
5'd18: mem[32*18+31:32*18] <= #1 di_w;
5'd19: mem[32*19+31:32*19] <= #1 di_w;
5'd20: mem[32*20+31:32*20] <= #1 di_w;
5'd21: mem[32*21+31:32*21] <= #1 di_w;
5'd22: mem[32*22+31:32*22] <= #1 di_w;
5'd23: mem[32*23+31:32*23] <= #1 di_w;
5'd24: mem[32*24+31:32*24] <= #1 di_w;
5'd25: mem[32*25+31:32*25] <= #1 di_w;
5'd26: mem[32*26+31:32*26] <= #1 di_w;
5'd27: mem[32*27+31:32*27] <= #1 di_w;
5'd28: mem[32*28+31:32*28] <= #1 di_w;
5'd29: mem[32*29+31:32*29] <= #1 di_w;
5'd30: mem[32*30+31:32*30] <= #1 di_w;
default: mem[32*31+31:32*31] <= #1 di_w;
endcase
//
// Read port A
//
always @(posedge clk or posedge rst)
if (rst) begin
intaddr_a <= #1 5'h00;
end
else if (ce_a)
intaddr_a <= #1 addr_a;
always @(mem or intaddr_a)
case (intaddr_a) // synopsys parallel_case
5'd00: do_a = 32'h0000_0000;
5'd01: do_a = mem[32*1+31:32*1];
5'd02: do_a = mem[32*2+31:32*2];
5'd03: do_a = mem[32*3+31:32*3];
5'd04: do_a = mem[32*4+31:32*4];
5'd05: do_a = mem[32*5+31:32*5];
5'd06: do_a = mem[32*6+31:32*6];
5'd07: do_a = mem[32*7+31:32*7];
5'd08: do_a = mem[32*8+31:32*8];
5'd09: do_a = mem[32*9+31:32*9];
5'd10: do_a = mem[32*10+31:32*10];
5'd11: do_a = mem[32*11+31:32*11];
5'd12: do_a = mem[32*12+31:32*12];
5'd13: do_a = mem[32*13+31:32*13];
5'd14: do_a = mem[32*14+31:32*14];
5'd15: do_a = mem[32*15+31:32*15];
5'd16: do_a = mem[32*16+31:32*16];
5'd17: do_a = mem[32*17+31:32*17];
5'd18: do_a = mem[32*18+31:32*18];
5'd19: do_a = mem[32*19+31:32*19];
5'd20: do_a = mem[32*20+31:32*20];
5'd21: do_a = mem[32*21+31:32*21];
5'd22: do_a = mem[32*22+31:32*22];
5'd23: do_a = mem[32*23+31:32*23];
5'd24: do_a = mem[32*24+31:32*24];
5'd25: do_a = mem[32*25+31:32*25];
5'd26: do_a = mem[32*26+31:32*26];
5'd27: do_a = mem[32*27+31:32*27];
5'd28: do_a = mem[32*28+31:32*28];
5'd29: do_a = mem[32*29+31:32*29];
5'd30: do_a = mem[32*30+31:32*30];
default: do_a = mem[32*31+31:32*31];
endcase
//
// Read port B
//
always @(posedge clk or posedge rst)
if (rst) begin
intaddr_b <= #1 5'h00;
end
else if (ce_b)
intaddr_b <= #1 addr_b;
always @(mem or intaddr_b)
case (intaddr_b) // synopsys parallel_case
5'd00: do_b = 32'h0000_0000;
5'd01: do_b = mem[32*1+31:32*1];
5'd02: do_b = mem[32*2+31:32*2];
5'd03: do_b = mem[32*3+31:32*3];
5'd04: do_b = mem[32*4+31:32*4];
5'd05: do_b = mem[32*5+31:32*5];
5'd06: do_b = mem[32*6+31:32*6];
5'd07: do_b = mem[32*7+31:32*7];
5'd08: do_b = mem[32*8+31:32*8];
5'd09: do_b = mem[32*9+31:32*9];
5'd10: do_b = mem[32*10+31:32*10];
5'd11: do_b = mem[32*11+31:32*11];
5'd12: do_b = mem[32*12+31:32*12];
5'd13: do_b = mem[32*13+31:32*13];
5'd14: do_b = mem[32*14+31:32*14];
5'd15: do_b = mem[32*15+31:32*15];
5'd16: do_b = mem[32*16+31:32*16];
5'd17: do_b = mem[32*17+31:32*17];
5'd18: do_b = mem[32*18+31:32*18];
5'd19: do_b = mem[32*19+31:32*19];
5'd20: do_b = mem[32*20+31:32*20];
5'd21: do_b = mem[32*21+31:32*21];
5'd22: do_b = mem[32*22+31:32*22];
5'd23: do_b = mem[32*23+31:32*23];
5'd24: do_b = mem[32*24+31:32*24];
5'd25: do_b = mem[32*25+31:32*25];
5'd26: do_b = mem[32*26+31:32*26];
5'd27: do_b = mem[32*27+31:32*27];
5'd28: do_b = mem[32*28+31:32*28];
5'd29: do_b = mem[32*29+31:32*29];
5'd30: do_b = mem[32*30+31:32*30];
default: do_b = mem[32*31+31:32*31];
endcase
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDLCLKP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__SDLCLKP_FUNCTIONAL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_pg/sky130_fd_sc_hs__u_dl_p_pg.v"
`celldefine
module sky130_fd_sc_hs__sdlclkp (
VPWR,
VGND,
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
input VPWR;
input VGND;
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
wire SCE_GATE ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_hs__u_dl_p_pg u_dl_p_pg0 (m0 , SCE_GATE, clkn, VPWR, VGND);
and and0 (GCLK , m0n, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDLCLKP_FUNCTIONAL_V |
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Module: timer.v
// Description: Wishbone based Timer
// Phase accumulator clock:
// Fo = Fc * N / 2^bits
// here N: 12507 and bits: 33
// it gives a frequency of 18.200080376 Hz
// --------------------------------------------------------------------
// --------------------------------------------------------------------
module timer #(
parameter res = 33, // bit resolution (default: 33 bits)
parameter phase = 12507 // phase value for the counter
)
(
input wb_clk_i, // Wishbone slave interface
input wb_rst_i,
output reg wb_tgc_o // Interrupt output
);
reg [res-1:0] cnt;
reg old_clk2;
wire clk2;
// Continuous assignments
assign clk2 = cnt[res-1];
// Behaviour
always @(posedge wb_clk_i)
cnt <= wb_rst_i ? 0 : (cnt + phase);
always @(posedge wb_clk_i)
old_clk2 <= wb_rst_i ? 1'b0 : clk2;
always @(posedge wb_clk_i)
wb_tgc_o <= wb_rst_i ? 1'b0 : (!old_clk2 & clk2);
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:23:58 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7_103 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W17_102 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W64_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_5 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W55_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W55_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_8 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W64_0_7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
output [63:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire enable_Pipeline_input, Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5,
OP_FLAG_INIT, SIGN_FLAG_INIT, ZERO_FLAG_INIT, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, ADD_OVRFLW_NRM, n_7_net_, left_right_SHT2,
bit_shift_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2,
ADD_OVRFLW_NRM2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2,
SIGN_FLAG_NRM, ZERO_FLAG_NRM, n_21_net_, SIGN_FLAG_SFG, OP_FLAG_SFG,
ZERO_FLAG_SFG, N94, N95, ADD_OVRFLW_SGF,
inst_ShiftRegister_net3955607, SFT2FRMT_STAGE_VARS_net3955517,
FRMT_STAGE_DATAOUT_net3955445, SGF_STAGE_DMP_net3955499,
NRM_STAGE_Raw_mant_net3955481, INPUT_STAGE_OPERANDY_net3955445,
EXP_STAGE_DMP_net3955499, SHT1_STAGE_DMP_net3955499,
SHT2_STAGE_DMP_net3955499, SHT2_SHIFT_DATA_net3955481,
array_comparators_GTComparator_N0, n830, n831, n832,
DP_OP_15J206_122_2221_n22, DP_OP_15J206_122_2221_n21,
DP_OP_15J206_122_2221_n20, DP_OP_15J206_122_2221_n19,
DP_OP_15J206_122_2221_n18, DP_OP_15J206_122_2221_n17,
DP_OP_15J206_122_2221_n11, DP_OP_15J206_122_2221_n10,
DP_OP_15J206_122_2221_n9, DP_OP_15J206_122_2221_n8,
DP_OP_15J206_122_2221_n7, DP_OP_15J206_122_2221_n6,
DP_OP_15J206_122_2221_n5, DP_OP_15J206_122_2221_n4,
DP_OP_15J206_122_2221_n3, DP_OP_15J206_122_2221_n2,
DP_OP_15J206_122_2221_n1, intadd_470_CI, intadd_470_SUM_3_,
intadd_470_SUM_2_, intadd_470_SUM_1_, intadd_470_SUM_0_,
intadd_470_n4, intadd_470_n3, intadd_470_n2, intadd_470_n1, n835,
n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, n846,
n847, n848, n849, n850, n851, n852, n853, n854, n855, n856, n857,
n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, n868,
n869, n870, n871, n872, n873, n874, n875, n876, n877, n878, n879,
n880, n881, n882, n883, n884, n885, n886, n887, n888, n889, n890,
n891, n893, n894, n895, n896, n897, n898, n899, n900, n901, n902,
n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, n913,
n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, n924,
n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935,
n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946,
n947, n948, n949, n950, n951, n952, n953, n954, n955, n956, n957,
n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968,
n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990,
n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001,
n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011,
n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021,
n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031,
n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041,
n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051,
n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061,
n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071,
n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081,
n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091,
n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181,
n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631,
n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641,
n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651,
n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661,
n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671,
n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681,
n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691,
n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701,
n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711,
n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721,
n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731,
n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741,
n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751,
n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761,
n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771,
n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781,
n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791,
n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801,
n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811,
n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821,
n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831,
n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841,
n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851,
n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861,
n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871,
n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881,
n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891,
n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901,
n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911,
n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921,
n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931,
n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941,
n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951,
n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961,
n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971,
n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981,
n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991,
n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001,
n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011,
n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021,
n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031,
n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041,
n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051,
n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061,
n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071,
n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081,
n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091,
n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101,
n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111,
n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121,
n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131,
n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141,
n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151,
n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161,
n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171,
n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181,
n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191,
n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201,
n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211,
n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221,
n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231,
n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241,
n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251,
n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261,
n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271,
n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281,
n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291,
n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301,
n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311,
n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321,
n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331,
n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341,
n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351,
n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361,
n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371,
n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381,
n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391,
n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401,
n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411,
n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421,
n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431,
n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441,
n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451,
n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461,
n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471,
n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481,
n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491,
n2492, n2493, n2494, n2495, n2496, n2498, n2499, n2500, n2501, n2502,
n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512,
n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522,
n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532,
n2533, n2534, n2535, n2536;
wire [3:0] Shift_reg_FLAGS_7;
wire [63:0] intDX_EWSW;
wire [62:0] intDY_EWSW;
wire [62:0] DMP_INIT_EWSW;
wire [57:0] DmP_INIT_EWSW;
wire [62:0] DMP_EXP_EWSW;
wire [57:0] DmP_EXP_EWSW;
wire [5:0] Shift_amount_EXP_EW;
wire [62:0] DMP_SHT1_EWSW;
wire [51:0] DmP_mant_SHT1_SW;
wire [5:0] Shift_amount_SHT1_EWR;
wire [5:0] LZD_raw_out_EWR;
wire [5:2] shft_value_mux_o_EWR;
wire [54:0] Raw_mant_NRM_SWR;
wire [89:0] Data_array_SWR;
wire [62:0] DMP_SHT2_EWSW;
wire [5:2] shift_value_SHT2_EWR;
wire [10:0] DMP_exp_NRM2_EW;
wire [10:0] DMP_exp_NRM_EW;
wire [54:0] sftr_odat_SHT2_SWR;
wire [5:0] LZD_output_NRM2_EW;
wire [10:0] exp_rslt_NRM2_EW1;
wire [62:0] DMP_SFG;
wire [54:2] DmP_mant_SFG_SWR;
wire [54:1] Raw_mant_SGF;
wire [63:0] formatted_number_W;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7_103 inst_ShiftRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n832), .ENCLK(inst_ShiftRegister_net3955607), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W17_102 SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[1]), .ENCLK(
SFT2FRMT_STAGE_VARS_net3955517), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W64_0_6 FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[0]), .ENCLK(
FRMT_STAGE_DATAOUT_net3955445), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_5 SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(n_21_net_), .ENCLK(SGF_STAGE_DMP_net3955499), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W55_0_1 NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[2]), .ENCLK(
NRM_STAGE_Raw_mant_net3955481), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W64_0_7 INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(clk), .EN(enable_Pipeline_input), .ENCLK(
INPUT_STAGE_OPERANDY_net3955445), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_9 EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7_6), .ENCLK(EXP_STAGE_DMP_net3955499),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_8 SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7_5), .ENCLK(SHT1_STAGE_DMP_net3955499),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W63_0_7 SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(busy), .ENCLK(SHT2_STAGE_DMP_net3955499), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W55_0_4 SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(clk), .EN(n_7_net_), .ENCLK(SHT2_SHIFT_DATA_net3955481), .TE(1'b0) );
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n2536), .CK(
inst_ShiftRegister_net3955607), .RN(n2503), .Q(Shift_reg_FLAGS_7_6) );
DFFRXLTS inst_ShiftRegister_Q_reg_5_ ( .D(Shift_reg_FLAGS_7_6), .CK(
inst_ShiftRegister_net3955607), .RN(n2487), .Q(Shift_reg_FLAGS_7_5) );
DFFRXLTS inst_ShiftRegister_Q_reg_4_ ( .D(Shift_reg_FLAGS_7_5), .CK(
inst_ShiftRegister_net3955607), .RN(n2488), .QN(n852) );
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(busy), .CK(
inst_ShiftRegister_net3955607), .RN(n2504), .Q(Shift_reg_FLAGS_7[3])
);
DFFRXLTS inst_ShiftRegister_Q_reg_2_ ( .D(Shift_reg_FLAGS_7[3]), .CK(
inst_ShiftRegister_net3955607), .RN(n2488), .Q(Shift_reg_FLAGS_7[2])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(Shift_amount_EXP_EW[0]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2490), .Q(Shift_amount_SHT1_EWR[0])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(Shift_amount_EXP_EW[1]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2491), .Q(Shift_amount_SHT1_EWR[1])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(Shift_amount_EXP_EW[2]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2494), .Q(Shift_amount_SHT1_EWR[2])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(Shift_amount_EXP_EW[3]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2486), .Q(Shift_amount_SHT1_EWR[3])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(Shift_amount_EXP_EW[4]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2491), .Q(Shift_amount_SHT1_EWR[4])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(Shift_amount_EXP_EW[5]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2494), .Q(Shift_amount_SHT1_EWR[5])
);
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n2498),
.Q(ready) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(formatted_number_W[52]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2530), .Q(final_result_ieee[52])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(formatted_number_W[53]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2506), .Q(final_result_ieee[53])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(formatted_number_W[54]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2506), .Q(final_result_ieee[54])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(formatted_number_W[55]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2512), .Q(final_result_ieee[55])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(formatted_number_W[56]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2524), .Q(final_result_ieee[56])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(formatted_number_W[57]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2528), .Q(final_result_ieee[57])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(formatted_number_W[58]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2511), .Q(final_result_ieee[58])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(formatted_number_W[59]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2520), .Q(final_result_ieee[59])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(formatted_number_W[60]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2515), .Q(final_result_ieee[60])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(formatted_number_W[61]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2527), .Q(final_result_ieee[61])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(formatted_number_W[62]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2512), .Q(final_result_ieee[62])
);
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n2484), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2490), .Q(underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(array_comparators_GTComparator_N0),
.CK(FRMT_STAGE_DATAOUT_net3955445), .RN(n2504), .Q(overflow_flag) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(Data_X[18]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2486), .Q(intDX_EWSW[18]), .QN(
n2404) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(DmP_INIT_EWSW[0]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2504), .Q(DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(DmP_EXP_EWSW[0]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2504), .Q(DmP_mant_SHT1_SW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(DmP_INIT_EWSW[1]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2493), .Q(DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(DmP_EXP_EWSW[1]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2505), .Q(DmP_mant_SHT1_SW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(DmP_INIT_EWSW[2]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2489), .Q(DmP_EXP_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(DmP_EXP_EWSW[2]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2495), .Q(DmP_mant_SHT1_SW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(DmP_INIT_EWSW[3]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2490), .Q(DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(DmP_EXP_EWSW[3]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2498), .Q(DmP_mant_SHT1_SW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(DmP_INIT_EWSW[4]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2485), .Q(DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(DmP_EXP_EWSW[4]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2504), .Q(DmP_mant_SHT1_SW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(DmP_INIT_EWSW[5]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2492), .Q(DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(DmP_EXP_EWSW[5]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2491), .Q(DmP_mant_SHT1_SW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(DmP_INIT_EWSW[6]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2505), .Q(DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(DmP_EXP_EWSW[6]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2489), .Q(DmP_mant_SHT1_SW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(DmP_INIT_EWSW[7]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2495), .Q(DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(DmP_EXP_EWSW[7]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2486), .Q(DmP_mant_SHT1_SW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(DmP_INIT_EWSW[8]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2488), .Q(DmP_EXP_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(DmP_EXP_EWSW[8]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2486), .Q(DmP_mant_SHT1_SW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(DmP_INIT_EWSW[9]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n840), .Q(DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(DmP_EXP_EWSW[9]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2487), .Q(DmP_mant_SHT1_SW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(DmP_INIT_EWSW[10]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2503), .Q(DmP_EXP_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(DmP_EXP_EWSW[10]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2491), .Q(DmP_mant_SHT1_SW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(DmP_INIT_EWSW[11]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2487), .Q(DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(DmP_EXP_EWSW[11]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2491), .Q(DmP_mant_SHT1_SW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(DmP_INIT_EWSW[12]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2492), .Q(DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(DmP_EXP_EWSW[12]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2493), .Q(DmP_mant_SHT1_SW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(DmP_INIT_EWSW[13]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2505), .Q(DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(DmP_EXP_EWSW[13]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2489), .Q(DmP_mant_SHT1_SW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(DmP_INIT_EWSW[14]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2495), .Q(DmP_EXP_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(DmP_EXP_EWSW[14]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2503), .Q(DmP_mant_SHT1_SW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(DmP_INIT_EWSW[15]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n840), .Q(DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(DmP_EXP_EWSW[15]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2492), .Q(DmP_mant_SHT1_SW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(DmP_INIT_EWSW[16]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2502), .Q(DmP_EXP_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(DmP_EXP_EWSW[16]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2498), .Q(DmP_mant_SHT1_SW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(DmP_INIT_EWSW[17]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2496), .Q(DmP_EXP_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(DmP_EXP_EWSW[17]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2501), .Q(DmP_mant_SHT1_SW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(DmP_INIT_EWSW[18]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2499), .Q(DmP_EXP_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(DmP_EXP_EWSW[18]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n840), .Q(DmP_mant_SHT1_SW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(DmP_INIT_EWSW[19]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2496), .Q(DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(DmP_EXP_EWSW[19]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2503), .Q(DmP_mant_SHT1_SW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(DmP_INIT_EWSW[20]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2500), .Q(DmP_EXP_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(DmP_EXP_EWSW[20]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2498), .Q(DmP_mant_SHT1_SW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(DmP_INIT_EWSW[21]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2500), .Q(DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(DmP_EXP_EWSW[21]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n838), .Q(DmP_mant_SHT1_SW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(DmP_INIT_EWSW[22]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n1123), .Q(DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(DmP_EXP_EWSW[22]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2486), .Q(DmP_mant_SHT1_SW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(DmP_INIT_EWSW[23]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n839), .Q(DmP_EXP_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(DmP_EXP_EWSW[23]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n840), .Q(DmP_mant_SHT1_SW[23]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(DmP_INIT_EWSW[24]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n1123), .Q(DmP_EXP_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(DmP_EXP_EWSW[24]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2500), .Q(DmP_mant_SHT1_SW[24]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(DmP_INIT_EWSW[25]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2498), .Q(DmP_EXP_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(DmP_EXP_EWSW[25]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n838), .Q(DmP_mant_SHT1_SW[25]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(DmP_INIT_EWSW[26]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n1123), .Q(DmP_EXP_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(DmP_EXP_EWSW[26]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2486), .Q(DmP_mant_SHT1_SW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(DmP_INIT_EWSW[27]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n839), .Q(DmP_EXP_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(DmP_EXP_EWSW[27]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n840), .Q(DmP_mant_SHT1_SW[27]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_28_ ( .D(DmP_INIT_EWSW[28]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2494), .Q(DmP_EXP_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(DmP_EXP_EWSW[28]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2488), .Q(DmP_mant_SHT1_SW[28]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_29_ ( .D(DmP_INIT_EWSW[29]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2485), .Q(DmP_EXP_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(DmP_EXP_EWSW[29]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2488), .Q(DmP_mant_SHT1_SW[29]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_30_ ( .D(DmP_INIT_EWSW[30]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2485), .Q(DmP_EXP_EWSW[30]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(DmP_EXP_EWSW[30]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2494), .Q(DmP_mant_SHT1_SW[30]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_31_ ( .D(DmP_INIT_EWSW[31]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2503), .Q(DmP_EXP_EWSW[31]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(DmP_EXP_EWSW[31]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2488), .Q(DmP_mant_SHT1_SW[31]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_32_ ( .D(DmP_INIT_EWSW[32]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n838), .Q(DmP_EXP_EWSW[32]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(DmP_EXP_EWSW[32]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n1123), .Q(DmP_mant_SHT1_SW[32]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_33_ ( .D(DmP_INIT_EWSW[33]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2486), .Q(DmP_EXP_EWSW[33]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(DmP_EXP_EWSW[33]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n839), .Q(DmP_mant_SHT1_SW[33]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_34_ ( .D(DmP_INIT_EWSW[34]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n840), .Q(DmP_EXP_EWSW[34]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(DmP_EXP_EWSW[34]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2500), .Q(DmP_mant_SHT1_SW[34]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_35_ ( .D(DmP_INIT_EWSW[35]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n838), .Q(DmP_EXP_EWSW[35]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(DmP_EXP_EWSW[35]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n1123), .Q(DmP_mant_SHT1_SW[35]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_36_ ( .D(DmP_INIT_EWSW[36]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2496), .Q(DmP_EXP_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(DmP_EXP_EWSW[36]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2501), .Q(DmP_mant_SHT1_SW[36]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_37_ ( .D(DmP_INIT_EWSW[37]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2499), .Q(DmP_EXP_EWSW[37]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(DmP_EXP_EWSW[37]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2490), .Q(DmP_mant_SHT1_SW[37]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_38_ ( .D(DmP_INIT_EWSW[38]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2504), .Q(DmP_EXP_EWSW[38]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(DmP_EXP_EWSW[38]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2496), .Q(DmP_mant_SHT1_SW[38]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_39_ ( .D(DmP_INIT_EWSW[39]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2502), .Q(DmP_EXP_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(DmP_EXP_EWSW[39]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2501), .Q(DmP_mant_SHT1_SW[39]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_40_ ( .D(DmP_INIT_EWSW[40]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n1123), .Q(DmP_EXP_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(DmP_EXP_EWSW[40]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2500), .Q(DmP_mant_SHT1_SW[40]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_41_ ( .D(DmP_INIT_EWSW[41]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2486), .Q(DmP_EXP_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(DmP_EXP_EWSW[41]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n839), .Q(DmP_mant_SHT1_SW[41]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_42_ ( .D(DmP_INIT_EWSW[42]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n840), .Q(DmP_EXP_EWSW[42]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(DmP_EXP_EWSW[42]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2500), .Q(DmP_mant_SHT1_SW[42]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_43_ ( .D(DmP_INIT_EWSW[43]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2498), .Q(DmP_EXP_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(DmP_EXP_EWSW[43]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n838), .Q(DmP_mant_SHT1_SW[43]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_44_ ( .D(DmP_INIT_EWSW[44]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2499), .Q(DmP_EXP_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(DmP_EXP_EWSW[44]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2504), .Q(DmP_mant_SHT1_SW[44]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_45_ ( .D(DmP_INIT_EWSW[45]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2496), .Q(DmP_EXP_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(DmP_EXP_EWSW[45]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2490), .Q(DmP_mant_SHT1_SW[45]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_46_ ( .D(DmP_INIT_EWSW[46]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2502), .Q(DmP_EXP_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(DmP_EXP_EWSW[46]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2501), .Q(DmP_mant_SHT1_SW[46]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_47_ ( .D(DmP_INIT_EWSW[47]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2499), .Q(DmP_EXP_EWSW[47]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(DmP_EXP_EWSW[47]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2485), .Q(DmP_mant_SHT1_SW[47]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_48_ ( .D(DmP_INIT_EWSW[48]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2499), .Q(DmP_EXP_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(DmP_EXP_EWSW[48]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2485), .Q(DmP_mant_SHT1_SW[48]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_49_ ( .D(DmP_INIT_EWSW[49]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2498), .Q(DmP_EXP_EWSW[49]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(DmP_EXP_EWSW[49]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2496), .Q(DmP_mant_SHT1_SW[49]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_50_ ( .D(DmP_INIT_EWSW[50]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2490), .Q(DmP_EXP_EWSW[50]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(DmP_EXP_EWSW[50]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2501), .Q(DmP_mant_SHT1_SW[50]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_51_ ( .D(DmP_INIT_EWSW[51]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2485), .Q(DmP_EXP_EWSW[51]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(DmP_EXP_EWSW[51]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2485), .Q(DmP_mant_SHT1_SW[51]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_52_ ( .D(DmP_INIT_EWSW[52]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2502), .Q(DmP_EXP_EWSW[52]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_53_ ( .D(DmP_INIT_EWSW[53]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2501), .Q(DmP_EXP_EWSW[53]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_54_ ( .D(DmP_INIT_EWSW[54]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2499), .Q(DmP_EXP_EWSW[54]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_55_ ( .D(DmP_INIT_EWSW[55]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2486), .Q(DmP_EXP_EWSW[55]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_56_ ( .D(DmP_INIT_EWSW[56]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2502), .Q(DmP_EXP_EWSW[56]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_57_ ( .D(DmP_INIT_EWSW[57]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2498), .Q(DmP_EXP_EWSW[57]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(DMP_INIT_EWSW[0]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n840), .Q(DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(DMP_INIT_EWSW[1]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2492), .Q(DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(DMP_INIT_EWSW[2]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2493), .Q(DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(DMP_INIT_EWSW[3]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2505), .Q(DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(DMP_INIT_EWSW[4]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2489), .Q(DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(DMP_INIT_EWSW[5]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2495), .Q(DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(DMP_INIT_EWSW[6]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2493), .Q(DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(DMP_INIT_EWSW[7]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2495), .Q(DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(DMP_INIT_EWSW[8]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2505), .Q(DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(DMP_INIT_EWSW[9]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2489), .Q(DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(DMP_INIT_EWSW[10]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2490), .Q(DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(DMP_INIT_EWSW[11]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n840), .Q(DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(DMP_INIT_EWSW[12]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2492), .Q(DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(DMP_INIT_EWSW[13]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2493), .Q(DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(DMP_INIT_EWSW[14]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2505), .Q(DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(DMP_INIT_EWSW[15]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2489), .Q(DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(DMP_INIT_EWSW[16]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2495), .Q(DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(DMP_INIT_EWSW[17]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2503), .Q(DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(DMP_INIT_EWSW[18]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2505), .Q(DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(DMP_INIT_EWSW[19]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2489), .Q(DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(DMP_INIT_EWSW[20]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2485), .Q(DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(DMP_INIT_EWSW[21]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2504), .Q(DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(DMP_INIT_EWSW[22]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2492), .Q(DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(DMP_INIT_EWSW[23]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2493), .Q(DMP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(DMP_INIT_EWSW[24]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2505), .Q(DMP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(DMP_INIT_EWSW[25]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2489), .Q(DMP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(DMP_INIT_EWSW[26]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2495), .Q(DMP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(DMP_INIT_EWSW[27]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2486), .Q(DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(DMP_INIT_EWSW[28]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2498), .Q(DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(DMP_INIT_EWSW[29]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2492), .Q(DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(DMP_INIT_EWSW[30]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2512), .Q(DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_31_ ( .D(DMP_INIT_EWSW[31]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_32_ ( .D(DMP_INIT_EWSW[32]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2518), .Q(DMP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_33_ ( .D(DMP_INIT_EWSW[33]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2524), .Q(DMP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_34_ ( .D(DMP_INIT_EWSW[34]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_35_ ( .D(DMP_INIT_EWSW[35]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n840), .Q(DMP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_36_ ( .D(DMP_INIT_EWSW[36]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2523), .Q(DMP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_37_ ( .D(DMP_INIT_EWSW[37]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2519), .Q(DMP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_38_ ( .D(DMP_INIT_EWSW[38]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_39_ ( .D(DMP_INIT_EWSW[39]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2512), .Q(DMP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_40_ ( .D(DMP_INIT_EWSW[40]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_41_ ( .D(DMP_INIT_EWSW[41]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2518), .Q(DMP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_42_ ( .D(DMP_INIT_EWSW[42]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n839), .Q(DMP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_43_ ( .D(DMP_INIT_EWSW[43]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2516), .Q(DMP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_44_ ( .D(DMP_INIT_EWSW[44]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2510), .Q(DMP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_45_ ( .D(DMP_INIT_EWSW[45]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_46_ ( .D(DMP_INIT_EWSW[46]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_47_ ( .D(DMP_INIT_EWSW[47]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_48_ ( .D(DMP_INIT_EWSW[48]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_49_ ( .D(DMP_INIT_EWSW[49]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2528), .Q(DMP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_50_ ( .D(DMP_INIT_EWSW[50]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2486), .Q(DMP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_51_ ( .D(DMP_INIT_EWSW[51]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2516), .Q(DMP_EXP_EWSW[51]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_52_ ( .D(DMP_INIT_EWSW[52]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2510), .Q(DMP_EXP_EWSW[52]), .QN(n920)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_53_ ( .D(DMP_INIT_EWSW[53]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_EXP_EWSW[53]), .QN(n2424) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_54_ ( .D(DMP_INIT_EWSW[54]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_EXP_EWSW[54]), .QN(n2474) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_55_ ( .D(DMP_INIT_EWSW[55]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2515), .Q(DMP_EXP_EWSW[55]), .QN(n2473) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_56_ ( .D(DMP_INIT_EWSW[56]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2519), .Q(DMP_EXP_EWSW[56]), .QN(n2482) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_57_ ( .D(DMP_INIT_EWSW[57]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2528), .Q(DMP_EXP_EWSW[57]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_58_ ( .D(DMP_INIT_EWSW[58]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2527), .Q(DMP_EXP_EWSW[58]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_59_ ( .D(DMP_INIT_EWSW[59]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_EXP_EWSW[59]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_60_ ( .D(DMP_INIT_EWSW[60]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2528), .Q(DMP_EXP_EWSW[60]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_61_ ( .D(DMP_INIT_EWSW[61]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2492), .Q(DMP_EXP_EWSW[61]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_62_ ( .D(DMP_INIT_EWSW[62]), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2527), .Q(DMP_EXP_EWSW[62]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2519), .Q(ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2515), .Q(OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3955499), .RN(n2522), .Q(SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(DMP_EXP_EWSW[0]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(DMP_EXP_EWSW[1]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(DMP_EXP_EWSW[2]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2486), .Q(DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(DMP_EXP_EWSW[3]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2501), .Q(DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(DMP_EXP_EWSW[4]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2510), .Q(DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(DMP_EXP_EWSW[5]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(DMP_EXP_EWSW[6]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(DMP_EXP_EWSW[7]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(DMP_EXP_EWSW[8]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(DMP_EXP_EWSW[9]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2519), .Q(DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(DMP_EXP_EWSW[10]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2486), .Q(DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(DMP_EXP_EWSW[11]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2516), .Q(DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(DMP_EXP_EWSW[12]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2510), .Q(DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(DMP_EXP_EWSW[13]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(DMP_EXP_EWSW[14]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2513), .Q(DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(DMP_EXP_EWSW[15]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(DMP_EXP_EWSW[16]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2513), .Q(DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(DMP_EXP_EWSW[17]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2493), .Q(DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(DMP_EXP_EWSW[18]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2514), .Q(DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(DMP_EXP_EWSW[19]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2496), .Q(DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(DMP_EXP_EWSW[20]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2514), .Q(DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(DMP_EXP_EWSW[21]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(DMP_EXP_EWSW[22]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2514), .Q(DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(DMP_EXP_EWSW[23]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2525), .Q(DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(DMP_EXP_EWSW[24]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(DMP_EXP_EWSW[25]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(DMP_EXP_EWSW[26]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2509), .Q(DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(DMP_EXP_EWSW[27]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2515), .Q(DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(DMP_EXP_EWSW[28]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(DMP_EXP_EWSW[29]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2521), .Q(DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(DMP_EXP_EWSW[30]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2488), .Q(DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_31_ ( .D(DMP_EXP_EWSW[31]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2521), .Q(DMP_SHT1_EWSW[31]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_32_ ( .D(DMP_EXP_EWSW[32]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT1_EWSW[32]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_33_ ( .D(DMP_EXP_EWSW[33]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2509), .Q(DMP_SHT1_EWSW[33]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_34_ ( .D(DMP_EXP_EWSW[34]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2505), .Q(DMP_SHT1_EWSW[34]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_35_ ( .D(DMP_EXP_EWSW[35]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2504), .Q(DMP_SHT1_EWSW[35]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_36_ ( .D(DMP_EXP_EWSW[36]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2521), .Q(DMP_SHT1_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_37_ ( .D(DMP_EXP_EWSW[37]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2524), .Q(DMP_SHT1_EWSW[37]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_38_ ( .D(DMP_EXP_EWSW[38]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT1_EWSW[38]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_39_ ( .D(DMP_EXP_EWSW[39]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SHT1_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_40_ ( .D(DMP_EXP_EWSW[40]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT1_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_41_ ( .D(DMP_EXP_EWSW[41]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2515), .Q(DMP_SHT1_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_42_ ( .D(DMP_EXP_EWSW[42]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n838), .Q(DMP_SHT1_EWSW[42]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_43_ ( .D(DMP_EXP_EWSW[43]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2489), .Q(DMP_SHT1_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_44_ ( .D(DMP_EXP_EWSW[44]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2510), .Q(DMP_SHT1_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_45_ ( .D(DMP_EXP_EWSW[45]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2509), .Q(DMP_SHT1_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_46_ ( .D(DMP_EXP_EWSW[46]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2485), .Q(DMP_SHT1_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_47_ ( .D(DMP_EXP_EWSW[47]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SHT1_EWSW[47]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_48_ ( .D(DMP_EXP_EWSW[48]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT1_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_49_ ( .D(DMP_EXP_EWSW[49]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2524), .Q(DMP_SHT1_EWSW[49]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_50_ ( .D(DMP_EXP_EWSW[50]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2527), .Q(DMP_SHT1_EWSW[50]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_51_ ( .D(DMP_EXP_EWSW[51]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2519), .Q(DMP_SHT1_EWSW[51]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_52_ ( .D(DMP_EXP_EWSW[52]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SHT1_EWSW[52]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_53_ ( .D(DMP_EXP_EWSW[53]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_SHT1_EWSW[53]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_54_ ( .D(DMP_EXP_EWSW[54]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2523), .Q(DMP_SHT1_EWSW[54]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_55_ ( .D(DMP_EXP_EWSW[55]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n839), .Q(DMP_SHT1_EWSW[55]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_56_ ( .D(DMP_EXP_EWSW[56]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2515), .Q(DMP_SHT1_EWSW[56]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_57_ ( .D(DMP_EXP_EWSW[57]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2528), .Q(DMP_SHT1_EWSW[57]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_58_ ( .D(DMP_EXP_EWSW[58]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_SHT1_EWSW[58]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_59_ ( .D(DMP_EXP_EWSW[59]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_SHT1_EWSW[59]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_60_ ( .D(DMP_EXP_EWSW[60]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2511), .Q(DMP_SHT1_EWSW[60]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_61_ ( .D(DMP_EXP_EWSW[61]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n839), .Q(DMP_SHT1_EWSW[61]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_62_ ( .D(DMP_EXP_EWSW[62]), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_SHT1_EWSW[62]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2524), .Q(ZERO_FLAG_SHT1) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2511), .Q(OP_FLAG_SHT1) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3955499), .RN(n2523), .Q(SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(DMP_SHT1_EWSW[0]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(DMP_SHT1_EWSW[1]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(DMP_SHT1_EWSW[2]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(DMP_SHT1_EWSW[3]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2496), .Q(DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(DMP_SHT1_EWSW[4]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(DMP_SHT1_EWSW[5]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2486), .Q(DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(DMP_SHT1_EWSW[6]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(DMP_SHT1_EWSW[7]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(DMP_SHT1_EWSW[8]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(DMP_SHT1_EWSW[9]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2505), .Q(DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(DMP_SHT1_EWSW[10]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(DMP_SHT1_EWSW[11]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2503), .Q(DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(DMP_SHT1_EWSW[12]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2524), .Q(DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(DMP_SHT1_EWSW[13]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2511), .Q(DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(DMP_SHT1_EWSW[14]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2519), .Q(DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(DMP_SHT1_EWSW[15]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(DMP_SHT1_EWSW[16]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(DMP_SHT1_EWSW[17]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2530), .Q(DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(DMP_SHT1_EWSW[18]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2518), .Q(DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(DMP_SHT1_EWSW[19]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(DMP_SHT1_EWSW[20]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2512), .Q(DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(DMP_SHT1_EWSW[21]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2530), .Q(DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(DMP_SHT1_EWSW[22]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2528), .Q(DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(DMP_SHT1_EWSW[23]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2528), .Q(DMP_SHT2_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(DMP_SHT1_EWSW[24]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2525), .Q(DMP_SHT2_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(DMP_SHT1_EWSW[25]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2494), .Q(DMP_SHT2_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(DMP_SHT1_EWSW[26]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2531), .Q(DMP_SHT2_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(DMP_SHT1_EWSW[27]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SHT2_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(DMP_SHT1_EWSW[28]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2525), .Q(DMP_SHT2_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(DMP_SHT1_EWSW[29]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2525), .Q(DMP_SHT2_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(DMP_SHT1_EWSW[30]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2514), .Q(DMP_SHT2_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_31_ ( .D(DMP_SHT1_EWSW[31]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2493), .Q(DMP_SHT2_EWSW[31]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_32_ ( .D(DMP_SHT1_EWSW[32]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2514), .Q(DMP_SHT2_EWSW[32]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_33_ ( .D(DMP_SHT1_EWSW[33]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_SHT2_EWSW[33]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_34_ ( .D(DMP_SHT1_EWSW[34]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2525), .Q(DMP_SHT2_EWSW[34]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_35_ ( .D(DMP_SHT1_EWSW[35]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2502), .Q(DMP_SHT2_EWSW[35]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_36_ ( .D(DMP_SHT1_EWSW[36]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SHT2_EWSW[36]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_37_ ( .D(DMP_SHT1_EWSW[37]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2523), .Q(DMP_SHT2_EWSW[37]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_38_ ( .D(DMP_SHT1_EWSW[38]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SHT2_EWSW[38]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_39_ ( .D(DMP_SHT1_EWSW[39]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n840), .Q(DMP_SHT2_EWSW[39]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_40_ ( .D(DMP_SHT1_EWSW[40]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_SHT2_EWSW[40]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_41_ ( .D(DMP_SHT1_EWSW[41]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2524), .Q(DMP_SHT2_EWSW[41]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_42_ ( .D(DMP_SHT1_EWSW[42]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2519), .Q(DMP_SHT2_EWSW[42]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_43_ ( .D(DMP_SHT1_EWSW[43]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_SHT2_EWSW[43]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_44_ ( .D(DMP_SHT1_EWSW[44]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2523), .Q(DMP_SHT2_EWSW[44]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_45_ ( .D(DMP_SHT1_EWSW[45]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_SHT2_EWSW[45]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_46_ ( .D(DMP_SHT1_EWSW[46]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_SHT2_EWSW[46]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_47_ ( .D(DMP_SHT1_EWSW[47]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2511), .Q(DMP_SHT2_EWSW[47]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_48_ ( .D(DMP_SHT1_EWSW[48]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2494), .Q(DMP_SHT2_EWSW[48]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_49_ ( .D(DMP_SHT1_EWSW[49]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2503), .Q(DMP_SHT2_EWSW[49]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_50_ ( .D(DMP_SHT1_EWSW[50]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2531), .Q(DMP_SHT2_EWSW[50]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_51_ ( .D(DMP_SHT1_EWSW[51]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2501), .Q(DMP_SHT2_EWSW[51]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_51_ ( .D(DMP_SHT2_EWSW[51]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2496), .QN(n870) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_52_ ( .D(DMP_SHT1_EWSW[52]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_SHT2_EWSW[52]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_52_ ( .D(DMP_SHT2_EWSW[52]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2527), .Q(DMP_SFG[52]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(DMP_SFG[52]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2515), .Q(DMP_exp_NRM_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(DMP_exp_NRM_EW[0]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2523), .Q(DMP_exp_NRM2_EW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_53_ ( .D(DMP_SHT1_EWSW[53]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2511), .Q(DMP_SHT2_EWSW[53]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_53_ ( .D(DMP_SHT2_EWSW[53]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2527), .Q(DMP_SFG[53]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(DMP_SFG[53]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2509), .Q(DMP_exp_NRM_EW[1]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(DMP_exp_NRM_EW[1]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2520), .Q(DMP_exp_NRM2_EW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(DMP_SHT1_EWSW[54]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2518), .Q(DMP_SHT2_EWSW[54]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_54_ ( .D(DMP_SHT2_EWSW[54]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_SFG[54]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(DMP_SFG[54]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2514), .Q(DMP_exp_NRM_EW[2]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(DMP_exp_NRM_EW[2]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2499), .Q(DMP_exp_NRM2_EW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_55_ ( .D(DMP_SHT1_EWSW[55]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2527), .Q(DMP_SHT2_EWSW[55]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_55_ ( .D(DMP_SHT2_EWSW[55]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2526), .Q(DMP_SFG[55]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(DMP_SFG[55]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2509), .Q(DMP_exp_NRM_EW[3]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(DMP_exp_NRM_EW[3]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2491), .Q(DMP_exp_NRM2_EW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_56_ ( .D(DMP_SHT1_EWSW[56]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2531), .Q(DMP_SHT2_EWSW[56]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_56_ ( .D(DMP_SHT2_EWSW[56]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2513), .Q(DMP_SFG[56]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(DMP_SFG[56]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2521), .Q(DMP_exp_NRM_EW[4]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(DMP_exp_NRM_EW[4]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2531), .Q(DMP_exp_NRM2_EW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_57_ ( .D(DMP_SHT1_EWSW[57]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2526), .Q(DMP_SHT2_EWSW[57]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_57_ ( .D(DMP_SHT2_EWSW[57]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2513), .Q(DMP_SFG[57]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(DMP_SFG[57]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2501), .Q(DMP_exp_NRM_EW[5]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(DMP_exp_NRM_EW[5]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2509), .Q(DMP_exp_NRM2_EW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_58_ ( .D(DMP_SHT1_EWSW[58]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2526), .Q(DMP_SHT2_EWSW[58]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_58_ ( .D(DMP_SHT2_EWSW[58]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2526), .Q(DMP_SFG[58]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(DMP_SFG[58]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2521), .Q(DMP_exp_NRM_EW[6]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(DMP_exp_NRM_EW[6]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2488), .Q(DMP_exp_NRM2_EW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_59_ ( .D(DMP_SHT1_EWSW[59]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2531), .Q(DMP_SHT2_EWSW[59]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_59_ ( .D(DMP_SHT2_EWSW[59]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SFG[59]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(DMP_SFG[59]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2505), .Q(DMP_exp_NRM_EW[7]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(DMP_exp_NRM_EW[7]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2516), .Q(DMP_exp_NRM2_EW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_60_ ( .D(DMP_SHT1_EWSW[60]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2526), .Q(DMP_SHT2_EWSW[60]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_60_ ( .D(DMP_SHT2_EWSW[60]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SFG[60]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(DMP_SFG[60]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2509), .Q(DMP_exp_NRM_EW[8]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(DMP_exp_NRM_EW[8]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2529), .Q(DMP_exp_NRM2_EW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_61_ ( .D(DMP_SHT1_EWSW[61]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2514), .Q(DMP_SHT2_EWSW[61]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_61_ ( .D(DMP_SHT2_EWSW[61]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2496), .Q(DMP_SFG[61]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(DMP_SFG[61]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2489), .Q(DMP_exp_NRM_EW[9]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(DMP_exp_NRM_EW[9]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2528), .Q(DMP_exp_NRM2_EW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_62_ ( .D(DMP_SHT1_EWSW[62]), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2518), .Q(DMP_SHT2_EWSW[62]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_62_ ( .D(DMP_SHT2_EWSW[62]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2509), .Q(DMP_SFG[62]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(DMP_SFG[62]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2509), .Q(DMP_exp_NRM_EW[10]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(DMP_exp_NRM_EW[10]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2521), .Q(DMP_exp_NRM2_EW[10])
);
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2504), .Q(ZERO_FLAG_SHT2) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n840), .Q(OP_FLAG_SHT2) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3955499), .RN(n2499), .Q(SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2490), .Q(ZERO_FLAG_SFG) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2490), .Q(OP_FLAG_SFG) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(Raw_mant_SGF[2]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2521), .QN(n854) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(Raw_mant_SGF[22]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2531), .QN(n851) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(Raw_mant_SGF[27]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2530), .QN(n850) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(Raw_mant_SGF[44]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2527), .QN(n849) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(Raw_mant_SGF[53]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2506), .QN(n842) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(Raw_mant_SGF[54]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2492), .Q(Raw_mant_NRM_SWR[54]),
.QN(n2421) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(LZD_raw_out_EWR[2]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2515), .Q(LZD_output_NRM2_EW[2])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(LZD_raw_out_EWR[3]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n839), .Q(LZD_output_NRM2_EW[3])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(LZD_raw_out_EWR[1]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2520), .Q(LZD_output_NRM2_EW[1])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(LZD_raw_out_EWR[4]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2511), .Q(LZD_output_NRM2_EW[4])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(LZD_raw_out_EWR[0]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n839), .Q(LZD_output_NRM2_EW[0])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(LZD_raw_out_EWR[5]), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2515), .Q(LZD_output_NRM2_EW[5])
);
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2522), .Q(SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SFG), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2511), .Q(ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_NRM), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2524), .Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT1SHT2), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2528), .Q(zero_flag) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(SIGN_FLAG_SFG), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2492), .Q(SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(SIGN_FLAG_NRM), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2492), .Q(SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(formatted_number_W[63]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2493), .Q(final_result_ieee[63])
);
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_51_ ( .D(Data_array_SWR[51]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2492), .QN(n867) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_49_ ( .D(Data_array_SWR[49]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n838), .QN(n861) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_48_ ( .D(Data_array_SWR[48]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2526), .QN(n844) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_46_ ( .D(Data_array_SWR[46]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2514), .QN(n845) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_44_ ( .D(Data_array_SWR[44]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2513), .QN(n864) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_41_ ( .D(Data_array_SWR[41]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2513), .QN(n841) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_40_ ( .D(Data_array_SWR[40]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2525), .QN(n863) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_38_ ( .D(Data_array_SWR[38]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2525), .QN(n865) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_37_ ( .D(Data_array_SWR[37]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2511), .QN(n858) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_36_ ( .D(Data_array_SWR[36]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2521), .QN(n847) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_34_ ( .D(Data_array_SWR[34]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2499), .QN(n846) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_28_ ( .D(Data_array_SWR[28]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2529), .QN(n866) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(Data_array_SWR[23]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2522), .QN(n848) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(Data_array_SWR[22]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2530), .QN(n843) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(Data_array_SWR[21]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .QN(n859) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(Data_array_SWR[18]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .QN(n856) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(Data_array_SWR[12]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .QN(n862) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(Data_array_SWR[11]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .QN(n871) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(Data_array_SWR[10]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2530), .QN(n869) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(Data_array_SWR[9]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2516), .QN(n868) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(Data_array_SWR[3]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2516), .Q(Data_array_SWR[58]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(Data_array_SWR[2]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2531), .Q(Data_array_SWR[57]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(Data_array_SWR[1]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2530), .Q(Data_array_SWR[56]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(Data_array_SWR[0]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2516), .Q(Data_array_SWR[55]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(formatted_number_W[25]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2522), .Q(final_result_ieee[25])
);
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2534), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2528), .Q(left_right_SHT2) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(sftr_odat_SHT2_SWR[1]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2511), .Q(N95) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(sftr_odat_SHT2_SWR[54]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2521), .Q(DmP_mant_SFG_SWR[54]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(formatted_number_W[0]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2530), .Q(final_result_ieee[0])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(formatted_number_W[1]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2512), .Q(final_result_ieee[1])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(formatted_number_W[2]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2515), .Q(final_result_ieee[2])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(formatted_number_W[3]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2518), .Q(final_result_ieee[3])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(formatted_number_W[4]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2520), .Q(final_result_ieee[4])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(formatted_number_W[5]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2530), .Q(final_result_ieee[5])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(formatted_number_W[6]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2522), .Q(final_result_ieee[6])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(formatted_number_W[7]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2493), .Q(final_result_ieee[7])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(formatted_number_W[8]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2492), .Q(final_result_ieee[8])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(formatted_number_W[9]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n838), .Q(final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(formatted_number_W[10]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2530), .Q(final_result_ieee[10])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(formatted_number_W[11]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2522), .Q(final_result_ieee[11])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(formatted_number_W[12]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2493), .Q(final_result_ieee[12])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(formatted_number_W[13]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2492), .Q(final_result_ieee[13])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(formatted_number_W[14]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n838), .Q(final_result_ieee[14])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(formatted_number_W[15]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2530), .Q(final_result_ieee[15])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(formatted_number_W[16]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2522), .Q(final_result_ieee[16])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(formatted_number_W[17]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n838), .Q(final_result_ieee[17])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(formatted_number_W[18]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2530), .Q(final_result_ieee[18])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(formatted_number_W[19]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2522), .Q(final_result_ieee[19])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(formatted_number_W[20]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2493), .Q(final_result_ieee[20])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(formatted_number_W[21]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2492), .Q(final_result_ieee[21])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(formatted_number_W[22]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n838), .Q(final_result_ieee[22])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(formatted_number_W[23]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2530), .Q(final_result_ieee[23])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(formatted_number_W[24]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2522), .Q(final_result_ieee[24])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(formatted_number_W[26]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2493), .Q(final_result_ieee[26])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(formatted_number_W[27]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2492), .Q(final_result_ieee[27])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(formatted_number_W[28]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n838), .Q(final_result_ieee[28])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(formatted_number_W[29]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2530), .Q(final_result_ieee[29])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(formatted_number_W[30]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2510), .Q(final_result_ieee[30])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(formatted_number_W[31]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2529), .Q(final_result_ieee[31])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_32_ ( .D(formatted_number_W[32]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2501), .Q(final_result_ieee[32])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_33_ ( .D(formatted_number_W[33]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2517), .Q(final_result_ieee[33])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_34_ ( .D(formatted_number_W[34]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2529), .Q(final_result_ieee[34])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_35_ ( .D(formatted_number_W[35]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2528), .Q(final_result_ieee[35])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_36_ ( .D(formatted_number_W[36]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2486), .Q(final_result_ieee[36])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_37_ ( .D(formatted_number_W[37]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n840), .Q(final_result_ieee[37])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_38_ ( .D(formatted_number_W[38]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2510), .Q(final_result_ieee[38])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_39_ ( .D(formatted_number_W[39]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2529), .Q(final_result_ieee[39])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_40_ ( .D(formatted_number_W[40]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2499), .Q(final_result_ieee[40])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(formatted_number_W[41]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2529), .Q(final_result_ieee[41])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(formatted_number_W[42]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2519), .Q(final_result_ieee[42])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(formatted_number_W[43]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2519), .Q(final_result_ieee[43])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(formatted_number_W[44]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2492), .Q(final_result_ieee[44])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(formatted_number_W[45]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2512), .Q(final_result_ieee[45])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(formatted_number_W[46]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2507), .Q(final_result_ieee[46])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(formatted_number_W[47]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2506), .Q(final_result_ieee[47])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(formatted_number_W[48]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2524), .Q(final_result_ieee[48])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(formatted_number_W[49]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2507), .Q(final_result_ieee[49])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(formatted_number_W[50]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2524), .Q(final_result_ieee[50])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(formatted_number_W[51]), .CK(
FRMT_STAGE_DATAOUT_net3955445), .RN(n2523), .Q(final_result_ieee[51])
);
CMPR32X2TS DP_OP_15J206_122_2221_U12 ( .A(DMP_exp_NRM2_EW[0]), .B(n2244),
.C(DP_OP_15J206_122_2221_n22), .CO(DP_OP_15J206_122_2221_n11), .S(
exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_15J206_122_2221_U11 ( .A(DP_OP_15J206_122_2221_n21), .B(
DMP_exp_NRM2_EW[1]), .C(DP_OP_15J206_122_2221_n11), .CO(
DP_OP_15J206_122_2221_n10), .S(exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_15J206_122_2221_U10 ( .A(DP_OP_15J206_122_2221_n20), .B(
DMP_exp_NRM2_EW[2]), .C(DP_OP_15J206_122_2221_n10), .CO(
DP_OP_15J206_122_2221_n9), .S(exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_15J206_122_2221_U9 ( .A(DP_OP_15J206_122_2221_n19), .B(
DMP_exp_NRM2_EW[3]), .C(DP_OP_15J206_122_2221_n9), .CO(
DP_OP_15J206_122_2221_n8), .S(exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_15J206_122_2221_U8 ( .A(DP_OP_15J206_122_2221_n18), .B(
DMP_exp_NRM2_EW[4]), .C(DP_OP_15J206_122_2221_n8), .CO(
DP_OP_15J206_122_2221_n7), .S(exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_15J206_122_2221_U7 ( .A(DP_OP_15J206_122_2221_n17), .B(
DMP_exp_NRM2_EW[5]), .C(DP_OP_15J206_122_2221_n7), .CO(
DP_OP_15J206_122_2221_n6), .S(exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS intadd_470_U5 ( .A(DmP_EXP_EWSW[53]), .B(n2424), .C(intadd_470_CI), .CO(intadd_470_n4), .S(intadd_470_SUM_0_) );
CMPR32X2TS intadd_470_U4 ( .A(DmP_EXP_EWSW[54]), .B(n2474), .C(intadd_470_n4), .CO(intadd_470_n3), .S(intadd_470_SUM_1_) );
CMPR32X2TS intadd_470_U3 ( .A(DmP_EXP_EWSW[55]), .B(n2473), .C(intadd_470_n3), .CO(intadd_470_n2), .S(intadd_470_SUM_2_) );
CMPR32X2TS intadd_470_U2 ( .A(DmP_EXP_EWSW[56]), .B(n2482), .C(intadd_470_n2), .CO(intadd_470_n1), .S(intadd_470_SUM_3_) );
DFFSX2TS R_0 ( .D(n2483), .CK(INPUT_STAGE_OPERANDY_net3955445), .SN(n2486),
.Q(n2535) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(Data_Y[47]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2501), .Q(intDY_EWSW[47]), .QN(
n2481) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(Data_Y[19]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2504), .Q(intDY_EWSW[19]), .QN(
n2480) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(Data_Y[0]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n840), .Q(intDY_EWSW[0]), .QN(
n2479) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(Data_Y[1]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2492), .Q(intDY_EWSW[1]), .QN(
n2478) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(Data_Y[38]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2496), .Q(intDY_EWSW[38]), .QN(
n2477) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(Data_Y[37]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .Q(intDY_EWSW[37]), .QN(
n2476) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(Data_Y[18]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2499), .Q(intDY_EWSW[18]), .QN(
n2475) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(Raw_mant_SGF[9]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n839), .Q(Raw_mant_NRM_SWR[9]),
.QN(n2472) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(Data_Y[46]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2496), .Q(intDY_EWSW[46]), .QN(
n2471) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n830), .CK(clk), .RN(
n2485), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n2470) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(Data_Y[32]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .Q(intDY_EWSW[32]), .QN(
n2469) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(Data_Y[51]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2501), .Q(intDY_EWSW[51]), .QN(
n2468) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(Data_Y[52]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2496), .Q(intDY_EWSW[52]), .QN(
n2467) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(Data_Y[48]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2503), .Q(intDY_EWSW[48]), .QN(
n2466) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(Data_Y[10]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .Q(intDY_EWSW[10]), .QN(
n2465) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(Data_Y[44]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2499), .Q(intDY_EWSW[44]), .QN(
n2464) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(Data_Y[9]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDY_EWSW[9]), .QN(
n2463) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(Data_Y[40]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2500), .Q(intDY_EWSW[40]), .QN(
n2462) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(Data_Y[2]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2493), .Q(intDY_EWSW[2]), .QN(
n2461) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(Data_Y[56]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2490), .Q(intDY_EWSW[56]), .QN(
n2460) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(Data_Y[34]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2500), .Q(intDY_EWSW[34]), .QN(
n2459) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(Data_Y[30]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2490), .Q(intDY_EWSW[30]), .QN(
n2458) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(Data_Y[22]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n840), .Q(intDY_EWSW[22]), .QN(
n2457) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(Data_Y[14]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2504), .Q(intDY_EWSW[14]), .QN(
n2456) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(Data_Y[27]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .Q(intDY_EWSW[27]), .QN(
n2455) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(Data_Y[57]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2502), .Q(intDY_EWSW[57]), .QN(
n2454) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(Data_Y[45]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n840), .Q(intDY_EWSW[45]), .QN(
n2453) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(Data_Y[42]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .Q(intDY_EWSW[42]), .QN(
n2452) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(Data_Y[54]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2501), .Q(intDY_EWSW[54]), .QN(
n2451) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(Data_Y[8]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDY_EWSW[8]), .QN(
n2450) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(Data_Y[49]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2502), .Q(intDY_EWSW[49]), .QN(
n2449) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(Data_Y[11]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n840), .Q(intDY_EWSW[11]), .QN(
n2448) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(Data_Y[24]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n838), .Q(intDY_EWSW[24]), .QN(
n2447) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(Data_Y[17]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2502), .Q(intDY_EWSW[17]), .QN(
n2446) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(Data_Y[16]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2486), .Q(intDY_EWSW[16]), .QN(
n2445) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(Data_Y[25]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n1123), .Q(intDY_EWSW[25]), .QN(
n2444) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(Data_Y[26]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2500), .Q(intDY_EWSW[26]), .QN(
n2443) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(Data_Y[36]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2499), .Q(intDY_EWSW[36]), .QN(
n2442) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(Data_Y[28]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2503), .Q(intDY_EWSW[28]), .QN(
n2441) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(Data_Y[20]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n839), .Q(intDY_EWSW[20]), .QN(
n2440) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(Data_Y[12]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2486), .Q(intDY_EWSW[12]), .QN(
n2439) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(Data_Y[50]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2499), .Q(intDY_EWSW[50]), .QN(
n2438) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(sftr_odat_SHT2_SWR[51]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2485), .Q(DmP_mant_SFG_SWR[51]), .QN(
n2423) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_49_ ( .D(DMP_SHT2_EWSW[49]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2521), .Q(DMP_SFG[49]), .QN(n2422) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_50_ ( .D(DMP_SHT2_EWSW[50]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2507), .Q(DMP_SFG[50]), .QN(n2420) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(sftr_odat_SHT2_SWR[52]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2509), .Q(DmP_mant_SFG_SWR[52]), .QN(
n2419) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_29_ ( .D(Data_array_SWR[29]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2505), .Q(Data_array_SWR[75]), .QN(
n2418) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(sftr_odat_SHT2_SWR[49]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2508), .Q(DmP_mant_SFG_SWR[49]), .QN(
n2417) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_47_ ( .D(DMP_SHT2_EWSW[47]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2527), .Q(DMP_SFG[47]), .QN(n2416) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_48_ ( .D(DMP_SHT2_EWSW[48]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2509), .Q(DMP_SFG[48]), .QN(n2415) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_43_ ( .D(Data_array_SWR[43]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2514), .Q(Data_array_SWR[83]), .QN(
n2414) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(Data_X[60]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2488), .Q(intDX_EWSW[60]), .QN(
n2413) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(Data_X[58]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .Q(intDX_EWSW[58]), .QN(
n2412) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_54_ ( .D(Data_array_SWR[54]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2493), .Q(Data_array_SWR[89]), .QN(
n2411) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(Data_X[62]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDX_EWSW[62]), .QN(
n2410) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_45_ ( .D(Data_array_SWR[45]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2514), .Q(Data_array_SWR[84]), .QN(
n2409) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_52_ ( .D(Data_array_SWR[52]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2530), .Q(Data_array_SWR[87]), .QN(
n2408) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(Data_array_SWR[24]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2524), .Q(Data_array_SWR[71]), .QN(
n2407) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(Data_X[61]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2488), .Q(intDX_EWSW[61]), .QN(
n2406) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(Data_Y[39]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2501), .Q(intDY_EWSW[39]), .QN(
n2405) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(Data_X[52]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2504), .Q(intDX_EWSW[52]), .QN(
n2401) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(Data_X[48]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2485), .Q(intDX_EWSW[48]), .QN(
n2400) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(Data_X[10]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDX_EWSW[10]), .QN(
n2399) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(Data_X[57]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .QN(n2398) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(Data_X[45]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2490), .QN(n2397) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(Data_X[33]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2489), .QN(n2396) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(Data_X[8]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2488), .QN(n2395) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(Data_X[44]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2502), .Q(intDX_EWSW[44]), .QN(
n2393) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(Data_X[53]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2485), .QN(n2392) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(Data_X[49]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2503), .QN(n2391) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(Data_X[11]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .QN(n2390) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(Data_X[38]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2490), .Q(intDX_EWSW[38]), .QN(
n2388) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(Data_X[37]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .Q(intDX_EWSW[37]), .QN(
n2387) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(Data_X[16]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDX_EWSW[16]), .QN(
n2383) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(Data_X[35]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2495), .QN(n2381) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(Data_X[31]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2505), .QN(n2380) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(Data_X[25]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2504), .QN(n2379) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(Data_X[15]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .QN(n2378) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(Data_X[3]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .QN(n2377) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(Data_X[6]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2503), .Q(intDX_EWSW[6]), .QN(
n2371) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(Data_X[4]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2486), .Q(intDX_EWSW[4]), .QN(
n2370) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(Data_X[1]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .Q(intDX_EWSW[1]), .QN(
n2369) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(Data_X[36]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2505), .Q(intDX_EWSW[36]), .QN(
n2368) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(Data_X[17]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDX_EWSW[17]), .QN(
n2367) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(sftr_odat_SHT2_SWR[47]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2522), .Q(DmP_mant_SFG_SWR[47]), .QN(
n2366) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_45_ ( .D(DMP_SHT2_EWSW[45]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SFG[45]), .QN(n2365) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(Data_X[5]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2487), .Q(intDX_EWSW[5]), .QN(
n2364) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(sftr_odat_SHT2_SWR[45]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2511), .Q(DmP_mant_SFG_SWR[45]), .QN(
n2363) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(sftr_odat_SHT2_SWR[43]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2524), .Q(DmP_mant_SFG_SWR[43]), .QN(
n2362) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_43_ ( .D(DMP_SHT2_EWSW[43]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2523), .Q(DMP_SFG[43]), .QN(n2361) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_41_ ( .D(DMP_SHT2_EWSW[41]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SFG[41]), .QN(n2360) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(sftr_odat_SHT2_SWR[48]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2519), .Q(DmP_mant_SFG_SWR[48]), .QN(
n2359) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(sftr_odat_SHT2_SWR[41]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2519), .Q(DmP_mant_SFG_SWR[41]), .QN(
n2358) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_39_ ( .D(DMP_SHT2_EWSW[39]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2528), .Q(DMP_SFG[39]), .QN(n2357) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(Raw_mant_SGF[35]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2521), .Q(Raw_mant_NRM_SWR[35]),
.QN(n2356) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_44_ ( .D(DMP_SHT2_EWSW[44]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_SFG[44]), .QN(n2355) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(Raw_mant_SGF[4]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2509), .Q(Raw_mant_NRM_SWR[4]),
.QN(n2354) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(shft_value_mux_o_EWR[5]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2523), .Q(shift_value_SHT2_EWR[5]),
.QN(n2353) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(sftr_odat_SHT2_SWR[39]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2507), .Q(DmP_mant_SFG_SWR[39]), .QN(
n2352) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_37_ ( .D(DMP_SHT2_EWSW[37]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2515), .Q(DMP_SFG[37]), .QN(n2351) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(Raw_mant_SGF[17]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2510), .Q(Raw_mant_NRM_SWR[17]),
.QN(n2350) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(shft_value_mux_o_EWR[3]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2518), .Q(shift_value_SHT2_EWR[3]),
.QN(n2349) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(sftr_odat_SHT2_SWR[37]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2530), .Q(DmP_mant_SFG_SWR[37]), .QN(
n2348) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(sftr_odat_SHT2_SWR[35]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2516), .Q(DmP_mant_SFG_SWR[35]), .QN(
n2347) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_35_ ( .D(DMP_SHT2_EWSW[35]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2514), .Q(DMP_SFG[35]), .QN(n2346) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_33_ ( .D(DMP_SHT2_EWSW[33]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2493), .Q(DMP_SFG[33]), .QN(n2345) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(Raw_mant_SGF[41]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2508), .Q(Raw_mant_NRM_SWR[41]),
.QN(n2344) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_42_ ( .D(DMP_SHT2_EWSW[42]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_SFG[42]), .QN(n2343) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(Raw_mant_SGF[31]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n1123), .Q(Raw_mant_NRM_SWR[31]),
.QN(n2342) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(Raw_mant_SGF[23]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2516), .Q(Raw_mant_NRM_SWR[23]),
.QN(n2341) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(sftr_odat_SHT2_SWR[33]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2508), .Q(DmP_mant_SFG_SWR[33]), .QN(
n2340) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_31_ ( .D(DMP_SHT2_EWSW[31]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2526), .Q(DMP_SFG[31]), .QN(n2339) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(Raw_mant_SGF[33]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2525), .Q(Raw_mant_NRM_SWR[33]),
.QN(n2338) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(Data_Y[61]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2493), .Q(intDY_EWSW[61]), .QN(
n2337) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(Raw_mant_SGF[6]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2512), .Q(Raw_mant_NRM_SWR[6]),
.QN(n2336) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(sftr_odat_SHT2_SWR[31]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2490), .Q(DmP_mant_SFG_SWR[31]), .QN(
n2332) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_29_ ( .D(DMP_SHT2_EWSW[29]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2514), .Q(DMP_SFG[29]), .QN(n2331) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(sftr_odat_SHT2_SWR[42]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2507), .Q(DmP_mant_SFG_SWR[42]), .QN(
n2330) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(Raw_mant_SGF[11]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2511), .Q(Raw_mant_NRM_SWR[11]),
.QN(n2328) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(sftr_odat_SHT2_SWR[29]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2526), .Q(DmP_mant_SFG_SWR[29]), .QN(
n2327) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(sftr_odat_SHT2_SWR[27]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2502), .Q(DmP_mant_SFG_SWR[27]), .QN(
n2326) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_27_ ( .D(DMP_SHT2_EWSW[27]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2513), .Q(DMP_SFG[27]), .QN(n2325) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_25_ ( .D(DMP_SHT2_EWSW[25]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SFG[25]), .QN(n2324) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_38_ ( .D(DMP_SHT2_EWSW[38]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_SFG[38]), .QN(n2323) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(sftr_odat_SHT2_SWR[25]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2525), .Q(DmP_mant_SFG_SWR[25]), .QN(
n2322) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_23_ ( .D(DMP_SHT2_EWSW[23]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2524), .Q(DMP_SFG[23]), .QN(n2321) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(Raw_mant_SGF[15]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2521), .Q(Raw_mant_NRM_SWR[15]),
.QN(n2320) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(sftr_odat_SHT2_SWR[23]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2520), .Q(DmP_mant_SFG_SWR[23]), .QN(
n2319) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(DMP_SHT2_EWSW[21]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n840), .Q(DMP_SFG[21]), .QN(n2318) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_36_ ( .D(DMP_SHT2_EWSW[36]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2511), .Q(DMP_SFG[36]), .QN(n2317) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(sftr_odat_SHT2_SWR[21]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2522), .Q(DmP_mant_SFG_SWR[21]), .QN(
n2316) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(sftr_odat_SHT2_SWR[19]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2512), .Q(DmP_mant_SFG_SWR[19]), .QN(
n2315) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(DMP_SHT2_EWSW[19]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2519), .Q(DMP_SFG[19]), .QN(n2314) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(DMP_SHT2_EWSW[17]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2515), .Q(DMP_SFG[17]), .QN(n2313) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(Raw_mant_SGF[20]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2516), .Q(Raw_mant_NRM_SWR[20]),
.QN(n2312) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(sftr_odat_SHT2_SWR[17]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2527), .Q(DmP_mant_SFG_SWR[17]), .QN(
n2311) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(DMP_SHT2_EWSW[15]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2518), .Q(DMP_SFG[15]), .QN(n2310) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(sftr_odat_SHT2_SWR[36]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2513), .Q(DmP_mant_SFG_SWR[36]), .QN(
n2309) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(sftr_odat_SHT2_SWR[15]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2493), .Q(DmP_mant_SFG_SWR[15]), .QN(
n2308) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(DMP_SHT2_EWSW[13]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SFG[13]), .QN(n2307) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_32_ ( .D(DMP_SHT2_EWSW[32]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SFG[32]), .QN(n2306) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(sftr_odat_SHT2_SWR[13]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2507), .Q(DmP_mant_SFG_SWR[13]), .QN(
n2305) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(DMP_SHT2_EWSW[11]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2510), .Q(DMP_SFG[11]), .QN(n2303) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_30_ ( .D(DMP_SHT2_EWSW[30]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2508), .Q(DMP_SFG[30]), .QN(n2299) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(sftr_odat_SHT2_SWR[30]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2526), .Q(DmP_mant_SFG_SWR[30]), .QN(
n2293) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_26_ ( .D(DMP_SHT2_EWSW[26]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2525), .Q(DMP_SFG[26]), .QN(n2290) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(Raw_mant_SGF[34]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2519), .Q(Raw_mant_NRM_SWR[34]),
.QN(n2289) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_24_ ( .D(DMP_SHT2_EWSW[24]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2513), .Q(DMP_SFG[24]), .QN(n2288) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(sftr_odat_SHT2_SWR[24]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2528), .Q(DmP_mant_SFG_SWR[24]), .QN(
n2287) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(DMP_SHT2_EWSW[20]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2518), .Q(DMP_SFG[20]), .QN(n2286) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(Raw_mant_SGF[42]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2508), .Q(Raw_mant_NRM_SWR[42]),
.QN(n2285) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(DMP_SHT2_EWSW[18]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_SFG[18]), .QN(n2284) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(sftr_odat_SHT2_SWR[18]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2523), .Q(DmP_mant_SFG_SWR[18]), .QN(
n2283) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(DMP_SHT2_EWSW[14]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2511), .Q(DMP_SFG[14]), .QN(n2282) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(DMP_SHT2_EWSW[12]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2512), .Q(DMP_SFG[12]), .QN(n2281) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(sftr_odat_SHT2_SWR[12]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2509), .Q(DmP_mant_SFG_SWR[12]), .QN(
n2280) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(Data_Y[6]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2505), .Q(intDY_EWSW[6]), .QN(
n2275) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(Data_Y[4]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2489), .Q(intDY_EWSW[4]), .QN(
n2274) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(Data_X[59]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .Q(intDX_EWSW[59]), .QN(
n2273) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(Data_X[39]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2489), .Q(intDX_EWSW[39]), .QN(
n2272) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(Data_X[19]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2486), .Q(intDX_EWSW[19]), .QN(
n2271) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(Data_X[47]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2499), .Q(intDX_EWSW[47]), .QN(
n2270) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(Data_X[56]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2488), .Q(intDX_EWSW[56]), .QN(
n2269) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(Data_X[32]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2495), .Q(intDX_EWSW[32]), .QN(
n2268) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(Data_X[55]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2487), .Q(intDX_EWSW[55]), .QN(
n2267) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(Data_X[9]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .Q(intDX_EWSW[9]), .QN(
n2266) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(Data_X[50]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n840), .Q(intDX_EWSW[50]), .QN(
n2265) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(Data_X[43]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2496), .Q(intDX_EWSW[43]), .QN(
n2264) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(Data_X[0]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2490), .Q(intDX_EWSW[0]), .QN(
n2263) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(Data_X[40]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2501), .Q(intDX_EWSW[40]), .QN(
n2262) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(Data_X[24]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .Q(intDX_EWSW[24]), .QN(
n2259) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(Data_X[2]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2488), .Q(intDX_EWSW[2]), .QN(
n2257) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(Data_X[26]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2503), .Q(intDX_EWSW[26]), .QN(
n2256) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(Data_X[23]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2487), .Q(intDX_EWSW[23]), .QN(
n2255) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(sftr_odat_SHT2_SWR[50]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2521), .Q(DmP_mant_SFG_SWR[50]), .QN(
n2254) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_46_ ( .D(DMP_SHT2_EWSW[46]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2511), .Q(DMP_SFG[46]), .QN(n2253) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(Data_X[7]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2488), .Q(intDX_EWSW[7]), .QN(
n2252) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(sftr_odat_SHT2_SWR[46]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2522), .Q(DmP_mant_SFG_SWR[46]), .QN(
n2251) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(sftr_odat_SHT2_SWR[44]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2527), .Q(DmP_mant_SFG_SWR[44]), .QN(
n2250) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(Raw_mant_SGF[3]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2521), .Q(Raw_mant_NRM_SWR[3]),
.QN(n2249) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_40_ ( .D(DMP_SHT2_EWSW[40]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2528), .Q(DMP_SFG[40]), .QN(n2248) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(Raw_mant_SGF[39]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2514), .Q(Raw_mant_NRM_SWR[39]),
.QN(n2247) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(sftr_odat_SHT2_SWR[40]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2524), .Q(DmP_mant_SFG_SWR[40]), .QN(
n2245) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(sftr_odat_SHT2_SWR[38]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2515), .Q(DmP_mant_SFG_SWR[38]), .QN(
n2243) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_34_ ( .D(DMP_SHT2_EWSW[34]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2525), .Q(DMP_SFG[34]), .QN(n2242) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(sftr_odat_SHT2_SWR[34]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2514), .Q(DmP_mant_SFG_SWR[34]), .QN(
n2241) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(sftr_odat_SHT2_SWR[32]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2513), .Q(DmP_mant_SFG_SWR[32]), .QN(
n2240) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_28_ ( .D(DMP_SHT2_EWSW[28]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2491), .Q(DMP_SFG[28]), .QN(n2239) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(sftr_odat_SHT2_SWR[28]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2508), .Q(DmP_mant_SFG_SWR[28]), .QN(
n2238) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(sftr_odat_SHT2_SWR[26]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2525), .Q(DmP_mant_SFG_SWR[26]), .QN(
n2237) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(DMP_SHT2_EWSW[22]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2506), .Q(DMP_SFG[22]), .QN(n2236) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(sftr_odat_SHT2_SWR[22]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2519), .Q(DmP_mant_SFG_SWR[22]), .QN(
n2235) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(sftr_odat_SHT2_SWR[20]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2518), .Q(DmP_mant_SFG_SWR[20]), .QN(
n2234) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(DMP_SHT2_EWSW[16]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2520), .Q(DMP_SFG[16]), .QN(n2233) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(sftr_odat_SHT2_SWR[16]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2493), .Q(DmP_mant_SFG_SWR[16]), .QN(
n2232) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(sftr_odat_SHT2_SWR[14]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2493), .Q(DmP_mant_SFG_SWR[14]), .QN(
n2231) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_10_ ( .D(DMP_SHT2_EWSW[10]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2530), .Q(DMP_SFG[10]), .QN(n2230) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(sftr_odat_SHT2_SWR[8]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2503), .Q(DmP_mant_SFG_SWR[8]), .QN(
n2228) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(DMP_SHT2_EWSW[4]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2510), .Q(DMP_SFG[4]), .QN(n2227) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n831), .CK(clk), .RN(
n2487), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n2225) );
CMPR32X2TS DP_OP_15J206_122_2221_U6 ( .A(n2244), .B(DMP_exp_NRM2_EW[6]), .C(
DP_OP_15J206_122_2221_n6), .CO(DP_OP_15J206_122_2221_n5), .S(
exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_15J206_122_2221_U5 ( .A(n2244), .B(DMP_exp_NRM2_EW[7]), .C(
DP_OP_15J206_122_2221_n5), .CO(DP_OP_15J206_122_2221_n4), .S(
exp_rslt_NRM2_EW1[7]) );
CMPR32X2TS DP_OP_15J206_122_2221_U4 ( .A(n2244), .B(DMP_exp_NRM2_EW[8]), .C(
DP_OP_15J206_122_2221_n4), .CO(DP_OP_15J206_122_2221_n3), .S(
exp_rslt_NRM2_EW1[8]) );
CMPR32X2TS DP_OP_15J206_122_2221_U3 ( .A(n2244), .B(DMP_exp_NRM2_EW[9]), .C(
DP_OP_15J206_122_2221_n3), .CO(DP_OP_15J206_122_2221_n2), .S(
exp_rslt_NRM2_EW1[9]) );
CMPR32X2TS DP_OP_15J206_122_2221_U2 ( .A(n2244), .B(DMP_exp_NRM2_EW[10]),
.C(DP_OP_15J206_122_2221_n2), .CO(DP_OP_15J206_122_2221_n1), .S(
exp_rslt_NRM2_EW1[10]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(DMP_SHT2_EWSW[9]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SFG[9]), .QN(n2302) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(DMP_SHT2_EWSW[8]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SFG[8]), .QN(n2279) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(DMP_SHT2_EWSW[7]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n840), .Q(DMP_SFG[7]), .QN(n2300) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(DMP_SHT2_EWSW[6]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SFG[6]), .QN(n2278) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(DMP_SHT2_EWSW[5]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SFG[5]), .QN(n2297) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(DMP_SHT2_EWSW[3]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2517), .Q(DMP_SFG[3]), .QN(n2294) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_2_ ( .D(DMP_SHT2_EWSW[2]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2529), .Q(DMP_SFG[2]), .QN(n2276) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(DMP_SHT2_EWSW[1]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2500), .Q(DMP_SFG[1]), .QN(n2296) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(DMP_SHT2_EWSW[0]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2522), .Q(DMP_SFG[0]), .QN(n2292) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(n2536), .CK(clk), .RN(
n2488), .Q(inst_FSM_INPUT_ENABLE_state_reg[1]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(sftr_odat_SHT2_SWR[6]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2529), .Q(DmP_mant_SFG_SWR[6]), .QN(
n2277) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(sftr_odat_SHT2_SWR[7]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n839), .Q(DmP_mant_SFG_SWR[7]), .QN(
n2298) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(sftr_odat_SHT2_SWR[9]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2529), .Q(DmP_mant_SFG_SWR[9]), .QN(
n2301) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(sftr_odat_SHT2_SWR[2]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2530), .Q(DmP_mant_SFG_SWR[2]), .QN(
n2291) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(sftr_odat_SHT2_SWR[4]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2510), .Q(DmP_mant_SFG_SWR[4]), .QN(
n2226) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(sftr_odat_SHT2_SWR[5]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2530), .Q(DmP_mant_SFG_SWR[5]), .QN(
n2295) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(sftr_odat_SHT2_SWR[10]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2519), .Q(DmP_mant_SFG_SWR[10]), .QN(
n2229) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(sftr_odat_SHT2_SWR[11]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n839), .Q(DmP_mant_SFG_SWR[11]), .QN(
n2304) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(Data_Y[23]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2486), .QN(n2433) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(Data_Y[7]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2495), .Q(intDY_EWSW[7]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(Data_Y[5]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2485), .Q(intDY_EWSW[5]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(Raw_mant_SGF[29]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n1123), .Q(Raw_mant_NRM_SWR[29]),
.QN(n2246) );
DFFRX1TS inst_ShiftRegister_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[1]), .CK(
inst_ShiftRegister_net3955607), .RN(n2487), .Q(Shift_reg_FLAGS_7[0])
);
DFFRX4TS SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(ADD_OVRFLW_NRM), .CK(
SFT2FRMT_STAGE_VARS_net3955517), .RN(n2519), .Q(ADD_OVRFLW_NRM2), .QN(
n2244) );
DFFRX1TS NRM_STAGE_FLAGS_Q_reg_2_ ( .D(ADD_OVRFLW_SGF), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2525), .Q(ADD_OVRFLW_NRM) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(shft_value_mux_o_EWR[4]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2528), .Q(shift_value_SHT2_EWR[4])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(Raw_mant_SGF[14]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2515), .Q(Raw_mant_NRM_SWR[14])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(Raw_mant_SGF[1]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2514), .Q(Raw_mant_NRM_SWR[1]) );
DFFRX2TS SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2533), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2522), .Q(bit_shift_SHT2) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(Raw_mant_SGF[45]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2524), .Q(Raw_mant_NRM_SWR[45])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(Raw_mant_SGF[7]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2489), .Q(Raw_mant_NRM_SWR[7]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(Raw_mant_SGF[12]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2517), .Q(Raw_mant_NRM_SWR[12])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(Raw_mant_SGF[28]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n1123), .Q(Raw_mant_NRM_SWR[28])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(Raw_mant_SGF[51]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2511), .Q(Raw_mant_NRM_SWR[51])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(Raw_mant_SGF[52]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2520), .Q(Raw_mant_NRM_SWR[52])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(Raw_mant_SGF[38]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2507), .Q(Raw_mant_NRM_SWR[38])
);
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(Data_Y[58]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2505), .Q(intDY_EWSW[58]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(Raw_mant_SGF[25]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2531), .Q(Raw_mant_NRM_SWR[25])
);
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(Data_Y[60]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2489), .Q(intDY_EWSW[60]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(Raw_mant_SGF[32]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2525), .Q(Raw_mant_NRM_SWR[32])
);
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(Raw_mant_SGF[43]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2493), .Q(Raw_mant_NRM_SWR[43])
);
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(sftr_odat_SHT2_SWR[53]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2520), .Q(DmP_mant_SFG_SWR[53]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(Raw_mant_SGF[21]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2531), .Q(Raw_mant_NRM_SWR[21])
);
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(Data_array_SWR[16]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .Q(Data_array_SWR[67]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(Data_array_SWR[13]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .Q(Data_array_SWR[64]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(Data_array_SWR[14]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .Q(Data_array_SWR[65]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(Data_array_SWR[15]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .Q(Data_array_SWR[66]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(Data_array_SWR[17]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .Q(Data_array_SWR[68]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_39_ ( .D(Data_array_SWR[39]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2526), .Q(Data_array_SWR[81]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_42_ ( .D(Data_array_SWR[42]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2513), .Q(Data_array_SWR[82]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(Raw_mant_SGF[5]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2489), .Q(Raw_mant_NRM_SWR[5]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(Raw_mant_SGF[19]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2492), .Q(Raw_mant_NRM_SWR[19])
);
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(Raw_mant_SGF[48]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2507), .Q(Raw_mant_NRM_SWR[48])
);
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(Raw_mant_SGF[30]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2525), .Q(Raw_mant_NRM_SWR[30])
);
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(Raw_mant_SGF[50]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2523), .Q(Raw_mant_NRM_SWR[50]),
.QN(n2329) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(Raw_mant_SGF[10]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2529), .Q(Raw_mant_NRM_SWR[10])
);
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(Raw_mant_SGF[36]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2493), .Q(Raw_mant_NRM_SWR[36])
);
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(Data_array_SWR[8]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2531), .Q(Data_array_SWR[63]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(N94), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2509), .Q(Raw_mant_NRM_SWR[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(sftr_odat_SHT2_SWR[0]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2524), .Q(N94) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(shft_value_mux_o_EWR[2]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2516), .Q(shift_value_SHT2_EWR[2])
);
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(Data_Y[3]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .Q(intDY_EWSW[3]), .QN(
n2425) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(Data_Y[55]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n840), .Q(intDY_EWSW[55]), .QN(
n2427) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(Data_Y[15]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2490), .Q(intDY_EWSW[15]), .QN(
n2429) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(Data_Y[31]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2503), .Q(intDY_EWSW[31]), .QN(
n2430) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(Data_Y[35]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2500), .Q(intDY_EWSW[35]), .QN(
n2431) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(Data_Y[43]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n838), .Q(intDY_EWSW[43]), .QN(
n2432) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(Data_Y[13]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .Q(intDY_EWSW[13]), .QN(
n2434) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(Data_Y[21]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2500), .Q(intDY_EWSW[21]), .QN(
n2435) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(Data_Y[29]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2491), .Q(intDY_EWSW[29]), .QN(
n2436) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(Data_Y[53]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2496), .Q(intDY_EWSW[53]), .QN(
n2426) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(Data_Y[33]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2498), .Q(intDY_EWSW[33]), .QN(
n2428) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(Data_Y[41]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n1123), .Q(intDY_EWSW[41]), .QN(
n2437) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_33_ ( .D(Data_array_SWR[33]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2509), .Q(Data_array_SWR[79]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(sftr_odat_SHT2_SWR[3]), .CK(
SGF_STAGE_DMP_net3955499), .RN(n2521), .Q(DmP_mant_SFG_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_30_ ( .D(Data_array_SWR[30]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2521), .Q(Data_array_SWR[76]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(Data_array_SWR[6]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2531), .Q(Data_array_SWR[61]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(Data_array_SWR[7]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2516), .Q(Data_array_SWR[62]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(Data_X[63]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2485), .Q(intDX_EWSW[63]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(Data_X[51]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2499), .Q(intDX_EWSW[51]), .QN(
n2394) );
DFFRX2TS inst_ShiftRegister_Q_reg_1_ ( .D(Shift_reg_FLAGS_7[2]), .CK(
inst_ShiftRegister_net3955607), .RN(n2488), .Q(Shift_reg_FLAGS_7[1]),
.QN(n2532) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(Raw_mant_SGF[16]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2529), .Q(Raw_mant_NRM_SWR[16])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(Raw_mant_SGF[18]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2530), .Q(Raw_mant_NRM_SWR[18])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(Raw_mant_SGF[40]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2526), .Q(Raw_mant_NRM_SWR[40])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(Raw_mant_SGF[49]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2515), .Q(Raw_mant_NRM_SWR[49])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(Raw_mant_SGF[13]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2517), .Q(Raw_mant_NRM_SWR[13])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(Raw_mant_SGF[37]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2514), .Q(Raw_mant_NRM_SWR[37])
);
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(Data_Y[62]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2495), .Q(intDY_EWSW[62]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(Raw_mant_SGF[46]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2528), .Q(Raw_mant_NRM_SWR[46]),
.QN(n2335) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(Data_Y[59]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n840), .Q(intDY_EWSW[59]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(Data_array_SWR[25]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2517), .Q(Data_array_SWR[72]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_47_ ( .D(Data_array_SWR[47]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n838), .Q(Data_array_SWR[85]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_35_ ( .D(Data_array_SWR[35]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2525), .Q(Data_array_SWR[80]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_31_ ( .D(Data_array_SWR[31]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n840), .Q(Data_array_SWR[77]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(Data_array_SWR[19]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .Q(Data_array_SWR[69]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_27_ ( .D(Data_array_SWR[27]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n838), .Q(Data_array_SWR[74]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_53_ ( .D(Data_array_SWR[53]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n838), .Q(Data_array_SWR[88]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_32_ ( .D(Data_array_SWR[32]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2509), .Q(Data_array_SWR[78]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(Data_array_SWR[20]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n839), .Q(Data_array_SWR[70]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_26_ ( .D(Data_array_SWR[26]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2522), .Q(Data_array_SWR[73]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(Raw_mant_SGF[24]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2530), .Q(Raw_mant_NRM_SWR[24])
);
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(Data_X[41]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n840), .Q(intDX_EWSW[41]), .QN(
n2376) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(Data_X[29]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2493), .Q(intDX_EWSW[29]), .QN(
n2386) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(Data_X[21]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2487), .Q(intDX_EWSW[21]), .QN(
n2384) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(Data_X[13]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2485), .Q(intDX_EWSW[13]), .QN(
n2382) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(Raw_mant_SGF[47]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2515), .Q(Raw_mant_NRM_SWR[47])
);
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(Raw_mant_SGF[8]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2504), .Q(Raw_mant_NRM_SWR[8]),
.QN(n2333) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(Data_X[27]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDX_EWSW[27]), .QN(
n2385) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(Data_X[28]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2504), .Q(intDX_EWSW[28]), .QN(
n2375) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(Data_X[20]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDX_EWSW[20]), .QN(
n2373) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(Data_X[12]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2487), .Q(intDX_EWSW[12]), .QN(
n2372) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(Data_X[14]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2494), .Q(intDX_EWSW[14]), .QN(
n2258) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(Data_X[54]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2503), .Q(intDX_EWSW[54]), .QN(
n2402) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(Data_X[34]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2492), .Q(intDX_EWSW[34]), .QN(
n2261) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(Data_X[30]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2493), .Q(intDX_EWSW[30]), .QN(
n2260) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(Data_X[22]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2487), .Q(intDX_EWSW[22]), .QN(
n2374) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(Data_X[42]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2496), .Q(intDX_EWSW[42]), .QN(
n2389) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(Raw_mant_SGF[26]), .CK(
NRM_STAGE_Raw_mant_net3955481), .RN(n2493), .Q(Raw_mant_NRM_SWR[26]),
.QN(n2334) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_50_ ( .D(Data_array_SWR[50]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n1123), .Q(Data_array_SWR[86]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(Data_X[46]), .CK(
INPUT_STAGE_OPERANDY_net3955445), .RN(n2501), .Q(intDX_EWSW[46]), .QN(
n2403) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(Data_array_SWR[5]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2531), .Q(Data_array_SWR[60]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(Data_array_SWR[4]), .CK(
SHT2_SHIFT_DATA_net3955481), .RN(n2530), .Q(Data_array_SWR[59]) );
BUFX6TS U1206 ( .A(n1123), .Y(n2498) );
AOI222X4TS U1207 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[36]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[16]), .C0(Raw_mant_NRM_SWR[38]), .C1(n1342), .Y(n1427) );
AOI222X4TS U1208 ( .A0(n915), .A1(DmP_mant_SHT1_SW[0]), .B0(n2221), .B1(
Raw_mant_NRM_SWR[52]), .C0(n914), .C1(n2533), .Y(n1460) );
AOI2BB1X1TS U1209 ( .A0N(n1602), .A1N(n1601), .B0(n1600), .Y(n1607) );
OAI21X2TS U1210 ( .A0(DmP_mant_SFG_SWR[50]), .A1(DMP_SFG[48]), .B0(n1627),
.Y(n1569) );
AOI21X1TS U1211 ( .A0(n1690), .A1(n1693), .B0(n1694), .Y(n1684) );
OAI21X1TS U1212 ( .A0(n1697), .A1(n1699), .B0(n1591), .Y(n1690) );
OAI21X2TS U1213 ( .A0(DmP_mant_SFG_SWR[46]), .A1(DMP_SFG[44]), .B0(n1653),
.Y(n1565) );
AOI21X1TS U1214 ( .A0(n1618), .A1(n1621), .B0(n1622), .Y(n1697) );
OAI21X1TS U1215 ( .A0(n1716), .A1(n1718), .B0(n1589), .Y(n1709) );
OAI21X1TS U1216 ( .A0(n1729), .A1(n1731), .B0(n1588), .Y(n1722) );
AOI21X1TS U1217 ( .A0(n1735), .A1(n1738), .B0(n1739), .Y(n1729) );
OAI21X1TS U1218 ( .A0(n1742), .A1(n1744), .B0(n1587), .Y(n1735) );
AOI21X1TS U1219 ( .A0(n1748), .A1(n1751), .B0(n1752), .Y(n1742) );
OAI21X1TS U1220 ( .A0(n1755), .A1(n1757), .B0(n1586), .Y(n1748) );
AOI21X1TS U1221 ( .A0(n1761), .A1(n1764), .B0(n1765), .Y(n1755) );
OAI21X1TS U1222 ( .A0(n1769), .A1(n1771), .B0(n1585), .Y(n1761) );
AOI21X1TS U1223 ( .A0(n1775), .A1(n1778), .B0(n1779), .Y(n1769) );
OAI21X1TS U1224 ( .A0(n1782), .A1(n1784), .B0(n1584), .Y(n1775) );
AOI21X1TS U1225 ( .A0(n1788), .A1(n1791), .B0(n1792), .Y(n1782) );
OAI21X1TS U1226 ( .A0(n1795), .A1(n1797), .B0(n1583), .Y(n1788) );
AOI21X1TS U1227 ( .A0(n1801), .A1(n1804), .B0(n1805), .Y(n1795) );
AOI21X1TS U1228 ( .A0(n1814), .A1(n1817), .B0(n1818), .Y(n1808) );
OAI21X1TS U1229 ( .A0(n1703), .A1(n1705), .B0(n1590), .Y(n1618) );
AOI21X1TS U1230 ( .A0(n1709), .A1(n1712), .B0(n1713), .Y(n1703) );
AOI21X1TS U1231 ( .A0(n1722), .A1(n1725), .B0(n1726), .Y(n1716) );
AOI21X1TS U1232 ( .A0(DMP_SFG[37]), .A1(DmP_mant_SFG_SWR[39]), .B0(n1698),
.Y(n1558) );
AOI21X1TS U1233 ( .A0(DMP_SFG[33]), .A1(DmP_mant_SFG_SWR[35]), .B0(n1717),
.Y(n1554) );
OAI21X2TS U1234 ( .A0(n2306), .A1(n2241), .B0(n1553), .Y(n1717) );
OAI21X1TS U1235 ( .A0(DmP_mant_SFG_SWR[34]), .A1(DMP_SFG[32]), .B0(n1724),
.Y(n1553) );
AOI21X1TS U1236 ( .A0(DMP_SFG[31]), .A1(DmP_mant_SFG_SWR[33]), .B0(n1730),
.Y(n1552) );
NOR2X1TS U1237 ( .A(n1638), .B(n1934), .Y(n1639) );
OAI21XLTS U1238 ( .A0(n1402), .A1(n1495), .B0(n1401), .Y(Data_array_SWR[50])
);
OAI21XLTS U1239 ( .A0(n1497), .A1(n2195), .B0(n1478), .Y(Data_array_SWR[11])
);
OAI21XLTS U1240 ( .A0(n2182), .A1(n1453), .B0(n1415), .Y(Data_array_SWR[51])
);
OAI21XLTS U1241 ( .A0(n1397), .A1(n1445), .B0(n1394), .Y(Data_array_SWR[49])
);
OAI21XLTS U1242 ( .A0(n1502), .A1(n2199), .B0(n1501), .Y(Data_array_SWR[10])
);
OAI21XLTS U1243 ( .A0(n1497), .A1(n2199), .B0(n1345), .Y(Data_array_SWR[12])
);
OAI21XLTS U1244 ( .A0(n2188), .A1(n1495), .B0(n1360), .Y(Data_array_SWR[28])
);
OAI21XLTS U1245 ( .A0(n1454), .A1(n2195), .B0(n1424), .Y(Data_array_SWR[31])
);
OAI21XLTS U1246 ( .A0(n1469), .A1(n1495), .B0(n1374), .Y(Data_array_SWR[20])
);
OAI21XLTS U1247 ( .A0(n1484), .A1(n2199), .B0(n1476), .Y(Data_array_SWR[5])
);
OAI21XLTS U1248 ( .A0(n1427), .A1(n1445), .B0(n1392), .Y(Data_array_SWR[38])
);
OAI21XLTS U1249 ( .A0(n1469), .A1(n2195), .B0(n1426), .Y(Data_array_SWR[19])
);
OAI21XLTS U1250 ( .A0(n1440), .A1(n2195), .B0(n1429), .Y(Data_array_SWR[35])
);
OAI21XLTS U1251 ( .A0(n1441), .A1(n1445), .B0(n1389), .Y(Data_array_SWR[37])
);
OAI21XLTS U1252 ( .A0(n1408), .A1(n1445), .B0(n1399), .Y(Data_array_SWR[46])
);
OAI21XLTS U1253 ( .A0(n1454), .A1(n1495), .B0(n1368), .Y(Data_array_SWR[32])
);
OAI21XLTS U1254 ( .A0(n1403), .A1(n2195), .B0(n1384), .Y(Data_array_SWR[47])
);
OAI21XLTS U1255 ( .A0(n2190), .A1(n1495), .B0(n1457), .Y(Data_array_SWR[29])
);
OAI21XLTS U1256 ( .A0(n1489), .A1(n2199), .B0(n1348), .Y(Data_array_SWR[4])
);
OAI21XLTS U1257 ( .A0(n1447), .A1(n1445), .B0(n1387), .Y(Data_array_SWR[41])
);
OAI21XLTS U1258 ( .A0(n1446), .A1(n1445), .B0(n1444), .Y(Data_array_SWR[34])
);
OAI21XLTS U1259 ( .A0(n1452), .A1(n1445), .B0(n1377), .Y(Data_array_SWR[40])
);
OAI21XLTS U1260 ( .A0(n1412), .A1(n1445), .B0(n1364), .Y(Data_array_SWR[44])
);
OAI21XLTS U1261 ( .A0(n1403), .A1(n1445), .B0(n1371), .Y(Data_array_SWR[48])
);
OAI21XLTS U1262 ( .A0(n1479), .A1(n2195), .B0(n1464), .Y(Data_array_SWR[7])
);
OAI21XLTS U1263 ( .A0(n1489), .A1(n2195), .B0(n1487), .Y(Data_array_SWR[3])
);
OAI21XLTS U1264 ( .A0(n1440), .A1(n1445), .B0(n1382), .Y(Data_array_SWR[36])
);
OAI21XLTS U1265 ( .A0(n1480), .A1(n2199), .B0(n1462), .Y(Data_array_SWR[9])
);
OAI21XLTS U1266 ( .A0(n1432), .A1(n1445), .B0(n1420), .Y(Data_array_SWR[33])
);
OAI21XLTS U1267 ( .A0(n1485), .A1(n2199), .B0(n1483), .Y(Data_array_SWR[6])
);
OAI21XLTS U1268 ( .A0(n1460), .A1(n2199), .B0(n1459), .Y(Data_array_SWR[2])
);
OAI21XLTS U1269 ( .A0(n2184), .A1(n1495), .B0(n1434), .Y(Data_array_SWR[30])
);
OAI21XLTS U1270 ( .A0(n1448), .A1(n1445), .B0(n1396), .Y(Data_array_SWR[42])
);
OAI21XLTS U1271 ( .A0(n1407), .A1(n1445), .B0(n1406), .Y(Data_array_SWR[45])
);
OAI21XLTS U1272 ( .A0(n1479), .A1(n2199), .B0(n1354), .Y(Data_array_SWR[8])
);
OAI21XLTS U1273 ( .A0(n1452), .A1(n2195), .B0(n1451), .Y(Data_array_SWR[39])
);
OAI21XLTS U1274 ( .A0(n1412), .A1(n2195), .B0(n1411), .Y(Data_array_SWR[43])
);
OAI21XLTS U1275 ( .A0(n1490), .A1(n2195), .B0(n1467), .Y(Data_array_SWR[15])
);
CLKINVX6TS U1276 ( .A(n1373), .Y(n835) );
OR3X1TS U1277 ( .A(n1110), .B(Raw_mant_NRM_SWR[3]), .C(Raw_mant_NRM_SWR[4]),
.Y(n1336) );
NAND2X1TS U1278 ( .A(n1312), .B(n1313), .Y(n1110) );
NAND3BX1TS U1279 ( .AN(Raw_mant_NRM_SWR[10]), .B(n2328), .C(n1308), .Y(n1320) );
NAND2X1TS U1280 ( .A(n1308), .B(Raw_mant_NRM_SWR[10]), .Y(n2214) );
NAND2X1TS U1281 ( .A(n963), .B(n2320), .Y(n976) );
NOR2BX2TS U1282 ( .AN(n950), .B(Raw_mant_NRM_SWR[16]), .Y(n963) );
NOR3X1TS U1283 ( .A(Raw_mant_NRM_SWR[18]), .B(Raw_mant_NRM_SWR[17]), .C(
n1310), .Y(n950) );
NAND3BX1TS U1284 ( .AN(Raw_mant_NRM_SWR[19]), .B(n947), .C(n2312), .Y(n1310)
);
NAND2X1TS U1285 ( .A(Raw_mant_NRM_SWR[21]), .B(n971), .Y(n1321) );
NOR3X1TS U1286 ( .A(Raw_mant_NRM_SWR[23]), .B(n894), .C(n1112), .Y(n971) );
NAND2BX1TS U1287 ( .AN(Raw_mant_NRM_SWR[24]), .B(n941), .Y(n1112) );
NOR3BX1TS U1288 ( .AN(n2211), .B(Raw_mant_NRM_SWR[26]), .C(
Raw_mant_NRM_SWR[25]), .Y(n941) );
NOR2X1TS U1289 ( .A(Raw_mant_NRM_SWR[31]), .B(n969), .Y(n1324) );
NAND2X1TS U1290 ( .A(n1117), .B(n2289), .Y(n970) );
NOR2X1TS U1291 ( .A(Raw_mant_NRM_SWR[35]), .B(n1325), .Y(n1117) );
NAND2BX1TS U1292 ( .AN(Raw_mant_NRM_SWR[36]), .B(n943), .Y(n1325) );
NOR3X1TS U1293 ( .A(Raw_mant_NRM_SWR[37]), .B(Raw_mant_NRM_SWR[38]), .C(
n1326), .Y(n943) );
NOR2X1TS U1294 ( .A(Raw_mant_NRM_SWR[41]), .B(n968), .Y(n936) );
NAND2X1TS U1295 ( .A(n1107), .B(n2285), .Y(n968) );
OAI21X1TS U1296 ( .A0(DmP_mant_SFG_SWR[6]), .A1(DMP_SFG[4]), .B0(n1906), .Y(
n1525) );
CLKINVX6TS U1297 ( .A(n1125), .Y(n1177) );
INVX2TS U1298 ( .A(n955), .Y(n935) );
BUFX6TS U1299 ( .A(OP_FLAG_SFG), .Y(n1768) );
AOI2BB1X2TS U1300 ( .A0N(n893), .A1N(DmP_mant_SFG_SWR[53]), .B0(n1572), .Y(
n1609) );
OAI21X1TS U1301 ( .A0(n1613), .A1(n1821), .B0(n1612), .Y(n1617) );
AOI2BB1X2TS U1302 ( .A0N(DMP_SFG[49]), .A1N(DmP_mant_SFG_SWR[51]), .B0(n1570), .Y(n1603) );
XOR2X1TS U1303 ( .A(n1637), .B(n1636), .Y(Raw_mant_SGF[49]) );
XOR2X1TS U1304 ( .A(n1650), .B(n1649), .Y(Raw_mant_SGF[47]) );
XOR2X1TS U1305 ( .A(n1663), .B(n1662), .Y(Raw_mant_SGF[45]) );
AOI21X2TS U1306 ( .A0(DMP_SFG[43]), .A1(DmP_mant_SFG_SWR[45]), .B0(n1659),
.Y(n1564) );
XOR2X1TS U1307 ( .A(n1676), .B(n1675), .Y(Raw_mant_SGF[43]) );
AOI21X2TS U1308 ( .A0(DMP_SFG[39]), .A1(DmP_mant_SFG_SWR[41]), .B0(n1685),
.Y(n1560) );
OAI21X2TS U1309 ( .A0(DmP_mant_SFG_SWR[40]), .A1(DMP_SFG[38]), .B0(n1692),
.Y(n1559) );
OAI21X2TS U1310 ( .A0(n2299), .A1(n2240), .B0(n1551), .Y(n1730) );
OAI21X1TS U1311 ( .A0(DmP_mant_SFG_SWR[32]), .A1(DMP_SFG[30]), .B0(n1737),
.Y(n1551) );
AOI21X1TS U1312 ( .A0(DMP_SFG[29]), .A1(DmP_mant_SFG_SWR[31]), .B0(n1743),
.Y(n1550) );
OAI21X2TS U1313 ( .A0(n2239), .A1(n2293), .B0(n1549), .Y(n1743) );
AOI2BB1X2TS U1314 ( .A0N(DMP_SFG[25]), .A1N(DmP_mant_SFG_SWR[27]), .B0(n1546), .Y(n1763) );
OAI21X1TS U1315 ( .A0(n2288), .A1(n2237), .B0(n1545), .Y(n1770) );
OAI21X1TS U1316 ( .A0(DmP_mant_SFG_SWR[26]), .A1(DMP_SFG[24]), .B0(n1777),
.Y(n1545) );
AOI2BB1X2TS U1317 ( .A0N(DMP_SFG[21]), .A1N(DmP_mant_SFG_SWR[23]), .B0(n1542), .Y(n1790) );
OAI21X1TS U1318 ( .A0(DmP_mant_SFG_SWR[22]), .A1(DMP_SFG[20]), .B0(n1803),
.Y(n1541) );
OAI21X1TS U1319 ( .A0(DmP_mant_SFG_SWR[20]), .A1(DMP_SFG[18]), .B0(n1816),
.Y(n1539) );
OAI32X1TS U1320 ( .A0(n939), .A1(n882), .A2(Raw_mant_NRM_SWR[7]), .B0(n2217),
.B1(n939), .Y(n940) );
AOI2BB1X2TS U1321 ( .A0N(DMP_SFG[15]), .A1N(DmP_mant_SFG_SWR[17]), .B0(n1536), .Y(n1830) );
INVX2TS U1322 ( .A(n976), .Y(n1118) );
OAI21X1TS U1323 ( .A0(n2282), .A1(n2232), .B0(n1535), .Y(n1836) );
OAI21X1TS U1324 ( .A0(DmP_mant_SFG_SWR[16]), .A1(DMP_SFG[14]), .B0(n1843),
.Y(n1535) );
AOI2BB1X2TS U1325 ( .A0N(DMP_SFG[11]), .A1N(DmP_mant_SFG_SWR[13]), .B0(n1532), .Y(n1856) );
NAND2XLTS U1326 ( .A(n1867), .B(n1919), .Y(n1868) );
OAI21X1TS U1327 ( .A0(DmP_mant_SFG_SWR[12]), .A1(DMP_SFG[10]), .B0(n1867),
.Y(n1531) );
NAND2XLTS U1328 ( .A(n1880), .B(n1922), .Y(n1881) );
OAI21X1TS U1329 ( .A0(DmP_mant_SFG_SWR[10]), .A1(DMP_SFG[8]), .B0(n1880),
.Y(n1529) );
BUFX4TS U1330 ( .A(n2162), .Y(n2175) );
NAND2XLTS U1331 ( .A(n1893), .B(n1934), .Y(n1894) );
AOI2BB1X2TS U1332 ( .A0N(DMP_SFG[5]), .A1N(DmP_mant_SFG_SWR[7]), .B0(n1526),
.Y(n1893) );
NAND2XLTS U1333 ( .A(n1906), .B(n1919), .Y(n1907) );
NAND2XLTS U1334 ( .A(n1920), .B(n1919), .Y(n1921) );
OR2X4TS U1335 ( .A(n1519), .B(n1102), .Y(n1303) );
BUFX6TS U1336 ( .A(n838), .Y(n2486) );
CLKBUFX2TS U1337 ( .A(n2384), .Y(n889) );
CLKBUFX2TS U1338 ( .A(n2374), .Y(n875) );
CLKBUFX2TS U1339 ( .A(n2258), .Y(n880) );
CLKBUFX2TS U1340 ( .A(n2382), .Y(n888) );
CLKBUFX2TS U1341 ( .A(n2389), .Y(n874) );
CLKBUFX2TS U1342 ( .A(n2376), .Y(n891) );
CLKBUFX2TS U1343 ( .A(n2260), .Y(n876) );
CLKBUFX2TS U1344 ( .A(n2385), .Y(n881) );
CLKBUFX2TS U1345 ( .A(n2386), .Y(n890) );
CLKBUFX2TS U1346 ( .A(n2261), .Y(n877) );
OR2X2TS U1347 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1021) );
BUFX6TS U1348 ( .A(n2532), .Y(n915) );
CLKBUFX2TS U1349 ( .A(Raw_mant_NRM_SWR[8]), .Y(n882) );
CLKBUFX2TS U1350 ( .A(Raw_mant_NRM_SWR[54]), .Y(n886) );
CLKINVX6TS U1351 ( .A(rst), .Y(n1123) );
XOR2X1TS U1352 ( .A(n1599), .B(n1598), .Y(Raw_mant_SGF[51]) );
OAI21X2TS U1353 ( .A0(DmP_mant_SFG_SWR[42]), .A1(DMP_SFG[40]), .B0(n1679),
.Y(n1561) );
OAI21X1TS U1354 ( .A0(DmP_mant_SFG_SWR[30]), .A1(DMP_SFG[28]), .B0(n1750),
.Y(n1549) );
OAI21X1TS U1355 ( .A0(n2290), .A1(n2238), .B0(n1547), .Y(n1756) );
NOR2X1TS U1356 ( .A(n1625), .B(n1934), .Y(n1626) );
OAI21X1TS U1357 ( .A0(DmP_mant_SFG_SWR[28]), .A1(DMP_SFG[26]), .B0(n1763),
.Y(n1547) );
AOI2BB1X2TS U1358 ( .A0N(DMP_SFG[23]), .A1N(DmP_mant_SFG_SWR[25]), .B0(n1544), .Y(n1777) );
OAI211X1TS U1359 ( .A0(n1460), .A1(n2189), .B0(n1418), .C0(n1341), .Y(
Data_array_SWR[0]) );
OAI222X1TS U1360 ( .A0(n2199), .A1(n2194), .B0(n2193), .B1(n2196), .C0(n2195), .C1(n2192), .Y(Data_array_SWR[25]) );
OAI21X1TS U1361 ( .A0(n2236), .A1(n2287), .B0(n1543), .Y(n1783) );
INVX3TS U1362 ( .A(n1466), .Y(n2199) );
OAI21X1TS U1363 ( .A0(DmP_mant_SFG_SWR[24]), .A1(DMP_SFG[22]), .B0(n1790),
.Y(n1543) );
INVX3TS U1364 ( .A(n1466), .Y(n1495) );
AND2X4TS U1365 ( .A(n2187), .B(n2191), .Y(n1373) );
AND2X4TS U1366 ( .A(n2191), .B(n2185), .Y(n1385) );
INVX3TS U1367 ( .A(n1466), .Y(n1445) );
AND2X4TS U1368 ( .A(n2196), .B(n2187), .Y(n1390) );
AND2X4TS U1369 ( .A(n2196), .B(n2185), .Y(n1466) );
AOI2BB1X2TS U1370 ( .A0N(DMP_SFG[19]), .A1N(DmP_mant_SFG_SWR[21]), .B0(n1540), .Y(n1803) );
AOI2BB1X2TS U1371 ( .A0N(DMP_SFG[17]), .A1N(DmP_mant_SFG_SWR[19]), .B0(n1538), .Y(n1816) );
OAI21X1TS U1372 ( .A0(n2233), .A1(n2283), .B0(n1537), .Y(n1823) );
OAI21X1TS U1373 ( .A0(DmP_mant_SFG_SWR[18]), .A1(DMP_SFG[16]), .B0(n1830),
.Y(n1537) );
NAND3BX1TS U1374 ( .AN(Raw_mant_NRM_SWR[14]), .B(n1118), .C(
Raw_mant_NRM_SWR[13]), .Y(n1309) );
AOI21X1TS U1375 ( .A0(DMP_SFG[15]), .A1(DmP_mant_SFG_SWR[17]), .B0(n1836),
.Y(n1536) );
AOI2BB1X2TS U1376 ( .A0N(DMP_SFG[13]), .A1N(DmP_mant_SFG_SWR[15]), .B0(n1534), .Y(n1843) );
AOI21X1TS U1377 ( .A0(DMP_SFG[13]), .A1(DmP_mant_SFG_SWR[15]), .B0(n1849),
.Y(n1534) );
OAI21X1TS U1378 ( .A0(n2281), .A1(n2231), .B0(n1533), .Y(n1849) );
OAI21X1TS U1379 ( .A0(DmP_mant_SFG_SWR[14]), .A1(DMP_SFG[12]), .B0(n1856),
.Y(n1533) );
OAI211X1TS U1380 ( .A0(Raw_mant_NRM_SWR[29]), .A1(n975), .B0(n945), .C0(n944), .Y(n946) );
AOI21X1TS U1381 ( .A0(DMP_SFG[11]), .A1(DmP_mant_SFG_SWR[13]), .B0(n1862),
.Y(n1532) );
AOI2BB1X2TS U1382 ( .A0N(DMP_SFG[9]), .A1N(DmP_mant_SFG_SWR[11]), .B0(n1530),
.Y(n1867) );
NOR2X2TS U1383 ( .A(array_comparators_GTComparator_N0), .B(n2484), .Y(n2200)
);
NAND2BX1TS U1384 ( .AN(Raw_mant_NRM_SWR[32]), .B(n1113), .Y(n969) );
AOI2BB1X2TS U1385 ( .A0N(DMP_SFG[7]), .A1N(DmP_mant_SFG_SWR[9]), .B0(n1528),
.Y(n1880) );
AOI21X1TS U1386 ( .A0(DMP_SFG[7]), .A1(DmP_mant_SFG_SWR[9]), .B0(n1887), .Y(
n1528) );
INVX6TS U1387 ( .A(n2157), .Y(n2162) );
OAI21X1TS U1388 ( .A0(n2278), .A1(n2228), .B0(n1527), .Y(n1887) );
OAI21X1TS U1389 ( .A0(DmP_mant_SFG_SWR[8]), .A1(DMP_SFG[6]), .B0(n1893), .Y(
n1527) );
OAI32X4TS U1390 ( .A0(n968), .A1(Raw_mant_NRM_SWR[40]), .A2(n2247), .B0(
n2344), .B1(n968), .Y(n2205) );
OAI21X2TS U1391 ( .A0(n2249), .A1(n1366), .B0(n1340), .Y(n860) );
AOI2BB1X2TS U1392 ( .A0N(DMP_SFG[3]), .A1N(DmP_mant_SFG_SWR[5]), .B0(n1524),
.Y(n1906) );
OAI21X1TS U1393 ( .A0(n1179), .A1(n2418), .B0(n1178), .Y(n857) );
AO21XLTS U1394 ( .A0(n1928), .A1(n1930), .B0(n1929), .Y(n1923) );
OR2X4TS U1395 ( .A(n1508), .B(n1217), .Y(n1510) );
INVX4TS U1396 ( .A(n2534), .Y(n836) );
NOR2X6TS U1397 ( .A(n1217), .B(n1125), .Y(n983) );
NOR2X6TS U1398 ( .A(n1217), .B(n1021), .Y(n982) );
OAI21X1TS U1399 ( .A0(DmP_mant_SFG_SWR[4]), .A1(DMP_SFG[2]), .B0(n1920), .Y(
n1523) );
NAND2X2TS U1400 ( .A(shift_value_SHT2_EWR[4]), .B(n1257), .Y(n992) );
BUFX4TS U1401 ( .A(n1008), .Y(n837) );
INVX2TS U1402 ( .A(n1772), .Y(n1585) );
INVX2TS U1403 ( .A(n1758), .Y(n1586) );
INVX2TS U1404 ( .A(n1745), .Y(n1587) );
INVX2TS U1405 ( .A(n1661), .Y(n1594) );
INVX2TS U1406 ( .A(n1648), .Y(n1595) );
INVX2TS U1407 ( .A(n1635), .Y(n1596) );
CLKINVX3TS U1408 ( .A(n1194), .Y(n986) );
INVX2TS U1409 ( .A(n1700), .Y(n1591) );
INVX2TS U1410 ( .A(n1706), .Y(n1590) );
INVX6TS U1411 ( .A(n1366), .Y(n1342) );
INVX2TS U1412 ( .A(n1719), .Y(n1589) );
INVX2TS U1413 ( .A(n1687), .Y(n1592) );
INVX2TS U1414 ( .A(n1674), .Y(n1593) );
INVX2TS U1415 ( .A(n1732), .Y(n1588) );
INVX2TS U1416 ( .A(n1785), .Y(n1584) );
NAND2X1TS U1417 ( .A(DmP_mant_SFG_SWR[26]), .B(n2288), .Y(n1778) );
XOR2XLTS U1418 ( .A(DmP_mant_SFG_SWR[52]), .B(DMP_SFG[50]), .Y(n1604) );
NOR2X6TS U1419 ( .A(shift_value_SHT2_EWR[4]), .B(n2353), .Y(n989) );
NOR2X1TS U1420 ( .A(Raw_mant_NRM_SWR[51]), .B(Raw_mant_NRM_SWR[52]), .Y(n932) );
NAND2X1TS U1421 ( .A(DmP_mant_SFG_SWR[30]), .B(n2239), .Y(n1751) );
INVX1TS U1422 ( .A(n851), .Y(n894) );
NAND2X1TS U1423 ( .A(DmP_mant_SFG_SWR[32]), .B(n2299), .Y(n1738) );
NAND2X1TS U1424 ( .A(DmP_mant_SFG_SWR[44]), .B(n2343), .Y(n1667) );
NAND2X1TS U1425 ( .A(DmP_mant_SFG_SWR[42]), .B(n2248), .Y(n1680) );
NAND2X1TS U1426 ( .A(DmP_mant_SFG_SWR[34]), .B(n2306), .Y(n1725) );
NAND2X1TS U1427 ( .A(DmP_mant_SFG_SWR[40]), .B(n2323), .Y(n1693) );
NAND2X1TS U1428 ( .A(DmP_mant_SFG_SWR[38]), .B(n2317), .Y(n1621) );
NAND2X1TS U1429 ( .A(DmP_mant_SFG_SWR[36]), .B(n2242), .Y(n1712) );
NOR3X1TS U1430 ( .A(Raw_mant_NRM_SWR[48]), .B(Raw_mant_NRM_SWR[49]), .C(
Raw_mant_NRM_SWR[50]), .Y(n1114) );
NAND2X1TS U1431 ( .A(DmP_mant_SFG_SWR[46]), .B(n2355), .Y(n1654) );
NAND2X1TS U1432 ( .A(DmP_mant_SFG_SWR[48]), .B(n2253), .Y(n1641) );
NAND2X1TS U1433 ( .A(DmP_mant_SFG_SWR[28]), .B(n2290), .Y(n1764) );
NAND2X1TS U1434 ( .A(DmP_mant_SFG_SWR[50]), .B(n2415), .Y(n1628) );
NAND2X1TS U1435 ( .A(n2419), .B(DMP_SFG[50]), .Y(n1606) );
BUFX6TS U1436 ( .A(n2518), .Y(n838) );
BUFX6TS U1437 ( .A(n2530), .Y(n2522) );
BUFX6TS U1438 ( .A(n2512), .Y(n839) );
BUFX6TS U1439 ( .A(n2498), .Y(n2492) );
BUFX6TS U1440 ( .A(n1123), .Y(n2493) );
BUFX6TS U1441 ( .A(n1123), .Y(n2530) );
BUFX6TS U1442 ( .A(n2498), .Y(n840) );
AOI2BB1X4TS U1443 ( .A0N(DMP_SFG[43]), .A1N(DmP_mant_SFG_SWR[45]), .B0(n1564), .Y(n1653) );
OAI21X4TS U1444 ( .A0(n2323), .A1(n2245), .B0(n1559), .Y(n1685) );
OAI21X4TS U1445 ( .A0(n2317), .A1(n2243), .B0(n1557), .Y(n1698) );
OAI21X4TS U1446 ( .A0(n2415), .A1(n2254), .B0(n1569), .Y(n1597) );
OAI21X4TS U1447 ( .A0(n2355), .A1(n2251), .B0(n1565), .Y(n1646) );
OAI21X4TS U1448 ( .A0(n2248), .A1(n2330), .B0(n1561), .Y(n1672) );
AOI2BB1X4TS U1449 ( .A0N(DMP_SFG[47]), .A1N(DmP_mant_SFG_SWR[49]), .B0(n1568), .Y(n1627) );
AOI2BB1X4TS U1450 ( .A0N(DMP_SFG[37]), .A1N(DmP_mant_SFG_SWR[39]), .B0(n1558), .Y(n1692) );
OAI21X4TS U1451 ( .A0(n2253), .A1(n2359), .B0(n1567), .Y(n1633) );
OAI21X4TS U1452 ( .A0(n2343), .A1(n2250), .B0(n1563), .Y(n1659) );
XOR2X1TS U1453 ( .A(n1610), .B(DmP_mant_SFG_SWR[54]), .Y(Raw_mant_SGF[54])
);
OAI2BB2XLTS U1454 ( .B0(intDX_EWSW[12]), .B1(n2042), .A0N(intDY_EWSW[13]),
.A1N(n888), .Y(n2054) );
NAND2BXLTS U1455 ( .AN(intDY_EWSW[13]), .B(intDX_EWSW[13]), .Y(n2029) );
NAND2BXLTS U1456 ( .AN(intDY_EWSW[21]), .B(intDX_EWSW[21]), .Y(n2028) );
OAI2BB2XLTS U1457 ( .B0(intDX_EWSW[40]), .B1(n2100), .A0N(intDY_EWSW[41]),
.A1N(n891), .Y(n2105) );
AOI221X1TS U1458 ( .A0(n888), .A1(intDY_EWSW[13]), .B0(intDY_EWSW[2]), .B1(
n2257), .C0(n1995), .Y(n2000) );
AOI221X1TS U1459 ( .A0(n2264), .A1(intDY_EWSW[43]), .B0(n872), .B1(n2255),
.C0(n1989), .Y(n1991) );
AOI221X1TS U1460 ( .A0(n2380), .A1(intDY_EWSW[31]), .B0(intDY_EWSW[30]),
.B1(n876), .C0(n1988), .Y(n1992) );
NAND2BXLTS U1461 ( .AN(intDY_EWSW[59]), .B(intDX_EWSW[59]), .Y(n2086) );
OAI32X1TS U1462 ( .A0(n2069), .A1(n2068), .A2(n2067), .B0(n2066), .B1(n2068),
.Y(n2073) );
OAI2BB2XLTS U1463 ( .B0(intDX_EWSW[20]), .B1(n2062), .A0N(intDY_EWSW[21]),
.A1N(n889), .Y(n2074) );
OAI2BB2XLTS U1464 ( .B0(intDX_EWSW[28]), .B1(n2017), .A0N(intDY_EWSW[29]),
.A1N(n890), .Y(n2026) );
NAND2BXLTS U1465 ( .AN(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n2018) );
CLKAND2X2TS U1466 ( .A(bit_shift_SHT2), .B(n1021), .Y(n1199) );
NAND2X1TS U1467 ( .A(n934), .B(n1362), .Y(n951) );
CLKAND2X2TS U1468 ( .A(n933), .B(n932), .Y(n1115) );
AOI221X1TS U1469 ( .A0(n2381), .A1(intDY_EWSW[35]), .B0(intDY_EWSW[34]),
.B1(n877), .C0(n1945), .Y(n1948) );
AOI221X1TS U1470 ( .A0(n874), .A1(intDY_EWSW[42]), .B0(intDY_EWSW[41]), .B1(
n891), .C0(n1946), .Y(n1947) );
AOI221X1TS U1471 ( .A0(n2388), .A1(intDY_EWSW[38]), .B0(intDY_EWSW[22]),
.B1(n875), .C0(n1940), .Y(n1941) );
NAND2BXLTS U1472 ( .AN(intDY_EWSW[41]), .B(intDX_EWSW[41]), .Y(n2014) );
NAND2BXLTS U1473 ( .AN(intDY_EWSW[62]), .B(intDX_EWSW[62]), .Y(n2094) );
AO22XLTS U1474 ( .A0(n2187), .A1(n2188), .B0(n2185), .B1(n2186), .Y(n2193)
);
OAI21X1TS U1475 ( .A0(n2230), .A1(n2280), .B0(n1531), .Y(n1862) );
OAI21X1TS U1476 ( .A0(n2276), .A1(n2226), .B0(n1523), .Y(n1913) );
OAI21X1TS U1477 ( .A0(n2284), .A1(n2234), .B0(n1539), .Y(n1809) );
OAI21X1TS U1478 ( .A0(n2227), .A1(n2277), .B0(n1525), .Y(n1900) );
NAND2BXLTS U1479 ( .AN(DMP_SFG[1]), .B(DmP_mant_SFG_SWR[3]), .Y(n1930) );
OAI21X1TS U1480 ( .A0(n2279), .A1(n2229), .B0(n1529), .Y(n1874) );
AOI21X1TS U1481 ( .A0(DMP_SFG[3]), .A1(DmP_mant_SFG_SWR[5]), .B0(n1913), .Y(
n1524) );
OAI21X1TS U1482 ( .A0(n2286), .A1(n2235), .B0(n1541), .Y(n1796) );
AO22XLTS U1483 ( .A0(n2187), .A1(n2186), .B0(n2185), .B1(n2192), .Y(n2197)
);
INVX6TS U1484 ( .A(n836), .Y(n1379) );
NAND2X1TS U1485 ( .A(n955), .B(n936), .Y(n1326) );
NAND2BXLTS U1486 ( .AN(n951), .B(Raw_mant_NRM_SWR[43]), .Y(n965) );
OAI211XLTS U1487 ( .A0(n2354), .A1(n1110), .B0(n1109), .C0(n1108), .Y(n1111)
);
NAND2BXLTS U1488 ( .AN(n893), .B(DmP_mant_SFG_SWR[53]), .Y(n1614) );
NAND2BXLTS U1489 ( .AN(n1779), .B(n1778), .Y(n1780) );
NOR2XLTS U1490 ( .A(n1648), .B(n1647), .Y(n1649) );
NAND2BXLTS U1491 ( .AN(n1792), .B(n1791), .Y(n1793) );
OAI222X1TS U1492 ( .A0(n2193), .A1(n2191), .B0(n835), .B1(n2184), .C0(n2183),
.C1(n2190), .Y(Data_array_SWR[27]) );
NAND2BXLTS U1493 ( .AN(n1655), .B(n1654), .Y(n1656) );
NOR2XLTS U1494 ( .A(n1651), .B(n1919), .Y(n1652) );
XOR2XLTS U1495 ( .A(n1708), .B(n1707), .Y(Raw_mant_SGF[37]) );
NOR2XLTS U1496 ( .A(n1635), .B(n1634), .Y(n1636) );
NAND2BXLTS U1497 ( .AN(n1694), .B(n1693), .Y(n1695) );
NOR2XLTS U1498 ( .A(n1690), .B(n1919), .Y(n1691) );
NAND2BXLTS U1499 ( .AN(n1832), .B(n1831), .Y(n1833) );
NAND2BXLTS U1500 ( .AN(n1845), .B(n1844), .Y(n1846) );
NAND2BXLTS U1501 ( .AN(n1713), .B(n1712), .Y(n1714) );
NOR2XLTS U1502 ( .A(n1709), .B(n1919), .Y(n1710) );
NAND2BXLTS U1503 ( .AN(n1629), .B(n1628), .Y(n1630) );
NAND2BXLTS U1504 ( .AN(n1752), .B(n1751), .Y(n1753) );
NAND2BXLTS U1505 ( .AN(n1642), .B(n1641), .Y(n1643) );
OAI21XLTS U1506 ( .A0(n1490), .A1(n1495), .B0(n1351), .Y(Data_array_SWR[16])
);
NAND2BXLTS U1507 ( .AN(n1739), .B(n1738), .Y(n1740) );
NAND2BXLTS U1508 ( .AN(n1622), .B(n1621), .Y(n1623) );
NOR2XLTS U1509 ( .A(n1618), .B(n1919), .Y(n1619) );
NOR2XLTS U1510 ( .A(n1600), .B(n1601), .Y(n1598) );
NAND2BXLTS U1511 ( .AN(n1765), .B(n1764), .Y(n1766) );
NAND2BXLTS U1512 ( .AN(n1858), .B(n1857), .Y(n1859) );
XOR2XLTS U1513 ( .A(n1702), .B(n1701), .Y(Raw_mant_SGF[39]) );
NAND2BXLTS U1514 ( .AN(n1681), .B(n1680), .Y(n1682) );
NOR2XLTS U1515 ( .A(n1677), .B(n1919), .Y(n1678) );
NAND2BXLTS U1516 ( .AN(n1726), .B(n1725), .Y(n1727) );
NOR2XLTS U1517 ( .A(n1722), .B(n1919), .Y(n1723) );
NAND2BXLTS U1518 ( .AN(n1818), .B(n1817), .Y(n1819) );
XOR2XLTS U1519 ( .A(n1734), .B(n1733), .Y(Raw_mant_SGF[33]) );
XOR2XLTS U1520 ( .A(n1689), .B(n1688), .Y(Raw_mant_SGF[41]) );
XOR2XLTS U1521 ( .A(n1721), .B(n1720), .Y(Raw_mant_SGF[35]) );
OAI21XLTS U1522 ( .A0(n2182), .A1(n2199), .B0(n1366), .Y(Data_array_SWR[54])
);
OAI21XLTS U1523 ( .A0(n1418), .A1(n1495), .B0(n1417), .Y(Data_array_SWR[1])
);
OAI21XLTS U1524 ( .A0(n1468), .A1(n1495), .B0(n1431), .Y(Data_array_SWR[18])
);
OAI21XLTS U1525 ( .A0(n1439), .A1(n1495), .B0(n1438), .Y(Data_array_SWR[21])
);
OAI21XLTS U1526 ( .A0(n2192), .A1(n835), .B0(n1357), .Y(Data_array_SWR[23])
);
NAND3XLTS U1527 ( .A(n2220), .B(n2219), .C(n2218), .Y(LZD_raw_out_EWR[3]) );
NAND2BXLTS U1528 ( .AN(n1615), .B(n1614), .Y(n1616) );
NAND2BXLTS U1529 ( .AN(n1668), .B(n1667), .Y(n1669) );
NOR2XLTS U1530 ( .A(n1664), .B(n1919), .Y(n1665) );
NAND2BXLTS U1531 ( .AN(n1805), .B(n1804), .Y(n1806) );
AO22XLTS U1532 ( .A0(n2178), .A1(intDX_EWSW[60]), .B0(n2177), .B1(
intDY_EWSW[60]), .Y(DMP_INIT_EWSW[60]) );
AO22XLTS U1533 ( .A0(n2178), .A1(intDX_EWSW[59]), .B0(n2167), .B1(
intDY_EWSW[59]), .Y(DMP_INIT_EWSW[59]) );
AO22XLTS U1534 ( .A0(n2178), .A1(intDX_EWSW[58]), .B0(n2162), .B1(
intDY_EWSW[58]), .Y(DMP_INIT_EWSW[58]) );
OR2X1TS U1535 ( .A(n916), .B(n917), .Y(n853) );
OR2X1TS U1536 ( .A(n918), .B(n919), .Y(n855) );
OAI21X1TS U1537 ( .A0(n1125), .A1(n2411), .B0(n1124), .Y(n998) );
OAI21X1TS U1538 ( .A0(n1125), .A1(n2407), .B0(n1085), .Y(n1086) );
OAI21X1TS U1539 ( .A0(n1125), .A1(n2408), .B0(n1124), .Y(n1126) );
NAND2X2TS U1540 ( .A(bit_shift_SHT2), .B(shift_value_SHT2_EWR[3]), .Y(n1124)
);
INVX1TS U1541 ( .A(n1154), .Y(n1145) );
INVX1TS U1542 ( .A(n1235), .Y(n1265) );
INVX1TS U1543 ( .A(n1241), .Y(n1250) );
INVX1TS U1544 ( .A(n1238), .Y(n1256) );
NOR4X2TS U1545 ( .A(n2011), .B(n2084), .C(n2096), .D(n2088), .Y(n2144) );
BUFX4TS U1546 ( .A(n2500), .Y(n2501) );
BUFX4TS U1547 ( .A(n1123), .Y(n2531) );
BUFX4TS U1548 ( .A(n1123), .Y(n2516) );
BUFX4TS U1549 ( .A(n1123), .Y(n2500) );
BUFX4TS U1550 ( .A(n838), .Y(n2521) );
BUFX4TS U1551 ( .A(n2522), .Y(n2509) );
BUFX4TS U1552 ( .A(n2516), .Y(n2511) );
BUFX4TS U1553 ( .A(n2531), .Y(n2507) );
BUFX4TS U1554 ( .A(n2530), .Y(n2524) );
BUFX4TS U1555 ( .A(n2531), .Y(n2515) );
OAI32X1TS U1556 ( .A0(n1317), .A1(Raw_mant_NRM_SWR[0]), .A2(
Raw_mant_NRM_SWR[1]), .B0(n1316), .B1(n1317), .Y(n1318) );
AOI211X1TS U1557 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n950), .B0(n1317), .C0(
n1333), .Y(n952) );
AOI32X4TS U1558 ( .A0(n2249), .A1(n940), .A2(n2354), .B0(n1110), .B1(n940),
.Y(n1317) );
BUFX4TS U1559 ( .A(n2500), .Y(n2499) );
BUFX4TS U1560 ( .A(n838), .Y(n2490) );
BUFX4TS U1561 ( .A(n2500), .Y(n2496) );
BUFX4TS U1562 ( .A(n839), .Y(n2489) );
BUFX4TS U1563 ( .A(n840), .Y(n2505) );
BUFX4TS U1564 ( .A(n2498), .Y(n2504) );
BUFX4TS U1565 ( .A(n838), .Y(n2503) );
BUFX4TS U1566 ( .A(n2516), .Y(n2519) );
BUFX4TS U1567 ( .A(n2530), .Y(n2520) );
BUFX4TS U1568 ( .A(n2516), .Y(n2528) );
BUFX4TS U1569 ( .A(n2531), .Y(n2506) );
BUFX4TS U1570 ( .A(n1123), .Y(n2491) );
BUFX4TS U1571 ( .A(n838), .Y(n2485) );
BUFX4TS U1572 ( .A(n2500), .Y(n2494) );
BUFX4TS U1573 ( .A(n2486), .Y(n2488) );
BUFX4TS U1574 ( .A(n2492), .Y(n2508) );
BUFX4TS U1575 ( .A(n838), .Y(n2525) );
BUFX4TS U1576 ( .A(n2522), .Y(n2514) );
BUFX6TS U1577 ( .A(n2492), .Y(n2529) );
BUFX4TS U1578 ( .A(n2492), .Y(n2517) );
AOI21X2TS U1579 ( .A0(n1206), .A1(Data_array_SWR[87]), .B0(n1199), .Y(n1511)
);
INVX4TS U1580 ( .A(n1021), .Y(n1206) );
INVX2TS U1581 ( .A(n2433), .Y(n872) );
NOR2X4TS U1582 ( .A(n1508), .B(n1216), .Y(n1231) );
INVX2TS U1583 ( .A(inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n873) );
AOI222X4TS U1584 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[26]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[26]), .C0(Raw_mant_NRM_SWR[28]), .C1(n2533), .Y(n2188) );
AOI222X4TS U1585 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[24]), .B0(
Raw_mant_NRM_SWR[26]), .B1(n2533), .C0(Raw_mant_NRM_SWR[28]), .C1(
n2221), .Y(n2192) );
AOI211XLTS U1586 ( .A0(Raw_mant_NRM_SWR[26]), .A1(n2211), .B0(n2210), .C0(
n2209), .Y(n2212) );
INVX2TS U1587 ( .A(intDY_EWSW[7]), .Y(n878) );
INVX2TS U1588 ( .A(intDY_EWSW[5]), .Y(n879) );
OAI221X1TS U1589 ( .A0(n2391), .A1(intDY_EWSW[49]), .B0(n2402), .B1(
intDY_EWSW[54]), .C0(n1966), .Y(n1967) );
OAI211X2TS U1590 ( .A0(intDY_EWSW[12]), .A1(n2372), .B0(n2055), .C0(n2029),
.Y(n2059) );
AOI221X1TS U1591 ( .A0(n2378), .A1(intDY_EWSW[15]), .B0(intDY_EWSW[12]),
.B1(n2372), .C0(n1971), .Y(n1978) );
OAI211X2TS U1592 ( .A0(intDY_EWSW[20]), .A1(n2373), .B0(n2075), .C0(n2028),
.Y(n2068) );
AOI221X1TS U1593 ( .A0(n889), .A1(intDY_EWSW[21]), .B0(intDY_EWSW[20]), .B1(
n2373), .C0(n1997), .Y(n1998) );
OAI211X2TS U1594 ( .A0(intDY_EWSW[28]), .A1(n2375), .B0(n2027), .C0(n2018),
.Y(n2078) );
AOI221X1TS U1595 ( .A0(n890), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[28]), .B1(
n2375), .C0(n1996), .Y(n1999) );
CLKINVX6TS U1596 ( .A(n1768), .Y(n1919) );
INVX2TS U1597 ( .A(n868), .Y(n883) );
INVX2TS U1598 ( .A(n869), .Y(n884) );
INVX2TS U1599 ( .A(n871), .Y(n885) );
AOI211XLTS U1600 ( .A0(n929), .A1(n913), .B0(Raw_mant_NRM_SWR[48]), .C0(
Raw_mant_NRM_SWR[47]), .Y(n930) );
OAI21X2TS U1601 ( .A0(n2356), .A1(n1366), .B0(n1365), .Y(n1443) );
OAI21X2TS U1602 ( .A0(n2328), .A1(n1366), .B0(n1352), .Y(n1500) );
OAI21X2TS U1603 ( .A0(n1362), .A1(n1366), .B0(n1361), .Y(n1405) );
INVX2TS U1604 ( .A(n850), .Y(n887) );
OAI21X2TS U1605 ( .A0(n1305), .A1(shift_value_SHT2_EWR[4]), .B0(n1257), .Y(
n1292) );
CLKINVX3TS U1606 ( .A(n1521), .Y(n1257) );
CLKINVX6TS U1607 ( .A(n1385), .Y(n2183) );
OAI211X2TS U1608 ( .A0(n2414), .A1(n1021), .B0(n1020), .C0(n1033), .Y(n1517)
);
INVX6TS U1609 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1380) );
BUFX4TS U1610 ( .A(n2162), .Y(n2166) );
BUFX6TS U1611 ( .A(n2162), .Y(n2173) );
CLKINVX6TS U1612 ( .A(n1390), .Y(n1488) );
CLKINVX6TS U1613 ( .A(n1390), .Y(n2195) );
OAI21X2TS U1614 ( .A0(n836), .A1(n2249), .B0(n1369), .Y(n1414) );
OAI21X2TS U1615 ( .A0(n836), .A1(n2342), .B0(n1355), .Y(n1437) );
OAI21X2TS U1616 ( .A0(n836), .A1(n2328), .B0(n1375), .Y(n1410) );
OAI21X2TS U1617 ( .A0(n836), .A1(n2341), .B0(n1358), .Y(n1456) );
OAI21X2TS U1618 ( .A0(n836), .A1(n2356), .B0(n1349), .Y(n1471) );
OAI21X2TS U1619 ( .A0(n836), .A1(n1362), .B0(n1346), .Y(n1482) );
OAI21X2TS U1620 ( .A0(n836), .A1(n2320), .B0(n1378), .Y(n1450) );
INVX6TS U1621 ( .A(n836), .Y(n2221) );
NOR2X2TS U1622 ( .A(ADD_OVRFLW_NRM), .B(n915), .Y(n2534) );
BUFX4TS U1623 ( .A(n985), .Y(n1200) );
CLKINVX6TS U1624 ( .A(n2162), .Y(n2170) );
CLKINVX6TS U1625 ( .A(n2162), .Y(n2169) );
BUFX6TS U1626 ( .A(n1342), .Y(n2533) );
INVX3TS U1627 ( .A(n1098), .Y(n1260) );
CLKINVX6TS U1628 ( .A(n1510), .Y(n1262) );
INVX3TS U1629 ( .A(n1169), .Y(n1129) );
INVX4TS U1630 ( .A(n2176), .Y(n2161) );
BUFX3TS U1631 ( .A(n2162), .Y(n2176) );
CLKINVX6TS U1632 ( .A(n2162), .Y(n2174) );
CLKINVX3TS U1633 ( .A(n2162), .Y(n2171) );
INVX6TS U1634 ( .A(n1305), .Y(n1508) );
BUFX6TS U1635 ( .A(left_right_SHT2), .Y(n1305) );
NAND2X2TS U1636 ( .A(bit_shift_SHT2), .B(n1208), .Y(n1033) );
BUFX6TS U1637 ( .A(n1073), .Y(n1208) );
INVX2TS U1638 ( .A(n852), .Y(busy) );
INVX2TS U1639 ( .A(n870), .Y(n893) );
INVX2TS U1640 ( .A(n842), .Y(n895) );
AOI222X4TS U1641 ( .A0(n1208), .A1(n896), .B0(n1206), .B1(Data_array_SWR[67]), .C0(n1177), .C1(Data_array_SWR[70]), .Y(n1218) );
INVX2TS U1642 ( .A(n866), .Y(n896) );
AOI21X2TS U1643 ( .A0(n1208), .A1(Data_array_SWR[78]), .B0(n1086), .Y(n1195)
);
AOI21X2TS U1644 ( .A0(n1206), .A1(Data_array_SWR[86]), .B0(n998), .Y(n1506)
);
INVX2TS U1645 ( .A(n867), .Y(n897) );
AOI21X2TS U1646 ( .A0(n1206), .A1(Data_array_SWR[88]), .B0(n1199), .Y(n1214)
);
INVX2TS U1647 ( .A(n856), .Y(n898) );
INVX2TS U1648 ( .A(n859), .Y(n899) );
INVX2TS U1649 ( .A(n843), .Y(n900) );
INVX2TS U1650 ( .A(n848), .Y(n901) );
INVX2TS U1651 ( .A(n846), .Y(n902) );
INVX2TS U1652 ( .A(n847), .Y(n903) );
INVX2TS U1653 ( .A(n858), .Y(n904) );
INVX2TS U1654 ( .A(n865), .Y(n905) );
INVX2TS U1655 ( .A(n863), .Y(n906) );
INVX2TS U1656 ( .A(n864), .Y(n907) );
INVX2TS U1657 ( .A(n862), .Y(n908) );
INVX2TS U1658 ( .A(n845), .Y(n909) );
INVX2TS U1659 ( .A(n861), .Y(n910) );
INVX2TS U1660 ( .A(n844), .Y(n911) );
INVX2TS U1661 ( .A(n841), .Y(n912) );
AOI32X1TS U1662 ( .A0(n2412), .A1(n2086), .A2(intDY_EWSW[58]), .B0(
intDY_EWSW[59]), .B1(n2273), .Y(n2087) );
OAI221XLTS U1663 ( .A0(n2412), .A1(intDY_EWSW[58]), .B0(n2273), .B1(
intDY_EWSW[59]), .C0(n1942), .Y(n1953) );
NOR4X1TS U1664 ( .A(n913), .B(Raw_mant_NRM_SWR[45]), .C(Raw_mant_NRM_SWR[46]), .D(n2207), .Y(n934) );
NOR3X1TS U1665 ( .A(n913), .B(Raw_mant_NRM_SWR[45]), .C(Raw_mant_NRM_SWR[46]), .Y(n2208) );
OAI221X1TS U1666 ( .A0(n2410), .A1(intDY_EWSW[62]), .B0(n2413), .B1(
intDY_EWSW[60]), .C0(n1955), .Y(n1962) );
NOR4X2TS U1667 ( .A(Raw_mant_NRM_SWR[14]), .B(Raw_mant_NRM_SWR[12]), .C(
Raw_mant_NRM_SWR[13]), .D(n976), .Y(n1308) );
INVX2TS U1668 ( .A(n849), .Y(n913) );
NOR2X2TS U1669 ( .A(Raw_mant_NRM_SWR[39]), .B(Raw_mant_NRM_SWR[40]), .Y(n955) );
NOR4X1TS U1670 ( .A(Raw_mant_NRM_SWR[16]), .B(Raw_mant_NRM_SWR[18]), .C(
Raw_mant_NRM_SWR[17]), .D(Raw_mant_NRM_SWR[14]), .Y(n1311) );
INVX2TS U1671 ( .A(n854), .Y(n914) );
OAI221X1TS U1672 ( .A0(n2394), .A1(intDY_EWSW[51]), .B0(n2400), .B1(
intDY_EWSW[48]), .C0(n1957), .Y(n1960) );
AOI211X1TS U1673 ( .A0(n1117), .A1(Raw_mant_NRM_SWR[34]), .B0(n1334), .C0(
n1116), .Y(n1121) );
OAI221X1TS U1674 ( .A0(intDX_EWSW[39]), .A1(n2405), .B0(n2272), .B1(
intDY_EWSW[39]), .C0(n1941), .Y(n1954) );
INVX1TS U1675 ( .A(n1307), .Y(enable_Pipeline_input) );
NOR2XLTS U1676 ( .A(Data_array_SWR[76]), .B(n1002), .Y(n916) );
NOR2XLTS U1677 ( .A(n1208), .B(n1002), .Y(n917) );
AOI21X2TS U1678 ( .A0(n1207), .A1(Data_array_SWR[72]), .B0(n857), .Y(n1288)
);
AOI211XLTS U1679 ( .A0(intDX_EWSW[16]), .A1(n2445), .B0(n2063), .C0(n2069),
.Y(n2060) );
OAI21X2TS U1680 ( .A0(intDY_EWSW[18]), .A1(n2172), .B0(n2065), .Y(n2069) );
NOR2XLTS U1681 ( .A(Data_array_SWR[79]), .B(n1037), .Y(n918) );
NOR2XLTS U1682 ( .A(n1208), .B(n1037), .Y(n919) );
OAI21X1TS U1683 ( .A0(n1169), .A1(n2418), .B0(n1036), .Y(n1037) );
OAI221X1TS U1684 ( .A0(n2268), .A1(intDY_EWSW[32]), .B0(n2396), .B1(
intDY_EWSW[33]), .C0(n1943), .Y(n1952) );
OAI221XLTS U1685 ( .A0(n2392), .A1(intDY_EWSW[53]), .B0(n2399), .B1(
intDY_EWSW[10]), .C0(n1956), .Y(n1961) );
NOR2X4TS U1686 ( .A(n1305), .B(n1216), .Y(n1279) );
OAI221X1TS U1687 ( .A0(n2267), .A1(intDY_EWSW[55]), .B0(n2401), .B1(
intDY_EWSW[52]), .C0(n1963), .Y(n1970) );
NAND2X2TS U1688 ( .A(n2349), .B(shift_value_SHT2_EWR[2]), .Y(n1125) );
AOI211X2TS U1689 ( .A0(intDX_EWSW[44]), .A1(n2464), .B0(n2098), .C0(n2108),
.Y(n2106) );
OAI21X2TS U1690 ( .A0(intDY_EWSW[46]), .A1(n2403), .B0(n2097), .Y(n2108) );
OAI21X2TS U1691 ( .A0(n836), .A1(n2247), .B0(n1343), .Y(n1493) );
CLKINVX6TS U1692 ( .A(n1385), .Y(n2189) );
OAI21XLTS U1693 ( .A0(n1491), .A1(n1495), .B0(n1472), .Y(Data_array_SWR[17])
);
OAI21XLTS U1694 ( .A0(n1496), .A1(n1495), .B0(n1494), .Y(Data_array_SWR[14])
);
OAI21XLTS U1695 ( .A0(n1498), .A1(n1495), .B0(n1474), .Y(Data_array_SWR[13])
);
CLKINVX6TS U1696 ( .A(n1021), .Y(n1133) );
CLKINVX6TS U1697 ( .A(n1768), .Y(n1922) );
AOI31XLTS U1698 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n2211), .A2(n2334), .B0(
n964), .Y(n966) );
OAI31X4TS U1699 ( .A0(Raw_mant_NRM_SWR[51]), .A1(Raw_mant_NRM_SWR[52]), .A2(
n931), .B0(n933), .Y(n954) );
NOR2BX2TS U1700 ( .AN(Raw_mant_NRM_SWR[28]), .B(n1329), .Y(n1334) );
OAI32X1TS U1701 ( .A0(n1119), .A1(Raw_mant_NRM_SWR[12]), .A2(
Raw_mant_NRM_SWR[14]), .B0(n1118), .B1(n1119), .Y(n1120) );
NOR2X2TS U1702 ( .A(shift_value_SHT2_EWR[5]), .B(shift_value_SHT2_EWR[4]),
.Y(n1519) );
NAND2X2TS U1703 ( .A(shift_value_SHT2_EWR[4]), .B(n2353), .Y(n1194) );
NAND2X2TS U1704 ( .A(shift_value_SHT2_EWR[5]), .B(shift_value_SHT2_EWR[4]),
.Y(n1203) );
OAI21X2TS U1705 ( .A0(shift_value_SHT2_EWR[4]), .A1(n1508), .B0(n1257), .Y(
n1228) );
OAI21XLTS U1706 ( .A0(intDX_EWSW[1]), .A1(n2478), .B0(intDX_EWSW[0]), .Y(
n2032) );
OAI21XLTS U1707 ( .A0(intDY_EWSW[35]), .A1(n2381), .B0(intDY_EWSW[34]), .Y(
n2118) );
NOR2XLTS U1708 ( .A(n2135), .B(intDX_EWSW[48]), .Y(n2136) );
NOR2XLTS U1709 ( .A(n2098), .B(intDX_EWSW[44]), .Y(n2099) );
OAI21XLTS U1710 ( .A0(intDY_EWSW[55]), .A1(n2142), .B0(intDY_EWSW[54]), .Y(
n2143) );
NOR2XLTS U1711 ( .A(Raw_mant_NRM_SWR[14]), .B(Raw_mant_NRM_SWR[13]), .Y(n937) );
AOI21X1TS U1712 ( .A0(DMP_SFG[5]), .A1(DmP_mant_SFG_SWR[7]), .B0(n1900), .Y(
n1526) );
OAI211XLTS U1713 ( .A0(n1203), .A1(n1214), .B0(n1041), .C0(n1040), .Y(n1042)
);
AOI21X1TS U1714 ( .A0(DMP_SFG[9]), .A1(DmP_mant_SFG_SWR[11]), .B0(n1874),
.Y(n1530) );
AOI21X1TS U1715 ( .A0(DMP_SFG[17]), .A1(DmP_mant_SFG_SWR[19]), .B0(n1823),
.Y(n1538) );
NOR2XLTS U1716 ( .A(n1508), .B(n1194), .Y(n1081) );
NOR2XLTS U1717 ( .A(n1775), .B(n1919), .Y(n1776) );
OR2X1TS U1718 ( .A(n1379), .B(n2421), .Y(n1339) );
NOR2XLTS U1719 ( .A(Raw_mant_NRM_SWR[4]), .B(n2249), .Y(n977) );
OAI2BB1X1TS U1720 ( .A0N(DmP_mant_SFG_SWR[52]), .A1N(DMP_SFG[50]), .B0(n1571), .Y(n1613) );
NOR2XLTS U1721 ( .A(n1735), .B(n1919), .Y(n1736) );
NOR2XLTS U1722 ( .A(n1841), .B(n1934), .Y(n1842) );
OAI211XLTS U1723 ( .A0(n873), .A1(n1939), .B0(n2222), .C0(beg_OP), .Y(n1307)
);
NOR2XLTS U1724 ( .A(n1877), .B(n1876), .Y(n1878) );
NOR2XLTS U1725 ( .A(n1798), .B(n1797), .Y(n1799) );
OAI21XLTS U1726 ( .A0(n1923), .A1(n1922), .B0(n1921), .Y(n1927) );
NOR2XLTS U1727 ( .A(n1661), .B(n1660), .Y(n1662) );
NOR2XLTS U1728 ( .A(n1811), .B(n1810), .Y(n1812) );
OAI21XLTS U1729 ( .A0(n1882), .A1(n1922), .B0(n1881), .Y(n1886) );
OAI21XLTS U1730 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(n2222), .B0(
n1939), .Y(n830) );
OAI211XLTS U1731 ( .A0(n1305), .A1(n1176), .B0(n1175), .C0(n1303), .Y(
sftr_odat_SHT2_SWR[0]) );
OAI21XLTS U1732 ( .A0(n1435), .A1(n1495), .B0(n1422), .Y(Data_array_SWR[22])
);
OR2X1TS U1733 ( .A(n2484), .B(exp_rslt_NRM2_EW1[3]), .Y(
formatted_number_W[55]) );
XNOR2X1TS U1734 ( .A(DP_OP_15J206_122_2221_n1), .B(ADD_OVRFLW_NRM2), .Y(n926) );
AND4X1TS U1735 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
exp_rslt_NRM2_EW1[0]), .D(exp_rslt_NRM2_EW1[1]), .Y(n921) );
AND4X1TS U1736 ( .A(exp_rslt_NRM2_EW1[6]), .B(exp_rslt_NRM2_EW1[5]), .C(
exp_rslt_NRM2_EW1[4]), .D(n921), .Y(n922) );
AND4X1TS U1737 ( .A(exp_rslt_NRM2_EW1[9]), .B(exp_rslt_NRM2_EW1[8]), .C(
exp_rslt_NRM2_EW1[7]), .D(n922), .Y(n923) );
AND3X1TS U1738 ( .A(n926), .B(exp_rslt_NRM2_EW1[10]), .C(n923), .Y(
array_comparators_GTComparator_N0) );
OR4X2TS U1739 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
exp_rslt_NRM2_EW1[0]), .D(exp_rslt_NRM2_EW1[1]), .Y(n924) );
OR4X2TS U1740 ( .A(exp_rslt_NRM2_EW1[6]), .B(exp_rslt_NRM2_EW1[5]), .C(
exp_rslt_NRM2_EW1[4]), .D(n924), .Y(n925) );
NOR4X1TS U1741 ( .A(exp_rslt_NRM2_EW1[9]), .B(exp_rslt_NRM2_EW1[8]), .C(
exp_rslt_NRM2_EW1[7]), .D(n925), .Y(n927) );
NOR3BX1TS U1742 ( .AN(n927), .B(n926), .C(exp_rslt_NRM2_EW1[10]), .Y(n928)
);
BUFX3TS U1743 ( .A(n928), .Y(n2484) );
NOR2XLTS U1744 ( .A(Raw_mant_NRM_SWR[45]), .B(Raw_mant_NRM_SWR[46]), .Y(n929) );
NOR3XLTS U1745 ( .A(Raw_mant_NRM_SWR[49]), .B(Raw_mant_NRM_SWR[50]), .C(n930), .Y(n931) );
NOR2X1TS U1746 ( .A(n886), .B(n895), .Y(n933) );
NAND2X2TS U1747 ( .A(n1114), .B(n1115), .Y(n2207) );
INVX2TS U1748 ( .A(Raw_mant_NRM_SWR[47]), .Y(n1362) );
NOR2X2TS U1749 ( .A(Raw_mant_NRM_SWR[43]), .B(n951), .Y(n1107) );
NOR2X2TS U1750 ( .A(Raw_mant_NRM_SWR[33]), .B(n970), .Y(n1113) );
NAND2BX2TS U1751 ( .AN(Raw_mant_NRM_SWR[30]), .B(n1324), .Y(n1329) );
AOI22X1TS U1752 ( .A0(n1334), .A1(n2246), .B0(n936), .B1(n935), .Y(n953) );
NOR4X2TS U1753 ( .A(Raw_mant_NRM_SWR[28]), .B(n887), .C(Raw_mant_NRM_SWR[29]), .D(n1329), .Y(n2211) );
NOR2BX2TS U1754 ( .AN(n971), .B(Raw_mant_NRM_SWR[21]), .Y(n947) );
AOI32X1TS U1755 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n963), .A2(n937), .B0(
Raw_mant_NRM_SWR[15]), .B1(n963), .Y(n938) );
NAND2X1TS U1756 ( .A(n1308), .B(Raw_mant_NRM_SWR[11]), .Y(n978) );
NAND2X1TS U1757 ( .A(n938), .B(n978), .Y(n939) );
NOR2X2TS U1758 ( .A(Raw_mant_NRM_SWR[9]), .B(n1320), .Y(n2217) );
NOR2X1TS U1759 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .Y(n1312)
);
NOR3BX2TS U1760 ( .AN(n2217), .B(n882), .C(Raw_mant_NRM_SWR[7]), .Y(n1313)
);
NOR2X2TS U1761 ( .A(n914), .B(n1336), .Y(n1316) );
NAND2X1TS U1762 ( .A(n1316), .B(Raw_mant_NRM_SWR[0]), .Y(n949) );
NOR2X1TS U1763 ( .A(n1112), .B(n2341), .Y(n964) );
NAND2X1TS U1764 ( .A(n947), .B(Raw_mant_NRM_SWR[19]), .Y(n972) );
OAI2BB1X1TS U1765 ( .A0N(n941), .A1N(Raw_mant_NRM_SWR[24]), .B0(n972), .Y(
n2210) );
NOR2XLTS U1766 ( .A(Raw_mant_NRM_SWR[28]), .B(n1329), .Y(n942) );
NAND2X1TS U1767 ( .A(n942), .B(n887), .Y(n975) );
OAI21XLTS U1768 ( .A0(Raw_mant_NRM_SWR[31]), .A1(Raw_mant_NRM_SWR[32]), .B0(
n1113), .Y(n945) );
OAI21XLTS U1769 ( .A0(Raw_mant_NRM_SWR[35]), .A1(Raw_mant_NRM_SWR[36]), .B0(
n943), .Y(n944) );
NOR3X1TS U1770 ( .A(n964), .B(n2210), .C(n946), .Y(n948) );
NAND2X1TS U1771 ( .A(n947), .B(Raw_mant_NRM_SWR[20]), .Y(n1109) );
OAI211X1TS U1772 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n949), .B0(n948), .C0(n1109), .Y(n1333) );
NAND4X1TS U1773 ( .A(n954), .B(n953), .C(n952), .D(n965), .Y(
LZD_raw_out_EWR[1]) );
INVX2TS U1774 ( .A(n2207), .Y(n960) );
NAND4XLTS U1775 ( .A(n955), .B(n1107), .C(Raw_mant_NRM_SWR[37]), .D(n2285),
.Y(n958) );
AOI21X1TS U1776 ( .A0(Raw_mant_NRM_SWR[49]), .A1(n2329), .B0(
Raw_mant_NRM_SWR[51]), .Y(n956) );
AOI2BB1XLTS U1777 ( .A0N(Raw_mant_NRM_SWR[52]), .A1N(n956), .B0(n895), .Y(
n957) );
OAI22X1TS U1778 ( .A0(n958), .A1(Raw_mant_NRM_SWR[38]), .B0(n886), .B1(n957),
.Y(n959) );
AOI31XLTS U1779 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n960), .A2(n2335), .B0(n959), .Y(n961) );
OAI31X1TS U1780 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n2350), .A2(n1310), .B0(
n961), .Y(n962) );
AOI21X1TS U1781 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n963), .B0(n962), .Y(n981)
);
AOI21X1TS U1782 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n2333), .B0(
Raw_mant_NRM_SWR[9]), .Y(n967) );
OAI211X1TS U1783 ( .A0(n967), .A1(n1320), .B0(n966), .C0(n965), .Y(n2216) );
OAI22X1TS U1784 ( .A0(n2342), .A1(n969), .B0(n2207), .B1(n1362), .Y(n974) );
OA22X1TS U1785 ( .A0(n2338), .A1(n970), .B0(n1329), .B1(n2246), .Y(n1328) );
OAI211X1TS U1786 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n972), .B0(n1328), .C0(
n1321), .Y(n973) );
NOR4BX1TS U1787 ( .AN(n975), .B(n2205), .C(n974), .D(n973), .Y(n979) );
OAI211X1TS U1788 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n977), .B0(n1313), .C0(
n2336), .Y(n2218) );
NAND4X1TS U1789 ( .A(n979), .B(n978), .C(n1309), .D(n2218), .Y(n1119) );
AOI211X1TS U1790 ( .A0(n1316), .A1(Raw_mant_NRM_SWR[1]), .B0(n2216), .C0(
n1119), .Y(n980) );
OAI211X1TS U1791 ( .A0(n2356), .A1(n1325), .B0(n981), .C0(n980), .Y(
LZD_raw_out_EWR[0]) );
NAND2X2TS U1792 ( .A(Shift_reg_FLAGS_7[1]), .B(ADD_OVRFLW_NRM), .Y(n1366) );
AOI33XLTS U1793 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[2]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n2470), .B1(n873), .B2(n2225),
.Y(n832) );
INVX2TS U1794 ( .A(n1519), .Y(n1217) );
NAND3XLTS U1795 ( .A(bit_shift_SHT2), .B(n1508), .C(n1217), .Y(n1008) );
AOI22X1TS U1796 ( .A0(Data_array_SWR[63]), .A1(n982), .B0(n908), .B1(n983),
.Y(n995) );
OR2X2TS U1797 ( .A(shift_value_SHT2_EWR[2]), .B(n2349), .Y(n1169) );
NOR2XLTS U1798 ( .A(n1217), .B(n1169), .Y(n984) );
BUFX4TS U1799 ( .A(n984), .Y(n1215) );
NAND2X1TS U1800 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1179) );
NOR2XLTS U1801 ( .A(n1217), .B(n1179), .Y(n985) );
AOI22X1TS U1802 ( .A0(Data_array_SWR[67]), .A1(n1215), .B0(
Data_array_SWR[70]), .B1(n1200), .Y(n994) );
BUFX3TS U1803 ( .A(n1177), .Y(n1130) );
AOI22X1TS U1804 ( .A0(n896), .A1(n1130), .B0(n1206), .B1(Data_array_SWR[71]),
.Y(n988) );
INVX2TS U1805 ( .A(n1179), .Y(n1073) );
INVX4TS U1806 ( .A(n1169), .Y(n1207) );
AOI22X1TS U1807 ( .A0(n1208), .A1(n903), .B0(n1207), .B1(Data_array_SWR[78]),
.Y(n987) );
NAND2X1TS U1808 ( .A(n988), .B(n987), .Y(n1259) );
AOI22X1TS U1809 ( .A0(n1133), .A1(n906), .B0(n1129), .B1(n911), .Y(n991) );
AOI22X1TS U1810 ( .A0(n1208), .A1(Data_array_SWR[87]), .B0(n1130), .B1(n907),
.Y(n990) );
NAND2X1TS U1811 ( .A(n991), .B(n990), .Y(n1235) );
AOI22X1TS U1812 ( .A0(n986), .A1(n1259), .B0(n989), .B1(n1235), .Y(n993) );
NAND2X1TS U1813 ( .A(shift_value_SHT2_EWR[5]), .B(bit_shift_SHT2), .Y(n1521)
);
NAND4XLTS U1814 ( .A(n995), .B(n994), .C(n993), .D(n992), .Y(n1105) );
OR2X2TS U1815 ( .A(n1305), .B(n1217), .Y(n1287) );
CLKBUFX2TS U1816 ( .A(n1287), .Y(n1098) );
INVX4TS U1817 ( .A(n1098), .Y(n1222) );
AOI22X1TS U1818 ( .A0(n1133), .A1(n909), .B0(n1177), .B1(Data_array_SWR[86]),
.Y(n996) );
OAI211X2TS U1819 ( .A0(n2411), .A1(n1169), .B0(n996), .C0(n1033), .Y(n1258)
);
AOI22X1TS U1820 ( .A0(n1305), .A1(n1105), .B0(n1222), .B1(n1258), .Y(n997)
);
NAND2X1TS U1821 ( .A(n837), .B(n997), .Y(sftr_odat_SHT2_SWR[46]) );
AOI22X1TS U1822 ( .A0(n1133), .A1(n902), .B0(n1177), .B1(n905), .Y(n1000) );
AOI22X1TS U1823 ( .A0(n1208), .A1(n909), .B0(n1207), .B1(Data_array_SWR[82]),
.Y(n999) );
NAND2X1TS U1824 ( .A(n1000), .B(n999), .Y(n1084) );
AOI22X1TS U1825 ( .A0(n1133), .A1(n898), .B0(n1177), .B1(n900), .Y(n1001) );
OAI2BB1X1TS U1826 ( .A0N(n1207), .A1N(Data_array_SWR[73]), .B0(n1001), .Y(
n1002) );
AOI22X1TS U1827 ( .A0(n982), .A1(Data_array_SWR[57]), .B0(n1200), .B1(
Data_array_SWR[65]), .Y(n1004) );
AOI22X1TS U1828 ( .A0(n1215), .A1(n884), .B0(n983), .B1(Data_array_SWR[61]),
.Y(n1003) );
OAI211XLTS U1829 ( .A0(n853), .A1(n1194), .B0(n1004), .C0(n1003), .Y(n1005)
);
AOI21X1TS U1830 ( .A0(n989), .A1(n1084), .B0(n1005), .Y(n1006) );
OAI21X1TS U1831 ( .A0(n1506), .A1(n1203), .B0(n1006), .Y(n1507) );
INVX2TS U1832 ( .A(n1511), .Y(n1272) );
AOI22X1TS U1833 ( .A0(n1305), .A1(n1507), .B0(n1260), .B1(n1272), .Y(n1007)
);
NAND2X1TS U1834 ( .A(n837), .B(n1007), .Y(sftr_odat_SHT2_SWR[52]) );
AOI22X1TS U1835 ( .A0(n982), .A1(n883), .B0(n983), .B1(Data_array_SWR[64]),
.Y(n1015) );
AOI22X1TS U1836 ( .A0(n1215), .A1(Data_array_SWR[68]), .B0(n1200), .B1(n899),
.Y(n1014) );
AOI22X1TS U1837 ( .A0(n1133), .A1(Data_array_SWR[72]), .B0(n1130), .B1(
Data_array_SWR[75]), .Y(n1010) );
AOI22X1TS U1838 ( .A0(n1208), .A1(n904), .B0(n1129), .B1(Data_array_SWR[79]),
.Y(n1009) );
NAND2X1TS U1839 ( .A(n1010), .B(n1009), .Y(n1251) );
AOI22X1TS U1840 ( .A0(n1133), .A1(n912), .B0(n1129), .B1(n910), .Y(n1012) );
AOI22X1TS U1841 ( .A0(n1208), .A1(Data_array_SWR[88]), .B0(n1177), .B1(
Data_array_SWR[84]), .Y(n1011) );
NAND2X1TS U1842 ( .A(n1012), .B(n1011), .Y(n1238) );
AOI22X1TS U1843 ( .A0(n986), .A1(n1251), .B0(n989), .B1(n1238), .Y(n1013) );
NAND4XLTS U1844 ( .A(n1015), .B(n1014), .C(n1013), .D(n992), .Y(n1103) );
AOI22X1TS U1845 ( .A0(n1130), .A1(n910), .B0(n1129), .B1(Data_array_SWR[88]),
.Y(n1016) );
OAI211X2TS U1846 ( .A0(n2409), .A1(n1021), .B0(n1016), .C0(n1033), .Y(n1253)
);
AOI22X1TS U1847 ( .A0(n1305), .A1(n1103), .B0(n1222), .B1(n1253), .Y(n1017)
);
NAND2X1TS U1848 ( .A(n837), .B(n1017), .Y(sftr_odat_SHT2_SWR[45]) );
AOI22X1TS U1849 ( .A0(n1215), .A1(Data_array_SWR[69]), .B0(n983), .B1(
Data_array_SWR[66]), .Y(n1024) );
AOI22X1TS U1850 ( .A0(n982), .A1(n885), .B0(n1200), .B1(n901), .Y(n1023) );
AOI22X1TS U1851 ( .A0(n1133), .A1(Data_array_SWR[74]), .B0(n1130), .B1(
Data_array_SWR[77]), .Y(n1019) );
AOI22X1TS U1852 ( .A0(n1208), .A1(Data_array_SWR[81]), .B0(n1129), .B1(
Data_array_SWR[80]), .Y(n1018) );
NAND2X1TS U1853 ( .A(n1019), .B(n1018), .Y(n1518) );
AOI22X1TS U1854 ( .A0(n1130), .A1(Data_array_SWR[85]), .B0(n1129), .B1(n897),
.Y(n1020) );
AOI22X1TS U1855 ( .A0(n986), .A1(n1518), .B0(n989), .B1(n1517), .Y(n1022) );
NAND4XLTS U1856 ( .A(n1024), .B(n1023), .C(n1022), .D(n992), .Y(n1162) );
AOI22X1TS U1857 ( .A0(n1305), .A1(n1162), .B0(n1222), .B1(n1517), .Y(n1025)
);
NAND2X1TS U1858 ( .A(n837), .B(n1025), .Y(sftr_odat_SHT2_SWR[43]) );
AOI22X1TS U1859 ( .A0(n982), .A1(n884), .B0(n983), .B1(Data_array_SWR[65]),
.Y(n1032) );
AOI22X1TS U1860 ( .A0(n1215), .A1(n898), .B0(n1200), .B1(n900), .Y(n1031) );
AOI22X1TS U1861 ( .A0(n1133), .A1(Data_array_SWR[73]), .B0(n1130), .B1(
Data_array_SWR[76]), .Y(n1027) );
AOI22X1TS U1862 ( .A0(n1208), .A1(n905), .B0(n1129), .B1(n902), .Y(n1026) );
NAND2X1TS U1863 ( .A(n1027), .B(n1026), .Y(n1246) );
AOI22X1TS U1864 ( .A0(n1208), .A1(Data_array_SWR[89]), .B0(n1206), .B1(
Data_array_SWR[82]), .Y(n1029) );
AOI22X1TS U1865 ( .A0(n1130), .A1(n909), .B0(n1129), .B1(Data_array_SWR[86]),
.Y(n1028) );
NAND2X1TS U1866 ( .A(n1029), .B(n1028), .Y(n1241) );
AOI22X1TS U1867 ( .A0(n986), .A1(n1246), .B0(n989), .B1(n1241), .Y(n1030) );
NAND4XLTS U1868 ( .A(n1032), .B(n1031), .C(n1030), .D(n992), .Y(n1164) );
AOI22X1TS U1869 ( .A0(n1133), .A1(n907), .B0(n1130), .B1(n911), .Y(n1034) );
OAI211X2TS U1870 ( .A0(n2408), .A1(n1169), .B0(n1034), .C0(n1033), .Y(n1245)
);
AOI22X1TS U1871 ( .A0(n1305), .A1(n1164), .B0(n1222), .B1(n1245), .Y(n1035)
);
NAND2X1TS U1872 ( .A(n837), .B(n1035), .Y(sftr_odat_SHT2_SWR[44]) );
AOI22X1TS U1873 ( .A0(n1133), .A1(n899), .B0(n1177), .B1(Data_array_SWR[72]),
.Y(n1036) );
AOI22X1TS U1874 ( .A0(n1133), .A1(n904), .B0(n1177), .B1(n912), .Y(n1039) );
AOI22X1TS U1875 ( .A0(n1208), .A1(n910), .B0(n1207), .B1(Data_array_SWR[84]),
.Y(n1038) );
NAND2X2TS U1876 ( .A(n1039), .B(n1038), .Y(n1285) );
AOI22X1TS U1877 ( .A0(n982), .A1(Data_array_SWR[60]), .B0(n1200), .B1(
Data_array_SWR[68]), .Y(n1041) );
AOI22X1TS U1878 ( .A0(n1215), .A1(Data_array_SWR[64]), .B0(n983), .B1(n883),
.Y(n1040) );
AOI21X1TS U1879 ( .A0(n989), .A1(n1285), .B0(n1042), .Y(n1043) );
OAI21X1TS U1880 ( .A0(n855), .A1(n1194), .B0(n1043), .Y(n1166) );
AOI22X1TS U1881 ( .A0(n1133), .A1(n910), .B0(n1177), .B1(Data_array_SWR[88]),
.Y(n1044) );
NAND2X2TS U1882 ( .A(n1044), .B(n1124), .Y(n1278) );
AOI22X1TS U1883 ( .A0(n1305), .A1(n1166), .B0(n1222), .B1(n1278), .Y(n1045)
);
NAND2X1TS U1884 ( .A(n837), .B(n1045), .Y(sftr_odat_SHT2_SWR[49]) );
AOI22X1TS U1885 ( .A0(n982), .A1(Data_array_SWR[62]), .B0(n1200), .B1(
Data_array_SWR[69]), .Y(n1052) );
AOI22X1TS U1886 ( .A0(n1215), .A1(Data_array_SWR[66]), .B0(n983), .B1(n885),
.Y(n1051) );
AOI22X1TS U1887 ( .A0(n1133), .A1(n901), .B0(n1177), .B1(Data_array_SWR[74]),
.Y(n1047) );
AOI22X1TS U1888 ( .A0(n1208), .A1(Data_array_SWR[80]), .B0(n1207), .B1(
Data_array_SWR[77]), .Y(n1046) );
NAND2X1TS U1889 ( .A(n1047), .B(n1046), .Y(n1141) );
AOI22X1TS U1890 ( .A0(n1208), .A1(n897), .B0(n1206), .B1(Data_array_SWR[81]),
.Y(n1049) );
AOI22X1TS U1891 ( .A0(n1130), .A1(Data_array_SWR[83]), .B0(n1207), .B1(
Data_array_SWR[85]), .Y(n1048) );
NAND2X2TS U1892 ( .A(n1049), .B(n1048), .Y(n1151) );
AOI22X1TS U1893 ( .A0(n986), .A1(n1141), .B0(n989), .B1(n1151), .Y(n1050) );
NAND4XLTS U1894 ( .A(n1052), .B(n1051), .C(n1050), .D(n992), .Y(n1153) );
AOI22X1TS U1895 ( .A0(n1133), .A1(Data_array_SWR[85]), .B0(n1177), .B1(n897),
.Y(n1053) );
NAND2X1TS U1896 ( .A(n1053), .B(n1124), .Y(n1154) );
AOI22X1TS U1897 ( .A0(n1305), .A1(n1153), .B0(n1222), .B1(n1154), .Y(n1054)
);
NAND2X1TS U1898 ( .A(n837), .B(n1054), .Y(sftr_odat_SHT2_SWR[47]) );
AOI22X1TS U1899 ( .A0(n1215), .A1(n899), .B0(n983), .B1(Data_array_SWR[68]),
.Y(n1059) );
AOI22X1TS U1900 ( .A0(n982), .A1(Data_array_SWR[64]), .B0(n1200), .B1(
Data_array_SWR[72]), .Y(n1058) );
AOI22X1TS U1901 ( .A0(n1133), .A1(Data_array_SWR[75]), .B0(n1130), .B1(
Data_array_SWR[79]), .Y(n1056) );
AOI22X1TS U1902 ( .A0(n1073), .A1(n912), .B0(n1129), .B1(n904), .Y(n1055) );
NAND2X1TS U1903 ( .A(n1056), .B(n1055), .Y(n1252) );
AOI22X1TS U1904 ( .A0(n986), .A1(n1252), .B0(n989), .B1(n1253), .Y(n1057) );
NAND4XLTS U1905 ( .A(n1059), .B(n1058), .C(n1057), .D(n992), .Y(n1158) );
AOI22X1TS U1906 ( .A0(n1305), .A1(n1158), .B0(n1222), .B1(n1238), .Y(n1060)
);
NAND2X1TS U1907 ( .A(n837), .B(n1060), .Y(sftr_odat_SHT2_SWR[41]) );
AOI22X1TS U1908 ( .A0(n1215), .A1(n900), .B0(n983), .B1(n898), .Y(n1065) );
AOI22X1TS U1909 ( .A0(n982), .A1(Data_array_SWR[65]), .B0(n1200), .B1(
Data_array_SWR[73]), .Y(n1064) );
AOI22X1TS U1910 ( .A0(n1133), .A1(Data_array_SWR[76]), .B0(n1130), .B1(n902),
.Y(n1062) );
AOI22X1TS U1911 ( .A0(n1208), .A1(Data_array_SWR[82]), .B0(n1129), .B1(n905),
.Y(n1061) );
NAND2X1TS U1912 ( .A(n1062), .B(n1061), .Y(n1261) );
AOI22X1TS U1913 ( .A0(n986), .A1(n1261), .B0(n989), .B1(n1258), .Y(n1063) );
NAND4XLTS U1914 ( .A(n1065), .B(n1064), .C(n1063), .D(n992), .Y(n1156) );
AOI22X1TS U1915 ( .A0(n1305), .A1(n1156), .B0(n1222), .B1(n1235), .Y(n1066)
);
NAND2X1TS U1916 ( .A(n837), .B(n1066), .Y(sftr_odat_SHT2_SWR[40]) );
AOI22X1TS U1917 ( .A0(n982), .A1(Data_array_SWR[66]), .B0(n983), .B1(
Data_array_SWR[69]), .Y(n1071) );
AOI22X1TS U1918 ( .A0(n1215), .A1(n901), .B0(n1200), .B1(Data_array_SWR[74]),
.Y(n1070) );
AOI22X1TS U1919 ( .A0(n1133), .A1(Data_array_SWR[77]), .B0(n1177), .B1(
Data_array_SWR[80]), .Y(n1068) );
AOI22X1TS U1920 ( .A0(n1208), .A1(Data_array_SWR[83]), .B0(n1207), .B1(
Data_array_SWR[81]), .Y(n1067) );
NAND2X1TS U1921 ( .A(n1068), .B(n1067), .Y(n1142) );
AOI22X1TS U1922 ( .A0(n986), .A1(n1142), .B0(n989), .B1(n1154), .Y(n1069) );
NAND4XLTS U1923 ( .A(n1071), .B(n1070), .C(n1069), .D(n992), .Y(n1150) );
AOI22X1TS U1924 ( .A0(n1305), .A1(n1150), .B0(n1222), .B1(n1151), .Y(n1072)
);
NAND2X1TS U1925 ( .A(n837), .B(n1072), .Y(sftr_odat_SHT2_SWR[39]) );
AOI22X1TS U1926 ( .A0(Data_array_SWR[67]), .A1(n983), .B0(n982), .B1(n908),
.Y(n1078) );
AOI22X1TS U1927 ( .A0(Data_array_SWR[70]), .A1(n1215), .B0(
Data_array_SWR[71]), .B1(n1200), .Y(n1077) );
AOI22X1TS U1928 ( .A0(n896), .A1(n1133), .B0(n1177), .B1(Data_array_SWR[78]),
.Y(n1075) );
AOI22X1TS U1929 ( .A0(n1073), .A1(n906), .B0(n1129), .B1(n903), .Y(n1074) );
NAND2X1TS U1930 ( .A(n1075), .B(n1074), .Y(n1247) );
AOI22X1TS U1931 ( .A0(n986), .A1(n1247), .B0(n989), .B1(n1245), .Y(n1076) );
NAND4XLTS U1932 ( .A(n1078), .B(n1077), .C(n1076), .D(n992), .Y(n1160) );
AOI22X1TS U1933 ( .A0(n1305), .A1(n1160), .B0(n1222), .B1(n1241), .Y(n1079)
);
NAND2X1TS U1934 ( .A(n837), .B(n1079), .Y(sftr_odat_SHT2_SWR[42]) );
INVX2TS U1935 ( .A(n989), .Y(n1216) );
NOR2XLTS U1936 ( .A(n1305), .B(n1194), .Y(n1080) );
BUFX4TS U1937 ( .A(n1080), .Y(n1300) );
INVX2TS U1938 ( .A(n1506), .Y(n1271) );
AOI22X1TS U1939 ( .A0(n1231), .A1(n1272), .B0(n1300), .B1(n1271), .Y(n1089)
);
BUFX4TS U1940 ( .A(n1081), .Y(n1290) );
AOI22X1TS U1941 ( .A0(n1133), .A1(n903), .B0(n1177), .B1(n906), .Y(n1083) );
AOI22X1TS U1942 ( .A0(n1208), .A1(n911), .B0(n1207), .B1(n907), .Y(n1082) );
NAND2X2TS U1943 ( .A(n1083), .B(n1082), .Y(n1276) );
INVX2TS U1944 ( .A(n1228), .Y(n1232) );
INVX2TS U1945 ( .A(n1084), .Y(n1274) );
AOI22X1TS U1946 ( .A0(n896), .A1(n1129), .B0(n1206), .B1(Data_array_SWR[70]),
.Y(n1085) );
OAI22X1TS U1947 ( .A0(n1274), .A1(n1287), .B0(n1195), .B1(n1510), .Y(n1087)
);
AOI211X1TS U1948 ( .A0(n1290), .A1(n1276), .B0(n1232), .C0(n1087), .Y(n1088)
);
NAND2X1TS U1949 ( .A(n1089), .B(n1088), .Y(sftr_odat_SHT2_SWR[34]) );
INVX2TS U1950 ( .A(n1214), .Y(n1280) );
AOI22X1TS U1951 ( .A0(n1300), .A1(n1278), .B0(n1280), .B1(n1231), .Y(n1094)
);
AOI22X1TS U1952 ( .A0(n1206), .A1(Data_array_SWR[79]), .B0(n1177), .B1(n904),
.Y(n1090) );
OAI21X1TS U1953 ( .A0(n1179), .A1(n2409), .B0(n1090), .Y(n1091) );
AOI21X2TS U1954 ( .A0(n1207), .A1(n912), .B0(n1091), .Y(n1283) );
OAI22X1TS U1955 ( .A0(n855), .A1(n1510), .B0(n1283), .B1(n1098), .Y(n1092)
);
AOI211X1TS U1956 ( .A0(n1290), .A1(n1285), .B0(n1232), .C0(n1092), .Y(n1093)
);
NAND2X1TS U1957 ( .A(n1094), .B(n1093), .Y(sftr_odat_SHT2_SWR[33]) );
AOI22X1TS U1958 ( .A0(n1280), .A1(n1279), .B0(n1290), .B1(n1278), .Y(n1097)
);
INVX2TS U1959 ( .A(n1292), .Y(n1266) );
OAI22X1TS U1960 ( .A0(n855), .A1(n1287), .B0(n1283), .B1(n1510), .Y(n1095)
);
AOI211X1TS U1961 ( .A0(n1300), .A1(n1285), .B0(n1266), .C0(n1095), .Y(n1096)
);
NAND2X1TS U1962 ( .A(n1097), .B(n1096), .Y(sftr_odat_SHT2_SWR[21]) );
AOI22X1TS U1963 ( .A0(n1279), .A1(n1272), .B0(n1290), .B1(n1271), .Y(n1101)
);
OAI22X1TS U1964 ( .A0(n1274), .A1(n1510), .B0(n1195), .B1(n1098), .Y(n1099)
);
AOI211X1TS U1965 ( .A0(n1300), .A1(n1276), .B0(n1266), .C0(n1099), .Y(n1100)
);
NAND2X1TS U1966 ( .A(n1101), .B(n1100), .Y(sftr_odat_SHT2_SWR[20]) );
NAND2X1TS U1967 ( .A(bit_shift_SHT2), .B(n1305), .Y(n1102) );
INVX2TS U1968 ( .A(n1510), .Y(n1302) );
AOI22X1TS U1969 ( .A0(n1262), .A1(n1253), .B0(n1508), .B1(n1103), .Y(n1104)
);
NAND2X1TS U1970 ( .A(n1303), .B(n1104), .Y(sftr_odat_SHT2_SWR[9]) );
AOI22X1TS U1971 ( .A0(n1262), .A1(n1258), .B0(n1508), .B1(n1105), .Y(n1106)
);
NAND2X1TS U1972 ( .A(n1303), .B(n1106), .Y(sftr_odat_SHT2_SWR[8]) );
OAI21XLTS U1973 ( .A0(Raw_mant_NRM_SWR[40]), .A1(Raw_mant_NRM_SWR[42]), .B0(
n1107), .Y(n1108) );
AOI21X1TS U1974 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1313), .B0(n1111), .Y(n2220) );
NOR2BX1TS U1975 ( .AN(n894), .B(n1112), .Y(n1322) );
AOI22X1TS U1976 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n1113), .B0(n1322), .B1(
n2341), .Y(n1122) );
NOR2BX1TS U1977 ( .AN(n1115), .B(n1114), .Y(n1116) );
NAND4XLTS U1978 ( .A(n2220), .B(n1122), .C(n1121), .D(n1120), .Y(
LZD_raw_out_EWR[2]) );
BUFX3TS U1979 ( .A(n2492), .Y(n2510) );
BUFX3TS U1980 ( .A(n838), .Y(n2513) );
BUFX3TS U1981 ( .A(n2516), .Y(n2512) );
BUFX3TS U1982 ( .A(n2492), .Y(n2526) );
BUFX3TS U1983 ( .A(n2531), .Y(n2527) );
BUFX3TS U1984 ( .A(n2531), .Y(n2518) );
BUFX3TS U1985 ( .A(n2516), .Y(n2523) );
BUFX3TS U1986 ( .A(n1123), .Y(n2487) );
BUFX3TS U1987 ( .A(n2500), .Y(n2495) );
BUFX3TS U1988 ( .A(n838), .Y(n2502) );
AO21X2TS U1989 ( .A0(n1206), .A1(Data_array_SWR[89]), .B0(n1199), .Y(n1291)
);
AOI21X2TS U1990 ( .A0(n1206), .A1(n911), .B0(n1126), .Y(n1298) );
INVX2TS U1991 ( .A(n1298), .Y(n1146) );
AOI22X1TS U1992 ( .A0(n1231), .A1(n1291), .B0(n1300), .B1(n1146), .Y(n1138)
);
AOI22X1TS U1993 ( .A0(n1206), .A1(n900), .B0(n1177), .B1(Data_array_SWR[73]),
.Y(n1128) );
AOI22X1TS U1994 ( .A0(n1208), .A1(n902), .B0(n1207), .B1(Data_array_SWR[76]),
.Y(n1127) );
NAND2X1TS U1995 ( .A(n1128), .B(n1127), .Y(n1296) );
AOI22X1TS U1996 ( .A0(n1133), .A1(Data_array_SWR[78]), .B0(n1129), .B1(n906),
.Y(n1132) );
AOI22X1TS U1997 ( .A0(n1208), .A1(n907), .B0(n1130), .B1(n903), .Y(n1131) );
NAND2X1TS U1998 ( .A(n1132), .B(n1131), .Y(n1221) );
AOI22X1TS U1999 ( .A0(n1302), .A1(n1296), .B0(n1260), .B1(n1221), .Y(n1137)
);
AOI22X1TS U2000 ( .A0(n1133), .A1(n905), .B0(n1207), .B1(n909), .Y(n1135) );
AOI22X1TS U2001 ( .A0(n1208), .A1(Data_array_SWR[86]), .B0(n1177), .B1(
Data_array_SWR[82]), .Y(n1134) );
NAND2X2TS U2002 ( .A(n1135), .B(n1134), .Y(n1289) );
NAND2X1TS U2003 ( .A(n1290), .B(n1289), .Y(n1136) );
NAND4XLTS U2004 ( .A(n1228), .B(n1138), .C(n1137), .D(n1136), .Y(
sftr_odat_SHT2_SWR[32]) );
INVX2TS U2005 ( .A(n1300), .Y(n1282) );
AOI22X1TS U2006 ( .A0(n1262), .A1(n1141), .B0(n1260), .B1(n1142), .Y(n1140)
);
AOI21X1TS U2007 ( .A0(n1290), .A1(n1151), .B0(n1257), .Y(n1139) );
OAI211X1TS U2008 ( .A0(n1145), .A1(n1282), .B0(n1140), .C0(n1139), .Y(
sftr_odat_SHT2_SWR[31]) );
INVX2TS U2009 ( .A(n1290), .Y(n1244) );
AOI22X1TS U2010 ( .A0(n1262), .A1(n1142), .B0(n1260), .B1(n1141), .Y(n1144)
);
AOI21X1TS U2011 ( .A0(n1300), .A1(n1151), .B0(n1257), .Y(n1143) );
OAI211X1TS U2012 ( .A0(n1244), .A1(n1145), .B0(n1144), .C0(n1143), .Y(
sftr_odat_SHT2_SWR[23]) );
AOI22X1TS U2013 ( .A0(n1279), .A1(n1291), .B0(n1290), .B1(n1146), .Y(n1149)
);
AOI22X1TS U2014 ( .A0(n1222), .A1(n1296), .B0(n1302), .B1(n1221), .Y(n1148)
);
AOI21X1TS U2015 ( .A0(n1300), .A1(n1289), .B0(n1266), .Y(n1147) );
NAND3XLTS U2016 ( .A(n1149), .B(n1148), .C(n1147), .Y(sftr_odat_SHT2_SWR[22]) );
AOI22X1TS U2017 ( .A0(n1262), .A1(n1151), .B0(n1508), .B1(n1150), .Y(n1152)
);
NAND2X1TS U2018 ( .A(n1303), .B(n1152), .Y(sftr_odat_SHT2_SWR[15]) );
AOI22X1TS U2019 ( .A0(n1262), .A1(n1154), .B0(n1508), .B1(n1153), .Y(n1155)
);
NAND2X1TS U2020 ( .A(n1303), .B(n1155), .Y(sftr_odat_SHT2_SWR[7]) );
AOI22X1TS U2021 ( .A0(n1262), .A1(n1235), .B0(n1508), .B1(n1156), .Y(n1157)
);
NAND2X1TS U2022 ( .A(n1303), .B(n1157), .Y(sftr_odat_SHT2_SWR[14]) );
AOI22X1TS U2023 ( .A0(n1262), .A1(n1238), .B0(n1508), .B1(n1158), .Y(n1159)
);
NAND2X1TS U2024 ( .A(n1303), .B(n1159), .Y(sftr_odat_SHT2_SWR[13]) );
AOI22X1TS U2025 ( .A0(n1302), .A1(n1241), .B0(n1508), .B1(n1160), .Y(n1161)
);
NAND2X1TS U2026 ( .A(n1303), .B(n1161), .Y(sftr_odat_SHT2_SWR[12]) );
AOI22X1TS U2027 ( .A0(n1302), .A1(n1517), .B0(n1508), .B1(n1162), .Y(n1163)
);
NAND2X1TS U2028 ( .A(n1303), .B(n1163), .Y(sftr_odat_SHT2_SWR[11]) );
AOI22X1TS U2029 ( .A0(n1262), .A1(n1245), .B0(n1508), .B1(n1164), .Y(n1165)
);
NAND2X1TS U2030 ( .A(n1303), .B(n1165), .Y(sftr_odat_SHT2_SWR[10]) );
AOI22X1TS U2031 ( .A0(n1262), .A1(n1278), .B0(n1508), .B1(n1166), .Y(n1167)
);
NAND2X1TS U2032 ( .A(n1303), .B(n1167), .Y(sftr_odat_SHT2_SWR[5]) );
OR2X1TS U2033 ( .A(busy), .B(Shift_reg_FLAGS_7[1]), .Y(n_7_net_) );
NAND2X1TS U2034 ( .A(DmP_EXP_EWSW[52]), .B(n920), .Y(n1168) );
OAI21XLTS U2035 ( .A0(DmP_EXP_EWSW[52]), .A1(n920), .B0(n1168), .Y(
Shift_amount_EXP_EW[0]) );
NAND2X1TS U2036 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n873), .Y(n2222) );
NOR2X1TS U2037 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2225), .Y(n2224) );
INVX2TS U2038 ( .A(n2224), .Y(n1939) );
INVX2TS U2039 ( .A(intadd_470_SUM_0_), .Y(Shift_amount_EXP_EW[1]) );
INVX2TS U2040 ( .A(intadd_470_SUM_1_), .Y(Shift_amount_EXP_EW[2]) );
INVX2TS U2041 ( .A(intadd_470_SUM_2_), .Y(Shift_amount_EXP_EW[3]) );
INVX2TS U2042 ( .A(intadd_470_SUM_3_), .Y(Shift_amount_EXP_EW[4]) );
INVX2TS U2043 ( .A(n1168), .Y(intadd_470_CI) );
OAI32X1TS U2044 ( .A0(n1194), .A1(n1169), .A2(n2407), .B0(n1218), .B1(n1194),
.Y(n1173) );
AOI22X1TS U2045 ( .A0(n1200), .A1(n908), .B0(n983), .B1(Data_array_SWR[59]),
.Y(n1171) );
AOI22X1TS U2046 ( .A0(n1215), .A1(Data_array_SWR[63]), .B0(n982), .B1(
Data_array_SWR[55]), .Y(n1170) );
OAI211XLTS U2047 ( .A0(n1298), .A1(n1203), .B0(n1171), .C0(n1170), .Y(n1172)
);
AOI211X1TS U2048 ( .A0(n989), .A1(n1221), .B0(n1173), .C0(n1172), .Y(n1176)
);
NAND2X1TS U2049 ( .A(n1291), .B(n1222), .Y(n1174) );
OAI211XLTS U2050 ( .A0(n1176), .A1(n1508), .B0(n837), .C0(n1174), .Y(
sftr_odat_SHT2_SWR[54]) );
NAND2X1TS U2051 ( .A(n1291), .B(n1262), .Y(n1175) );
AOI22X1TS U2052 ( .A0(n1206), .A1(Data_array_SWR[68]), .B0(n1177), .B1(n899),
.Y(n1178) );
INVX2TS U2053 ( .A(n1203), .Y(n1185) );
AOI22X1TS U2054 ( .A0(n982), .A1(Data_array_SWR[56]), .B0(n1200), .B1(
Data_array_SWR[64]), .Y(n1181) );
AOI22X1TS U2055 ( .A0(n1215), .A1(n883), .B0(n983), .B1(Data_array_SWR[60]),
.Y(n1180) );
OAI211XLTS U2056 ( .A0(n1283), .A1(n1216), .B0(n1181), .C0(n1180), .Y(n1182)
);
AOI21X1TS U2057 ( .A0(n1185), .A1(n1278), .B0(n1182), .Y(n1183) );
OAI21X1TS U2058 ( .A0(n1288), .A1(n1194), .B0(n1183), .Y(n1212) );
NAND2X1TS U2059 ( .A(n1508), .B(n1212), .Y(n1184) );
OAI211XLTS U2060 ( .A0(n1510), .A1(n1214), .B0(n1303), .C0(n1184), .Y(
sftr_odat_SHT2_SWR[1]) );
OR2X1TS U2061 ( .A(n2484), .B(exp_rslt_NRM2_EW1[0]), .Y(
formatted_number_W[52]) );
OR2X1TS U2062 ( .A(n2484), .B(exp_rslt_NRM2_EW1[8]), .Y(
formatted_number_W[60]) );
OR2X1TS U2063 ( .A(n2484), .B(exp_rslt_NRM2_EW1[7]), .Y(
formatted_number_W[59]) );
OR2X1TS U2064 ( .A(n2484), .B(exp_rslt_NRM2_EW1[4]), .Y(
formatted_number_W[56]) );
OR2X1TS U2065 ( .A(n2484), .B(exp_rslt_NRM2_EW1[9]), .Y(
formatted_number_W[61]) );
OR2X1TS U2066 ( .A(n2484), .B(exp_rslt_NRM2_EW1[1]), .Y(
formatted_number_W[53]) );
OR2X1TS U2067 ( .A(n2484), .B(exp_rslt_NRM2_EW1[5]), .Y(
formatted_number_W[57]) );
OR2X1TS U2068 ( .A(n2484), .B(exp_rslt_NRM2_EW1[6]), .Y(
formatted_number_W[58]) );
OR2X1TS U2069 ( .A(n2484), .B(exp_rslt_NRM2_EW1[2]), .Y(
formatted_number_W[54]) );
AOI22X1TS U2070 ( .A0(n1215), .A1(Data_array_SWR[65]), .B0(n1200), .B1(n898),
.Y(n1188) );
AOI22X1TS U2071 ( .A0(n982), .A1(Data_array_SWR[61]), .B0(n983), .B1(n884),
.Y(n1187) );
AOI22X1TS U2072 ( .A0(n989), .A1(n1289), .B0(n1185), .B1(n1291), .Y(n1186)
);
NAND3XLTS U2073 ( .A(n1188), .B(n1187), .C(n1186), .Y(n1295) );
AOI22X1TS U2074 ( .A0(n1305), .A1(n1295), .B0(n1290), .B1(n1296), .Y(n1189)
);
OAI211X1TS U2075 ( .A0(n1298), .A1(n1287), .B0(n1189), .C0(n837), .Y(
sftr_odat_SHT2_SWR[48]) );
AOI22X1TS U2076 ( .A0(Data_array_SWR[67]), .A1(n1200), .B0(n982), .B1(
Data_array_SWR[59]), .Y(n1191) );
AOI22X1TS U2077 ( .A0(n1215), .A1(n908), .B0(Data_array_SWR[63]), .B1(n983),
.Y(n1190) );
OAI211XLTS U2078 ( .A0(n1203), .A1(n1511), .B0(n1191), .C0(n1190), .Y(n1192)
);
AOI21X1TS U2079 ( .A0(n989), .A1(n1276), .B0(n1192), .Y(n1193) );
OAI21X1TS U2080 ( .A0(n1195), .A1(n1194), .B0(n1193), .Y(n1504) );
NAND2X1TS U2081 ( .A(n1305), .B(n1504), .Y(n1196) );
OAI211X1TS U2082 ( .A0(n1506), .A1(n1287), .B0(n1196), .C0(n837), .Y(
sftr_odat_SHT2_SWR[50]) );
AOI22X1TS U2083 ( .A0(n1206), .A1(Data_array_SWR[80]), .B0(n1207), .B1(
Data_array_SWR[83]), .Y(n1198) );
AOI22X1TS U2084 ( .A0(n1208), .A1(Data_array_SWR[85]), .B0(n1177), .B1(
Data_array_SWR[81]), .Y(n1197) );
NAND2X1TS U2085 ( .A(n1198), .B(n1197), .Y(n1267) );
AOI21X1TS U2086 ( .A0(n1206), .A1(n897), .B0(n1199), .Y(n1205) );
AOI22X1TS U2087 ( .A0(n1215), .A1(n885), .B0(n1200), .B1(Data_array_SWR[66]),
.Y(n1202) );
AOI22X1TS U2088 ( .A0(n982), .A1(Data_array_SWR[58]), .B0(n983), .B1(
Data_array_SWR[62]), .Y(n1201) );
OAI211XLTS U2089 ( .A0(n1203), .A1(n1205), .B0(n1202), .C0(n1201), .Y(n1204)
);
AOI21X1TS U2090 ( .A0(n989), .A1(n1267), .B0(n1204), .Y(n1306) );
INVX2TS U2091 ( .A(n1205), .Y(n1301) );
AOI22X1TS U2092 ( .A0(n1206), .A1(Data_array_SWR[69]), .B0(n1177), .B1(n901),
.Y(n1210) );
AOI22X1TS U2093 ( .A0(n1208), .A1(Data_array_SWR[77]), .B0(n1207), .B1(
Data_array_SWR[74]), .Y(n1209) );
NAND2X1TS U2094 ( .A(n1210), .B(n1209), .Y(n1299) );
AOI22X1TS U2095 ( .A0(n1222), .A1(n1301), .B0(n1290), .B1(n1299), .Y(n1211)
);
OAI211X1TS U2096 ( .A0(n1306), .A1(n1508), .B0(n837), .C0(n1211), .Y(
sftr_odat_SHT2_SWR[51]) );
NAND2X1TS U2097 ( .A(n1305), .B(n1212), .Y(n1213) );
OAI211X1TS U2098 ( .A0(n1214), .A1(n1287), .B0(n1213), .C0(n837), .Y(
sftr_odat_SHT2_SWR[53]) );
CLKAND2X2TS U2099 ( .A(n1215), .B(Data_array_SWR[71]), .Y(n1220) );
OAI22X1TS U2100 ( .A0(n1218), .A1(n1217), .B0(n1298), .B1(n1216), .Y(n1219)
);
AOI211X1TS U2101 ( .A0(n986), .A1(n1221), .B0(n1220), .C0(n1219), .Y(n1294)
);
AOI22X1TS U2102 ( .A0(n1291), .A1(n1300), .B0(n1222), .B1(n1289), .Y(n1223)
);
OAI211X1TS U2103 ( .A0(n1294), .A1(n1508), .B0(n1228), .C0(n1223), .Y(
sftr_odat_SHT2_SWR[38]) );
AOI22X1TS U2104 ( .A0(n1300), .A1(n1280), .B0(n1231), .B1(n1278), .Y(n1224)
);
OAI211XLTS U2105 ( .A0(n1283), .A1(n1244), .B0(n1228), .C0(n1224), .Y(n1225)
);
AOI21X1TS U2106 ( .A0(n1260), .A1(n1285), .B0(n1225), .Y(n1226) );
OAI21X1TS U2107 ( .A0(n1288), .A1(n1510), .B0(n1226), .Y(
sftr_odat_SHT2_SWR[37]) );
AOI22X1TS U2108 ( .A0(n1300), .A1(n1272), .B0(n1231), .B1(n1271), .Y(n1227)
);
OAI211XLTS U2109 ( .A0(n1274), .A1(n1244), .B0(n1228), .C0(n1227), .Y(n1229)
);
AOI21X1TS U2110 ( .A0(n1260), .A1(n1276), .B0(n1229), .Y(n1230) );
OAI21X1TS U2111 ( .A0(n853), .A1(n1510), .B0(n1230), .Y(
sftr_odat_SHT2_SWR[36]) );
INVX2TS U2112 ( .A(n1299), .Y(n1270) );
OAI32X1TS U2113 ( .A0(n1232), .A1(n1300), .A2(n1231), .B0(n1301), .B1(n1232),
.Y(n1234) );
OAI21XLTS U2114 ( .A0(n1260), .A1(n1290), .B0(n1267), .Y(n1233) );
OAI211X1TS U2115 ( .A0(n1510), .A1(n1270), .B0(n1234), .C0(n1233), .Y(
sftr_odat_SHT2_SWR[35]) );
AOI21X1TS U2116 ( .A0(n1300), .A1(n1258), .B0(n1257), .Y(n1237) );
AOI22X1TS U2117 ( .A0(n1262), .A1(n1259), .B0(n1260), .B1(n1261), .Y(n1236)
);
OAI211X1TS U2118 ( .A0(n1244), .A1(n1265), .B0(n1237), .C0(n1236), .Y(
sftr_odat_SHT2_SWR[30]) );
AOI22X1TS U2119 ( .A0(n1262), .A1(n1251), .B0(n1260), .B1(n1252), .Y(n1240)
);
AOI21X1TS U2120 ( .A0(n1300), .A1(n1253), .B0(n1257), .Y(n1239) );
OAI211X1TS U2121 ( .A0(n1244), .A1(n1256), .B0(n1240), .C0(n1239), .Y(
sftr_odat_SHT2_SWR[29]) );
AOI21X1TS U2122 ( .A0(n1300), .A1(n1245), .B0(n1257), .Y(n1243) );
AOI22X1TS U2123 ( .A0(n1262), .A1(n1246), .B0(n1260), .B1(n1247), .Y(n1242)
);
OAI211X1TS U2124 ( .A0(n1244), .A1(n1250), .B0(n1243), .C0(n1242), .Y(
sftr_odat_SHT2_SWR[28]) );
AOI21X1TS U2125 ( .A0(n1290), .A1(n1245), .B0(n1257), .Y(n1249) );
AOI22X1TS U2126 ( .A0(n1262), .A1(n1247), .B0(n1260), .B1(n1246), .Y(n1248)
);
OAI211X1TS U2127 ( .A0(n1250), .A1(n1282), .B0(n1249), .C0(n1248), .Y(
sftr_odat_SHT2_SWR[26]) );
AOI22X1TS U2128 ( .A0(n1262), .A1(n1252), .B0(n1260), .B1(n1251), .Y(n1255)
);
AOI21X1TS U2129 ( .A0(n1290), .A1(n1253), .B0(n1257), .Y(n1254) );
OAI211X1TS U2130 ( .A0(n1256), .A1(n1282), .B0(n1255), .C0(n1254), .Y(
sftr_odat_SHT2_SWR[25]) );
AOI21X1TS U2131 ( .A0(n1290), .A1(n1258), .B0(n1257), .Y(n1264) );
AOI22X1TS U2132 ( .A0(n1262), .A1(n1261), .B0(n1260), .B1(n1259), .Y(n1263)
);
OAI211X1TS U2133 ( .A0(n1265), .A1(n1282), .B0(n1264), .C0(n1263), .Y(
sftr_odat_SHT2_SWR[24]) );
OAI32X1TS U2134 ( .A0(n1266), .A1(n1290), .A2(n1279), .B0(n1301), .B1(n1266),
.Y(n1269) );
OAI21XLTS U2135 ( .A0(n1302), .A1(n1300), .B0(n1267), .Y(n1268) );
OAI211X1TS U2136 ( .A0(n1287), .A1(n1270), .B0(n1269), .C0(n1268), .Y(
sftr_odat_SHT2_SWR[19]) );
AOI22X1TS U2137 ( .A0(n1290), .A1(n1272), .B0(n1279), .B1(n1271), .Y(n1273)
);
OAI211XLTS U2138 ( .A0(n1274), .A1(n1282), .B0(n1292), .C0(n1273), .Y(n1275)
);
AOI21X1TS U2139 ( .A0(n1302), .A1(n1276), .B0(n1275), .Y(n1277) );
OAI21X1TS U2140 ( .A0(n853), .A1(n1287), .B0(n1277), .Y(
sftr_odat_SHT2_SWR[18]) );
AOI22X1TS U2141 ( .A0(n1280), .A1(n1290), .B0(n1279), .B1(n1278), .Y(n1281)
);
OAI211XLTS U2142 ( .A0(n1283), .A1(n1282), .B0(n1292), .C0(n1281), .Y(n1284)
);
AOI21X1TS U2143 ( .A0(n1302), .A1(n1285), .B0(n1284), .Y(n1286) );
OAI21X1TS U2144 ( .A0(n1288), .A1(n1287), .B0(n1286), .Y(
sftr_odat_SHT2_SWR[17]) );
AOI22X1TS U2145 ( .A0(n1291), .A1(n1290), .B0(n1302), .B1(n1289), .Y(n1293)
);
OAI211X1TS U2146 ( .A0(n1294), .A1(n1305), .B0(n1293), .C0(n1292), .Y(
sftr_odat_SHT2_SWR[16]) );
AOI22X1TS U2147 ( .A0(n1300), .A1(n1296), .B0(n1508), .B1(n1295), .Y(n1297)
);
OAI211X1TS U2148 ( .A0(n1298), .A1(n1510), .B0(n1297), .C0(n1303), .Y(
sftr_odat_SHT2_SWR[6]) );
AOI22X1TS U2149 ( .A0(n1302), .A1(n1301), .B0(n1300), .B1(n1299), .Y(n1304)
);
OAI211X1TS U2150 ( .A0(n1306), .A1(n1305), .B0(n1304), .C0(n1303), .Y(
sftr_odat_SHT2_SWR[3]) );
OAI211X1TS U2151 ( .A0(n1311), .A1(n1310), .B0(n2214), .C0(n1309), .Y(n1315)
);
INVX2TS U2152 ( .A(n1312), .Y(n1314) );
OAI32X1TS U2153 ( .A0(n1315), .A1(n914), .A2(n1314), .B0(n1313), .B1(n1315),
.Y(n1319) );
OAI211X1TS U2154 ( .A0(n2472), .A1(n1320), .B0(n1319), .C0(n1318), .Y(
LZD_raw_out_EWR[5]) );
NOR2XLTS U2155 ( .A(n914), .B(Raw_mant_NRM_SWR[1]), .Y(n1337) );
INVX2TS U2156 ( .A(n1321), .Y(n1323) );
AOI211X1TS U2157 ( .A0(n1324), .A1(Raw_mant_NRM_SWR[30]), .B0(n1323), .C0(
n1322), .Y(n2213) );
NOR2XLTS U2158 ( .A(Raw_mant_NRM_SWR[37]), .B(Raw_mant_NRM_SWR[38]), .Y(
n1327) );
OAI22X1TS U2159 ( .A0(n1327), .A1(n1326), .B0(n2289), .B1(n1325), .Y(n1332)
);
NOR2XLTS U2160 ( .A(Raw_mant_NRM_SWR[26]), .B(Raw_mant_NRM_SWR[25]), .Y(
n1330) );
OAI21XLTS U2161 ( .A0(n1330), .A1(n1329), .B0(n1328), .Y(n1331) );
NOR4X1TS U2162 ( .A(n1334), .B(n1333), .C(n1332), .D(n1331), .Y(n1335) );
OAI211X1TS U2163 ( .A0(n1337), .A1(n1336), .B0(n2213), .C0(n1335), .Y(
LZD_raw_out_EWR[4]) );
NAND2X1TS U2164 ( .A(n1379), .B(Raw_mant_NRM_SWR[0]), .Y(n1338) );
AND3X1TS U2165 ( .A(n1339), .B(Shift_reg_FLAGS_7[1]), .C(n1338), .Y(n2182)
);
AOI22X2TS U2166 ( .A0(n1379), .A1(LZD_raw_out_EWR[1]), .B0(
Shift_amount_SHT1_EWR[1]), .B1(n915), .Y(n2196) );
OAI22X2TS U2167 ( .A0(Shift_reg_FLAGS_7[1]), .A1(Shift_amount_SHT1_EWR[0]),
.B0(LZD_raw_out_EWR[0]), .B1(n836), .Y(n2185) );
INVX2TS U2168 ( .A(n2196), .Y(n2191) );
AOI22X1TS U2169 ( .A0(n1379), .A1(n895), .B0(Raw_mant_NRM_SWR[1]), .B1(n1342), .Y(n1418) );
AOI22X1TS U2170 ( .A0(Raw_mant_NRM_SWR[51]), .A1(n1379), .B0(
DmP_mant_SHT1_SW[1]), .B1(n915), .Y(n1340) );
INVX2TS U2171 ( .A(n2185), .Y(n2187) );
AOI22X1TS U2172 ( .A0(n860), .A1(n1373), .B0(n886), .B1(n1379), .Y(n1341) );
AOI222X4TS U2173 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[10]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[42]), .C0(Raw_mant_NRM_SWR[12]), .C1(n2533), .Y(n1497) );
AOI22X1TS U2174 ( .A0(n2533), .A1(Raw_mant_NRM_SWR[15]), .B0(
DmP_mant_SHT1_SW[13]), .B1(n915), .Y(n1343) );
AOI222X4TS U2175 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[12]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[40]), .C0(Raw_mant_NRM_SWR[14]), .C1(n2533), .Y(n1496) );
AOI222X4TS U2176 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[11]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[41]), .C0(Raw_mant_NRM_SWR[13]), .C1(n1342), .Y(n1498) );
OAI22X1TS U2177 ( .A0(n1496), .A1(n2183), .B0(n1498), .B1(n2195), .Y(n1344)
);
AOI21X1TS U2178 ( .A0(n1373), .A1(n1493), .B0(n1344), .Y(n1345) );
AOI222X4TS U2179 ( .A0(n915), .A1(DmP_mant_SHT1_SW[2]), .B0(n2221), .B1(
Raw_mant_NRM_SWR[50]), .C0(Raw_mant_NRM_SWR[4]), .C1(n1342), .Y(n1489)
);
AOI22X1TS U2180 ( .A0(n1342), .A1(Raw_mant_NRM_SWR[7]), .B0(
DmP_mant_SHT1_SW[5]), .B1(n2532), .Y(n1346) );
AOI222X4TS U2181 ( .A0(n2532), .A1(DmP_mant_SHT1_SW[4]), .B0(
Raw_mant_NRM_SWR[6]), .B1(n1342), .C0(Raw_mant_NRM_SWR[48]), .C1(n2221), .Y(n1485) );
AOI222X4TS U2182 ( .A0(n915), .A1(DmP_mant_SHT1_SW[3]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n2533), .C0(Raw_mant_NRM_SWR[49]), .C1(n2221), .Y(n1484) );
OAI22X1TS U2183 ( .A0(n1485), .A1(n2183), .B0(n1484), .B1(n2195), .Y(n1347)
);
AOI21X1TS U2184 ( .A0(n1373), .A1(n1482), .B0(n1347), .Y(n1348) );
AOI222X4TS U2185 ( .A0(n915), .A1(DmP_mant_SHT1_SW[14]), .B0(
Raw_mant_NRM_SWR[16]), .B1(n2533), .C0(Raw_mant_NRM_SWR[38]), .C1(
n2221), .Y(n1490) );
AOI22X1TS U2186 ( .A0(n1342), .A1(Raw_mant_NRM_SWR[19]), .B0(
DmP_mant_SHT1_SW[17]), .B1(n2532), .Y(n1349) );
AOI222X4TS U2187 ( .A0(n2532), .A1(DmP_mant_SHT1_SW[16]), .B0(
Raw_mant_NRM_SWR[18]), .B1(n2533), .C0(Raw_mant_NRM_SWR[36]), .C1(
n2221), .Y(n1468) );
AOI222X4TS U2188 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[15]), .B0(
Raw_mant_NRM_SWR[17]), .B1(n1342), .C0(Raw_mant_NRM_SWR[37]), .C1(
n2221), .Y(n1491) );
OAI22X1TS U2189 ( .A0(n1468), .A1(n2189), .B0(n1491), .B1(n2195), .Y(n1350)
);
AOI21X1TS U2190 ( .A0(n1373), .A1(n1471), .B0(n1350), .Y(n1351) );
AOI222X4TS U2191 ( .A0(n915), .A1(DmP_mant_SHT1_SW[6]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[46]), .C0(n882), .C1(n2533), .Y(n1479) );
AOI22X1TS U2192 ( .A0(Raw_mant_NRM_SWR[43]), .A1(n1379), .B0(
DmP_mant_SHT1_SW[9]), .B1(n915), .Y(n1352) );
AOI222X4TS U2193 ( .A0(n915), .A1(DmP_mant_SHT1_SW[8]), .B0(n2221), .B1(n913), .C0(Raw_mant_NRM_SWR[10]), .C1(n1342), .Y(n1502) );
AOI222X4TS U2194 ( .A0(n915), .A1(DmP_mant_SHT1_SW[7]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1342), .C0(Raw_mant_NRM_SWR[45]), .C1(n2221), .Y(n1480) );
OAI22X1TS U2195 ( .A0(n1502), .A1(n2189), .B0(n1480), .B1(n1488), .Y(n1353)
);
AOI21X1TS U2196 ( .A0(n1373), .A1(n1500), .B0(n1353), .Y(n1354) );
AOI22X1TS U2197 ( .A0(n1342), .A1(Raw_mant_NRM_SWR[23]), .B0(
DmP_mant_SHT1_SW[21]), .B1(n2532), .Y(n1355) );
AOI222X4TS U2198 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[23]), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1342), .C0(Raw_mant_NRM_SWR[29]), .C1(
n2221), .Y(n2194) );
AOI222X4TS U2199 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[22]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1342), .C0(Raw_mant_NRM_SWR[30]), .C1(
n2221), .Y(n2198) );
OAI22X1TS U2200 ( .A0(n2194), .A1(n2189), .B0(n2198), .B1(n1488), .Y(n1356)
);
AOI21X1TS U2201 ( .A0(n1466), .A1(n1437), .B0(n1356), .Y(n1357) );
AOI22X1TS U2202 ( .A0(n1342), .A1(Raw_mant_NRM_SWR[31]), .B0(
DmP_mant_SHT1_SW[29]), .B1(n915), .Y(n1358) );
AOI222X4TS U2203 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[28]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[24]), .C0(Raw_mant_NRM_SWR[30]), .C1(n2533), .Y(n2184) );
AOI222X4TS U2204 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[27]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[25]), .C0(Raw_mant_NRM_SWR[29]), .C1(n2533), .Y(n2190) );
OAI22X1TS U2205 ( .A0(n2184), .A1(n2183), .B0(n2190), .B1(n1488), .Y(n1359)
);
AOI21X1TS U2206 ( .A0(n1373), .A1(n1456), .B0(n1359), .Y(n1360) );
AOI222X4TS U2207 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[42]), .B0(n913), .B1(
n2533), .C0(Raw_mant_NRM_SWR[10]), .C1(n2221), .Y(n1412) );
AOI22X1TS U2208 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n1379), .B0(
DmP_mant_SHT1_SW[45]), .B1(n915), .Y(n1361) );
AOI222X4TS U2209 ( .A0(n915), .A1(DmP_mant_SHT1_SW[44]), .B0(
Raw_mant_NRM_SWR[46]), .B1(n2533), .C0(n882), .C1(n2221), .Y(n1408) );
AOI222X4TS U2210 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[43]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[9]), .C0(Raw_mant_NRM_SWR[45]), .C1(n1342), .Y(n1407)
);
OAI22X1TS U2211 ( .A0(n1408), .A1(n2183), .B0(n1407), .B1(n1488), .Y(n1363)
);
AOI21X1TS U2212 ( .A0(n1373), .A1(n1405), .B0(n1363), .Y(n1364) );
AOI222X4TS U2213 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[30]), .B0(
Raw_mant_NRM_SWR[32]), .B1(n2533), .C0(n894), .C1(n2221), .Y(n1454) );
AOI22X1TS U2214 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n1379), .B0(
DmP_mant_SHT1_SW[33]), .B1(n2532), .Y(n1365) );
AOI222X4TS U2215 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[32]), .B0(
Raw_mant_NRM_SWR[34]), .B1(n1342), .C0(Raw_mant_NRM_SWR[20]), .C1(
n2221), .Y(n1446) );
AOI222X4TS U2216 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[31]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[21]), .C0(Raw_mant_NRM_SWR[33]), .C1(n2533), .Y(n1432) );
OAI22X1TS U2217 ( .A0(n1446), .A1(n2183), .B0(n1432), .B1(n1488), .Y(n1367)
);
AOI21X1TS U2218 ( .A0(n1373), .A1(n1443), .B0(n1367), .Y(n1368) );
AOI222X4TS U2219 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[46]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[6]), .C0(Raw_mant_NRM_SWR[48]), .C1(n1342), .Y(n1403)
);
AOI22X1TS U2220 ( .A0(n1342), .A1(Raw_mant_NRM_SWR[51]), .B0(
DmP_mant_SHT1_SW[49]), .B1(n915), .Y(n1369) );
AOI222X4TS U2221 ( .A0(n915), .A1(DmP_mant_SHT1_SW[48]), .B0(
Raw_mant_NRM_SWR[50]), .B1(n2533), .C0(Raw_mant_NRM_SWR[4]), .C1(n2221), .Y(n1402) );
AOI222X4TS U2222 ( .A0(n915), .A1(DmP_mant_SHT1_SW[47]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[5]), .C0(Raw_mant_NRM_SWR[49]), .C1(n1342), .Y(n1397)
);
OAI22X1TS U2223 ( .A0(n1402), .A1(n2189), .B0(n1397), .B1(n1488), .Y(n1370)
);
AOI21X1TS U2224 ( .A0(n1373), .A1(n1414), .B0(n1370), .Y(n1371) );
AOI222X4TS U2225 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[18]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[34]), .C0(Raw_mant_NRM_SWR[20]), .C1(n2533), .Y(n1469) );
AOI222X4TS U2226 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[20]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[32]), .C0(n894), .C1(n1342), .Y(n1435) );
AOI222X4TS U2227 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[19]), .B0(
Raw_mant_NRM_SWR[21]), .B1(n1342), .C0(Raw_mant_NRM_SWR[33]), .C1(
n2221), .Y(n1439) );
OAI22X1TS U2228 ( .A0(n1435), .A1(n2189), .B0(n1439), .B1(n1488), .Y(n1372)
);
AOI21X1TS U2229 ( .A0(n1373), .A1(n1437), .B0(n1372), .Y(n1374) );
AOI222X4TS U2230 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[38]), .B0(
Raw_mant_NRM_SWR[40]), .B1(n1342), .C0(Raw_mant_NRM_SWR[14]), .C1(
n2221), .Y(n1452) );
AOI22X1TS U2231 ( .A0(n1342), .A1(Raw_mant_NRM_SWR[43]), .B0(
DmP_mant_SHT1_SW[41]), .B1(n2532), .Y(n1375) );
AOI222X4TS U2232 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[40]), .B0(
Raw_mant_NRM_SWR[42]), .B1(n2533), .C0(Raw_mant_NRM_SWR[12]), .C1(
n2221), .Y(n1448) );
AOI222X4TS U2233 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[39]), .B0(
Raw_mant_NRM_SWR[41]), .B1(n2533), .C0(Raw_mant_NRM_SWR[13]), .C1(
n2221), .Y(n1447) );
OAI22X1TS U2234 ( .A0(n1448), .A1(n2189), .B0(n1447), .B1(n1488), .Y(n1376)
);
AOI21X1TS U2235 ( .A0(n1373), .A1(n1410), .B0(n1376), .Y(n1377) );
AOI222X4TS U2236 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[34]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[18]), .C0(Raw_mant_NRM_SWR[36]), .C1(n2533), .Y(n1440) );
AOI22X1TS U2237 ( .A0(n1342), .A1(Raw_mant_NRM_SWR[39]), .B0(
DmP_mant_SHT1_SW[37]), .B1(n2532), .Y(n1378) );
AOI222X4TS U2238 ( .A0(n1380), .A1(DmP_mant_SHT1_SW[35]), .B0(n1379), .B1(
Raw_mant_NRM_SWR[17]), .C0(Raw_mant_NRM_SWR[37]), .C1(n2533), .Y(n1441) );
OAI22X1TS U2239 ( .A0(n1427), .A1(n2189), .B0(n1441), .B1(n1488), .Y(n1381)
);
AOI21X1TS U2240 ( .A0(n1373), .A1(n1450), .B0(n1381), .Y(n1382) );
OAI22X1TS U2241 ( .A0(n1402), .A1(n835), .B0(n1397), .B1(n2183), .Y(n1383)
);
AOI21X1TS U2242 ( .A0(n1466), .A1(n1405), .B0(n1383), .Y(n1384) );
OAI22X1TS U2243 ( .A0(n1412), .A1(n835), .B0(n1448), .B1(n2195), .Y(n1386)
);
AOI21X1TS U2244 ( .A0(n1385), .A1(n1410), .B0(n1386), .Y(n1387) );
OAI22X1TS U2245 ( .A0(n1452), .A1(n835), .B0(n1427), .B1(n1488), .Y(n1388)
);
AOI21X1TS U2246 ( .A0(n1385), .A1(n1450), .B0(n1388), .Y(n1389) );
OAI22X1TS U2247 ( .A0(n1447), .A1(n835), .B0(n1452), .B1(n2183), .Y(n1391)
);
AOI21X1TS U2248 ( .A0(n1390), .A1(n1450), .B0(n1391), .Y(n1392) );
AOI222X4TS U2249 ( .A0(n915), .A1(DmP_mant_SHT1_SW[50]), .B0(
Raw_mant_NRM_SWR[52]), .B1(n2533), .C0(n914), .C1(n2221), .Y(n2180) );
OAI22X1TS U2250 ( .A0(n2180), .A1(n835), .B0(n1402), .B1(n2195), .Y(n1393)
);
AOI21X1TS U2251 ( .A0(n1385), .A1(n1414), .B0(n1393), .Y(n1394) );
OAI22X1TS U2252 ( .A0(n1407), .A1(n835), .B0(n1412), .B1(n2183), .Y(n1395)
);
AOI21X1TS U2253 ( .A0(n1390), .A1(n1410), .B0(n1395), .Y(n1396) );
OAI22X1TS U2254 ( .A0(n1397), .A1(n835), .B0(n1403), .B1(n2183), .Y(n1398)
);
AOI21X1TS U2255 ( .A0(n1390), .A1(n1405), .B0(n1398), .Y(n1399) );
AOI222X4TS U2256 ( .A0(n915), .A1(DmP_mant_SHT1_SW[51]), .B0(n895), .B1(
n2533), .C0(Raw_mant_NRM_SWR[1]), .C1(n2221), .Y(n2181) );
OAI22X1TS U2257 ( .A0(n2181), .A1(n835), .B0(n2180), .B1(n2183), .Y(n1400)
);
AOI21X1TS U2258 ( .A0(n1390), .A1(n1414), .B0(n1400), .Y(n1401) );
OAI22X1TS U2259 ( .A0(n1403), .A1(n835), .B0(n1408), .B1(n1488), .Y(n1404)
);
AOI21X1TS U2260 ( .A0(n1385), .A1(n1405), .B0(n1404), .Y(n1406) );
OAI22X1TS U2261 ( .A0(n1408), .A1(n835), .B0(n1407), .B1(n2183), .Y(n1409)
);
AOI21X1TS U2262 ( .A0(n1466), .A1(n1410), .B0(n1409), .Y(n1411) );
INVX4TS U2263 ( .A(n1373), .Y(n1453) );
OAI22X1TS U2264 ( .A0(n2180), .A1(n2195), .B0(n2181), .B1(n2189), .Y(n1413)
);
AOI21X1TS U2265 ( .A0(n1466), .A1(n1414), .B0(n1413), .Y(n1415) );
OAI22X1TS U2266 ( .A0(n1489), .A1(n1453), .B0(n1460), .B1(n1488), .Y(n1416)
);
AOI21X1TS U2267 ( .A0(n1385), .A1(n860), .B0(n1416), .Y(n1417) );
OAI22X1TS U2268 ( .A0(n1440), .A1(n1453), .B0(n1446), .B1(n1488), .Y(n1419)
);
AOI21X1TS U2269 ( .A0(n1385), .A1(n1443), .B0(n1419), .Y(n1420) );
OAI22X1TS U2270 ( .A0(n2194), .A1(n1453), .B0(n2198), .B1(n2183), .Y(n1421)
);
AOI21X1TS U2271 ( .A0(n1390), .A1(n1437), .B0(n1421), .Y(n1422) );
OAI22X1TS U2272 ( .A0(n1446), .A1(n835), .B0(n1432), .B1(n2183), .Y(n1423)
);
AOI21X1TS U2273 ( .A0(n1466), .A1(n1456), .B0(n1423), .Y(n1424) );
OAI22X1TS U2274 ( .A0(n1435), .A1(n1453), .B0(n1439), .B1(n2183), .Y(n1425)
);
AOI21X1TS U2275 ( .A0(n1466), .A1(n1471), .B0(n1425), .Y(n1426) );
OAI22X1TS U2276 ( .A0(n1427), .A1(n835), .B0(n1441), .B1(n2183), .Y(n1428)
);
AOI21X1TS U2277 ( .A0(n1466), .A1(n1443), .B0(n1428), .Y(n1429) );
OAI22X1TS U2278 ( .A0(n1439), .A1(n1453), .B0(n1469), .B1(n2189), .Y(n1430)
);
AOI21X1TS U2279 ( .A0(n1390), .A1(n1471), .B0(n1430), .Y(n1431) );
OAI22X1TS U2280 ( .A0(n1432), .A1(n1453), .B0(n1454), .B1(n2183), .Y(n1433)
);
AOI21X1TS U2281 ( .A0(n1390), .A1(n1456), .B0(n1433), .Y(n1434) );
OAI22X1TS U2282 ( .A0(n2198), .A1(n1453), .B0(n1435), .B1(n1488), .Y(n1436)
);
AOI21X1TS U2283 ( .A0(n1385), .A1(n1437), .B0(n1436), .Y(n1438) );
OAI22X1TS U2284 ( .A0(n1441), .A1(n1453), .B0(n1440), .B1(n2183), .Y(n1442)
);
AOI21X1TS U2285 ( .A0(n1390), .A1(n1443), .B0(n1442), .Y(n1444) );
OAI22X1TS U2286 ( .A0(n1448), .A1(n1453), .B0(n1447), .B1(n2183), .Y(n1449)
);
AOI21X1TS U2287 ( .A0(n1466), .A1(n1450), .B0(n1449), .Y(n1451) );
OAI22X1TS U2288 ( .A0(n1454), .A1(n1453), .B0(n2184), .B1(n1488), .Y(n1455)
);
AOI21X1TS U2289 ( .A0(n1385), .A1(n1456), .B0(n1455), .Y(n1457) );
OAI22X1TS U2290 ( .A0(n1484), .A1(n1453), .B0(n1489), .B1(n2189), .Y(n1458)
);
AOI21X1TS U2291 ( .A0(n1390), .A1(n860), .B0(n1458), .Y(n1459) );
OAI22X1TS U2292 ( .A0(n1497), .A1(n835), .B0(n1502), .B1(n1488), .Y(n1461)
);
AOI21X1TS U2293 ( .A0(n1385), .A1(n1500), .B0(n1461), .Y(n1462) );
OAI22X1TS U2294 ( .A0(n1502), .A1(n835), .B0(n1480), .B1(n2189), .Y(n1463)
);
AOI21X1TS U2295 ( .A0(n1466), .A1(n1482), .B0(n1463), .Y(n1464) );
OAI22X1TS U2296 ( .A0(n1468), .A1(n835), .B0(n1491), .B1(n2189), .Y(n1465)
);
AOI21X1TS U2297 ( .A0(n1466), .A1(n1493), .B0(n1465), .Y(n1467) );
OAI22X1TS U2298 ( .A0(n1469), .A1(n835), .B0(n1468), .B1(n1488), .Y(n1470)
);
AOI21X1TS U2299 ( .A0(n1385), .A1(n1471), .B0(n1470), .Y(n1472) );
OAI22X1TS U2300 ( .A0(n1490), .A1(n835), .B0(n1496), .B1(n1488), .Y(n1473)
);
AOI21X1TS U2301 ( .A0(n1385), .A1(n1493), .B0(n1473), .Y(n1474) );
OAI22X1TS U2302 ( .A0(n1479), .A1(n1453), .B0(n1485), .B1(n2195), .Y(n1475)
);
AOI21X1TS U2303 ( .A0(n1385), .A1(n1482), .B0(n1475), .Y(n1476) );
OAI22X1TS U2304 ( .A0(n1496), .A1(n1453), .B0(n1498), .B1(n2189), .Y(n1477)
);
AOI21X1TS U2305 ( .A0(n1466), .A1(n1500), .B0(n1477), .Y(n1478) );
OAI22X1TS U2306 ( .A0(n1480), .A1(n835), .B0(n1479), .B1(n2189), .Y(n1481)
);
AOI21X1TS U2307 ( .A0(n1390), .A1(n1482), .B0(n1481), .Y(n1483) );
OAI22X1TS U2308 ( .A0(n1485), .A1(n1453), .B0(n1484), .B1(n2189), .Y(n1486)
);
AOI21X1TS U2309 ( .A0(n1466), .A1(n860), .B0(n1486), .Y(n1487) );
OAI22X1TS U2310 ( .A0(n1491), .A1(n835), .B0(n1490), .B1(n2189), .Y(n1492)
);
AOI21X1TS U2311 ( .A0(n1390), .A1(n1493), .B0(n1492), .Y(n1494) );
OAI22X1TS U2312 ( .A0(n1498), .A1(n1453), .B0(n1497), .B1(n2189), .Y(n1499)
);
AOI21X1TS U2313 ( .A0(n1390), .A1(n1500), .B0(n1499), .Y(n1501) );
NOR2BX1TS U2314 ( .AN(LZD_output_NRM2_EW[5]), .B(ADD_OVRFLW_NRM2), .Y(n1503)
);
XOR2X1TS U2315 ( .A(n2244), .B(n1503), .Y(DP_OP_15J206_122_2221_n17) );
NAND2X1TS U2316 ( .A(n1508), .B(n1504), .Y(n1505) );
OAI211X1TS U2317 ( .A0(n1506), .A1(n1510), .B0(n1505), .C0(n1303), .Y(
sftr_odat_SHT2_SWR[4]) );
NAND2X1TS U2318 ( .A(n1508), .B(n1507), .Y(n1509) );
OAI211X1TS U2319 ( .A0(n1511), .A1(n1510), .B0(n1509), .C0(n1303), .Y(
sftr_odat_SHT2_SWR[2]) );
NOR2BX1TS U2320 ( .AN(LZD_output_NRM2_EW[4]), .B(ADD_OVRFLW_NRM2), .Y(n1512)
);
XOR2X1TS U2321 ( .A(n2244), .B(n1512), .Y(DP_OP_15J206_122_2221_n18) );
NOR2BX1TS U2322 ( .AN(LZD_output_NRM2_EW[3]), .B(ADD_OVRFLW_NRM2), .Y(n1513)
);
XOR2X1TS U2323 ( .A(n2244), .B(n1513), .Y(DP_OP_15J206_122_2221_n19) );
NOR2BX1TS U2324 ( .AN(LZD_output_NRM2_EW[2]), .B(ADD_OVRFLW_NRM2), .Y(n1514)
);
XOR2X1TS U2325 ( .A(n2244), .B(n1514), .Y(DP_OP_15J206_122_2221_n20) );
NOR2BX1TS U2326 ( .AN(LZD_output_NRM2_EW[1]), .B(ADD_OVRFLW_NRM2), .Y(n1515)
);
XOR2X1TS U2327 ( .A(n2244), .B(n1515), .Y(DP_OP_15J206_122_2221_n21) );
OR2X1TS U2328 ( .A(ADD_OVRFLW_NRM2), .B(LZD_output_NRM2_EW[0]), .Y(n1516) );
XOR2X1TS U2329 ( .A(n2244), .B(n1516), .Y(DP_OP_15J206_122_2221_n22) );
AOI22X1TS U2330 ( .A0(n1519), .A1(n1518), .B0(n986), .B1(n1517), .Y(n1520)
);
NAND2X1TS U2331 ( .A(n1521), .B(n1520), .Y(sftr_odat_SHT2_SWR[27]) );
NAND2X1TS U2332 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n1935) );
NAND2X1TS U2333 ( .A(DMP_SFG[1]), .B(DmP_mant_SFG_SWR[3]), .Y(n1522) );
AOI2BB2X1TS U2334 ( .B0(n1935), .B1(n1522), .A0N(DMP_SFG[1]), .A1N(
DmP_mant_SFG_SWR[3]), .Y(n1920) );
AOI21X1TS U2335 ( .A0(DMP_SFG[19]), .A1(DmP_mant_SFG_SWR[21]), .B0(n1809),
.Y(n1540) );
AOI21X1TS U2336 ( .A0(DMP_SFG[21]), .A1(DmP_mant_SFG_SWR[23]), .B0(n1796),
.Y(n1542) );
AOI21X1TS U2337 ( .A0(DMP_SFG[23]), .A1(DmP_mant_SFG_SWR[25]), .B0(n1783),
.Y(n1544) );
AOI21X1TS U2338 ( .A0(DMP_SFG[25]), .A1(DmP_mant_SFG_SWR[27]), .B0(n1770),
.Y(n1546) );
AOI21X1TS U2339 ( .A0(DMP_SFG[27]), .A1(DmP_mant_SFG_SWR[29]), .B0(n1756),
.Y(n1548) );
AOI2BB1X2TS U2340 ( .A0N(DMP_SFG[27]), .A1N(DmP_mant_SFG_SWR[29]), .B0(n1548), .Y(n1750) );
AOI2BB1X2TS U2341 ( .A0N(DMP_SFG[29]), .A1N(DmP_mant_SFG_SWR[31]), .B0(n1550), .Y(n1737) );
AOI2BB1X2TS U2342 ( .A0N(DMP_SFG[31]), .A1N(DmP_mant_SFG_SWR[33]), .B0(n1552), .Y(n1724) );
AOI2BB1X2TS U2343 ( .A0N(DMP_SFG[33]), .A1N(DmP_mant_SFG_SWR[35]), .B0(n1554), .Y(n1711) );
OAI21X2TS U2344 ( .A0(DmP_mant_SFG_SWR[36]), .A1(DMP_SFG[34]), .B0(n1711),
.Y(n1555) );
OAI21X2TS U2345 ( .A0(n2242), .A1(n2309), .B0(n1555), .Y(n1704) );
AOI21X1TS U2346 ( .A0(DMP_SFG[35]), .A1(DmP_mant_SFG_SWR[37]), .B0(n1704),
.Y(n1556) );
AOI2BB1X2TS U2347 ( .A0N(DMP_SFG[35]), .A1N(DmP_mant_SFG_SWR[37]), .B0(n1556), .Y(n1620) );
OAI21X2TS U2348 ( .A0(DmP_mant_SFG_SWR[38]), .A1(DMP_SFG[36]), .B0(n1620),
.Y(n1557) );
AOI2BB1X2TS U2349 ( .A0N(DMP_SFG[39]), .A1N(DmP_mant_SFG_SWR[41]), .B0(n1560), .Y(n1679) );
AOI21X2TS U2350 ( .A0(DMP_SFG[41]), .A1(DmP_mant_SFG_SWR[43]), .B0(n1672),
.Y(n1562) );
AOI2BB1X2TS U2351 ( .A0N(DMP_SFG[41]), .A1N(DmP_mant_SFG_SWR[43]), .B0(n1562), .Y(n1666) );
OAI21X2TS U2352 ( .A0(DmP_mant_SFG_SWR[44]), .A1(DMP_SFG[42]), .B0(n1666),
.Y(n1563) );
AOI21X2TS U2353 ( .A0(DMP_SFG[45]), .A1(DmP_mant_SFG_SWR[47]), .B0(n1646),
.Y(n1566) );
AOI2BB1X2TS U2354 ( .A0N(DMP_SFG[45]), .A1N(DmP_mant_SFG_SWR[47]), .B0(n1566), .Y(n1640) );
OAI21X2TS U2355 ( .A0(DmP_mant_SFG_SWR[48]), .A1(DMP_SFG[46]), .B0(n1640),
.Y(n1567) );
AOI21X2TS U2356 ( .A0(DMP_SFG[47]), .A1(DmP_mant_SFG_SWR[49]), .B0(n1633),
.Y(n1568) );
AOI21X1TS U2357 ( .A0(DMP_SFG[49]), .A1(DmP_mant_SFG_SWR[51]), .B0(n1597),
.Y(n1570) );
OAI21X1TS U2358 ( .A0(DmP_mant_SFG_SWR[52]), .A1(DMP_SFG[50]), .B0(n1603),
.Y(n1571) );
AOI21X1TS U2359 ( .A0(DmP_mant_SFG_SWR[53]), .A1(n893), .B0(n1613), .Y(n1572) );
OA21XLTS U2360 ( .A0(n1609), .A1(DmP_mant_SFG_SWR[54]), .B0(n1922), .Y(
ADD_OVRFLW_SGF) );
NOR2X1TS U2361 ( .A(N94), .B(N95), .Y(n1933) );
AOI21X1TS U2362 ( .A0(DMP_SFG[0]), .A1(n2291), .B0(n1933), .Y(n1573) );
AOI21X1TS U2363 ( .A0(DmP_mant_SFG_SWR[2]), .A1(n2292), .B0(n1573), .Y(n1928) );
NOR2X1TS U2364 ( .A(n2296), .B(DmP_mant_SFG_SWR[3]), .Y(n1929) );
NAND2X1TS U2365 ( .A(DmP_mant_SFG_SWR[4]), .B(n2276), .Y(n1925) );
NOR2X1TS U2366 ( .A(DmP_mant_SFG_SWR[4]), .B(n2276), .Y(n1924) );
AOI21X1TS U2367 ( .A0(n1923), .A1(n1925), .B0(n1924), .Y(n1914) );
NOR2X1TS U2368 ( .A(n2295), .B(DMP_SFG[3]), .Y(n1915) );
NOR2X1TS U2369 ( .A(n2294), .B(DmP_mant_SFG_SWR[5]), .Y(n1916) );
INVX2TS U2370 ( .A(n1916), .Y(n1574) );
OAI21X1TS U2371 ( .A0(n1914), .A1(n1915), .B0(n1574), .Y(n1908) );
NAND2X1TS U2372 ( .A(DmP_mant_SFG_SWR[6]), .B(n2227), .Y(n1910) );
NOR2X1TS U2373 ( .A(DmP_mant_SFG_SWR[6]), .B(n2227), .Y(n1909) );
AOI21X1TS U2374 ( .A0(n1908), .A1(n1910), .B0(n1909), .Y(n1901) );
NOR2X1TS U2375 ( .A(n2298), .B(DMP_SFG[5]), .Y(n1902) );
NOR2X1TS U2376 ( .A(n2297), .B(DmP_mant_SFG_SWR[7]), .Y(n1903) );
INVX2TS U2377 ( .A(n1903), .Y(n1575) );
OAI21X1TS U2378 ( .A0(n1901), .A1(n1902), .B0(n1575), .Y(n1895) );
NAND2X1TS U2379 ( .A(DmP_mant_SFG_SWR[8]), .B(n2278), .Y(n1897) );
NOR2X1TS U2380 ( .A(DmP_mant_SFG_SWR[8]), .B(n2278), .Y(n1896) );
AOI21X1TS U2381 ( .A0(n1895), .A1(n1897), .B0(n1896), .Y(n1888) );
NOR2X1TS U2382 ( .A(n2301), .B(DMP_SFG[7]), .Y(n1889) );
NOR2X1TS U2383 ( .A(n2300), .B(DmP_mant_SFG_SWR[9]), .Y(n1890) );
INVX2TS U2384 ( .A(n1890), .Y(n1576) );
OAI21X1TS U2385 ( .A0(n1888), .A1(n1889), .B0(n1576), .Y(n1882) );
NAND2X1TS U2386 ( .A(DmP_mant_SFG_SWR[10]), .B(n2279), .Y(n1884) );
NOR2X1TS U2387 ( .A(DmP_mant_SFG_SWR[10]), .B(n2279), .Y(n1883) );
AOI21X1TS U2388 ( .A0(n1882), .A1(n1884), .B0(n1883), .Y(n1875) );
NOR2X1TS U2389 ( .A(n2304), .B(DMP_SFG[9]), .Y(n1876) );
NOR2X1TS U2390 ( .A(n2302), .B(DmP_mant_SFG_SWR[11]), .Y(n1877) );
INVX2TS U2391 ( .A(n1877), .Y(n1577) );
OAI21X1TS U2392 ( .A0(n1875), .A1(n1876), .B0(n1577), .Y(n1869) );
NAND2X1TS U2393 ( .A(DmP_mant_SFG_SWR[12]), .B(n2230), .Y(n1871) );
NOR2X1TS U2394 ( .A(DmP_mant_SFG_SWR[12]), .B(n2230), .Y(n1870) );
AOI21X1TS U2395 ( .A0(n1869), .A1(n1871), .B0(n1870), .Y(n1861) );
NOR2X1TS U2396 ( .A(n2305), .B(DMP_SFG[11]), .Y(n1863) );
NOR2X1TS U2397 ( .A(n2303), .B(DmP_mant_SFG_SWR[13]), .Y(n1864) );
INVX2TS U2398 ( .A(n1864), .Y(n1578) );
OAI21X1TS U2399 ( .A0(n1861), .A1(n1863), .B0(n1578), .Y(n1854) );
NAND2X1TS U2400 ( .A(DmP_mant_SFG_SWR[14]), .B(n2281), .Y(n1857) );
NOR2X1TS U2401 ( .A(DmP_mant_SFG_SWR[14]), .B(n2281), .Y(n1858) );
AOI21X1TS U2402 ( .A0(n1854), .A1(n1857), .B0(n1858), .Y(n1848) );
NOR2X1TS U2403 ( .A(n2308), .B(DMP_SFG[13]), .Y(n1850) );
NOR2X1TS U2404 ( .A(n2307), .B(DmP_mant_SFG_SWR[15]), .Y(n1851) );
INVX2TS U2405 ( .A(n1851), .Y(n1579) );
OAI21X1TS U2406 ( .A0(n1848), .A1(n1850), .B0(n1579), .Y(n1841) );
NAND2X1TS U2407 ( .A(DmP_mant_SFG_SWR[16]), .B(n2282), .Y(n1844) );
NOR2X1TS U2408 ( .A(DmP_mant_SFG_SWR[16]), .B(n2282), .Y(n1845) );
AOI21X1TS U2409 ( .A0(n1841), .A1(n1844), .B0(n1845), .Y(n1835) );
NOR2X1TS U2410 ( .A(n2311), .B(DMP_SFG[15]), .Y(n1837) );
NOR2X1TS U2411 ( .A(n2310), .B(DmP_mant_SFG_SWR[17]), .Y(n1838) );
INVX2TS U2412 ( .A(n1838), .Y(n1580) );
OAI21X1TS U2413 ( .A0(n1835), .A1(n1837), .B0(n1580), .Y(n1828) );
NAND2X1TS U2414 ( .A(DmP_mant_SFG_SWR[18]), .B(n2233), .Y(n1831) );
NOR2X1TS U2415 ( .A(DmP_mant_SFG_SWR[18]), .B(n2233), .Y(n1832) );
AOI21X1TS U2416 ( .A0(n1828), .A1(n1831), .B0(n1832), .Y(n1822) );
NOR2X1TS U2417 ( .A(n2315), .B(DMP_SFG[17]), .Y(n1824) );
NOR2X1TS U2418 ( .A(n2313), .B(DmP_mant_SFG_SWR[19]), .Y(n1825) );
INVX2TS U2419 ( .A(n1825), .Y(n1581) );
OAI21X1TS U2420 ( .A0(n1822), .A1(n1824), .B0(n1581), .Y(n1814) );
NAND2X1TS U2421 ( .A(DmP_mant_SFG_SWR[20]), .B(n2284), .Y(n1817) );
NOR2X1TS U2422 ( .A(DmP_mant_SFG_SWR[20]), .B(n2284), .Y(n1818) );
NOR2X1TS U2423 ( .A(n2316), .B(DMP_SFG[19]), .Y(n1810) );
NOR2X1TS U2424 ( .A(n2314), .B(DmP_mant_SFG_SWR[21]), .Y(n1811) );
INVX2TS U2425 ( .A(n1811), .Y(n1582) );
OAI21X1TS U2426 ( .A0(n1808), .A1(n1810), .B0(n1582), .Y(n1801) );
NAND2X1TS U2427 ( .A(DmP_mant_SFG_SWR[22]), .B(n2286), .Y(n1804) );
NOR2X1TS U2428 ( .A(DmP_mant_SFG_SWR[22]), .B(n2286), .Y(n1805) );
NOR2X1TS U2429 ( .A(n2319), .B(DMP_SFG[21]), .Y(n1797) );
NOR2X1TS U2430 ( .A(n2318), .B(DmP_mant_SFG_SWR[23]), .Y(n1798) );
INVX2TS U2431 ( .A(n1798), .Y(n1583) );
NAND2X1TS U2432 ( .A(DmP_mant_SFG_SWR[24]), .B(n2236), .Y(n1791) );
NOR2X1TS U2433 ( .A(DmP_mant_SFG_SWR[24]), .B(n2236), .Y(n1792) );
NOR2X1TS U2434 ( .A(n2322), .B(DMP_SFG[23]), .Y(n1784) );
NOR2X1TS U2435 ( .A(n2321), .B(DmP_mant_SFG_SWR[25]), .Y(n1785) );
NOR2X1TS U2436 ( .A(DmP_mant_SFG_SWR[26]), .B(n2288), .Y(n1779) );
NOR2X1TS U2437 ( .A(n2326), .B(DMP_SFG[25]), .Y(n1771) );
NOR2X1TS U2438 ( .A(n2324), .B(DmP_mant_SFG_SWR[27]), .Y(n1772) );
NOR2X1TS U2439 ( .A(DmP_mant_SFG_SWR[28]), .B(n2290), .Y(n1765) );
NOR2X1TS U2440 ( .A(n2327), .B(DMP_SFG[27]), .Y(n1757) );
NOR2X1TS U2441 ( .A(n2325), .B(DmP_mant_SFG_SWR[29]), .Y(n1758) );
NOR2X1TS U2442 ( .A(DmP_mant_SFG_SWR[30]), .B(n2239), .Y(n1752) );
NOR2X1TS U2443 ( .A(n2332), .B(DMP_SFG[29]), .Y(n1744) );
NOR2X1TS U2444 ( .A(n2331), .B(DmP_mant_SFG_SWR[31]), .Y(n1745) );
NOR2X1TS U2445 ( .A(DmP_mant_SFG_SWR[32]), .B(n2299), .Y(n1739) );
NOR2X1TS U2446 ( .A(n2340), .B(DMP_SFG[31]), .Y(n1731) );
NOR2X1TS U2447 ( .A(n2339), .B(DmP_mant_SFG_SWR[33]), .Y(n1732) );
NOR2X1TS U2448 ( .A(DmP_mant_SFG_SWR[34]), .B(n2306), .Y(n1726) );
NOR2X1TS U2449 ( .A(n2347), .B(DMP_SFG[33]), .Y(n1718) );
NOR2X1TS U2450 ( .A(n2345), .B(DmP_mant_SFG_SWR[35]), .Y(n1719) );
NOR2X1TS U2451 ( .A(DmP_mant_SFG_SWR[36]), .B(n2242), .Y(n1713) );
NOR2X1TS U2452 ( .A(n2348), .B(DMP_SFG[35]), .Y(n1705) );
NOR2X1TS U2453 ( .A(n2346), .B(DmP_mant_SFG_SWR[37]), .Y(n1706) );
NOR2X1TS U2454 ( .A(DmP_mant_SFG_SWR[38]), .B(n2317), .Y(n1622) );
NOR2X1TS U2455 ( .A(n2352), .B(DMP_SFG[37]), .Y(n1699) );
NOR2X1TS U2456 ( .A(n2351), .B(DmP_mant_SFG_SWR[39]), .Y(n1700) );
NOR2X1TS U2457 ( .A(DmP_mant_SFG_SWR[40]), .B(n2323), .Y(n1694) );
NOR2X1TS U2458 ( .A(n2358), .B(DMP_SFG[39]), .Y(n1686) );
NOR2X1TS U2459 ( .A(n2357), .B(DmP_mant_SFG_SWR[41]), .Y(n1687) );
OAI21X1TS U2460 ( .A0(n1684), .A1(n1686), .B0(n1592), .Y(n1677) );
NOR2X1TS U2461 ( .A(DmP_mant_SFG_SWR[42]), .B(n2248), .Y(n1681) );
AOI21X1TS U2462 ( .A0(n1677), .A1(n1680), .B0(n1681), .Y(n1671) );
NOR2X1TS U2463 ( .A(n2362), .B(DMP_SFG[41]), .Y(n1673) );
NOR2X1TS U2464 ( .A(n2360), .B(DmP_mant_SFG_SWR[43]), .Y(n1674) );
OAI21X1TS U2465 ( .A0(n1671), .A1(n1673), .B0(n1593), .Y(n1664) );
NOR2X1TS U2466 ( .A(DmP_mant_SFG_SWR[44]), .B(n2343), .Y(n1668) );
AOI21X1TS U2467 ( .A0(n1664), .A1(n1667), .B0(n1668), .Y(n1658) );
NOR2X1TS U2468 ( .A(n2363), .B(DMP_SFG[43]), .Y(n1660) );
NOR2X1TS U2469 ( .A(n2361), .B(DmP_mant_SFG_SWR[45]), .Y(n1661) );
OAI21X1TS U2470 ( .A0(n1658), .A1(n1660), .B0(n1594), .Y(n1651) );
NOR2X1TS U2471 ( .A(DmP_mant_SFG_SWR[46]), .B(n2355), .Y(n1655) );
AOI21X1TS U2472 ( .A0(n1651), .A1(n1654), .B0(n1655), .Y(n1645) );
NOR2X1TS U2473 ( .A(n2366), .B(DMP_SFG[45]), .Y(n1647) );
NOR2X1TS U2474 ( .A(n2365), .B(DmP_mant_SFG_SWR[47]), .Y(n1648) );
OAI21X1TS U2475 ( .A0(n1645), .A1(n1647), .B0(n1595), .Y(n1638) );
NOR2X1TS U2476 ( .A(DmP_mant_SFG_SWR[48]), .B(n2253), .Y(n1642) );
AOI21X1TS U2477 ( .A0(n1638), .A1(n1641), .B0(n1642), .Y(n1632) );
NOR2X1TS U2478 ( .A(n2417), .B(DMP_SFG[47]), .Y(n1634) );
NOR2X1TS U2479 ( .A(n2416), .B(DmP_mant_SFG_SWR[49]), .Y(n1635) );
OAI21X1TS U2480 ( .A0(n1632), .A1(n1634), .B0(n1596), .Y(n1625) );
NOR2X1TS U2481 ( .A(DmP_mant_SFG_SWR[50]), .B(n2415), .Y(n1629) );
AOI21X1TS U2482 ( .A0(n1625), .A1(n1628), .B0(n1629), .Y(n1602) );
MXI2X1TS U2483 ( .A(n1597), .B(n1602), .S0(n1768), .Y(n1599) );
NOR2X1TS U2484 ( .A(n2422), .B(DmP_mant_SFG_SWR[51]), .Y(n1600) );
NOR2X1TS U2485 ( .A(n2423), .B(DMP_SFG[49]), .Y(n1601) );
MXI2X1TS U2486 ( .A(n1603), .B(n1607), .S0(n1768), .Y(n1605) );
XNOR2X1TS U2487 ( .A(n1605), .B(n1604), .Y(Raw_mant_SGF[52]) );
AOI22X1TS U2488 ( .A0(n1607), .A1(n1606), .B0(DmP_mant_SFG_SWR[52]), .B1(
n2420), .Y(n1611) );
NOR2BX1TS U2489 ( .AN(n893), .B(DmP_mant_SFG_SWR[53]), .Y(n1615) );
AOI211X1TS U2490 ( .A0(n1611), .A1(n1614), .B0(n1615), .C0(n1922), .Y(n1608)
);
AOI21X1TS U2491 ( .A0(n1609), .A1(n1922), .B0(n1608), .Y(n1610) );
CLKBUFX2TS U2492 ( .A(n1768), .Y(n1821) );
NAND2X1TS U2493 ( .A(n1611), .B(n1768), .Y(n1612) );
XNOR2X1TS U2494 ( .A(n1617), .B(n1616), .Y(Raw_mant_SGF[53]) );
AOI21X1TS U2495 ( .A0(n1620), .A1(n1922), .B0(n1619), .Y(n1624) );
XNOR2X1TS U2496 ( .A(n1624), .B(n1623), .Y(Raw_mant_SGF[38]) );
NOR2BX1TS U2497 ( .AN(exp_rslt_NRM2_EW1[10]), .B(
array_comparators_GTComparator_N0), .Y(formatted_number_W[62]) );
INVX4TS U2498 ( .A(n1768), .Y(n1934) );
AOI21X1TS U2499 ( .A0(n1627), .A1(n1922), .B0(n1626), .Y(n1631) );
XNOR2X1TS U2500 ( .A(n1631), .B(n1630), .Y(Raw_mant_SGF[50]) );
MXI2X1TS U2501 ( .A(n1633), .B(n1632), .S0(n1768), .Y(n1637) );
AOI21X1TS U2502 ( .A0(n1640), .A1(n1922), .B0(n1639), .Y(n1644) );
XNOR2X1TS U2503 ( .A(n1644), .B(n1643), .Y(Raw_mant_SGF[48]) );
MXI2X1TS U2504 ( .A(n1646), .B(n1645), .S0(n1768), .Y(n1650) );
AOI21X1TS U2505 ( .A0(n1653), .A1(n1922), .B0(n1652), .Y(n1657) );
XNOR2X1TS U2506 ( .A(n1657), .B(n1656), .Y(Raw_mant_SGF[46]) );
MXI2X1TS U2507 ( .A(n1659), .B(n1658), .S0(n1768), .Y(n1663) );
AOI21X1TS U2508 ( .A0(n1666), .A1(n1922), .B0(n1665), .Y(n1670) );
XNOR2X1TS U2509 ( .A(n1670), .B(n1669), .Y(Raw_mant_SGF[44]) );
MXI2X1TS U2510 ( .A(n1672), .B(n1671), .S0(n1768), .Y(n1676) );
NOR2XLTS U2511 ( .A(n1674), .B(n1673), .Y(n1675) );
AOI21X1TS U2512 ( .A0(n1679), .A1(n1922), .B0(n1678), .Y(n1683) );
XNOR2X1TS U2513 ( .A(n1683), .B(n1682), .Y(Raw_mant_SGF[42]) );
MXI2X1TS U2514 ( .A(n1685), .B(n1684), .S0(n1821), .Y(n1689) );
NOR2XLTS U2515 ( .A(n1687), .B(n1686), .Y(n1688) );
AOI21X1TS U2516 ( .A0(n1692), .A1(n1922), .B0(n1691), .Y(n1696) );
XNOR2X1TS U2517 ( .A(n1696), .B(n1695), .Y(Raw_mant_SGF[40]) );
MXI2X1TS U2518 ( .A(n1698), .B(n1697), .S0(n1768), .Y(n1702) );
NOR2XLTS U2519 ( .A(n1700), .B(n1699), .Y(n1701) );
MXI2X1TS U2520 ( .A(n1704), .B(n1703), .S0(n1768), .Y(n1708) );
NOR2XLTS U2521 ( .A(n1706), .B(n1705), .Y(n1707) );
AOI21X1TS U2522 ( .A0(n1711), .A1(n1919), .B0(n1710), .Y(n1715) );
XNOR2X1TS U2523 ( .A(n1715), .B(n1714), .Y(Raw_mant_SGF[36]) );
MXI2X1TS U2524 ( .A(n1717), .B(n1716), .S0(n1821), .Y(n1721) );
NOR2XLTS U2525 ( .A(n1719), .B(n1718), .Y(n1720) );
AOI21X1TS U2526 ( .A0(n1724), .A1(n1922), .B0(n1723), .Y(n1728) );
XNOR2X1TS U2527 ( .A(n1728), .B(n1727), .Y(Raw_mant_SGF[34]) );
MXI2X1TS U2528 ( .A(n1730), .B(n1729), .S0(n1768), .Y(n1734) );
NOR2XLTS U2529 ( .A(n1732), .B(n1731), .Y(n1733) );
AOI21X1TS U2530 ( .A0(n1737), .A1(n1919), .B0(n1736), .Y(n1741) );
XNOR2X1TS U2531 ( .A(n1741), .B(n1740), .Y(Raw_mant_SGF[32]) );
MXI2X1TS U2532 ( .A(n1743), .B(n1742), .S0(n1768), .Y(n1747) );
NOR2XLTS U2533 ( .A(n1745), .B(n1744), .Y(n1746) );
XOR2XLTS U2534 ( .A(n1747), .B(n1746), .Y(Raw_mant_SGF[31]) );
NOR2XLTS U2535 ( .A(n1748), .B(n1919), .Y(n1749) );
AOI21X1TS U2536 ( .A0(n1750), .A1(n1934), .B0(n1749), .Y(n1754) );
XNOR2X1TS U2537 ( .A(n1754), .B(n1753), .Y(Raw_mant_SGF[30]) );
MXI2X1TS U2538 ( .A(n1756), .B(n1755), .S0(n1768), .Y(n1760) );
NOR2XLTS U2539 ( .A(n1758), .B(n1757), .Y(n1759) );
XOR2XLTS U2540 ( .A(n1760), .B(n1759), .Y(Raw_mant_SGF[29]) );
NOR2XLTS U2541 ( .A(n1761), .B(n1919), .Y(n1762) );
AOI21X1TS U2542 ( .A0(n1763), .A1(n1922), .B0(n1762), .Y(n1767) );
XNOR2X1TS U2543 ( .A(n1767), .B(n1766), .Y(Raw_mant_SGF[28]) );
MXI2X1TS U2544 ( .A(n1770), .B(n1769), .S0(n1768), .Y(n1774) );
NOR2XLTS U2545 ( .A(n1772), .B(n1771), .Y(n1773) );
XOR2XLTS U2546 ( .A(n1774), .B(n1773), .Y(Raw_mant_SGF[27]) );
AOI21X1TS U2547 ( .A0(n1777), .A1(n1922), .B0(n1776), .Y(n1781) );
XNOR2X1TS U2548 ( .A(n1781), .B(n1780), .Y(Raw_mant_SGF[26]) );
MXI2X1TS U2549 ( .A(n1783), .B(n1782), .S0(n1768), .Y(n1787) );
NOR2XLTS U2550 ( .A(n1785), .B(n1784), .Y(n1786) );
XOR2XLTS U2551 ( .A(n1787), .B(n1786), .Y(Raw_mant_SGF[25]) );
NOR2XLTS U2552 ( .A(n1788), .B(n1919), .Y(n1789) );
AOI21X1TS U2553 ( .A0(n1790), .A1(n1919), .B0(n1789), .Y(n1794) );
XNOR2X1TS U2554 ( .A(n1794), .B(n1793), .Y(Raw_mant_SGF[24]) );
MXI2X1TS U2555 ( .A(n1796), .B(n1795), .S0(n1821), .Y(n1800) );
XOR2XLTS U2556 ( .A(n1800), .B(n1799), .Y(Raw_mant_SGF[23]) );
NOR2XLTS U2557 ( .A(n1801), .B(n1934), .Y(n1802) );
AOI21X1TS U2558 ( .A0(n1803), .A1(n1922), .B0(n1802), .Y(n1807) );
XNOR2X1TS U2559 ( .A(n1807), .B(n1806), .Y(Raw_mant_SGF[22]) );
MXI2X1TS U2560 ( .A(n1809), .B(n1808), .S0(n1821), .Y(n1813) );
XOR2XLTS U2561 ( .A(n1813), .B(n1812), .Y(Raw_mant_SGF[21]) );
NOR2XLTS U2562 ( .A(n1814), .B(n1934), .Y(n1815) );
AOI21X1TS U2563 ( .A0(n1816), .A1(n1934), .B0(n1815), .Y(n1820) );
XNOR2X1TS U2564 ( .A(n1820), .B(n1819), .Y(Raw_mant_SGF[20]) );
MXI2X1TS U2565 ( .A(n1823), .B(n1822), .S0(n1821), .Y(n1827) );
NOR2XLTS U2566 ( .A(n1825), .B(n1824), .Y(n1826) );
XOR2XLTS U2567 ( .A(n1827), .B(n1826), .Y(Raw_mant_SGF[19]) );
NOR2XLTS U2568 ( .A(n1828), .B(n1919), .Y(n1829) );
AOI21X1TS U2569 ( .A0(n1830), .A1(n1922), .B0(n1829), .Y(n1834) );
XNOR2X1TS U2570 ( .A(n1834), .B(n1833), .Y(Raw_mant_SGF[18]) );
MXI2X1TS U2571 ( .A(n1836), .B(n1835), .S0(n1768), .Y(n1840) );
NOR2XLTS U2572 ( .A(n1838), .B(n1837), .Y(n1839) );
XOR2XLTS U2573 ( .A(n1840), .B(n1839), .Y(Raw_mant_SGF[17]) );
AOI21X1TS U2574 ( .A0(n1843), .A1(n1922), .B0(n1842), .Y(n1847) );
XNOR2X1TS U2575 ( .A(n1847), .B(n1846), .Y(Raw_mant_SGF[16]) );
MXI2X1TS U2576 ( .A(n1849), .B(n1848), .S0(n1768), .Y(n1853) );
NOR2XLTS U2577 ( .A(n1851), .B(n1850), .Y(n1852) );
XOR2XLTS U2578 ( .A(n1853), .B(n1852), .Y(Raw_mant_SGF[15]) );
NOR2XLTS U2579 ( .A(n1854), .B(n1934), .Y(n1855) );
AOI21X1TS U2580 ( .A0(n1856), .A1(n1922), .B0(n1855), .Y(n1860) );
XNOR2X1TS U2581 ( .A(n1860), .B(n1859), .Y(Raw_mant_SGF[14]) );
MXI2X1TS U2582 ( .A(n1862), .B(n1861), .S0(n1768), .Y(n1866) );
NOR2XLTS U2583 ( .A(n1864), .B(n1863), .Y(n1865) );
XOR2XLTS U2584 ( .A(n1866), .B(n1865), .Y(Raw_mant_SGF[13]) );
OAI21XLTS U2585 ( .A0(n1934), .A1(n1869), .B0(n1868), .Y(n1873) );
NOR2BX1TS U2586 ( .AN(n1871), .B(n1870), .Y(n1872) );
XNOR2X1TS U2587 ( .A(n1873), .B(n1872), .Y(Raw_mant_SGF[12]) );
MXI2X1TS U2588 ( .A(n1875), .B(n1874), .S0(n1934), .Y(n1879) );
XOR2XLTS U2589 ( .A(n1879), .B(n1878), .Y(Raw_mant_SGF[11]) );
NOR2BX1TS U2590 ( .AN(n1884), .B(n1883), .Y(n1885) );
XNOR2X1TS U2591 ( .A(n1886), .B(n1885), .Y(Raw_mant_SGF[10]) );
MXI2X1TS U2592 ( .A(n1888), .B(n1887), .S0(n1934), .Y(n1892) );
NOR2XLTS U2593 ( .A(n1890), .B(n1889), .Y(n1891) );
XOR2XLTS U2594 ( .A(n1892), .B(n1891), .Y(Raw_mant_SGF[9]) );
OAI21XLTS U2595 ( .A0(n1895), .A1(n1922), .B0(n1894), .Y(n1899) );
NOR2BX1TS U2596 ( .AN(n1897), .B(n1896), .Y(n1898) );
XNOR2X1TS U2597 ( .A(n1899), .B(n1898), .Y(Raw_mant_SGF[8]) );
MXI2X1TS U2598 ( .A(n1901), .B(n1900), .S0(n1934), .Y(n1905) );
NOR2XLTS U2599 ( .A(n1903), .B(n1902), .Y(n1904) );
XOR2XLTS U2600 ( .A(n1905), .B(n1904), .Y(Raw_mant_SGF[7]) );
OAI21XLTS U2601 ( .A0(n1908), .A1(n1922), .B0(n1907), .Y(n1912) );
NOR2BX1TS U2602 ( .AN(n1910), .B(n1909), .Y(n1911) );
XNOR2X1TS U2603 ( .A(n1912), .B(n1911), .Y(Raw_mant_SGF[6]) );
MXI2X1TS U2604 ( .A(n1914), .B(n1913), .S0(n1934), .Y(n1918) );
NOR2XLTS U2605 ( .A(n1916), .B(n1915), .Y(n1917) );
XOR2XLTS U2606 ( .A(n1918), .B(n1917), .Y(Raw_mant_SGF[5]) );
NOR2BX1TS U2607 ( .AN(n1925), .B(n1924), .Y(n1926) );
XNOR2X1TS U2608 ( .A(n1927), .B(n1926), .Y(Raw_mant_SGF[4]) );
MXI2X1TS U2609 ( .A(n1928), .B(n1935), .S0(n1934), .Y(n1932) );
NOR2BX1TS U2610 ( .AN(n1930), .B(n1929), .Y(n1931) );
XNOR2X1TS U2611 ( .A(n1932), .B(n1931), .Y(Raw_mant_SGF[3]) );
NOR2XLTS U2612 ( .A(n1934), .B(n1933), .Y(n1937) );
OAI21XLTS U2613 ( .A0(DMP_SFG[0]), .A1(DmP_mant_SFG_SWR[2]), .B0(n1935), .Y(
n1936) );
XNOR2X1TS U2614 ( .A(n1937), .B(n1936), .Y(Raw_mant_SGF[2]) );
XOR2XLTS U2615 ( .A(DMP_EXP_EWSW[57]), .B(DmP_EXP_EWSW[57]), .Y(n1938) );
XOR2XLTS U2616 ( .A(intadd_470_n1), .B(n1938), .Y(Shift_amount_EXP_EW[5]) );
AOI22X1TS U2617 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1939), .B1(n873), .Y(n2536)
);
XNOR2X1TS U2618 ( .A(add_subt), .B(Data_Y[63]), .Y(n2483) );
XNOR2X1TS U2619 ( .A(intDX_EWSW[63]), .B(n2535), .Y(OP_FLAG_INIT) );
OAI22X1TS U2620 ( .A0(n2388), .A1(intDY_EWSW[38]), .B0(n875), .B1(
intDY_EWSW[22]), .Y(n1940) );
AOI22X1TS U2621 ( .A0(n2412), .A1(intDY_EWSW[58]), .B0(n2273), .B1(
intDY_EWSW[59]), .Y(n1942) );
AOI22X1TS U2622 ( .A0(n2268), .A1(intDY_EWSW[32]), .B0(n2396), .B1(
intDY_EWSW[33]), .Y(n1943) );
NAND2BXLTS U2623 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2097) );
AOI221X1TS U2624 ( .A0(n2270), .A1(intDY_EWSW[47]), .B0(intDY_EWSW[46]),
.B1(n2403), .C0(n2108), .Y(n1950) );
INVX2TS U2625 ( .A(intDX_EWSW[36]), .Y(n2114) );
OAI22X1TS U2626 ( .A0(n2387), .A1(intDY_EWSW[37]), .B0(n2368), .B1(
intDY_EWSW[36]), .Y(n1944) );
AOI221X1TS U2627 ( .A0(n2387), .A1(intDY_EWSW[37]), .B0(intDY_EWSW[36]),
.B1(n2114), .C0(n1944), .Y(n1949) );
OAI22X1TS U2628 ( .A0(n2381), .A1(intDY_EWSW[35]), .B0(n877), .B1(
intDY_EWSW[34]), .Y(n1945) );
OAI22X1TS U2629 ( .A0(n874), .A1(intDY_EWSW[42]), .B0(n891), .B1(
intDY_EWSW[41]), .Y(n1946) );
NAND4XLTS U2630 ( .A(n1950), .B(n1949), .C(n1948), .D(n1947), .Y(n1951) );
NOR4X1TS U2631 ( .A(n1954), .B(n1953), .C(n1952), .D(n1951), .Y(n2009) );
AOI22X1TS U2632 ( .A0(n2410), .A1(intDY_EWSW[62]), .B0(n2413), .B1(
intDY_EWSW[60]), .Y(n1955) );
AOI22X1TS U2633 ( .A0(n2392), .A1(intDY_EWSW[53]), .B0(n2399), .B1(
intDY_EWSW[10]), .Y(n1956) );
AOI22X1TS U2634 ( .A0(n2394), .A1(intDY_EWSW[51]), .B0(n2400), .B1(
intDY_EWSW[48]), .Y(n1957) );
AOI22X1TS U2635 ( .A0(n2269), .A1(intDY_EWSW[56]), .B0(n2398), .B1(
intDY_EWSW[57]), .Y(n1958) );
OAI221XLTS U2636 ( .A0(n2269), .A1(intDY_EWSW[56]), .B0(n2398), .B1(
intDY_EWSW[57]), .C0(n1958), .Y(n1959) );
NOR4X1TS U2637 ( .A(n1962), .B(n1961), .C(n1960), .D(n1959), .Y(n2008) );
AOI22X1TS U2638 ( .A0(n2267), .A1(intDY_EWSW[55]), .B0(n2401), .B1(
intDY_EWSW[52]), .Y(n1963) );
AOI22X1TS U2639 ( .A0(n2393), .A1(intDY_EWSW[44]), .B0(n2397), .B1(
intDY_EWSW[45]), .Y(n1964) );
OAI221XLTS U2640 ( .A0(n2393), .A1(intDY_EWSW[44]), .B0(n2397), .B1(
intDY_EWSW[45]), .C0(n1964), .Y(n1969) );
AOI22X1TS U2641 ( .A0(n2390), .A1(intDY_EWSW[11]), .B0(n2395), .B1(
intDY_EWSW[8]), .Y(n1965) );
OAI221XLTS U2642 ( .A0(n2390), .A1(intDY_EWSW[11]), .B0(n2395), .B1(
intDY_EWSW[8]), .C0(n1965), .Y(n1968) );
AOI22X1TS U2643 ( .A0(n2391), .A1(intDY_EWSW[49]), .B0(n2402), .B1(
intDY_EWSW[54]), .Y(n1966) );
NOR4X1TS U2644 ( .A(n1970), .B(n1969), .C(n1967), .D(n1968), .Y(n2007) );
OAI22X1TS U2645 ( .A0(n2378), .A1(intDY_EWSW[15]), .B0(n2372), .B1(
intDY_EWSW[12]), .Y(n1971) );
INVX2TS U2646 ( .A(intDX_EWSW[26]), .Y(n2165) );
OAI22X1TS U2647 ( .A0(n2364), .A1(intDY_EWSW[5]), .B0(n2256), .B1(
intDY_EWSW[26]), .Y(n1972) );
AOI221X1TS U2648 ( .A0(n2364), .A1(intDY_EWSW[5]), .B0(intDY_EWSW[26]), .B1(
n2165), .C0(n1972), .Y(n1977) );
OAI22X1TS U2649 ( .A0(n2377), .A1(intDY_EWSW[3]), .B0(n2371), .B1(
intDY_EWSW[6]), .Y(n1973) );
AOI221X1TS U2650 ( .A0(n2377), .A1(intDY_EWSW[3]), .B0(intDY_EWSW[6]), .B1(
n2371), .C0(n1973), .Y(n1976) );
OAI22X1TS U2651 ( .A0(n2266), .A1(intDY_EWSW[9]), .B0(n880), .B1(
intDY_EWSW[14]), .Y(n1974) );
AOI221X1TS U2652 ( .A0(n2266), .A1(intDY_EWSW[9]), .B0(intDY_EWSW[14]), .B1(
n880), .C0(n1974), .Y(n1975) );
NAND4XLTS U2653 ( .A(n1978), .B(n1977), .C(n1976), .D(n1975), .Y(n2005) );
OAI22X1TS U2654 ( .A0(n2252), .A1(intDY_EWSW[7]), .B0(n2370), .B1(
intDY_EWSW[4]), .Y(n1979) );
AOI221X1TS U2655 ( .A0(n2252), .A1(intDY_EWSW[7]), .B0(intDY_EWSW[4]), .B1(
n2370), .C0(n1979), .Y(n1986) );
INVX2TS U2656 ( .A(intDX_EWSW[50]), .Y(n2168) );
OAI22X1TS U2657 ( .A0(n2265), .A1(intDY_EWSW[50]), .B0(n2406), .B1(
intDY_EWSW[61]), .Y(n1980) );
AOI221X1TS U2658 ( .A0(n2168), .A1(intDY_EWSW[50]), .B0(intDY_EWSW[61]),
.B1(n2406), .C0(n1980), .Y(n1985) );
OAI22X1TS U2659 ( .A0(n881), .A1(intDY_EWSW[27]), .B0(n2262), .B1(
intDY_EWSW[40]), .Y(n1981) );
AOI221X1TS U2660 ( .A0(n881), .A1(intDY_EWSW[27]), .B0(intDY_EWSW[40]), .B1(
n2262), .C0(n1981), .Y(n1984) );
OAI22X1TS U2661 ( .A0(n2263), .A1(intDY_EWSW[0]), .B0(n2369), .B1(
intDY_EWSW[1]), .Y(n1982) );
AOI221X1TS U2662 ( .A0(n2263), .A1(intDY_EWSW[0]), .B0(intDY_EWSW[1]), .B1(
n2369), .C0(n1982), .Y(n1983) );
NAND4XLTS U2663 ( .A(n1986), .B(n1985), .C(n1984), .D(n1983), .Y(n2004) );
INVX2TS U2664 ( .A(intDX_EWSW[17]), .Y(n2163) );
OAI22X1TS U2665 ( .A0(n2383), .A1(intDY_EWSW[16]), .B0(n2367), .B1(
intDY_EWSW[17]), .Y(n1987) );
AOI221X1TS U2666 ( .A0(n2383), .A1(intDY_EWSW[16]), .B0(intDY_EWSW[17]),
.B1(n2163), .C0(n1987), .Y(n1993) );
OAI22X1TS U2667 ( .A0(n2380), .A1(intDY_EWSW[31]), .B0(n876), .B1(
intDY_EWSW[30]), .Y(n1988) );
OAI22X1TS U2668 ( .A0(n2264), .A1(intDY_EWSW[43]), .B0(n2255), .B1(n872),
.Y(n1989) );
INVX2TS U2669 ( .A(intDX_EWSW[18]), .Y(n2172) );
NAND2BXLTS U2670 ( .AN(intDY_EWSW[19]), .B(intDX_EWSW[19]), .Y(n2065) );
AOI221X1TS U2671 ( .A0(n2404), .A1(intDY_EWSW[18]), .B0(intDY_EWSW[19]),
.B1(n2271), .C0(n2069), .Y(n1990) );
NAND4XLTS U2672 ( .A(n1993), .B(n1992), .C(n1991), .D(n1990), .Y(n2003) );
OAI22X1TS U2673 ( .A0(n2379), .A1(intDY_EWSW[25]), .B0(n2259), .B1(
intDY_EWSW[24]), .Y(n1994) );
AOI221X1TS U2674 ( .A0(n2379), .A1(intDY_EWSW[25]), .B0(intDY_EWSW[24]),
.B1(n2259), .C0(n1994), .Y(n2001) );
OAI22X1TS U2675 ( .A0(n888), .A1(intDY_EWSW[13]), .B0(n2257), .B1(
intDY_EWSW[2]), .Y(n1995) );
OAI22X1TS U2676 ( .A0(n890), .A1(intDY_EWSW[29]), .B0(n2375), .B1(
intDY_EWSW[28]), .Y(n1996) );
OAI22X1TS U2677 ( .A0(n889), .A1(intDY_EWSW[21]), .B0(n2373), .B1(
intDY_EWSW[20]), .Y(n1997) );
NAND4XLTS U2678 ( .A(n2001), .B(n2000), .C(n1999), .D(n1998), .Y(n2002) );
NOR4X1TS U2679 ( .A(n2005), .B(n2004), .C(n2003), .D(n2002), .Y(n2006) );
NAND4XLTS U2680 ( .A(n2009), .B(n2008), .C(n2007), .D(n2006), .Y(n2158) );
NOR2BX1TS U2681 ( .AN(OP_FLAG_INIT), .B(n2158), .Y(ZERO_FLAG_INIT) );
NOR2BX1TS U2682 ( .AN(Shift_reg_FLAGS_7[3]), .B(Shift_reg_FLAGS_7[0]), .Y(
n_21_net_) );
NOR2XLTS U2683 ( .A(n2392), .B(intDY_EWSW[53]), .Y(n2010) );
INVX2TS U2684 ( .A(intDX_EWSW[55]), .Y(n2142) );
OAI22X1TS U2685 ( .A0(n2142), .A1(intDY_EWSW[55]), .B0(intDY_EWSW[54]), .B1(
n2402), .Y(n2132) );
AOI211X1TS U2686 ( .A0(intDX_EWSW[52]), .A1(n2467), .B0(n2010), .C0(n2132),
.Y(n2134) );
NOR2BX1TS U2687 ( .AN(intDX_EWSW[56]), .B(intDY_EWSW[56]), .Y(n2011) );
NOR2X1TS U2688 ( .A(n2398), .B(intDY_EWSW[57]), .Y(n2084) );
NAND2X1TS U2689 ( .A(n2337), .B(intDX_EWSW[61]), .Y(n2090) );
OAI211X1TS U2690 ( .A0(intDY_EWSW[60]), .A1(n2413), .B0(n2094), .C0(n2090),
.Y(n2096) );
OAI21X1TS U2691 ( .A0(intDY_EWSW[58]), .A1(n2412), .B0(n2086), .Y(n2088) );
NOR2X1TS U2692 ( .A(n2391), .B(intDY_EWSW[49]), .Y(n2135) );
NAND2BXLTS U2693 ( .AN(intDY_EWSW[51]), .B(intDX_EWSW[51]), .Y(n2137) );
OAI21X1TS U2694 ( .A0(intDY_EWSW[50]), .A1(n2168), .B0(n2137), .Y(n2141) );
AOI211X1TS U2695 ( .A0(intDX_EWSW[48]), .A1(n2466), .B0(n2135), .C0(n2141),
.Y(n2012) );
NAND3X1TS U2696 ( .A(n2134), .B(n2144), .C(n2012), .Y(n2152) );
NOR2BX1TS U2697 ( .AN(intDX_EWSW[39]), .B(intDY_EWSW[39]), .Y(n2126) );
AOI21X1TS U2698 ( .A0(intDX_EWSW[38]), .A1(n2477), .B0(n2126), .Y(n2125) );
NAND2X1TS U2699 ( .A(n2476), .B(intDX_EWSW[37]), .Y(n2113) );
OAI211X1TS U2700 ( .A0(intDY_EWSW[36]), .A1(n2114), .B0(n2125), .C0(n2113),
.Y(n2116) );
NOR2X1TS U2701 ( .A(n2397), .B(intDY_EWSW[45]), .Y(n2098) );
INVX2TS U2702 ( .A(intDX_EWSW[43]), .Y(n2101) );
OA22X1TS U2703 ( .A0(n874), .A1(intDY_EWSW[42]), .B0(n2101), .B1(
intDY_EWSW[43]), .Y(n2104) );
NAND2BXLTS U2704 ( .AN(intDY_EWSW[40]), .B(intDX_EWSW[40]), .Y(n2013) );
NAND4XLTS U2705 ( .A(n2106), .B(n2104), .C(n2014), .D(n2013), .Y(n2150) );
NAND2BXLTS U2706 ( .AN(intDY_EWSW[32]), .B(intDX_EWSW[32]), .Y(n2015) );
OA22X1TS U2707 ( .A0(n877), .A1(intDY_EWSW[34]), .B0(n2381), .B1(
intDY_EWSW[35]), .Y(n2120) );
OAI211XLTS U2708 ( .A0(n2396), .A1(intDY_EWSW[33]), .B0(n2015), .C0(n2120),
.Y(n2016) );
NOR4X1TS U2709 ( .A(n2152), .B(n2116), .C(n2150), .D(n2016), .Y(n2156) );
OA22X1TS U2710 ( .A0(n876), .A1(intDY_EWSW[30]), .B0(n2380), .B1(
intDY_EWSW[31]), .Y(n2027) );
OAI21XLTS U2711 ( .A0(intDY_EWSW[29]), .A1(n890), .B0(intDY_EWSW[28]), .Y(
n2017) );
NAND2BXLTS U2712 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n2020) );
OAI21X1TS U2713 ( .A0(intDY_EWSW[26]), .A1(n2165), .B0(n2020), .Y(n2079) );
NOR2X1TS U2714 ( .A(n2379), .B(intDY_EWSW[25]), .Y(n2076) );
NOR2XLTS U2715 ( .A(n2076), .B(intDX_EWSW[24]), .Y(n2019) );
AOI22X1TS U2716 ( .A0(n2019), .A1(intDY_EWSW[24]), .B0(intDY_EWSW[25]), .B1(
n2379), .Y(n2022) );
AOI32X1TS U2717 ( .A0(n2165), .A1(n2020), .A2(intDY_EWSW[26]), .B0(
intDY_EWSW[27]), .B1(n881), .Y(n2021) );
OAI32X1TS U2718 ( .A0(n2079), .A1(n2078), .A2(n2022), .B0(n2021), .B1(n2078),
.Y(n2025) );
OAI21XLTS U2719 ( .A0(intDY_EWSW[31]), .A1(n2380), .B0(intDY_EWSW[30]), .Y(
n2023) );
OAI2BB2XLTS U2720 ( .B0(intDX_EWSW[30]), .B1(n2023), .A0N(intDY_EWSW[31]),
.A1N(n2380), .Y(n2024) );
AOI211X1TS U2721 ( .A0(n2027), .A1(n2026), .B0(n2025), .C0(n2024), .Y(n2083)
);
INVX2TS U2722 ( .A(intDX_EWSW[23]), .Y(n2070) );
OA22X1TS U2723 ( .A0(n875), .A1(intDY_EWSW[22]), .B0(n2070), .B1(n872), .Y(
n2075) );
OA22X1TS U2724 ( .A0(n880), .A1(intDY_EWSW[14]), .B0(n2378), .B1(
intDY_EWSW[15]), .Y(n2055) );
OAI2BB1X1TS U2725 ( .A0N(n879), .A1N(intDX_EWSW[5]), .B0(intDY_EWSW[4]), .Y(
n2030) );
OAI22X1TS U2726 ( .A0(intDX_EWSW[4]), .A1(n2030), .B0(n879), .B1(
intDX_EWSW[5]), .Y(n2041) );
OAI2BB1X1TS U2727 ( .A0N(n878), .A1N(intDX_EWSW[7]), .B0(intDY_EWSW[6]), .Y(
n2031) );
OAI22X1TS U2728 ( .A0(intDX_EWSW[6]), .A1(n2031), .B0(n878), .B1(
intDX_EWSW[7]), .Y(n2040) );
NAND2BXLTS U2729 ( .AN(intDY_EWSW[2]), .B(intDX_EWSW[2]), .Y(n2034) );
AOI2BB2XLTS U2730 ( .B0(intDX_EWSW[1]), .B1(n2478), .A0N(intDY_EWSW[0]),
.A1N(n2032), .Y(n2033) );
OAI211XLTS U2731 ( .A0(n2377), .A1(intDY_EWSW[3]), .B0(n2034), .C0(n2033),
.Y(n2037) );
OAI21XLTS U2732 ( .A0(intDY_EWSW[3]), .A1(n2377), .B0(intDY_EWSW[2]), .Y(
n2035) );
AOI2BB2XLTS U2733 ( .B0(intDY_EWSW[3]), .B1(n2377), .A0N(intDX_EWSW[2]),
.A1N(n2035), .Y(n2036) );
AOI222X1TS U2734 ( .A0(intDX_EWSW[4]), .A1(n2274), .B0(intDX_EWSW[5]), .B1(
n879), .C0(n2037), .C1(n2036), .Y(n2039) );
AOI22X1TS U2735 ( .A0(intDX_EWSW[7]), .A1(n878), .B0(intDX_EWSW[6]), .B1(
n2275), .Y(n2038) );
OAI32X1TS U2736 ( .A0(n2041), .A1(n2040), .A2(n2039), .B0(n2038), .B1(n2040),
.Y(n2058) );
NAND2BXLTS U2737 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n2045) );
NOR2X1TS U2738 ( .A(n2390), .B(intDY_EWSW[11]), .Y(n2043) );
AOI21X1TS U2739 ( .A0(intDX_EWSW[10]), .A1(n2465), .B0(n2043), .Y(n2048) );
OAI211XLTS U2740 ( .A0(intDY_EWSW[8]), .A1(n2395), .B0(n2045), .C0(n2048),
.Y(n2057) );
OAI21XLTS U2741 ( .A0(intDY_EWSW[13]), .A1(n888), .B0(intDY_EWSW[12]), .Y(
n2042) );
NOR2XLTS U2742 ( .A(n2043), .B(intDX_EWSW[10]), .Y(n2044) );
AOI22X1TS U2743 ( .A0(intDY_EWSW[11]), .A1(n2390), .B0(intDY_EWSW[10]), .B1(
n2044), .Y(n2050) );
NAND3XLTS U2744 ( .A(n2395), .B(n2045), .C(intDY_EWSW[8]), .Y(n2047) );
NAND2BXLTS U2745 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n2046) );
AOI21X1TS U2746 ( .A0(n2047), .A1(n2046), .B0(n2059), .Y(n2049) );
OAI2BB2XLTS U2747 ( .B0(n2050), .B1(n2059), .A0N(n2049), .A1N(n2048), .Y(
n2053) );
OAI21XLTS U2748 ( .A0(intDY_EWSW[15]), .A1(n2378), .B0(intDY_EWSW[14]), .Y(
n2051) );
OAI2BB2XLTS U2749 ( .B0(intDX_EWSW[14]), .B1(n2051), .A0N(intDY_EWSW[15]),
.A1N(n2378), .Y(n2052) );
AOI211X1TS U2750 ( .A0(n2055), .A1(n2054), .B0(n2053), .C0(n2052), .Y(n2056)
);
OAI31X1TS U2751 ( .A0(n2059), .A1(n2058), .A2(n2057), .B0(n2056), .Y(n2061)
);
NOR2X1TS U2752 ( .A(n2163), .B(intDY_EWSW[17]), .Y(n2063) );
NAND3BXLTS U2753 ( .AN(n2068), .B(n2061), .C(n2060), .Y(n2082) );
OAI21XLTS U2754 ( .A0(intDY_EWSW[21]), .A1(n889), .B0(intDY_EWSW[20]), .Y(
n2062) );
NOR2XLTS U2755 ( .A(n2063), .B(intDX_EWSW[16]), .Y(n2064) );
AOI22X1TS U2756 ( .A0(n2064), .A1(intDY_EWSW[16]), .B0(intDY_EWSW[17]), .B1(
n2163), .Y(n2067) );
AOI32X1TS U2757 ( .A0(n2172), .A1(n2065), .A2(intDY_EWSW[18]), .B0(
intDY_EWSW[19]), .B1(n2271), .Y(n2066) );
OAI21XLTS U2758 ( .A0(n872), .A1(n2070), .B0(intDY_EWSW[22]), .Y(n2071) );
OAI2BB2XLTS U2759 ( .B0(intDX_EWSW[22]), .B1(n2071), .A0N(n872), .A1N(n2070),
.Y(n2072) );
AOI211X1TS U2760 ( .A0(n2075), .A1(n2074), .B0(n2073), .C0(n2072), .Y(n2081)
);
NOR2BX1TS U2761 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n2077) );
OR4X2TS U2762 ( .A(n2079), .B(n2078), .C(n2077), .D(n2076), .Y(n2080) );
AOI32X1TS U2763 ( .A0(n2083), .A1(n2082), .A2(n2081), .B0(n2080), .B1(n2083),
.Y(n2155) );
NOR2XLTS U2764 ( .A(n2084), .B(intDX_EWSW[56]), .Y(n2085) );
AOI22X1TS U2765 ( .A0(intDY_EWSW[57]), .A1(n2398), .B0(intDY_EWSW[56]), .B1(
n2085), .Y(n2089) );
OA21XLTS U2766 ( .A0(n2089), .A1(n2088), .B0(n2087), .Y(n2095) );
NAND2BXLTS U2767 ( .AN(intDX_EWSW[62]), .B(intDY_EWSW[62]), .Y(n2092) );
NAND3XLTS U2768 ( .A(n2413), .B(n2090), .C(intDY_EWSW[60]), .Y(n2091) );
OAI211XLTS U2769 ( .A0(intDX_EWSW[61]), .A1(n2337), .B0(n2092), .C0(n2091),
.Y(n2093) );
OAI2BB2XLTS U2770 ( .B0(n2096), .B1(n2095), .A0N(n2094), .A1N(n2093), .Y(
n2154) );
NOR2BX1TS U2771 ( .AN(n2097), .B(intDX_EWSW[46]), .Y(n2112) );
AOI22X1TS U2772 ( .A0(intDY_EWSW[45]), .A1(n2397), .B0(intDY_EWSW[44]), .B1(
n2099), .Y(n2109) );
OAI21XLTS U2773 ( .A0(intDY_EWSW[41]), .A1(n891), .B0(intDY_EWSW[40]), .Y(
n2100) );
OAI21XLTS U2774 ( .A0(intDY_EWSW[43]), .A1(n2101), .B0(intDY_EWSW[42]), .Y(
n2102) );
OAI2BB2XLTS U2775 ( .B0(intDX_EWSW[42]), .B1(n2102), .A0N(intDY_EWSW[43]),
.A1N(n2101), .Y(n2103) );
AOI32X1TS U2776 ( .A0(n2106), .A1(n2105), .A2(n2104), .B0(n2103), .B1(n2106),
.Y(n2107) );
OAI21XLTS U2777 ( .A0(n2109), .A1(n2108), .B0(n2107), .Y(n2111) );
NOR2BX1TS U2778 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2110) );
AOI211XLTS U2779 ( .A0(intDY_EWSW[46]), .A1(n2112), .B0(n2111), .C0(n2110),
.Y(n2151) );
NAND3XLTS U2780 ( .A(n2114), .B(n2113), .C(intDY_EWSW[36]), .Y(n2115) );
OAI21XLTS U2781 ( .A0(intDX_EWSW[37]), .A1(n2476), .B0(n2115), .Y(n2124) );
INVX2TS U2782 ( .A(n2116), .Y(n2122) );
OAI21XLTS U2783 ( .A0(intDY_EWSW[33]), .A1(n2396), .B0(intDY_EWSW[32]), .Y(
n2117) );
OAI2BB2XLTS U2784 ( .B0(intDX_EWSW[32]), .B1(n2117), .A0N(intDY_EWSW[33]),
.A1N(n2396), .Y(n2121) );
OAI2BB2XLTS U2785 ( .B0(intDX_EWSW[34]), .B1(n2118), .A0N(intDY_EWSW[35]),
.A1N(n2381), .Y(n2119) );
AOI32X1TS U2786 ( .A0(n2122), .A1(n2121), .A2(n2120), .B0(n2119), .B1(n2122),
.Y(n2123) );
OAI2BB1X1TS U2787 ( .A0N(n2125), .A1N(n2124), .B0(n2123), .Y(n2130) );
NOR2BX1TS U2788 ( .AN(intDY_EWSW[39]), .B(intDX_EWSW[39]), .Y(n2129) );
NOR3X1TS U2789 ( .A(n2477), .B(n2126), .C(intDX_EWSW[38]), .Y(n2128) );
INVX2TS U2790 ( .A(n2152), .Y(n2127) );
OAI31X1TS U2791 ( .A0(n2130), .A1(n2129), .A2(n2128), .B0(n2127), .Y(n2149)
);
OAI21XLTS U2792 ( .A0(intDY_EWSW[53]), .A1(n2392), .B0(intDY_EWSW[52]), .Y(
n2131) );
AOI2BB2XLTS U2793 ( .B0(intDY_EWSW[53]), .B1(n2392), .A0N(intDX_EWSW[52]),
.A1N(n2131), .Y(n2133) );
NOR2XLTS U2794 ( .A(n2133), .B(n2132), .Y(n2147) );
INVX2TS U2795 ( .A(n2134), .Y(n2140) );
AOI22X1TS U2796 ( .A0(intDY_EWSW[49]), .A1(n2391), .B0(intDY_EWSW[48]), .B1(
n2136), .Y(n2139) );
AOI32X1TS U2797 ( .A0(n2168), .A1(n2137), .A2(intDY_EWSW[50]), .B0(
intDY_EWSW[51]), .B1(n2394), .Y(n2138) );
OAI32X1TS U2798 ( .A0(n2141), .A1(n2140), .A2(n2139), .B0(n2138), .B1(n2140),
.Y(n2146) );
OAI2BB2XLTS U2799 ( .B0(intDX_EWSW[54]), .B1(n2143), .A0N(intDY_EWSW[55]),
.A1N(n2142), .Y(n2145) );
OAI31X1TS U2800 ( .A0(n2147), .A1(n2146), .A2(n2145), .B0(n2144), .Y(n2148)
);
OAI221XLTS U2801 ( .A0(n2152), .A1(n2151), .B0(n2150), .B1(n2149), .C0(n2148), .Y(n2153) );
AOI211X1TS U2802 ( .A0(n2156), .A1(n2155), .B0(n2154), .C0(n2153), .Y(n2157)
);
BUFX3TS U2803 ( .A(n2162), .Y(n2167) );
AOI21X1TS U2804 ( .A0(n2158), .A1(n2167), .B0(intDX_EWSW[63]), .Y(n2159) );
AOI21X1TS U2805 ( .A0(n2535), .A1(n2173), .B0(n2159), .Y(SIGN_FLAG_INIT) );
AOI2BB1XLTS U2806 ( .A0N(n2484), .A1N(SIGN_FLAG_SHT1SHT2), .B0(
array_comparators_GTComparator_N0), .Y(formatted_number_W[63]) );
NAND2X1TS U2807 ( .A(N94), .B(n1768), .Y(n2160) );
XNOR2X1TS U2808 ( .A(n2160), .B(N95), .Y(Raw_mant_SGF[1]) );
BUFX3TS U2809 ( .A(n2162), .Y(n2164) );
AOI22X1TS U2810 ( .A0(n2161), .A1(n2479), .B0(n2263), .B1(n2164), .Y(
DmP_INIT_EWSW[0]) );
AOI22X1TS U2811 ( .A0(n2161), .A1(n2478), .B0(n2369), .B1(n2166), .Y(
DmP_INIT_EWSW[1]) );
AOI22X1TS U2812 ( .A0(n2161), .A1(n2461), .B0(n2257), .B1(n2173), .Y(
DmP_INIT_EWSW[2]) );
AOI22X1TS U2813 ( .A0(n2161), .A1(n2425), .B0(n2377), .B1(n2173), .Y(
DmP_INIT_EWSW[3]) );
BUFX3TS U2814 ( .A(n2162), .Y(n2177) );
AOI22X1TS U2815 ( .A0(n2161), .A1(n2274), .B0(n2370), .B1(n2177), .Y(
DmP_INIT_EWSW[4]) );
AOI22X1TS U2816 ( .A0(n2161), .A1(n879), .B0(n2364), .B1(n2166), .Y(
DmP_INIT_EWSW[5]) );
AOI22X1TS U2817 ( .A0(n2161), .A1(n2275), .B0(n2371), .B1(n2166), .Y(
DmP_INIT_EWSW[6]) );
AOI22X1TS U2818 ( .A0(n2161), .A1(n878), .B0(n2252), .B1(n2176), .Y(
DmP_INIT_EWSW[7]) );
AOI22X1TS U2819 ( .A0(n2161), .A1(n2450), .B0(n2395), .B1(n2164), .Y(
DmP_INIT_EWSW[8]) );
AOI22X1TS U2820 ( .A0(n2161), .A1(n2463), .B0(n2266), .B1(n2164), .Y(
DmP_INIT_EWSW[9]) );
AOI22X1TS U2821 ( .A0(n2161), .A1(n2465), .B0(n2399), .B1(n2164), .Y(
DmP_INIT_EWSW[10]) );
AOI22X1TS U2822 ( .A0(n2161), .A1(n2448), .B0(n2390), .B1(n2164), .Y(
DmP_INIT_EWSW[11]) );
AOI22X1TS U2823 ( .A0(n2161), .A1(n2439), .B0(n2372), .B1(n2164), .Y(
DmP_INIT_EWSW[12]) );
AOI22X1TS U2824 ( .A0(n2170), .A1(n2434), .B0(n888), .B1(n2164), .Y(
DmP_INIT_EWSW[13]) );
AOI22X1TS U2825 ( .A0(n2170), .A1(n2456), .B0(n880), .B1(n2164), .Y(
DmP_INIT_EWSW[14]) );
AOI22X1TS U2826 ( .A0(n2170), .A1(n2429), .B0(n2378), .B1(n2164), .Y(
DmP_INIT_EWSW[15]) );
AOI22X1TS U2827 ( .A0(n2170), .A1(n2445), .B0(n2383), .B1(n2164), .Y(
DmP_INIT_EWSW[16]) );
AOI22X1TS U2828 ( .A0(n2170), .A1(n2446), .B0(n2163), .B1(n2164), .Y(
DmP_INIT_EWSW[17]) );
AOI22X1TS U2829 ( .A0(n2170), .A1(n2475), .B0(n2172), .B1(n2166), .Y(
DmP_INIT_EWSW[18]) );
AOI22X1TS U2830 ( .A0(n2170), .A1(n2480), .B0(n2271), .B1(n2164), .Y(
DmP_INIT_EWSW[19]) );
AOI22X1TS U2831 ( .A0(n2170), .A1(n2440), .B0(n2373), .B1(n2173), .Y(
DmP_INIT_EWSW[20]) );
AOI22X1TS U2832 ( .A0(n2170), .A1(n2435), .B0(n889), .B1(n2173), .Y(
DmP_INIT_EWSW[21]) );
AOI22X1TS U2833 ( .A0(n2170), .A1(n2457), .B0(n875), .B1(n2166), .Y(
DmP_INIT_EWSW[22]) );
AOI22X1TS U2834 ( .A0(n2170), .A1(n2433), .B0(n2255), .B1(n2173), .Y(
DmP_INIT_EWSW[23]) );
AOI22X1TS U2835 ( .A0(n2170), .A1(n2447), .B0(n2259), .B1(n2173), .Y(
DmP_INIT_EWSW[24]) );
AOI22X1TS U2836 ( .A0(n2170), .A1(n2444), .B0(n2379), .B1(n2166), .Y(
DmP_INIT_EWSW[25]) );
AOI22X1TS U2837 ( .A0(n2169), .A1(n2443), .B0(n2165), .B1(n2173), .Y(
DmP_INIT_EWSW[26]) );
AOI22X1TS U2838 ( .A0(n2169), .A1(n2455), .B0(n881), .B1(n2166), .Y(
DmP_INIT_EWSW[27]) );
AOI22X1TS U2839 ( .A0(n2169), .A1(n2441), .B0(n2375), .B1(n2173), .Y(
DmP_INIT_EWSW[28]) );
AOI22X1TS U2840 ( .A0(n2169), .A1(n2436), .B0(n890), .B1(n2167), .Y(
DmP_INIT_EWSW[29]) );
AOI22X1TS U2841 ( .A0(n2169), .A1(n2458), .B0(n876), .B1(n2167), .Y(
DmP_INIT_EWSW[30]) );
AOI22X1TS U2842 ( .A0(n2169), .A1(n2430), .B0(n2380), .B1(n2167), .Y(
DmP_INIT_EWSW[31]) );
AOI22X1TS U2843 ( .A0(n2169), .A1(n2469), .B0(n2268), .B1(n2167), .Y(
DmP_INIT_EWSW[32]) );
AOI22X1TS U2844 ( .A0(n2169), .A1(n2428), .B0(n2396), .B1(n2167), .Y(
DmP_INIT_EWSW[33]) );
AOI22X1TS U2845 ( .A0(n2169), .A1(n2459), .B0(n877), .B1(n2167), .Y(
DmP_INIT_EWSW[34]) );
AOI22X1TS U2846 ( .A0(n2169), .A1(n2431), .B0(n2381), .B1(n2167), .Y(
DmP_INIT_EWSW[35]) );
AOI22X1TS U2847 ( .A0(n2169), .A1(n2442), .B0(n2368), .B1(n2167), .Y(
DmP_INIT_EWSW[36]) );
AOI22X1TS U2848 ( .A0(n2169), .A1(n2476), .B0(n2387), .B1(n2167), .Y(
DmP_INIT_EWSW[37]) );
AOI22X1TS U2849 ( .A0(n2169), .A1(n2477), .B0(n2388), .B1(n2167), .Y(
DmP_INIT_EWSW[38]) );
AOI22X1TS U2850 ( .A0(n2170), .A1(n2405), .B0(n2272), .B1(n2164), .Y(
DmP_INIT_EWSW[39]) );
AOI22X1TS U2851 ( .A0(n2169), .A1(n2462), .B0(n2262), .B1(n2175), .Y(
DmP_INIT_EWSW[40]) );
AOI22X1TS U2852 ( .A0(n2170), .A1(n2437), .B0(n891), .B1(n2175), .Y(
DmP_INIT_EWSW[41]) );
AOI22X1TS U2853 ( .A0(n2169), .A1(n2452), .B0(n874), .B1(n2173), .Y(
DmP_INIT_EWSW[42]) );
AOI22X1TS U2854 ( .A0(n2170), .A1(n2432), .B0(n2264), .B1(n2173), .Y(
DmP_INIT_EWSW[43]) );
AOI22X1TS U2855 ( .A0(n2169), .A1(n2464), .B0(n2393), .B1(n2175), .Y(
DmP_INIT_EWSW[44]) );
AOI22X1TS U2856 ( .A0(n2170), .A1(n2453), .B0(n2397), .B1(n2167), .Y(
DmP_INIT_EWSW[45]) );
AOI22X1TS U2857 ( .A0(n2169), .A1(n2471), .B0(n2403), .B1(n2173), .Y(
DmP_INIT_EWSW[46]) );
AOI22X1TS U2858 ( .A0(n2170), .A1(n2481), .B0(n2270), .B1(n2166), .Y(
DmP_INIT_EWSW[47]) );
AOI22X1TS U2859 ( .A0(n2169), .A1(n2466), .B0(n2400), .B1(n2173), .Y(
DmP_INIT_EWSW[48]) );
AOI22X1TS U2860 ( .A0(n2170), .A1(n2449), .B0(n2391), .B1(n2175), .Y(
DmP_INIT_EWSW[49]) );
AOI22X1TS U2861 ( .A0(n2169), .A1(n2438), .B0(n2168), .B1(n2162), .Y(
DmP_INIT_EWSW[50]) );
AOI22X1TS U2862 ( .A0(n2169), .A1(n2468), .B0(n2394), .B1(n2166), .Y(
DmP_INIT_EWSW[51]) );
AOI22X1TS U2863 ( .A0(n2178), .A1(n2467), .B0(n2401), .B1(n2176), .Y(
DmP_INIT_EWSW[52]) );
AOI22X1TS U2864 ( .A0(n2170), .A1(n2426), .B0(n2392), .B1(n2166), .Y(
DmP_INIT_EWSW[53]) );
AOI22X1TS U2865 ( .A0(n2179), .A1(n2451), .B0(n2402), .B1(n2162), .Y(
DmP_INIT_EWSW[54]) );
AOI22X1TS U2866 ( .A0(n2161), .A1(n2427), .B0(n2267), .B1(n2162), .Y(
DmP_INIT_EWSW[55]) );
AOI22X1TS U2867 ( .A0(n2174), .A1(n2460), .B0(n2269), .B1(n2177), .Y(
DmP_INIT_EWSW[56]) );
AOI22X1TS U2868 ( .A0(n2161), .A1(n2454), .B0(n2398), .B1(n2175), .Y(
DmP_INIT_EWSW[57]) );
AOI22X1TS U2869 ( .A0(n2161), .A1(n2263), .B0(n2479), .B1(n2177), .Y(
DMP_INIT_EWSW[0]) );
AOI22X1TS U2870 ( .A0(n2174), .A1(n2369), .B0(n2478), .B1(n2177), .Y(
DMP_INIT_EWSW[1]) );
AOI22X1TS U2871 ( .A0(n2169), .A1(n2257), .B0(n2461), .B1(n2177), .Y(
DMP_INIT_EWSW[2]) );
AOI22X1TS U2872 ( .A0(n2170), .A1(n2377), .B0(n2425), .B1(n2177), .Y(
DMP_INIT_EWSW[3]) );
AOI22X1TS U2873 ( .A0(n2171), .A1(n2370), .B0(n2274), .B1(n2177), .Y(
DMP_INIT_EWSW[4]) );
AOI22X1TS U2874 ( .A0(n2174), .A1(n2364), .B0(n879), .B1(n2177), .Y(
DMP_INIT_EWSW[5]) );
AOI22X1TS U2875 ( .A0(n2174), .A1(n2371), .B0(n2275), .B1(n2177), .Y(
DMP_INIT_EWSW[6]) );
AOI22X1TS U2876 ( .A0(n2174), .A1(n2252), .B0(n878), .B1(n2177), .Y(
DMP_INIT_EWSW[7]) );
AOI22X1TS U2877 ( .A0(n2171), .A1(n2395), .B0(n2450), .B1(n2177), .Y(
DMP_INIT_EWSW[8]) );
AOI22X1TS U2878 ( .A0(n2174), .A1(n2266), .B0(n2463), .B1(n2177), .Y(
DMP_INIT_EWSW[9]) );
AOI22X1TS U2879 ( .A0(n2171), .A1(n2399), .B0(n2465), .B1(n2166), .Y(
DMP_INIT_EWSW[10]) );
AOI22X1TS U2880 ( .A0(n2174), .A1(n2390), .B0(n2448), .B1(n2173), .Y(
DMP_INIT_EWSW[11]) );
AOI22X1TS U2881 ( .A0(n2174), .A1(n2372), .B0(n2439), .B1(n2166), .Y(
DMP_INIT_EWSW[12]) );
AOI22X1TS U2882 ( .A0(n2171), .A1(n888), .B0(n2434), .B1(n2173), .Y(
DMP_INIT_EWSW[13]) );
AOI22X1TS U2883 ( .A0(n2174), .A1(n880), .B0(n2456), .B1(n2166), .Y(
DMP_INIT_EWSW[14]) );
AOI22X1TS U2884 ( .A0(n2174), .A1(n2378), .B0(n2429), .B1(n2173), .Y(
DMP_INIT_EWSW[15]) );
AOI22X1TS U2885 ( .A0(n2171), .A1(n2383), .B0(n2445), .B1(n2173), .Y(
DMP_INIT_EWSW[16]) );
AOI22X1TS U2886 ( .A0(n2174), .A1(n2367), .B0(n2446), .B1(n2166), .Y(
DMP_INIT_EWSW[17]) );
AOI22X1TS U2887 ( .A0(n2174), .A1(n2172), .B0(n2475), .B1(n2173), .Y(
DMP_INIT_EWSW[18]) );
AOI22X1TS U2888 ( .A0(n2171), .A1(n2271), .B0(n2480), .B1(n2166), .Y(
DMP_INIT_EWSW[19]) );
AOI22X1TS U2889 ( .A0(n2174), .A1(n2373), .B0(n2440), .B1(n2173), .Y(
DMP_INIT_EWSW[20]) );
AOI22X1TS U2890 ( .A0(n2174), .A1(n889), .B0(n2435), .B1(n2173), .Y(
DMP_INIT_EWSW[21]) );
AOI22X1TS U2891 ( .A0(n2174), .A1(n875), .B0(n2457), .B1(n2166), .Y(
DMP_INIT_EWSW[22]) );
AOI22X1TS U2892 ( .A0(n2174), .A1(n2255), .B0(n2433), .B1(n2173), .Y(
DMP_INIT_EWSW[23]) );
AOI22X1TS U2893 ( .A0(n2174), .A1(n2259), .B0(n2447), .B1(n2166), .Y(
DMP_INIT_EWSW[24]) );
AOI22X1TS U2894 ( .A0(n2171), .A1(n2379), .B0(n2444), .B1(n2166), .Y(
DMP_INIT_EWSW[25]) );
AOI22X1TS U2895 ( .A0(n2174), .A1(n2256), .B0(n2443), .B1(n2173), .Y(
DMP_INIT_EWSW[26]) );
AOI22X1TS U2896 ( .A0(n2174), .A1(n881), .B0(n2455), .B1(n2173), .Y(
DMP_INIT_EWSW[27]) );
AOI22X1TS U2897 ( .A0(n2171), .A1(n2375), .B0(n2441), .B1(n2173), .Y(
DMP_INIT_EWSW[28]) );
AOI22X1TS U2898 ( .A0(n2171), .A1(n890), .B0(n2436), .B1(n2173), .Y(
DMP_INIT_EWSW[29]) );
AOI22X1TS U2899 ( .A0(n2174), .A1(n876), .B0(n2458), .B1(n2175), .Y(
DMP_INIT_EWSW[30]) );
AOI22X1TS U2900 ( .A0(n2174), .A1(n2380), .B0(n2430), .B1(n2175), .Y(
DMP_INIT_EWSW[31]) );
AOI22X1TS U2901 ( .A0(n2171), .A1(n2268), .B0(n2469), .B1(n2175), .Y(
DMP_INIT_EWSW[32]) );
INVX4TS U2902 ( .A(n2175), .Y(n2179) );
AOI22X1TS U2903 ( .A0(n2179), .A1(n2396), .B0(n2428), .B1(n2175), .Y(
DMP_INIT_EWSW[33]) );
AOI22X1TS U2904 ( .A0(n2179), .A1(n877), .B0(n2459), .B1(n2175), .Y(
DMP_INIT_EWSW[34]) );
AOI22X1TS U2905 ( .A0(n2179), .A1(n2381), .B0(n2431), .B1(n2175), .Y(
DMP_INIT_EWSW[35]) );
AOI22X1TS U2906 ( .A0(n2179), .A1(n2368), .B0(n2442), .B1(n2175), .Y(
DMP_INIT_EWSW[36]) );
AOI22X1TS U2907 ( .A0(n2179), .A1(n2387), .B0(n2476), .B1(n2175), .Y(
DMP_INIT_EWSW[37]) );
AOI22X1TS U2908 ( .A0(n2179), .A1(n2388), .B0(n2477), .B1(n2175), .Y(
DMP_INIT_EWSW[38]) );
AOI22X1TS U2909 ( .A0(n2179), .A1(n2272), .B0(n2405), .B1(n2175), .Y(
DMP_INIT_EWSW[39]) );
AOI22X1TS U2910 ( .A0(n2179), .A1(n2262), .B0(n2462), .B1(n2175), .Y(
DMP_INIT_EWSW[40]) );
AOI22X1TS U2911 ( .A0(n2179), .A1(n891), .B0(n2437), .B1(n2162), .Y(
DMP_INIT_EWSW[41]) );
AOI22X1TS U2912 ( .A0(n2179), .A1(n874), .B0(n2452), .B1(n2162), .Y(
DMP_INIT_EWSW[42]) );
AOI22X1TS U2913 ( .A0(n2179), .A1(n2264), .B0(n2432), .B1(n2162), .Y(
DMP_INIT_EWSW[43]) );
AOI22X1TS U2914 ( .A0(n2179), .A1(n2393), .B0(n2464), .B1(n2162), .Y(
DMP_INIT_EWSW[44]) );
AOI22X1TS U2915 ( .A0(n2179), .A1(n2397), .B0(n2453), .B1(n2162), .Y(
DMP_INIT_EWSW[45]) );
INVX4TS U2916 ( .A(n2175), .Y(n2178) );
AOI22X1TS U2917 ( .A0(n2178), .A1(n2403), .B0(n2471), .B1(n2176), .Y(
DMP_INIT_EWSW[46]) );
AOI22X1TS U2918 ( .A0(n2178), .A1(n2270), .B0(n2481), .B1(n2176), .Y(
DMP_INIT_EWSW[47]) );
AOI22X1TS U2919 ( .A0(n2178), .A1(n2400), .B0(n2466), .B1(n2162), .Y(
DMP_INIT_EWSW[48]) );
AOI22X1TS U2920 ( .A0(n2178), .A1(n2391), .B0(n2449), .B1(n2162), .Y(
DMP_INIT_EWSW[49]) );
AOI22X1TS U2921 ( .A0(n2178), .A1(n2265), .B0(n2438), .B1(n2162), .Y(
DMP_INIT_EWSW[50]) );
AOI22X1TS U2922 ( .A0(n2178), .A1(n2394), .B0(n2468), .B1(n2176), .Y(
DMP_INIT_EWSW[51]) );
AOI22X1TS U2923 ( .A0(n2178), .A1(n2401), .B0(n2467), .B1(n2176), .Y(
DMP_INIT_EWSW[52]) );
AOI22X1TS U2924 ( .A0(n2178), .A1(n2392), .B0(n2426), .B1(n2176), .Y(
DMP_INIT_EWSW[53]) );
AOI22X1TS U2925 ( .A0(n2178), .A1(n2402), .B0(n2451), .B1(n2176), .Y(
DMP_INIT_EWSW[54]) );
AOI22X1TS U2926 ( .A0(n2178), .A1(n2267), .B0(n2427), .B1(n2176), .Y(
DMP_INIT_EWSW[55]) );
AOI22X1TS U2927 ( .A0(n2178), .A1(n2269), .B0(n2460), .B1(n2176), .Y(
DMP_INIT_EWSW[56]) );
AOI22X1TS U2928 ( .A0(n2178), .A1(n2398), .B0(n2454), .B1(n2176), .Y(
DMP_INIT_EWSW[57]) );
AO22XLTS U2929 ( .A0(n2179), .A1(intDX_EWSW[61]), .B0(n2162), .B1(
intDY_EWSW[61]), .Y(DMP_INIT_EWSW[61]) );
OR2X1TS U2930 ( .A(intDY_EWSW[62]), .B(intDX_EWSW[62]), .Y(DMP_INIT_EWSW[62]) );
OAI22X1TS U2931 ( .A0(n2182), .A1(n2195), .B0(n2181), .B1(n2199), .Y(
Data_array_SWR[53]) );
OAI222X1TS U2932 ( .A0(n2189), .A1(n2182), .B0(n2195), .B1(n2181), .C0(n2199), .C1(n2180), .Y(Data_array_SWR[52]) );
AOI22X1TS U2933 ( .A0(Shift_reg_FLAGS_7[1]), .A1(n887), .B0(
DmP_mant_SHT1_SW[25]), .B1(n915), .Y(n2186) );
OAI222X1TS U2934 ( .A0(n2197), .A1(n2191), .B0(n835), .B1(n2190), .C0(n2189),
.C1(n2188), .Y(Data_array_SWR[26]) );
OAI222X1TS U2935 ( .A0(n2199), .A1(n2198), .B0(n2197), .B1(n2196), .C0(n2195), .C1(n2194), .Y(Data_array_SWR[24]) );
BUFX3TS U2936 ( .A(n2200), .Y(n2201) );
CLKAND2X2TS U2937 ( .A(n2201), .B(sftr_odat_SHT2_SWR[2]), .Y(
formatted_number_W[0]) );
CLKAND2X2TS U2938 ( .A(n2201), .B(sftr_odat_SHT2_SWR[3]), .Y(
formatted_number_W[1]) );
CLKAND2X2TS U2939 ( .A(n2201), .B(sftr_odat_SHT2_SWR[4]), .Y(
formatted_number_W[2]) );
CLKAND2X2TS U2940 ( .A(n2201), .B(sftr_odat_SHT2_SWR[5]), .Y(
formatted_number_W[3]) );
CLKAND2X2TS U2941 ( .A(n2201), .B(sftr_odat_SHT2_SWR[6]), .Y(
formatted_number_W[4]) );
CLKAND2X2TS U2942 ( .A(n2201), .B(sftr_odat_SHT2_SWR[7]), .Y(
formatted_number_W[5]) );
CLKAND2X2TS U2943 ( .A(n2201), .B(sftr_odat_SHT2_SWR[8]), .Y(
formatted_number_W[6]) );
CLKAND2X2TS U2944 ( .A(n2201), .B(sftr_odat_SHT2_SWR[9]), .Y(
formatted_number_W[7]) );
CLKAND2X2TS U2945 ( .A(n2201), .B(sftr_odat_SHT2_SWR[10]), .Y(
formatted_number_W[8]) );
CLKAND2X2TS U2946 ( .A(n2201), .B(sftr_odat_SHT2_SWR[11]), .Y(
formatted_number_W[9]) );
CLKAND2X2TS U2947 ( .A(n2201), .B(sftr_odat_SHT2_SWR[12]), .Y(
formatted_number_W[10]) );
CLKAND2X2TS U2948 ( .A(n2201), .B(sftr_odat_SHT2_SWR[13]), .Y(
formatted_number_W[11]) );
BUFX3TS U2949 ( .A(n2200), .Y(n2203) );
CLKAND2X2TS U2950 ( .A(n2203), .B(sftr_odat_SHT2_SWR[14]), .Y(
formatted_number_W[12]) );
CLKAND2X2TS U2951 ( .A(n2203), .B(sftr_odat_SHT2_SWR[15]), .Y(
formatted_number_W[13]) );
CLKAND2X2TS U2952 ( .A(n2203), .B(sftr_odat_SHT2_SWR[16]), .Y(
formatted_number_W[14]) );
CLKAND2X2TS U2953 ( .A(n2203), .B(sftr_odat_SHT2_SWR[17]), .Y(
formatted_number_W[15]) );
CLKAND2X2TS U2954 ( .A(n2203), .B(sftr_odat_SHT2_SWR[18]), .Y(
formatted_number_W[16]) );
CLKAND2X2TS U2955 ( .A(n2203), .B(sftr_odat_SHT2_SWR[19]), .Y(
formatted_number_W[17]) );
CLKAND2X2TS U2956 ( .A(n2203), .B(sftr_odat_SHT2_SWR[20]), .Y(
formatted_number_W[18]) );
CLKAND2X2TS U2957 ( .A(n2203), .B(sftr_odat_SHT2_SWR[21]), .Y(
formatted_number_W[19]) );
CLKAND2X2TS U2958 ( .A(n2203), .B(sftr_odat_SHT2_SWR[22]), .Y(
formatted_number_W[20]) );
CLKAND2X2TS U2959 ( .A(n2203), .B(sftr_odat_SHT2_SWR[23]), .Y(
formatted_number_W[21]) );
CLKAND2X2TS U2960 ( .A(n2203), .B(sftr_odat_SHT2_SWR[24]), .Y(
formatted_number_W[22]) );
CLKAND2X2TS U2961 ( .A(n2203), .B(sftr_odat_SHT2_SWR[25]), .Y(
formatted_number_W[23]) );
BUFX3TS U2962 ( .A(n2200), .Y(n2204) );
CLKAND2X2TS U2963 ( .A(n2204), .B(sftr_odat_SHT2_SWR[26]), .Y(
formatted_number_W[24]) );
CLKAND2X2TS U2964 ( .A(n2204), .B(sftr_odat_SHT2_SWR[27]), .Y(
formatted_number_W[25]) );
CLKAND2X2TS U2965 ( .A(n2204), .B(sftr_odat_SHT2_SWR[28]), .Y(
formatted_number_W[26]) );
CLKAND2X2TS U2966 ( .A(n2204), .B(sftr_odat_SHT2_SWR[29]), .Y(
formatted_number_W[27]) );
CLKAND2X2TS U2967 ( .A(n2204), .B(sftr_odat_SHT2_SWR[30]), .Y(
formatted_number_W[28]) );
CLKAND2X2TS U2968 ( .A(n2204), .B(sftr_odat_SHT2_SWR[31]), .Y(
formatted_number_W[29]) );
CLKAND2X2TS U2969 ( .A(n2204), .B(sftr_odat_SHT2_SWR[32]), .Y(
formatted_number_W[30]) );
CLKAND2X2TS U2970 ( .A(n2204), .B(sftr_odat_SHT2_SWR[33]), .Y(
formatted_number_W[31]) );
CLKAND2X2TS U2971 ( .A(n2204), .B(sftr_odat_SHT2_SWR[34]), .Y(
formatted_number_W[32]) );
CLKAND2X2TS U2972 ( .A(n2204), .B(sftr_odat_SHT2_SWR[35]), .Y(
formatted_number_W[33]) );
CLKAND2X2TS U2973 ( .A(n2204), .B(sftr_odat_SHT2_SWR[36]), .Y(
formatted_number_W[34]) );
CLKAND2X2TS U2974 ( .A(n2204), .B(sftr_odat_SHT2_SWR[37]), .Y(
formatted_number_W[35]) );
BUFX3TS U2975 ( .A(n2200), .Y(n2202) );
CLKAND2X2TS U2976 ( .A(n2202), .B(sftr_odat_SHT2_SWR[38]), .Y(
formatted_number_W[36]) );
CLKAND2X2TS U2977 ( .A(n2202), .B(sftr_odat_SHT2_SWR[39]), .Y(
formatted_number_W[37]) );
CLKAND2X2TS U2978 ( .A(n2202), .B(sftr_odat_SHT2_SWR[40]), .Y(
formatted_number_W[38]) );
CLKAND2X2TS U2979 ( .A(n2202), .B(sftr_odat_SHT2_SWR[41]), .Y(
formatted_number_W[39]) );
CLKAND2X2TS U2980 ( .A(n2202), .B(sftr_odat_SHT2_SWR[42]), .Y(
formatted_number_W[40]) );
CLKAND2X2TS U2981 ( .A(n2202), .B(sftr_odat_SHT2_SWR[43]), .Y(
formatted_number_W[41]) );
CLKAND2X2TS U2982 ( .A(n2202), .B(sftr_odat_SHT2_SWR[44]), .Y(
formatted_number_W[42]) );
CLKAND2X2TS U2983 ( .A(n2202), .B(sftr_odat_SHT2_SWR[45]), .Y(
formatted_number_W[43]) );
CLKAND2X2TS U2984 ( .A(n2202), .B(sftr_odat_SHT2_SWR[46]), .Y(
formatted_number_W[44]) );
CLKAND2X2TS U2985 ( .A(n2202), .B(sftr_odat_SHT2_SWR[47]), .Y(
formatted_number_W[45]) );
CLKAND2X2TS U2986 ( .A(n2202), .B(sftr_odat_SHT2_SWR[48]), .Y(
formatted_number_W[46]) );
CLKAND2X2TS U2987 ( .A(n2202), .B(sftr_odat_SHT2_SWR[49]), .Y(
formatted_number_W[47]) );
CLKAND2X2TS U2988 ( .A(n2201), .B(sftr_odat_SHT2_SWR[50]), .Y(
formatted_number_W[48]) );
CLKAND2X2TS U2989 ( .A(n2202), .B(sftr_odat_SHT2_SWR[51]), .Y(
formatted_number_W[49]) );
CLKAND2X2TS U2990 ( .A(n2203), .B(sftr_odat_SHT2_SWR[52]), .Y(
formatted_number_W[50]) );
CLKAND2X2TS U2991 ( .A(n2204), .B(sftr_odat_SHT2_SWR[53]), .Y(
formatted_number_W[51]) );
AO22XLTS U2992 ( .A0(n2221), .A1(LZD_raw_out_EWR[2]), .B0(
Shift_amount_SHT1_EWR[2]), .B1(n915), .Y(shft_value_mux_o_EWR[2]) );
INVX2TS U2993 ( .A(n2205), .Y(n2206) );
OAI31X1TS U2994 ( .A0(n2208), .A1(Raw_mant_NRM_SWR[47]), .A2(n2207), .B0(
n2206), .Y(n2209) );
OAI211XLTS U2995 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n2214), .B0(n2213), .C0(
n2212), .Y(n2215) );
AOI211XLTS U2996 ( .A0(n2217), .A1(n882), .B0(n2216), .C0(n2215), .Y(n2219)
);
AO22XLTS U2997 ( .A0(n2534), .A1(LZD_raw_out_EWR[3]), .B0(
Shift_amount_SHT1_EWR[3]), .B1(n915), .Y(shft_value_mux_o_EWR[3]) );
AO22XLTS U2998 ( .A0(n2221), .A1(LZD_raw_out_EWR[4]), .B0(
Shift_amount_SHT1_EWR[4]), .B1(n915), .Y(shft_value_mux_o_EWR[4]) );
AO22XLTS U2999 ( .A0(n2534), .A1(LZD_raw_out_EWR[5]), .B0(
Shift_amount_SHT1_EWR[5]), .B1(n915), .Y(shft_value_mux_o_EWR[5]) );
AOI22X1TS U3001 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n2470), .B0(
beg_OP), .B1(n873), .Y(n2223) );
OAI22X1TS U3002 ( .A0(n2224), .A1(n2223), .B0(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B1(n2222), .Y(n831) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
/*
* Usage notes:
*
* IRDY# control:
* Master inititated wait states (delay from FRAME# active to IRDY# active
* are controlled in a number of ways. The "header.v" defines PRDY1, PRDY2,
* PRDY3, and RAND set the default behavior. If none of these are defined,
* no waits are inserted by the rw_tasks. The globals "irdy_delay" and
* "irdy_random" can be used to control wait state behavior "on-the-fly".
* When irdy_random is non-zero, each PCI data phase uses the next entry
* in the irdy_pattern table to determine the number of wait states. When
* irdy_random is zero, the number of waits is determined by the global
* irdy_delay. The valid range for irdy_delay is 0-7 (three bits). irdy_delay
* and irdy_random may be set at any time during a simulation.
*/
`define WDTIMER 1000
`define MAXDEVSEL 8
`ifdef MAXRETRY
`else
`define MAXRETRY 200
`endif
`ifdef PCI64
`else
`define PCI64 0
`endif
`define MAX_PCI_BURST_COUNT 40
// We'll change MAX_PCI_BURST_COUNT to 64 once we're sure this works.
reg [35:0] pci_cmd_list [0:63];
reg [31:0] pci_burst_start_address;
reg [31:0] pci_burst_current_address;
integer pci_cmd_list_index;
reg rwtPAR, rwtPAR64;
reg rwtPARen, rwtPARen1, rwtPAR64en, rwtPAR64en1;
integer irdy_random;
reg [2:0] irdy_delay;
reg [1:0] irdy_pattern [0:127];
reg [6:0] irdy_pattern_index;
integer Tinval;
integer Tval;
initial begin
//PCI timing
Tinval = Thld;
Tval = hclk-Tsu;
`ifdef PRDY1
irdy_delay= 1;
`else
`ifdef PRDY2
irdy_delay= 2;
`else
`ifdef PRDY3
irdy_delay= 3;
`else
irdy_delay= 0;
`endif
`endif
`endif
`ifdef RAND
irdy_random = 1;
`else
irdy_random = 0;
`endif
irdy_pattern_index = 0;
irdy_pattern[0] = 2'h0;
irdy_pattern[1] = 2'h0;
irdy_pattern[2] = 2'h0;
irdy_pattern[3] = 2'h0;
irdy_pattern[4] = 2'h0;
irdy_pattern[5] = 2'h0;
irdy_pattern[6] = 2'h0;
irdy_pattern[7] = 2'h0;
irdy_pattern[8] = 2'h0;
irdy_pattern[9] = 2'h1;
irdy_pattern[10] = 2'h1;
irdy_pattern[11] = 2'h1;
irdy_pattern[12] = 2'h1;
irdy_pattern[13] = 2'h1;
irdy_pattern[14] = 2'h1;
irdy_pattern[15] = 2'h1;
irdy_pattern[16] = 2'h1;
irdy_pattern[17] = 2'h1;
irdy_pattern[18] = 2'h2;
irdy_pattern[19] = 2'h2;
irdy_pattern[20] = 2'h2;
irdy_pattern[21] = 2'h2;
irdy_pattern[22] = 2'h2;
irdy_pattern[23] = 2'h3;
irdy_pattern[24] = 2'h3;
irdy_pattern[25] = 2'h3;
irdy_pattern[26] = 2'h3;
irdy_pattern[27] = 2'h3;
irdy_pattern[28] = 2'h0;
irdy_pattern[29] = 2'h0;
irdy_pattern[30] = 2'h1;
irdy_pattern[31] = 2'h1;
irdy_pattern[32] = 2'h2;
irdy_pattern[33] = 2'h2;
irdy_pattern[34] = 2'h3;
irdy_pattern[35] = 2'h3;
irdy_pattern[36] = 2'h2;
irdy_pattern[37] = 2'h1;
irdy_pattern[38] = 2'h0;
irdy_pattern[39] = 2'h1;
irdy_pattern[40] = 2'h0;
irdy_pattern[41] = 2'h1;
irdy_pattern[42] = 2'h0;
irdy_pattern[43] = 2'h1;
irdy_pattern[44] = 2'h0;
irdy_pattern[45] = 2'h1;
irdy_pattern[46] = 2'h0;
irdy_pattern[47] = 2'h1;
irdy_pattern[48] = 2'h0;
irdy_pattern[49] = 2'h2;
irdy_pattern[50] = 2'h0;
irdy_pattern[51] = 2'h2;
irdy_pattern[52] = 2'h0;
irdy_pattern[53] = 2'h2;
irdy_pattern[54] = 2'h0;
irdy_pattern[55] = 2'h3;
irdy_pattern[56] = 2'h0;
irdy_pattern[57] = 2'h2;
irdy_pattern[58] = 2'h0;
irdy_pattern[59] = 2'h1;
irdy_pattern[60] = 2'h2;
irdy_pattern[61] = 2'h1;
irdy_pattern[62] = 2'h2;
irdy_pattern[63] = 2'h1;
irdy_pattern[64] = 2'h2;
irdy_pattern[65] = 2'h3;
irdy_pattern[66] = 2'h1;
irdy_pattern[67] = 2'h2;
irdy_pattern[68] = 2'h3;
irdy_pattern[69] = 2'h1;
irdy_pattern[70] = 2'h2;
irdy_pattern[71] = 2'h3;
irdy_pattern[72] = 2'h1;
irdy_pattern[73] = 2'h2;
irdy_pattern[74] = 2'h3;
irdy_pattern[75] = 2'h0;
irdy_pattern[76] = 2'h1;
irdy_pattern[77] = 2'h0;
irdy_pattern[78] = 2'h2;
irdy_pattern[79] = 2'h0;
irdy_pattern[80] = 2'h3;
irdy_pattern[81] = 2'h0;
irdy_pattern[82] = 2'h0;
irdy_pattern[83] = 2'h0;
irdy_pattern[84] = 2'h0;
irdy_pattern[85] = 2'h1;
irdy_pattern[86] = 2'h1;
irdy_pattern[87] = 2'h1;
irdy_pattern[88] = 2'h0;
irdy_pattern[89] = 2'h2;
irdy_pattern[90] = 2'h2;
irdy_pattern[91] = 2'h0;
irdy_pattern[92] = 2'h0;
irdy_pattern[93] = 2'h0;
irdy_pattern[94] = 2'h3;
irdy_pattern[95] = 2'h1;
irdy_pattern[96] = 2'h0;
irdy_pattern[97] = 2'h0;
irdy_pattern[98] = 2'h2;
irdy_pattern[99] = 2'h0;
irdy_pattern[100] = 2'h0;
irdy_pattern[101] = 2'h0;
irdy_pattern[102] = 2'h0;
irdy_pattern[103] = 2'h0;
irdy_pattern[104] = 2'h1;
irdy_pattern[105] = 2'h1;
irdy_pattern[106] = 2'h1;
irdy_pattern[107] = 2'h0;
irdy_pattern[108] = 2'h1;
irdy_pattern[109] = 2'h0;
irdy_pattern[110] = 2'h0;
irdy_pattern[111] = 2'h0;
irdy_pattern[112] = 2'h3;
irdy_pattern[113] = 2'h3;
irdy_pattern[114] = 2'h0;
irdy_pattern[115] = 2'h0;
irdy_pattern[116] = 2'h3;
irdy_pattern[117] = 2'h0;
irdy_pattern[118] = 2'h2;
irdy_pattern[119] = 2'h1;
irdy_pattern[120] = 2'h1;
irdy_pattern[121] = 2'h0;
irdy_pattern[122] = 2'h0;
irdy_pattern[123] = 2'h0;
irdy_pattern[124] = 2'h0;
irdy_pattern[125] = 2'h1;
irdy_pattern[126] = 2'h2;
irdy_pattern[127] = 2'h1;
end // initial begin
/*
* pci_write(host_cycle_type, address, count, mode):
*
* Low level PCI write task. This task is called by mov_dw and mov_burst,
* which act as wrappers around this task. The global memory, pci_cmd_list,
* is used to pass the data to be written to this task.
* This task is now also called by pci_burst_end.
*/
task pci_write;
input [3:0] host_cycle_type; // config, io, or mem write
input [31:0] address; // first address of transaction
input [29:0] count; // burst size
input [1:0] mode; // 0=inc, 1=burst, 2=fbtb ,3=res
integer trans_count;
integer devsel_count;
integer trdy_count;
integer irdy_count;
integer burst_count;
integer data_phase_done;
integer terminated;
integer fbtb;
integer trdy_timer;
integer initial_data_phase;
reg [8:0] retry_counter;
reg [35:0] tmp_pci_cmd;
reg [35:0] tmp_pci_cmd_1;
reg [7:0] tmp_be;
reg [63:0] tmp_data;
reg first_xfer;
reg disable_64;
begin
if (disable_64 != 1) disable_64 = 0;
case (mw0_size)
2'b00: mw0_mask = 11'h0;
2'b01: mw0_mask = 11'h1;
2'b10: mw0_mask = 11'h3;
2'b11: mw0_mask = 11'h7;
endcase
case (mw1_size)
2'b00: mw1_mask = 11'h0;
2'b01: mw1_mask = 11'h1;
2'b10: mw1_mask = 11'h3;
2'b11: mw1_mask = 11'h7;
endcase
case (aw_size)
0: aw_mask = 20'h1;
1: aw_mask = 20'h3;
2: aw_mask = 20'h7;
3: aw_mask = 20'hF;
4: aw_mask = 20'h1F;
5: aw_mask = 20'h3F;
6: aw_mask = 20'h7F;
7: aw_mask = 20'hFF;
8: aw_mask = 20'h1FF;
9: aw_mask = 20'h3FF;
10: aw_mask = 20'h7FF;
11: aw_mask = 20'hFFF;
default: aw_mask = 20'h1;
endcase // case(aw_size)
/*
* Make sure the command is a write command
*/
if (host_cycle_type[0] != 1) begin
$display("Error! task pci_write(%h,%h,%h)", host_cycle_type, address, count);
$display(" PCI test master received a read command in a write task");
$stop;
end // if (host_cycle_type[0] != 0)
/*
* Initialize some counters used for error checking
*/
retry_count = 0;
trans_count = 0;
fbtb = 0;
@(posedge HCLK);
/*
* Outermost loop handles retries and target aborts. Master loops here
* until all data is sent, or retry count is exceeded, or target abort.
*/
begin : retry_loop
while (trans_count < count) begin
/*
* wait for grant
*/
if (!GNT_RWTn) begin
if (fbtb) begin
// we still have the bus, so just continue
end // if (fbtb)
else
REQ_RWTn <= #Tval 0;
end
else begin
while (!(!GNT_RWTn && FRAMEn && PRDYn)) begin
REQ_RWTn <= #Tval 0;
framee_n <= #Tval 'bz;
req64_n <= #Tval 'bz;
hb_ad_bus <= #Tval 64'bz;
byte_ens <= #Tval 'bz;
rwtPARen <= #Tval 0;
rwtPAR64en <= #Tval 0;
@(posedge HCLK);
prdyy_n <= #Tval 'bz;
end // while (!(!GNT_RWTn && FRAMEn && PRDYn))
end // else: !if(fbtb && !GNT_RWTn)
// We will do a 64 bit transfer on any memory transaction. However, the
// FPGA should not respond to all of these... We'll check that below.
// If we have have only 1 piece of data, or two pieces aligned to
// 64 bits, then we will unly request using 32 bit transactions. This
// saves us from frame issues in the testbench.
if (`PCI64 && ((mode != 0) && (host_cycle_type == MEM_RD ||
host_cycle_type == MEM_WR ||
host_cycle_type == MEM_RD_MULTI ||
host_cycle_type == MEM_RD_LINE ||
host_cycle_type == MEM_WR_INV) &&
~((count == 1) || (~address[2] && count == 2) ||
((trans_count == count - 1) ||
~address[2] && trans_count == count - 2))))
enable_64 = ~disable_64;
else
enable_64 = 1'b0;
disable_64 = 1'b0; // reset 64 bit disable
/*
* address phase. Drive address, command, IDSEL (if config cycle)
* and FRAME#. Negate REQ# if this is the last transaction.
* Drive AD16 as IDSEL, for AGP support.
*/
if (host_cycle_type==CONFIG_WR) begin
`ifdef PCIX
hb_ad_bus <= #Tinval 64'bx;
`endif
`ifdef PCIX
IDSEL <= #Tinval 'bx;
`endif
hb_ad_bus <= #Tval {32'b0, 16'h1, address[15:0]};
IDSEL <= #Tval 1;
end // if (host_cycle_type==CONFIG_WR)
else begin
`ifdef PCIX
hb_ad_bus <= #Tinval 64'bx;
`endif
if (~enable_64) hb_ad_bus <= #Tval {31'b0, address};
else hb_ad_bus <= #Tval {31'b0, address[31:3], 3'b0};
end // else: !if(host_cycle_type==CONFIG_WR)
`ifdef PCIX
byte_ens <= #Tinval 'bx;
`endif
byte_ens <= #Tval {4'hF, host_cycle_type};
rwtPARen <= #Tval 1;
rwtPAR64en <= #Tval 1;
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 0;
req64_n <= #Tval ~enable_64;
devsel_count = 0;
if (mode==2'h2) begin
if (trans_count == count-1)
REQ_RWTn <= #Tval 1;
end
else
REQ_RWTn <= #Tval 1;
/*
* data phases
*/
@ (posedge HCLK);
IDSEL <= #Tval 'bz;
initial_data_phase = 1;
burst_count = 0;
terminated = 0;
transmit_64 = enable_64; // First pass, make them equal
xfer_odd = 0;
retransmit = 0;
first_xfer = 1;
begin : burst_loop
while ((trans_count < count) && !terminated) begin
trdy_count = 0;
// The data that gets sent depends on the wrapper task that
// called this one.
case (mode)
2'h0: begin // mov_dw
tmp_pci_cmd = pci_cmd_list[0];
tmp_be = {4'hF, tmp_pci_cmd[35:32]};
//tmp_data = {32'b0, tmp_pci_cmd[31:0] + trans_count};
tmp_data = {32'b0, tmp_pci_cmd[31:0]};
inc_trans = 1;
last_xfer = (trans_count == count - 1);
end // case: 2'h0
2'h1: begin // mov_burst
tmp_pci_cmd = pci_cmd_list[trans_count];
tmp_pci_cmd_1 = pci_cmd_list[trans_count+1];
if (retransmit || ~enable_64 || ~transmit_64 || (trans_count == count - 1))
begin
tmp_be = {4'hF, tmp_pci_cmd[35:32]};
tmp_data = {32'h0, tmp_pci_cmd[31:0]};
inc_trans = 1;
last_xfer = (trans_count == count - 1);
retransmit = 0;
end else begin
if (address[2] && first_xfer) begin
// We started on an odd address.
tmp_be = {tmp_pci_cmd[35:32], 4'hF};
tmp_data = {tmp_pci_cmd[31:0], 32'hFEED_BEEF};
inc_trans = 1;
last_xfer = (trans_count == count - 1);
xfer_odd = 1;
end else begin
inc_trans = 2;
tmp_be = {tmp_pci_cmd_1[35:32], tmp_pci_cmd[35:32]};
tmp_data = {tmp_pci_cmd_1[31:0], tmp_pci_cmd[31:0]};
last_xfer = (trans_count == count - 2);
end
end
end // case: 2'h1
2'h2: begin //mov_fbtb
tmp_pci_cmd = pci_cmd_list[2*trans_count+1];
tmp_pci_cmd_1 = pci_cmd_list[trans_count+1];
if (retransmit || ~enable_64 || ~transmit_64 || (trans_count == count - 1))
begin
tmp_be = {4'hF, tmp_pci_cmd[35:32]};
tmp_data = {32'h0, tmp_pci_cmd[31:0]};
inc_trans = 1;
last_xfer = (trans_count == count - 1);
retransmit = 0;
end else begin
if (address[2] && first_xfer) begin
// We started on an odd address.
tmp_be = {tmp_pci_cmd[35:32], 4'hF};
tmp_data = {tmp_pci_cmd[31:0], 32'hFEED_BEEF};
inc_trans = 1;
last_xfer = (trans_count == count - 1);
xfer_odd = 1;
end else begin
inc_trans = 2;
tmp_be = {tmp_pci_cmd_1[35:32], tmp_pci_cmd[35:32]};
tmp_data = {tmp_pci_cmd_1[31:0], tmp_pci_cmd[31:0]};
last_xfer = (trans_count == count - 2);
end
end
fbtb = 1;
end // case: 2'h2
2'h3: begin // reserved
$display ("task pci_write: coding error, invalid mode");
$stop;
end // case: 2'h2,2'h3
endcase // case (mode)
`ifdef PCIX
byte_ens <= #Tinval 'bx;
`endif
byte_ens <= #Tval tmp_be;
rwtPARen <= #Tval 1;
// Loop here to handle delay in asserting IRDY#
if (irdy_random) begin
irdy_delay=irdy_pattern[irdy_pattern_index];
irdy_pattern_index = irdy_pattern_index + 1;
end // if (irdy_random)
for (irdy_count=0; irdy_count<irdy_delay; irdy_count = irdy_count + 1) begin
// negate IRDY# if it was already on (from a previous data phase)
if (!prdyy_n) begin
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
prdyy_n <= #Tval 1;
end // if (!prdyy_n)
`ifdef PCIX
hb_ad_bus <= #Tinval 64'bx;
`endif
@ (posedge HCLK);
if (DEVSELn!=0)
devsel_count = devsel_count + 1;
if (TRDYn!=0)
trdy_count = trdy_count + 1;
end // for (irdy_count=0; irdy_count<irdy_delay; irdy_count = irdy_count + 1)
// Assert IRDY# and drive data. Also, check if STOP# asserted.
// If so, negate FRAME# (Fig's 9-4,9-7,9-9 in "PCI System
// Architecture, Third Edition") FRAME# is also negated if
// this is the last piece of data in the transaction. Finally,
// if we are running in mode 2 (fbtb), FRAME# is negated
// because every transaction is single cycle.
if (PRDYn!='b0) begin
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
end // if (PRDYn!='b0)
prdyy_n <= #Tval 0;
`ifdef PCIX
hb_ad_bus <= #Tinval 64'bx;
`endif
hb_ad_bus <= #Tval tmp_data;
if (last_xfer || !STOPn || (mode==2)) begin
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tinval 'bx;
`endif
framee_n <= #Tval 1;
req64_n <= #Tval 1;
end // if ((trans_count == count-1) || !STOPn)
// Negate REQ# if this is the last transaction
if (trans_count >= count-1)
REQ_RWTn <= #Tval 1;
// Loop until target signals end of data phase, or until
// a time out is detected
data_phase_done = 0;
while (!data_phase_done) begin
@ (posedge HCLK);
// increment devsel and trdy watchdog timers
if (DEVSELn!=0)
devsel_count = devsel_count + 1;
if (TRDYn!=0)
trdy_count = trdy_count + 1;
if (TRDYn==0 && ~ACK64n) begin
//address[2] = 1'b0;
first_xfer = 1'b0;
end
// Normal end of data phase. Target accepted data
if (DEVSELn==0 && TRDYn==0 && STOPn==1) begin
if ((rwt_log != 0)&& rwt_write_log) $fdisplay (rwt_log, "PCI WRITE: address=%h data=%h",address, AD);
retry_count = 0;
data_phase_done=1;
// check if we are transfering 64 bits
if (~ACK64n) begin
transmit_64 = 1'b1;
retransmit = 0;
xfer_odd = 0;
if (~enable_64 ||
~((address[31:13] == rbase_a[31:13]) || // DE registers
((address[31:22] | mw0_mask) ==
(rbase_mw0[31:22] | mw0_mask)) || // Memory Windows 0
((address[31:22] | mw1_mask) ==
(rbase_mw1[31:22] | mw1_mask)) || // Memory Windows 1
((address[31:12] | aw_mask) ==
(address[31:12] | aw_mask)))) begin // DE cache
$display ("task pci_write: ACK64n recieved with no REQ64n");
$stop;
end
end else begin
transmit_64 = 1'b0;
if (xfer_odd) retransmit = 1;
xfer_odd = 0;
end
if (!retransmit) begin
trans_count = trans_count + (transmit_64 ? inc_trans : 1);
burst_count = burst_count + 1;
end
if (trans_count >= count) begin
framee_n <= #Tval 'bz;
req64_n <= #Tval 'bz;
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
prdyy_n <= #Tval 1;
`ifdef PCIX
hb_ad_bus <= #Tinval 64'hx;
`endif
hb_ad_bus <=#Tval 64'hz;
`ifdef PCIX
byte_ens <= #Tinval 8'hx;
`endif
byte_ens <= #Tval 8'hz;
prdyy_n <= #(hclk+Tval) 'bz;
rwtPARen <= #Tval 0;
end // if (trans_count == count)
else begin
if (mode==2) begin //fbtb
tmp_pci_cmd = pci_cmd_list[2*trans_count];
address = tmp_pci_cmd[31:0];
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
prdyy_n <= #Tval 1;
terminated = 1;
end // if (fbtb)
else
address = (transmit_64) ? address + (4 * inc_trans) :
address + 4;
end // else: !if(trans_count == count)
end // if (DEVSELn==0 && TRDYn==0 && STOPn==1)
// Retry or Disconnect w/o data
else if (DEVSELn==0 && TRDYn==1 && STOPn==0) begin
`ifdef RWTASK_DEBUG
if (burst_count == 0)
$display ("PCI RETRY (write) at address %h, time: %d",address, $time);
else
$display ("PCI DISCONNECT w/o data (write) at address %h, time: %d",address, $time);
`endif
// must stop requesting the bus
REQ_RWTn <= #Tval 1;
// ensure that FRAME# is negated before negating IRDY#,
// to properly terminate the transaction.
if (!framee_n) begin
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 1;
req64_n <= #Tval 1;
@ (posedge HCLK);
end // if (!framee_n)
retry_count = retry_count + 1;
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
prdyy_n <= #Tval 1;
`ifdef PCIX
hb_ad_bus <= #Tinval 64'hx;
`endif
hb_ad_bus <=#Tval 64'hz;
`ifdef PCIX
byte_ens <= #Tinval 8'hx;
`endif
byte_ens <= #Tval 8'hz;
framee_n <= #Tval 'bz;
req64_n <= #Tval 'bz;
prdyy_n <= #(hclk+Tval) 'bz;
data_phase_done = 1;
terminated = 1;
rwtPARen <= #Tval 0;
@ (posedge HCLK);
@ (posedge HCLK);
end // if (DEVSELn==0 && TRDYn==1 && STOPn==0)
// Disconnect with data
else if (DEVSELn==0 && TRDYn==0 && STOPn==0) begin
`ifdef RWTASK_DEBUG
$display ("PCI DISCONNECT with data (write) at address %h, time: %d",address, $time);
`endif
if ((rwt_log != 0)&& rwt_write_log) $fdisplay (rwt_log, "PCI WRITE: address=%h data=%h",address, AD);
//if (~xfer_odd & transmit_64) address[2] = 1'b0;
// stop requesting if not on last data phase
if (!framee_n) REQ_RWTn <= #Tval 1;
// If we are xferring jsut the upper DWORD and we get a
// Disconnect with data and the host does not respond to a 64
// bit xfer, then we keep the trans_count the same so we
// can retransmit just the upper data.
trans_count = (transmit_64 & xfer_odd & ACK64n) ?
trans_count :
trans_count + (transmit_64 ? inc_trans : 1);
// If the disconnect was a 64 bit transfer, then keep enable_64
// set, otherwise complete the transfer with 32 bit xfers
enable_64 = ~ACK64n;
// inc the address, or fetch the next one
if (fbtb==0)
casex ({transmit_64, xfer_odd})
2'b0x: address = address + 4;
2'b10: address = address + (4* inc_trans);
2'b11: address = address;
endcase
else if (trans_count < count) begin
if (transmit_64 && xfer_odd || ~transmit_64)
tmp_pci_cmd = pci_cmd_list[2*trans_count];
else
tmp_pci_cmd = pci_cmd_list[2*trans_count+1];
address = tmp_pci_cmd[31:0];
end // else: !if(!fbtb)
// ensure that FRAME# is negated before negating IRDY#,
// to properly terminate the transaction.
if (!framee_n) begin
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 1;
req64_n <= #Tval 1;
@ (posedge HCLK);
end // if (!framee_n)
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
prdyy_n <= #Tval 1;
`ifdef PCIX
hb_ad_bus <= #Tinval 64'hx;
`endif
hb_ad_bus <=#Tval 64'hz;
`ifdef PCIX
byte_ens <= #Tinval 8'hx;
`endif
byte_ens <= #Tval 8'hz;
framee_n <= #Tval 'bz;
req64_n <= #Tval 'bz;
prdyy_n <= #(hclk+Tval) 'bz;
data_phase_done = 1;
terminated = 1;
rwtPARen <= #Tval 0;
disable_64 = 1'b1;
end // if (DEVSELn==0 && TRDYn==0 && STOPn==0)
// Target abort: stop entire transaction
else if (DEVSELn==1 && STOPn==0) begin
// (should check to make sure DEVSEL had been asserted
// at some time.)
$display ("PCI Target Abort (write) at address %h, time: %d",address, $time);
// stop requesting the bus
REQ_RWTn <= #Tval 1;
if (!framee_n) begin
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 1;
req64_n <= #Tval 1;
end // if (!framee_n)
@ (posedge HCLK);
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
prdyy_n <= #Tval 1;
`ifdef PCIX
hb_ad_bus <= #Tinval 64'hx;
`endif
hb_ad_bus <= #Tval 64'hz;
`ifdef PCIX
byte_ens <= #Tinval 8'hx;
`endif
byte_ens <= #Tval 8'hz;
rwtPARen <= #Tval 0;
@ (posedge HCLK);
prdyy_n <= #Tval 'bz;
data_phase_done = 1;
trans_count = count;
end // if (DEVSELn==1 && STOPn==0)
// No response yet. check watchdog timers for expiration
else begin
if (trdy_count >= `WDTIMER) begin
$display ("PCI info: TRDY# timeout (write) at address %h, time: %d",address, $time);
$stop;
end // if (trdy_timer >= WDTIMER)
if (retry_count >= `MAXRETRY) begin
$display ("PCI info: max RETRY count exceeded (write) at address %h, time: %d",address, $time);
$stop;
end // if (retry_count >= 'MAXRETRY)
if (devsel_count >= `MAXDEVSEL) begin
$display ("PCI info: no DEVSEL asserted (write) at address %h, time= %d", address, $time);
REQ_RWTn <= #Tval 1;
if (!framee_n) begin
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 1;
req64_n <= #Tval 1;
end // if (!framee_n)
@ (posedge HCLK);
prdyy_n <= #Tval 1;
byte_ens <= #Tval 8'hz;
framee_n <= #Tval 'bz;
req64_n <= #Tval 'bz;
rwtPARen <= #Tval 0;
@ (posedge HCLK);
prdyy_n <= #Tval 'bz;
disable retry_loop;
end // if (devsel_count >= 'MAXDEVSEL)
end
end // while (!data_phase_done)
end // while (trans_count < count)
end // block: burst_loop
initial_data_phase = 0;
end // while (trans_count < count)
end // block: retry_loop
end
endtask //pci_write
/*
* mov_dw: write dwords with incrementing data
*/
task mov_dw;
input [3:0] host_cycle_type;
input [31:0] address;
input [31:0] data;
input [3:0] byte_enables;
input [29:0] NO_OF_BEATS; //number of beats in one burst cycle (max=1G beats)
begin
// Are there any burst_data requests pending?
if (pci_cmd_list_index > 0)
pci_burst_end; // This will call pci_write
pci_cmd_list[0] = {byte_enables, data};
pci_write(host_cycle_type, address, NO_OF_BEATS, 0);
end
endtask // mov_dw
/*
* mov_burst: write up to 8 dwords of data in a burst
*/
task mov_burst;
input [3:0] host_cycle_type;
input [31:0] address;
input [3:0] byte_enables;
input [3:0] NO_OF_BEATS;
input [31:0] data1;
input [31:0] data2;
input [31:0] data3;
input [31:0] data4;
input [31:0] data5;
input [31:0] data6;
input [31:0] data7;
input [31:0] data8;
begin
// Are there any burst_data requests pending?
if (pci_cmd_list_index > 0)
pci_burst_end; // This will call pci_write
pci_cmd_list[0] = {byte_enables, data1};
pci_cmd_list[1] = {byte_enables, data2};
pci_cmd_list[2] = {byte_enables, data3};
pci_cmd_list[3] = {byte_enables, data4};
pci_cmd_list[4] = {byte_enables, data5};
pci_cmd_list[5] = {byte_enables, data6};
pci_cmd_list[6] = {byte_enables, data7};
pci_cmd_list[7] = {byte_enables, data8};
pci_write(host_cycle_type, address, NO_OF_BEATS, 1);
end
endtask //mov_burst
/*
* mov_fbtb: write dwords with fast back to back
*/
task mov_fbtb;
input [3:0] host_cycle_type;
input [3:0] count; // max count depends on pci_cmd_list size declared above
reg [31:0] address;
reg [35:0] tmp;
begin
// Are there any burst_data requests pending?
if (pci_cmd_list_index > 0)
pci_burst_end; // This will call pci_write
tmp = pci_cmd_list[0];
address = tmp[31:0];
pci_write(host_cycle_type, address, count, 2);
end
endtask // mov_fbtb
/*
* pci_burst_end: Wrap up the data sent by pci_burst_data
*/
task pci_burst_end;
integer i;
reg [35:0] pci_cmd;
begin
if (pci_cmd_list_index > 0)
begin
`ifdef DISPLAY_PCI_BURST
$display ("PCI BURST START: address=%h time=%d",pci_burst_start_address, $time);
for (i = 0; i < pci_cmd_list_index; i = i + 1)
begin
pci_cmd = pci_cmd_list[i];
$display("PCI BURST DATA: %h %h", pci_cmd[31:0], pci_cmd[35:32]);
end
`endif // ifdef DISPLAY_PCI_BURST
pci_write(MEM_WR, pci_burst_start_address, pci_cmd_list_index, 1);
`ifdef DISPLAY_PCI_BURST
$display ("PCI BURST DONE");
`endif // ifdef DISPLAY_PCI_BURST
end
pci_cmd_list_index = 0;
end
endtask //pci_burst_end
/*
* pci_burst_data: write dwords of data in a burst
* When finished, call pci_burst_end
* Include write combining
* If new address is out of range, flush and start new burst.
*/
task pci_burst_data;
input [31:0] address;
input [3:0] byte_enables;
input [31:0] data;
begin
if (pci_cmd_list_index == 0)
begin
// Start a new burst list
pci_burst_start_address = address;
pci_cmd_list[0] = {byte_enables, data};
pci_burst_current_address = address + 4;
pci_cmd_list_index = 1;
end
else if (address == pci_burst_current_address)
begin
// Add one entry to the burst list
pci_cmd_list[pci_cmd_list_index] = {byte_enables, data};
pci_burst_current_address = pci_burst_current_address + 4;
pci_cmd_list_index = pci_cmd_list_index + 1;
end
else if ((address == pci_burst_current_address + 4) &&
(pci_cmd_list_index < (`MAX_PCI_BURST_COUNT - 1)))
begin
// Write combining - Add a dummy write
pci_cmd_list[pci_cmd_list_index ] = 36'hF_0000_0000;
pci_cmd_list[pci_cmd_list_index + 1] = {byte_enables, data};
pci_burst_current_address = pci_burst_current_address + 8;
pci_cmd_list_index = pci_cmd_list_index + 2;
end
else if ((address == pci_burst_current_address + 8) &&
(pci_cmd_list_index < (`MAX_PCI_BURST_COUNT - 2)))
begin
// Write combining - Add two dummy writes
pci_cmd_list[pci_cmd_list_index ] = 36'hF_0000_0000;
pci_cmd_list[pci_cmd_list_index + 1] = 36'hF_0000_0000;
pci_cmd_list[pci_cmd_list_index + 2] = {byte_enables, data};
pci_burst_current_address = pci_burst_current_address + 12;
pci_cmd_list_index = pci_cmd_list_index + 3;
end
else
begin
// We're writing to a new address, so flush the old list
pci_burst_end;
// Now start a new burst list
pci_burst_start_address = address;
pci_cmd_list[0] = {byte_enables, data};
pci_burst_current_address = address + 4;
pci_cmd_list_index = 1;
end
// Now check if the burst list is full
if (pci_cmd_list_index >= `MAX_PCI_BURST_COUNT)
pci_burst_end;
end
endtask //pci_burst_data
/*
* Task: pci_read
*
* Inputs:
* HCLK PCI CLK
* DEVSELn PCI DEVSEL#
* TRDYn PCI TRDY#
* STOPn PCI STOP#
* AD PCI AD
*
* Outputs:
* framee_n PCI FRAME#
* prdyy_n PCI IRDY#
* IDSEL PCI IDSEL
* hb_ad_bus PCI AD
* byte_ens PCI C/BE#
* test_reg receive data register
*
*
*/
task pci_read;
input [3:0] host_cycle_type;
input [31:0] address;
input [3:0] byte_enables;
input [29:0] count; //number of beats in one burst cycle (max= 1G beats)
integer retry_count;
integer trans_count;
integer devsel_count;
integer trdy_count;
integer irdy_count;
integer burst_count;
integer data_phase_done;
integer terminated;
integer initial_data_phase;
begin
case (mw0_size)
2'b00: mw0_mask = 11'h0;
2'b01: mw0_mask = 11'h1;
2'b10: mw0_mask = 11'h3;
2'b11: mw0_mask = 11'h7;
endcase
case (mw1_size)
2'b00: mw1_mask = 11'h0;
2'b01: mw1_mask = 11'h1;
2'b10: mw1_mask = 11'h3;
2'b11: mw1_mask = 11'h7;
endcase
case (aw_size)
0: aw_mask = 20'h1;
1: aw_mask = 20'h3;
2: aw_mask = 20'h7;
3: aw_mask = 20'hF;
4: aw_mask = 20'h1F;
5: aw_mask = 20'h3F;
6: aw_mask = 20'h7F;
7: aw_mask = 20'hFF;
8: aw_mask = 20'h1FF;
9: aw_mask = 20'h3FF;
10: aw_mask = 20'h7FF;
11: aw_mask = 20'hFFF;
default: aw_mask = 20'h1;
endcase // case(aw_size)
// Are there any burst_data requests pending?
if (pci_cmd_list_index > 0)
pci_burst_end; // This will call pci_write
/*
* Make sure the command is a read command
*/
if (host_cycle_type[0] != 0) begin
$display("Error! task rd(%h,%h,%h)", host_cycle_type, address, count);
$display(" PCI test master received a write command in a read task");
$stop;
end // if (host_cycle_type[0] != 0)
/*
* Initialize some counters used for error checking
*/
retry_count = 0;
trans_count = 0;
@(posedge HCLK);
/*
* Outermost loop handles retries.
*/
begin : retry_loop
while (trans_count < count) begin
/*
* wait for grant
*/
while (!(!GNT_RWTn && FRAMEn && PRDYn)) begin
REQ_RWTn <= #Tval 0;
@(posedge HCLK);
end // while (!(!GNT_RWTn && FRAMEn && PRDYn))
// We will do a 64 bit transfer on any memory transaction. However,
// the FPGA should not respond to all of these... We'll check that
// below.
if (`PCI64 && (host_cycle_type == MEM_RD ||
host_cycle_type == MEM_WR ||
host_cycle_type == MEM_RD_MULTI ||
host_cycle_type == MEM_RD_LINE ||
host_cycle_type == MEM_WR_INV) &&
~((count == 1) || (~address[2] && count == 2) ||
((trans_count == count - 1) ||
~address[2] && trans_count == count - 2)))
enable_64 = 1'b1;
else
enable_64 = 1'b0;
/*
* Address Phase
*/
if (host_cycle_type==CONFIG_RD) begin
`ifdef PCIX
hb_ad_bus <= #Tinval 64'bx;
`endif
`ifdef PCIX
IDSEL <= #Tinval 'bx;
`endif
hb_ad_bus <= #Tval {32'b0, 16'h1, address[15:0]};
IDSEL <= #Tval 1;
end // if (host_cycle_type==CONFIG_RD)
else begin
`ifdef PCIX
hb_ad_bus <= #Tinval 64'bx;
`endif
hb_ad_bus <= #Tval {32'b0, address};
end // else: !if(host_cycle_type==CONFIG_RD)
`ifdef PCIX
byte_ens <= #Tinval 'bx;
`endif
byte_ens <= #Tval host_cycle_type;
prdyy_n <= #Tval 'bz;
rwtPARen <= #Tval 1;
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 0;
req64_n <= #Tval ~enable_64;
REQ_RWTn <= #Tval 1;
devsel_count = 0;
/*
* Data Phases
*/
@ (posedge HCLK);
`ifdef PCIX
byte_ens <= #Tinval 'bx;
`endif
byte_ens <= #Tval byte_enables;
hb_ad_bus <= #Tval 64'bz;
rwtPARen <= #Tval 0;
IDSEL <= #Tval 'bz;
initial_data_phase = 1;
burst_count = 0;
terminated = 0;
begin : burst_loop
while ((trans_count < count) && !terminated) begin
trdy_count = 0;
// count edges until time to assert irdy#
if (irdy_random) begin
irdy_delay=irdy_pattern[irdy_pattern_index];
irdy_pattern_index = irdy_pattern_index + 1;
end // if (irdy_random)
for (irdy_count=0; irdy_count<irdy_delay; irdy_count = irdy_count + 1) begin
if (!prdyy_n) begin
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
prdyy_n <= #Tval 1;
end // if (!prdyy_n)
@ (posedge HCLK)
if (DEVSELn!=0)
devsel_count = devsel_count + 1;
if (TRDYn!=0)
trdy_count = trdy_count + 1;
end // for (irdy_count=0; irdy_count<irdy_delay; irdy_count = irdy_count + 1)
// Assert IRDY#. Also, check if STOP# asserted.
// If so, negate FRAME# (Fig's 9-4,9-7,9-9 in "PCI System
// Architecture, Third Edition") FRAME# is also negated if
// this is the last piece of data in the transaction.
if (PRDYn!='b0) begin
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
end // if (PRDYn!='b0)
prdyy_n <= #Tval 0;
if ((trans_count == count-1) || !STOPn) begin
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 1;
req64_n <= #Tval 1;
end // if (trans_count == count-1)
if (trans_count == count-1)
REQ_RWTn <= #Tval 1;
// Loop until target signals end of data phase, or until
// a time out is detected
data_phase_done = 0;
while (!data_phase_done) begin
@ (posedge HCLK);
// increment devsel and trdy watchdog timers
if (DEVSELn!=0)
devsel_count = devsel_count + 1;
if (TRDYn!=0)
trdy_count = trdy_count + 1;
// Normal end of data phase. Master grabs data
if (DEVSELn==0 && TRDYn==0 && STOPn==1) begin
`ifdef DISPLAY_READ
$display ("PCI READ: address=%h data=%h time=%d",address, AD, $time);
`endif // ifdef DISPLAY_READ
if ((rwt_log != 0)&& rwt_read_log) $fdisplay (rwt_log, "PCI READ: address=%h data=%h",address, AD);
retry_count = 0;
data_phase_done = 1;
trans_count = trans_count + 1;
burst_count = burst_count + 1;
address = address + 4;
test_reg = AD;
if (trans_count == count) begin
framee_n <= #Tval 'bz;
req64_n <= #Tval 'bz;
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
prdyy_n <= #Tval 1;
`ifdef PCIX
byte_ens <= #Tinval 8'hx;
`endif
byte_ens <= #Tval 8'hz;
prdyy_n <= #(hclk+Tval) 'bz;
end // if (trans_count == count)
end // if (DEVSELn==0 && TRDYn==0 && STOPn==1)
// Retry or Disconnect w/o data
else if (DEVSELn==0 && TRDYn==1 && STOPn==0) begin
`ifdef RWTASK_DEBUG
if (burst_count == 0)
$display ("PCI RETRY (read) at address %h, time: %d",address, $time);
else
$display ("PCI DISCONNECT w/o data (read) at address %h, time: %d",address, $time);
`endif
// must stop requesting the bus
REQ_RWTn <= #Tval 1;
// ensure that FRAME# is negated before negating IRDY#,
// to properly terminate the transaction.
if (!framee_n) begin
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 1;
req64_n <= #Tval 1;
@ (posedge HCLK);
end // if (!framee_n)
retry_count = retry_count + 1;
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
prdyy_n <= #Tval 1;
`ifdef PCIX
hb_ad_bus <= #Tinval 64'hx;
`endif
hb_ad_bus <=#Tval 64'hz;
`ifdef PCIX
byte_ens <= #Tinval 8'hx;
`endif
byte_ens <= #Tval 8'hz;
framee_n <= #Tval 'bz;
req64_n <= #Tval 'bz;
@(posedge HCLK);
prdyy_n <= #Tval 'bz;
data_phase_done = 1;
terminated = 1;
@ (posedge HCLK);
@ (posedge HCLK);
end // if (DEVSELn==0 && TRDYn==1 && STOPn==0)
// Disconnect with data
else if (DEVSELn==0 && TRDYn==0 && STOPn==0) begin
`ifdef RWTASK_DEBUG
$display ("PCI DISCONNECT with data (read) at address %h, time: %d",address, $time);
`endif
`ifdef DISPLAY_READ
$display ("PCI READ: address=%h data=%h",address, AD);
`endif
if ((rwt_log != 0)&& rwt_read_log) $fdisplay (rwt_log, "PCI READ: address=%h data=%h",address, AD);
if (!framee_n)
REQ_RWTn <= #Tval 1;
trans_count = trans_count + 1;
address = address + 4;
test_reg = AD;
// ensure that FRAME# is negated before negating IRDY#,
// to properly terminate the transaction.
if (!framee_n) begin
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 1;
req64_n <= #Tval 1;
@ (posedge HCLK);
end // if (!framee_n)
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
prdyy_n <= #Tval 1;
`ifdef PCIX
hb_ad_bus <= #Tinval 64'hx;
`endif
hb_ad_bus <=#Tval 64'hz;
`ifdef PCIX
byte_ens <= #Tinval 8'hx;
`endif
byte_ens <= #Tval 8'hz;
framee_n <= #Tval 'bz;
req64_n <= #Tval 'bz;
@(posedge HCLK);
prdyy_n <= #Tval 'bz;
data_phase_done = 1;
terminated = 1;
end // if (DEVSELn==0 && TRDYn==0 && STOPn==0)
// Target abort: stop entire transaction
else if (DEVSELn==1 && STOPn==0) begin
$display ("PCI Target Abort (read) at address %h, time: %d",address, $time);
// stop requesting the bus
REQ_RWTn <= #Tval 1;
if (!framee_n) begin
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 1;
req64_n <= #Tval 1;
end // if (!framee_n)
@ (posedge HCLK);
prdyy_n <= #Tval 1;
byte_ens <= #Tval 8'hz;
@ (posedge HCLK);
prdyy_n <= #Tval 'bz;
data_phase_done = 1;
trans_count = count;
end // if (DEVSELn==1 && STOPn==0)
// No response yet. check watchdog timers for expiration
else begin
if (trdy_count >= `WDTIMER) begin
$display ("PCI info: TRDY# timeout (read) at address %h, time: %d",address, $time);
$stop;
end // if (trdy_count >= `WDTIMER)
if (retry_count >= `MAXRETRY) begin
$display ("PCI info: max RETRY count exceeded (read) at address %h, time: %d",address, $time);
$stop;
end // if (retry_count >= `MAXRETRY)
if (devsel_count >= `MAXDEVSEL) begin
$display ("PCI info: no DEVSEL asserted (read) at address %h, time= %d", address, $time);
REQ_RWTn <= #Tval 1;
if (!framee_n) begin
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 1;
req64_n <= #Tval 1;
end // if (!framee_n)
@ (posedge HCLK);
prdyy_n <= #Tval 1;
byte_ens <= #Tval 8'hz;
@ (posedge HCLK);
prdyy_n <= #Tval 'bz;
@ (posedge HCLK);
disable retry_loop;
end // if (devsel_count >= 'MAXDEVSEL)
end // else: !if(DEVSELn==1 && STOPn==0)
end // while (!data_phase_done)
end // while (trans_count < count)
end // block: burst_loop
initial_data_phase = 0;
end // while (trans_count < count)
end // block: retry_loop
end
endtask // pci_read
/*
* Task: rd
* read with byte enables all asserted.
*
* Inputs:
* HCLK PCI CLK
* DEVSELn PCI DEVSEL#
* TRDYn PCI TRDY#
* STOPn PCI STOP#
* AD PCI AD
*
* Outputs:
* framee_n PCI FRAME#
* prdyy_n PCI IRDY#
* IDSEL PCI IDSEL
* hb_ad_bus PCI AD
* byte_ens PCI C/BE#
* test_reg receive data register
*
*
*/
task rd;
input [3:0] host_cycle_type;
input [31:0] address;
input [29:0] count; //number of beats in one burst cycle (max= 1G beats)
begin
pci_read(host_cycle_type, address, 4'h0, count);
end
endtask // rd
/*
* Task: rd_byte
* read with byte enable control.
*/
task rd_byte;
input [3:0] host_cycle_type;
input [31:0] address;
input [3:0] byte_enables;
input [29:0] count; //number of beats in one burst cycle (max= 1G beats)
begin
pci_read(host_cycle_type, address, byte_enables, count);
end
endtask // rd_byte
/*
* Task: rd_verify
*
* This task uses the following 'defines:
* RAND, PRDY[1-3],
*
* Inputs:
* HCLK PCI CLK
* DEVSELn PCI DEVSEL#
* TRDYn PCI TRDY#
* STOPn PCI STOP#
* AD PCI AD
*
* Outputs:
* framee_n PCI FRAME#
* prdyy_n PCI IRDY#
* IDSEL PCI IDSEL
* hb_ad_bus PCI AD
* byte_ens PCI C/BE#
* test_reg receive data register
*
*
*/
task rd_verify;
input [3:0] host_cycle_type;
input [31:0] address;
input [29:0] NO_OF_BEATS; //number of beats in one burst cycle
input [31:0] initial_rd_pattern; //the initail read comparison pattern
integer retry_count;
integer trans_count;
integer devsel_count;
integer trdy_count;
integer irdy_count;
integer burst_count;
integer data_phase_done;
integer terminated;
integer initial_data_phase;
begin
// Are there any burst_data requests pending?
if (pci_cmd_list_index > 0)
pci_burst_end; // This will call pci_write
/*
* Make sure the command is a read command
*/
if (host_cycle_type[0] != 0) begin
$display("Error! task rd(%h,%h,%h)", host_cycle_type, address, count);
$display(" PCI test master received a write command in a read task");
$stop;
end // if (host_cycle_type[0] != 0)
/*
* Initialize some counters used for error checking
*/
retry_count = 0;
trans_count = 0;
@(posedge HCLK);
/*
* Outermost loop handles retries.
*/
begin : retry_loop
while (trans_count < count) begin
/*
* wait for grant
*/
while (!(!GNT_RWTn && FRAMEn && PRDYn)) begin
REQ_RWTn <= #Tval 0;
@(posedge HCLK);
end // while (!(!GNT_RWTn && FRAMEn && PRDYn))
/*
* Address Phase
*/
if (host_cycle_type==CONFIG_RD) begin
`ifdef PCIX
hb_ad_bus <= #Tinval 64'bx;
`endif
`ifdef PCIX
IDSEL <= #Tinval 'bx;
`endif
hb_ad_bus <= #Tval {32'b0, 16'h1, address[15:0]};
IDSEL <= #Tval 1;
end // if (host_cycle_type==CONFIG_RD)
else begin
`ifdef PCIX
hb_ad_bus <= #Tinval 32'bx;
`endif
hb_ad_bus <= #Tval {32'b0, address};
end // else: !if(host_cycle_type==CONFIG_RD)
`ifdef PCIX
byte_ens <= #Tinval 'bx;
`endif
byte_ens <= #Tval host_cycle_type;
prdyy_n <= #Tval 'bz;
rwtPARen <= #Tval 1;
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 0;
req64_n <= #Tval 1;
REQ_RWTn <= #Tval 1;
devsel_count = 0;
/*
* Data Phases
*/
@ (posedge HCLK);
`ifdef PCIX
byte_ens <= #Tinval 'bx;
`endif
byte_ens <= #Tval 0;
hb_ad_bus <= #Tval 64'bz;
rwtPARen <= #Tval 0;
IDSEL <= #Tval 'bz;
initial_data_phase = 1;
burst_count = 0;
terminated = 0;
begin : burst_loop
while ((trans_count < count) && !terminated) begin
trdy_count = 0;
// count edges until time to assert irdy#
if (irdy_random) begin
irdy_delay=irdy_pattern[irdy_pattern_index];
irdy_pattern_index = irdy_pattern_index + 1;
end // if (irdy_random)
for (irdy_count=0; irdy_count<irdy_delay; irdy_count = irdy_count + 1) begin
if (!prdyy_n) begin
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
prdyy_n <= #Tval 1;
end // if (!prdyy_n)
@ (posedge HCLK)
if (DEVSELn!=0)
devsel_count = devsel_count + 1;
if (TRDYn!=0)
trdy_count = trdy_count + 1;
end // for (irdy_count=0; irdy_count<irdy_delay; irdy_count = irdy_count + 1)
// Assert IRDY#. Also, check if STOP# asserted.
// If so, negate FRAME# (Fig's 9-4,9-7,9-9 in "PCI System
// Architecture, Third Edition") FRAME# is also negated if
// this is the last piece of data in the transaction.
if (PRDYn!='b0) begin
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
end // if (PRDYn!='b0)
prdyy_n <= #Tval 0;
if ((trans_count == count-1) || !STOPn) begin
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 1;
req64_n <= #Tval 1;
end // if (trans_count == count-1)
if (trans_count == count-1)
REQ_RWTn <= #Tval 1;
// Loop until target signals end of data phase, or until
// a time out is detected
data_phase_done = 0;
while (!data_phase_done) begin
@ (posedge HCLK);
// increment devsel and trdy watchdog timers
if (DEVSELn!=0)
devsel_count = devsel_count + 1;
if (TRDYn!=0)
trdy_count = trdy_count + 1;
// Normal end of data phase. Master grabs data
if (DEVSELn==0 && TRDYn==0 && STOPn==1) begin
`ifdef DISPLAY_READ
$display ("PCI READ: address=%h data=%h time=%d",address, AD, $time);
`endif // ifdef DISPLAY_READ
if ((rwt_log != 0)&& rwt_read_log) $fdisplay (rwt_log, "PCI READ: address=%h data=%h",address, AD);
retry_count = 0;
data_phase_done = 1;
trans_count = trans_count + 1;
burst_count = burst_count + 1;
address = address + 4;
test_reg = AD;
if (test_reg==(initial_rd_pattern[31:0] + trans_count))
$display("COMPARISON PASSED, ADDR=%h EXPECTED DATA=%h ACTUAL_DATA=%h",
address, initial_rd_pattern, test_reg);
else
$display("COMPARISON FAILED!!!, ADDR=%h EXPECTED DATA=%h ACTUAL_DATA=%h",
address, initial_rd_pattern, test_reg);
if (trans_count == count) begin
framee_n <= #Tval 'bz;
req64_n <= #Tval 'bz;
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
prdyy_n <= #Tval 1;
`ifdef PCIX
byte_ens <= #Tinval 8'hx;
`endif
byte_ens <= #Tval 8'hz;
@(posedge HCLK);
prdyy_n <= #Tval 'bz;
end // if (trans_count == count)
end // if (DEVSELn==0 && TRDYn==0 && STOPn==1)
// Retry or Disconnect w/o data
else if (DEVSELn==0 && TRDYn==1 && STOPn==0) begin
`ifdef RWTASK_DEBUG
if (burst_count == 0)
$display ("PCI RETRY (read) at address %h, time: %d",address, $time);
else
$display ("PCI DISCONNECT w/o data (read) at address %h, time: %d",address, $time);
`endif
// must stop requesting the bus
REQ_RWTn <= #Tval 1;
// ensure that FRAME# is negated before negating IRDY#,
// to properly terminate the transaction.
if (!framee_n) begin
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 1;
req64_n <= #Tval 1;
@ (posedge HCLK);
end // if (!framee_n)
retry_count = retry_count + 1;
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
prdyy_n <= #Tval 1;
`ifdef PCIX
hb_ad_bus <= #Tinval 64'hx;
`endif
hb_ad_bus <=#Tval 64'hz;
`ifdef PCIX
byte_ens <= #Tinval 8'hx;
`endif
byte_ens <= #Tval 8'hz;
framee_n <= #Tval 'bz;
req64_n <= #Tval 'bz;
@(posedge HCLK);
prdyy_n <= #Tval 'bz;
data_phase_done = 1;
terminated = 1;
@ (posedge HCLK);
@ (posedge HCLK);
end // if (DEVSELn==0 && TRDYn==1 && STOPn==0)
// Disconnect with data
else if (DEVSELn==0 && TRDYn==0 && STOPn==0) begin
`ifdef RWTASK_DEBUG
$display ("PCI DISCONNECT with data (read) at address %h, time: %d",address, $time);
`endif
`ifdef DISPLAY_READ
$display ("PCI READ: address=%h data=%h",address, AD);
`endif
if ((rwt_log != 0)&& rwt_read_log) $fdisplay (rwt_log, "PCI READ: address=%h data=%h",address, AD);
if (!framee_n)
REQ_RWTn <= #Tval 1;
trans_count = trans_count + 1;
address = address + 4;
test_reg = AD;
if (test_reg==(initial_rd_pattern[31:0] + trans_count))
$display("COMPARISON PASSED, ADDR=%h EXPECTED DATA=%h ACTUAL_DATA=%h",
address, initial_rd_pattern, test_reg);
else
$display("COMPARISON FAILED!!!, ADDR=%h EXPECTED DATA=%h ACTUAL_DATA=%h",
address, initial_rd_pattern, test_reg);
// ensure that FRAME# is negated before negating IRDY#,
// to properly terminate the transaction.
if (!framee_n) begin
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 1;
req64_n <= #Tval 1;
@ (posedge HCLK);
end // if (!framee_n)
`ifdef PCIX
prdyy_n <= #Tinval 'bx;
`endif
prdyy_n <= #Tval 1;
`ifdef PCIX
hb_ad_bus <= #Tinval 64'hx;
`endif
hb_ad_bus <=#Tval 64'hz;
`ifdef PCIX
byte_ens <= #Tinval 8'hx;
`endif
byte_ens <= #Tval 8'hz;
framee_n <= #Tval 'bz;
req64_n <= #Tval 'bz;
@(posedge HCLK);
prdyy_n <= #Tval 'bz;
data_phase_done = 1;
terminated = 1;
end // if (DEVSELn==0 && TRDYn==0 && STOPn==0)
// Target abort: stop entire transaction
else if (DEVSELn==1 && STOPn==0) begin
$display ("PCI Target Abort (read) at address %h, time: %d",address, $time);
// stop requesting the bus
REQ_RWTn <= #Tval 1;
if (!framee_n) begin
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 1;
req64_n <= #Tval 1;
end // if (!framee_n)
@ (posedge HCLK);
prdyy_n <= #Tval 1;
byte_ens <= #Tval 8'hz;
@ (posedge HCLK);
prdyy_n <= #Tval 'bz;
data_phase_done = 1;
trans_count = count;
end // if (DEVSELn==1 && STOPn==0)
// No response yet. check watchdog timers for expiration
else begin
if (trdy_count >= `WDTIMER) begin
$display ("PCI info: TRDY# timeout (read) at address %h, time: %d",address, $time);
$stop;
end // if (trdy_count >= `WDTIMER)
if (retry_count >= `MAXRETRY) begin
$display ("PCI info: max RETRY count exceeded (read) at address %h, time: %d",address, $time);
$stop;
end // if (retry_count >= `MAXRETRY)
if (devsel_count >= `MAXDEVSEL) begin
$display ("PCI info: no DEVSEL asserted (read) at address %h, time= %d", address, $time);
REQ_RWTn <= #Tval 1;
if (!framee_n) begin
`ifdef PCIX
framee_n <= #Tinval 'bx;
req64_n <= #Tval 'bx;
`endif
framee_n <= #Tval 1;
req64_n <= #Tval 1;
end // if (!framee_n)
@ (posedge HCLK);
prdyy_n <= #Tval 1;
byte_ens <= #Tval 8'hz;
@ (posedge HCLK);
prdyy_n <= #Tval 'bz;
@ (posedge HCLK);
disable retry_loop;
end // if (devsel_count >= 'MAXDEVSEL)
end // else: !if(DEVSELn==1 && STOPn==0)
end // while (!data_phase_done)
end // while (trans_count < count)
end // block: burst_loop
initial_data_phase = 0;
end // while (trans_count < count)
end // block: retry_loop
end
endtask // rd_verify
/***********************************************************/
/**** TASK TO IMPLEMENT DAC_SNOOP ON THE PCI BUS ***/
/***********************************************************/
task pci_dac_snoop;
input [3:0] host_cycle_type;
input [31:0] address;
input [31:0] data;
input [3:0] byte_enables;
input [29:0] NO_OF_BEATS; //number of beats in one burst cycle (max=1G beats)
input [1:0] trdy_stop_type;
integer index_beat_timer;
integer index_beat_count;
begin
// Are there any burst_data requests pending?
if (pci_cmd_list_index > 0)
pci_burst_end; // This will call pci_write
$display ("DAC SNOOP CYCLE IS ACTIVATED at ADDR=%h at TIME= %d", address, $time);
//XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
//**** address phase. Present address ,assert framee_n signal &
// check if cyle type is configuration *********
//XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
#(hclk-Tsu-Thld)
fork
hb_ad_bus = {32'b0, address};
framee_n = 0;
prdyy_n = 1;
trdyy_n = 1;
stopp_n = 1;
IDSEL = 'bz;
byte_ens[3:0] = host_cycle_type[3:0];
join
//XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// CHECK IF CYCLE IS SINGLE TRANSFER OR BURST
//XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
@ (posedge HCLK)
if (NO_OF_BEATS==1)
/**************** SINGLE WRITE TRANSFER CYCLE , NO PRDY WAIT *****************/
begin
#(Thld) fork
hb_ad_bus = 64'hz;
byte_ens[3:0] = 8'hz;
IDSEL = 'bz;
framee_n = 1;
join
@ (posedge HCLK)
#(hclk-Tsu) fork
prdyy_n = 0;
hb_ad_bus = {32'b0, data};
byte_ens[3:0] = byte_enables ;
join
@ (posedge HCLK)
@ (posedge HCLK)
begin
trdyy_n = 1;
stopp_n = 1;
if (trdy_stop_type[1:0] ==2'h0) //trdy_single
#(hclk-Tsu)
trdyy_n = 0;
else if (trdy_stop_type[1:0] ==2'h3) //stop_single
#(hclk-Tsu)
stopp_n = 0;
end
@ (posedge HCLK)
#(Thld) fork
prdyy_n = 1;
trdyy_n = 1;
stopp_n = 1;
hb_ad_bus = 64'hz;
byte_ens[3:0] = 8'hz;
join
@ (posedge HCLK)
#(Thld)
fork
trdyy_n = 1'hz;
stopp_n = 1'hz;
join
end
/************************ BURST WRITE TRANSFER CYCLES , NO PRDY WAIT********************/
else if (NO_OF_BEATS!==1)
begin
#(Thld) fork
hb_ad_bus = 64'hz;
byte_ens[3:0] = 8'hz;
IDSEL = 'bz;
join
@ (posedge HCLK)
#(hclk-Tsu) fork
prdyy_n = 0;
hb_ad_bus = {32'b0, data} ;
byte_ens[3:0] = byte_enables ;
join
@ (posedge HCLK)
@ (posedge HCLK)
begin
trdyy_n = 1;
stopp_n = 1;
#(hclk-Tsu)
trdyy_n = 0;
end
for (index_beat_count=1; index_beat_count <= NO_OF_BEATS; index_beat_count = index_beat_count+1 )
begin
@ (posedge HCLK)
if (trdy_stop_type[1:0] ==2'h1 && index_beat_count == NO_OF_BEATS-1) /* BEAT BEFORE LAST */
begin
#(Thld) fork
framee_n = 1;
hb_ad_bus = 64'hz;
byte_ens[3:0] = 8'hz;
join
#(hclk-Tsu) fork
hb_ad_bus = {32'b0, data + index_beat_count};
byte_ens[3:0] = byte_enables ;
join
end
else if (trdy_stop_type[1:0] ==2'h1 && index_beat_count!==NO_OF_BEATS)
begin
#(Thld) fork
hb_ad_bus = 64'hz;
byte_ens[3:0] = 8'hz;
join
#(hclk-Tsu) fork
hb_ad_bus = {32'b0, data + index_beat_count};
byte_ens[3:0] = byte_enables ;
join
end
else if (trdy_stop_type[1:0] ==2'h1 && index_beat_count==NO_OF_BEATS) /*LAST BEAT */
begin
#(Thld) fork
prdyy_n = 1;
trdyy_n = 1;
stopp_n = 1;
hb_ad_bus = 64'hz;
byte_ens[3:0] = 8'hz;
join
end
else if (trdy_stop_type[1:0] ==2'h2) //TRDY_BURST_STOP
begin
begin
#(Thld) fork
framee_n = 1;
hb_ad_bus = 64'hz;
byte_ens[3:0] = 8'hz;
trdyy_n = 1;
join
#(hclk-Tsu-Thld) fork
hb_ad_bus = {32'b0, data + index_beat_count};
byte_ens[3:0] = byte_enables ;
stopp_n = 0;
join
end
@ (posedge HCLK)
fork
prdyy_n = 1;
trdyy_n = 1;
stopp_n = 1;
hb_ad_bus = 64'hz;
byte_ens[3:0] = 8'hz;
index_beat_count = NO_OF_BEATS;
join
end
end
@ (posedge HCLK)
#(Thld)
fork
trdyy_n = 1'hz;
stopp_n = 1'hz;
join
end
end
endtask //pci_dac_snoop
always @(posedge HCLK) begin
rwtPAR <= #Tval ^{AD[31:0],C_BEn[3:0]};
rwtPAR64 <= #Tval ^{AD[63:32],C_BEn[7:4]};
rwtPARen1 <= #Tval rwtPARen;
end // always @ (posedge HCLK)
assign PAR = rwtPARen1 ? rwtPAR : 1'bz;
assign PAR64 = rwtPARen1 ? rwtPAR64 : 1'bz;
/* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
//
// CPU_MOV.VLG - "CPU Move"
//
// This file contains tasks which convert cpu address instruction
// into bus instructions. Currently, this file contains tasks
// which simulate the DWORD and BYTE memory instruction. (WORD
// memory cycles will be simulated when resources permit.)
//
// At the bus level, all memory accesses are performed on 32 bit
// boundaries. (i.e. these memory accesses are DWORD aligned.)
// In addition to 32 bit data, the memory bus also receives a
// four bit bus strobe, each bit corresponding to a BYTE of data.
// Although 32 bit data is presented, the bus masks off each
// BYTE whose bus strobe bit is 1.
//
// Whenever the CPU accesses data, the CPU must DWORD align
// the data and calculate the appropriate strobes. If the
// data size is greater than a BYTE, then it is possible that
// the data access can not fullfilled in a single bus access.
// In this case, it is the responsibility of the CPU to
// break the access into 2 distinct bus requests.
//
// The following table lists cpu memory access to bus memory
// address conversions for various BYTES accesses. By
// convenstion, data which is masked off is indicated by
// the character 'x'.
//
// +-------------------+--------------------------------+
// | CPU Access | BUS Access |
// +-------------------+--------------------------------+
// | Address Data | Address Data Strobe |
// +-------------------+--------------------------------+
// | 0x00000000 0x12 | 0x00000000 xxxxxx12 0b1110 |
// +-------------------+--------------------------------+
// | 0x00000001 0x12 | 0x00000000 xxxx12xx 0b1101 |
// +-------------------+--------------------------------+
// | 0x00000002 0x12 | 0x00000000 xx12xxxx 0b1011 |
// +-------------------+--------------------------------+
// | 0x00000003 0x12 | 0x00000000 12xxxxxx 0b0111 |
// +-------------------+--------------------------------+
// | 0x00000004 0x12 | 0x00000004 xxxxxx12 0b1110 |
// +-------------------+--------------------------------+
//
//
// The following table lists cpu memory access to bus memory
// address conversions for various DWORD accesses. Unlike BYTE
// accesses, the CPU must convert a single DWORD access into
// multiple BUS cycles.
//
// +-------------------------+------------------------------------+
// | CPU Access | BUS Access |
// +-------------------------+------------------------------------+
// | Address Data | Cycle Address Data Strobe |
// +-------------------------+------------------------------------+
// | 0x00000000 0x12345678 | (1) 0x00000000 12345678 0b0000 |
// +-------------------------+------------------------------------+
// | 0x00000001 0x12345678 | (1) 0x00000000 345678xx 0b0001 |
// | | (2) 0x00000004 xxxxxx12 0b1110 |
// +-------------------------+------------------------------------+
// | 0x00000002 0x12345678 | (1) 0x00000000 5678xxxx 0b0011 |
// | | (2) 0x00000004 xxxx1234 0b1100 |
// +-------------------------+------------------------------------+
// | 0x00000003 0x12345678 | (1) 0x00000000 78xxxxxx 0b0111 |
// | | (2) 0x00000004 xx123456 0b1000 |
// +-------------------------+------------------------------------+
// | 0x00000004 0x12345678 | (1) 0x00000004 12345678 0b0000 |
// +-------------------------+------------------------------------+
// */
// /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
//
//
task cpu_mov_dw;
input[3:0] Access;
input[31:0] Address;
input[31:0] Data;
reg[31:0] shift_back, shift_forward;
reg[31:0] Address1, Address2;
reg[31:0] Data1, Data2;
reg[3:0] Mask1, Mask2;
reg[3:0] Strobe1, Strobe2;
reg[3:0] StandardMask ;
reg[3:0] Strobe;
/* initial */
begin
StandardMask = 4'b1111;
shift_back = (Address & 32'h0000_0003);
if (shift_back > 0)
begin
shift_forward = 4 - shift_back;
Address1 = Address - shift_back;
Data1 = Data << (shift_back * 8);
Mask1 = StandardMask << shift_back;
Strobe1 = ~Mask1;
Address2 = Address + shift_forward;
Data2 = Data >> (shift_forward * 8);
Mask2 = StandardMask >> shift_forward;
Strobe2 = ~Mask2;
mov_dw(Access, Address1, Data1, Strobe1, 1);
mov_dw(Access, Address2, Data2, Strobe2, 1);
end
else /* There is no need to shift data. */
begin
Strobe = ~StandardMask;
mov_dw(Access, Address, Data, Strobe, 1);
end
end
endtask // cpu_mov_dw
task cpu_mov_w;
input[3:0] Access;
input[31:0] Address;
input[15:0] Data;
reg[31:0] shift_back;
reg[31:0] Data2;
reg[3:0] StandardMask ;
reg[3:0] Strobe;
/* initial */
begin
StandardMask = 4'b0011;
shift_back = (Address & 32'h0000_0003);
if (shift_back > 2)
begin
mov_dw(Access, Address - 3, Data << 24, 4'b1000, 1);
mov_dw(Access, Address + 1, Data, 4'b0001, 1);
end
else /* Shift the data in the word */
begin
Strobe = ~(StandardMask << shift_back);
Data2 = Data << (shift_back << 3);
mov_dw(Access, Address - shift_back, Data2, Strobe, 1);
end
end
endtask // cpu_mov_w
task cpu_mov_b;
input[3:0] Access;
input[31:0] Address;
input[7:0] Data;
reg[31:0] shift_back, shift_forward;
reg[31:0] NewAddress;
reg[31:0] LongData;
reg[3:0] Mask;
reg[3:0] StandardMask;
reg[3:0] Strobe;
/* initial */
begin
LongData = Data;
StandardMask = 4'b0001;
shift_back = (Address & 32'h0000_0003);
if (shift_back > 0)
begin
shift_forward = 4 - shift_back;
NewAddress = Address - shift_back;
LongData = LongData << (shift_back * 8);
Mask = StandardMask << shift_back;
Strobe = ~Mask;
mov_dw(Access, NewAddress, LongData, Strobe, 1);
end
else /* There is no need to shift data. */
begin
Strobe = ~StandardMask;
mov_dw(Access, Address, LongData, Strobe, 1);
end
end
endtask // cpu_mov_b
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 18:05:44 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemFaces/MemFaces_stub.v
// Design : MemFaces
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.4" *)
module MemFaces(clka, addra, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,addra[9:0],douta[799:0]" */;
input clka;
input [9:0]addra;
output [799:0]douta;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4B_PP_SYMBOL_V
`define SKY130_FD_SC_HD__AND4B_PP_SYMBOL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__and4b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4B_PP_SYMBOL_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_hinterp(
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [11:0] x,
input signed [11:0] y,
input signed [17:0] tsx,
input signed [17:0] tsy,
input diff_x_positive,
input [16:0] diff_x_q,
input [16:0] diff_x_r,
input diff_y_positive,
input [16:0] diff_y_q,
input [16:0] diff_y_r,
input [10:0] dst_squarew,
output pipe_stb_o,
input pipe_ack_i,
output reg signed [11:0] dx,
output reg signed [11:0] dy,
output signed [17:0] tx,
output signed [17:0] ty
);
reg load;
reg next_point;
/* Interpolators */
tmu2_geninterp18 i_tx(
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(tsx),
.positive(diff_x_positive),
.q(diff_x_q),
.r(diff_x_r),
.divisor({6'd0, dst_squarew}),
.o(tx)
);
tmu2_geninterp18 i_ty(
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(tsy),
.positive(diff_y_positive),
.q(diff_y_q),
.r(diff_y_r),
.divisor({6'd0, dst_squarew}),
.o(ty)
);
always @(posedge sys_clk) begin
if(load) begin
dx <= x;
dy <= y;
end else if(next_point)
dx <= dx + 12'd1;
end
/* Controller */
reg [10:0] remaining_points;
always @(posedge sys_clk) begin
if(load)
remaining_points <= dst_squarew - 11'd1;
else if(next_point)
remaining_points <= remaining_points - 11'd1;
end
wire last_point = remaining_points == 11'd0;
reg state;
reg next_state;
parameter IDLE = 1'b0;
parameter BUSY = 1'b1;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
assign busy = state;
assign pipe_ack_o = ~state;
assign pipe_stb_o = state;
always @(*) begin
next_state = state;
load = 1'b0;
next_point = 1'b0;
case(state)
IDLE: begin
if(pipe_stb_i) begin
load = 1'b1;
next_state = BUSY;
end
end
BUSY: begin
if(pipe_ack_i) begin
if(last_point)
next_state = IDLE;
else
next_point = 1'b1;
end
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DLRTP_PP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTP_PP_BLACKBOX_V
|
`include "defines.vh"
module prio_enc #(
parameter WIDTH_LOG = 4
) (x, msb);
localparam WIDTH = 1 << WIDTH_LOG;
localparam HI = WIDTH - 1;
input [HI:0] x;
`define FAST_1
//`define FAST_2
//`define SLOW
`ifdef FAST_1
// This seems to compile to most cost-efficient
// implementation across all toolchains.
output reg [WIDTH_LOG - 1:0] msb;
integer i, width;
reg [HI:0] part;
always @* begin
msb = 0;
part = x;
for (i = WIDTH_LOG - 1; i >= 0; i = i - 1) begin
width = 1 << i;
if (|(part >> width))
msb[i] = 1;
// Hopefully synthesizer understands that 'part' is shrinking...
part = msb[i] ? part >> width : part & ((1'd1 << width) - 1'd1);
end
end
`endif
`ifdef FAST_2
// The most low-level implementation. Surprinsingly it's not always
// the fastest...
output [WIDTH_LOG - 1:0] msb;
wire [WIDTH_LOG*WIDTH - 1:0] ors;
assign ors[WIDTH_LOG*WIDTH - 1:(WIDTH_LOG - 1)*WIDTH] = x;
genvar w, i;
integer j;
generate
for (w = WIDTH_LOG - 1; w >= 0; w = w - 1) begin
assign msb[w] = |ors[w*WIDTH + 2*(1 << w) - 1:w*WIDTH + (1 << w)];
if (w > 0) begin
assign ors[(w - 1)*WIDTH + (1 << w) - 1:(w - 1)*WIDTH] = msb[w] ? ors[w*WIDTH + 2*(1 << w) - 1:w*WIDTH + (1 << w)] : ors[w*WIDTH + (1 << w) - 1:w*WIDTH];
end
end
endgenerate
`endif
`ifdef SLOW
// Slow but simple. Some synthesizers are able
// to generate good RTL from this but not all.
output reg [WIDTH_LOG - 1:0] msb;
integer i;
always @* begin
msb = 0;
for (i = HI; i >= 0; i = i - 1)
if (!msb && x[i])
msb = i;
end
`endif
`ifdef SIM
// initial
// $monitor("%t: x=%b, msb=%b, ors=%b", $time, x, msb, ors);
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCIN_BEHAVIORAL_V
`define SKY130_FD_SC_LS__FAHCIN_BEHAVIORAL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fahcin (
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire ci ;
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM, A, B, ci );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCIN_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR3_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__XOR3_BEHAVIORAL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR3_BEHAVIORAL_V |
module mio (/*AUTOARG*/
// Outputs
tx_clk, tx_access, tx_packet, rx_wait, wait_out, access_out,
packet_out, reg_wait_out, reg_access_out, reg_packet_out,
// Inputs
clk, nreset, tx_wait, rx_clk, rx_access, rx_packet, access_in,
packet_in, wait_in, reg_access_in, reg_packet_in, reg_wait_in
);
//#####################################################################
//# INTERFACE
//#####################################################################
//parameters
parameter NMIO = 8; // IO width
parameter AW = 32; // address width
parameter MPW = 128; // mio packet width (>PW)
parameter PW = 2*AW+40; // emesh packet width
parameter DEF_CFG = 0; // Default config
parameter DEF_CLK = 0; // Default clock
parameter TARGET = "GENERIC";// GENERIC,XILINX,ALTERA,GENERIC,ASIC
// reset, clk, config
input clk; // main core clock
input nreset; // async active low reset
// tx chip interface (to IO)
output tx_clk; // phase shited io_clk
output tx_access; // access signal for IO
output [NMIO-1:0] tx_packet; // packet for IO
input tx_wait; // pushback from IO
// rx chip interface (from IO)
input rx_clk; // rx clock
input rx_access; // rx access
input [NMIO-1:0] rx_packet; // rx packet
output rx_wait; // pushback from IO
// core emesh interface
input access_in; // access for tx
input [PW-1:0] packet_in; // access for tx
output wait_out; // access from tx fifo
output access_out; // access from rx
output [PW-1:0] packet_out; // packet from rx
input wait_in; // pushback for rx fifo
// register config interface
input reg_access_in; // config register access
input [PW-1:0] reg_packet_in; // config register packet
output reg_wait_out; // pushback by register read
output reg_access_out;// config readback
output [PW-1:0] reg_packet_out;// config reacback packet
input reg_wait_in; // pushback for readback
//#####################################################################
//# BODY
//#####################################################################
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire amode; // From mio_regs of mio_regs.v
wire clkchange; // From mio_regs of mio_regs.v
wire [7:0] clkdiv; // From mio_regs of mio_regs.v
wire [15:0] clkphase0; // From mio_regs of mio_regs.v
wire [15:0] clkphase1; // From mio_regs of mio_regs.v
wire [4:0] ctrlmode; // From mio_regs of mio_regs.v
wire [7:0] datasize; // From mio_regs of mio_regs.v
wire ddr_mode; // From mio_regs of mio_regs.v
wire [AW-1:0] dstaddr; // From mio_regs of mio_regs.v
wire emode; // From mio_regs of mio_regs.v
wire framepol; // From mio_regs of mio_regs.v
wire io_clk; // From oh_clockdiv of oh_clockdiv.v
wire lsbfirst; // From mio_regs of mio_regs.v
wire rx_access_io2c; // From mio_dp of mio_dp.v
wire rx_empty; // From mio_dp of mio_dp.v
wire rx_en; // From mio_regs of mio_regs.v
wire rx_full; // From mio_dp of mio_dp.v
wire [MPW-1:0] rx_packet_io2c; // From mio_dp of mio_dp.v
wire rx_prog_full; // From mio_dp of mio_dp.v
wire rx_wait_c2io; // From mio_if of mio_if.v
wire tx_access_c2io; // From mio_if of mio_if.v
wire tx_empty; // From mio_dp of mio_dp.v
wire tx_en; // From mio_regs of mio_regs.v
wire tx_full; // From mio_dp of mio_dp.v
wire [MPW-1:0] tx_packet_c2io; // From mio_if of mio_if.v
wire tx_prog_full; // From mio_dp of mio_dp.v
wire tx_wait_io2c; // From mio_dp of mio_dp.v
// End of automatics
//################################
//# CONFIGURATION REGISTERS
//################################
/*mio_regs AUTO_TEMPLATE (.\(.*\)_out (reg_\1_out[]),
.\(.*\)_in (reg_\1_in[]),
);
*/
mio_regs #(.AW(AW),
.PW(PW),
.DEF_CFG(DEF_CFG),
.DEF_CLK(DEF_CLK))
mio_regs (.dmode (),
/*AUTOINST*/
// Outputs
.wait_out (reg_wait_out), // Templated
.access_out (reg_access_out), // Templated
.packet_out (reg_packet_out[PW-1:0]), // Templated
.tx_en (tx_en),
.rx_en (rx_en),
.ddr_mode (ddr_mode),
.emode (emode),
.amode (amode),
.datasize (datasize[7:0]),
.lsbfirst (lsbfirst),
.framepol (framepol),
.ctrlmode (ctrlmode[4:0]),
.dstaddr (dstaddr[AW-1:0]),
.clkchange (clkchange),
.clkdiv (clkdiv[7:0]),
.clkphase0 (clkphase0[15:0]),
.clkphase1 (clkphase1[15:0]),
// Inputs
.clk (clk),
.nreset (nreset),
.access_in (reg_access_in), // Templated
.packet_in (reg_packet_in[PW-1:0]), // Templated
.wait_in (reg_wait_in), // Templated
.tx_full (tx_full),
.tx_prog_full (tx_prog_full),
.tx_empty (tx_empty),
.rx_full (rx_full),
.rx_prog_full (rx_prog_full),
.rx_empty (rx_empty));
//################################
//# TX CLOCK DRIVER
//################################
/*oh_clockdiv AUTO_TEMPLATE (
.clkout0 (io_clk),
.clkout1 (tx_clk),
.clken (tx_en),
);
*/
oh_clockdiv oh_clockdiv(.clkrise0 (),
.clkfall0 (),
.clkrise1 (),
.clkfall1 (),
.clkstable (),
/*AUTOINST*/
// Outputs
.clkout0 (io_clk), // Templated
.clkout1 (tx_clk), // Templated
// Inputs
.clk (clk),
.nreset (nreset),
.clkchange (clkchange),
.clken (tx_en), // Templated
.clkdiv (clkdiv[7:0]),
.clkphase0 (clkphase0[15:0]),
.clkphase1 (clkphase1[15:0]));
//################################
//# DATAPATH
//################################
/*mio_dp AUTO_TEMPLATE (.wait_in (rx_wait_c2io),
.wait_out (tx_wait_io2c),
.packet_out (rx_packet_io2c[MPW-1:0]),
.packet_in (tx_packet_c2io[MPW-1:0]),
.access_in (tx_access_c2io),
.\(.*\)_out (rx_\1_io2c[]),
);
*/
mio_dp #(.TARGET(TARGET),
.NMIO(NMIO),
.PW(MPW))
mio_dp(/*AUTOINST*/
// Outputs
.tx_full (tx_full),
.tx_prog_full (tx_prog_full),
.tx_empty (tx_empty),
.rx_full (rx_full),
.rx_prog_full (rx_prog_full),
.rx_empty (rx_empty),
.tx_access (tx_access),
.tx_packet (tx_packet[NMIO-1:0]),
.rx_wait (rx_wait),
.wait_out (tx_wait_io2c), // Templated
.access_out (rx_access_io2c), // Templated
.packet_out (rx_packet_io2c[MPW-1:0]), // Templated
// Inputs
.clk (clk),
.io_clk (io_clk),
.nreset (nreset),
.datasize (datasize[7:0]),
.ddr_mode (ddr_mode),
.lsbfirst (lsbfirst),
.framepol (framepol),
.tx_en (tx_en),
.rx_en (rx_en),
.tx_wait (tx_wait),
.rx_clk (rx_clk),
.rx_access (rx_access),
.rx_packet (rx_packet[NMIO-1:0]),
.access_in (tx_access_c2io), // Templated
.packet_in (tx_packet_c2io[MPW-1:0]), // Templated
.wait_in (rx_wait_c2io)); // Templated
//################################
//# MIO INTERFACE
//################################
/*mio_if AUTO_TEMPLATE (
.\(.*\)_\(.*\)_out (\1_\2_c2io[]),
.\(.*\)_\(.*\)_in (\1_\2_io2c[]),
);
*/
mio_if #(.AW(AW),
.PW(PW),
.MPW(MPW))
mio_if (
/*AUTOINST*/
// Outputs
.access_out (access_out),
.packet_out (packet_out[PW-1:0]),
.wait_out (wait_out),
.rx_wait_out (rx_wait_c2io), // Templated
.tx_access_out (tx_access_c2io), // Templated
.tx_packet_out (tx_packet_c2io[MPW-1:0]), // Templated
// Inputs
.clk (clk),
.nreset (nreset),
.amode (amode),
.emode (emode),
.lsbfirst (lsbfirst),
.datasize (datasize[7:0]),
.ctrlmode (ctrlmode[4:0]),
.dstaddr (dstaddr[AW-1:0]),
.wait_in (wait_in),
.access_in (access_in),
.packet_in (packet_in[PW-1:0]),
.rx_access_in (rx_access_io2c), // Templated
.rx_packet_in (rx_packet_io2c[MPW-1:0]), // Templated
.tx_wait_in (tx_wait_io2c)); // Templated
endmodule // mio_dp
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../common/hdl")
// End:
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
// Parameters used for fsm states
parameter WIN_UNCHANGE_START = 1'b0;
parameter WIN_UNCHANGE_CHECK = 1'b1;
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
`ifdef OVL_SHARED_CODE
reg [width-1:0] r_test_expr;
reg r_state;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
r_state <= WIN_UNCHANGE_START;
// r_test_expr deliberately not reset
end
else begin
r_test_expr <= test_expr;
case (r_state)
WIN_UNCHANGE_START: if (start_event == 1'b1) begin
r_state <= WIN_UNCHANGE_CHECK;
end
WIN_UNCHANGE_CHECK: if (end_event == 1'b1) begin
r_state <= WIN_UNCHANGE_START;
end
endcase
end
end
`endif
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression has changed value before the event window closes");
end
end
end
assign fire_2state_1 = ((r_state == WIN_UNCHANGE_CHECK) && (r_test_expr != test_expr));
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1, fire_xcheck_2, fire_xcheck_3;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
if (fire_xcheck_2) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
if (fire_xcheck_3) begin
ovl_error_t(`OVL_FIRE_XCHECK,"end_event contains X or Z");
end
end
end
wire valid_start_event = ((start_event ^ start_event) == 1'b0);
wire valid_test_expr = ((test_expr ^ test_expr) == {width{1'b0}});
wire valid_end_event = ((end_event ^ end_event) == 1'b0);
always @ (valid_start_event or r_state) begin
if (valid_start_event || (r_state != WIN_UNCHANGE_START)) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1; // start_event X when r_state is WIN_UNCHANGE_START
end
end
always @ (valid_test_expr or r_state or start_event) begin
if (valid_test_expr || !((r_state == WIN_UNCHANGE_CHECK) || start_event)) begin
fire_xcheck_2 = 1'b0;
end
else begin
fire_xcheck_2 = 1'b1; // test_expr X when r_state is CHECK or start_event high
end
end
always @ (valid_end_event or r_state) begin
if (valid_end_event || (r_state != WIN_UNCHANGE_CHECK)) begin
fire_xcheck_3 = 1'b0;
end
else begin
fire_xcheck_3 = 1'b1; // end_event X when r_state is WIN_UNCHANGE_CHECK
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
wire fire_cover_1, fire_cover_2;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_cover_1) begin
ovl_cover_t("window_open covered"); // basic
end
if (fire_cover_2) begin
ovl_cover_t("window covered"); // basic
end
end
end
assign fire_cover_1 = ((OVL_COVER_BASIC_ON > 0) && (start_event == 1'b1) && (r_state == WIN_UNCHANGE_START));
assign fire_cover_2 = ((OVL_COVER_BASIC_ON > 0) && (end_event == 1'b1) && (r_state == WIN_UNCHANGE_CHECK));
`endif // OVL_COVER_ON
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file ram_8x512_hi.v when simulating
// the core, ram_8x512_hi. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module ram_8x512_hi(
addr,
clk,
din,
dout,
en,
we);
input [8 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input we;
// synthesis translate_off
BLKMEMSP_V6_2 #(
.c_addr_width(9),
.c_default_data("0"),
.c_depth(512),
.c_enable_rlocs(0),
.c_has_default_data(1),
.c_has_din(1),
.c_has_en(1),
.c_has_limit_data_pitch(0),
.c_has_nd(0),
.c_has_rdy(0),
.c_has_rfd(0),
.c_has_sinit(0),
.c_has_we(1),
.c_limit_data_pitch(18),
.c_mem_init_file("mif_file_16_1"),
.c_pipe_stages(0),
.c_reg_inputs(0),
.c_sinit_value("0"),
.c_width(8),
.c_write_mode(0),
.c_ybottom_addr("0"),
.c_yclk_is_rising(1),
.c_yen_is_high(0),
.c_yhierarchy("hierarchy1"),
.c_ymake_bmm(0),
.c_yprimitive_type("16kx1"),
.c_ysinit_is_high(1),
.c_ytop_addr("1024"),
.c_yuse_single_primitive(0),
.c_ywe_is_high(0),
.c_yydisable_warnings(1))
inst (
.ADDR(addr),
.CLK(clk),
.DIN(din),
.DOUT(dout),
.EN(en),
.WE(we),
.ND(),
.RFD(),
.RDY(),
.SINIT());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of ram_8x512_hi is "black_box"
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4BB_TB_V
`define SKY130_FD_SC_MS__AND4BB_TB_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and4bb.v"
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B_N = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B_N = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B_N = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B_N = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_ms__and4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4BB_TB_V
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_srl_fifo;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire [2:0] count;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
count);
// dump file
$dumpfile("test_axis_srl_fifo.lxt");
$dumpvars(0, test_axis_srl_fifo);
end
axis_srl_fifo #(
.DEPTH(4),
.DATA_WIDTH(8)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// Status
.count(count)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2015 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2015.4
// \ \ Description : Xilinx Unified Simulation Library Component
// / / _no_description_
// /___/ /\ Filename : IBUFDS_DPHY.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_DPHY #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter DIFF_TERM = "TRUE",
parameter IOSTANDARD = "DEFAULT",
parameter SIM_DEVICE = "ULTRASCALE_PLUS"
)(
output HSRX_O,
output LPRX_O_N,
output LPRX_O_P,
input HSRX_DISABLE,
input I,
input IB,
input LPRX_DISABLE
);
// define constants
localparam MODULE_NAME = "IBUFDS_DPHY";
// Parameter encodings and registers
localparam DIFF_TERM_FALSE = 1;
localparam DIFF_TERM_TRUE = 0;
localparam IOSTANDARD_DEFAULT = 0;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "IBUFDS_DPHY_dr.v"
`else
localparam [40:1] DIFF_TERM_REG = DIFF_TERM;
localparam [56:1] IOSTANDARD_REG = IOSTANDARD;
`endif
wire DIFF_TERM_BIN;
wire IOSTANDARD_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire HSRX_O_out;
wire LPRX_O_N_out;
wire LPRX_O_P_out;
wire HSRX_DISABLE_in;
wire IB_in;
wire I_in;
wire LPRX_DISABLE_in;
assign HSRX_O = HSRX_O_out;
assign LPRX_O_N = LPRX_O_N_out;
assign LPRX_O_P = LPRX_O_P_out;
assign HSRX_DISABLE_in = HSRX_DISABLE;
assign IB_in = IB;
assign I_in = I;
assign LPRX_DISABLE_in = LPRX_DISABLE;
assign DIFF_TERM_BIN =
(DIFF_TERM_REG == "FALSE") ? DIFF_TERM_FALSE :
(DIFF_TERM_REG == "TRUE") ? DIFF_TERM_TRUE :
DIFF_TERM_TRUE;
assign IOSTANDARD_BIN =
(IOSTANDARD_REG == "DEFAULT") ? IOSTANDARD_DEFAULT :
IOSTANDARD_DEFAULT;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((DIFF_TERM_REG != "TRUE") &&
(DIFF_TERM_REG != "FALSE"))) begin
$display("Error: [Unisim %s-101] DIFF_TERM attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DIFF_TERM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_DEVICE != "ULTRASCALE_PLUS") &&
(SIM_DEVICE != "ULTRASCALE_PLUS_ES1") &&
(SIM_DEVICE != "ULTRASCALE_PLUS_ES2") &&
(SIM_DEVICE != "VERSAL_AI_CORE") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_EDGE") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_RF") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES1") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES2") &&
(SIM_DEVICE != "VERSAL_HBM") &&
(SIM_DEVICE != "VERSAL_HBM_ES1") &&
(SIM_DEVICE != "VERSAL_HBM_ES2") &&
(SIM_DEVICE != "VERSAL_PREMIUM") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES1") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES2") &&
(SIM_DEVICE != "VERSAL_PRIME") &&
(SIM_DEVICE != "VERSAL_PRIME_ES1") &&
(SIM_DEVICE != "VERSAL_PRIME_ES2"))) begin
$display("Error: [Unisim %s-102] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE);
attr_err = 1'b1;
end
// no check
// if ((attr_test == 1'b1) ||
// ((IOSTANDARD_REG != "DEFAULT"))) begin
// $display("Error: [Unisim %s-102] IOSTANDARD attribute is set to %s. Legal values for this attribute are DEFAULT. Instance: %m", MODULE_NAME, IOSTANDARD_REG);
// attr_err = 1'b1;
// end
if (attr_err == 1'b1) #1 $finish;
end
reg o_out;
wire [1:0] lp_out;
wire sim_mode;
wire lp_mode;
wire lp_rx_disable;
wire hs_mode;
wire hs_out;
reg [3*8:1] strP,strN;
always @(*)
begin
$sformat(strP, "%v", I);
$sformat(strN, "%v", IB);
end
assign lp_mode = (strP[24:17] == "S") & (strN[24:17] == "S"); // For LP strength type Strong
//assign sim_mode = (SIM_DEVICE == "ULTRASCALE_PLUS" || SIM_DEVICE== "ULTRASCALE_PLUS_ES1" || SIM_DEVICE== "ULTRASCALE_PLUS_ES2") ? 1'b0 : 1'b0;
assign sim_mode = 1'b0;
assign #1 lp_out[0] = lp_mode === 1'b1 ? I_in : 1'b0;
assign #1 lp_out[1] = lp_mode === 1'b1 ? IB_in : 1'b0;
assign HSRX_O_out = (HSRX_DISABLE_in === 1'b0) ? o_out : (HSRX_DISABLE_in === 1'bx || HSRX_DISABLE_in === 1'bz) ? 1'bx : 1'b0;
assign LPRX_O_N_out = (LPRX_DISABLE_in === 1'b0) ? lp_out[1] : (LPRX_DISABLE_in === 1'bx || LPRX_DISABLE_in === 1'bz) ? 1'bx : sim_mode;
assign LPRX_O_P_out = (LPRX_DISABLE_in === 1'b0) ? lp_out[0] : (LPRX_DISABLE_in === 1'bx || LPRX_DISABLE_in === 1'bz) ? 1'bx : sim_mode;
always @ (I_in or IB_in) begin
if (I_in == 1'b1 && IB_in == 1'b0)
o_out <= 1'b1;
else if (I_in == 1'b0 && IB_in == 1'b1)
o_out <= 1'b0;
else if ((I_in === 1'bx) || (IB_in === 1'bx) || I_in === 1'bz || IB_in === 1'bz )
o_out <= 1'bx;
end
endmodule
`endcelldefine
|