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The Goodyear Massively Parallel Processor (MPP) was a
massively parallel processing supercomputer built by Goodyear Aerospace
for the NASA Goddard Space Flight Center. It was designed to deliver enormous computational power at lower cost than other existing supercomputer architectures, by using thousands of simple processing elements, rather than one or a few highly complex CPUs. Development of the MPP began circa 1979; it was delivered in May 1983, and was in general use from 1985 until 1991.
It was based on Goodyear's earlier STARAN array processor, a 4x256 1-bit processing element (PE) computer. The MPP was a 128x128 2-dimensional array of 1-bit wide PEs. In actuality 132x128 PEs were configured with a 4x128 configuration added for fault tolerance to substitute for up to 4 rows (or columns) of processors in the presence of problems. The PEs operated in a single instruction, multiple data (SIMD) fashioneach PE performed the same operation simultaneously, on different data elements, under the control of a microprogrammed control unit.
After the MPP was retired in 1991, it was donated to the Smithsonian Institution, and is now in the collection of the National Air and Space Museum's Steven F. Udvar-Hazy Center. It was succeeded at Goddard by the MasPar MP-1 and Cray T3D massively parallel computers.
Applications
The MPP was initially developed for high-speed analysis of satellite images. In early tests, it was able to extract and separate different land-use areas on Landsat imagery in 18 seconds, as compared with 7 hours on a DEC VAX-11/780.
Once the system was put into production use, NASA's Office of Space Science and Applications solicited proposals from scientists across the country to test and implement a wide range of computational algorithms on the MPP. 40 projects were accepted, to form the "MPP Working Group"; results of most of them were presented at the First Symposium on the Frontiers of Massively Parallel Computation, in 1986.
Some examples of applications that were made of the MPP are:
Signal processing of synthetic aperture radar data
Generating topographic maps via stereo analysis of satellite images
Mathematical modeling of ocean circulation
Ray traced computer graphics
Neural networks
Solving large systems of linear equations
Simulation of cosmic ray charged particle transport
High resolution Mandelbrot sets
System architecture
The overall MPP hardware consisted of the Array Unit, Array Control Unit, Staging Memory, and Host Processor.
The Array Unit was the heart of the MPP, being the 128x128 array of 16,384 processing elements. Each PE was connected to its four nearest neighbors - north, south, east, and west. The array could be configured as a plane, a cylinder, a daisy-chain or as a torus. The PEs were implemented on a custom silicon-on-sapphire LSI chip which contained eight of the PEs as a 2x4 subarray. Each of the PEs had arithmetic and logic units, 35 shift registers, and 1024 bits of random-access memory implemented with off-the-shelf memory chips. The processors worked in a bit-slice manner and could operate on variable lengths of data. The operating frequency of the array was 10 MHz. Data-bus states of all 16,384 PEs were combined in a tree of inclusive-or logic elements whose single output was used in the Array Control Unit for operations such as finding the maximum or minimum value of an array in parallel. A register in each PE controlled masking of operations — masked operations were only performed on those PEs where this register bit was set.
The Array Control Unit (ACU) broadcast commands and memory addresses to all PEs in the Array Unit, and received status bits from the Array Unit.
It performed bookkeeping operations such as loop control and subroutine calling. Application program code was stored in the ACU's memory; the ACU executed scalar parts of the program, and then queued up parallel instructions for the array. It also controlled the shifting of data among PEs, and between the Array Unit and the Staging Memory.
The Staging Memory was a 32MB block of memory for buffering Array Unit
data. It was useful because the PEs themselves had only a total of 2MB of memory (1024 bits per PE), and because it provided higher communication bit rate than the Host Processor connection (80 megabytes/second versus 5 megabytes/second). The Staging Memory also provided data-manipulation features such as "corner turning" (rearranging byte- or word-oriented data from the array) and multi-dimensional array access.
Data was moved between the Staging Memory and the array via 128 parallel lines.
The Host Processor was a front-end computer that loaded programs and data into the MPP, and provided software development tools and networked access to the MPP. The original Host Processor was a PDP-11, which was soon replaced by a VAX-11/780 connected to the MPP by a DR-780 channel. The VAX ran the VMS operating system, and was programmed in MPP Pascal.
Speed of operations
The raw computing speed for basic arithmetic operations on the MPP was as follows:
See also
ICL DAP
Thinking Machines Connection Machine
MasPar
Beowulf cluster
Parsytec
SUPRENUM
References
Neil Boyd Coletti, "Image processing on MPP-like arrays", Ph.D. thesis, Department of Computer Science, University of Illinois at Urbana-Champaign, 1983.
E. Gallopoulos, D. Kopetzky, S.McEwan, D.L. Slotnick and A. Spry, "MPP program development and simulation". In "The Massively Parallel Processor", J.L. Potter ed., pp. 276–290, MIT Press, 1985
Tom Henkel. "MPP processes satellite data; Supercomputer claims world's fastest I/O rate", Computerworld, 13 Feb 1984, p. 99.
Eric J. Lerner. "Many processors make light work", Aerospace America, February 1986, p. 50.
Todd Kushner, Angela Wu, Azriel Rosenfeld, "Image Processing on MPP", Pattern Recognition - PR, vol. 15, no. 3, pp. 121–130, 1982
Supercomputers
Massively parallel computers
One-of-a-kind computers
MPP
Computers using bit-slice designs |
In control systems theory, the describing function (DF) method, developed by Nikolay Mitrofanovich Krylov and Nikolay Bogoliubov in the 1930s, and extended by Ralph Kochenburger is an approximate procedure for analyzing certain nonlinear control problems. It is based on quasi-linearization, which is the approximation of the non-linear system under investigation by a linear time-invariant (LTI) transfer function that depends on the amplitude of the input waveform. By definition, a transfer function of a true LTI system cannot depend on the amplitude of the input function because an LTI system is linear. Thus, this dependence on amplitude generates a family of linear systems that are combined in an attempt to capture salient features of the non-linear system behavior. The describing function is one of the few widely applicable methods for designing nonlinear systems, and is very widely used as a standard mathematical tool for analyzing limit cycles in closed-loop controllers, such as industrial process controls, servomechanisms, and electronic oscillators.
The method
Consider feedback around a discontinuous (but piecewise continuous) nonlinearity (e.g., an amplifier with saturation, or an element with deadband effects) cascaded with a slow stable linear system. The continuous region in which the feedback is presented to the nonlinearity depends on the amplitude of the output of the linear system. As the linear system's output amplitude decays, the nonlinearity may move into a different continuous region. This switching from one continuous region to another can generate periodic oscillations. The describing function method attempts to predict characteristics of those oscillations (e.g., their fundamental frequency) by assuming that the slow system acts like a low-pass or bandpass filter that concentrates all energy around a single frequency. Even if the output waveform has several modes, the method can still provide intuition about properties like frequency and possibly amplitude; in this case, the describing function method can be thought of as describing the sliding mode of the feedback system.
Using this low-pass assumption, the system response can be described by one of a family of sinusoidal waveforms; in this case the system would be characterized by a sine input describing function (SIDF) giving the system response to an input consisting of a sine wave of amplitude A and frequency . This SIDF is a modification of the transfer function used to characterize linear systems. In a quasi-linear system, when the input is a sine wave, the output will be a sine wave of the same frequency but with a scaled amplitude and shifted phase as given by . Many systems are approximately quasi-linear in the sense that although the response to a sine wave is not a pure sine wave, most of the energy in the output is indeed at the same frequency as the input. This is because such systems may possess intrinsic low-pass or bandpass characteristics such that harmonics are naturally attenuated, or because external filters are added for this purpose. An important application of the SIDF technique is to estimate the oscillation amplitude in sinusoidal electronic oscillators.
Other types of describing functions that have been used are DFs for level inputs and for Gaussian noise inputs. Although not a complete description of the system, the DFs often suffice to answer specific questions about control and stability. DF methods are best for analyzing systems with relatively weak nonlinearities. In addition the higher order sinusoidal input describing functions (HOSIDF), describe the response of a class of nonlinear systems at harmonics of the input frequency of a sinusoidal input. The HOSIDFs are an extension of the SIDF for systems where the nonlinearities are significant in the response.
Caveats
Although the describing function method can produce reasonably accurate results for a wide class of systems, it can fail badly for others. For example, the method can fail if the system emphasizes higher harmonics of the nonlinearity. Such examples have been presented by Tzypkin for bang–bang systems. A fairly similar example is a closed-loop oscillator consisting of a non-inverting Schmitt trigger followed by an inverting integrator that feeds back its output to the Schmitt trigger's input. The output of the Schmitt trigger is going to be a square waveform, while that of the integrator (following it) is going to have a triangle waveform with peaks coinciding with the transitions in the square wave. Each of these two oscillator stages lags the signal exactly by 90 degrees (relative to its input). If one were to perform DF analysis on this circuit, the triangle wave at the Schmitt trigger's input would be replaced by its fundamental (sine wave), which passing through the trigger would cause a phase shift of less than 90 degrees (because the sine wave would trigger it sooner than the triangle wave does) so the system would appear not to oscillate in the same (simple) way.
Also, in the case where the conditions for Aizerman's or Kalman conjectures are fulfilled, there are no periodic solutions by describing function method, but counterexamples with hidden periodic attractors are known. Counterexamples to the describing function method can be constructed for discontinuous dynamical systems when a rest segment destroys predicted limit cycles. Therefore, the application of the describing function method requires additional justification.
References
Further reading
N. Krylov and N. Bogolyubov: Introduction to Nonlinear Mechanics, Princeton University Press, 1947
A. Gelb and W. E. Vander Velde: Multiple-Input Describing Functions and Nonlinear System Design, McGraw Hill, 1968.
James K. Roberge, Operational Amplifiers: Theory and Practice, chapter 6: Non-Linear Systems, 1975; free copy courtesy of MIT OpenCourseWare 6.010 (2013); see also (1985) video recording of Roberge's lecture on describing functions
P.W.J.M. Nuij, O.H. Bosgra, M. Steinbuch, Higher Order Sinusoidal Input Describing Functions for the Analysis of Nonlinear Systems with Harmonic Responses, Mechanical Systems and Signal Processing, 20(8), 1883–1904, (2006)
External links
Electrical Engineering Encyclopedia: Describing Functions
Nonlinear control
Hidden oscillation |
picoJava is a microprocessor specification dedicated to native execution of Java bytecode without the need for an interpreter or just-in-time compilation. The aim is to speed bytecode execution up by up to 20 times, compared to standard Intel CPU with a Java virtual machine.
GNU Compiler Collection has been available until version 3.2.3 as machine definition 'pj,' probably first patch was for version 2.9.
GNU Binutils is still available as machine definition 'pj,' as of Binutil version 2.28. GNU Debugger was once implemented, but code might be lost. Sun Microsystems provided instruction set simulator worked with GDB as SCSL open source code.
This approach results in the fastest Java runtime performance with a small memory footprint and competitive performance on code not written in the Java language.
The picoJava specification does not include any memory or I/O interface logic, so that developers can add their own logic to customize memory and an interface.
Products
picoJava was originally designed to be used in consumer electronic products that run Java applications.
Sun Microsystems never released a product based on this technology; however, Sun have licensed the technology to companies such as Fujitsu, NEC and Siemens. The Verilog code of picoJava was later released under SCSL open source code, but the download page is currently not available.
In 2000 Fujitsu released the J-Starter Kit, a development system featuring a picoJava Architecture processor.
The open-source version of picoJava has been implemented in an FPGA.
See also
Jazelle
MAJC
Notes
References
McGhan, Harlan; O’Connor, Mike (October 1998). "PicoJava: A Direct Execution Engine For Java Bytecode". Computer, Volume 31, Issue 10: pp. 22–30.
O’Connor, J. Michael; Tremblay, Marc (March/April 1997). "picoJava-I: The Java Virtual Machine in Hardware". IEEE Micro, Volume 17, Issue 2: pp. 45–53.
Hangal, Sudheendra; O'Connor, J. Michael (May/June 1999). "Performance analysis and validation of the picoJava processor." IEEE Micro, Volume 19, Issue 3.
External links
picoJava at Sun Community Source Licensing (SCSL)
Release announcement (Fujitsu)
Java virtual machine |
Integrated circuits are put into protective packages to allow easy handling and assembly onto printed circuit boards and to protect the devices from damage. A very large number of different types of package exist. Some package types have standardized dimensions and tolerances, and are registered with trade industry associations such as JEDEC and Pro Electron. Other types are proprietary designations that may be made by only one or two manufacturers. Integrated circuit packaging is the last assembly process before testing and shipping devices to customers.
Occasionally specially-processed integrated circuit dies are prepared for direct connections to a substrate without an intermediate header or carrier. In flip chip systems the IC is connected by solder bumps to a substrate. In beam-lead technology, the metallized pads that would be used for wire bonding connections in a conventional chip are thickened and extended to allow external connections to the circuit. Assemblies using "bare" chips have additional packaging or filling with epoxy to protect the devices from moisture.
Through-hole packages
Through-hole technology uses holes drilled through the printed circuit board (PCB) for mounting the components. The component has leads that are soldered to pads on the PCB to electrically and mechanically connect them to the PCB.
Surface mount
Chip on board is a packaging technique that directly connects a die to a PCB, without an interposer or lead frame.
Chip carrier
A chip carrier is a rectangular package with contacts on all four edges. Leaded chip carriers have metal leads wrapped around the edge of the package, in the shape of a letter J. Leadless chip carriers have metal pads on the edges. Chip carrier packages may be made of ceramic or plastic and are usually secured to a printed circuit board by soldering, though sockets can be used for testing.
Pin grid arrays
Flat packages
Small outline packages
A small outline integrated circuit (SOIC) is a surface-mounted integrated circuit (IC) package which occupies an area about 30–50% less than an equivalent dual in-line package (DIP), with a typical thickness being 70% less. They are generally available in the same pin-outs as their counterpart DIP ICs.
Chip-scale packages
According to IPC's standard J-STD-012, Implementation of Flip Chip and Chip Scale Technology, in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1 mm. Chip-scale package
Ball grid array
Ball grid array (BGA) uses the underside of the package to place pads with balls of solder in grid pattern as connections to PCB.
Transistor, diode, small-pin-count IC packages
MELF: Metal electrode leadless face (usually for resistors and diodes)
SOD: Small-outline diode.
SOT: Small-outline transistor (also SOT-23, SOT-223, SOT-323).
TO-XX: wide range of small pin count packages often used for discrete parts like transistors or diodes.
TO-3: Panel-mount with leads
TO-5: Metal can package with radial leads
TO-18: Metal can package with radial leads
TO-39
TO-46
TO-66: Similar shape to the TO-3 but smaller
TO-92: Plastic-encapsulated package with three leads
TO-99: Metal can package with eight radial leads
TO-100
TO-126: Plastic-encapsulated package with three leads and a hole for mounting on a heat sink
TO-220: Through-hole plastic package with a (usually) metal heat sink tab and three leads
TO-226
TO-247: Plastic-encapsulated package with three leads and a hole for mounting on a heat sink
TO-251: Also called IPAK: SMT package similar to the DPAK but with longer leads for SMT or TH mounting
TO-252: (also called SOT428, DPAK): SMT package similar to the DPAK but smaller
TO-262: Also called I2PAK: SMT package similar to the D2PAK but with longer leads for SMT or TH mounting
TO-263: Also called D2PAK: SMT package similar to the TO-220 without the extended tab and mounting hole
TO-274: Also called Super-247: SMT package similar to the TO-247 without the mounting hole
Dimension reference
Surface-mount
C Clearance between IC body and PCB
H Total height
T Lead thickness
L Total carrier length
LW Lead width
LL Lead length
P Pitch
Through-hole
C Clearance between IC body and board
H Total height
T Lead thickness
L Total carrier length
LW Lead width
LL Lead length
P Pitch
WB IC body width
WL Lead-to-lead width
Package dimensions
All measurements below are given in mm. To convert mm to mils, divide mm by 0.0254 (i.e., 2.54 mm / 0.0254 = 100 mil).
C Clearance between package body and PCB.
H Height of package from pin tip to top of package.
T Thickness of pin.
L Length of package body only.
LW Pin width.
LL Pin length from package to pin tip.
P Pin pitch (distance between conductors to the PCB).
WB Width of the package body only.
WL Length from pin tip to pin tip on the opposite side.
Dual row
Quad rows
LGA
Multi-chip packages
A variety of techniques for interconnecting several chips within a single package have been proposed and researched:
SiP (system in package)
PoP (package on package)
3D-SICs, Monolithic 3D ICs, and other three-dimensional integrated circuits
Multi-chip module
WSI (wafer-scale integration)
Proximity communication
By terminal count
Surface-mount components are usually smaller than their counterparts with leads, and are designed to be handled by machines rather than by humans. The electronics industry has standardized package shapes and sizes (the leading standardisation body is JEDEC).
The codes given in the chart below usually tell the length and width of the components in tenths of millimeters or hundredths of inches. For example, a metric 2520 component is 2.5 mm by 2.0 mm which corresponds roughly to 0.10 inches by 0.08 inches (hence, imperial size is 1008). Exceptions occur for imperial in the two smallest rectangular passive sizes. The metric codes still represent the dimensions in mm, even though the imperial size codes are no longer aligned. Problematically, some manufacturers are developing metric 0201 components with dimensions of , but the imperial 01005 name is already being used for the package. These increasingly small sizes, especially 0201 and 01005, can sometimes be a challenge from a manufacturability or reliability perspective.
Two-terminal packages
Rectangular passive components
Mostly resistors and capacitors.
Tantalum capacitors
Aluminum capacitors
Small-outline diode (SOD)
Metal electrode leadless face (MELF)
Mostly resistors and diodes; barrel shaped components, dimensions do not match those of rectangular references for identical codes.
DO-214
Commonly used for rectifier, Schottky, and other diodes.
Three- and four-terminal packages
Small-outline transistor (SOT)
Other
DPAK (TO-252, SOT-428): Discrete Packaging. Developed by Motorola to house higher powered devices. Comes in three or five-terminal versions.
D2PAK (TO-263, SOT-404): Bigger than the DPAK; basically a surface mount equivalent of the TO220 through-hole package. Comes in 3, 5, 6, 7, 8 or 9-terminal versions.
D3PAK (TO-268): Even larger than D2PAK.
Five- and six-terminal packages
Small-outline transistor (SOT)
Packages with more than six terminals
Dual-in-line
Flatpack was one of the earliest surface-mounted packages.
Small-outline integrated circuit (SOIC): dual-in-line, 8 or more pins, gull-wing lead form, pin spacing 1.27 mm.
Small-outline package, J-leaded (SOJ): The same as SOIC except J-leaded.
Thin small-outline package (TSOP): thinner than SOIC with smaller pin spacing of 0.5 mm.
Shrink small-outline package (SSOP): pin spacing of 0.65 mm, sometimes 0.635 mm or in some cases 0.8 mm.
Thin shrink small-outline package (TSSOP).
Quarter-size small-outline package (QSOP): with pin spacing of 0.635 mm.
Very small outline package (VSOP): even smaller than QSOP; 0.4-, 0.5-, or 0.65-mm pin spacing.
Dual flat no-lead (DFN): smaller footprint than leaded equivalent.
Quad-in-line
Plastic leaded chip carrier (PLCC): square, J-lead, pin spacing 1.27 mm
Quad flat package (QFP): various sizes, with pins on all four sides
Low-profile quad flat-package (LQFP): 1.4 mm high, varying sized and pins on all four sides
Plastic quad flat-pack (PQFP), a square with pins on all four sides, 44 or more pins
Ceramic quad flat-pack (CQFP): similar to PQFP
Metric quad flat-pack (MQFP): a QFP package with metric pin distribution
Thin quad flat-pack (TQFP), a thinner version of LQFP
Quad flat no-lead (QFN): smaller footprint than leaded equivalent
Leadless chip carrier (LCC): contacts are recessed vertically to "wick-in" solder. Common in aviation electronics because of robustness to mechanical vibration.
Micro leadframe package (MLP, MLF): with a 0.5 mm contact pitch, no leads (same as QFN)
Power quad flat no-lead (PQFN): with exposed die-pads for heatsinking
Grid arrays
Ball grid array (BGA): A square or rectangular array of solder balls on one surface, ball spacing typically
Fine-pitch ball grid array (FBGA): A square or rectangular array of solder balls on one surface
Low-profile fine-pitch ball grid array (LFBGA): A square or rectangular array of solder balls on one surface, ball spacing typically 0.8 mm
Micro ball grid array (μBGA): Ball spacing less than 1 mm
Thin fine-pitch ball grid array (TFBGA): A square or rectangular array of solder balls on one surface, ball spacing typically 0.5 mm
Land grid array (LGA): An array of bare lands only. Similar to in appearance to QFN, but mating is by spring pins within a socket rather than solder.
Column grid array (CGA): A circuit package in which the input and output points are high-temperature solder cylinders or columns arranged in a grid pattern.
Ceramic column grid array (CCGA): A circuit package in which the input and output points are high-temperature solder cylinders or columns arranged in a grid pattern. The body of the component is ceramic.
Lead-less package (LLP): A package with metric pin distribution (0.5 mm pitch).
Non-packaged devices
Although surface-mount, these devices require specific process for assembly.
Chip-on-board (COB), a bare silicon chip, that is usually an integrated circuit, is supplied without a package (which is usually a lead frame overmolded with epoxy) and is attached, often with epoxy, directly to a circuit board. The chip is then wire bonded and protected from mechanical damage and contamination by an epoxy "glob-top".
Chip-on-flex (COF), a variation of COB, where a chip is mounted directly to a flex circuit. Tape-automated bonding process is also a chip-on-flex process as well.
Chip-on-glass (COG), a variation of COB, where a chip, typically a liquid crystal display (LCD) controller, is mounted directly on glass.
Chip-on-wire (COW), a variation of COB, where a chip, typically a LED or RFID chip, is mounted directly on wire, thus making it a very thin and flexible wire. Such wire may then be covered with cotton, glass or other materials to make into smart textiles or electronic textiles.
There are often subtle variations in package details from manufacturer to manufacturer, and even though standard designations are used, designers need to confirm dimensions when laying out printed circuit boards.
See also
Surface-mount technology
Three-dimensional integrated circuit
Interposer
IPC (electronics)
List of chip carriers
List of electronics package dimensions
Redistribution layer
Small-outline transistor
Wafer-level packaging
References
External links
JEDEC JEP95 official list of all (over 500) standard electronic packages
Fairchild Index of Package Information
An illustrated listing of different package types, with links to typical dimensions/features of each
Intersil packaging information
ICpackage.org
Solder Pad Layout Dimensions
International Microelectronics And Packaging Society
Semiconductor packages
Electronics lists |
OpenJPEG is an open-source library to encode and decode JPEG 2000 images. As of version 2.1 released in April 2014, it is officially conformant with the JPEG 2000 Part-1 standard. It was subsequently adopted by ImageMagick instead of JasPer in 6.8.8-2 and approved as new reference software for this standard in July 2015. OpenJPEG is a fork of libj2k, a JPEG-2000 codec library written by David Janssens during his master thesis at University of Louvain (UCLouvain) in 2001.
Unlike JasPer, another open-source JPEG 2000 implementation, OpenJPEG fully respects the JPEG 2000 specification and can compress and decompress lossless 16-bit images.
See also
Grok (JPEG 2000)
Kakadu library
References
External links
Communications and Remote Sensing Lab
Digital Signal Processing Lab (DSPLab)
JPEG
C (programming language) libraries
Graphics libraries |
Steven McGeady is a former Intel executive best known as a witness in the Microsoft antitrust trial. His notes and testimony contained colorful quotes by Microsoft executives threatening to "cut off Netscape's air supply" and Bill Gates' guess that "this antitrust thing will blow over". Attorney David Boies said that McGeady's testimony showed him to be "an extremely conscientious, capable and honest witness", while Microsoft portrayed him as someone with an "axe to grind". McGeady left Intel in 2000, but later again gained notoriety for defending his former employee Mike Hawash after his arrest on federal terrorism charges. From its founding in 2002 until its sale in November 2013, he was Chairman of Portland-based healthcare technology firm ShiftWise. He is a member of the Reed College Board of Trustees, the Portland Art Museum Board of Trustees, and the PNCA Board of Governors, and lives in Portland, Oregon.
Early life
Steven McGeady was born in Baltimore, Maryland. His father was a manager for Bethlehem Steel. After high school in Michigan City, Indiana he briefly attended Purdue University. Then in 1976, he enrolled at Reed College in Portland, Oregon. While attending Reed College from 1976 to 1980, he studied Physics and Philosophy but did not graduate. The majority of his time was occupied at the school's computer center where he and friends would experiment with a Digital Equipment Corporation (DEC) PDP-11/70 computer donated by Howard Vollum, the founder of Tektronix. Reed's computer was the first in the Northwest to run the Unix operating system, allowing McGeady to become an early developer in that environment.
After college, McGeady was a software engineering manager at Ann Arbor Terminals and Oregon based Tektronix. In 1985 he joined Intel, and in 1991 he co-founded the Intel Architecture Labs in Hillsboro. In 1993, he was promoted to a vice president position at the company.
Intel
At the time of his departure in June 2000, McGeady was Vice President of Intel's New Business Group. During 15 years at Intel, he led a variety of software, marketing, and investment initiatives for Intel, including the i960 RISC microprocessor software development, Intel's digital video and multimedia research, Intel's first Internet development group, and a group focused on Internet-based healthcare delivery.
McGeady was a co-founder of the Intel Architecture Labs, a research and development group focused on advancing the personal-computer platform. McGeady ran the software, multimedia, data security, and Internet programs within this group for most of the 1990s. His group developed Intel's ProShare video-conferencing technology, the Indeo video compression technology, and Intel's Display Control Interface and VxD graphics software, later licensed to Microsoft to form the core of DirectX. His research group worked with the MIT Media Lab, Xerox PARC, and other groups, and developed early prototypes of digital video recorders (DVRs), video broadcast servers, and other technologies.
As manager of the i960 software development tools team from 1986–1996, McGeady was an early developer and promoter of open-source software, beginning with Richard Stallman's GNU C compiler and tools. McGeady wrote the i960 target for GNU Compiler Collection (gcc) and led the team that developed a suite of tools including a globally optimizing, trace-driven optimizer for gcc and the first GNU Debugger (gdb) port to a remote, stand-alone system. He hired Cygnus Support to integrate those changes into the mainline GNU tools and to improve the tools' ability to deal with many object file formats.
McGeady was Vice-President of Intel's Multimedia, Communications, and Internet activities from 1990 through 1996, where he led the development of the first desktop video-compression software for the PC, Intel's early implementations of multimedia network broadcast protocols, the first products to combine television and web pages, online virtual communities, the Java language, and data security infrastructure.
As a software engineer and developer, McGeady was often a minority voice at hardware-dominated Intel. In 1996 he was asked by then-CEO Andy Grove to take a job as Grove's assistant and is the only known person to turn the job down. Grove later said that he and Intel would have grasped the importance of the Internet to the company more quickly had McGeady taken the job. McGeady had a less positive relationship with succeeding CEO Craig Barrett, reportedly telling Barrett to "pound sand" when Barrett instructed him not to testify in the Microsoft case.
Microsoft trials
In 1998, McGeady was a witness for the US Department of Justice in the U.S. vs. Microsoft antitrust case, where he testified about Microsoft's attempts to control Intel's software efforts as well as their behavior toward Netscape and Sun's Javasoft. He was the only executive from the PC industry to testify for the government. McGeady testified that Microsoft opposed Intel's 1995 work on a new technology called Native Signal Processing, which would have used instructions from Intel's chips, rather than software code from Microsoft, to run multimedia and communications programs more quickly.
McGeady testified for the government and against Microsoft despite pressure from inside Intel. Intel's then-COO Craig Barrett instructed McGeady not to cooperate with Department of Justice attorneys, but "He [told] Barrett to go stuff it".
McGeady also claimed in his testimony that Microsoft Vice-President Paul Maritz had described, in a meeting at Intel, Microsoft's plan to "embrace, extend, [and] extinguish" the HTML standard until it would be incompatible with the Netscape browser. While this term had some currency before his 1998 testimony, this was its first prominent public exposure. Documents presented by the government showed Microsoft was concerned about McGeady: "Steve McGeady remains an issue for us. He is a champion of Java and a believer that the day of bloatware is over", wrote Microsoft VP Paul Maritz in an email to Bill Gates. "He has more IQ than most [people at Intel]".
In November 1998, McGeady testified that Microsoft leveraged its monopoly power in Windows to impede Intel's ability to compete with Microsoft in areas involving system software and influence of OEMs:
McGeady testified that Microsoft feared competition from Intel's software development: At an August 2, 1995 meeting Bill Gates allegedly threatened to terminate Windows support for Intel's new microprocessors unless they were able to "get alignment" between Intel and MS on Intel's Internet and communications software programs, and Gates allegedly told Andy Grove to shut down the Intel Architecture Labs, the organization driving Intel's Internet program.
McGeady testified that Microsoft was upset that Intel "shifting the software boundary" without Microsoft's permission: IAL's development of Native Signal Processing (NSP) program caused this concern. NSP was a layer of software that interfaced with both the Windows OS and the hardware in order to support real-time audio, real-time video, and 3D graphics. According to McGeady, NSP threatened Microsoft because it was software at the operating system level, while Microsoft believed they "owned software to the metal", (i.e., to the hardware level). (10AM17, 12PM13) Ultimately, Andy Grove admitted that Intel "caved" by retracting NSP.
Microsoft was concerned about IAL: Gates allegedly said regarding Intel Architecture Labs: "Having 700 software engineers running around in the industry is an okay thing as long as Microsoft knows what they're doing first". According to McGeady, they did not want to relinquish control over any application interfaces to Intel. To take advantage of multimedia hardware, Intel was writing device drivers that allowed application developers direct control of (e.g.) graphics and video devices. To prevent this Microsoft threatened to continue bad-mouthing IAL's software and to withhold support for Intel's MMX microprocessor.
McGeady testified that Microsoft used its monopoly power in Windows to restrict support for Netscape and Java, and to their plans to compete with Netscape through predatory pricing, through the leveraging of their Windows OS monopoly, and through the creation of incompatible HTML standards:
Netscape: McGeady testified that Microsoft generally discouraged Intel from working with Netscape, and that Gates allegedly urged Grove to push Intel's internal information technology group away from Netscape's server toward Microsoft's IIS, and stressed that it was "very important" that Intel "NOT ever publicly say they are standardizing on Netscape browsers". McGeady testified to Microsoft's three-prong strategy to defeat Netscape: they allegedly stated that they would "cut off Netscape's air supply" by giving away Internet Explorer for free, preventing Netscape from deriving any revenue from its browser; that Microsoft asserted they would "fight with the OS and the apps arm", meaning they would create dependencies between Windows and the browser that would create advantages for their browser over Netscape's; and MS's professed strategy of "embrace, extend, extinguish", planning to "extend" the HTML standard to the point where it would be incompatible with the Netscape browser.
Java: McGeady testified that Microsoft made it clear to Intel that support for Java would be a "show stopper" in Intel's relationship with Microsoft, threatening to terminate cooperation that Intel required for new microprocessors. Microsoft allegedly proposed that Intel help them prevent the Java component model from becoming a de facto standard by developing a Java system incompatible with Sun's, defeating Java's "write once, run anywhere" capabilities, and tying Java to Windows. Microsoft would distribute this Java virtual machine as part of Internet Explorer, a variant of MS's "embrace, extend, extinguish" strategy. When Microsoft learned that McGeady's group at Intel had implemented its own Java VM and multimedia class libraries that ran very fast on the Intel architecture, Microsoft became very upset. McGeady testified that Microsoft pressed Intel to stop this work.
The DoJ made four major arguments based on McGeady's testimony:
Intel and its software development effort were hampered by Microsoft's bully tactics;
Microsoft used Intel against Netscape in the "Browser Wars";
McGeady was an expert witness on software standards, innovation and competition; and
McGeady felt Microsoft hampered Java development.
Microsoft, in their response to McGeady's testimony, made the point that his testimony contained several pro-Microsoft threads and that Intel practiced similar cross-product subsidization, distributing free Intel Architecture Labs software funded by microprocessor revenues. They also claimed that Microsoft's influence over Intel and its microprocessors was unrelated to the downstream software segment.
Cross-examination of McGeady revealed conflicting interpretations of many Microsoft/Intel meetings, differing reasons for Intel's decisions, and for McGeady's anti-Microsoft bias:
Microsoft defended its attempts to coordinate strategy with Intel and tried to dispel the bully image;
Microsoft presented reasons for the discontinuation of Intel's Native Signal Processing initiative;
Microsoft highlighted Intel practices that resemble Microsoft's alleged anti-competitive behavior;
Microsoft defended its Java program; and
Microsoft aggressively attacked McGeady to discredit him as a witness.
McGeady's notes suggested that portions of his testimony could be considered embellishments or stories heard in other contexts, and he was frequently forced to suggest that he had a recollection of meetings and conversations superior to that of other Intel officials, as well as Netscape officers. Microsoft revealed Intel documents that painted McGeady as a "prima donna" who was criticized for his department's belligerence toward Microsoft.
Microsoft claimed that McGeady's actions suggested that he considered himself above Intel policy and an extra-corporate defender of truth and justice in the Internet world, and McGeady openly suggested that Intel's interference with Microsoft would aid the industry. McGeady admitted leaking confidential information to The New York Times journalist John Markoff and met with Netscape's Jim Clark to keep Netscape from being complacent about the threat from Microsoft. Documents show McGeady envisioning entrapping Microsoft in an antitrust suit, and later he indirectly volunteered to testify against Microsoft.
McGeady was called again to testify in the 2001 remedy phase of the Microsoft trial.
Other activities
During 1996/97, McGeady was a visiting researcher at the MIT Media Lab, pursuing research on emergent and self-organizing behavior in computer networks. During this time he was a keynote speaker at the first Harvard Conference on the Internet and Society. His speech from the event, "The Digital Reformation: Freedom, Risk, Responsibility" was reprinted in the Harvard Journal of Law and Technology, and is credited by some as formulating early theories regarding what became social media.
During 1997 and 1998, McGeady was a member of the National Research Council Computer Science and Technology Board Committee on Information Systems Trustworthiness, and is a co-author of its book on the subject.
Mike Hawash case
McGeady entered the news again in 2003 because of his defense of his former Intel employee Mike Hawash who was arrested at Intel in early 2003. McGeady organized a defense fund and protested Hawash's 6-week incommunicado detention without charge. Hawash ultimately pleaded guilty to conspiring to aid the Taliban in fighting against U.S. forces in Afghanistan, and received a reduced sentence in the so-called Portland Seven case in exchange for testifying against some of his co-conspirators.
References
External links
McGeady: Microsoft threats killed Intel's multimedia software twice
1957 births
Living people
American computer programmers
Businesspeople from Portland, Oregon
Purdue University alumni
Reed College alumni
Intel people
Pacific Northwest College of Art
Tektronix people |
The University of Hagen (, informally often referred to as FU Hagen) is a public research university that is primarily focused on distance teaching. While its main campus is located in Hagen, North Rhine-Westphalia, Germany, the university maintains more than 50 study and research centers in Germany and throughout Europe. According to the Federal Statistical Office of Germany, it is Germany's second-largest university. The university was founded in 1974 as a public research university by the state Nordrhein-Westfalen and began its research and teaching activities in 1975. It was founded following the idea of UK's Open University to provide higher and continuing education opportunities through a distance education system in Germany.
The university awards the same qualifications as other German on-campus universities and maintains the same requirements. Initially, the university had only three faculties with 1,304 full and part-time students, but today the university has developed into Germany's leading institution for distance education and is the only full university in that field with a student body of 83,536 students in the summer term of 2013 and 86,889 students in the winter term 2013/14. Besides the substantial number of off-campus students, a considerable number of full-time postgraduate research students as well as more than 1,800 members of academic and research staff are based on the University of Hagen's main campus in Hagen.
The faculties of the University of Hagen award undergraduate, graduate and postdoctoral degrees and enable habilitation. All the degrees awarded by the University of Hagen are equivalent to those awarded by traditional German universities. The University of Hagen awards degrees and does research in the fields of business administration and economics, mathematics, computer science, law, psychology, cultural studies and political science. The university has produced many notable alumni in the fields of law, economics, business and politics, among them two Gottfried Wilhelm Leibniz Prize winners, 1 Gossen Prize laureate, at least 25 university professors, numerous members of the German parliament, and the former Foreign Minister and Vice Chancellor of Germany, Guido Westerwelle.
The University of Hagen is a member of the European University Association (EUA), European Association of Distance Teaching Universities (EADTU) and it is accredited by ACQUIN, FIBAA (Foundation for International Business Administration Accreditation) as well as AQAS (Agentur für Qualitätssicherung durch Akkreditierung von Studiengängen).
History
Lifelong learning, further education concurrent with work, along with the necessity to relieve the overcrowded on-campus universities have been important topics in the early seventies of the last century. All this inspired the then minister of Higher Education and Research of the state North Rhine Westphalia to establish a public research university at Hagen dedicated to distance teaching.
Under the NRW-Foundation Law of 1 December 1974 the "pioneers" from academia and administration had only ten months for preparing the new university, so that 1,300 students could embark on their studies from winter academic term 1975/76. The two academic departments of economics and mathematics were soon joined by business administration, education, cultural sciences, social sciences and humanities, as well as electrical engineering, information technology, law and computer science. After some restructuring, these subject areas have been organised into five faculties. The first study centres in North Rhine - Westphalia started operating simultaneously with the FernUniversität,.
According to the Bologna Process every course offered by the university has been transformed to bachelor's and master's degrees. The transformation was finished in 2010. Due to the transformation a sharp rise in the number of students was observable, e.g. 3,400 new students seeking a bachelor's degree in psychology enrolled in 2009.
Organisation and administration
Governance
The Rectorate is the 'executive body' of the university, headed by rector Helmut Hoyer. The rectorate consists of the chancellor, Regina Zdebel, who is the head of the central administration and responsible for the university's budgeting, and three pro-rectors, who are responsible for international relations, teaching and communication, and research and structure respectively.
The Senate is the 'legislative branch' of the university. The rector and the members of the rectorate are senators ex officio, as are also the deans of the faculties, and the university's equal opportunities officer. Another 20 senators are elected for four-year terms, within the following quotas: eight university professors; four academic staff; four delegates of the student body; and four employees of the university administration.
The University Council is the advisory board to the aforementioned entities. Amongst others its members include many CEOs of German industries, it formerly also included the late President of Germany Johannes Rau.
Faculties
Since a 2006 structural reformation, the university consists of five faculties, which in turn comprise several disciplines, departments, and institutes. As a consequence of the Bologna process, most faculties now offer Bachelor's, Master's, and PhD degrees to comply with the new European degree standard. A notable exception is the undergraduate program in law, from which students still graduate with the Staatsexamen (state examination), a central examination at Master's level held by the State of North Rhine-Westphalia. Each of the faculties is headed by a dean and a faculty council overseeing the research and teaching conducts.
The university is organised into five faculties:
Faculty of Cultural and Social Sciences
Faculty of Mathematics and Computer Science
Faculty of Business Administration and Economics
Faculty of Law
Faculty of Psychology
Campus and study centers
Initially, FernUniversität's departments were housed in rented apartments and buildings located all over Hagen and even outside the city. The development of FernUniversität's campus near the roadways A 45 and A 46 began in 1980 with the first office building Allgemeines Verfügungszentrum (AVZ I). Since the first building constructed several further buildings followed and increased the university campus, among them: The Eugen-Schmalenbach-Building (AVZ II), the Philipp-Reis-Building, the Centre of Technology and Innovation (TGZ), the extension of the University Library, and the new canteen. As more and more university buildings are concentrated on the Campus, it has become easier for the academic staff of different academic areas to cooperate and engage in cross-disciplinary research.
Furthermore, as a distance university, the University of Hagen operates numerous regional and study centers located across Germany and in other European countries, which are an important aspect of the university's blended learning concept. At these regional and study centers, students attend mandatory seminars and preparatory classes for exams, study together with other students, borrow books, and find mentors. Today, the university has more than 50 study centres within Germany and cooperates intensively with several other renowned institutions, such as Karlsruhe Institute of Technology, Goethe University Frankfurt, Johannes Kepler University Linz or the University of Jena to broaden their teaching options and research.
Germany
North Rhine-Westphalia
Bonn (regional center)
Euskirchen
Coesfeld (regional center)
Borken
Herford
Lüdinghausen
Rheine
Hagen (regional center)
Arnsberg
Bottrop
Brilon
Castrop-Rauxel
Neuss (regional center)
Eschweiler
Krefeld
Wesel
Minden
Saarland
Saarbrücken (operated by Saarland University)
Saxony
Leipzig
Thuringia
Erfurt (operated by University of Jena)
Baden-Württemberg
Karlsruhe (operated by Karlsruhe Institute of Technology)
Stuttgart (regional center)
Schwäbisch Gmünd
Villingen-Schwenningen
Bavaria
Munich
Nuremberg
Berlin
Berlin (regional center)
Hamburg
Hamburg (regional center)
Hesse
Frankfurt/Main (operated by Goethe University Frankfurt)
Bad Hersfeld
Lower Saxony
Hannover (regional center)
Other countries
Austria
Bregenz (operated by Johannes Kepler University Linz)
Linz
Steyr
Vienna
Saalfelden
Villach
Switzerland
Zurich (operated by University of Zurich)
Russia
Smolensk
Hungary
Budapest
Latvia
Riga
Academics
The University of Hagen provides the opportunity to study for a PhD on a part-time as distance option, or a full-time on-Campus basis in all of its disciplines offered. The university also offers a range of Master's levels modules such as the MBA, MSc and M.A., as well as the German Staatsexamen for its law degree.
Unlike German campus universities, degree awarding ceremonies at the University of Hagen are not graduation ceremonies as such, but instead University of Hagen graduates normally graduate in absentia at a joint meeting of the university's Council and Senate ("Congregation") which takes place at a meeting entirely separate from the degree ceremony.
Organisation and length of courses
The academic year is divided into two semesters. The winter semester runs from 1 October – 31 March and the summer semester from 1 April – 30 September. Online and self-study courses are held from mid-October to mid-February and mid-April to mid-July. Additionally, the University of Hagen offers presence classes and special seminars, some of which are required to graduate successfully. Students can generally begin their studies in the winter or in the summer semester. The standard time required to finish a Bachelor's degree's course load of 180 ECTS in full-time study is set at six semesters. The overall period of study for an undergraduate degree is divided into two parts: a period of basic study, equalling a course load of four semesters, at the end of which students must sit a formal examination, and a period of advanced study, equalling the course load of two semesters, after which students take their final examinations. Master's degrees, if done as full-time study, usually equalling the course load of four semesters. However, since a large proportion of the student body at the University of Hagen is studying part-time, the regular study time can deviate. The normal duration of PhD programs for full-time students is 6 semesters.
Research
The University of Hagen supports focus- and profile-oriented research. Interdisciplinary and cross-faculty collaboration leads to the grouping together of competencies and to the formation of competitive research focal points. At the same time, basic and applied research is the basis for promoting the new generation of academics.
Research Institutes
FIRM – Forschungsinstitut für rechtliches Informationsmanagement (Research Institute for Legal Informationmanagement)
FTB – Forschungsinstitut Technologie und Behinderung (Research Center for Technology and Disabilities)
FTK – Forschungsinstitut für Telekommunikation (Research Institute for Telecommunication)
HIMS – Hagener Institut für Managementstudien e.V. (Hagener Institute for Management Studies)
IKS – Institut für kooperative Systeme (Institute for Cooperative Systems)
IWW – Institut für Wirtschaftswissenschaftliche Forschung und Weiterbildung GmbH (Institute for Economic Research and Training)
TestDaF-Institut (Institute for Market Research)
Spin-offs
ISL – Internet Sicherheitslösungen GmbH (Internet Security Solutions Ltd.)
MMK – MultiMedia Kommunikationssysteme GmbH (MultiMedia Communication Systems Ltd.)
Peperoni Mobile & Internet Software GmbH
Partnerships and cooperations
In the fields of research and development the FU Hagen's faculties and chairs hold a wide array of diverse cooperations with renowned international scientific institutions, companies, associations (like the Kurt Haertel Institute for Intellectual Property) as well as public institutions.
Furthermore, exchange of technology and knowledge is conducted through a variety of cooperation projects between science and industry, ranging from final theses by arrangement with the individual employer to commissioned research. Moreover, joint development of academic further education programs with companies, associations and scientific institutions contributes to the interlinking of academia and practice.
Ranking and reputation
The special status of the FernUniversität Hagen as a university for distance learning mostly excludes the university from being ranked in general rankings. Only the renowned CHE ranking included the university in its university ranking of 2005 and evaluated the quality of the subjects Economics, Sociology and Business Administration. The departments of sociology and business administration received stellar placements – both research intensity and quality were emphasised to be in line with those of other top placed departments of on-campus universities.
Student life
Student body
The University of Hagen had a student body of 83,536 students in the summer term of 2013. The average age of the matriculated students was 32 years. About 80% of the students at the FU Hagen are in full or part-time employment and 19% have already received a first academic degree.
Notable alumni
Oliver Bierhoff, retired German football striker and general manager of the Germany national football team
Ijad Madisch, physician and co-founder of ResearchGate
Mohammed bin Rashid Al Maktoum, Prime Minister of the United Arab Emirates and holder of an honorary doctorate from FU Hagen
Heinz-Willi Mölders, board member of RWE (2005-today)
Ursula Mueller, United Nations Assistant Secretary-General for Humanitarian Affairs and Deputy Emergency Relief Coordinator in the Office for the Coordination of Humanitarian Affairs
Bernd Lucke, German economist and Founder of the German party AfD
Roman Inderst, German economist
Stefan Kirsten, CFO of Deutsche Annington (2011-today)
Patrick Dahmen, Board member of AXA, Germany (2007-today)
Michael Klug, CFO of Sony Music Entertainment, Germany (2011-today)
Jens Spahn, Member of the German Bundestag
Oliver Kahn, German football goalkeeper
Richard Nagorny, CFO of AstraZeneca, Germany (2005–2010)
Theo Lieven, Founder of Vobis Data Computer
Anne Schäfer, tennis player
Ulla Schmidt, German politician
Stefan Schulz, Member of the supervisory board of SAP (2002–2017)
Dirk Mausbeck, Board member of EnBW
Guido Westerwelle, former German Minister of Foreign Affairs, Vice Chancellor of Germany from 2009 to 2011
See also
Education in Germany
Hagen
North Rhine-Westphalia
List of universities in Germany
List of business schools in Europe
List of early modern universities in Europe
Notes and references
External links
Map of the regional and study centers
Universities and colleges established in 1974
Hagen
1974 establishments in West Germany
Distance education institutions based in Germany
Universities and colleges in North Rhine-Westphalia |
The W65C21S is a very flexible Peripheral Interface Adapter (PIA) for use with WDC’s 65xx and other 8-bit microprocessor families. It is produced by Western Design Center (WDC).
The W65C21S provides programmed microprocessor control of up to two peripheral devices (Port A and Port B). Peripheral device control is accomplished through two 8-bit bidirectional I/O Ports, with individually designed Data Direction Registers. The Data Direction Registers provide selection of data flow direction (input or output) at each respective I/O Port. Data flow direction may be selected on a line-by-line basis with intermixed input and output lines within the same port. The “handshake” interrupt control feature is provided by four peripheral control lines. This capability provides enhanced control over data transfer functions between the microprocessor and peripheral devices, as well as bidirectional data transfer between W65C21S Peripheral Interface Adapters in multiprocessor systems.
The PIA interfaces to the 65xx microprocessor family with a reset line, a ϕ2 clock line, a read/write line, two interrupt request lines, two register select lines, three chip select lines and an 8-bit bidirectional data bus. The PIA interfaces to the peripheral devices with four interrupt/control lines and two 8-bit bidirectional buses.
The W65C21S PIA is organized into two independent sections referred to as the A Side and the B Side. Each section consists of Control Register (CRA, CRB), Data Direction Register (DDRA, DDRB), Output Register (ORA, ORB), Interrupt Status Control (ISCA, ISCB) and the buffers necessary to drive the Peripheral Interface buses. Data Bus Buffers (DBB) interface data from the two sections to the data bus, while the Date Input Register (DIR) interfaces data from the DBB to the PIA registers. Chip Select and RWB control circuitry interface to the processor bus control lines.
Features of the W65C21S
Low power CMOS N-well silicon gate technology
High speed/Low power replacement for Motorola / Rockwell / AMI / *MOS Technology / MOSTEK / HITACHI / ST Microelectronics / GTE / CMD 6520, 6521, 6820, 6821 PIA’s
Two 8-bit bidirectional I/O ports with individual data direction control.
Automatic “Handshake” control of data transfers
Two interrupts (one for each port) with program control
Static to 14 MHz operation, with high speed Port A, CA2 outputs.
Industrial temperature range
40 Pin Plastic Dip and 44 Pin Plastic PLCC versions
5 volt ± 10% supply requirements
Compatible with the 65xx and 68xx family of microprocessors
External links
W65C21S Datasheet
Input/output integrated circuits |
In an integrated circuit, a signal can couple from one node to another via the substrate. This phenomenon is referred to as substrate coupling or substrate noise coupling.
The push for reduced cost, more compact circuit boards, and added customer features has provided
incentives for the inclusion of analog functions on primarily digital MOS integrated circuits (ICs) forming
mixed-signal ICs. In these systems, the speed of digital circuits is constantly increasing, chips are
becoming more densely packed, interconnect layers are added, and analog resolution is increased. In addition, recent increase in wireless applications and its growing market are introducing a new set of aggressive design goals for realizing mixed-signal systems.
Here, the designer integrates radio frequency
(RF) analog and base band digital circuitry on a single chip.
The goal is to make single-chip radio frequency
integrated circuits (RFICs) on silicon, where all the blocks are fabricated on the same chip.
One of the advantages of this integration is low power dissipation for portability due to a reduction in the number of package pins and associated bond wire capacitance.
Another reason that an integrated solution offers lower power consumption is that routing high-frequency signals off-chip often requires a 50Ω impedance match, which can result in higher power dissipation.
Other advantages include improved high-frequency performance due to reduced package interconnect parasitics, higher system reliability, smaller package count, and higher integration of RF components with VLSI-compatible digital circuits.
In fact, the single-chip transceiver is now a reality.
The design of such systems, however, is a complicated task. There are two main challenges in realizing
mixed-signal ICs. The first challenging task, specific to RFICs, is to fabricate good on-chip passive elements
such as high-Q inductors. The second challenging task, applicable to any mixed-signal IC and the subject
of this chapter, is to minimize noise coupling between various parts of the system to avoid any malfunctioning
of the system.
In other words, for successful system-on-chip integration of mixed-signal systems, the
noise coupling caused by nonideal isolation must be minimized so that sensitive analog
circuits and noisy digital circuits can effectively coexist, and the system operates correctly.
To elaborate, note that in mixed-signal
circuits, both sensitive analog circuits and high-swing high-frequency noise injector digital circuits may be
present on the same chip, leading to undesired signal coupling between these two types of circuit via the conductive substrate.
The reduced distance between these circuits, which is the result of constant technology scaling (see Moore's law and the International Technology Roadmap for Semiconductors),
exacerbates the coupling.
The problem is severe, since signals of different nature and strength interfere,
thus affecting the overall performance, which demands higher clock rates and greater analog
precisions.
The primary mixed-signal noise coupling problem comes from fast-changing digital signals
coupling to sensitive analog nodes.
Another significant cause of undesired signal
coupling is the crosstalk between analog nodes themselves owing to
high-frequency/high-power analog
signals.
One of the media through which mixed-signal noise coupling occurs is the substrate.
Digital operations cause fluctuations in the underlying substrate voltage, which spreads
through the common substrate causing variations in the substrate potential of sensitive
devices in the analog section.
Similarly, in the case of crosstalk between analog nodes, a signal can couple from one
node to another via the substrate.
This phenomenon is referred to as substrate coupling or substrate noise coupling.
Modelling, analysis, and verification of mixed signal coupling
There is a sizeable literature on substrate, and mixed signal coupling. Some of the most common topics are:
Differentiating between the random noise inherent to electronic devices and the deterministic noise generated by circuits.
Examining the physical phenomena responsible for the creation of undesired signals in a digital circuit and the mechanisms of their transport to other parts of the system. The substrate is the most common coupling mechanism, but capacitive coupling, mutual inductance, and coupling through power supplies are also analyzed.
Comparing various modeling approaches and simulation techniques. There are many possible models for digital noise generation, the substrate impedance network, and the sensitivity of the (unintended) receiver. The chosen techniques significantly influence the speed and accuracy of the analysis.
Substrate and mixed-signal analysis techniques can be applied to placement and power distribution synthesis.
References
Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and Scheffer, A survey of the field of electronic design automation. This article was derived, with permission, from Chapter 23 of Book 2, Mixed-Signal Noise Coupling in System-on-Chip Design: Modeling, Analysis, and Validation, by Nishath Verghese and Makoto Nagata
Further reading / External links
Technical Book: "Noise Coupling in Integrated Circuits: A Practical Approach to Analysis, Modeling, and Suppression", by Cosmin Iorga, Ph.D., 286pages, Hardcover
Electronic design
Electronic design automation
Electronic engineering
Integrated circuits |