input
stringlengths 144
489k
| output
stringlengths 45
339k
| shard
stringclasses 16
values | filename
stringlengths 135
135
| line_num
int64 0
2.62k
| context
sequence |
|---|---|---|---|---|---|
{"name": "trans_QADD8", "code": "__int64 __fastcall trans_QADD8 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_qadd8 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,421 | [
"{\"name\": \"gen_helper_qadd8\", \"code\": \"unsigned __int64 __fastcall gen_helper_qadd8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_qadd8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_QADD\", \"code\": \"__int64 __fastcall trans_QADD ( __int64 @@a1@@ , int * @@a2@@ ) { return op_qaddsub ( @@a1@@ , @@a2@@ , Number , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_QSUB8", "code": "__int64 __fastcall trans_QSUB8 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_qsub8 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,422 | [
"{\"name\": \"gen_helper_qsub8\", \"code\": \"unsigned __int64 __fastcall gen_helper_qsub8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_qsub8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_QSUB\", \"code\": \"__int64 __fastcall trans_QSUB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_qaddsub ( @@a1@@ , @@a2@@ , Number , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UQADD16", "code": "__int64 __fastcall trans_UQADD16 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_uqadd16 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,423 | [
"{\"name\": \"gen_helper_uqadd16\", \"code\": \"unsigned __int64 __fastcall gen_helper_uqadd16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_uqadd16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UQASX", "code": "__int64 __fastcall trans_UQASX ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_uqaddsubx ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,424 | [
"{\"name\": \"gen_helper_uqaddsubx\", \"code\": \"unsigned __int64 __fastcall gen_helper_uqaddsubx ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_uqaddsubx , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UQSAX", "code": "__int64 __fastcall trans_UQSAX ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_uqsubaddx ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,425 | [
"{\"name\": \"gen_helper_uqsubaddx\", \"code\": \"unsigned __int64 __fastcall gen_helper_uqsubaddx ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_uqsubaddx , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UQSUB16", "code": "__int64 __fastcall trans_UQSUB16 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_uqsub16 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,426 | [
"{\"name\": \"gen_helper_uqsub16\", \"code\": \"unsigned __int64 __fastcall gen_helper_uqsub16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_uqsub16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UQADD8", "code": "__int64 __fastcall trans_UQADD8 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_uqadd8 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,427 | [
"{\"name\": \"gen_helper_uqadd8\", \"code\": \"unsigned __int64 __fastcall gen_helper_uqadd8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_uqadd8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UQSUB8", "code": "__int64 __fastcall trans_UQSUB8 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_uqsub8 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,428 | [
"{\"name\": \"gen_helper_uqsub8\", \"code\": \"unsigned __int64 __fastcall gen_helper_uqsub8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_uqsub8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SHADD16", "code": "__int64 __fastcall trans_SHADD16 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_shadd16 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,429 | [
"{\"name\": \"gen_helper_shadd16\", \"code\": \"unsigned __int64 __fastcall gen_helper_shadd16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_shadd16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SHASX", "code": "__int64 __fastcall trans_SHASX ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_shaddsubx ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,430 | [
"{\"name\": \"gen_helper_shaddsubx\", \"code\": \"unsigned __int64 __fastcall gen_helper_shaddsubx ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_shaddsubx , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SHSAX", "code": "__int64 __fastcall trans_SHSAX ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_shsubaddx ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,431 | [
"{\"name\": \"gen_helper_shsubaddx\", \"code\": \"unsigned __int64 __fastcall gen_helper_shsubaddx ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_shsubaddx , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SHSUB16", "code": "__int64 __fastcall trans_SHSUB16 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_shsub16 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,432 | [
"{\"name\": \"gen_helper_shsub16\", \"code\": \"unsigned __int64 __fastcall gen_helper_shsub16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_shsub16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SHADD8", "code": "__int64 __fastcall trans_SHADD8 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_shadd8 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,433 | [
"{\"name\": \"gen_helper_shadd8\", \"code\": \"unsigned __int64 __fastcall gen_helper_shadd8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_shadd8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SHSUB8", "code": "__int64 __fastcall trans_SHSUB8 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_shsub8 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,434 | [
"{\"name\": \"gen_helper_shsub8\", \"code\": \"unsigned __int64 __fastcall gen_helper_shsub8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_shsub8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UHADD16", "code": "__int64 __fastcall trans_UHADD16 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_uhadd16 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,435 | [
"{\"name\": \"gen_helper_uhadd16\", \"code\": \"unsigned __int64 __fastcall gen_helper_uhadd16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_uhadd16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UHASX", "code": "__int64 __fastcall trans_UHASX ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_uhaddsubx ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,436 | [
"{\"name\": \"gen_helper_uhaddsubx\", \"code\": \"unsigned __int64 __fastcall gen_helper_uhaddsubx ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_uhaddsubx , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UHSAX", "code": "__int64 __fastcall trans_UHSAX ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_uhsubaddx ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,437 | [
"{\"name\": \"gen_helper_uhsubaddx\", \"code\": \"unsigned __int64 __fastcall gen_helper_uhsubaddx ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_uhsubaddx , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UHSUB16", "code": "__int64 __fastcall trans_UHSUB16 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_uhsub16 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,438 | [
"{\"name\": \"gen_helper_uhsub16\", \"code\": \"unsigned __int64 __fastcall gen_helper_uhsub16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_uhsub16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UHADD8", "code": "__int64 __fastcall trans_UHADD8 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_uhadd8 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,439 | [
"{\"name\": \"gen_helper_uhadd8\", \"code\": \"unsigned __int64 __fastcall gen_helper_uhadd8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_uhadd8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UHSUB8", "code": "__int64 __fastcall trans_UHSUB8 ( __int64 @@a1@@ , int * @@a2@@ ) { return op_par_addsub ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_helper_uhsub8 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,440 | [
"{\"name\": \"gen_helper_uhsub8\", \"code\": \"unsigned __int64 __fastcall gen_helper_uhsub8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_uhsub8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_par_addsub\", \"code\": \"__int64 __fastcall op_par_addsub ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 , __int64 ) ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v3@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_PKH", "code": "__int64 __fastcall trans_PKH ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { bool @@v2@@ ; unsigned int @@v4@@ ; __int64 @@v5@@ ; __int64 @@v6@@ ; @@v4@@ = * @@a2@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v2@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v2@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v2@@ ) return Number L ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a2@@ [ Number ] ) { if ( ! @@v4@@ ) @@v4@@ = Number ; tcg_gen_sari_i32 ( @@v6@@ , @@v6@@ , @@v4@@ ) ; tcg_gen_deposit_i32 ( @@v5@@ , @@v5@@ , @@v6@@ , Number L , Number L ) ; } else { tcg_gen_shli_i32 ( @@v6@@ , @@v6@@ , @@v4@@ ) ; tcg_gen_deposit_i32 ( @@v5@@ , @@v6@@ , @@v5@@ , Number L , Number L ) ; } tcg_temp_free_i32 ( @@v6@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v5@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_PKH"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "tn", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "shift", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "tm", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,441 | [
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shl\", \"code\": \"__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_sar\", \"code\": \"__int64 __fastcall gen_sar ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v5@@ , @@v5@@ , @@v6@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_gen_sar_i32 ( @@a1@@ , @@a2@@ , @@v5@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "op_sat", "code": "__int64 __fastcall op_sat ( __int64 @@a1@@ , unsigned int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , _QWORD , __int64 , __int64 ) ) { unsigned int @@v4@@ ; unsigned int @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; @@v6@@ = * @@a2@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a2@@ [ Number ] ) { if ( @@v6@@ ) @@v4@@ = @@v6@@ ; else @@v4@@ = Number ; tcg_gen_sari_i32 ( @@v7@@ , @@v7@@ , @@v4@@ ) ; } else { tcg_gen_shli_i32 ( @@v7@@ , @@v7@@ , @@v6@@ ) ; } @@v8@@ = tcg_const_i32 ( @@a2@@ [ Number ] ) ; @@a3@@ ( @@v7@@ , cpu_env , @@v7@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v7@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 9, "n": "void (__fastcall *)(__int64, _QWORD, __int64, __int64)"}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r8"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v6", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "gen", "t": {"T": 9, "n": "void (*)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)"}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_sat"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r8"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "shift", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "satimm", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,442 | [
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shl\", \"code\": \"__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_sar\", \"code\": \"__int64 __fastcall gen_sar ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v5@@ , @@v5@@ , @@v6@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_gen_sar_i32 ( @@a1@@ , @@a2@@ , @@v5@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SSAT", "code": "__int64 __fastcall trans_SSAT ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { return op_sat ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , _QWORD , __int64 , __int64 ) ) gen_helper_ssat ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_sat"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,443 | [
"{\"name\": \"gen_helper_ssat\", \"code\": \"unsigned __int64 __fastcall gen_helper_ssat ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_ssat , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_sat\", \"code\": \"__int64 __fastcall op_sat ( __int64 @@a1@@ , unsigned int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , _QWORD , __int64 , __int64 ) ) { unsigned int @@v4@@ ; unsigned int @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; @@v6@@ = * @@a2@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a2@@ [ Number ] ) { if ( @@v6@@ ) @@v4@@ = @@v6@@ ; else @@v4@@ = Number ; tcg_gen_sari_i32 ( @@v7@@ , @@v7@@ , @@v4@@ ) ; } else { tcg_gen_shli_i32 ( @@v7@@ , @@v7@@ , @@v6@@ ) ; } @@v8@@ = tcg_const_i32 ( @@a2@@ [ Number ] ) ; @@a3@@ ( @@v7@@ , cpu_env , @@v7@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, _QWORD, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_USAT", "code": "__int64 __fastcall trans_USAT ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { return op_sat ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , _QWORD , __int64 , __int64 ) ) gen_helper_usat ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_sat"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,444 | [
"{\"name\": \"gen_helper_usat\", \"code\": \"unsigned __int64 __fastcall gen_helper_usat ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_usat , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_sat\", \"code\": \"__int64 __fastcall op_sat ( __int64 @@a1@@ , unsigned int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , _QWORD , __int64 , __int64 ) ) { unsigned int @@v4@@ ; unsigned int @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; @@v6@@ = * @@a2@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a2@@ [ Number ] ) { if ( @@v6@@ ) @@v4@@ = @@v6@@ ; else @@v4@@ = Number ; tcg_gen_sari_i32 ( @@v7@@ , @@v7@@ , @@v4@@ ) ; } else { tcg_gen_shli_i32 ( @@v7@@ , @@v7@@ , @@v6@@ ) ; } @@v8@@ = tcg_const_i32 ( @@a2@@ [ Number ] ) ; @@a3@@ ( @@v7@@ , cpu_env , @@v7@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, _QWORD, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SSAT16", "code": "__int64 __fastcall trans_SSAT16 ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { __int64 @@result@@ ; if ( ! * ( _DWORD * ) ( @@a1@@ + Number ) || arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_sat ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , _QWORD , __int64 , __int64 ) ) gen_helper_ssat16 ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_sat"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,445 | [
"{\"name\": \"gen_helper_ssat\", \"code\": \"unsigned __int64 __fastcall gen_helper_ssat ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_ssat , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_ssat16\", \"code\": \"unsigned __int64 __fastcall gen_helper_ssat16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_ssat16 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_sat\", \"code\": \"__int64 __fastcall op_sat ( __int64 @@a1@@ , unsigned int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , _QWORD , __int64 , __int64 ) ) { unsigned int @@v4@@ ; unsigned int @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; @@v6@@ = * @@a2@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a2@@ [ Number ] ) { if ( @@v6@@ ) @@v4@@ = @@v6@@ ; else @@v4@@ = Number ; tcg_gen_sari_i32 ( @@v7@@ , @@v7@@ , @@v4@@ ) ; } else { tcg_gen_shli_i32 ( @@v7@@ , @@v7@@ , @@v6@@ ) ; } @@v8@@ = tcg_const_i32 ( @@a2@@ [ Number ] ) ; @@a3@@ ( @@v7@@ , cpu_env , @@v7@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, _QWORD, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_SSAT\", \"code\": \"__int64 __fastcall trans_SSAT ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { return op_sat ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , _QWORD , __int64 , __int64 ) ) gen_helper_ssat ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}]}"
] |
{"name": "trans_USAT16", "code": "__int64 __fastcall trans_USAT16 ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { __int64 @@result@@ ; if ( ! * ( _DWORD * ) ( @@a1@@ + Number ) || arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_sat ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , _QWORD , __int64 , __int64 ) ) gen_helper_usat16 ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_sat"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,446 | [
"{\"name\": \"gen_helper_usat\", \"code\": \"unsigned __int64 __fastcall gen_helper_usat ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_usat , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_usat16\", \"code\": \"unsigned __int64 __fastcall gen_helper_usat16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_usat16 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_sat\", \"code\": \"__int64 __fastcall op_sat ( __int64 @@a1@@ , unsigned int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , _QWORD , __int64 , __int64 ) ) { unsigned int @@v4@@ ; unsigned int @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; @@v6@@ = * @@a2@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a2@@ [ Number ] ) { if ( @@v6@@ ) @@v4@@ = @@v6@@ ; else @@v4@@ = Number ; tcg_gen_sari_i32 ( @@v7@@ , @@v7@@ , @@v4@@ ) ; } else { tcg_gen_shli_i32 ( @@v7@@ , @@v7@@ , @@v6@@ ) ; } @@v8@@ = tcg_const_i32 ( @@a2@@ [ Number ] ) ; @@a3@@ ( @@v7@@ , cpu_env , @@v7@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, _QWORD, __int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_USAT\", \"code\": \"__int64 __fastcall trans_USAT ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { return op_sat ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , _QWORD , __int64 , __int64 ) ) gen_helper_usat ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}]}"
] |
{"name": "op_xta", "code": "__int64 __fastcall op_xta ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) , void ( __fastcall * @@a4@@ ) ( __int64 , __int64 , __int64 ) ) { __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_rotri_i32 ( @@v7@@ , @@v7@@ , ( unsigned int ) ( Number * @@a2@@ [ Number ] ) ) ; @@a3@@ ( @@v7@@ , @@v7@@ ) ; if ( @@a2@@ [ Number ] != Number ) { @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a4@@ ( @@v7@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; } store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 9, "n": "void (__fastcall *)(__int64, __int64)"}, "location": "r16"}, {"n": "a4", "t": {"T": 9, "n": "void (__fastcall *)(__int64, __int64, __int64)"}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "gen_extract", "t": {"T": 9, "n": "void (*)(TCGv_i32, TCGv_i32)"}, "location": "r16"}, {"n": "gen_add", "t": {"T": 9, "n": "void (*)(TCGv_i32, TCGv_i32, TCGv_i32)"}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr_rot"}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "tmp2", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,447 | [
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "trans_SXTAB", "code": "__int64 __fastcall trans_SXTAB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_xta ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) & tcg_gen_ext8s_i32 , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_add_i32 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr_rot"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,448 | [
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_xta\", \"code\": \"__int64 __fastcall op_xta ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) , void ( __fastcall * @@a4@@ ) ( __int64 , __int64 , __int64 ) ) { __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_rotri_i32 ( @@v7@@ , @@v7@@ , ( unsigned int ) ( Number * @@a2@@ [ Number ] ) ) ; @@a3@@ ( @@v7@@ , @@v7@@ ) ; if ( @@a2@@ [ Number ] != Number ) { @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a4@@ ( @@v7@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; } store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SXTAH", "code": "__int64 __fastcall trans_SXTAH ( __int64 @@a1@@ , int * @@a2@@ ) { return op_xta ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) & tcg_gen_ext16s_i32 , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_add_i32 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr_rot"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,449 | [
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_xta\", \"code\": \"__int64 __fastcall op_xta ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) , void ( __fastcall * @@a4@@ ) ( __int64 , __int64 , __int64 ) ) { __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_rotri_i32 ( @@v7@@ , @@v7@@ , ( unsigned int ) ( Number * @@a2@@ [ Number ] ) ) ; @@a3@@ ( @@v7@@ , @@v7@@ ) ; if ( @@a2@@ [ Number ] != Number ) { @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a4@@ ( @@v7@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; } store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SXTAB16", "code": "__int64 __fastcall trans_SXTAB16 ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( ! * ( _DWORD * ) ( @@a1@@ + Number ) || arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_xta ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) gen_helper_sxtb16 , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_add16 ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr_rot"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,450 | [
"{\"name\": \"gen_helper_sxtb16\", \"code\": \"unsigned __int64 __fastcall gen_helper_sxtb16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_sxtb16 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_add16\", \"code\": \"__int64 __fastcall gen_add16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v6@@ ; @@v6@@ = tcg_temp_new_i32 ( ) ; tcg_gen_xor_i32 ( @@v6@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_andi_i32 ( @@v6@@ , @@v6@@ , Number ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , Number L ) ; tcg_gen_add_i32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_xor_i32 ( @@a1@@ , @@a2@@ , @@v6@@ ) ; return tcg_temp_free_i32 ( @@v6@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_xta\", \"code\": \"__int64 __fastcall op_xta ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) , void ( __fastcall * @@a4@@ ) ( __int64 , __int64 , __int64 ) ) { __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_rotri_i32 ( @@v7@@ , @@v7@@ , ( unsigned int ) ( Number * @@a2@@ [ Number ] ) ) ; @@a3@@ ( @@v7@@ , @@v7@@ ) ; if ( @@a2@@ [ Number ] != Number ) { @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a4@@ ( @@v7@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; } store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_SXTAB\", \"code\": \"__int64 __fastcall trans_SXTAB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_xta ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) & tcg_gen_ext8s_i32 , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_add_i32 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}"
] |
{"name": "trans_UXTAB", "code": "__int64 __fastcall trans_UXTAB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_xta ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) & tcg_gen_ext8u_i32 , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_add_i32 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr_rot"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,451 | [
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_xta\", \"code\": \"__int64 __fastcall op_xta ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) , void ( __fastcall * @@a4@@ ) ( __int64 , __int64 , __int64 ) ) { __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_rotri_i32 ( @@v7@@ , @@v7@@ , ( unsigned int ) ( Number * @@a2@@ [ Number ] ) ) ; @@a3@@ ( @@v7@@ , @@v7@@ ) ; if ( @@a2@@ [ Number ] != Number ) { @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a4@@ ( @@v7@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; } store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UXTAH", "code": "__int64 __fastcall trans_UXTAH ( __int64 @@a1@@ , int * @@a2@@ ) { return op_xta ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) & tcg_gen_ext16u_i32 , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_add_i32 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr_rot"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,452 | [
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_xta\", \"code\": \"__int64 __fastcall op_xta ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) , void ( __fastcall * @@a4@@ ) ( __int64 , __int64 , __int64 ) ) { __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_rotri_i32 ( @@v7@@ , @@v7@@ , ( unsigned int ) ( Number * @@a2@@ [ Number ] ) ) ; @@a3@@ ( @@v7@@ , @@v7@@ ) ; if ( @@a2@@ [ Number ] != Number ) { @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a4@@ ( @@v7@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; } store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UXTAB16", "code": "__int64 __fastcall trans_UXTAB16 ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( ! * ( _DWORD * ) ( @@a1@@ + Number ) || arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_xta ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) gen_helper_uxtb16 , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) gen_add16 ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr_rot"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,453 | [
"{\"name\": \"gen_helper_uxtb16\", \"code\": \"unsigned __int64 __fastcall gen_helper_uxtb16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_uxtb16 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_add16\", \"code\": \"__int64 __fastcall gen_add16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v6@@ ; @@v6@@ = tcg_temp_new_i32 ( ) ; tcg_gen_xor_i32 ( @@v6@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_andi_i32 ( @@v6@@ , @@v6@@ , Number ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , Number L ) ; tcg_gen_add_i32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_xor_i32 ( @@a1@@ , @@a2@@ , @@v6@@ ) ; return tcg_temp_free_i32 ( @@v6@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_xta\", \"code\": \"__int64 __fastcall op_xta ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) , void ( __fastcall * @@a4@@ ) ( __int64 , __int64 , __int64 ) ) { __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_rotri_i32 ( @@v7@@ , @@v7@@ , ( unsigned int ) ( Number * @@a2@@ [ Number ] ) ) ; @@a3@@ ( @@v7@@ , @@v7@@ ) ; if ( @@a2@@ [ Number ] != Number ) { @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a4@@ ( @@v7@@ , @@v7@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; } store_reg ( @@a1@@ , * @@a2@@ , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64)\"}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_UXTAB\", \"code\": \"__int64 __fastcall trans_UXTAB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_xta ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) & tcg_gen_ext8u_i32 , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 ) ) tcg_gen_add_i32 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}"
] |
{"name": "trans_SEL", "code": "__int64 __fastcall trans_SEL ( __int64 @@a1@@ , int * @@a2@@ ) { bool @@v2@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; __int64 @@v6@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v2@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v2@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v2@@ ) return Number L ; @@v4@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v6@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v6@@ , cpu_env , Number L ) ; gen_helper_sel_flags ( @@v4@@ , @@v6@@ , @@v4@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v4@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "t2", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "t1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "t3", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,454 | [
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_sel_flags\", \"code\": \"unsigned __int64 __fastcall gen_helper_sel_flags ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_sel_flags , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ld_i32\", \"code\": \"__int64 __fastcall tcg_gen_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "op_rr", "code": "__int64 __fastcall op_rr ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) ) { __int64 @@v5@@ ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v5@@ , @@v5@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v5@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 9, "n": "void (__fastcall *)(__int64, __int64)"}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "gen", "t": {"T": 9, "n": "void (*)(TCGv_i32, TCGv_i32)"}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rr"}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,455 | [
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "trans_REV", "code": "__int64 __fastcall trans_REV ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_rr ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) & tcg_gen_bswap32_i32 ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rr"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,456 | [
"{\"name\": \"bswap32\", \"code\": \"__int64 __fastcall bswap32 ( unsigned int @@a1@@ ) { return _bswap_32 ( @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_rr\", \"code\": \"__int64 __fastcall op_rr ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) ) { __int64 @@v5@@ ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v5@@ , @@v5@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v5@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_REV16", "code": "__int64 __fastcall trans_REV16 ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_rr ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) gen_rev16 ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rr"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,457 | [
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_rev16\", \"code\": \"__int64 __fastcall gen_rev16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v4@@ ; __int64 @@v5@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v5@@ = tcg_const_i32 ( Number L ) ; tcg_gen_shri_i32 ( @@v4@@ , @@a2@@ , Number L ) ; tcg_gen_and_i32 ( @@v4@@ , @@v4@@ , @@v5@@ ) ; tcg_gen_and_i32 ( @@a2@@ , @@a2@@ , @@v5@@ ) ; tcg_gen_shli_i32 ( @@a2@@ , @@a2@@ , Number L ) ; tcg_gen_or_i32 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_temp_free_i32 ( @@v4@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_rr\", \"code\": \"__int64 __fastcall op_rr ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) ) { __int64 @@v5@@ ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v5@@ , @@v5@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v5@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_REV\", \"code\": \"__int64 __fastcall trans_REV ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_rr ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) & tcg_gen_bswap32_i32 ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_REVSH", "code": "__int64 __fastcall trans_REVSH ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_rr ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) gen_revsh ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rr"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,458 | [
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_revsh\", \"code\": \"__int64 __fastcall gen_revsh ( __int64 @@a1@@ , __int64 @@a2@@ ) { tcg_gen_ext16u_i32 ( @@a2@@ , @@a2@@ ) ; tcg_gen_bswap16_i32 ( @@a2@@ , @@a2@@ ) ; return tcg_gen_ext16s_i32 ( @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_rr\", \"code\": \"__int64 __fastcall op_rr ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) ) { __int64 @@v5@@ ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v5@@ , @@v5@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v5@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_REV\", \"code\": \"__int64 __fastcall trans_REV ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_rr ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) & tcg_gen_bswap32_i32 ) ; else @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_RBIT", "code": "__int64 __fastcall trans_RBIT ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 @@result@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = op_rr ( @@a1@@ , @@a2@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) gen_helper_rbit ) ; else @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rr"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,459 | [
"{\"name\": \"gen_helper_rbit\", \"code\": \"unsigned __int64 __fastcall gen_helper_rbit ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_rbit , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"op_rr\", \"code\": \"__int64 __fastcall op_rr ( __int64 @@a1@@ , int * @@a2@@ , void ( __fastcall * @@a3@@ ) ( __int64 , __int64 ) ) { __int64 @@v5@@ ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@a3@@ ( @@v5@@ , @@v5@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v5@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "op_smlad", "code": "__int64 __fastcall op_smlad ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 @@v7@@ ; __int64 v8 ; __int64 v9 ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v8 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) gen_swap_half ( v8 ) ; gen_smul_dual ( @@v7@@ , v8 ) ; if ( @@a4@@ ) tcg_gen_sub_i32 ( @@v7@@ , @@v7@@ , v8 ) ; else gen_helper_add_setq ( @@v7@@ , cpu_env , @@v7@@ , v8 ) ; tcg_temp_free_i32 ( v8 ) ; if ( * @@a2@@ != Number ) { v9 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v7@@ , cpu_env , @@v7@@ , v9 ) ; tcg_temp_free_i32 ( v9 ) ; } store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v7@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "char", "s": 1}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "char", "s": 1}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}]} | [{"n": "m_swap", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r16"}, {"n": "sub", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}, {"n": "t1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,460 | [
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_add_setq\", \"code\": \"unsigned __int64 __fastcall gen_helper_add_setq ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_add_setq , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_sub_i32\", \"code\": \"__int64 __fastcall tcg_gen_sub_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_smul_dual\", \"code\": \"__int64 __fastcall gen_smul_dual ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v4@@ ; __int64 @@v5@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ext16s_i32 ( @@v4@@ , @@a1@@ ) ; tcg_gen_ext16s_i32 ( @@v5@@ , @@a2@@ ) ; tcg_gen_mul_i32 ( @@v4@@ , @@v4@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; tcg_gen_sari_i32 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_sari_i32 ( @@a2@@ , @@a2@@ , Number L ) ; tcg_gen_mul_i32 ( @@a2@@ , @@a2@@ , @@a1@@ ) ; tcg_gen_mov_i32 ( @@a1@@ , @@v4@@ ) ; return tcg_temp_free_i32 ( @@v4@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_swap_half\", \"code\": \"__int64 __fastcall gen_swap_half ( __int64 @@a1@@ ) { return tcg_gen_rotri_i32 ( @@a1@@ , @@a1@@ , Number L ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}"
] |
{"name": "trans_SMLAD", "code": "__int64 __fastcall trans_SMLAD ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlad ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,461 | [
"{\"name\": \"op_smlad\", \"code\": \"__int64 __fastcall op_smlad ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 @@v7@@ ; __int64 v8 ; __int64 v9 ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v8 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) gen_swap_half ( v8 ) ; gen_smul_dual ( @@v7@@ , v8 ) ; if ( @@a4@@ ) tcg_gen_sub_i32 ( @@v7@@ , @@v7@@ , v8 ) ; else gen_helper_add_setq ( @@v7@@ , cpu_env , @@v7@@ , v8 ) ; tcg_temp_free_i32 ( v8 ) ; if ( * @@a2@@ != Number ) { v9 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v7@@ , cpu_env , @@v7@@ , v9 ) ; tcg_temp_free_i32 ( v9 ) ; } store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}]}"
] |
{"name": "trans_SMLADX", "code": "__int64 __fastcall trans_SMLADX ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlad ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,462 | [
"{\"name\": \"op_smlad\", \"code\": \"__int64 __fastcall op_smlad ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 @@v7@@ ; __int64 v8 ; __int64 v9 ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v8 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) gen_swap_half ( v8 ) ; gen_smul_dual ( @@v7@@ , v8 ) ; if ( @@a4@@ ) tcg_gen_sub_i32 ( @@v7@@ , @@v7@@ , v8 ) ; else gen_helper_add_setq ( @@v7@@ , cpu_env , @@v7@@ , v8 ) ; tcg_temp_free_i32 ( v8 ) ; if ( * @@a2@@ != Number ) { v9 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v7@@ , cpu_env , @@v7@@ , v9 ) ; tcg_temp_free_i32 ( v9 ) ; } store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}]}",
"{\"name\": \"trans_SMLAD\", \"code\": \"__int64 __fastcall trans_SMLAD ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlad ( @@a1@@ , @@a2@@ , Number , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}"
] |
{"name": "trans_SMLSD", "code": "__int64 __fastcall trans_SMLSD ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlad ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,463 | [
"{\"name\": \"op_smlad\", \"code\": \"__int64 __fastcall op_smlad ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 @@v7@@ ; __int64 v8 ; __int64 v9 ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v8 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) gen_swap_half ( v8 ) ; gen_smul_dual ( @@v7@@ , v8 ) ; if ( @@a4@@ ) tcg_gen_sub_i32 ( @@v7@@ , @@v7@@ , v8 ) ; else gen_helper_add_setq ( @@v7@@ , cpu_env , @@v7@@ , v8 ) ; tcg_temp_free_i32 ( v8 ) ; if ( * @@a2@@ != Number ) { v9 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v7@@ , cpu_env , @@v7@@ , v9 ) ; tcg_temp_free_i32 ( v9 ) ; } store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}]}"
] |
{"name": "trans_SMLSDX", "code": "__int64 __fastcall trans_SMLSDX ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlad ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,464 | [
"{\"name\": \"op_smlad\", \"code\": \"__int64 __fastcall op_smlad ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 @@v7@@ ; __int64 v8 ; __int64 v9 ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; v8 = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) gen_swap_half ( v8 ) ; gen_smul_dual ( @@v7@@ , v8 ) ; if ( @@a4@@ ) tcg_gen_sub_i32 ( @@v7@@ , @@v7@@ , v8 ) ; else gen_helper_add_setq ( @@v7@@ , cpu_env , @@v7@@ , v8 ) ; tcg_temp_free_i32 ( v8 ) ; if ( * @@a2@@ != Number ) { v9 = load_reg ( @@a1@@ , * @@a2@@ ) ; gen_helper_add_setq ( @@v7@@ , cpu_env , @@v7@@ , v9 ) ; tcg_temp_free_i32 ( v9 ) ; } store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v7@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}]}",
"{\"name\": \"trans_SMLSD\", \"code\": \"__int64 __fastcall trans_SMLSD ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlad ( @@a1@@ , @@a2@@ , Number , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}"
] |
{"name": "op_smlald", "code": "__int64 __fastcall op_smlald ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) gen_swap_half ( @@v8@@ ) ; gen_smul_dual ( @@v7@@ , @@v8@@ ) ; @@v9@@ = tcg_temp_new_i64 ( ) ; @@v10@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ext_i32_i64 ( @@v9@@ , @@v7@@ ) ; tcg_gen_ext_i32_i64 ( @@v10@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; if ( @@a4@@ ) tcg_gen_sub_i64 ( @@v9@@ , @@v9@@ , @@v10@@ ) ; else tcg_gen_add_i64 ( @@v9@@ , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i64 ( @@v10@@ ) ; gen_addq ( @@a1@@ , @@v9@@ , * @@a2@@ , @@a2@@ [ Number ] ) ; gen_storeq_reg ( @@a1@@ , * @@a2@@ , @@a2@@ [ Number ] , @@v9@@ ) ; tcg_temp_free_i64 ( @@v9@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "char", "s": 1}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "char", "s": 1}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "v10", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "m_swap", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r16"}, {"n": "sub", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}, {"n": "l1", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s16"}, {"n": "t2", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "t1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s32"}, {"n": "l2", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,465 | [
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_add_i64\", \"code\": \"__int64 __fastcall tcg_gen_add_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_sub_i64\", \"code\": \"__int64 __fastcall tcg_gen_sub_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_smul_dual\", \"code\": \"__int64 __fastcall gen_smul_dual ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v4@@ ; __int64 @@v5@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ext16s_i32 ( @@v4@@ , @@a1@@ ) ; tcg_gen_ext16s_i32 ( @@v5@@ , @@a2@@ ) ; tcg_gen_mul_i32 ( @@v4@@ , @@v4@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; tcg_gen_sari_i32 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_sari_i32 ( @@a2@@ , @@a2@@ , Number L ) ; tcg_gen_mul_i32 ( @@a2@@ , @@a2@@ , @@a1@@ ) ; tcg_gen_mov_i32 ( @@a1@@ , @@v4@@ ) ; return tcg_temp_free_i32 ( @@v4@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_swap_half\", \"code\": \"__int64 __fastcall gen_swap_half ( __int64 @@a1@@ ) { return tcg_gen_rotri_i32 ( @@a1@@ , @@a1@@ , Number L ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_storeq_reg\", \"code\": \"__int64 __fastcall gen_storeq_reg ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , __int64 @@a4@@ ) { __int64 v7 ; __int64 v8 ; v7 = tcg_temp_new_i32 ( ) ; tcg_gen_extrl_i64_i32 ( v7 , @@a4@@ ) ; store_reg ( @@a1@@ , @@a2@@ , v7 ) ; v8 = tcg_temp_new_i32 ( ) ; tcg_gen_extrh_i64_i32 ( v8 , @@a4@@ ) ; return store_reg ( @@a1@@ , @@a3@@ , v8 ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_addq\", \"code\": \"__int64 __fastcall gen_addq ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int64 @@v6@@ ; __int64 @@v7@@ ; __int64 @@v8@@ ; @@v6@@ = load_reg ( @@a1@@ , @@a3@@ ) ; @@v7@@ = load_reg ( @@a1@@ , @@a4@@ ) ; @@v8@@ = tcg_temp_new_i64 ( ) ; tcg_gen_concat_i32_i64 ( @@v8@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_add_i64 ( @@a2@@ , @@a2@@ , @@v8@@ ) ; return tcg_temp_free_i64 ( @@v8@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMLALD", "code": "__int64 __fastcall trans_SMLALD ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlald ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,466 | [
"{\"name\": \"trans_SMLAL\", \"code\": \"__int64 __fastcall trans_SMLAL ( __int64 @@a1@@ , int * @@a2@@ ) { return op_mlal ( @@a1@@ , @@a2@@ , Number , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}",
"{\"name\": \"op_smlald\", \"code\": \"__int64 __fastcall op_smlald ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) gen_swap_half ( @@v8@@ ) ; gen_smul_dual ( @@v7@@ , @@v8@@ ) ; @@v9@@ = tcg_temp_new_i64 ( ) ; @@v10@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ext_i32_i64 ( @@v9@@ , @@v7@@ ) ; tcg_gen_ext_i32_i64 ( @@v10@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; if ( @@a4@@ ) tcg_gen_sub_i64 ( @@v9@@ , @@v9@@ , @@v10@@ ) ; else tcg_gen_add_i64 ( @@v9@@ , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i64 ( @@v10@@ ) ; gen_addq ( @@a1@@ , @@v9@@ , * @@a2@@ , @@a2@@ [ Number ] ) ; gen_storeq_reg ( @@a1@@ , * @@a2@@ , @@a2@@ [ Number ] , @@v9@@ ) ; tcg_temp_free_i64 ( @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMLALDX", "code": "__int64 __fastcall trans_SMLALDX ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlald ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,467 | [
"{\"name\": \"trans_SMLAL\", \"code\": \"__int64 __fastcall trans_SMLAL ( __int64 @@a1@@ , int * @@a2@@ ) { return op_mlal ( @@a1@@ , @@a2@@ , Number , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}",
"{\"name\": \"op_smlald\", \"code\": \"__int64 __fastcall op_smlald ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) gen_swap_half ( @@v8@@ ) ; gen_smul_dual ( @@v7@@ , @@v8@@ ) ; @@v9@@ = tcg_temp_new_i64 ( ) ; @@v10@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ext_i32_i64 ( @@v9@@ , @@v7@@ ) ; tcg_gen_ext_i32_i64 ( @@v10@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; if ( @@a4@@ ) tcg_gen_sub_i64 ( @@v9@@ , @@v9@@ , @@v10@@ ) ; else tcg_gen_add_i64 ( @@v9@@ , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i64 ( @@v10@@ ) ; gen_addq ( @@a1@@ , @@v9@@ , * @@a2@@ , @@a2@@ [ Number ] ) ; gen_storeq_reg ( @@a1@@ , * @@a2@@ , @@a2@@ [ Number ] , @@v9@@ ) ; tcg_temp_free_i64 ( @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_SMLALD\", \"code\": \"__int64 __fastcall trans_SMLALD ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlald ( @@a1@@ , @@a2@@ , Number , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}"
] |
{"name": "trans_SMLSLD", "code": "__int64 __fastcall trans_SMLSLD ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlald ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,468 | [
"{\"name\": \"op_smlald\", \"code\": \"__int64 __fastcall op_smlald ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) gen_swap_half ( @@v8@@ ) ; gen_smul_dual ( @@v7@@ , @@v8@@ ) ; @@v9@@ = tcg_temp_new_i64 ( ) ; @@v10@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ext_i32_i64 ( @@v9@@ , @@v7@@ ) ; tcg_gen_ext_i32_i64 ( @@v10@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; if ( @@a4@@ ) tcg_gen_sub_i64 ( @@v9@@ , @@v9@@ , @@v10@@ ) ; else tcg_gen_add_i64 ( @@v9@@ , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i64 ( @@v10@@ ) ; gen_addq ( @@a1@@ , @@v9@@ , * @@a2@@ , @@a2@@ [ Number ] ) ; gen_storeq_reg ( @@a1@@ , * @@a2@@ , @@a2@@ [ Number ] , @@v9@@ ) ; tcg_temp_free_i64 ( @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMLSLDX", "code": "__int64 __fastcall trans_SMLSLDX ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlald ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,469 | [
"{\"name\": \"op_smlald\", \"code\": \"__int64 __fastcall op_smlald ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) gen_swap_half ( @@v8@@ ) ; gen_smul_dual ( @@v7@@ , @@v8@@ ) ; @@v9@@ = tcg_temp_new_i64 ( ) ; @@v10@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ext_i32_i64 ( @@v9@@ , @@v7@@ ) ; tcg_gen_ext_i32_i64 ( @@v10@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; if ( @@a4@@ ) tcg_gen_sub_i64 ( @@v9@@ , @@v9@@ , @@v10@@ ) ; else tcg_gen_add_i64 ( @@v9@@ , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i64 ( @@v10@@ ) ; gen_addq ( @@a1@@ , @@v9@@ , * @@a2@@ , @@a2@@ [ Number ] ) ; gen_storeq_reg ( @@a1@@ , * @@a2@@ , @@a2@@ [ Number ] , @@v9@@ ) ; tcg_temp_free_i64 ( @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_SMLSLD\", \"code\": \"__int64 __fastcall trans_SMLSLD ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smlald ( @@a1@@ , @@a2@@ , Number , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}"
] |
{"name": "op_smmla", "code": "__int64 __fastcall op_smmla ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { bool @@v4@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v4@@ ) return Number L ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_muls2_i32 ( @@v9@@ , @@v8@@ , @@v8@@ , @@v9@@ ) ; if ( * @@a2@@ != Number ) { @@v10@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; if ( @@a4@@ ) { @@v11@@ = tcg_const_i32 ( Number L ) ; tcg_gen_sub2_i32 ( @@v9@@ , @@v8@@ , @@v11@@ , @@v10@@ , @@v9@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; } else { tcg_gen_add_i32 ( @@v8@@ , @@v8@@ , @@v10@@ ) ; } tcg_temp_free_i32 ( @@v10@@ ) ; } if ( @@a3@@ ) { tcg_gen_shri_i32 ( @@v9@@ , @@v9@@ , Number L ) ; tcg_gen_add_i32 ( @@v8@@ , @@v8@@ , @@v9@@ ) ; } tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v8@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "char", "s": 1}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "char", "s": 1}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "v10", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "v11", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "round", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r16"}, {"n": "sub", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "t3", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "t2", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "t1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s32"}, {"n": "zero", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,470 | [
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMMLA", "code": "__int64 __fastcall trans_SMMLA ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smmla ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,471 | [
"{\"name\": \"op_smmla\", \"code\": \"__int64 __fastcall op_smmla ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { bool @@v4@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v4@@ ) return Number L ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_muls2_i32 ( @@v9@@ , @@v8@@ , @@v8@@ , @@v9@@ ) ; if ( * @@a2@@ != Number ) { @@v10@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; if ( @@a4@@ ) { @@v11@@ = tcg_const_i32 ( Number L ) ; tcg_gen_sub2_i32 ( @@v9@@ , @@v8@@ , @@v11@@ , @@v10@@ , @@v9@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; } else { tcg_gen_add_i32 ( @@v8@@ , @@v8@@ , @@v10@@ ) ; } tcg_temp_free_i32 ( @@v10@@ ) ; } if ( @@a3@@ ) { tcg_gen_shri_i32 ( @@v9@@ , @@v9@@ , Number L ) ; tcg_gen_add_i32 ( @@v8@@ , @@v8@@ , @@v9@@ ) ; } tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMMLAR", "code": "__int64 __fastcall trans_SMMLAR ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smmla ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,472 | [
"{\"name\": \"op_smmla\", \"code\": \"__int64 __fastcall op_smmla ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { bool @@v4@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v4@@ ) return Number L ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_muls2_i32 ( @@v9@@ , @@v8@@ , @@v8@@ , @@v9@@ ) ; if ( * @@a2@@ != Number ) { @@v10@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; if ( @@a4@@ ) { @@v11@@ = tcg_const_i32 ( Number L ) ; tcg_gen_sub2_i32 ( @@v9@@ , @@v8@@ , @@v11@@ , @@v10@@ , @@v9@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; } else { tcg_gen_add_i32 ( @@v8@@ , @@v8@@ , @@v10@@ ) ; } tcg_temp_free_i32 ( @@v10@@ ) ; } if ( @@a3@@ ) { tcg_gen_shri_i32 ( @@v9@@ , @@v9@@ , Number L ) ; tcg_gen_add_i32 ( @@v8@@ , @@v8@@ , @@v9@@ ) ; } tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_SMMLA\", \"code\": \"__int64 __fastcall trans_SMMLA ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smmla ( @@a1@@ , @@a2@@ , Number , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}"
] |
{"name": "trans_SMMLS", "code": "__int64 __fastcall trans_SMMLS ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smmla ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,473 | [
"{\"name\": \"op_smmla\", \"code\": \"__int64 __fastcall op_smmla ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { bool @@v4@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v4@@ ) return Number L ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_muls2_i32 ( @@v9@@ , @@v8@@ , @@v8@@ , @@v9@@ ) ; if ( * @@a2@@ != Number ) { @@v10@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; if ( @@a4@@ ) { @@v11@@ = tcg_const_i32 ( Number L ) ; tcg_gen_sub2_i32 ( @@v9@@ , @@v8@@ , @@v11@@ , @@v10@@ , @@v9@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; } else { tcg_gen_add_i32 ( @@v8@@ , @@v8@@ , @@v10@@ ) ; } tcg_temp_free_i32 ( @@v10@@ ) ; } if ( @@a3@@ ) { tcg_gen_shri_i32 ( @@v9@@ , @@v9@@ , Number L ) ; tcg_gen_add_i32 ( @@v8@@ , @@v8@@ , @@v9@@ ) ; } tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_SMMLSR", "code": "__int64 __fastcall trans_SMMLSR ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smmla ( @@a1@@ , @@a2@@ , Number , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,474 | [
"{\"name\": \"op_smmla\", \"code\": \"__int64 __fastcall op_smmla ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ , char @@a4@@ ) { bool @@v4@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; else @@v4@@ = ! arm_dc_feature ( @@a1@@ , Number ) ; if ( @@v4@@ ) return Number L ; @@v8@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_muls2_i32 ( @@v9@@ , @@v8@@ , @@v8@@ , @@v9@@ ) ; if ( * @@a2@@ != Number ) { @@v10@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; if ( @@a4@@ ) { @@v11@@ = tcg_const_i32 ( Number L ) ; tcg_gen_sub2_i32 ( @@v9@@ , @@v8@@ , @@v11@@ , @@v10@@ , @@v9@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; } else { tcg_gen_add_i32 ( @@v8@@ , @@v8@@ , @@v10@@ ) ; } tcg_temp_free_i32 ( @@v10@@ ) ; } if ( @@a3@@ ) { tcg_gen_shri_i32 ( @@v9@@ , @@v9@@ , Number L ) ; tcg_gen_add_i32 ( @@v8@@ , @@v8@@ , @@v9@@ ) ; } tcg_temp_free_i32 ( @@v9@@ ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_SMMLS\", \"code\": \"__int64 __fastcall trans_SMMLS ( __int64 @@a1@@ , int * @@a2@@ ) { return op_smmla ( @@a1@@ , @@a2@@ , Number , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}]}"
] |
{"name": "op_div", "code": "__int64 __fastcall op_div ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! isar_feature_thumb_div ( * ( unsigned int * * ) ( @@a1@@ + Number ) ) ; else @@v3@@ = ! isar_feature_arm_div ( * ( unsigned int * * ) ( @@a1@@ + Number ) ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) gen_helper_udiv ( @@v6@@ , @@v6@@ , @@v7@@ ) ; else gen_helper_sdiv ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "char", "s": 1}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "u", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "t1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "t2", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,475 | [
"{\"name\": \"isar_feature_thumb_div\", \"code\": \"bool __fastcall isar_feature_thumb_div ( unsigned int * @@a1@@ ) { return ( unsigned int ) extract32 ( * @@a1@@ , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_arm_div\", \"code\": \"bool __fastcall isar_feature_arm_div ( unsigned int * @@a1@@ ) { return ( unsigned int ) extract32 ( * @@a1@@ , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_sdiv\", \"code\": \"unsigned __int64 __fastcall gen_helper_sdiv ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_sdiv , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_udiv\", \"code\": \"unsigned __int64 __fastcall gen_helper_udiv ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_udiv , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "trans_SDIV", "code": "__int64 __fastcall trans_SDIV ( __int64 @@a1@@ , int * @@a2@@ ) { return op_div ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,476 | [
"{\"name\": \"op_div\", \"code\": \"__int64 __fastcall op_div ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! isar_feature_thumb_div ( * ( unsigned int * * ) ( @@a1@@ + Number ) ) ; else @@v3@@ = ! isar_feature_arm_div ( * ( unsigned int * * ) ( @@a1@@ + Number ) ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) gen_helper_udiv ( @@v6@@ , @@v6@@ , @@v7@@ ) ; else gen_helper_sdiv ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_UDIV", "code": "__int64 __fastcall trans_UDIV ( __int64 @@a1@@ , int * @@a2@@ ) { return op_div ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_rrr"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,477 | [
"{\"name\": \"op_div\", \"code\": \"__int64 __fastcall op_div ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ ) { bool @@v3@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v3@@ = ! isar_feature_thumb_div ( * ( unsigned int * * ) ( @@a1@@ + Number ) ) ; else @@v3@@ = ! isar_feature_arm_div ( * ( unsigned int * * ) ( @@a1@@ + Number ) ) ; if ( @@v3@@ ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( @@a3@@ ) gen_helper_udiv ( @@v6@@ , @@v6@@ , @@v7@@ ) ; else gen_helper_sdiv ( @@v6@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; store_reg ( @@a1@@ , * @@a2@@ , @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "op_addr_block_pre", "code": "__int64 __fastcall op_addr_block_pre ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( * @@a2@@ ) { if ( @@a2@@ [ Number ] ) tcg_gen_addi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; else tcg_gen_addi_i32 ( @@v5@@ , @@v5@@ , ( unsigned int ) ( Number * @@a3@@ ) ) ; } else if ( ! @@a2@@ [ Number ] && @@a3@@ != Number ) { tcg_gen_addi_i32 ( @@v5@@ , @@v5@@ , ( unsigned int ) ( Number * ( Number - @@a3@@ ) ) ) ; } if ( * ( _BYTE * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] ) gen_helper_v8m_stackcheck ( cpu_env , @@v5@@ ) ; return @@v5@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "n", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_block"}, "location": "r64"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,478 | [
"{\"name\": \"gen_helper_v8m_stackcheck\", \"code\": \"unsigned __int64 __fastcall gen_helper_v8m_stackcheck ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_v8m_stackcheck , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "op_addr_block_post", "code": "__int64 __fastcall op_addr_block_post ( __int64 @@a1@@ , _DWORD * @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { if ( ! @@a2@@ [ Number ] ) return tcg_temp_free_i32 ( @@a3@@ ) ; if ( * @@a2@@ ) { if ( ! @@a2@@ [ Number ] && @@a4@@ != Number ) tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , ( unsigned int ) ( Number * ( Number - @@a4@@ ) ) ) ; } else if ( @@a2@@ [ Number ] ) { tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , Number L ) ; } else { tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , ( unsigned int ) ( Number * @@a4@@ ) ) ; } return store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}]} | [{"n": "addr", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "n", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_block"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,479 | [
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "op_stm", "code": "__int64 __fastcall op_stm ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ ) { __int64 @@result@@ ; bool @@v5@@ ; int @@i@@ ; int @@v7@@ ; int @@v8@@ ; int @@v9@@ ; int @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; @@v5@@ = @@a2@@ [ Number ] != Number ; if ( @@a2@@ [ Number ] && * ( _DWORD * ) ( @@a1@@ + Number ) || ( @@v8@@ = @@a2@@ [ Number ] , @@v9@@ = ctpop16 ( @@v8@@ ) , @@v9@@ < @@a3@@ ) || @@a2@@ [ Number ] == Number ) { unallocated_encoding ( @@a1@@ ) ; @@result@@ = Number L ; } else { @@v12@@ = op_addr_block_pre ( @@a1@@ , @@a2@@ , @@v9@@ ) ; @@v10@@ = get_mem_index ( @@a1@@ ) ; @@v7@@ = Number ; for ( @@i@@ = Number ; @@i@@ <= Number ; ++ @@i@@ ) { if ( ( ( @@v8@@ >> @@i@@ ) & Number ) != Number ) { if ( ! @@v5@@ || @@i@@ == Number ) { @@v11@@ = load_reg ( @@a1@@ , @@i@@ ) ; } else { @@v11@@ = tcg_temp_new_i32 ( ) ; @@v13@@ = tcg_const_i32 ( ( unsigned int ) @@i@@ ) ; gen_helper_get_user_reg ( @@v11@@ , cpu_env , @@v13@@ ) ; tcg_temp_free_i32 ( @@v13@@ ) ; } gen_aa32_st32 ( @@a1@@ , @@v11@@ , @@v12@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; if ( ++ @@v7@@ != @@v9@@ ) tcg_gen_addi_i32 ( @@v12@@ , @@v12@@ , Number L ) ; } } op_addr_block_post ( @@a1@@ , @@a2@@ , @@v12@@ , @@v9@@ ) ; @@result@@ = Number L ; } return @@result@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v12", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v11", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v10", "t": {"T": 1, "n": "int", "s": 4}, "location": "s28"}, {"n": "v9", "t": {"T": 1, "n": "int", "s": 4}, "location": "s32"}, {"n": "v8", "t": {"T": 1, "n": "int", "s": 4}, "location": "s36"}, {"n": "v7", "t": {"T": 1, "n": "int", "s": 4}, "location": "s40"}, {"n": "i", "t": {"T": 1, "n": "int", "s": 4}, "location": "s44"}, {"n": "v5", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s45"}, {"n": "v13", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "min_n", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_block"}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r8"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "mem_idx", "t": {"T": 1, "n": "int", "s": 4}, "location": "s28"}, {"n": "n", "t": {"T": 1, "n": "int", "s": 4}, "location": "s32"}, {"n": "list", "t": {"T": 1, "n": "int", "s": 4}, "location": "s36"}, {"n": "j", "t": {"T": 1, "n": "int", "s": 4}, "location": "s40"}, {"n": "i", "t": {"T": 1, "n": "int", "s": 4}, "location": "s44"}, {"n": "user", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s45"}, {"n": "tmp2", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,480 | [
"{\"name\": \"ctpop16\", \"code\": \"__int64 __fastcall ctpop16 ( unsigned __int16 @@a1@@ ) { return _popcountdi2 ( @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int16\", \"s\": 2}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_get_user_reg\", \"code\": \"unsigned __int64 __fastcall gen_helper_get_user_reg ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_get_user_reg , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_aa32_st32\", \"code\": \"__int64 __fastcall gen_aa32_st32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_st_i32 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"op_addr_block_pre\", \"code\": \"__int64 __fastcall op_addr_block_pre ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( * @@a2@@ ) { if ( @@a2@@ [ Number ] ) tcg_gen_addi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; else tcg_gen_addi_i32 ( @@v5@@ , @@v5@@ , ( unsigned int ) ( Number * @@a3@@ ) ) ; } else if ( ! @@a2@@ [ Number ] && @@a3@@ != Number ) { tcg_gen_addi_i32 ( @@v5@@ , @@v5@@ , ( unsigned int ) ( Number * ( Number - @@a3@@ ) ) ) ; } if ( * ( _BYTE * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] ) gen_helper_v8m_stackcheck ( cpu_env , @@v5@@ ) ; return @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_addr_block_post\", \"code\": \"__int64 __fastcall op_addr_block_post ( __int64 @@a1@@ , _DWORD * @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { if ( ! @@a2@@ [ Number ] ) return tcg_temp_free_i32 ( @@a3@@ ) ; if ( * @@a2@@ ) { if ( ! @@a2@@ [ Number ] && @@a4@@ != Number ) tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , ( unsigned int ) ( Number * ( Number - @@a4@@ ) ) ) ; } else if ( @@a2@@ [ Number ] ) { tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , Number L ) ; } else { tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , ( unsigned int ) ( Number * @@a4@@ ) ) ; } return store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}]}"
] |
{"name": "trans_STM", "code": "__int64 __fastcall trans_STM ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { return op_stm ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_block"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,481 | [
"{\"name\": \"op_stm\", \"code\": \"__int64 __fastcall op_stm ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ ) { __int64 @@result@@ ; bool @@v5@@ ; int @@i@@ ; int @@v7@@ ; int @@v8@@ ; int @@v9@@ ; int @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; @@v5@@ = @@a2@@ [ Number ] != Number ; if ( @@a2@@ [ Number ] && * ( _DWORD * ) ( @@a1@@ + Number ) || ( @@v8@@ = @@a2@@ [ Number ] , @@v9@@ = ctpop16 ( @@v8@@ ) , @@v9@@ < @@a3@@ ) || @@a2@@ [ Number ] == Number ) { unallocated_encoding ( @@a1@@ ) ; @@result@@ = Number L ; } else { @@v12@@ = op_addr_block_pre ( @@a1@@ , @@a2@@ , @@v9@@ ) ; @@v10@@ = get_mem_index ( @@a1@@ ) ; @@v7@@ = Number ; for ( @@i@@ = Number ; @@i@@ <= Number ; ++ @@i@@ ) { if ( ( ( @@v8@@ >> @@i@@ ) & Number ) != Number ) { if ( ! @@v5@@ || @@i@@ == Number ) { @@v11@@ = load_reg ( @@a1@@ , @@i@@ ) ; } else { @@v11@@ = tcg_temp_new_i32 ( ) ; @@v13@@ = tcg_const_i32 ( ( unsigned int ) @@i@@ ) ; gen_helper_get_user_reg ( @@v11@@ , cpu_env , @@v13@@ ) ; tcg_temp_free_i32 ( @@v13@@ ) ; } gen_aa32_st32 ( @@a1@@ , @@v11@@ , @@v12@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; if ( ++ @@v7@@ != @@v9@@ ) tcg_gen_addi_i32 ( @@v12@@ , @@v12@@ , Number L ) ; } } op_addr_block_post ( @@a1@@ , @@a2@@ , @@v12@@ , @@v9@@ ) ; @@result@@ = Number L ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s28\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s32\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s40\"}, {\"n\": \"i\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s44\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s45\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_STM_t32", "code": "__int64 __fastcall trans_STM_t32 ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { if ( ! @@a2@@ [ Number ] || ( ( ( int ) @@a2@@ [ Number ] >> @@a2@@ [ Number ] ) & Number ) == Number ) return op_stm ( @@a1@@ , @@a2@@ , Number ) ; unallocated_encoding ( @@a1@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_block"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,482 | [
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"op_stm\", \"code\": \"__int64 __fastcall op_stm ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ ) { __int64 @@result@@ ; bool @@v5@@ ; int @@i@@ ; int @@v7@@ ; int @@v8@@ ; int @@v9@@ ; int @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; @@v5@@ = @@a2@@ [ Number ] != Number ; if ( @@a2@@ [ Number ] && * ( _DWORD * ) ( @@a1@@ + Number ) || ( @@v8@@ = @@a2@@ [ Number ] , @@v9@@ = ctpop16 ( @@v8@@ ) , @@v9@@ < @@a3@@ ) || @@a2@@ [ Number ] == Number ) { unallocated_encoding ( @@a1@@ ) ; @@result@@ = Number L ; } else { @@v12@@ = op_addr_block_pre ( @@a1@@ , @@a2@@ , @@v9@@ ) ; @@v10@@ = get_mem_index ( @@a1@@ ) ; @@v7@@ = Number ; for ( @@i@@ = Number ; @@i@@ <= Number ; ++ @@i@@ ) { if ( ( ( @@v8@@ >> @@i@@ ) & Number ) != Number ) { if ( ! @@v5@@ || @@i@@ == Number ) { @@v11@@ = load_reg ( @@a1@@ , @@i@@ ) ; } else { @@v11@@ = tcg_temp_new_i32 ( ) ; @@v13@@ = tcg_const_i32 ( ( unsigned int ) @@i@@ ) ; gen_helper_get_user_reg ( @@v11@@ , cpu_env , @@v13@@ ) ; tcg_temp_free_i32 ( @@v13@@ ) ; } gen_aa32_st32 ( @@a1@@ , @@v11@@ , @@v12@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; if ( ++ @@v7@@ != @@v9@@ ) tcg_gen_addi_i32 ( @@v12@@ , @@v12@@ , Number L ) ; } } op_addr_block_post ( @@a1@@ , @@a2@@ , @@v12@@ , @@v9@@ ) ; @@result@@ = Number L ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s28\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s32\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s40\"}, {\"n\": \"i\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s44\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s45\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"trans_STM\", \"code\": \"__int64 __fastcall trans_STM ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { return op_stm ( @@a1@@ , @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}]}"
] |
{"name": "do_ldm", "code": "__int64 __fastcall do_ldm ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ ) { __int64 v4 ; char @@v7@@ ; bool @@v8@@ ; char @@v9@@ ; int @@i@@ ; int @@v11@@ ; int @@v12@@ ; int @@v13@@ ; int @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; __int64 v17 ; __int64 v18 ; @@v8@@ = @@a2@@ [ Number ] != Number ; @@v9@@ = Number ; if ( @@a2@@ [ Number ] ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { LABEL_3 : unallocated_encoding ( @@a1@@ ) ; return Number L ; } if ( ( unsigned int ) extract32 ( @@a2@@ [ Number ] , Number , Number ) ) { @@v9@@ = Number ; @@v8@@ = Number ; } else if ( @@a2@@ [ Number ] ) { goto LABEL_3 ; } } @@v12@@ = @@a2@@ [ Number ] ; @@v13@@ = ctpop16 ( @@v12@@ ) ; if ( @@v13@@ < @@a3@@ || @@a2@@ [ Number ] == Number ) goto LABEL_3 ; @@v16@@ = op_addr_block_pre ( @@a1@@ , @@a2@@ , @@v13@@ ) ; @@v14@@ = get_mem_index ( @@a1@@ ) ; @@v7@@ = Number ; @@v15@@ = Number L ; @@v11@@ = Number ; for ( @@i@@ = Number ; @@i@@ <= Number ; ++ @@i@@ ) { if ( ( ( @@v12@@ >> @@i@@ ) & Number ) != Number ) { v17 = tcg_temp_new_i32 ( ) ; gen_aa32_ld32u ( @@a1@@ , v17 , @@v16@@ , @@v14@@ ) ; if ( @@v8@@ ) { v4 = tcg_const_i32 ( ( unsigned int ) @@i@@ ) ; gen_helper_set_user_reg ( cpu_env , v4 , v17 ) ; tcg_temp_free_i32 ( v4 ) ; tcg_temp_free_i32 ( v17 ) ; } else if ( @@i@@ == @@a2@@ [ Number ] ) { @@v15@@ = v17 ; @@v7@@ = Number ; } else if ( @@i@@ == Number && @@v9@@ ) { store_pc_exc_ret ( @@a1@@ , v17 ) ; } else { store_reg_from_load ( @@a1@@ , @@i@@ , v17 ) ; } if ( ++ @@v11@@ != @@v13@@ ) tcg_gen_addi_i32 ( @@v16@@ , @@v16@@ , Number L ) ; } } op_addr_block_post ( @@a1@@ , @@a2@@ , @@v16@@ , @@v13@@ ) ; if ( @@v7@@ ) store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; if ( @@v9@@ ) { v18 = load_cpu_offset ( Number ) ; if ( ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number ) gen_io_start ( ) ; gen_helper_cpsr_write_eret ( cpu_env , v18 ) ; if ( ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number ) gen_io_end ( ) ; tcg_temp_free_i32 ( v18 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v16", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v15", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "v14", "t": {"T": 1, "n": "int", "s": 4}, "location": "s36"}, {"n": "v13", "t": {"T": 1, "n": "int", "s": 4}, "location": "s40"}, {"n": "v12", "t": {"T": 1, "n": "int", "s": 4}, "location": "s44"}, {"n": "v11", "t": {"T": 1, "n": "int", "s": 4}, "location": "s48"}, {"n": "i", "t": {"T": 1, "n": "int", "s": 4}, "location": "s52"}, {"n": "v9", "t": {"T": 1, "n": "char", "s": 1}, "location": "s53"}, {"n": "v8", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s54"}, {"n": "v7", "t": {"T": 1, "n": "char", "s": 1}, "location": "s55"}]} | [{"n": "min_n", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_block"}, "location": "r64"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "loaded_var", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s32"}, {"n": "mem_idx", "t": {"T": 1, "n": "int", "s": 4}, "location": "s36"}, {"n": "n", "t": {"T": 1, "n": "int", "s": 4}, "location": "s40"}, {"n": "list", "t": {"T": 1, "n": "int", "s": 4}, "location": "s44"}, {"n": "j", "t": {"T": 1, "n": "int", "s": 4}, "location": "s48"}, {"n": "i", "t": {"T": 1, "n": "int", "s": 4}, "location": "s52"}, {"n": "exc_return", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s53"}, {"n": "user", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s54"}, {"n": "loaded_base", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s55"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,483 | [
"{\"name\": \"ctpop16\", \"code\": \"__int64 __fastcall ctpop16 ( unsigned __int16 @@a1@@ ) { return _popcountdi2 ( @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned __int16\", \"s\": 2}, \"location\": \"r56\"}]}",
"{\"name\": \"extract32\", \"code\": \"__int64 __fastcall extract32 ( unsigned int @@a1@@ , int @@a2@@ , int @@a3@@ ) { if ( @@a2@@ < Number || @@a3@@ <= Number || @@a3@@ > Number - @@a2@@ ) _assert_fail ( String , String , Number , String ) ; return ( @@a1@@ >> @@a2@@ ) & ( Number >> ( Number - @@a3@@ ) ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tb_cflags\", \"code\": \"__int64 __fastcall tb_cflags ( __int64 @@a1@@ ) { return * ( unsigned int * ) ( @@a1@@ + Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_helper_cpsr_write\", \"code\": \"unsigned __int64 __fastcall gen_helper_cpsr_write ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_cpsr_write , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_cpsr_write_eret\", \"code\": \"unsigned __int64 __fastcall gen_helper_cpsr_write_eret ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_cpsr_write_eret , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_set_user_reg\", \"code\": \"unsigned __int64 __fastcall gen_helper_set_user_reg ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_set_user_reg , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_io_start\", \"code\": \"__int64 gen_io_start ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_const_i32 ( Number L ) ; tcg_gen_st_i32 ( @@v1@@ , cpu_env , Number ) ; return tcg_temp_free_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_io_end\", \"code\": \"__int64 gen_io_end ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_const_i32 ( Number L ) ; tcg_gen_st_i32 ( @@v1@@ , cpu_env , Number ) ; return tcg_temp_free_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_cpu_offset\", \"code\": \"__int64 __fastcall load_cpu_offset ( int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v2@@ , cpu_env , @@a1@@ ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"store_reg_from_load\", \"code\": \"__int64 __fastcall store_reg_from_load ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@result@@ ; if ( @@a2@@ == Number && arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = gen_bx_excret ( @@a1@@ , @@a3@@ ) ; else @@result@@ = store_reg ( @@a1@@ , @@a2@@ , @@a3@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_aa32_ld32u\", \"code\": \"__int64 __fastcall gen_aa32_ld32u ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_ld_i32 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"store_pc_exc_ret\", \"code\": \"__int64 __fastcall store_pc_exc_ret ( __int64 @@a1@@ , __int64 @@a2@@ ) { tcg_gen_mov_i32 ( qword_4BEB8 , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"op_addr_block_pre\", \"code\": \"__int64 __fastcall op_addr_block_pre ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; if ( * @@a2@@ ) { if ( @@a2@@ [ Number ] ) tcg_gen_addi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; else tcg_gen_addi_i32 ( @@v5@@ , @@v5@@ , ( unsigned int ) ( Number * @@a3@@ ) ) ; } else if ( ! @@a2@@ [ Number ] && @@a3@@ != Number ) { tcg_gen_addi_i32 ( @@v5@@ , @@v5@@ , ( unsigned int ) ( Number * ( Number - @@a3@@ ) ) ) ; } if ( * ( _BYTE * ) ( @@a1@@ + Number ) && @@a2@@ [ Number ] == Number && @@a2@@ [ Number ] ) gen_helper_v8m_stackcheck ( cpu_env , @@v5@@ ) ; return @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"op_addr_block_post\", \"code\": \"__int64 __fastcall op_addr_block_post ( __int64 @@a1@@ , _DWORD * @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { if ( ! @@a2@@ [ Number ] ) return tcg_temp_free_i32 ( @@a3@@ ) ; if ( * @@a2@@ ) { if ( ! @@a2@@ [ Number ] && @@a4@@ != Number ) tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , ( unsigned int ) ( Number * ( Number - @@a4@@ ) ) ) ; } else if ( @@a2@@ [ Number ] ) { tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , Number L ) ; } else { tcg_gen_addi_i32 ( @@a3@@ , @@a3@@ , ( unsigned int ) ( Number * @@a4@@ ) ) ; } return store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}]}"
] |
{"name": "trans_LDM_a32", "code": "__int64 __fastcall trans_LDM_a32 ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { if ( ! arm_dc_feature ( @@a1@@ , Number ) || ! @@a2@@ [ Number ] || ( ( ( int ) @@a2@@ [ Number ] >> @@a2@@ [ Number ] ) & Number ) == Number ) return do_ldm ( @@a1@@ , @@a2@@ , Number ) ; unallocated_encoding ( @@a1@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_block"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,484 | [
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"do_ldm\", \"code\": \"__int64 __fastcall do_ldm ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ ) { __int64 v4 ; char @@v7@@ ; bool @@v8@@ ; char @@v9@@ ; int @@i@@ ; int @@v11@@ ; int @@v12@@ ; int @@v13@@ ; int @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; __int64 v17 ; __int64 v18 ; @@v8@@ = @@a2@@ [ Number ] != Number ; @@v9@@ = Number ; if ( @@a2@@ [ Number ] ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { LABEL_3 : unallocated_encoding ( @@a1@@ ) ; return Number L ; } if ( ( unsigned int ) extract32 ( @@a2@@ [ Number ] , Number , Number ) ) { @@v9@@ = Number ; @@v8@@ = Number ; } else if ( @@a2@@ [ Number ] ) { goto LABEL_3 ; } } @@v12@@ = @@a2@@ [ Number ] ; @@v13@@ = ctpop16 ( @@v12@@ ) ; if ( @@v13@@ < @@a3@@ || @@a2@@ [ Number ] == Number ) goto LABEL_3 ; @@v16@@ = op_addr_block_pre ( @@a1@@ , @@a2@@ , @@v13@@ ) ; @@v14@@ = get_mem_index ( @@a1@@ ) ; @@v7@@ = Number ; @@v15@@ = Number L ; @@v11@@ = Number ; for ( @@i@@ = Number ; @@i@@ <= Number ; ++ @@i@@ ) { if ( ( ( @@v12@@ >> @@i@@ ) & Number ) != Number ) { v17 = tcg_temp_new_i32 ( ) ; gen_aa32_ld32u ( @@a1@@ , v17 , @@v16@@ , @@v14@@ ) ; if ( @@v8@@ ) { v4 = tcg_const_i32 ( ( unsigned int ) @@i@@ ) ; gen_helper_set_user_reg ( cpu_env , v4 , v17 ) ; tcg_temp_free_i32 ( v4 ) ; tcg_temp_free_i32 ( v17 ) ; } else if ( @@i@@ == @@a2@@ [ Number ] ) { @@v15@@ = v17 ; @@v7@@ = Number ; } else if ( @@i@@ == Number && @@v9@@ ) { store_pc_exc_ret ( @@a1@@ , v17 ) ; } else { store_reg_from_load ( @@a1@@ , @@i@@ , v17 ) ; } if ( ++ @@v11@@ != @@v13@@ ) tcg_gen_addi_i32 ( @@v16@@ , @@v16@@ , Number L ) ; } } op_addr_block_post ( @@a1@@ , @@a2@@ , @@v16@@ , @@v13@@ ) ; if ( @@v7@@ ) store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; if ( @@v9@@ ) { v18 = load_cpu_offset ( Number ) ; if ( ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number ) gen_io_start ( ) ; gen_helper_cpsr_write_eret ( cpu_env , v18 ) ; if ( ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number ) gen_io_end ( ) ; tcg_temp_free_i32 ( v18 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s40\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s44\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s48\"}, {\"n\": \"i\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s52\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s53\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s54\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s55\"}]}"
] |
{"name": "trans_LDM_t32", "code": "__int64 __fastcall trans_LDM_t32 ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { if ( ! @@a2@@ [ Number ] || ( ( ( int ) @@a2@@ [ Number ] >> @@a2@@ [ Number ] ) & Number ) == Number ) return do_ldm ( @@a1@@ , @@a2@@ , Number ) ; unallocated_encoding ( @@a1@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_block"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,485 | [
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"do_ldm\", \"code\": \"__int64 __fastcall do_ldm ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ ) { __int64 v4 ; char @@v7@@ ; bool @@v8@@ ; char @@v9@@ ; int @@i@@ ; int @@v11@@ ; int @@v12@@ ; int @@v13@@ ; int @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; __int64 v17 ; __int64 v18 ; @@v8@@ = @@a2@@ [ Number ] != Number ; @@v9@@ = Number ; if ( @@a2@@ [ Number ] ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { LABEL_3 : unallocated_encoding ( @@a1@@ ) ; return Number L ; } if ( ( unsigned int ) extract32 ( @@a2@@ [ Number ] , Number , Number ) ) { @@v9@@ = Number ; @@v8@@ = Number ; } else if ( @@a2@@ [ Number ] ) { goto LABEL_3 ; } } @@v12@@ = @@a2@@ [ Number ] ; @@v13@@ = ctpop16 ( @@v12@@ ) ; if ( @@v13@@ < @@a3@@ || @@a2@@ [ Number ] == Number ) goto LABEL_3 ; @@v16@@ = op_addr_block_pre ( @@a1@@ , @@a2@@ , @@v13@@ ) ; @@v14@@ = get_mem_index ( @@a1@@ ) ; @@v7@@ = Number ; @@v15@@ = Number L ; @@v11@@ = Number ; for ( @@i@@ = Number ; @@i@@ <= Number ; ++ @@i@@ ) { if ( ( ( @@v12@@ >> @@i@@ ) & Number ) != Number ) { v17 = tcg_temp_new_i32 ( ) ; gen_aa32_ld32u ( @@a1@@ , v17 , @@v16@@ , @@v14@@ ) ; if ( @@v8@@ ) { v4 = tcg_const_i32 ( ( unsigned int ) @@i@@ ) ; gen_helper_set_user_reg ( cpu_env , v4 , v17 ) ; tcg_temp_free_i32 ( v4 ) ; tcg_temp_free_i32 ( v17 ) ; } else if ( @@i@@ == @@a2@@ [ Number ] ) { @@v15@@ = v17 ; @@v7@@ = Number ; } else if ( @@i@@ == Number && @@v9@@ ) { store_pc_exc_ret ( @@a1@@ , v17 ) ; } else { store_reg_from_load ( @@a1@@ , @@i@@ , v17 ) ; } if ( ++ @@v11@@ != @@v13@@ ) tcg_gen_addi_i32 ( @@v16@@ , @@v16@@ , Number L ) ; } } op_addr_block_post ( @@a1@@ , @@a2@@ , @@v16@@ , @@v13@@ ) ; if ( @@v7@@ ) store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; if ( @@v9@@ ) { v18 = load_cpu_offset ( Number ) ; if ( ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number ) gen_io_start ( ) ; gen_helper_cpsr_write_eret ( cpu_env , v18 ) ; if ( ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number ) gen_io_end ( ) ; tcg_temp_free_i32 ( v18 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s40\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s44\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s48\"}, {\"n\": \"i\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s52\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s53\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s54\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s55\"}]}"
] |
{"name": "trans_LDM_t16", "code": "__int64 __fastcall trans_LDM_t16 ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { @@a2@@ [ Number ] = ( ( ( int ) @@a2@@ [ Number ] >> @@a2@@ [ Number ] ) & Number ) == Number ; return do_ldm ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ldst_block"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,486 | [
"{\"name\": \"do_ldm\", \"code\": \"__int64 __fastcall do_ldm ( __int64 @@a1@@ , _DWORD * @@a2@@ , int @@a3@@ ) { __int64 v4 ; char @@v7@@ ; bool @@v8@@ ; char @@v9@@ ; int @@i@@ ; int @@v11@@ ; int @@v12@@ ; int @@v13@@ ; int @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; __int64 v17 ; __int64 v18 ; @@v8@@ = @@a2@@ [ Number ] != Number ; @@v9@@ = Number ; if ( @@a2@@ [ Number ] ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { LABEL_3 : unallocated_encoding ( @@a1@@ ) ; return Number L ; } if ( ( unsigned int ) extract32 ( @@a2@@ [ Number ] , Number , Number ) ) { @@v9@@ = Number ; @@v8@@ = Number ; } else if ( @@a2@@ [ Number ] ) { goto LABEL_3 ; } } @@v12@@ = @@a2@@ [ Number ] ; @@v13@@ = ctpop16 ( @@v12@@ ) ; if ( @@v13@@ < @@a3@@ || @@a2@@ [ Number ] == Number ) goto LABEL_3 ; @@v16@@ = op_addr_block_pre ( @@a1@@ , @@a2@@ , @@v13@@ ) ; @@v14@@ = get_mem_index ( @@a1@@ ) ; @@v7@@ = Number ; @@v15@@ = Number L ; @@v11@@ = Number ; for ( @@i@@ = Number ; @@i@@ <= Number ; ++ @@i@@ ) { if ( ( ( @@v12@@ >> @@i@@ ) & Number ) != Number ) { v17 = tcg_temp_new_i32 ( ) ; gen_aa32_ld32u ( @@a1@@ , v17 , @@v16@@ , @@v14@@ ) ; if ( @@v8@@ ) { v4 = tcg_const_i32 ( ( unsigned int ) @@i@@ ) ; gen_helper_set_user_reg ( cpu_env , v4 , v17 ) ; tcg_temp_free_i32 ( v4 ) ; tcg_temp_free_i32 ( v17 ) ; } else if ( @@i@@ == @@a2@@ [ Number ] ) { @@v15@@ = v17 ; @@v7@@ = Number ; } else if ( @@i@@ == Number && @@v9@@ ) { store_pc_exc_ret ( @@a1@@ , v17 ) ; } else { store_reg_from_load ( @@a1@@ , @@i@@ , v17 ) ; } if ( ++ @@v11@@ != @@v13@@ ) tcg_gen_addi_i32 ( @@v16@@ , @@v16@@ , Number L ) ; } } op_addr_block_post ( @@a1@@ , @@a2@@ , @@v16@@ , @@v13@@ ) ; if ( @@v7@@ ) store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v15@@ ) ; if ( @@v9@@ ) { v18 = load_cpu_offset ( Number ) ; if ( ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number ) gen_io_start ( ) ; gen_helper_cpsr_write_eret ( cpu_env , v18 ) ; if ( ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number ) gen_io_end ( ) ; tcg_temp_free_i32 ( v18 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s40\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s44\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s48\"}, {\"n\": \"i\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s52\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s53\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s54\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s55\"}]}"
] |
{"name": "trans_B", "code": "__int64 __fastcall trans_B ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_i"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,487 | [
"{\"name\": \"read_pc\", \"code\": \"__int64 __fastcall read_pc ( __int64 @@a1@@ ) { int @@v1@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v1@@ = Number ; else @@v1@@ = Number ; return ( unsigned int ) * ( _QWORD * ) ( @@a1@@ + Number ) + @@v1@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_jmp\", \"code\": \"__int64 __fastcall gen_jmp ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@result@@ ; if ( ! is_singlestepping ( @@a1@@ ) ) return gen_goto_tb ( @@a1@@ , Number , @@a2@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_B_cond_thumb", "code": "__int64 __fastcall trans_B_cond_thumb ( __int64 @@a1@@ , int * @@a2@@ ) { int @@v3@@ ; if ( * @@a2@@ > Number ) return Number L ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { unallocated_encoding ( @@a1@@ ) ; } else { arm_skip_unless ( @@a1@@ , * @@a2@@ ) ; @@v3@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v3@@ + @@a2@@ [ Number ] ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_ci"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,488 | [
"{\"name\": \"read_pc\", \"code\": \"__int64 __fastcall read_pc ( __int64 @@a1@@ ) { int @@v1@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v1@@ = Number ; else @@v1@@ = Number ; return ( unsigned int ) * ( _QWORD * ) ( @@a1@@ + Number ) + @@v1@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_jmp\", \"code\": \"__int64 __fastcall gen_jmp ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@result@@ ; if ( ! is_singlestepping ( @@a1@@ ) ) return gen_goto_tb ( @@a1@@ , Number , @@a2@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_skip_unless\", \"code\": \"unsigned __int64 __fastcall arm_skip_unless ( __int64 @@a1@@ , int @@a2@@ ) { arm_gen_condlabel ( @@a1@@ ) ; return arm_gen_test_cc ( @@a2@@ ^ Number , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"trans_B\", \"code\": \"__int64 __fastcall trans_B ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_BL", "code": "__int64 __fastcall trans_BL ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; tcg_gen_movi_i32 ( qword_4BEB0 , * ( _QWORD * ) ( @@a1@@ + Number ) | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_i"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,489 | [
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"read_pc\", \"code\": \"__int64 __fastcall read_pc ( __int64 @@a1@@ ) { int @@v1@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v1@@ = Number ; else @@v1@@ = Number ; return ( unsigned int ) * ( _QWORD * ) ( @@a1@@ + Number ) + @@v1@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_jmp\", \"code\": \"__int64 __fastcall gen_jmp ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@result@@ ; if ( ! is_singlestepping ( @@a1@@ ) ) return gen_goto_tb ( @@a1@@ , Number , @@a2@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_B\", \"code\": \"__int64 __fastcall trans_B ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_BLX_i", "code": "__int64 __fastcall trans_BLX_i ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v3@@ ; __int64 @@v4@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) && ( * @@a2@@ & Number ) != Number ) return Number L ; tcg_gen_movi_i32 ( qword_4BEB0 , * ( _QWORD * ) ( @@a1@@ + Number ) | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; @@v4@@ = tcg_const_i32 ( * ( _DWORD * ) ( @@a1@@ + Number ) == Number ) ; store_cpu_offset ( @@v4@@ , Number ) ; @@v3@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , * @@a2@@ + ( @@v3@@ & Number ) ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_BLX_i"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,490 | [
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"store_cpu_offset\", \"code\": \"__int64 __fastcall store_cpu_offset ( __int64 @@a1@@ , int @@a2@@ ) { tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"read_pc\", \"code\": \"__int64 __fastcall read_pc ( __int64 @@a1@@ ) { int @@v1@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v1@@ = Number ; else @@v1@@ = Number ; return ( unsigned int ) * ( _QWORD * ) ( @@a1@@ + Number ) + @@v1@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_jmp\", \"code\": \"__int64 __fastcall gen_jmp ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@result@@ ; if ( ! is_singlestepping ( @@a1@@ ) ) return gen_goto_tb ( @@a1@@ , Number , @@a2@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_B\", \"code\": \"__int64 __fastcall trans_B ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_BL\", \"code\": \"__int64 __fastcall trans_BL ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; tcg_gen_movi_i32 ( qword_4BEB0 , * ( _QWORD * ) ( @@a1@@ + Number ) | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_BL_BLX_prefix", "code": "__int64 __fastcall trans_BL_BLX_prefix ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) _assert_fail ( String , String , Number , String ) ; @@v2@@ = read_pc ( @@a1@@ ) ; tcg_gen_movi_i32 ( qword_4BEB0 , ( * @@a2@@ << Number ) + @@v2@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_BL_BLX_prefix"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,491 | [
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"read_pc\", \"code\": \"__int64 __fastcall read_pc ( __int64 @@a1@@ ) { int @@v1@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v1@@ = Number ; else @@v1@@ = Number ; return ( unsigned int ) * ( _QWORD * ) ( @@a1@@ + Number ) + @@v1@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_B\", \"code\": \"__int64 __fastcall trans_B ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_BL\", \"code\": \"__int64 __fastcall trans_BL ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; tcg_gen_movi_i32 ( qword_4BEB0 , * ( _QWORD * ) ( @@a1@@ + Number ) | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_BL_suffix", "code": "__int64 __fastcall trans_BL_suffix ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; if ( arm_dc_feature ( @@a1@@ , Number ) ) _assert_fail ( String , String , Number , String ) ; tcg_gen_addi_i32 ( @@v3@@ , qword_4BEB0 , ( Number * * @@a2@@ ) | Number ) ; tcg_gen_movi_i32 ( qword_4BEB0 , * ( _QWORD * ) ( @@a1@@ + Number ) | Number ) ; gen_bx ( @@a1@@ , @@v3@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_BL_suffix"}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,492 | [
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_bx\", \"code\": \"__int64 __fastcall gen_bx ( __int64 @@a1@@ , __int64 @@a2@@ ) { * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; tcg_gen_andi_i32 ( qword_4BEB8 , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; return store_cpu_offset ( @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"trans_B\", \"code\": \"__int64 __fastcall trans_B ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_BL\", \"code\": \"__int64 __fastcall trans_BL ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; tcg_gen_movi_i32 ( qword_4BEB0 , * ( _QWORD * ) ( @@a1@@ + Number ) | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "trans_BLX_suffix", "code": "__int64 __fastcall trans_BLX_suffix ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) ) _assert_fail ( String , String , Number , String ) ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; @@v3@@ = tcg_temp_new_i32 ( ) ; tcg_gen_addi_i32 ( @@v3@@ , qword_4BEB0 , ( unsigned int ) ( Number * * @@a2@@ ) ) ; tcg_gen_andi_i32 ( @@v3@@ , @@v3@@ , Number L ) ; tcg_gen_movi_i32 ( qword_4BEB0 , * ( _QWORD * ) ( @@a1@@ + Number ) | Number ) ; gen_bx ( @@a1@@ , @@v3@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_BLX_suffix"}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,493 | [
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_bx\", \"code\": \"__int64 __fastcall gen_bx ( __int64 @@a1@@ , __int64 @@a2@@ ) { * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; tcg_gen_andi_i32 ( qword_4BEB8 , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; return store_cpu_offset ( @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"trans_B\", \"code\": \"__int64 __fastcall trans_B ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_BL\", \"code\": \"__int64 __fastcall trans_BL ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; tcg_gen_movi_i32 ( qword_4BEB0 , * ( _QWORD * ) ( @@a1@@ + Number ) | * ( _DWORD * ) ( @@a1@@ + Number ) ) ; @@v2@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v2@@ + * @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "op_tbranch", "code": "__int64 __fastcall op_tbranch ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ ) { int @@v3@@ ; int v4 ; unsigned int v5 ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v8@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; if ( @@a3@@ ) tcg_gen_add_i32 ( @@v8@@ , @@v8@@ , @@v8@@ ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_add_i32 ( @@v9@@ , @@v9@@ , @@v8@@ ) ; if ( @@a3@@ ) @@v3@@ = * ( _DWORD * ) ( @@a1@@ + Number ) | Number ; else @@v3@@ = Number ; v4 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v8@@ , @@v9@@ , v4 , @@v3@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_gen_add_i32 ( @@v8@@ , @@v8@@ , @@v8@@ ) ; v5 = read_pc ( @@a1@@ ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , v5 ) ; store_reg ( @@a1@@ , Number , @@v8@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "char", "s": 1}, "location": "r16"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r32"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}]} | [{"n": "half", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r16"}, {"n": "v3", "t": {"T": 1, "n": "__int32", "s": 4}, "location": "r32"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_tbranch"}, "location": "r64"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s32"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,494 | [
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"read_pc\", \"code\": \"__int64 __fastcall read_pc ( __int64 @@a1@@ ) { int @@v1@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v1@@ = Number ; else @@v1@@ = Number ; return ( unsigned int ) * ( _QWORD * ) ( @@a1@@ + Number ) + @@v1@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_aa32_ld_i32\", \"code\": \"__int64 __fastcall gen_aa32_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_ld_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_TBB", "code": "__int64 __fastcall trans_TBB ( __int64 @@a1@@ , int * @@a2@@ ) { return op_tbranch ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_tbranch"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,495 | [
"{\"name\": \"op_tbranch\", \"code\": \"__int64 __fastcall op_tbranch ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ ) { int @@v3@@ ; int v4 ; unsigned int v5 ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v8@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; if ( @@a3@@ ) tcg_gen_add_i32 ( @@v8@@ , @@v8@@ , @@v8@@ ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_add_i32 ( @@v9@@ , @@v9@@ , @@v8@@ ) ; if ( @@a3@@ ) @@v3@@ = * ( _DWORD * ) ( @@a1@@ + Number ) | Number ; else @@v3@@ = Number ; v4 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v8@@ , @@v9@@ , v4 , @@v3@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_gen_add_i32 ( @@v8@@ , @@v8@@ , @@v8@@ ) ; v5 = read_pc ( @@a1@@ ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , v5 ) ; store_reg ( @@a1@@ , Number , @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}]}"
] |
{"name": "trans_TBH", "code": "__int64 __fastcall trans_TBH ( __int64 @@a1@@ , int * @@a2@@ ) { return op_tbranch ( @@a1@@ , @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_tbranch"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,496 | [
"{\"name\": \"op_tbranch\", \"code\": \"__int64 __fastcall op_tbranch ( __int64 @@a1@@ , int * @@a2@@ , char @@a3@@ ) { int @@v3@@ ; int v4 ; unsigned int v5 ; __int64 @@v8@@ ; __int64 @@v9@@ ; @@v8@@ = load_reg ( @@a1@@ , * @@a2@@ ) ; if ( @@a3@@ ) tcg_gen_add_i32 ( @@v8@@ , @@v8@@ , @@v8@@ ) ; @@v9@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_add_i32 ( @@v9@@ , @@v9@@ , @@v8@@ ) ; if ( @@a3@@ ) @@v3@@ = * ( _DWORD * ) ( @@a1@@ + Number ) | Number ; else @@v3@@ = Number ; v4 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld_i32 ( @@a1@@ , @@v8@@ , @@v9@@ , v4 , @@v3@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_gen_add_i32 ( @@v8@@ , @@v8@@ , @@v8@@ ) ; v5 = read_pc ( @@a1@@ ) ; tcg_gen_addi_i32 ( @@v8@@ , @@v8@@ , v5 ) ; store_reg ( @@a1@@ , Number , @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}]}"
] |
{"name": "trans_CBZ", "code": "__int64 __fastcall trans_CBZ ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 v2 ; int @@v3@@ ; __int64 @@v6@@ ; @@v6@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; arm_gen_condlabel ( @@a1@@ ) ; if ( @@a2@@ [ Number ] ) v2 = Number L ; else v2 = Number L ; tcg_gen_brcondi_i32 ( v2 , @@v6@@ , Number L , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; tcg_temp_free_i32 ( @@v6@@ ) ; @@v3@@ = read_pc ( @@a1@@ ) ; gen_jmp ( @@a1@@ , @@v3@@ + * @@a2@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_CBZ"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,497 | [
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_br\", \"code\": \"__int64 __fastcall tcg_gen_br ( __int64 @@a1@@ ) { __int64 @@v1@@ ; ++ * ( _WORD * ) ( @@a1@@ + Number ) ; @@v1@@ = label_arg ( @@a1@@ ) ; return tcg_gen_op1 ( Number L , @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"read_pc\", \"code\": \"__int64 __fastcall read_pc ( __int64 @@a1@@ ) { int @@v1@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v1@@ = Number ; else @@v1@@ = Number ; return ( unsigned int ) * ( _QWORD * ) ( @@a1@@ + Number ) + @@v1@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_jmp\", \"code\": \"__int64 __fastcall gen_jmp ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@result@@ ; if ( ! is_singlestepping ( @@a1@@ ) ) return gen_goto_tb ( @@a1@@ , Number , @@a2@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_gen_condlabel\", \"code\": \"__int64 __fastcall arm_gen_condlabel ( __int64 @@a1@@ ) { __int64 @@result@@ ; @@result@@ = * ( unsigned int * ) ( @@a1@@ + Number ) ; if ( ! ( _DWORD ) @@result@@ ) { * ( _QWORD * ) ( @@a1@@ + Number ) = gen_new_label ( ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_SVC", "code": "__int64 __fastcall trans_SVC ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v2@@ ; int @@v4@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v2@@ = Number ; else @@v2@@ = Number ; @@v4@@ = @@v2@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) || ! ( unsigned __int8 ) semihosting_enabled ( ) || * ( _DWORD * ) ( @@a1@@ + Number ) || * @@a2@@ != @@v4@@ ) { gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = * @@a2@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } else { gen_exception_internal_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}, {"n": "v4", "t": {"T": 1, "n": "int", "s": 4}, "location": "s4"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_SVC"}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}, {"n": "semihost_imm", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s4"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,498 | [
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception_internal\", \"code\": \"__int64 __fastcall gen_exception_internal ( unsigned int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_const_i32 ( @@a1@@ ) ; if ( ! excp_is_internal ( @@a1@@ ) ) _assert_fail ( String , String , Number , String ) ; gen_helper_exception_internal ( cpu_env , @@v2@@ ) ; return tcg_temp_free_i32 ( @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_pc_im\", \"code\": \"__int64 __fastcall gen_set_pc_im ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_movi_i32 ( qword_4BEB8 , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_exception_internal_insn\", \"code\": \"__int64 __fastcall gen_exception_internal_insn ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@result@@ ; gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; gen_exception_internal ( @@a3@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_RFE", "code": "__int64 __fastcall trans_RFE ( __int64 @@a1@@ , int * @@a2@@ ) { __int64 result ; int v3 ; int v4 ; __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) || arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { unallocated_encoding ( @@a1@@ ) ; result = Number L ; } else { @@v5@@ = load_reg ( @@a1@@ , @@a2@@ [ Number ] ) ; tcg_gen_addi_i32 ( @@v5@@ , @@v5@@ , ( unsigned int ) pre_offset_62924 [ * @@a2@@ ] ) ; @@v6@@ = tcg_temp_new_i32 ( ) ; v3 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld32u ( @@a1@@ , @@v6@@ , @@v5@@ , v3 ) ; tcg_gen_addi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; @@v7@@ = tcg_temp_new_i32 ( ) ; v4 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld32u ( @@a1@@ , @@v7@@ , @@v5@@ , v4 ) ; if ( @@a2@@ [ Number ] ) { tcg_gen_addi_i32 ( @@v5@@ , @@v5@@ , ( unsigned int ) post_offset_62925 [ * @@a2@@ ] ) ; store_reg ( @@a1@@ , @@a2@@ [ Number ] , @@v5@@ ) ; } else { tcg_temp_free_i32 ( @@v5@@ ) ; } gen_rfe ( @@a1@@ , @@v6@@ , @@v7@@ ) ; result = Number L ; } return result ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_RFE"}, "location": "r64"}, {"n": "t1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "t2", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,499 | [
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_aa32_ld32u\", \"code\": \"__int64 __fastcall gen_aa32_ld32u ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_ld_i32 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_rfe\", \"code\": \"__int64 __fastcall gen_rfe ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@result@@ ; store_pc_exc_ret ( @@a1@@ , @@a2@@ ) ; if ( ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number ) gen_io_start ( ) ; gen_helper_cpsr_write_eret ( cpu_env , @@a3@@ ) ; tcg_temp_free_i32 ( @@a3@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "trans_SRS", "code": "__int64 __fastcall trans_SRS ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { if ( ! arm_dc_feature ( @@a1@@ , Number ) || arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; gen_srs ( @@a1@@ , * @@a2@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] != Number ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_SRS"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,500 | [
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_srs\", \"code\": \"__int64 __fastcall gen_srs ( __int64 @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ , char @@a4@@ ) { unsigned int v4 ; __int64 result ; int v6 ; int v7 ; char @@v10@@ ; unsigned int v11 ; unsigned int v12 ; __int64 @@v13@@ ; __int64 v14 ; __int64 v15 ; __int64 v16 ; __int64 v17 ; @@v10@@ = Number ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) == Number && * ( _BYTE * ) ( @@a1@@ + Number ) != Number && @@a2@@ == Number ) { v4 = syn_uncategorized ( ) ; result = gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , v4 , Number ) ; } else { if ( ! * ( _DWORD * ) ( @@a1@@ + Number ) || * ( _DWORD * ) ( @@a1@@ + Number ) == Number ) @@v10@@ = Number ; switch ( @@a2@@ ) { case Number : case Number : case Number : case Number : case Number : case Number : case Number : break ; case Number : if ( * ( _DWORD * ) ( @@a1@@ + Number ) != Number ) @@v10@@ = Number ; break ; case Number : if ( * ( _DWORD * ) ( @@a1@@ + Number ) == Number || ! arm_dc_feature ( @@a1@@ , Number ) ) @@v10@@ = Number ; break ; default : @@v10@@ = Number ; break ; } if ( @@v10@@ ) { result = unallocated_encoding ( @@a1@@ ) ; } else { @@v13@@ = tcg_temp_new_i32 ( ) ; v14 = tcg_const_i32 ( @@a2@@ ) ; gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; gen_helper_get_r13_banked ( @@v13@@ , cpu_env , v14 ) ; tcg_temp_free_i32 ( v14 ) ; if ( @@a3@@ == Number ) { v11 = Number ; } else { if ( @@a3@@ > Number ) abort ( ) ; if ( @@a3@@ == Number ) { v11 = Number ; } else if ( @@a3@@ ) { v11 = Number ; } else { v11 = Number ; } } tcg_gen_addi_i32 ( @@v13@@ , @@v13@@ , v11 ) ; v15 = load_reg ( @@a1@@ , Number ) ; v6 = get_mem_index ( @@a1@@ ) ; gen_aa32_st32 ( @@a1@@ , v15 , @@v13@@ , v6 ) ; tcg_temp_free_i32 ( v15 ) ; v16 = load_cpu_offset ( Number ) ; tcg_gen_addi_i32 ( @@v13@@ , @@v13@@ , Number L ) ; v7 = get_mem_index ( @@a1@@ ) ; gen_aa32_st32 ( @@a1@@ , v16 , @@v13@@ , v7 ) ; tcg_temp_free_i32 ( v16 ) ; if ( @@a4@@ ) { if ( @@a3@@ == Number ) { v12 = Number ; } else if ( @@a3@@ == Number ) { v12 = Number ; } else if ( @@a3@@ ) { v12 = Number ; } else { v12 = Number ; } tcg_gen_addi_i32 ( @@v13@@ , @@v13@@ , v12 ) ; v17 = tcg_const_i32 ( @@a2@@ ) ; gen_helper_set_r13_banked ( cpu_env , v17 , @@v13@@ ) ; tcg_temp_free_i32 ( v17 ) ; } tcg_temp_free_i32 ( @@v13@@ ) ; result = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } } return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s21\"}]}"
] |
{"name": "trans_CPS", "code": "__int64 __fastcall trans_CPS ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; int @@v4@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) || arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) return Number L ; @@v4@@ = Number ; @@v3@@ = Number ; if ( ( @@a2@@ [ Number ] & Number ) != Number ) { if ( * @@a2@@ ) @@v3@@ = Number ; if ( @@a2@@ [ Number ] ) @@v3@@ |= Number ; if ( @@a2@@ [ Number ] ) @@v3@@ |= Number ; if ( ( @@a2@@ [ Number ] & Number ) != Number ) @@v4@@ = @@v3@@ ; } if ( @@a2@@ [ Number ] ) { @@v3@@ |= Number ; @@v4@@ |= @@a2@@ [ Number ] ; } if ( @@v3@@ ) gen_set_psr_im ( @@a1@@ , @@v3@@ , Number , @@v4@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "int", "s": 4}, "location": "s4"}, {"n": "v3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_CPS"}, "location": "r64"}, {"n": "val", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s4"}, {"n": "mask", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,501 | [
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_set_psr\", \"code\": \"__int64 __fastcall gen_set_psr ( __int64 @@a1@@ , unsigned int @@a2@@ , int @@a3@@ , __int64 @@a4@@ ) { __int64 @@v6@@ ; if ( @@a3@@ ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) return Number L ; @@v6@@ = load_cpu_offset ( Number ) ; tcg_gen_andi_i32 ( @@v6@@ , @@v6@@ , ~ @@a2@@ ) ; tcg_gen_andi_i32 ( @@a4@@ , @@a4@@ , @@a2@@ ) ; tcg_gen_or_i32 ( @@v6@@ , @@v6@@ , @@a4@@ ) ; store_cpu_offset ( @@v6@@ , Number ) ; } else { gen_set_cpsr ( @@a4@@ , @@a2@@ ) ; } tcg_temp_free_i32 ( @@a4@@ ) ; gen_lookup_tb ( @@a1@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_psr_im\", \"code\": \"__int64 __fastcall gen_set_psr_im ( __int64 @@a1@@ , unsigned int @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int64 @@v7@@ ; @@v7@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v7@@ , @@a4@@ ) ; return gen_set_psr ( @@a1@@ , @@a2@@ , @@a3@@ , @@v7@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_CPS_v7m", "code": "__int64 __fastcall trans_CPS_v7m ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 v4 ; __int64 v5 ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) return Number L ; @@v3@@ = tcg_const_i32 ( ( unsigned int ) @@a2@@ [ Number ] ) ; if ( * @@a2@@ ) { v4 = tcg_const_i32 ( Number L ) ; gen_helper_v7m_msr ( cpu_env , v4 , @@v3@@ ) ; tcg_temp_free_i32 ( v4 ) ; } if ( @@a2@@ [ Number ] ) { v5 = tcg_const_i32 ( Number L ) ; gen_helper_v7m_msr ( cpu_env , v5 , @@v3@@ ) ; tcg_temp_free_i32 ( v5 ) ; } tcg_temp_free_i32 ( @@v3@@ ) ; gen_lookup_tb ( @@a1@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_CPS_v7m"}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,502 | [
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_v7m_msr\", \"code\": \"unsigned __int64 __fastcall gen_helper_v7m_msr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_v7m_msr , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_lookup_tb\", \"code\": \"__int64 __fastcall gen_lookup_tb ( __int64 @@a1@@ ) { __int64 @@result@@ ; tcg_gen_movi_i32 ( qword_4BEB8 , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"trans_CPS\", \"code\": \"__int64 __fastcall trans_CPS ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; int @@v4@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) || arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) return Number L ; @@v4@@ = Number ; @@v3@@ = Number ; if ( ( @@a2@@ [ Number ] & Number ) != Number ) { if ( * @@a2@@ ) @@v3@@ = Number ; if ( @@a2@@ [ Number ] ) @@v3@@ |= Number ; if ( @@a2@@ [ Number ] ) @@v3@@ |= Number ; if ( ( @@a2@@ [ Number ] & Number ) != Number ) @@v4@@ = @@v3@@ ; } if ( @@a2@@ [ Number ] ) { @@v3@@ |= Number ; @@v4@@ |= @@a2@@ [ Number ] ; } if ( @@v3@@ ) gen_set_psr_im ( @@a1@@ , @@v3@@ , Number , @@v4@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s4\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s8\"}]}"
] |
{"name": "trans_CLREX", "code": "__int64 __fastcall trans_CLREX ( __int64 @@a1@@ ) { bool v1 ; bool v2 ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { v1 = ! arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ; v2 = v1 ; } else { v2 = ! arm_dc_feature ( @@a1@@ , Number ) ; } if ( v2 ) return Number L ; gen_clrex ( @@a1@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,503 | [
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}"
] |
{"name": "trans_DSB", "code": "__int64 __fastcall trans_DSB ( __int64 @@a1@@ ) { if ( ! arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; tcg_gen_mb ( Number L ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,504 | [
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}"
] |
{"name": "trans_DMB", "code": "__int64 __fastcall trans_DMB ( __int64 @@a1@@ ) { return trans_DSB ( @@a1@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,505 | [
"{\"name\": \"trans_DSB\", \"code\": \"__int64 __fastcall trans_DSB ( __int64 @@a1@@ ) { if ( ! arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; tcg_gen_mb ( Number L ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}"
] |
{"name": "trans_ISB", "code": "__int64 __fastcall trans_ISB ( __int64 @@a1@@ ) { if ( ! arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; gen_goto_tb ( @@a1@@ , Number , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,506 | [
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_goto_tb\", \"code\": \"__int64 __fastcall gen_goto_tb ( __int64 @@a1@@ , unsigned int @@a2@@ , __int64 @@a3@@ ) { __int64 @@result@@ ; int @@v4@@ ; @@v4@@ = @@a3@@ ; if ( use_goto_tb ( @@a1@@ , @@a3@@ ) ) { tcg_gen_goto_tb ( @@a2@@ ) ; gen_set_pc_im ( @@a1@@ , @@v4@@ ) ; tcg_gen_exit_tb ( * ( _QWORD * ) @@a1@@ , @@a2@@ ) ; } else { gen_set_pc_im ( @@a1@@ , @@v4@@ ) ; gen_goto_ptr ( ) ; } @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s24\"}]}"
] |
{"name": "trans_SB", "code": "__int64 __fastcall trans_SB ( __int64 @@a1@@ ) { if ( ! isar_feature_aa32_sb ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; tcg_gen_mb ( Number L ) ; gen_goto_tb ( @@a1@@ , Number , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,507 | [
"{\"name\": \"isar_feature_aa32_sb\", \"code\": \"bool __fastcall isar_feature_aa32_sb ( __int64 @@a1@@ ) { return ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_goto_tb\", \"code\": \"__int64 __fastcall gen_goto_tb ( __int64 @@a1@@ , unsigned int @@a2@@ , __int64 @@a3@@ ) { __int64 @@result@@ ; int @@v4@@ ; @@v4@@ = @@a3@@ ; if ( use_goto_tb ( @@a1@@ , @@a3@@ ) ) { tcg_gen_goto_tb ( @@a2@@ ) ; gen_set_pc_im ( @@a1@@ , @@v4@@ ) ; tcg_gen_exit_tb ( * ( _QWORD * ) @@a1@@ , @@a2@@ ) ; } else { gen_set_pc_im ( @@a1@@ , @@v4@@ ) ; gen_goto_ptr ( ) ; } @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s24\"}]}"
] |
{"name": "trans_SETEND", "code": "__int64 __fastcall trans_SETEND ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( * @@a2@@ != ( * ( _DWORD * ) ( @@a1@@ + Number ) == Number ) ) { gen_helper_setend ( cpu_env ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_SETEND"}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,508 | [
"{\"name\": \"gen_helper_setend\", \"code\": \"unsigned __int64 __fastcall gen_helper_setend ( __int64 @@a1@@ ) { __int64 @@v2@@ ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; @@v2@@ = tcgv_ptr_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_setend , Number L , Number L , & @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}"
] |
{"name": "trans_PLD", "code": "bool __fastcall trans_PLD ( __int64 @@a1@@ ) { return arm_dc_feature ( @@a1@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,509 | [
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}"
] |
{"name": "trans_PLDW", "code": "bool __fastcall trans_PLDW ( __int64 @@a1@@ ) { return arm_dc_feature ( @@a1@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,510 | [
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"trans_PLD\", \"code\": \"bool __fastcall trans_PLD ( __int64 @@a1@@ ) { return arm_dc_feature ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}"
] |
{"name": "trans_PLI", "code": "bool __fastcall trans_PLI ( __int64 @@a1@@ ) { return arm_dc_feature ( @@a1@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,511 | [
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}"
] |
{"name": "trans_IT", "code": "__int64 __fastcall trans_IT ( __int64 @@a1@@ , int * @@a2@@ ) { int @@v3@@ ; @@v3@@ = * @@a2@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = ( * @@a2@@ >> Number ) & Number ; * ( _DWORD * ) ( @@a1@@ + Number ) = @@v3@@ & Number ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "s4"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_IT"}, "location": "r64"}, {"n": "cond_mask", "t": {"T": 1, "n": "int", "s": 4}, "location": "s4"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,512 | [] |
{"name": "disas_arm_insn", "code": "__int64 __fastcall disas_arm_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int @@v2@@ ; unsigned int v3 ; __int64 result ; int @@v5@@ ; @@v5@@ = @@a2@@ >> Number ; if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v2@@ = default_exception_el ( @@a1@@ ) ; v3 = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , v3 , @@v2@@ ) ; } if ( @@v5@@ != Number ) { if ( @@v5@@ != Number ) arm_skip_unless ( @@a1@@ , @@v5@@ ) ; result = disas_a32 ( @@a1@@ , @@a2@@ ) ; if ( ! ( _BYTE ) result ) { if ( ( HIBYTE ( @@a2@@ ) & Number ) - Number <= Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { result = disas_vfp_insn ( @@a1@@ , @@a2@@ ) ; if ( ! ( _DWORD ) result ) return result ; } else { result = disas_coproc_insn ( @@a1@@ , @@a2@@ ) ; if ( ! ( _DWORD ) result ) return result ; } } return unallocated_encoding ( @@a1@@ ) ; } return result ; } if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return unallocated_encoding ( @@a1@@ ) ; result = disas_a32_uncond ( @@a1@@ , @@a2@@ ) ; if ( ( _BYTE ) result ) return result ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return unallocated_encoding ( @@a1@@ ) ; result = disas_neon_ls_insn ( @@a1@@ , @@a2@@ ) ; if ( ( _DWORD ) result ) return unallocated_encoding ( @@a1@@ ) ; return result ; } if ( ( @@a2@@ & Number ) == Number ) { result = disas_vfp_insn ( @@a1@@ , @@a2@@ ) ; if ( ! ( _DWORD ) result ) return result ; return unallocated_encoding ( @@a1@@ ) ; } if ( ( @@a2@@ & Number ) == Number ) { if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return unallocated_encoding ( @@a1@@ ) ; if ( ! ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) ) return unallocated_encoding ( @@a1@@ ) ; result = disas_iwmmxt_insn ( @@a1@@ , @@a2@@ ) ; if ( ( _DWORD ) result ) return unallocated_encoding ( @@a1@@ ) ; return result ; } if ( ( @@a2@@ & Number ) == Number && arm_dc_feature ( @@a1@@ , Number ) ) { result = disas_neon_insn_3same_ext ( @@a1@@ , @@a2@@ ) ; if ( ! ( _DWORD ) result ) return result ; return unallocated_encoding ( @@a1@@ ) ; } if ( ( @@a2@@ & Number ) == Number && arm_dc_feature ( @@a1@@ , Number ) ) { result = disas_neon_insn_2reg_scalar_ext ( @@a1@@ , @@a2@@ ) ; if ( ! ( _DWORD ) result ) return result ; } return unallocated_encoding ( @@a1@@ ) ; } if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return unallocated_encoding ( @@a1@@ ) ; result = disas_neon_data_insn ( @@a1@@ , @@a2@@ ) ; if ( ( _DWORD ) result ) return unallocated_encoding ( @@a1@@ ) ; return result ; }", "source": [{"n": "v2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r32"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "int", "s": 4}, "location": "s20"}]} | [{"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r32"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "insn", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "cond", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s20"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,513 | [
"{\"name\": \"extract32\", \"code\": \"__int64 __fastcall extract32 ( unsigned int @@a1@@ , int @@a2@@ , int @@a3@@ ) { if ( @@a2@@ < Number || @@a3@@ <= Number || @@a3@@ > Number - @@a2@@ ) _assert_fail ( String , String , Number , String ) ; return ( @@a1@@ >> @@a2@@ ) & ( Number >> ( Number - @@a3@@ ) ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"default_exception_el\", \"code\": \"__int64 __fastcall default_exception_el ( __int64 @@a1@@ ) { __int64 @@result@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) == Number && * ( _BYTE * ) ( @@a1@@ + Number ) ) return Number L ; @@result@@ = * ( unsigned int * ) ( @@a1@@ + Number ) ; if ( ( int ) @@result@@ <= Number ) @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception_insn\", \"code\": \"__int64 __fastcall gen_exception_insn ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , unsigned int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@result@@ ; gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; gen_exception ( @@a3@@ , @@a4@@ , @@a5@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"disas_vfp\", \"code\": \"_BOOL8 __fastcall disas_vfp ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; _BOOL8 result ; unsigned int v4 ; unsigned int v5 ; unsigned int v6 ; unsigned int v7 ; unsigned int v8 ; unsigned int v9 ; unsigned int v10 ; unsigned int v11 ; unsigned int v12 ; unsigned int v13 ; unsigned int v14 ; unsigned int v15 ; _DWORD @@v16@@ [ Number ] ; unsigned __int64 @@v17@@ ; @@v17@@ = __readfsqword ( Number ) ; v2 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { v10 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_0 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { result = Number L ; } } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_1 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_2 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v10 != Number ) { if ( v10 <= Number ) { if ( ! v10 ) { v11 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_22 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v11 != Number ) { if ( v11 <= Number ) { if ( ! v11 ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VMLS_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VMLA_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v11 == Number ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VNMUL_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VMUL_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } return Number L ; } disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDIV_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v10 == Number ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_6 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDUP ( @@a1@@ , @@v16@@ ) != Number ; } else { result = Number L ; } } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_3 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_4 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_5 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } } return Number L ; } v12 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v12 == Number ) { disas_vfp_extract_disas_vfp_Fmt_20 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v12 <= Number ) { if ( ! v12 ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VNMLA_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VNMLS_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v12 == Number ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VSUB_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VADD_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_24 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_imm_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } v13 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_37 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_fix_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v13 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_39 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_dp_int ( @@a1@@ , @@v16@@ ) != Number ; } else if ( ( @@a2@@ & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_33 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_VJCVT ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } else { disas_vfp_extract_disas_vfp_Fmt_35 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_int_dp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v13 > Number ) return Number L ; if ( ! v13 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_28 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCMP_dp ( @@a1@@ , @@v16@@ ) != Number ; } disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v14 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSQRT_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 == Number ) return ( unsigned __int8 ) trans_VNEG_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 > Number ) goto LABEL_195 ; if ( ! v14 ) return ( unsigned __int8 ) trans_VMOV_reg_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 == Number ) result = ( unsigned __int8 ) trans_VABS_dp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_195 : result = Number L ; return result ; } if ( v13 != ( _DWORD ) & loc_20000 ) return Number L ; v15 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != ( _DWORD ) & unk_50000 ) { if ( v15 <= ( unsigned int ) & unk_50000 ) { if ( v15 == Number ) { disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VRINTZ_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VRINTR_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v15 <= Number ) { if ( ! v15 ) { disas_vfp_extract_disas_vfp_Fmt_30 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f64_f16 ( @@a1@@ , @@v16@@ ) != Number ; } if ( v15 == Number ) { disas_vfp_extract_disas_vfp_Fmt_31 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f16_f64 ( @@a1@@ , @@v16@@ ) != Number ; } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_33 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VRINTX_dp ( @@a1@@ , @@v16@@ ) != Number ; } } else { if ( v2 > Number ) return Number L ; if ( v2 != Number ) { if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_16 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VLDM_VSTM_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_12 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDR_VSTR_dp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_15 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VLDM_VSTM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_11 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDR_VSTR_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_13 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDM_VSTM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_9 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMOV_64_sp ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } } else { if ( v2 != Number ) return Number L ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_14 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDM_VSTM_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_10 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMOV_64_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } } return result ; } } } return Number L ; } v4 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_7 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMSR_VMRS ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; return result ; } if ( v4 != Number ) { if ( v4 <= Number ) { if ( v4 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_19 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VFM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDIV_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v4 <= Number ) { if ( v4 == Number ) { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v6 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSUB_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 == Number ) return ( unsigned __int8 ) trans_VADD_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 > Number ) goto LABEL_66 ; if ( ! v6 ) return ( unsigned __int8 ) trans_VMUL_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 == Number ) result = ( unsigned __int8 ) trans_VNMUL_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_66 : result = Number L ; return result ; } if ( v4 <= Number ) { if ( ! v4 ) { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v5 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VNMLA_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 == Number ) return ( unsigned __int8 ) trans_VNMLS_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 > Number ) goto LABEL_52 ; if ( ! v5 ) return ( unsigned __int8 ) trans_VMLA_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 == Number ) result = ( unsigned __int8 ) trans_VMLS_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_52 : result = Number L ; return result ; } if ( v4 == Number ) { disas_vfp_extract_disas_vfp_Fmt_8 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_single ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_21 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_sp ( @@a1@@ , @@v16@@ ) != Number ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_23 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_imm_sp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } v7 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_36 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_fix_sp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v7 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_38 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_sp_int ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_34 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VCVT_int_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v7 > Number ) return Number L ; if ( ! v7 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_27 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCMP_sp ( @@a1@@ , @@v16@@ ) != Number ; } disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v8 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSQRT_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 == Number ) return ( unsigned __int8 ) trans_VNEG_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 > Number ) goto LABEL_96 ; if ( ! v8 ) return ( unsigned __int8 ) trans_VMOV_reg_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 == Number ) result = ( unsigned __int8 ) trans_VABS_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_96 : result = Number L ; return result ; } if ( v7 != ( _DWORD ) & loc_20000 ) return Number L ; v9 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != ( _DWORD ) & unk_50000 ) { if ( v9 <= ( unsigned int ) & unk_50000 ) { if ( v9 == Number ) { disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VRINTZ_sp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VRINTR_sp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v9 <= Number ) { if ( ! v9 ) { disas_vfp_extract_disas_vfp_Fmt_29 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f32_f16 ( @@a1@@ , @@v16@@ ) != Number ; } if ( v9 == Number ) { disas_vfp_extract_disas_vfp_Fmt_29 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f16_f32 ( @@a1@@ , @@v16@@ ) != Number ; } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_32 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VRINTX_sp ( @@a1@@ , @@v16@@ ) != Number ; } } return result ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v16\", \"t\": {\"T\": 2, \"n\": 10, \"s\": 4, \"t\": \"_DWORD\"}, \"location\": \"s48\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"disas_iwmmxt_insn\", \"code\": \"__int64 __fastcall disas_iwmmxt_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 result ; int v3 ; int v4 ; int v5 ; int v6 ; int v7 ; int v8 ; int v9 ; int v10 ; unsigned int v11 ; int v12 ; int v13 ; int v14 ; unsigned int v15 ; int v16 ; int v17 ; unsigned int v18 ; int v19 ; int v20 ; int v21 ; int v22 ; int v23 ; int v24 ; int v25 ; int v26 ; int v27 ; int v28 ; int v29 ; int v30 ; int v31 ; int v32 ; unsigned int v33 ; int v34 ; int j ; int i ; int l ; int k ; int v39 ; int v40 ; int v41 ; int v42 ; int v43 ; int v44 ; int v45 ; int v46 ; int @@v47@@ ; int v48 ; int v49 ; int v50 ; int v51 ; int v52 ; int v53 ; int v54 ; int v55 ; int v56 ; int v57 ; int v58 ; int v59 ; int v60 ; int v61 ; int v62 ; int v63 ; int v64 ; int @@v65@@ ; __int64 v66 ; __int64 v67 ; __int64 v68 ; __int64 v69 ; __int64 v70 ; __int64 v71 ; __int64 v72 ; __int64 v73 ; __int64 v74 ; __int64 v75 ; __int64 v76 ; __int64 v77 ; __int64 v78 ; __int64 v79 ; __int64 v80 ; __int64 v81 ; __int64 v82 ; __int64 v83 ; __int64 v84 ; __int64 v85 ; __int64 v86 ; __int64 @@v87@@ ; __int64 @@v88@@ ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) return Number L ; v11 = ( @@a2@@ >> Number ) & Number | ( unsigned __int8 ) ( @@a2@@ >> Number ) ; if ( v11 > Number ) return Number L ; if ( v11 < Number ) { if ( v11 > Number ) return Number L ; if ( v11 >= Number ) { switch ( v11 ) { case Number : case Number : LABEL_271 : if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v45 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v79 = tcg_temp_new_i32 ( ) ; if ( ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) goto LABEL_314 ; v26 = ( @@a2@@ >> Number ) & Number ; switch ( v26 ) { case Number : gen_helper_iwmmxt_srlq ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_srlw ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_srll ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; } goto LABEL_316 ; case Number : goto LABEL_369 ; case Number : LABEL_258 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v25 = ( @@a2@@ >> Number ) & Number ; if ( v25 == Number ) return Number L ; if ( v25 == Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_unpackhsl_M0 ( ) ; else gen_op_iwmmxt_unpackhul_M0 ( ) ; } else if ( v25 ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_unpackhsw_M0 ( ) ; else gen_op_iwmmxt_unpackhuw_M0 ( ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_unpackhsb_M0 ( ) ; } else { gen_op_iwmmxt_unpackhub_M0 ( ) ; } goto LABEL_385 ; case Number : LABEL_245 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v24 = ( @@a2@@ >> Number ) & Number ; if ( v24 == Number ) return Number L ; if ( v24 == Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_unpacklsl_M0 ( ) ; else gen_op_iwmmxt_unpacklul_M0 ( ) ; } else if ( v24 ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_unpacklsw_M0 ( ) ; else gen_op_iwmmxt_unpackluw_M0 ( ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_unpacklsb_M0 ( ) ; } else { gen_op_iwmmxt_unpacklub_M0 ( ) ; } goto LABEL_385 ; case Number : LABEL_330 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v58 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v31 = ( @@a2@@ >> Number ) & Number ; if ( v31 == Number ) return Number L ; if ( v31 == Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_maxsl_M0_wRn ( v58 ) ; else gen_op_iwmmxt_maxul_M0_wRn ( v58 ) ; } else if ( v31 ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_maxsw_M0_wRn ( v58 ) ; else gen_op_iwmmxt_maxuw_M0_wRn ( v58 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_maxsb_M0_wRn ( v58 ) ; } else { gen_op_iwmmxt_maxub_M0_wRn ( v58 ) ; } break ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } } else { if ( v11 > Number ) return Number L ; if ( v11 >= Number ) { switch ( v11 ) { case Number : LABEL_132 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v55 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_avgw1_M0_wRn ( v55 ) ; else gen_op_iwmmxt_avgw0_M0_wRn ( v55 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_avgb1_M0_wRn ( v55 ) ; } else { gen_op_iwmmxt_avgb0_M0_wRn ( v55 ) ; } goto LABEL_385 ; case Number : LABEL_222 : v64 = ( unsigned __int16 ) @@a2@@ >> Number ; if ( ( @@a2@@ & Number ) != Number || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v75 = tcg_temp_new_i32 ( ) ; v22 = ( @@a2@@ >> Number ) & Number ; if ( v22 == Number ) { gen_helper_iwmmxt_msbl ( v75 , cpu_M0 ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( v22 ) gen_helper_iwmmxt_msbw ( v75 , cpu_M0 ) ; else gen_helper_iwmmxt_msbb ( v75 , cpu_M0 ) ; } goto LABEL_231 ; case Number : case Number : LABEL_292 : if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v45 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v79 = tcg_temp_new_i32 ( ) ; if ( ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) goto LABEL_314 ; v28 = ( @@a2@@ >> Number ) & Number ; switch ( v28 ) { case Number : gen_helper_iwmmxt_sllq ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_sllw ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_slll ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; } goto LABEL_316 ; case Number : goto LABEL_232 ; case Number : LABEL_150 : v64 = ( unsigned __int16 ) @@a2@@ >> Number ; if ( v64 == Number || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v75 = tcg_temp_new_i32 ( ) ; v16 = ( @@a2@@ >> Number ) & Number ; if ( v16 == Number ) { tcg_gen_shri_i64 ( cpu_M0 , cpu_M0 , ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; tcg_gen_extrl_i64_i32 ( v75 , cpu_M0 ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( v16 ) { tcg_gen_shri_i64 ( cpu_M0 , cpu_M0 , ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; tcg_gen_extrl_i64_i32 ( v75 , cpu_M0 ) ; if ( ( @@a2@@ & Number ) != Number ) tcg_gen_ext16s_i32 ( v75 , v75 ) ; else tcg_gen_andi_i32 ( v75 , v75 , Number ) ; } else { tcg_gen_shri_i64 ( cpu_M0 , cpu_M0 , ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; tcg_gen_extrl_i64_i32 ( v75 , cpu_M0 ) ; if ( ( @@a2@@ & Number ) != Number ) tcg_gen_ext8s_i32 ( v75 , v75 ) ; else tcg_gen_andi_i32 ( v75 , v75 , Number L ) ; } } LABEL_231 : store_reg ( @@a1@@ , v64 , v75 ) ; return Number L ; case Number : goto LABEL_369 ; case Number : LABEL_99 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v50 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v13 = ( @@a2@@ >> Number ) & Number ; if ( v13 == Number ) return Number L ; if ( v13 == Number ) { gen_op_iwmmxt_unpackhl_M0_wRn ( v50 ) ; } else if ( v13 ) { gen_op_iwmmxt_unpackhw_M0_wRn ( v50 ) ; } else { gen_op_iwmmxt_unpackhb_M0_wRn ( v50 ) ; } goto LABEL_385 ; case Number : LABEL_92 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v49 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v12 = ( @@a2@@ >> Number ) & Number ; if ( v12 == Number ) return Number L ; if ( v12 == Number ) { gen_op_iwmmxt_unpackll_M0_wRn ( v49 ) ; } else if ( v12 ) { gen_op_iwmmxt_unpacklw_M0_wRn ( v49 ) ; } else { gen_op_iwmmxt_unpacklb_M0_wRn ( v49 ) ; } goto LABEL_385 ; case Number : LABEL_183 : if ( ( @@a2@@ & Number ) != ( _DWORD ) & loc_3F000 || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v78 = iwmmxt_load_creg ( Number ) ; v85 = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( v85 , v78 ) ; v19 = ( @@a2@@ >> Number ) & Number ; if ( v19 == Number ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_and_i32 ( v78 , v78 , v85 ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( v19 ) { for ( i = Number ; i <= Number ; ++ i ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_and_i32 ( v78 , v78 , v85 ) ; } } else { for ( j = Number ; j <= Number ; ++ j ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_and_i32 ( v78 , v78 , v85 ) ; } } } goto LABEL_198 ; case Number : LABEL_206 : if ( ( @@a2@@ & Number ) != ( _DWORD ) & loc_3F000 || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v78 = iwmmxt_load_creg ( Number ) ; v85 = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( v85 , v78 ) ; v21 = ( @@a2@@ >> Number ) & Number ; if ( v21 == Number ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_or_i32 ( v78 , v78 , v85 ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( v21 ) { for ( k = Number ; k <= Number ; ++ k ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_or_i32 ( v78 , v78 , v85 ) ; } } else { for ( l = Number ; l <= Number ; ++ l ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_or_i32 ( v78 , v78 , v85 ) ; } } } LABEL_198 : gen_set_cpsr ( v78 , Number ) ; tcg_temp_free_i32 ( v85 ) ; tcg_temp_free_i32 ( v78 ) ; return Number L ; case Number : goto LABEL_317 ; case Number : LABEL_164 : if ( ( @@a2@@ & Number ) != ( _DWORD ) & loc_3F000 || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v76 = iwmmxt_load_creg ( Number ) ; v17 = ( @@a2@@ >> Number ) & Number ; if ( v17 == Number ) { tcg_gen_shri_i32 ( v76 , v76 , ( ( Number * ( _BYTE ) @@a2@@ ) & Number ) + Number ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( v17 ) tcg_gen_shri_i32 ( v76 , v76 , ( ( Number * ( _BYTE ) @@a2@@ ) & Number ) + Number ) ; else tcg_gen_shri_i32 ( v76 , v76 , ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; } tcg_gen_shli_i32 ( v76 , v76 , Number L ) ; gen_set_cpsr ( v76 , Number ) ; tcg_temp_free_i32 ( v76 ) ; break ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } return Number L ; } if ( v11 > Number ) return Number L ; if ( v11 < Number ) { if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : LABEL_139 : gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v73 = iwmmxt_load_creg ( ( ( @@a2@@ >> Number ) & Number ) + Number ) ; tcg_gen_andi_i32 ( v73 , v73 , Number L ) ; iwmmxt_load_reg ( cpu_V1 , @@a2@@ & Number ) ; gen_helper_iwmmxt_align ( cpu_M0 , cpu_M0 , cpu_V1 , v73 ) ; tcg_temp_free_i32 ( v73 ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; return Number L ; case Number : case Number : goto LABEL_302 ; case Number : goto LABEL_232 ; case Number : goto LABEL_369 ; case Number : goto LABEL_317 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : goto LABEL_139 ; case Number : case Number : goto LABEL_271 ; case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : LABEL_89 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v48 = HIWORD ( @@a2@@ ) & Number ; gen_op_iwmmxt_movq_M0_wRn ( @@a2@@ & Number ) ; if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_maddsq_M0_wRn ( v48 ) ; else gen_op_iwmmxt_madduq_M0_wRn ( v48 ) ; goto LABEL_124 ; case Number : goto LABEL_330 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : goto LABEL_132 ; case Number : goto LABEL_139 ; case Number : goto LABEL_222 ; case Number : case Number : goto LABEL_292 ; case Number : goto LABEL_232 ; case Number : goto LABEL_150 ; case Number : goto LABEL_369 ; case Number : goto LABEL_99 ; case Number : goto LABEL_92 ; case Number : goto LABEL_183 ; case Number : goto LABEL_206 ; case Number : goto LABEL_317 ; case Number : goto LABEL_164 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : goto LABEL_132 ; case Number : goto LABEL_139 ; case Number : case Number : goto LABEL_282 ; case Number : goto LABEL_125 ; case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : goto LABEL_89 ; case Number : goto LABEL_330 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_199 ; case Number : goto LABEL_356 ; default : return Number L ; } } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : LABEL_343 : gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v80 = tcg_const_i32 ( ( @@a2@@ >> Number ) & Number ) ; iwmmxt_load_reg ( cpu_V1 , @@a2@@ & Number ) ; gen_helper_iwmmxt_align ( cpu_M0 , cpu_M0 , cpu_V1 , v80 ) ; tcg_temp_free_i32 ( v80 ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; return Number L ; case Number : case Number : goto LABEL_302 ; case Number : goto LABEL_232 ; case Number : goto LABEL_369 ; case Number : LABEL_119 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v53 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_macsw_M0_wRn ( v53 ) ; else gen_op_iwmmxt_macuw_M0_wRn ( v53 ) ; if ( ( @@a2@@ & Number ) == Number ) { iwmmxt_load_reg ( cpu_V1 , v42 ) ; tcg_gen_add_i64 ( cpu_M0 , cpu_M0 , cpu_V1 ) ; } goto LABEL_124 ; case Number : goto LABEL_317 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : case Number : case Number : case Number : if ( ( unsigned __int8 ) @@a2@@ >> Number == Number ) return Number L ; v44 = HIWORD ( @@a2@@ ) & Number ; v74 = load_reg ( @@a1@@ , ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_movq_M0_wRn ( v44 ) ; v15 = ( unsigned __int8 ) @@a2@@ >> Number ; if ( v15 == Number ) { v84 = tcg_const_i32 ( Number ) ; @@v87@@ = tcg_const_i32 ( ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; } else if ( v15 > Number ) { v84 = Number L ; @@v87@@ = Number L ; } else if ( ( unsigned __int8 ) @@a2@@ >> Number ) { v84 = tcg_const_i32 ( Number ) ; @@v87@@ = tcg_const_i32 ( ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; } else { v84 = tcg_const_i32 ( Number L ) ; @@v87@@ = tcg_const_i32 ( ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; } gen_helper_iwmmxt_insr ( cpu_M0 , cpu_M0 , v74 , v84 , @@v87@@ ) ; tcg_temp_free_i32 ( @@v87@@ ) ; tcg_temp_free_i32 ( v84 ) ; tcg_temp_free_i32 ( v74 ) ; gen_op_iwmmxt_movq_wRn_M0 ( v44 ) ; gen_op_iwmmxt_set_mup ( ) ; break ; case Number : goto LABEL_343 ; case Number : case Number : goto LABEL_271 ; case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : goto LABEL_119 ; case Number : goto LABEL_330 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } return Number L ; } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : case Number : case Number : case Number : if ( ( unsigned __int8 ) @@a2@@ >> Number == Number ) return Number L ; v77 = load_reg ( @@a1@@ , ( unsigned __int16 ) @@a2@@ >> Number ) ; v18 = ( unsigned __int8 ) @@a2@@ >> Number ; if ( v18 == Number ) { gen_helper_iwmmxt_bcstl ( cpu_M0 , v77 ) ; } else if ( v18 <= Number ) { if ( ( unsigned __int8 ) @@a2@@ >> Number ) gen_helper_iwmmxt_bcstw ( cpu_M0 , v77 ) ; else gen_helper_iwmmxt_bcstb ( cpu_M0 , v77 ) ; } tcg_temp_free_i32 ( v77 ) ; gen_op_iwmmxt_movq_wRn_M0 ( HIWORD ( @@a2@@ ) & Number ) ; gen_op_iwmmxt_set_mup ( ) ; break ; case Number : case Number : goto LABEL_343 ; case Number : case Number : goto LABEL_282 ; case Number : goto LABEL_125 ; case Number : case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : case Number : goto LABEL_119 ; case Number : case Number : LABEL_106 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v51 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_sadw_M0_wRn ( v51 ) ; else gen_op_iwmmxt_sadb_M0_wRn ( v51 ) ; if ( ( @@a2@@ & Number ) == Number ) gen_op_iwmmxt_addl_M0_wRn ( v42 ) ; goto LABEL_124 ; case Number : goto LABEL_330 ; case Number : case Number : goto LABEL_357 ; case Number : case Number : goto LABEL_344 ; case Number : goto LABEL_199 ; case Number : case Number : goto LABEL_356 ; case Number : goto LABEL_222 ; case Number : case Number : goto LABEL_292 ; case Number : goto LABEL_232 ; case Number : goto LABEL_150 ; case Number : goto LABEL_99 ; case Number : goto LABEL_92 ; case Number : goto LABEL_183 ; case Number : goto LABEL_206 ; case Number : goto LABEL_317 ; case Number : goto LABEL_164 ; default : return Number L ; } return Number L ; } if ( v11 <= Number ) { switch ( v11 ) { case Number : gen_op_iwmmxt_movq_M0_wRn ( @@a2@@ & Number ) ; gen_op_iwmmxt_orq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; gen_op_iwmmxt_setpsr_nz ( ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; case Number : case Number : goto LABEL_343 ; case Number : case Number : goto LABEL_282 ; case Number : goto LABEL_125 ; case Number : case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : case Number : goto LABEL_112 ; case Number : if ( ( @@a2@@ & Number ) == Number ) { v63 = ( unsigned __int16 ) @@a2@@ >> Number ; v41 = HIWORD ( @@a2@@ ) & Number ; switch ( v41 ) { case Number : case Number : return Number L ; case Number : gen_op_iwmmxt_set_cup ( ) ; goto LABEL_80 ; case Number : LABEL_80 : v70 = iwmmxt_load_creg ( v41 ) ; v83 = load_reg ( @@a1@@ , v63 ) ; tcg_gen_andc_i32 ( v70 , v70 , v83 ) ; tcg_temp_free_i32 ( v83 ) ; iwmmxt_store_creg ( v41 , v70 ) ; return Number L ; case Number : case Number : case Number : case Number : gen_op_iwmmxt_set_cup ( ) ; v71 = load_reg ( @@a1@@ , v63 ) ; iwmmxt_store_creg ( v41 , v71 ) ; return Number L ; default : return Number L ; } } return Number L ; case Number : case Number : goto LABEL_106 ; case Number : goto LABEL_330 ; case Number : case Number : goto LABEL_357 ; case Number : case Number : goto LABEL_344 ; case Number : goto LABEL_199 ; case Number : case Number : goto LABEL_356 ; case Number : gen_op_iwmmxt_movq_M0_wRn ( @@a2@@ & Number ) ; gen_op_iwmmxt_xorq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; gen_op_iwmmxt_setpsr_nz ( ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; case Number : goto LABEL_222 ; case Number : case Number : goto LABEL_292 ; case Number : goto LABEL_232 ; case Number : goto LABEL_150 ; case Number : goto LABEL_99 ; case Number : goto LABEL_92 ; case Number : if ( ( @@a2@@ & Number ) != Number ) return Number L ; v72 = iwmmxt_load_creg ( HIWORD ( @@a2@@ ) & Number ) ; store_reg ( @@a1@@ , ( unsigned __int16 ) @@a2@@ >> Number , v72 ) ; break ; case Number : goto LABEL_183 ; case Number : goto LABEL_206 ; case Number : goto LABEL_317 ; case Number : goto LABEL_164 ; default : return Number L ; } return Number L ; } if ( v11 <= Number && v11 >= Number ) { switch ( v11 ) { case Number : gen_op_iwmmxt_movq_M0_wRn ( @@a2@@ & Number ) ; gen_op_iwmmxt_andq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; gen_op_iwmmxt_setpsr_nz ( ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : v46 = ( @@a2@@ >> Number ) & Number ; @@v47@@ = ( unsigned __int16 ) @@a2@@ >> Number ; v62 = @@a2@@ & Number ; if ( @@v47@@ == Number || v62 == Number ) return Number L ; gen_op_iwmmxt_movq_M0_wRn ( v46 ) ; v82 = load_reg ( @@a1@@ , @@v47@@ ) ; v86 = load_reg ( @@a1@@ , v62 ) ; v33 = HIWORD ( @@a2@@ ) & Number ; if ( v33 >= Number ) { if ( ( @@a2@@ & Number ) != Number ) tcg_gen_shri_i32 ( v82 , v82 , Number L ) ; if ( ( @@a2@@ & Number ) != Number ) tcg_gen_shri_i32 ( v86 , v86 , Number L ) ; gen_helper_iwmmxt_muladdswl ( cpu_M0 , cpu_M0 , v82 , v86 ) ; } else if ( v33 ) { if ( v33 != Number ) { tcg_temp_free_i32 ( v86 ) ; tcg_temp_free_i32 ( v82 ) ; return Number L ; } gen_helper_iwmmxt_muladdsw ( cpu_M0 , cpu_M0 , v82 , v86 ) ; } else { gen_helper_iwmmxt_muladdsl ( cpu_M0 , cpu_M0 , v82 , v86 ) ; } tcg_temp_free_i32 ( v86 ) ; tcg_temp_free_i32 ( v82 ) ; gen_op_iwmmxt_movq_wRn_M0 ( v46 ) ; gen_op_iwmmxt_set_mup ( ) ; break ; case Number : case Number : goto LABEL_343 ; case Number : case Number : goto LABEL_271 ; case Number : case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : case Number : LABEL_112 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v52 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_mulshw_M0_wRn ( v52 ) ; else gen_op_iwmmxt_mulslw_M0_wRn ( v52 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_muluhw_M0_wRn ( v52 ) ; } else { gen_op_iwmmxt_mululw_M0_wRn ( v52 ) ; } goto LABEL_124 ; case Number : goto LABEL_330 ; case Number : case Number : goto LABEL_357 ; case Number : case Number : goto LABEL_344 ; case Number : case Number : goto LABEL_356 ; case Number : gen_op_iwmmxt_movq_M0_wRn ( @@a2@@ & Number ) ; tcg_gen_neg_i64 ( cpu_M0 , cpu_M0 ) ; gen_op_iwmmxt_andq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; gen_op_iwmmxt_setpsr_nz ( ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; case Number : case Number : goto LABEL_302 ; case Number : goto LABEL_232 ; case Number : goto LABEL_317 ; default : return Number L ; } return Number L ; } } } } } } } } return Number L ; } switch ( v11 ) { case Number : goto LABEL_132 ; case Number : case Number : LABEL_282 : if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v45 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v79 = tcg_temp_new_i32 ( ) ; if ( ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) goto LABEL_314 ; v27 = ( @@a2@@ >> Number ) & Number ; switch ( v27 ) { case Number : gen_helper_iwmmxt_sraq ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_sraw ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_sral ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; } goto LABEL_316 ; case Number : LABEL_125 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v54 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v14 = ( @@a2@@ >> Number ) & Number ; if ( v14 == Number ) return Number L ; if ( v14 == Number ) { gen_op_iwmmxt_cmpeql_M0_wRn ( v54 ) ; } else if ( v14 ) { gen_op_iwmmxt_cmpeqw_M0_wRn ( v54 ) ; } else { gen_op_iwmmxt_cmpeqb_M0_wRn ( v54 ) ; } goto LABEL_385 ; case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : goto LABEL_330 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : LABEL_199 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v20 = ( @@a2@@ >> Number ) & Number ; if ( v20 == Number ) return Number L ; if ( v20 == Number ) { gen_helper_iwmmxt_addcl ( cpu_M0 , cpu_M0 ) ; } else if ( v20 ) { gen_helper_iwmmxt_addcw ( cpu_M0 , cpu_M0 ) ; } else { gen_helper_iwmmxt_addcb ( cpu_M0 , cpu_M0 ) ; } break ; case Number : goto LABEL_356 ; default : return Number L ; } } LABEL_124 : gen_op_iwmmxt_movq_wRn_M0 ( v42 ) ; gen_op_iwmmxt_set_mup ( ) ; return Number L ; } switch ( v11 ) { case Number : case Number : LABEL_302 : if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v45 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v79 = tcg_temp_new_i32 ( ) ; v29 = ( @@a2@@ >> Number ) & Number ; switch ( v29 ) { case Number : if ( ! ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) { gen_helper_iwmmxt_rorq ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; goto LABEL_316 ; } break ; case Number : if ( ! ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) { gen_helper_iwmmxt_rorw ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; LABEL_316 : tcg_temp_free_i32 ( v79 ) ; gen_op_iwmmxt_movq_wRn_M0 ( v45 ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; } break ; case Number : if ( ! ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) { gen_helper_iwmmxt_rorl ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; goto LABEL_316 ; } break ; default : goto LABEL_316 ; } LABEL_314 : tcg_temp_free_i32 ( v79 ) ; return Number L ; case Number : LABEL_232 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v56 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v23 = ( @@a2@@ >> Number ) & Number ; if ( v23 == Number ) return Number L ; if ( v23 == Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_cmpgtsl_M0_wRn ( v56 ) ; else gen_op_iwmmxt_cmpgtul_M0_wRn ( v56 ) ; } else if ( v23 ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_cmpgtsw_M0_wRn ( v56 ) ; else gen_op_iwmmxt_cmpgtuw_M0_wRn ( v56 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_cmpgtsb_M0_wRn ( v56 ) ; } else { gen_op_iwmmxt_cmpgtub_M0_wRn ( v56 ) ; } goto LABEL_385 ; case Number : LABEL_369 : if ( ( @@a2@@ & Number ) == Number || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v61 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v32 = ( @@a2@@ >> Number ) & Number ; switch ( v32 ) { case Number : if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_packsq_M0_wRn ( v61 ) ; else gen_op_iwmmxt_packuq_M0_wRn ( v61 ) ; break ; case Number : if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_packsw_M0_wRn ( v61 ) ; else gen_op_iwmmxt_packuw_M0_wRn ( v61 ) ; break ; case Number : if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_packsl_M0_wRn ( v61 ) ; else gen_op_iwmmxt_packul_M0_wRn ( v61 ) ; break ; } LABEL_385 : gen_op_iwmmxt_movq_wRn_M0 ( v43 ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; case Number : LABEL_317 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v57 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v30 = ( @@a2@@ >> Number ) & Number ; if ( v30 == Number ) return Number L ; if ( v30 == Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_minsl_M0_wRn ( v57 ) ; else gen_op_iwmmxt_minul_M0_wRn ( v57 ) ; } else if ( v30 ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_minsw_M0_wRn ( v57 ) ; else gen_op_iwmmxt_minuw_M0_wRn ( v57 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_minsb_M0_wRn ( v57 ) ; } else { gen_op_iwmmxt_minub_M0_wRn ( v57 ) ; } goto LABEL_124 ; case Number : LABEL_357 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v60 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; switch ( ( @@a2@@ >> Number ) & Number ) { case Number : gen_op_iwmmxt_addnb_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addub_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addsb_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addnw_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_adduw_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addsw_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addnl_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addul_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addsl_M0_wRn ( v60 ) ; goto LABEL_385 ; default : result = Number L ; break ; } return result ; case Number : LABEL_344 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v59 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; switch ( ( @@a2@@ >> Number ) & Number ) { case Number : gen_op_iwmmxt_subnb_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subub_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subsb_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subnw_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subuw_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subsw_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subnl_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subul_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subsl_M0_wRn ( v59 ) ; goto LABEL_385 ; default : result = Number L ; break ; } return result ; case Number : LABEL_356 : gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v81 = tcg_const_i32 ( HIWORD ( @@a2@@ ) & Number | @@a2@@ & Number ) ; gen_helper_iwmmxt_shufh ( cpu_M0 , cpu_env , cpu_M0 , v81 ) ; tcg_temp_free_i32 ( v81 ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; default : return Number L ; } } if ( ( @@a2@@ & Number ) == Number ) { v39 = @@a2@@ & Number ; @@v65@@ = HIWORD ( @@a2@@ ) & Number ; if ( ( @@a2@@ & Number ) != Number ) { iwmmxt_load_reg ( cpu_V0 , v39 ) ; tcg_gen_extrl_i64_i32 ( cpu_R [ ( unsigned __int16 ) @@a2@@ >> Number ] , cpu_V0 ) ; tcg_gen_extrh_i64_i32 ( cpu_R [ @@v65@@ ] , cpu_V0 ) ; } else { tcg_gen_concat_i32_i64 ( cpu_V0 , cpu_R [ ( unsigned __int16 ) @@a2@@ >> Number ] , cpu_R [ @@v65@@ ] ) ; iwmmxt_store_reg ( cpu_V0 , v39 ) ; gen_op_iwmmxt_set_mup ( ) ; } result = Number L ; } else { v40 = ( unsigned __int16 ) @@a2@@ >> Number ; @@v88@@ = tcg_temp_new_i32 ( ) ; if ( gen_iwmmxt_address ( @@a1@@ , @@a2@@ , @@v88@@ ) ) { tcg_temp_free_i32 ( @@v88@@ ) ; result = Number L ; } else { if ( ( @@a2@@ & Number ) != Number ) { if ( @@a2@@ >> Number == Number ) { v67 = tcg_temp_new_i32 ( ) ; v3 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld32u ( @@a1@@ , v67 , @@v88@@ , v3 ) ; iwmmxt_store_creg ( v40 , v67 ) ; } else { v34 = Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) { v4 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld64 ( @@a1@@ , cpu_M0 , @@v88@@ , v4 ) ; v34 = Number ; } else { v66 = tcg_temp_new_i32 ( ) ; v5 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld32u ( @@a1@@ , v66 , @@v88@@ , v5 ) ; } } else { v66 = tcg_temp_new_i32 ( ) ; v6 = get_mem_index ( @@a1@@ ) ; if ( ( @@a2@@ & Number ) != Number ) gen_aa32_ld16u ( @@a1@@ , v66 , @@v88@@ , v6 ) ; else gen_aa32_ld8u ( @@a1@@ , v66 , @@v88@@ , v6 ) ; } if ( v34 ) { tcg_gen_extu_i32_i64 ( cpu_M0 , v66 ) ; tcg_temp_free_i32 ( v66 ) ; } gen_op_iwmmxt_movq_wRn_M0 ( v40 ) ; } } else if ( @@a2@@ >> Number == Number ) { v68 = iwmmxt_load_creg ( v40 ) ; v7 = get_mem_index ( @@a1@@ ) ; gen_aa32_st32 ( @@a1@@ , v68 , @@v88@@ , v7 ) ; tcg_temp_free_i32 ( v68 ) ; } else { gen_op_iwmmxt_movq_M0_wRn ( v40 ) ; v69 = tcg_temp_new_i32 ( ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) { v8 = get_mem_index ( @@a1@@ ) ; gen_aa32_st64 ( @@a1@@ , cpu_M0 , @@v88@@ , v8 ) ; } else { tcg_gen_extrl_i64_i32 ( v69 , cpu_M0 ) ; v9 = get_mem_index ( @@a1@@ ) ; gen_aa32_st32 ( @@a1@@ , v69 , @@v88@@ , v9 ) ; } } else { tcg_gen_extrl_i64_i32 ( v69 , cpu_M0 ) ; v10 = get_mem_index ( @@a1@@ ) ; if ( ( @@a2@@ & Number ) != Number ) gen_aa32_st16 ( @@a1@@ , v69 , @@v88@@ , v10 ) ; else gen_aa32_st8 ( @@a1@@ , v69 , @@v88@@ , v10 ) ; } tcg_temp_free_i32 ( v69 ) ; } tcg_temp_free_i32 ( @@v88@@ ) ; result = Number L ; } } return result ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v87\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v65\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v47\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s52\"}, {\"n\": \"v88\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"disas_vfp_insn\", \"code\": \"__int64 __fastcall disas_vfp_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) == Number ) { if ( disas_vfp_uncond ( @@a1@@ , @@a2@@ ) ) return Number L ; } else if ( disas_vfp ( @@a1@@ , @@a2@@ ) ) { return Number L ; } return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"disas_neon_ls_insn\", \"code\": \"__int64 __fastcall disas_neon_ls_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; unsigned int v3 ; int v5 ; int v6 ; int v7 ; int v8 ; int v9 ; unsigned int v10 ; unsigned int v11 ; unsigned int v12 ; unsigned int v13 ; int v14 ; int v15 ; int v16 ; int v17 ; int v18 ; int v19 ; int @@v20@@ ; unsigned int v21 ; int v22 ; int v23 ; int v24 ; int v25 ; unsigned int v26 ; int i ; int l ; int m ; int @@j@@ ; int @@v31@@ ; int @@k@@ ; int @@v33@@ ; int @@v34@@ ; int @@v35@@ ; int @@v36@@ ; int @@v37@@ ; int v38 ; int v39 ; int v40 ; int @@v41@@ ; unsigned int @@v42@@ ; unsigned int @@v43@@ ; int @@v44@@ ; int @@v45@@ ; int @@v46@@ ; __int64 v47 ; __int64 v48 ; __int64 v49 ; __int64 v50 ; __int64 v51 ; __int64 @@v52@@ ; __int64 @@v53@@ ; __int64 @@v54@@ ; __int64 @@v55@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { v2 = * ( _DWORD * ) ( @@a1@@ + Number ) ; v3 = syn_simd_access_trap ( Number , Number , Number ) ; gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , v3 , v2 ) ; return Number L ; } if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) return Number L ; if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v20@@ = ( ( unsigned __int16 ) @@a2@@ >> Number ) | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v20@@ = ( unsigned __int16 ) @@a2@@ >> Number ; } @@v34@@ = HIWORD ( @@a2@@ ) & Number ; @@v35@@ = @@a2@@ & Number ; @@v31@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; @@v36@@ = get_mem_index ( @@a1@@ ) ; if ( ( @@a2@@ & Number ) == Number ) { @@v43@@ = ( @@a2@@ >> Number ) & Number ; v24 = ( unsigned __int8 ) @@a2@@ >> Number ; if ( @@v43@@ > Number ) return Number L ; v5 = @@v43@@ & Number ; if ( v5 == Number ) { if ( ( @@a2@@ & Number ) != Number ) return Number L ; } else if ( v5 == Number && ( ( @@a2@@ >> Number ) & Number ) == Number ) { return Number L ; } v38 = * ( ( _DWORD * ) & neon_ls_element_type + Number * ( int ) @@v43@@ ) ; @@v44@@ = * ( ( _DWORD * ) & unk_4D764 + Number * ( int ) @@v43@@ ) ; @@v45@@ = dword_4D768 [ Number * @@v43@@ ] ; if ( v24 == Number && ( @@v45@@ | @@v44@@ ) != Number ) return Number L ; if ( ! ( ( unsigned __int8 ) @@a2@@ >> Number ) ) @@v31@@ = Number ; if ( @@v44@@ == Number && ! @@v31@@ ) v24 = Number ; @@v52@@ = tcg_temp_new_i64 ( ) ; v49 = tcg_temp_new_i32 ( ) ; @@v53@@ = tcg_const_i32 ( ( unsigned int ) ( Number << v24 ) ) ; load_reg_var ( @@a1@@ , v49 , @@v34@@ ) ; for ( i = Number ; i < v38 ; ++ i ) { for ( @@j@@ = Number ; @@j@@ < Number >> v24 ; ++ @@j@@ ) { for ( @@k@@ = Number ; @@k@@ < @@v44@@ ; ++ @@k@@ ) { @@v46@@ = i + @@v20@@ + @@k@@ * @@v45@@ ; if ( ( @@a2@@ & Number ) != Number ) { gen_aa32_ld_i64 ( @@a1@@ , @@v52@@ , v49 , @@v36@@ , @@v31@@ | v24 ) ; neon_store_element64 ( @@v46@@ , @@j@@ , v24 , @@v52@@ ) ; } else { neon_load_element64 ( @@v52@@ , @@v46@@ , @@j@@ , v24 ) ; gen_aa32_st_i64 ( @@a1@@ , @@v52@@ , v49 , @@v36@@ , @@v31@@ | v24 ) ; } tcg_gen_add_i32 ( v49 , v49 , @@v53@@ ) ; } } } tcg_temp_free_i32 ( v49 ) ; tcg_temp_free_i32 ( @@v53@@ ) ; tcg_temp_free_i64 ( @@v52@@ ) ; v21 = Number * @@v44@@ * v38 ; goto LABEL_111 ; } v25 = ( @@a2@@ >> Number ) & Number ; if ( v25 == Number ) { @@v41@@ = ( @@a2@@ >> Number ) & Number ; if ( ( @@a2@@ & Number ) == Number ) return Number L ; v26 = ( unsigned __int8 ) @@a2@@ >> Number ; v39 = ( ( @@a2@@ >> Number ) & Number ) + Number ; if ( v26 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number || ! @@v41@@ ) return Number L ; v26 = Number ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number && @@v41@@ == Number && ! v26 ) return Number L ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number && @@v41@@ == Number ) return Number L ; v50 = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , v50 , @@v34@@ ) ; if ( ( @@a2@@ & Number ) != Number ) v6 = Number ; else v6 = Number ; v22 = v6 ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) v7 = Number ; else v7 = Number * v6 ; @@v42@@ = v7 ; v47 = tcg_temp_new_i32 ( ) ; for ( l = Number ; l < v39 ; ++ l ) { v8 = v26 | * ( _DWORD * ) ( @@a1@@ + Number ) ; v9 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld_i32 ( @@a1@@ , v47 , v50 , v9 , v8 ) ; if ( ( @@v20@@ & Number ) != Number && @@v42@@ == Number ) { v10 = neon_reg_offset ( @@v20@@ , Number ) ; tcg_gen_gvec_dup_i32 ( v26 , v10 , Number L , Number L , v47 ) ; v11 = neon_reg_offset ( @@v20@@ , Number ) ; v12 = neon_reg_offset ( @@v20@@ + Number , Number ) ; tcg_gen_gvec_mov ( Number L , v12 , v11 , Number L , Number L ) ; } else { v13 = neon_reg_offset ( @@v20@@ , Number ) ; tcg_gen_gvec_dup_i32 ( v26 , v13 , @@v42@@ , @@v42@@ , v47 ) ; } tcg_gen_addi_i32 ( v50 , v50 , ( unsigned int ) ( Number << v26 ) ) ; @@v20@@ += v22 ; } tcg_temp_free_i32 ( v47 ) ; tcg_temp_free_i32 ( v50 ) ; v21 = v39 << v26 ; goto LABEL_111 ; } @@v37@@ = ( unsigned __int8 ) @@a2@@ >> Number ; if ( v25 == Number ) { @@v33@@ = ( @@a2@@ >> Number ) & Number ; if ( ( @@a2@@ & Number ) != Number ) v15 = Number ; else v15 = Number ; v23 = v15 ; } else if ( v25 ) { @@v33@@ = ( unsigned __int8 ) @@a2@@ >> Number ; if ( ( @@a2@@ & Number ) != Number ) v14 = Number ; else v14 = Number ; v23 = v14 ; } else { @@v33@@ = ( unsigned __int8 ) @@a2@@ >> Number ; v23 = Number ; } v40 = ( ( @@a2@@ >> Number ) & Number ) + Number ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { if ( v25 == Number && ( @@v37@@ & Number ) == Number ) return Number L ; goto LABEL_102 ; } if ( v40 > Number ) goto LABEL_101 ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { if ( ( @@a2@@ & Number ) != Number ) return Number L ; LABEL_95 : if ( v25 == Number && ( @@v37@@ & Number ) != Number ) return Number L ; goto LABEL_102 ; } if ( v40 > Number ) goto LABEL_101 ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) LABEL_101 : abort ( ) ; goto LABEL_95 ; } if ( ( ( @@v37@@ >> v25 ) & Number ) != Number || v25 == Number && ( ( @@v37@@ & Number ) == Number || ( @@v37@@ & Number ) == Number ) ) return Number L ; LABEL_102 : if ( ( int ) ( v23 * ( ( @@a2@@ >> Number ) & Number ) + @@v20@@ ) > Number ) return Number L ; v48 = tcg_temp_new_i32 ( ) ; v51 = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , v51 , @@v34@@ ) ; for ( m = Number ; m < v40 ; ++ m ) { if ( ( @@a2@@ & Number ) != Number ) { v16 = v25 | * ( _DWORD * ) ( @@a1@@ + Number ) ; v17 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld_i32 ( @@a1@@ , v48 , v51 , v17 , v16 ) ; neon_store_element ( @@v20@@ , @@v33@@ , v25 , v48 ) ; } else { neon_load_element ( v48 , @@v20@@ , @@v33@@ , v25 ) ; v18 = v25 | * ( _DWORD * ) ( @@a1@@ + Number ) ; v19 = get_mem_index ( @@a1@@ ) ; gen_aa32_st_i32 ( @@a1@@ , v48 , v51 , v19 , v18 ) ; } @@v20@@ += v23 ; tcg_gen_addi_i32 ( v51 , v51 , ( unsigned int ) ( Number << v25 ) ) ; } tcg_temp_free_i32 ( v51 ) ; tcg_temp_free_i32 ( v48 ) ; v21 = v40 << v25 ; LABEL_111 : if ( @@v35@@ != Number ) { @@v54@@ = load_reg ( @@a1@@ , @@v34@@ ) ; if ( @@v35@@ == Number ) { tcg_gen_addi_i32 ( @@v54@@ , @@v54@@ , v21 ) ; } else { @@v55@@ = load_reg ( @@a1@@ , @@v35@@ ) ; tcg_gen_add_i32 ( @@v54@@ , @@v54@@ , @@v55@@ ) ; tcg_temp_free_i32 ( @@v55@@ ) ; } store_reg ( @@a1@@ , @@v34@@ , @@v54@@ ) ; } return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v36\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v35\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s108\"}, {\"n\": \"v34\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s112\"}, {\"n\": \"v33\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s116\"}, {\"n\": \"k\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s120\"}, {\"n\": \"v31\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s124\"}, {\"n\": \"j\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s128\"}, {\"n\": \"v20\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s144\"}, {\"n\": \"v55\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v54\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v53\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v52\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v46\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s68\"}, {\"n\": \"v45\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s72\"}, {\"n\": \"v44\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s76\"}, {\"n\": \"v43\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s80\"}, {\"n\": \"v42\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s84\"}, {\"n\": \"v41\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s88\"}, {\"n\": \"v37\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s96\"}]}",
"{\"name\": \"disas_neon_data_insn\", \"code\": \"__int64 __fastcall disas_neon_data_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; unsigned int v3 ; __int64 result ; int v5 ; char * v6 ; char * v7 ; unsigned int @@v8@@ ; unsigned int v9 ; __int64 v10 ; __int64 @@v11@@ ; unsigned int @@v12@@ ; int v13 ; _BOOL4 v14 ; int v15 ; int v16 ; int v17 ; int v18 ; int v19 ; int v20 ; int v21 ; int v22 ; unsigned int v23 ; int v24 ; unsigned int v25 ; __int64 v26 ; __int64 v27 ; int v28 ; int v29 ; int v30 ; __int64 v31 ; int v32 ; unsigned int v33 ; unsigned int v34 ; unsigned int v35 ; int v36 ; unsigned int @@v37@@ ; unsigned int v38 ; unsigned int @@v39@@ ; unsigned int v40 ; bool @@v42@@ ; int @@v43@@ ; int @@v44@@ ; int @@v45@@ ; unsigned int v46 ; int i3 ; int v48 ; unsigned int v49 ; int v50 ; int v51 ; int v52 ; int v53 ; signed int v54 ; int i ; int v56 ; int j ; int i8 ; int i6 ; int i7 ; int i4 ; int i5 ; int i1 ; int nn ; int kk ; int ll ; int mm ; int k ; int l ; int n ; int ii ; int jj ; int @@v73@@ ; int @@v74@@ ; unsigned int v75 ; unsigned int v76 ; unsigned int v77 ; unsigned int v78 ; unsigned int v79 ; int @@i2@@ ; int @@m@@ ; unsigned int @@v82@@ ; int @@v83@@ ; unsigned int @@v84@@ ; int @@v85@@ ; int @@v86@@ ; unsigned int @@v87@@ ; unsigned int @@v88@@ ; unsigned int @@v89@@ ; unsigned int @@v90@@ ; int v91 ; int v92 ; int v93 ; int v94 ; int v95 ; unsigned int @@v96@@ ; int @@v97@@ ; int @@v98@@ ; int @@v99@@ ; int @@v100@@ ; unsigned int @@v101@@ ; int @@v102@@ ; int @@v103@@ ; __int64 v104 ; __int64 v105 ; __int64 v106 ; __int64 v107 ; __int64 v108 ; __int64 v109 ; __int64 v110 ; __int64 v111 ; __int64 v112 ; __int64 v113 ; __int64 v114 ; __int64 v115 ; __int64 v116 ; __int64 v117 ; __int64 v118 ; __int64 v119 ; __int64 v120 ; __int64 v121 ; __int64 v122 ; __int64 v123 ; __int64 v124 ; __int64 v125 ; __int64 v126 ; __int64 v127 ; __int64 v128 ; __int64 v129 ; __int64 v130 ; __int64 v131 ; __int64 v132 ; __int64 v133 ; __int64 v134 ; __int64 v135 ; __int64 v136 ; __int64 v137 ; __int64 v138 ; __int64 v139 ; __int64 v140 ; __int64 v141 ; __int64 v142 ; __int64 v143 ; __int64 v144 ; __int64 v145 ; __int64 v146 ; __int64 v147 ; __int64 v148 ; __int64 v149 ; __int64 v150 ; __int64 v151 ; __int64 v152 ; __int64 v153 ; __int64 v154 ; __int64 v155 ; __int64 v156 ; __int64 v157 ; __int64 v158 ; __int64 v159 ; __int64 v160 ; __int64 v161 ; __int64 v162 ; __int64 v163 ; __int64 v164 ; __int64 v165 ; __int64 v166 ; __int64 v167 ; __int64 v168 ; __int64 v169 ; __int64 v170 ; __int64 v171 ; __int64 @@v172@@ ; __int64 @@v173@@ ; unsigned __int64 @@v174@@ ; unsigned __int64 ( __fastcall * @@v175@@ ) ( __int64 , __int64 , __int64 , __int64 ) ; __int64 @@v176@@ ; unsigned __int64 ( __fastcall * @@v177@@ ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; __int64 v178 ; __int64 v179 ; __int64 @@v180@@ ; __int64 @@v181@@ ; __int64 @@v182@@ ; __int64 @@v183@@ ; __int64 @@v184@@ ; __int64 @@v185@@ ; __int64 @@v186@@ ; __int64 @@v187@@ ; __int64 @@v188@@ ; __int64 @@v189@@ ; __int64 @@v190@@ ; __int64 @@v191@@ ; __int64 @@v192@@ ; __int64 @@v193@@ ; __int64 @@v194@@ ; __int64 @@v195@@ ; __int64 @@v196@@ ; __int64 @@v197@@ ; __int64 @@v198@@ ; __int64 @@v199@@ ; __int64 @@v200@@ ; __int64 @@v201@@ ; __int64 @@v202@@ ; __int64 v203 ; __int64 v204 ; __int64 v205 ; __int64 v206 ; __int64 v207 ; __int64 @@v208@@ ; __int64 @@v209@@ ; __int64 @@v210@@ ; __int64 @@v211@@ ; __int64 @@v212@@ ; __int64 @@v213@@ ; __int64 @@v214@@ ; __int64 @@v215@@ ; __int64 @@v216@@ ; __int64 @@v217@@ ; __int64 @@v218@@ ; __int64 @@v219@@ ; __int64 @@v220@@ ; __int64 @@v221@@ ; __int64 @@v222@@ ; __int64 @@v223@@ ; __int64 @@v224@@ ; __int64 @@v225@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { v2 = * ( _DWORD * ) ( @@a1@@ + Number ) ; v3 = syn_simd_access_trap ( Number , Number , Number ) ; gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , v3 , v2 ) ; return Number L ; } if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) return Number L ; @@v85@@ = ( @@a2@@ & Number ) != Number ; @@v86@@ = HIBYTE ( @@a2@@ ) & Number ; if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v43@@ = ( ( unsigned __int16 ) @@a2@@ >> Number ) | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v43@@ = ( unsigned __int16 ) @@a2@@ >> Number ; } if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v44@@ = HIWORD ( @@a2@@ ) & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v44@@ = HIWORD ( @@a2@@ ) & Number ; } if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v45@@ = @@a2@@ & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v45@@ = @@a2@@ & Number ; } v46 = ( @@a2@@ >> Number ) & Number ; if ( ( @@a2@@ & Number ) != Number ) v5 = Number ; else v5 = Number ; @@v87@@ = v5 ; @@v88@@ = neon_reg_offset ( @@v43@@ , Number ) ; @@v89@@ = neon_reg_offset ( @@v44@@ , Number ) ; @@v90@@ = neon_reg_offset ( @@v45@@ , Number ) ; if ( ( @@a2@@ & Number ) == Number ) { v91 = ( @@a2@@ >> Number ) & Number | ( @@a2@@ >> Number ) & Number ; if ( ( ( ( int ) neon_3r_sizes [ v91 ] >> v46 ) & Number ) == Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number && ( ( ( unsigned __int8 ) @@v45@@ | ( unsigned __int8 ) ( @@v44@@ | @@v43@@ ) ) & Number ) != Number ) return Number L ; switch ( v91 ) { case Number : if ( @@v86@@ ) v6 = ( char * ) & uqadd_op ; else v6 = ( char * ) & sqadd_op ; goto LABEL_76 ; case Number : switch ( v46 | ( Number * @@v86@@ ) ) { case Number : tcg_gen_gvec_and ( Number L , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_andc ( Number L , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_or ( Number L , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_orc ( Number L , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_xor ( Number L , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_bitsel ( Number L , @@v88@@ , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_bitsel ( Number L , @@v88@@ , @@v90@@ , @@v89@@ , @@v88@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_bitsel ( Number L , @@v88@@ , @@v90@@ , @@v88@@ , @@v89@@ , @@v87@@ , @@v87@@ ) ; break ; default : return Number L ; } return Number L ; case Number : if ( @@v86@@ ) v6 = ( char * ) & uqsub_op ; else v6 = ( char * ) & sqsub_op ; LABEL_76 : tcg_gen_gvec_4 ( @@v88@@ , Number L , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ , & v6 [ Number * v46 ] ) ; return Number L ; case Number : @@v8@@ = @@v87@@ ; v9 = @@v90@@ ; v10 = @@v89@@ ; @@v11@@ = @@v88@@ ; if ( @@v86@@ ) @@v12@@ = Number ; else @@v12@@ = Number ; goto LABEL_95 ; case Number : @@v8@@ = @@v87@@ ; v9 = @@v90@@ ; v10 = @@v89@@ ; @@v11@@ = @@v88@@ ; if ( @@v86@@ ) @@v12@@ = Number ; else @@v12@@ = Number ; LABEL_95 : tcg_gen_gvec_cmp ( @@v12@@ , v46 , @@v11@@ , v10 , v9 , @@v8@@ , @@v87@@ ) ; return Number L ; case Number : if ( @@v86@@ ) tcg_gen_gvec_umax ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; else tcg_gen_gvec_smax ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : if ( @@v86@@ ) tcg_gen_gvec_umin ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; else tcg_gen_gvec_smin ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : if ( @@v86@@ ) tcg_gen_gvec_sub ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; else tcg_gen_gvec_add ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : if ( @@v86@@ ) tcg_gen_gvec_cmp ( Number L , v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; else tcg_gen_gvec_3 ( @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ , ( char * ) & cmtst_op + Number * ( int ) v46 ) ; return Number L ; case Number : if ( @@v86@@ ) v7 = ( char * ) & mls_op + Number * ( int ) v46 ; else v7 = ( char * ) & mla_op + Number * ( int ) v46 ; tcg_gen_gvec_3 ( @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ , v7 ) ; return Number L ; case Number : if ( @@v86@@ ) { if ( ! v46 ) goto LABEL_107 ; result = Number L ; } else { tcg_gen_gvec_mul ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; result = Number L ; } return result ; case Number : if ( ! @@v86@@ ) goto LABEL_107 ; if ( v46 == Number ) return do_v81_helper ( @@a1@@ , ( __int64 ) gen_helper_gvec_qrdmlah_s16 , @@v85@@ , @@v43@@ , @@v44@@ , @@v45@@ ) ; if ( v46 == Number ) return do_v81_helper ( @@a1@@ , ( __int64 ) gen_helper_gvec_qrdmlah_s32 , @@v85@@ , @@v43@@ , @@v44@@ , @@v45@@ ) ; return Number L ; case Number : if ( ( @@a2@@ & Number ) == Number ) return Number L ; if ( @@v86@@ ) { if ( ! isar_feature_aa32_sha2 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || v46 == Number ) return Number L ; v163 = vfp_reg_ptr ( Number , @@v43@@ ) ; v168 = vfp_reg_ptr ( Number , @@v44@@ ) ; @@v172@@ = vfp_reg_ptr ( Number , @@v45@@ ) ; if ( v46 == Number ) { gen_helper_crypto_sha256su1 ( v163 , v168 , @@v172@@ ) ; } else if ( v46 ) { gen_helper_crypto_sha256h2 ( v163 , v168 , @@v172@@ ) ; } else { gen_helper_crypto_sha256h ( v163 , v168 , @@v172@@ ) ; } } else { if ( ! isar_feature_aa32_sha1 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; v163 = vfp_reg_ptr ( Number , @@v43@@ ) ; v168 = vfp_reg_ptr ( Number , @@v44@@ ) ; @@v172@@ = vfp_reg_ptr ( Number , @@v45@@ ) ; v205 = tcg_const_i32 ( v46 ) ; gen_helper_crypto_sha1_3reg ( v163 , v168 , @@v172@@ , v205 ) ; tcg_temp_free_i32 ( v205 ) ; } tcg_temp_free_ptr ( v163 ) ; tcg_temp_free_ptr ( v168 ) ; tcg_temp_free_ptr ( @@v172@@ ) ; return Number L ; case Number : if ( @@v86@@ ) { if ( v46 == Number ) return do_v81_helper ( @@a1@@ , ( __int64 ) gen_helper_gvec_qrdmlsh_s16 , @@v85@@ , @@v43@@ , @@v44@@ , @@v45@@ ) ; if ( v46 == Number ) return do_v81_helper ( @@a1@@ , ( __int64 ) gen_helper_gvec_qrdmlsh_s32 , @@v85@@ , @@v43@@ , @@v44@@ , @@v45@@ ) ; return Number L ; } if ( v46 == Number ) return Number L ; LABEL_107 : if ( v46 == Number ) { for ( i = Number ; ; ++ i ) { v13 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v13 <= i ) break ; neon_load_reg64 ( cpu_V0 , i + @@v44@@ ) ; neon_load_reg64 ( cpu_V1 , i + @@v45@@ ) ; if ( v91 == Number ) { if ( @@v86@@ ) gen_helper_neon_qrshl_u64 ( cpu_V0 , cpu_env , cpu_V1 , cpu_V0 ) ; else gen_helper_neon_qrshl_s64 ( cpu_V0 , cpu_env , cpu_V1 , cpu_V0 ) ; } else { if ( v91 > Number ) goto LABEL_127 ; switch ( v91 ) { case Number : if ( @@v86@@ ) gen_helper_neon_rshl_u64 ( cpu_V0 , cpu_V1 , cpu_V0 ) ; else gen_helper_neon_rshl_s64 ( cpu_V0 , cpu_V1 , cpu_V0 ) ; break ; case Number : if ( @@v86@@ ) gen_helper_neon_shl_u64 ( cpu_V0 , cpu_V1 , cpu_V0 ) ; else gen_helper_neon_shl_s64 ( cpu_V0 , cpu_V1 , cpu_V0 ) ; break ; case Number : if ( @@v86@@ ) gen_helper_neon_qshl_u64 ( cpu_V0 , cpu_env , cpu_V1 , cpu_V0 ) ; else gen_helper_neon_qshl_s64 ( cpu_V0 , cpu_env , cpu_V1 , cpu_V0 ) ; break ; default : LABEL_127 : abort ( ) ; } } neon_store_reg64 ( cpu_V0 , i + @@v43@@ ) ; } return Number L ; } @@v74@@ = Number ; switch ( v91 ) { case Number : case Number : case Number : case Number : @@v103@@ = @@v44@@ ; @@v44@@ = @@v45@@ ; @@v45@@ = @@v103@@ ; goto LABEL_153 ; case Number : case Number : case Number : @@v74@@ = Number ; goto LABEL_153 ; case Number : if ( arm_dc_feature ( @@a1@@ , Number ) ) goto LABEL_153 ; return Number L ; case Number : v14 = @@v86@@ && ( ( @@a2@@ >> Number ) & Number ) <= Number ; @@v74@@ = v14 ; goto LABEL_153 ; case Number : if ( @@v86@@ || ! v46 ) goto LABEL_153 ; return Number L ; case Number : if ( @@v86@@ ) goto LABEL_153 ; return Number L ; case Number : @@v74@@ = HIBYTE ( @@a2@@ ) & Number ; goto LABEL_153 ; case Number : if ( ! @@v86@@ || arm_dc_feature ( @@a1@@ , Number ) ) goto LABEL_153 ; return Number L ; default : LABEL_153 : if ( @@v74@@ && ( @@a2@@ & Number ) != Number ) return Number L ; v56 = Number ; while ( Number ) { v16 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v16 <= v56 ) break ; if ( @@v74@@ ) { if ( v56 > Number ) { v104 = neon_load_reg ( @@v45@@ , Number ) ; v128 = neon_load_reg ( @@v45@@ , Number ) ; } else { v104 = neon_load_reg ( @@v44@@ , Number ) ; v128 = neon_load_reg ( @@v44@@ , Number ) ; } } else { v104 = neon_load_reg ( @@v44@@ , v56 ) ; v128 = neon_load_reg ( @@v45@@ , v56 ) ; } switch ( v91 ) { case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_hadd_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hadd_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hadd_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hadd_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hadd_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hadd_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_rhadd_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rhadd_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rhadd_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rhadd_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rhadd_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rhadd_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_hsub_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hsub_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hsub_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hsub_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hsub_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hsub_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_shl_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_shl_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_shl_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_shl_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_shl_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_shl_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_qshl_s8 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qshl_u8 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qshl_s16 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qshl_u16 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qshl_s32 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qshl_u32 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_rshl_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rshl_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rshl_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rshl_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rshl_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rshl_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_qrshl_s8 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qrshl_u8 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qrshl_s16 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qrshl_u16 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qrshl_s32 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qrshl_u32 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_abd_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_abd_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_abd_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_abd_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_abd_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_abd_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_abd_s8 ( v104 , v104 , v128 ) ; goto LABEL_235 ; case Number : gen_helper_neon_abd_u8 ( v104 , v104 , v128 ) ; goto LABEL_235 ; case Number : gen_helper_neon_abd_s16 ( v104 , v104 , v128 ) ; goto LABEL_235 ; case Number : gen_helper_neon_abd_u16 ( v104 , v104 , v128 ) ; goto LABEL_235 ; case Number : gen_helper_neon_abd_s32 ( v104 , v104 , v128 ) ; goto LABEL_235 ; case Number : gen_helper_neon_abd_u32 ( v104 , v104 , v128 ) ; LABEL_235 : tcg_temp_free_i32 ( v128 ) ; v128 = neon_load_reg ( @@v43@@ , v56 ) ; gen_neon_add ( v46 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : gen_helper_neon_mul_p8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_pmax_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmax_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmax_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmax_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : tcg_gen_smax_i32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : tcg_gen_umax_i32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_pmin_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmin_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmin_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmin_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : tcg_gen_smin_i32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : tcg_gen_umin_i32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : if ( @@v86@@ ) { if ( v46 == Number ) { gen_helper_neon_qrdmulh_s16 ( v104 , cpu_env , v104 , v128 ) ; } else { if ( v46 != Number ) abort ( ) ; gen_helper_neon_qrdmulh_s32 ( v104 , cpu_env , v104 , v128 ) ; } } else if ( v46 == Number ) { gen_helper_neon_qdmulh_s16 ( v104 , cpu_env , v104 , v128 ) ; } else { if ( v46 != Number ) abort ( ) ; gen_helper_neon_qdmulh_s32 ( v104 , cpu_env , v104 , v128 ) ; } goto LABEL_312 ; case Number : if ( v46 == Number ) { tcg_gen_add_i32 ( v104 , v104 , v128 ) ; } else if ( v46 ) { gen_helper_neon_padd_u16 ( v104 , v104 , v128 ) ; } else { gen_helper_neon_padd_u8 ( v104 , v104 , v128 ) ; } goto LABEL_312 ; case Number : @@v224@@ = get_fpstatus_ptr ( Number ) ; @@v225@@ = neon_load_reg ( @@v43@@ , v56 ) ; if ( v46 ) gen_helper_vfp_negs ( v104 , v104 ) ; gen_helper_vfp_muladds ( v104 , v104 , v128 , @@v225@@ , @@v224@@ ) ; tcg_temp_free_i32 ( @@v225@@ ) ; tcg_temp_free_ptr ( @@v224@@ ) ; goto LABEL_312 ; case Number : @@v223@@ = get_fpstatus_ptr ( Number ) ; v15 = v46 | ( Number * @@v86@@ ) ; if ( v15 == Number ) { gen_helper_neon_abd_f32 ( v104 , v104 , v128 , @@v223@@ ) ; } else { if ( v15 > Number ) goto LABEL_279 ; if ( v15 == Number ) goto LABEL_276 ; if ( v15 > Number ) goto LABEL_279 ; if ( ! v15 ) { LABEL_276 : gen_helper_vfp_adds ( v104 , v104 , v128 , @@v223@@ ) ; } else { if ( v15 != Number ) LABEL_279 : abort ( ) ; gen_helper_vfp_subs ( v104 , v104 , v128 , @@v223@@ ) ; } } tcg_temp_free_ptr ( @@v223@@ ) ; LABEL_312 : tcg_temp_free_i32 ( v128 ) ; if ( @@v74@@ && @@v43@@ == @@v45@@ ) neon_store_scratch ( v56 , v104 ) ; else neon_store_reg ( @@v43@@ , v56 , v104 ) ; ++ v56 ; break ; case Number : @@v222@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_muls ( v104 , v104 , v128 , @@v222@@ ) ; if ( ! @@v86@@ ) { tcg_temp_free_i32 ( v128 ) ; v128 = neon_load_reg ( @@v43@@ , v56 ) ; if ( v46 ) gen_helper_vfp_subs ( v104 , v128 , v104 , @@v222@@ ) ; else gen_helper_vfp_adds ( v104 , v104 , v128 , @@v222@@ ) ; } tcg_temp_free_ptr ( @@v222@@ ) ; goto LABEL_312 ; case Number : @@v221@@ = get_fpstatus_ptr ( Number ) ; if ( @@v86@@ ) { if ( v46 ) gen_helper_neon_cgt_f32 ( v104 , v104 , v128 , @@v221@@ ) ; else gen_helper_neon_cge_f32 ( v104 , v104 , v128 , @@v221@@ ) ; } else { gen_helper_neon_ceq_f32 ( v104 , v104 , v128 , @@v221@@ ) ; } tcg_temp_free_ptr ( @@v221@@ ) ; goto LABEL_312 ; case Number : @@v220@@ = get_fpstatus_ptr ( Number ) ; if ( v46 ) gen_helper_neon_acgt_f32 ( v104 , v104 , v128 , @@v220@@ ) ; else gen_helper_neon_acge_f32 ( v104 , v104 , v128 , @@v220@@ ) ; tcg_temp_free_ptr ( @@v220@@ ) ; goto LABEL_312 ; case Number : @@v219@@ = get_fpstatus_ptr ( Number ) ; if ( v46 ) gen_helper_vfp_mins ( v104 , v104 , v128 , @@v219@@ ) ; else gen_helper_vfp_maxs ( v104 , v104 , v128 , @@v219@@ ) ; tcg_temp_free_ptr ( @@v219@@ ) ; goto LABEL_312 ; case Number : if ( @@v86@@ ) { @@v218@@ = get_fpstatus_ptr ( Number ) ; if ( v46 ) gen_helper_vfp_minnums ( v104 , v104 , v128 , @@v218@@ ) ; else gen_helper_vfp_maxnums ( v104 , v104 , v128 , @@v218@@ ) ; tcg_temp_free_ptr ( @@v218@@ ) ; } else if ( v46 ) { gen_helper_rsqrts_f32 ( v104 , v104 , v128 , cpu_env ) ; } else { gen_helper_recps_f32 ( v104 , v104 , v128 , cpu_env ) ; } goto LABEL_312 ; default : abort ( ) ; } } if ( @@v74@@ && @@v43@@ == @@v45@@ ) { for ( j = Number ; ; ++ j ) { v17 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v17 <= j ) break ; v105 = neon_load_scratch ( j ) ; neon_store_reg ( @@v43@@ , j , v105 ) ; } } break ; } break ; default : goto LABEL_107 ; } return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { if ( v46 == Number ) { LABEL_722 : if ( @@v86@@ ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) return Number L ; if ( ( @@a2@@ & Number ) == Number || ( @@a2@@ & Number ) != Number && ( @@v43@@ & Number ) != Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { @@v84@@ = Number ; @@v83@@ = ( @@a2@@ >> Number ) & Number ; } else if ( ( @@a2@@ & Number ) != Number ) { @@v84@@ = Number ; @@v83@@ = ( @@a2@@ >> Number ) & Number ; } else { @@v84@@ = Number ; @@v83@@ = ( @@a2@@ >> Number ) & Number ; } if ( ( @@a2@@ & Number ) != Number ) @@v37@@ = Number ; else @@v37@@ = Number ; if ( ( @@a2@@ & Number ) != Number ) v38 = Number ; else v38 = Number ; @@v39@@ = neon_element_offset ( @@v45@@ , @@v83@@ , @@v84@@ ) ; v40 = neon_reg_offset ( @@v43@@ , Number ) ; tcg_gen_gvec_dup_mem ( @@v84@@ , v40 , @@v39@@ , v38 , @@v37@@ ) ; } else { if ( ( int ) ( @@v44@@ + ( ( @@a2@@ >> Number ) & Number ) + Number ) > Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { v126 = neon_load_reg ( @@v43@@ , Number ) ; } else { v126 = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( v126 , Number ) ; } v153 = neon_load_reg ( @@v45@@ , Number ) ; v167 = vfp_reg_ptr ( Number , @@v44@@ ) ; v179 = tcg_const_i32 ( Number * ( ( ( @@a2@@ >> Number ) & Number ) + Number ) ) ; gen_helper_neon_tbl ( v153 , v153 , v126 , v167 , v179 ) ; tcg_temp_free_i32 ( v126 ) ; if ( ( @@a2@@ & Number ) != Number ) { v127 = neon_load_reg ( @@v43@@ , Number ) ; } else { v127 = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( v127 , Number ) ; } v162 = neon_load_reg ( @@v45@@ , Number ) ; gen_helper_neon_tbl ( v162 , v162 , v127 , v167 , v179 ) ; tcg_temp_free_i32 ( v179 ) ; tcg_temp_free_ptr ( v167 ) ; neon_store_reg ( @@v43@@ , Number , v153 ) ; neon_store_reg ( @@v43@@ , Number , v162 ) ; tcg_temp_free_i32 ( v127 ) ; } } else { v95 = ( @@a2@@ >> Number ) & Number | ( @@a2@@ >> Number ) & Number ; v49 = ( @@a2@@ >> Number ) & Number ; if ( ( ( ( int ) neon_2rm_sizes [ v95 ] >> ( ( @@a2@@ >> Number ) & Number ) ) & Number ) == Number ) return Number L ; if ( neon_2rm_is_v8_op ( v95 ) && ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( v95 != Number && v95 != Number && ( @@a2@@ & Number ) != Number && ( ( ( unsigned __int8 ) @@v43@@ | ( unsigned __int8 ) @@v45@@ ) & Number ) != Number ) return Number L ; switch ( v95 ) { case Number : for ( k = Number ; ; ++ k ) { v30 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v30 <= k ) break ; v117 = neon_load_reg ( @@v45@@ , Number * k ) ; v137 = neon_load_reg ( @@v45@@ , Number * k + Number ) ; if ( v49 != Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_swap_half ( v117 ) ; else tcg_gen_bswap32_i32 ( v117 , v117 ) ; } neon_store_reg ( @@v43@@ , Number * k + Number , v117 ) ; if ( v49 != Number ) { if ( v49 ) gen_swap_half ( v137 ) ; else tcg_gen_bswap32_i32 ( v137 , v137 ) ; } neon_store_reg ( @@v43@@ , Number * k , v137 ) ; } return Number L ; case Number : case Number : case Number : case Number : for ( l = Number ; l < @@v85@@ + Number ; ++ l ) { v31 = neon_load_reg ( @@v45@@ , Number * l ) ; gen_neon_widen ( cpu_V0 , v31 , v49 , v95 & Number ) ; v118 = neon_load_reg ( @@v45@@ , Number * l + Number ) ; gen_neon_widen ( cpu_V1 , v118 , v49 , v95 & Number ) ; if ( v49 == Number ) { tcg_gen_add_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_paddl_u32 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; else gen_helper_neon_paddl_u16 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; } if ( v95 > Number ) { neon_load_reg64 ( cpu_V1 , l + @@v43@@ ) ; gen_neon_addl ( v49 ) ; } neon_store_reg64 ( cpu_V0 , l + @@v43@@ ) ; } return Number L ; case Number : case Number : if ( ! isar_feature_aa32_aes ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ( ( ( unsigned __int8 ) @@v43@@ | ( unsigned __int8 ) @@v45@@ ) & Number ) != Number ) { return Number L ; } v164 = vfp_reg_ptr ( Number , @@v43@@ ) ; v169 = vfp_reg_ptr ( Number , @@v45@@ ) ; v33 = extract32 ( @@a2@@ , Number , Number ) ; v161 = tcg_const_i32 ( v33 ) ; if ( v95 == Number ) gen_helper_crypto_aese ( v164 , v169 , v161 ) ; else gen_helper_crypto_aesmc ( v164 , v169 , v161 ) ; tcg_temp_free_ptr ( v164 ) ; tcg_temp_free_ptr ( v169 ) ; tcg_temp_free_i32 ( v161 ) ; return Number L ; case Number : tcg_gen_gvec_not ( Number L , @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : if ( ! isar_feature_aa32_sha1 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ( ( ( unsigned __int8 ) @@v43@@ | ( unsigned __int8 ) @@v45@@ ) & Number ) != Number ) { return Number L ; } v165 = vfp_reg_ptr ( Number , @@v43@@ ) ; v170 = vfp_reg_ptr ( Number , @@v45@@ ) ; gen_helper_crypto_sha1h ( v165 , v170 ) ; tcg_temp_free_ptr ( v165 ) ; tcg_temp_free_ptr ( v170 ) ; return Number L ; case Number : tcg_gen_gvec_abs ( v49 , @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : tcg_gen_gvec_neg ( v49 , @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : if ( v49 != Number ) goto LABEL_853 ; for ( @@m@@ = Number ; ; @@m@@ += Number ) { v32 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v32 <= @@m@@ ) break ; v119 = neon_load_reg ( @@v45@@ , @@m@@ ) ; v138 = neon_load_reg ( @@v43@@ , @@m@@ + Number ) ; neon_store_reg ( @@v45@@ , @@m@@ , v138 ) ; neon_store_reg ( @@v43@@ , @@m@@ + Number , v119 ) ; } return Number L ; case Number : return ( unsigned int ) gen_neon_unzip ( @@v43@@ , @@v45@@ , v49 , @@v85@@ ) != Number ; case Number : return ( unsigned int ) gen_neon_zip ( @@v43@@ , @@v45@@ , v49 , @@v85@@ ) != Number ; case Number : case Number : if ( ( @@v45@@ & Number ) != Number ) return Number L ; v139 = Number L ; for ( n = Number ; n <= Number ; ++ n ) { neon_load_reg64 ( cpu_V0 , n + @@v45@@ ) ; v120 = tcg_temp_new_i32 ( ) ; gen_neon_narrow_op ( v95 == Number , @@v85@@ , v49 , v120 , cpu_V0 ) ; if ( n ) { neon_store_reg ( @@v43@@ , Number , v139 ) ; neon_store_reg ( @@v43@@ , Number , v120 ) ; } else { v139 = v120 ; } } return Number L ; case Number : if ( ( @@a2@@ & Number ) != Number || ( @@v43@@ & Number ) != Number ) return Number L ; v121 = neon_load_reg ( @@v45@@ , Number ) ; v140 = neon_load_reg ( @@v45@@ , Number ) ; for ( ii = Number ; ii <= Number ; ++ ii ) { if ( ii == Number ) v121 = v140 ; gen_neon_widen ( cpu_V0 , v121 , v49 , Number ) ; tcg_gen_shli_i64 ( cpu_V0 , cpu_V0 , Number << v49 ) ; neon_store_reg64 ( cpu_V0 , ii + @@v43@@ ) ; } return Number L ; case Number : if ( ( ( ( unsigned __int8 ) @@v43@@ | ( unsigned __int8 ) @@v45@@ ) & Number ) != Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { if ( ! isar_feature_aa32_sha2 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; } else if ( ! isar_feature_aa32_sha1 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) { return Number L ; } v166 = vfp_reg_ptr ( Number , @@v43@@ ) ; v171 = vfp_reg_ptr ( Number , @@v45@@ ) ; if ( ( @@a2@@ & Number ) != Number ) gen_helper_crypto_sha256su0 ( v166 , v171 ) ; else gen_helper_crypto_sha1su1 ( v166 , v171 ) ; tcg_temp_free_ptr ( v166 ) ; tcg_temp_free_ptr ( v171 ) ; return Number L ; case Number : if ( ! isar_feature_aa32_fp16_spconv ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ( @@a2@@ & Number ) != Number || ( @@v45@@ & Number ) != Number ) return Number L ; @@v182@@ = get_fpstatus_ptr ( Number ) ; @@v183@@ = get_ahp_flag ( ) ; v122 = neon_load_reg ( @@v45@@ , Number ) ; gen_helper_vfp_fcvt_f32_to_f16 ( v122 , v122 , @@v182@@ , @@v183@@ ) ; v141 = neon_load_reg ( @@v45@@ , Number ) ; gen_helper_vfp_fcvt_f32_to_f16 ( v141 , v141 , @@v182@@ , @@v183@@ ) ; tcg_gen_shli_i32 ( v141 , v141 , Number L ) ; tcg_gen_or_i32 ( v141 , v141 , v122 ) ; tcg_temp_free_i32 ( v122 ) ; v123 = neon_load_reg ( @@v45@@ , Number ) ; gen_helper_vfp_fcvt_f32_to_f16 ( v123 , v123 , @@v182@@ , @@v183@@ ) ; v158 = neon_load_reg ( @@v45@@ , Number ) ; neon_store_reg ( @@v43@@ , Number , v141 ) ; gen_helper_vfp_fcvt_f32_to_f16 ( v158 , v158 , @@v182@@ , @@v183@@ ) ; tcg_gen_shli_i32 ( v158 , v158 , Number L ) ; tcg_gen_or_i32 ( v158 , v158 , v123 ) ; neon_store_reg ( @@v43@@ , Number , v158 ) ; tcg_temp_free_i32 ( v123 ) ; tcg_temp_free_i32 ( @@v183@@ ) ; tcg_temp_free_ptr ( @@v182@@ ) ; return Number L ; case Number : if ( ! isar_feature_aa32_fp16_spconv ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ( @@a2@@ & Number ) != Number || ( @@v43@@ & Number ) != Number ) return Number L ; @@v180@@ = get_fpstatus_ptr ( Number ) ; @@v181@@ = get_ahp_flag ( ) ; v159 = tcg_temp_new_i32 ( ) ; v124 = neon_load_reg ( @@v45@@ , Number ) ; v142 = neon_load_reg ( @@v45@@ , Number ) ; tcg_gen_ext16u_i32 ( v159 , v124 ) ; gen_helper_vfp_fcvt_f16_to_f32 ( v159 , v159 , @@v180@@ , @@v181@@ ) ; neon_store_reg ( @@v43@@ , Number , v159 ) ; tcg_gen_shri_i32 ( v124 , v124 , Number L ) ; gen_helper_vfp_fcvt_f16_to_f32 ( v124 , v124 , @@v180@@ , @@v181@@ ) ; neon_store_reg ( @@v43@@ , Number , v124 ) ; v160 = tcg_temp_new_i32 ( ) ; tcg_gen_ext16u_i32 ( v160 , v142 ) ; gen_helper_vfp_fcvt_f16_to_f32 ( v160 , v160 , @@v180@@ , @@v181@@ ) ; neon_store_reg ( @@v43@@ , Number , v160 ) ; tcg_gen_shri_i32 ( v142 , v142 , Number L ) ; gen_helper_vfp_fcvt_f16_to_f32 ( v142 , v142 , @@v180@@ , @@v181@@ ) ; neon_store_reg ( @@v43@@ , Number , v142 ) ; tcg_temp_free_i32 ( @@v181@@ ) ; tcg_temp_free_ptr ( @@v180@@ ) ; break ; default : LABEL_853 : for ( jj = Number ; ; ++ jj ) { v36 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v36 <= jj ) break ; v125 = neon_load_reg ( @@v45@@ , jj ) ; switch ( v95 ) { case Number : if ( v49 ) { if ( v49 != Number ) abort ( ) ; gen_swap_half ( v125 ) ; } else { tcg_gen_bswap32_i32 ( v125 , v125 ) ; } break ; case Number : gen_rev16 ( v125 , v125 ) ; break ; case Number : if ( v49 == Number ) { gen_helper_neon_cls_s32 ( v125 , v125 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_cls_s16 ( v125 , v125 ) ; else gen_helper_neon_cls_s8 ( v125 , v125 ) ; } break ; case Number : if ( v49 == Number ) { tcg_gen_clzi_i32 ( v125 , v125 , Number L ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_clz_u16 ( v125 , v125 ) ; else gen_helper_neon_clz_u8 ( v125 , v125 ) ; } break ; case Number : gen_helper_neon_cnt_u8 ( v125 , v125 ) ; break ; case Number : if ( v49 == Number ) { gen_helper_neon_qabs_s32 ( v125 , cpu_env , v125 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_qabs_s16 ( v125 , cpu_env , v125 ) ; else gen_helper_neon_qabs_s8 ( v125 , cpu_env , v125 ) ; } break ; case Number : if ( v49 == Number ) { gen_helper_neon_qneg_s32 ( v125 , cpu_env , v125 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_qneg_s16 ( v125 , cpu_env , v125 ) ; else gen_helper_neon_qneg_s8 ( v125 , cpu_env , v125 ) ; } break ; case Number : case Number : v143 = tcg_const_i32 ( Number L ) ; if ( v49 == Number ) { gen_helper_neon_cgt_s32 ( v125 , v125 , v143 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_cgt_s16 ( v125 , v125 , v143 ) ; else gen_helper_neon_cgt_s8 ( v125 , v125 , v143 ) ; } tcg_temp_free_i32 ( v143 ) ; if ( v95 == Number ) goto LABEL_898 ; break ; case Number : case Number : v144 = tcg_const_i32 ( Number L ) ; if ( v49 == Number ) { gen_helper_neon_cge_s32 ( v125 , v125 , v144 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_cge_s16 ( v125 , v125 , v144 ) ; else gen_helper_neon_cge_s8 ( v125 , v125 , v144 ) ; } tcg_temp_free_i32 ( v144 ) ; if ( v95 == Number ) LABEL_898 : tcg_gen_not_i32 ( v125 , v125 ) ; break ; case Number : v145 = tcg_const_i32 ( Number L ) ; if ( v49 == Number ) { gen_helper_neon_ceq_u32 ( v125 , v125 , v145 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_ceq_u16 ( v125 , v125 , v145 ) ; else gen_helper_neon_ceq_u8 ( v125 , v125 , v145 ) ; } tcg_temp_free_i32 ( v145 ) ; break ; case Number : @@v202@@ = get_fpstatus_ptr ( Number ) ; v146 = tcg_const_i32 ( Number L ) ; gen_helper_neon_cgt_f32 ( v125 , v125 , v146 , @@v202@@ ) ; tcg_temp_free_i32 ( v146 ) ; tcg_temp_free_ptr ( @@v202@@ ) ; break ; case Number : @@v201@@ = get_fpstatus_ptr ( Number ) ; v147 = tcg_const_i32 ( Number L ) ; gen_helper_neon_cge_f32 ( v125 , v125 , v147 , @@v201@@ ) ; tcg_temp_free_i32 ( v147 ) ; tcg_temp_free_ptr ( @@v201@@ ) ; break ; case Number : @@v200@@ = get_fpstatus_ptr ( Number ) ; v148 = tcg_const_i32 ( Number L ) ; gen_helper_neon_ceq_f32 ( v125 , v125 , v148 , @@v200@@ ) ; tcg_temp_free_i32 ( v148 ) ; tcg_temp_free_ptr ( @@v200@@ ) ; break ; case Number : @@v199@@ = get_fpstatus_ptr ( Number ) ; v149 = tcg_const_i32 ( Number L ) ; gen_helper_neon_cge_f32 ( v125 , v149 , v125 , @@v199@@ ) ; tcg_temp_free_i32 ( v149 ) ; tcg_temp_free_ptr ( @@v199@@ ) ; break ; case Number : @@v198@@ = get_fpstatus_ptr ( Number ) ; v150 = tcg_const_i32 ( Number L ) ; gen_helper_neon_cgt_f32 ( v125 , v150 , v125 , @@v198@@ ) ; tcg_temp_free_i32 ( v150 ) ; tcg_temp_free_ptr ( @@v198@@ ) ; break ; case Number : gen_helper_vfp_abss ( v125 , v125 ) ; break ; case Number : gen_helper_vfp_negs ( v125 , v125 ) ; break ; case Number : v151 = neon_load_reg ( @@v43@@ , jj ) ; neon_store_reg ( @@v45@@ , jj , v151 ) ; break ; case Number : v152 = neon_load_reg ( @@v43@@ , jj ) ; if ( v49 ) { if ( v49 != Number ) abort ( ) ; gen_neon_trn_u16 ( v125 , v152 ) ; } else { gen_neon_trn_u8 ( v125 , v152 ) ; } neon_store_reg ( @@v45@@ , jj , v152 ) ; break ; case Number : case Number : case Number : case Number : case Number : @@v196@@ = get_fpstatus_ptr ( Number ) ; if ( v95 == Number ) @@v82@@ = Number ; else @@v82@@ = fp_decode_rm [ ( v95 >> Number ) & Number ^ Number ] ; v34 = arm_rmode_to_sf ( @@v82@@ ) ; @@v197@@ = tcg_const_i32 ( v34 ) ; gen_helper_set_neon_rmode ( @@v197@@ , @@v197@@ , cpu_env ) ; gen_helper_rints ( v125 , v125 , @@v196@@ ) ; gen_helper_set_neon_rmode ( @@v197@@ , @@v197@@ , cpu_env ) ; tcg_temp_free_ptr ( @@v196@@ ) ; tcg_temp_free_i32 ( @@v197@@ ) ; break ; case Number : @@v195@@ = get_fpstatus_ptr ( Number ) ; gen_helper_rints_exact ( v125 , v125 , @@v195@@ ) ; tcg_temp_free_ptr ( @@v195@@ ) ; break ; case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : @@v42@@ = ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) == Number ; @@v192@@ = get_fpstatus_ptr ( Number ) ; @@v96@@ = fp_decode_rm [ ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ] ; @@v193@@ = tcg_const_i32 ( Number L ) ; v35 = arm_rmode_to_sf ( @@v96@@ ) ; @@v194@@ = tcg_const_i32 ( v35 ) ; gen_helper_set_neon_rmode ( @@v194@@ , @@v194@@ , cpu_env ) ; if ( @@v42@@ ) gen_helper_vfp_tosls ( v125 , v125 , @@v193@@ , @@v192@@ ) ; else gen_helper_vfp_touls ( v125 , v125 , @@v193@@ , @@v192@@ ) ; gen_helper_set_neon_rmode ( @@v194@@ , @@v194@@ , cpu_env ) ; tcg_temp_free_i32 ( @@v194@@ ) ; tcg_temp_free_i32 ( @@v193@@ ) ; tcg_temp_free_ptr ( @@v192@@ ) ; break ; case Number : @@v191@@ = get_fpstatus_ptr ( Number ) ; gen_helper_recpe_u32 ( v125 , v125 , @@v191@@ ) ; tcg_temp_free_ptr ( @@v191@@ ) ; break ; case Number : @@v190@@ = get_fpstatus_ptr ( Number ) ; gen_helper_rsqrte_u32 ( v125 , v125 , @@v190@@ ) ; tcg_temp_free_ptr ( @@v190@@ ) ; break ; case Number : @@v189@@ = get_fpstatus_ptr ( Number ) ; gen_helper_recpe_f32 ( v125 , v125 , @@v189@@ ) ; tcg_temp_free_ptr ( @@v189@@ ) ; break ; case Number : @@v188@@ = get_fpstatus_ptr ( Number ) ; gen_helper_rsqrte_f32 ( v125 , v125 , @@v188@@ ) ; tcg_temp_free_ptr ( @@v188@@ ) ; break ; case Number : @@v187@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_sitos ( v125 , v125 , @@v187@@ ) ; tcg_temp_free_ptr ( @@v187@@ ) ; break ; case Number : @@v186@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_uitos ( v125 , v125 , @@v186@@ ) ; tcg_temp_free_ptr ( @@v186@@ ) ; break ; case Number : @@v185@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_tosizs ( v125 , v125 , @@v185@@ ) ; tcg_temp_free_ptr ( @@v185@@ ) ; break ; case Number : @@v184@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_touizs ( v125 , v125 , @@v184@@ ) ; tcg_temp_free_ptr ( @@v184@@ ) ; break ; default : abort ( ) ; } neon_store_reg ( @@v43@@ , jj , v125 ) ; } return Number L ; } } } else { v79 = ( @@a2@@ >> Number ) & Number ; if ( v79 > Number && ( @@a2@@ & Number ) == Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number && ( ( ( unsigned __int8 ) @@v45@@ | ( unsigned __int8 ) ( @@v44@@ | @@v43@@ ) ) & Number ) != Number ) return Number L ; if ( v79 ) { if ( v79 == Number ) { neon_load_reg64 ( cpu_V0 , @@v44@@ + Number ) ; if ( ( @@a2@@ & Number ) != Number ) neon_load_reg64 ( cpu_V1 , @@v45@@ ) ; } else if ( ( @@a2@@ & Number ) != Number ) { v204 = tcg_temp_new_i64 ( ) ; if ( v79 > Number ) { neon_load_reg64 ( cpu_V0 , @@v44@@ + Number ) ; neon_load_reg64 ( v204 , @@v45@@ ) ; } else { neon_load_reg64 ( cpu_V0 , @@v44@@ ) ; neon_load_reg64 ( v204 , @@v44@@ + Number ) ; } tcg_gen_shri_i64 ( cpu_V0 , cpu_V0 , Number * ( BYTE1 ( @@a2@@ ) & Number ) ) ; tcg_gen_shli_i64 ( cpu_V1 , v204 , Number * ( Number - ( BYTE1 ( @@a2@@ ) & Number ) ) ) ; tcg_gen_or_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; if ( v79 > Number ) { neon_load_reg64 ( cpu_V1 , @@v45@@ + Number ) ; v79 -= Number ; } else { neon_load_reg64 ( cpu_V1 , @@v45@@ ) ; } tcg_gen_shli_i64 ( cpu_V1 , cpu_V1 , Number * ( Number - v79 ) ) ; tcg_gen_shri_i64 ( v204 , v204 , Number * v79 ) ; tcg_gen_or_i64 ( cpu_V1 , cpu_V1 , v204 ) ; tcg_temp_free_i64 ( v204 ) ; } else { neon_load_reg64 ( cpu_V0 , @@v44@@ ) ; tcg_gen_shri_i64 ( cpu_V0 , cpu_V0 , Number * v79 ) ; neon_load_reg64 ( cpu_V1 , @@v45@@ ) ; tcg_gen_shli_i64 ( cpu_V1 , cpu_V1 , Number * ( Number - v79 ) ) ; tcg_gen_or_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; } } else { neon_load_reg64 ( cpu_V0 , @@v44@@ ) ; if ( ( @@a2@@ & Number ) != Number ) neon_load_reg64 ( cpu_V1 , @@v44@@ + Number ) ; } neon_store_reg64 ( cpu_V0 , @@v43@@ ) ; if ( ( @@a2@@ & Number ) != Number ) neon_store_reg64 ( cpu_V1 , @@v43@@ + Number ) ; } return Number L ; } v94 = ( @@a2@@ >> Number ) & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( ! v46 ) return Number L ; switch ( v94 ) { case Number : case Number : case Number : case Number : case Number : goto LABEL_645 ; case Number : case Number : case Number : if ( v46 == Number ) return Number L ; LABEL_645 : if ( @@v86@@ && ( ( ( unsigned __int8 ) @@v44@@ | ( unsigned __int8 ) @@v43@@ ) & Number ) != Number ) return Number L ; v113 = neon_get_scalar ( v46 , @@v45@@ ) ; neon_store_scratch ( Number , v113 ) ; for ( kk = Number ; ; ++ kk ) { v28 = @@v86@@ ? Number : Number ; if ( v28 <= kk ) break ; v114 = neon_load_scratch ( Number ) ; v134 = neon_load_reg ( @@v44@@ , kk ) ; if ( v94 == Number ) { if ( v46 == Number ) gen_helper_neon_qdmulh_s16 ( v114 , cpu_env , v114 , v134 ) ; else gen_helper_neon_qdmulh_s32 ( v114 , cpu_env , v114 , v134 ) ; } else if ( v94 == Number ) { if ( v46 == Number ) gen_helper_neon_qrdmulh_s16 ( v114 , cpu_env , v114 , v134 ) ; else gen_helper_neon_qrdmulh_s32 ( v114 , cpu_env , v114 , v134 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { @@v208@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_muls ( v114 , v114 , v134 , @@v208@@ ) ; tcg_temp_free_ptr ( @@v208@@ ) ; } else if ( v46 == Number ) { tcg_gen_mul_i32 ( v114 , v114 , v134 ) ; } else { gen_helper_neon_mul_u16 ( v114 , v114 , v134 ) ; } tcg_temp_free_i32 ( v134 ) ; if ( ( ( @@a2@@ >> Number ) & Number ) <= Number ) { v135 = neon_load_reg ( @@v43@@ , kk ) ; if ( v94 == Number ) { @@v209@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_subs ( v114 , v135 , v114 , @@v209@@ ) ; tcg_temp_free_ptr ( @@v209@@ ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) > Number ) goto LABEL_673 ; if ( v94 == Number ) { gen_neon_rsb ( v46 , v114 , v135 ) ; } else if ( v94 ) { if ( v94 != Number ) LABEL_673 : abort ( ) ; @@v210@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_adds ( v114 , v114 , v135 , @@v210@@ ) ; tcg_temp_free_ptr ( @@v210@@ ) ; } else { gen_neon_add ( v46 , v114 , v135 ) ; } } tcg_temp_free_i32 ( v135 ) ; } neon_store_reg ( @@v43@@ , kk , v114 ) ; } break ; case Number : case Number : case Number : goto LABEL_683 ; case Number : case Number : case Number : if ( @@v86@@ == Number ) return Number L ; LABEL_683 : if ( ( @@v43@@ & Number ) != Number ) return Number L ; v136 = neon_get_scalar ( v46 , @@v45@@ ) ; v207 = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( v207 , v136 ) ; v156 = neon_load_reg ( @@v44@@ , Number ) ; for ( ll = Number ; ll <= Number ; ++ ll ) { if ( ll ) { v136 = v207 ; gen_neon_mull ( cpu_V0 , v156 , v207 , v46 , @@v86@@ ) ; } else { v115 = neon_load_reg ( @@v44@@ , Number ) ; gen_neon_mull ( cpu_V0 , v115 , v136 , v46 , @@v86@@ ) ; } if ( v94 != Number ) neon_load_reg64 ( cpu_V1 , ll + @@v43@@ ) ; switch ( v94 ) { case Number : goto LABEL_693 ; case Number : case Number : gen_neon_addl_saturate ( cpu_V0 , cpu_V0 , v46 ) ; if ( v94 == Number ) gen_neon_negl ( cpu_V0 , v46 ) ; gen_neon_addl_saturate ( cpu_V0 , cpu_V1 , v46 ) ; break ; case Number : gen_neon_negl ( cpu_V0 , v46 ) ; LABEL_693 : gen_neon_addl ( v46 ) ; break ; case Number : break ; case Number : gen_neon_addl_saturate ( cpu_V0 , cpu_V0 , v46 ) ; break ; default : abort ( ) ; } neon_store_reg64 ( cpu_V0 , ll + @@v43@@ ) ; } return Number L ; case Number : case Number : if ( ! isar_feature_aa32_rdm ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v86@@ && ( ( ( unsigned __int8 ) @@v44@@ | ( unsigned __int8 ) @@v43@@ ) & Number ) != Number ) return Number L ; if ( v94 == Number ) { if ( v46 == Number ) @@v177@@ = gen_helper_neon_qrdmlah_s16 ; else @@v177@@ = gen_helper_neon_qrdmlah_s32 ; } else if ( v46 == Number ) { @@v177@@ = gen_helper_neon_qrdmlsh_s16 ; } else { @@v177@@ = gen_helper_neon_qrdmlsh_s32 ; } v131 = neon_get_scalar ( v46 , @@v45@@ ) ; for ( mm = Number ; ; ++ mm ) { v29 = @@v86@@ ? Number : Number ; if ( v29 <= mm ) break ; v116 = neon_load_reg ( @@v44@@ , mm ) ; v157 = neon_load_reg ( @@v43@@ , mm ) ; @@v177@@ ( v116 , cpu_env , v116 , v131 , v157 ) ; tcg_temp_free_i32 ( v157 ) ; neon_store_reg ( @@v43@@ , mm , v116 ) ; } goto LABEL_468 ; default : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; goto LABEL_722 ; } return Number L ; } @@v97@@ = * ( ( _DWORD * ) & neon_3reg_wide_56205 + Number * v94 ) ; @@v98@@ = * ( ( _DWORD * ) & unk_4E484 + Number * v94 ) ; @@v99@@ = * ( ( _DWORD * ) & unk_4E488 + Number * v94 ) ; @@v100@@ = dword_4E48C [ Number * v94 ] ; if ( ( ( @@v100@@ >> v46 ) & Number ) != Number || ( @@v100@@ & Number ) != Number && @@v86@@ ) return Number L ; if ( @@v98@@ && ( @@v44@@ & Number ) != Number || @@v99@@ && ( @@v45@@ & Number ) != Number || ! @@v99@@ && ( @@v43@@ & Number ) != Number ) return Number L ; if ( v94 == Number && v46 == Number ) { if ( ! isar_feature_aa32_pmull ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v211@@ = tcg_temp_new_i64 ( ) ; @@v212@@ = tcg_temp_new_i64 ( ) ; @@v213@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v211@@ , @@v44@@ ) ; neon_load_reg64 ( @@v212@@ , @@v45@@ ) ; gen_helper_neon_pmull_64_lo ( @@v213@@ , @@v211@@ , @@v212@@ ) ; neon_store_reg64 ( @@v213@@ , @@v43@@ ) ; gen_helper_neon_pmull_64_hi ( @@v213@@ , @@v211@@ , @@v212@@ ) ; neon_store_reg64 ( @@v213@@ , @@v43@@ + Number ) ; tcg_temp_free_i64 ( @@v211@@ ) ; tcg_temp_free_i64 ( @@v212@@ ) ; tcg_temp_free_i64 ( @@v213@@ ) ; return Number L ; } if ( @@v43@@ != @@v45@@ || @@v99@@ ) { if ( @@v43@@ == @@v44@@ && ! @@v98@@ ) { v27 = neon_load_reg ( @@v44@@ , Number ) ; neon_store_scratch ( Number , v27 ) ; } } else { v26 = neon_load_reg ( @@v45@@ , Number ) ; neon_store_scratch ( Number , v26 ) ; } v155 = Number L ; for ( nn = Number ; ; ++ nn ) { if ( nn > Number ) return Number L ; if ( @@v98@@ ) { neon_load_reg64 ( cpu_V0 , nn + @@v44@@ ) ; v111 = Number L ; } else { if ( nn == Number && @@v43@@ == @@v44@@ ) v111 = neon_load_scratch ( Number ) ; else v111 = neon_load_reg ( @@v44@@ , nn ) ; if ( @@v97@@ ) gen_neon_widen ( cpu_V0 , v111 , v46 , @@v86@@ ) ; } if ( @@v99@@ ) { neon_load_reg64 ( cpu_V1 , nn + @@v45@@ ) ; v133 = Number L ; } else { if ( nn == Number && @@v43@@ == @@v45@@ ) v133 = neon_load_scratch ( Number ) ; else v133 = neon_load_reg ( @@v45@@ , nn ) ; if ( @@v97@@ ) gen_neon_widen ( cpu_V1 , v133 , v46 , @@v86@@ ) ; } switch ( v94 ) { case Number : case Number : case Number : gen_neon_addl ( v46 ) ; break ; case Number : case Number : case Number : gen_neon_subl ( v46 ) ; break ; case Number : case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_abdl_s16 ( cpu_V0 , v111 , v133 ) ; break ; case Number : gen_helper_neon_abdl_u16 ( cpu_V0 , v111 , v133 ) ; break ; case Number : gen_helper_neon_abdl_s32 ( cpu_V0 , v111 , v133 ) ; break ; case Number : gen_helper_neon_abdl_u32 ( cpu_V0 , v111 , v133 ) ; break ; case Number : gen_helper_neon_abdl_s64 ( cpu_V0 , v111 , v133 ) ; break ; case Number : gen_helper_neon_abdl_u64 ( cpu_V0 , v111 , v133 ) ; break ; default : abort ( ) ; } tcg_temp_free_i32 ( v133 ) ; tcg_temp_free_i32 ( v111 ) ; break ; case Number : case Number : case Number : case Number : case Number : case Number : gen_neon_mull ( cpu_V0 , v111 , v133 , v46 , @@v86@@ ) ; break ; case Number : gen_helper_neon_mull_p8 ( cpu_V0 , v111 , v133 ) ; tcg_temp_free_i32 ( v133 ) ; tcg_temp_free_i32 ( v111 ) ; break ; default : abort ( ) ; } if ( v94 == Number ) { gen_neon_addl_saturate ( cpu_V0 , cpu_V0 , v46 ) ; neon_store_reg64 ( cpu_V0 , nn + @@v43@@ ) ; continue ; } if ( v94 == Number || ( ( @@a2@@ >> Number ) & Number ) > Number && ( ( @@a2@@ >> Number ) & Number ) <= Number ) break ; if ( v94 != Number && v94 != Number ) goto LABEL_636 ; v112 = tcg_temp_new_i32 ( ) ; if ( @@v86@@ ) { if ( v46 == Number ) { tcg_gen_addi_i64 ( cpu_V0 , cpu_V0 , Number ) ; tcg_gen_extrh_i64_i32 ( v112 , cpu_V0 ) ; } else if ( v46 ) { gen_helper_neon_narrow_round_high_u16 ( v112 , cpu_V0 ) ; } else { gen_helper_neon_narrow_round_high_u8 ( v112 , cpu_V0 ) ; } } else if ( v46 == Number ) { tcg_gen_extrh_i64_i32 ( v112 , cpu_V0 ) ; } else if ( v46 ) { gen_helper_neon_narrow_high_u16 ( v112 , cpu_V0 ) ; } else { gen_helper_neon_narrow_high_u8 ( v112 , cpu_V0 ) ; } if ( nn ) { neon_store_reg ( @@v43@@ , Number , v155 ) ; neon_store_reg ( @@v43@@ , Number , v112 ) ; } else { v155 = v112 ; } LABEL_637 : ; } neon_load_reg64 ( cpu_V1 , nn + @@v43@@ ) ; switch ( v94 ) { case Number : case Number : goto LABEL_615 ; case Number : case Number : gen_neon_addl_saturate ( cpu_V0 , cpu_V0 , v46 ) ; if ( v94 == Number ) gen_neon_negl ( cpu_V0 , v46 ) ; gen_neon_addl_saturate ( cpu_V0 , cpu_V1 , v46 ) ; break ; case Number : gen_neon_negl ( cpu_V0 , v46 ) ; LABEL_615 : gen_neon_addl ( v46 ) ; break ; default : abort ( ) ; } LABEL_636 : neon_store_reg64 ( cpu_V0 , nn + @@v43@@ ) ; goto LABEL_637 ; } if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) != Number && ( @@v43@@ & Number ) != Number ) return Number L ; v93 = ( @@a2@@ >> Number ) & Number ; v78 = ( @@a2@@ >> Number ) & Number | ( @@v86@@ << Number ) | @@a2@@ & Number ; switch ( v93 ) { case Number : case Number : v78 <<= Number ; goto LABEL_530 ; case Number : case Number : v78 <<= Number ; goto LABEL_530 ; case Number : case Number : v78 <<= Number ; goto LABEL_530 ; case Number : case Number : v78 |= v78 << Number ; goto LABEL_530 ; case Number : case Number : v78 = ( v78 << Number ) | ( v78 << Number ) ; goto LABEL_530 ; case Number : v23 = v78 << Number ; LOBYTE ( v23 ) = Number ; v78 = v23 ; goto LABEL_530 ; case Number : v78 = ( v78 << Number ) | Number ; goto LABEL_530 ; case Number : v78 |= ( v78 << Number ) | ( v78 << Number ) | ( v78 << Number ) ; if ( ( @@a2@@ & Number ) != Number ) v78 = ~ v78 ; goto LABEL_530 ; case Number : if ( ( @@a2@@ & Number ) != Number ) return Number L ; if ( ( v78 & Number ) != Number ) v24 = Number ; else v24 = Number ; v78 = ( v78 << Number ) & Number | ( v78 << Number ) & Number | v24 ; LABEL_530 : if ( ( @@a2@@ & Number ) != Number ) v78 = ~ v78 ; @@v101@@ = neon_reg_offset ( @@v43@@ , Number ) ; if ( ( @@a2@@ & Number ) != Number ) v25 = Number ; else v25 = Number ; if ( ( v93 & Number ) != Number && ( ( @@a2@@ >> Number ) & Number ) <= Number ) { if ( ( @@a2@@ & Number ) != Number ) tcg_gen_gvec_andi ( Number L , @@v101@@ , @@v101@@ , v78 , v25 , v25 ) ; else tcg_gen_gvec_ori ( Number L , @@v101@@ , @@v101@@ , v78 , v25 , v25 ) ; } else if ( v93 == Number && ( @@a2@@ & Number ) != Number ) { @@v214@@ = tcg_temp_new_i64 ( ) ; for ( i1 = Number ; i1 <= @@v85@@ ; ++ i1 ) { @@v176@@ = Number L ; for ( @@i2@@ = Number ; @@i2@@ <= Number ; ++ @@i2@@ ) { if ( ( v78 & ( Number << ( Number * i1 + @@i2@@ ) ) ) != Number ) @@v176@@ |= Number L << ( Number * ( unsigned __int8 ) @@i2@@ ) ; } tcg_gen_movi_i64 ( @@v214@@ , @@v176@@ ) ; neon_store_reg64 ( @@v214@@ , i1 + @@v43@@ ) ; } tcg_temp_free_i64 ( @@v214@@ ) ; } else { tcg_gen_gvec_dup32i ( @@v101@@ , v25 , v25 , v78 ) ; } break ; default : goto LABEL_530 ; } return Number L ; } v92 = ( @@a2@@ >> Number ) & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) > Number ) return Number L ; i3 = Number ; } else { for ( i3 = Number ; ( @@a2@@ & ( Number << ( i3 + Number ) ) ) == Number ; -- i3 ) ; } v50 = HIWORD ( @@a2@@ ) & ( ( Number << ( i3 + Number ) ) - Number ) ; if ( ( ( @@a2@@ >> Number ) & Number ) > Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) > Number ) { if ( v92 == Number ) { if ( ( @@a2@@ & Number ) != Number || ( @@v43@@ & Number ) != Number ) return Number L ; v110 = neon_load_reg ( @@v45@@ , Number ) ; v132 = neon_load_reg ( @@v45@@ , Number ) ; for ( i4 = Number ; i4 <= Number ; ++ i4 ) { if ( i4 == Number ) v110 = v132 ; gen_neon_widen ( cpu_V0 , v110 , i3 , @@v86@@ ) ; if ( v50 ) { tcg_gen_shli_i64 ( cpu_V0 , cpu_V0 , v50 ) ; if ( i3 <= Number || ! @@v86@@ ) { if ( i3 ) { if ( i3 == Number ) v77 = Number >> ( Number - ( BYTE2 ( @@a2@@ ) & ( ( Number << ( i3 + Number ) ) - Number ) ) ) ; else v77 = Number >> ( Number - ( BYTE2 ( @@a2@@ ) & ( ( Number << ( i3 + Number ) ) - Number ) ) ) ; } else { v77 = ( Number >> ( Number - v50 ) << Number ) | ( Number >> ( Number - v50 ) ) ; } if ( i3 > Number ) @@v174@@ = v77 ; else @@v174@@ = ( ( unsigned __int64 ) v77 << Number ) | v77 ; tcg_gen_andi_i64 ( cpu_V0 , cpu_V0 , ~ @@v174@@ ) ; } } neon_store_reg64 ( cpu_V0 , i4 + @@v43@@ ) ; } } else { if ( ( ( @@a2@@ >> Number ) & Number ) <= Number ) return Number L ; if ( ( @@a2@@ & Number ) == Number || ( @@a2@@ & Number ) != Number && ( ( ( unsigned __int8 ) @@v45@@ | ( unsigned __int8 ) @@v43@@ ) & Number ) != Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { if ( @@v86@@ ) @@v175@@ = gen_helper_vfp_touls_round_to_zero ; else @@v175@@ = gen_helper_vfp_tosls_round_to_zero ; } else if ( @@v86@@ ) { @@v175@@ = gen_helper_vfp_ultos ; } else { @@v175@@ = gen_helper_vfp_sltos ; } @@v215@@ = get_fpstatus_ptr ( Number ) ; @@v216@@ = tcg_const_i32 ( ( unsigned int ) ( Number - v50 ) ) ; for ( i5 = Number ; ; ++ i5 ) { v22 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v22 <= i5 ) break ; @@v217@@ = neon_load_reg ( @@v45@@ , i5 ) ; @@v175@@ ( @@v217@@ , @@v217@@ , @@v216@@ , @@v215@@ ) ; neon_store_reg ( @@v43@@ , i5 , @@v217@@ ) ; } tcg_temp_free_ptr ( @@v215@@ ) ; tcg_temp_free_i32 ( @@v216@@ ) ; } } else { if ( v92 == Number ) v21 = @@v86@@ == Number ; else v21 = HIBYTE ( @@a2@@ ) & Number ; @@v102@@ = v21 ; if ( ( @@v45@@ & Number ) != Number ) return Number L ; v54 = v50 - ( Number << ( i3 + Number ) ) ; v48 = i3 + Number ; if ( v48 == Number ) { v203 = tcg_const_i64 ( v54 ) ; neon_load_reg64 ( cpu_V0 , @@v45@@ ) ; neon_load_reg64 ( cpu_V1 , @@v45@@ + Number ) ; for ( i6 = Number ; i6 <= Number ; ++ i6 ) { if ( i6 ) @@v173@@ = cpu_V1 ; else @@v173@@ = cpu_V0 ; if ( ( @@a2@@ & Number ) != Number ) { if ( @@v102@@ ) gen_helper_neon_rshl_u64 ( cpu_V0 , @@v173@@ , v203 ) ; else gen_helper_neon_rshl_s64 ( cpu_V0 , @@v173@@ , v203 ) ; } else if ( @@v102@@ ) { gen_helper_neon_shl_u64 ( cpu_V0 , @@v173@@ , v203 ) ; } else { gen_helper_neon_shl_s64 ( cpu_V0 , @@v173@@ , v203 ) ; } v107 = tcg_temp_new_i32 ( ) ; gen_neon_narrow_op ( v92 == Number , @@v86@@ , Number , v107 , cpu_V0 ) ; neon_store_reg ( @@v43@@ , i6 , v107 ) ; } tcg_temp_free_i64 ( v203 ) ; } else { if ( v48 == Number ) v76 = ( ( unsigned __int16 ) v54 << Number ) | ( unsigned __int16 ) v54 ; else v76 = v54 ; v131 = tcg_const_i32 ( v76 ) ; v206 = neon_load_reg ( @@v45@@ + Number , Number ) ; v178 = neon_load_reg ( @@v45@@ + Number , Number ) ; for ( i7 = Number ; i7 <= Number ; ++ i7 ) { if ( i7 ) { v108 = v206 ; gen_neon_shift_narrow ( v48 , v206 , v131 , @@v85@@ , @@v102@@ ) ; } else { v108 = neon_load_reg ( @@v45@@ , Number ) ; gen_neon_shift_narrow ( v48 , v108 , v131 , @@v85@@ , @@v102@@ ) ; } if ( i7 ) { v154 = v178 ; gen_neon_shift_narrow ( v48 , v178 , v131 , @@v85@@ , @@v102@@ ) ; } else { v154 = neon_load_reg ( @@v45@@ , Number ) ; gen_neon_shift_narrow ( v48 , v154 , v131 , @@v85@@ , @@v102@@ ) ; } tcg_gen_concat_i32_i64 ( cpu_V0 , v108 , v154 ) ; tcg_temp_free_i32 ( v108 ) ; tcg_temp_free_i32 ( v154 ) ; v109 = tcg_temp_new_i32 ( ) ; gen_neon_narrow_op ( v92 == Number , @@v86@@ , v48 - Number , v109 , cpu_V0 ) ; neon_store_reg ( @@v43@@ , i7 , v109 ) ; } LABEL_468 : tcg_temp_free_i32 ( v131 ) ; } } return Number L ; } if ( ( @@a2@@ & Number ) != Number && ( ( ( unsigned __int8 ) @@v45@@ | ( unsigned __int8 ) @@v43@@ ) & Number ) != Number ) return Number L ; if ( ! @@v86@@ && ( v92 == Number || v92 == Number ) ) return Number L ; if ( ( ( @@a2@@ >> Number ) & Number ) <= Number ) v50 -= Number << ( i3 + Number ) ; if ( v92 == Number ) { if ( @@v86@@ ) { if ( v50 < Number << i3 ) tcg_gen_gvec_2i ( @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ , v50 , & sli_op [ Number * i3 ] ) ; } else if ( v50 < Number << i3 ) { tcg_gen_gvec_shli ( ( unsigned int ) i3 , @@v88@@ , @@v90@@ , v50 , @@v87@@ , @@v87@@ ) ; } else { tcg_gen_gvec_dup8i ( @@v88@@ , @@v87@@ , @@v87@@ , Number L ) ; } result = Number L ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) > Number ) goto LABEL_382 ; if ( v92 == Number ) { if ( @@v86@@ ) { v53 = - v50 ; if ( v53 < Number << i3 ) tcg_gen_gvec_2i ( @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ , v53 , & sri_op [ Number * i3 ] ) ; result = Number L ; } else { result = Number L ; } } else if ( v92 ) { if ( v92 != Number ) { LABEL_382 : if ( i3 == Number ) { @@v73@@ = @@v85@@ + Number ; } else { if ( ( @@a2@@ & Number ) != Number ) v20 = Number ; else v20 = Number ; @@v73@@ = v20 ; } v75 = dup_const ( ( unsigned int ) i3 , v50 ) ; for ( i8 = Number ; i8 < @@v73@@ ; ++ i8 ) { if ( i3 == Number ) { neon_load_reg64 ( cpu_V0 , i8 + @@v45@@ ) ; tcg_gen_movi_i64 ( cpu_V1 , v75 ) ; if ( v92 == Number ) { if ( @@v86@@ ) gen_helper_neon_qshl_u64 ( cpu_V0 , cpu_env , cpu_V0 , cpu_V1 ) ; else gen_helper_neon_qshl_s64 ( cpu_V0 , cpu_env , cpu_V0 , cpu_V1 ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) <= Number ) { if ( @@v86@@ ) gen_helper_neon_rshl_u64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; else gen_helper_neon_rshl_s64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; } else { gen_helper_neon_qshlu_s64 ( cpu_V0 , cpu_env , cpu_V0 , cpu_V1 ) ; } if ( v92 == Number ) { neon_load_reg64 ( cpu_V1 , i8 + @@v43@@ ) ; tcg_gen_add_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; } neon_store_reg64 ( cpu_V0 , i8 + @@v43@@ ) ; } else { v106 = neon_load_reg ( @@v45@@ , i8 ) ; v129 = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( v129 , v75 ) ; if ( v92 == Number ) { switch ( @@v86@@ | ( Number * i3 ) ) { case Number : gen_helper_neon_qshl_s8 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_qshl_u8 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_qshl_s16 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_qshl_u16 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_qshl_s32 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_qshl_u32 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; default : return Number L ; } } if ( ( ( @@a2@@ >> Number ) & Number ) <= Number ) { switch ( @@v86@@ | ( Number * i3 ) ) { case Number : gen_helper_neon_rshl_s8 ( v106 , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_rshl_u8 ( v106 , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_rshl_s16 ( v106 , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_rshl_u16 ( v106 , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_rshl_s32 ( v106 , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_rshl_u32 ( v106 , v106 , v129 ) ; goto LABEL_429 ; default : return Number L ; } } if ( i3 == Number ) { gen_helper_neon_qshlu_s32 ( v106 , cpu_env , v106 , v129 ) ; } else { if ( i3 > Number ) goto LABEL_420 ; if ( i3 ) { if ( i3 != Number ) LABEL_420 : abort ( ) ; gen_helper_neon_qshlu_s16 ( v106 , cpu_env , v106 , v129 ) ; } else { gen_helper_neon_qshlu_s8 ( v106 , cpu_env , v106 , v129 ) ; } } LABEL_429 : tcg_temp_free_i32 ( v129 ) ; if ( v92 == Number ) { v130 = neon_load_reg ( @@v43@@ , i8 ) ; gen_neon_add ( i3 , v106 , v130 ) ; tcg_temp_free_i32 ( v130 ) ; } neon_store_reg ( @@v43@@ , i8 , v106 ) ; } } return Number L ; } v52 = - v50 ; if ( @@v86@@ ) { if ( v52 < Number << i3 ) tcg_gen_gvec_2i ( @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ , v52 , & usra_op [ Number * i3 ] ) ; } else { v19 = ( Number << i3 ) - Number ; if ( v52 <= v19 ) v19 = v52 ; tcg_gen_gvec_2i ( @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ , v19 , & ssra_op [ Number * i3 ] ) ; } result = Number L ; } else { v51 = - v50 ; if ( @@v86@@ ) { if ( v51 < Number << i3 ) tcg_gen_gvec_shri ( ( unsigned int ) i3 , @@v88@@ , @@v90@@ , v51 , @@v87@@ , @@v87@@ ) ; else tcg_gen_gvec_dup8i ( @@v88@@ , @@v87@@ , @@v87@@ , Number L ) ; } else { v18 = ( Number << i3 ) - Number ; if ( v51 <= v18 ) v18 = v51 ; tcg_gen_gvec_sari ( ( unsigned int ) i3 , @@v88@@ , @@v90@@ , v18 , @@v87@@ , @@v87@@ ) ; } result = Number L ; } } return result ; }\", \"source\": [{\"n\": \"v39\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r104\"}, {\"n\": \"v37\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r112\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r88\"}, {\"n\": \"v217\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s120\"}, {\"n\": \"v216\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s128\"}, {\"n\": \"v215\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s136\"}, {\"n\": \"v214\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s144\"}, {\"n\": \"v213\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s152\"}, {\"n\": \"v212\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s160\"}, {\"n\": \"v211\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s168\"}, {\"n\": \"v210\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s184\"}, {\"n\": \"v209\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s192\"}, {\"n\": \"v208\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s200\"}, {\"n\": \"v202\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s232\"}, {\"n\": \"v201\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s240\"}, {\"n\": \"v200\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s248\"}, {\"n\": \"v199\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s256\"}, {\"n\": \"v198\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s264\"}, {\"n\": \"v197\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s272\"}, {\"n\": \"v196\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s280\"}, {\"n\": \"v195\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s288\"}, {\"n\": \"v194\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s296\"}, {\"n\": \"v193\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s304\"}, {\"n\": \"v192\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s312\"}, {\"n\": \"v191\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s320\"}, {\"n\": \"v190\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s328\"}, {\"n\": \"v189\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s336\"}, {\"n\": \"v188\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s344\"}, {\"n\": \"v187\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s352\"}, {\"n\": \"v186\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s360\"}, {\"n\": \"v185\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s368\"}, {\"n\": \"v184\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s376\"}, {\"n\": \"v225\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v183\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s416\"}, {\"n\": \"v182\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s424\"}, {\"n\": \"v181\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s440\"}, {\"n\": \"v180\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s448\"}, {\"n\": \"v177\", \"t\": {\"T\": 9, \"n\": \"unsigned __int64 (__fastcall *)(__int64 a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5)\"}, \"location\": \"s472\"}, {\"n\": \"v224\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v176\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s480\"}, {\"n\": \"v175\", \"t\": {\"T\": 9, \"n\": \"unsigned __int64 (__fastcall *)(__int64 a1, __int64 a2, __int64 a3, __int64 a4)\"}, \"location\": \"s488\"}, {\"n\": \"v174\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s496\"}, {\"n\": \"v173\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s504\"}, {\"n\": \"v172\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s512\"}, {\"n\": \"v103\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s556\"}, {\"n\": \"v223\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v102\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s560\"}, {\"n\": \"v101\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s568\"}, {\"n\": \"v100\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s576\"}, {\"n\": \"v99\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s580\"}, {\"n\": \"v98\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s584\"}, {\"n\": \"v97\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s588\"}, {\"n\": \"v96\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s592\"}, {\"n\": \"v90\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s604\"}, {\"n\": \"v89\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s608\"}, {\"n\": \"v88\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s612\"}, {\"n\": \"v87\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s616\"}, {\"n\": \"v86\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s620\"}, {\"n\": \"v85\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s624\"}, {\"n\": \"v84\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s628\"}, {\"n\": \"v83\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s632\"}, {\"n\": \"v82\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s636\"}, {\"n\": \"v222\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s64\"}, {\"n\": \"m\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s640\"}, {\"n\": \"i2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s644\"}, {\"n\": \"v74\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s652\"}, {\"n\": \"v73\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s656\"}, {\"n\": \"v45\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s672\"}, {\"n\": \"v44\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s676\"}, {\"n\": \"v43\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s680\"}, {\"n\": \"v42\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s681\"}, {\"n\": \"v221\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s72\"}, {\"n\": \"v220\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s80\"}, {\"n\": \"v219\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s88\"}, {\"n\": \"v218\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s96\"}]}",
"{\"name\": \"disas_neon_insn_3same_ext\", \"code\": \"__int64 __fastcall disas_neon_insn_3same_ext ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 result ; unsigned __int64 ( __fastcall * v3 ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; unsigned __int64 ( __fastcall * v4 ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; unsigned __int64 ( __fastcall * v5 ) ( __int64 , __int64 , __int64 , __int64 ) ; unsigned int @@v6@@ ; unsigned int v7 ; unsigned int v8 ; unsigned int v9 ; char @@v10@@ ; char @@v11@@ ; bool @@v12@@ ; bool @@v13@@ ; int @@v14@@ ; int @@v15@@ ; int @@v16@@ ; unsigned int @@v17@@ ; unsigned int @@v18@@ ; unsigned int @@v19@@ ; unsigned int @@v20@@ ; int @@v21@@ ; int @@v22@@ ; unsigned int @@v23@@ ; unsigned __int64 ( __fastcall * @@v24@@ ) ( __int64 , __int64 , __int64 , __int64 ) ; unsigned __int64 ( __fastcall * @@v25@@ ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; __int64 @@v26@@ ; @@v24@@ = Number L ; @@v25@@ = Number L ; @@v17@@ = Number ; @@v10@@ = Number ; @@v12@@ = ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) != Number ; @@v11@@ = Number ; if ( ( @@a2@@ & Number ) == Number ) { @@v22@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v17@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_vcma ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ! @@v22@@ && ! isar_feature_aa32_fp16_arith ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v22@@ ) v3 = gen_helper_gvec_fcmlas ; else v3 = gen_helper_gvec_fcmlah ; @@v25@@ = v3 ; } else if ( ( @@a2@@ & Number ) == Number ) { @@v21@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v17@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_vcma ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ! @@v21@@ && ! isar_feature_aa32_fp16_arith ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v21@@ ) v4 = gen_helper_gvec_fcadds ; else v4 = gen_helper_gvec_fcaddh ; @@v25@@ = v4 ; } else if ( ( @@a2@@ & Number ) == Number ) { @@v13@@ = ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) != Number ; if ( ! isar_feature_aa32_dp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v13@@ ) v5 = gen_helper_gvec_udot_b ; else v5 = gen_helper_gvec_sdot_b ; @@v24@@ = v5 ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v20@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_fhm ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v10@@ = Number ; @@v17@@ = @@v20@@ ; @@v25@@ = gen_helper_gvec_fmlal_a32 ; @@v11@@ = Number ; } if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v14@@ = ( ( unsigned __int16 ) @@a2@@ >> Number ) | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v14@@ = ( unsigned __int16 ) @@a2@@ >> Number ; } if ( ( ( unsigned __int8 ) @@v14@@ & @@v12@@ ) != Number ) return Number L ; if ( @@v12@@ || @@v10@@ != Number ) { if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v15@@ = HIWORD ( @@a2@@ ) & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v15@@ = HIWORD ( @@a2@@ ) & Number ; } if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v16@@ = @@a2@@ & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v16@@ = @@a2@@ & Number ; } if ( ( @@v12@@ & ( unsigned __int8 ) ( @@v16@@ | @@v15@@ ) & ( ( unsigned __int8 ) @@v10@@ ^ Number ) ) != Number ) return Number L ; @@v18@@ = vfp_reg_offset ( Number , @@v15@@ ) ; @@v19@@ = vfp_reg_offset ( Number , @@v16@@ ) ; } else { @@v18@@ = vfp_reg_offset ( Number , ( @@a2@@ >> Number ) & Number | ( @@a2@@ >> Number ) & Number ) ; @@v19@@ = vfp_reg_offset ( Number , ( Number * ( _BYTE ) @@a2@@ ) & Number | ( @@a2@@ >> Number ) & Number ) ; } if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { @@v6@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; v7 = syn_simd_access_trap ( Number , Number , Number ) ; gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , v7 , @@v6@@ ) ; result = Number L ; } else if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) { result = Number L ; } else { @@v23@@ = Number * ( @@v12@@ + Number ) ; if ( @@v25@@ ) { if ( @@v11@@ ) @@v26@@ = cpu_env ; else @@v26@@ = get_fpstatus_ptr ( Number ) ; v8 = vfp_reg_offset ( Number , @@v14@@ ) ; tcg_gen_gvec_3_ptr ( v8 , @@v18@@ , @@v19@@ , @@v26@@ , @@v23@@ , @@v23@@ , @@v17@@ , @@v25@@ ) ; if ( @@v11@@ != Number ) tcg_temp_free_ptr ( @@v26@@ ) ; } else { v9 = vfp_reg_offset ( Number , @@v14@@ ) ; tcg_gen_gvec_3_ool ( v9 , @@v18@@ , @@v19@@ , @@v23@@ , @@v23@@ , @@v17@@ , @@v24@@ ) ; } result = Number L ; } return result ; }\", \"source\": [{\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v24\", \"t\": {\"T\": 9, \"n\": \"unsigned __int64 (__fastcall *)(__int64 a1, __int64 a2, __int64 a3, __int64 a4)\"}, \"location\": \"s104\"}, {\"n\": \"v23\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s108\"}, {\"n\": \"v22\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s112\"}, {\"n\": \"v21\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s116\"}, {\"n\": \"v20\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s120\"}, {\"n\": \"v19\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s124\"}, {\"n\": \"v18\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s128\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s132\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s136\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s140\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s144\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s145\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s146\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s147\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s148\"}, {\"n\": \"v26\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s88\"}, {\"n\": \"v25\", \"t\": {\"T\": 9, \"n\": \"unsigned __int64 (__fastcall *)(__int64 a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5)\"}, \"location\": \"s96\"}]}",
"{\"name\": \"disas_neon_insn_2reg_scalar_ext\", \"code\": \"__int64 __fastcall disas_neon_insn_2reg_scalar_ext ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 result ; unsigned __int64 ( __fastcall * v3 ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; unsigned __int64 ( __fastcall * v4 ) ( __int64 , __int64 , __int64 , __int64 ) ; unsigned int @@v5@@ ; unsigned int v6 ; unsigned int v7 ; unsigned int v8 ; char @@v9@@ ; char @@v10@@ ; bool @@v11@@ ; int @@v12@@ ; int @@v13@@ ; unsigned int @@v14@@ ; unsigned int @@v15@@ ; unsigned int @@v16@@ ; unsigned int @@v17@@ ; int @@v18@@ ; int @@v19@@ ; int @@v20@@ ; unsigned int @@v21@@ ; int @@v22@@ ; int @@v23@@ ; int @@v24@@ ; int @@v25@@ ; int @@v26@@ ; unsigned int @@v27@@ ; unsigned __int64 ( __fastcall * @@v28@@ ) ( __int64 , __int64 , __int64 , __int64 ) ; unsigned __int64 ( __fastcall * @@v29@@ ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; __int64 @@v30@@ ; @@v28@@ = Number L ; @@v29@@ = Number L ; @@v9@@ = Number ; @@v11@@ = ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) != Number ; @@v10@@ = Number ; if ( ( @@a2@@ & Number ) == Number ) { @@v25@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v26@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_vcma ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v26@@ ) { if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v14@@ = @@a2@@ & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v14@@ = @@a2@@ & Number ; } @@v18@@ = Number ; } else { if ( ! isar_feature_aa32_fp16_arith ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v14@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v18@@ = extract32 ( @@a2@@ , Number , Number ) ; } @@v15@@ = @@v25@@ | ( Number * @@v18@@ ) ; if ( @@v26@@ ) v3 = gen_helper_gvec_fcmlas_idx ; else v3 = gen_helper_gvec_fcmlah_idx ; @@v29@@ = v3 ; } else if ( ( @@a2@@ & Number ) == Number ) { @@v24@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_dp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v24@@ ) v4 = gen_helper_gvec_udot_idx_b ; else v4 = gen_helper_gvec_sdot_idx_b ; @@v28@@ = v4 ; @@v15@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v14@@ = extract32 ( @@a2@@ , Number , Number ) ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v20@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v21@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v22@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v23@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_fhm ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v11@@ ) { @@v14@@ = @@v21@@ ; @@v19@@ = Number * @@v23@@ + @@v22@@ ; } else { @@v14@@ = Number * @@v21@@ + @@v23@@ ; @@v19@@ = @@v22@@ ; } @@v9@@ = Number ; @@v15@@ = @@v20@@ | ( Number * @@v19@@ ) ; @@v29@@ = gen_helper_gvec_fmlal_idx_a32 ; @@v10@@ = Number ; } if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v12@@ = ( ( unsigned __int16 ) @@a2@@ >> Number ) | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v12@@ = ( unsigned __int16 ) @@a2@@ >> Number ; } if ( ( ( unsigned __int8 ) @@v12@@ & @@v11@@ ) != Number ) return Number L ; if ( @@v11@@ || @@v9@@ != Number ) { if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v13@@ = HIWORD ( @@a2@@ ) & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v13@@ = HIWORD ( @@a2@@ ) & Number ; } if ( ( ( unsigned __int8 ) @@v13@@ & @@v11@@ & ( ( unsigned __int8 ) @@v9@@ ^ Number ) ) != Number ) return Number L ; @@v16@@ = vfp_reg_offset ( Number , @@v13@@ ) ; @@v17@@ = vfp_reg_offset ( Number , @@v14@@ ) ; } else { @@v16@@ = vfp_reg_offset ( Number , ( @@a2@@ >> Number ) & Number | ( @@a2@@ >> Number ) & Number ) ; @@v17@@ = vfp_reg_offset ( Number , @@v14@@ ) ; } if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { @@v5@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; v6 = syn_simd_access_trap ( Number , Number , Number ) ; gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , v6 , @@v5@@ ) ; result = Number L ; } else if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) { result = Number L ; } else { @@v27@@ = Number * ( @@v11@@ + Number ) ; if ( @@v29@@ ) { if ( @@v10@@ ) @@v30@@ = cpu_env ; else @@v30@@ = get_fpstatus_ptr ( Number ) ; v7 = vfp_reg_offset ( Number , @@v12@@ ) ; tcg_gen_gvec_3_ptr ( v7 , @@v16@@ , @@v17@@ , @@v30@@ , @@v27@@ , @@v27@@ , @@v15@@ , @@v29@@ ) ; if ( @@v10@@ != Number ) tcg_temp_free_ptr ( @@v30@@ ) ; } else { v8 = vfp_reg_offset ( Number , @@v12@@ ) ; tcg_gen_gvec_3_ool ( v8 , @@v16@@ , @@v17@@ , @@v27@@ , @@v27@@ , @@v15@@ , @@v28@@ ) ; } result = Number L ; } return result ; }\", \"source\": [{\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v25\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v24\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s104\"}, {\"n\": \"v23\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s108\"}, {\"n\": \"v22\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s112\"}, {\"n\": \"v21\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s116\"}, {\"n\": \"v20\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s120\"}, {\"n\": \"v19\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s124\"}, {\"n\": \"v18\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s128\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s132\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s136\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s140\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s144\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s148\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s152\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s153\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s154\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s155\"}, {\"n\": \"v30\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s72\"}, {\"n\": \"v29\", \"t\": {\"T\": 9, \"n\": \"unsigned __int64 (__fastcall *)(__int64 a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5)\"}, \"location\": \"s80\"}, {\"n\": \"v28\", \"t\": {\"T\": 9, \"n\": \"unsigned __int64 (__fastcall *)(__int64 a1, __int64 a2, __int64 a3, __int64 a4)\"}, \"location\": \"s88\"}, {\"n\": \"v27\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s92\"}, {\"n\": \"v26\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s96\"}]}",
"{\"name\": \"disas_coproc_insn\", \"code\": \"__int64 __fastcall disas_coproc_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 result ; unsigned int v4 ; bool v5 ; const char * v6 ; const char * v7 ; const char * v8 ; const char * v9 ; char @@v10@@ ; unsigned int @@v11@@ ; unsigned int @@v12@@ ; unsigned int @@v13@@ ; int @@v14@@ ; unsigned int @@v15@@ ; unsigned int @@v16@@ ; int @@v17@@ ; unsigned int @@v18@@ ; int @@v19@@ ; __int64 @@v20@@ ; __int64 @@v21@@ ; __int64 @@v22@@ ; __int64 @@v23@@ ; __int64 @@v24@@ ; __int64 @@v25@@ ; __int64 @@v26@@ ; __int64 @@v27@@ ; __int64 @@v28@@ ; __int64 @@v29@@ ; __int64 @@v30@@ ; __int64 @@v31@@ ; __int64 @@v32@@ ; __int64 @@v33@@ ; __int64 @@v34@@ ; __int64 v35 ; __int64 v36 ; __int64 @@v37@@ ; @@v16@@ = ( @@a2@@ >> Number ) & Number ; if ( arm_dc_feature ( @@a1@@ , Number ) && ( ( @@a2@@ >> Number ) & Number ) <= Number ) { if ( ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , @@v16@@ , Number ) ) { if ( arm_dc_feature ( @@a1@@ , Number ) ) { result = disas_iwmmxt_insn ( @@a1@@ , @@a2@@ ) ; } else if ( arm_dc_feature ( @@a1@@ , Number ) ) { result = disas_dsp_insn ( @@a1@@ , @@a2@@ ) ; } else { result = Number L ; } } else { result = Number L ; } } else { if ( ( @@a2@@ & Number ) != Number && ( @@a2@@ & Number ) == Number ) return Number L ; @@v17@@ = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { @@v11@@ = HIWORD ( @@a2@@ ) & Number ; @@v12@@ = ( @@a2@@ >> Number ) & Number ; @@v13@@ = ( unsigned __int8 ) @@a2@@ >> Number ; @@v14@@ = Number ; } else { @@v11@@ = Number ; @@v12@@ = ( unsigned __int8 ) @@a2@@ >> Number ; @@v13@@ = Number ; @@v14@@ = HIWORD ( @@a2@@ ) & Number ; } @@v18@@ = ( @@a2@@ >> Number ) & Number ; @@v19@@ = ( unsigned __int16 ) @@a2@@ >> Number ; @@v22@@ = get_arm_cp_reginfo ( * ( _QWORD * ) ( @@a1@@ + Number ) , @@v13@@ | ( @@v17@@ << Number ) | ( @@v11@@ << Number ) | ( ( ( @@a2@@ & Number ) == Number ) << Number ) | ( @@v16@@ << Number ) | ( * ( unsigned __int8 * ) ( @@a1@@ + Number ) << Number ) | ( Number * @@v12@@ ) ) ; if ( @@v22@@ ) { if ( ! cp_access_ok ( * ( _DWORD * ) ( @@a1@@ + Number ) , @@v22@@ , ( @@a2@@ & Number ) != Number ) ) return Number L ; if ( * ( _QWORD * ) ( @@v22@@ + Number ) || arm_dc_feature ( @@a1@@ , Number ) && ( ( @@a2@@ >> Number ) & Number ) <= Number ) { if ( @@v16@@ == Number ) { if ( ( @@a2@@ & Number ) != Number ) @@v15@@ = syn_cp14_rt_trap ( Number , Number , @@v12@@ , @@v13@@ , @@v11@@ , @@v17@@ , @@v19@@ , @@v18@@ , Number ) ; else @@v15@@ = syn_cp14_rrt_trap ( Number , Number , @@v12@@ , @@v17@@ , @@v19@@ , @@v14@@ , @@v18@@ , Number ) ; } else if ( @@v16@@ == Number ) { if ( ( @@a2@@ & Number ) != Number ) @@v15@@ = syn_cp15_rt_trap ( Number , Number , @@v12@@ , @@v13@@ , @@v11@@ , @@v17@@ , @@v19@@ , @@v18@@ , Number ) ; else @@v15@@ = syn_cp15_rrt_trap ( Number , Number , @@v12@@ , @@v17@@ , @@v19@@ , @@v14@@ , @@v18@@ , Number ) ; } else { if ( arm_dc_feature ( @@a1@@ , Number ) ) _assert_fail ( String , String , Number , String ) ; @@v15@@ = syn_uncategorized ( ) ; } gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; @@v23@@ = tcg_const_i64 ( @@v22@@ ) ; @@v24@@ = tcg_const_i32 ( @@v15@@ ) ; @@v25@@ = tcg_const_i32 ( @@v18@@ ) ; gen_helper_access_check_cp_reg ( cpu_env , @@v23@@ , @@v24@@ , @@v25@@ ) ; tcg_temp_free_ptr ( @@v23@@ ) ; tcg_temp_free_i32 ( @@v24@@ ) ; tcg_temp_free_i32 ( @@v25@@ ) ; } else if ( ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ) { gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; } v4 = * ( _DWORD * ) ( @@v22@@ + Number ) & Number ; if ( v4 == Number ) return Number L ; if ( v4 == Number ) { if ( @@v18@@ ) { result = Number L ; } else { gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; result = Number L ; } } else { if ( ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number && ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ) gen_io_start ( ) ; if ( @@v18@@ ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ) { @@v21@@ = tcg_const_i32 ( ( unsigned int ) * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } else if ( * ( _QWORD * ) ( @@v22@@ + Number ) ) { @@v21@@ = tcg_temp_new_i32 ( ) ; @@v33@@ = tcg_const_i64 ( @@v22@@ ) ; gen_helper_get_cp_reg ( @@v21@@ , cpu_env , @@v33@@ ) ; tcg_temp_free_ptr ( @@v33@@ ) ; } else { @@v21@@ = load_cpu_offset ( * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } if ( @@v19@@ == Number ) { gen_set_cpsr ( @@v21@@ , Number ) ; tcg_temp_free_i32 ( @@v21@@ ) ; } else { store_reg ( @@a1@@ , @@v19@@ , @@v21@@ ) ; } } else { if ( ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ) { @@v20@@ = tcg_const_i64 ( * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } else if ( * ( _QWORD * ) ( @@v22@@ + Number ) ) { @@v20@@ = tcg_temp_new_i64 ( ) ; @@v34@@ = tcg_const_i64 ( @@v22@@ ) ; gen_helper_get_cp_reg64 ( @@v20@@ , cpu_env , @@v34@@ ) ; tcg_temp_free_ptr ( @@v34@@ ) ; } else { @@v20@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ld_i64 ( @@v20@@ , cpu_env , * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } v35 = tcg_temp_new_i32 ( ) ; tcg_gen_extrl_i64_i32 ( v35 , @@v20@@ ) ; store_reg ( @@a1@@ , @@v19@@ , v35 ) ; v36 = tcg_temp_new_i32 ( ) ; tcg_gen_extrh_i64_i32 ( v36 , @@v20@@ ) ; tcg_temp_free_i64 ( @@v20@@ ) ; store_reg ( @@a1@@ , @@v14@@ , v36 ) ; } } else { if ( ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { if ( * ( _QWORD * ) ( @@v22@@ + Number ) ) { @@v27@@ = load_reg ( @@a1@@ , @@v19@@ ) ; @@v28@@ = tcg_const_i64 ( @@v22@@ ) ; gen_helper_set_cp_reg ( cpu_env , @@v28@@ , @@v27@@ ) ; tcg_temp_free_ptr ( @@v28@@ ) ; tcg_temp_free_i32 ( @@v27@@ ) ; } else { @@v26@@ = load_reg ( @@a1@@ , @@v19@@ ) ; store_cpu_offset ( @@v26@@ , * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } } else { @@v29@@ = tcg_temp_new_i64 ( ) ; @@v30@@ = load_reg ( @@a1@@ , @@v19@@ ) ; @@v31@@ = load_reg ( @@a1@@ , @@v14@@ ) ; tcg_gen_concat_i32_i64 ( @@v29@@ , @@v30@@ , @@v31@@ ) ; tcg_temp_free_i32 ( @@v30@@ ) ; tcg_temp_free_i32 ( @@v31@@ ) ; if ( * ( _QWORD * ) ( @@v22@@ + Number ) ) { @@v32@@ = tcg_const_i64 ( @@v22@@ ) ; gen_helper_set_cp_reg64 ( cpu_env , @@v32@@ , @@v29@@ ) ; tcg_temp_free_ptr ( @@v32@@ ) ; } else { tcg_gen_st_i64 ( @@v29@@ , cpu_env , * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } tcg_temp_free_i64 ( @@v29@@ ) ; } } v5 = ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number && ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ; @@v10@@ = v5 ; if ( ! @@v18@@ && ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) == Number ) { @@v37@@ = tcg_const_i32 ( * ( unsigned int * ) ( @@a1@@ + Number ) ) ; if ( arm_dc_feature ( @@a1@@ , Number ) ) gen_helper_rebuild_hflags_m32 ( cpu_env , @@v37@@ ) ; else gen_helper_rebuild_hflags_a32 ( cpu_env , @@v37@@ ) ; tcg_temp_free_i32 ( @@v37@@ ) ; @@v10@@ = Number ; } if ( @@v10@@ ) gen_lookup_tb ( @@a1@@ ) ; result = Number L ; } } else { if ( ( @@a2@@ & Number ) != Number ) { if ( qemu_loglevel_mask ( Number ) ) { if ( * ( _BYTE * ) ( @@a1@@ + Number ) ) v8 = String ; else v8 = String ; if ( @@v18@@ ) v9 = String ; else v9 = String ; qemu_log ( String , v9 , @@v16@@ , @@v12@@ , @@v11@@ , @@a2@@ & Number , @@v13@@ , v8 ) ; } } else if ( qemu_loglevel_mask ( Number ) ) { if ( * ( _BYTE * ) ( @@a1@@ + Number ) ) v6 = String ; else v6 = String ; if ( @@v18@@ ) v7 = String ; else v7 = String ; qemu_log ( String , v7 , @@v16@@ , @@v12@@ , @@a2@@ & Number , v6 ) ; } result = Number L ; } } return result ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v24\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s104\"}, {\"n\": \"v23\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s112\"}, {\"n\": \"v22\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s120\"}, {\"n\": \"v21\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s128\"}, {\"n\": \"v20\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s136\"}, {\"n\": \"v19\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s140\"}, {\"n\": \"v18\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s144\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s148\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s156\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s160\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s164\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s168\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s172\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s176\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s177\"}, {\"n\": \"v34\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v33\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v32\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v31\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v30\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v29\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s64\"}, {\"n\": \"v28\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s72\"}, {\"n\": \"v37\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v27\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s80\"}, {\"n\": \"v26\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s88\"}, {\"n\": \"v25\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s96\"}]}",
"{\"name\": \"arm_skip_unless\", \"code\": \"unsigned __int64 __fastcall arm_skip_unless ( __int64 @@a1@@ , int @@a2@@ ) { arm_gen_condlabel ( @@a1@@ ) ; return arm_gen_test_cc ( @@a2@@ ^ Number , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"disas_a32\", \"code\": \"_BOOL8 __fastcall disas_a32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; _BOOL8 result ; unsigned int v4 ; int v5 ; int v6 ; int v7 ; int v8 ; unsigned int v9 ; unsigned int v10 ; int v11 ; unsigned int v12 ; unsigned int v13 ; int v14 ; int v15 ; unsigned int v16 ; unsigned int v17 ; int v18 ; unsigned int v19 ; unsigned int v20 ; unsigned int v21 ; unsigned int v22 ; unsigned int v23 ; unsigned int v24 ; int v25 ; unsigned int v26 ; unsigned int v27 ; int v28 ; unsigned int v29 ; unsigned int v30 ; unsigned int v31 ; int v32 ; unsigned int v33 ; unsigned int v34 ; int v35 ; unsigned int v36 ; unsigned int v37 ; unsigned int v38 ; unsigned int v39 ; unsigned int v40 ; int @@v41@@ ; int @@v42@@ ; unsigned __int64 @@v43@@ ; @@v43@@ = __readfsqword ( Number ) ; switch ( ( @@a2@@ >> Number ) & Number ) { case Number : v2 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { v12 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { v20 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_a32_extract_ldst_ri8_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_LDRSH_ri ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v20 == Number ) { disas_a32_extract_ldst_ri8_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_LDRSB_ri ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v20 <= Number ) { if ( v20 == Number ) { disas_a32_extract_ldst_ri8_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_LDRH_ri ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v20 <= Number ) { if ( v20 == Number ) { disas_a32_extract_ldrex ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; v22 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_LDREXH ( @@a1@@ , & @@v41@@ ) != Number ; if ( v22 == Number ) return ( unsigned __int8 ) trans_LDAEXH ( @@a1@@ , & @@v41@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_LDAH ( @@a1@@ , & @@v41@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_LDREXB ( @@a1@@ , & @@v41@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_LDAB ( @@a1@@ , & @@v41@@ ) != Number ; if ( v22 == Number ) return ( unsigned __int8 ) trans_LDAEXB ( @@a1@@ , & @@v41@@ ) != Number ; } } } return Number L ; } if ( v20 <= Number ) { if ( v20 == Number ) { disas_a32_extract_ldst_ri8_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STRD_ri_a32 ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v20 <= Number ) { if ( v20 == Number ) { disas_a32_extract_ldst_ri8_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_LDRD_ri_a32 ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v20 <= Number ) { if ( ! v20 ) { v21 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_a32_extract_strex ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STREXH ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v21 == Number ) { disas_a32_extract_strex ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STLEXH ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v21 <= Number ) { if ( v21 == Number ) { disas_a32_extract_stl ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( unsigned __int16 ) @@a2@@ >> Number == Number ) result = ( unsigned __int8 ) trans_STLH ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; return result ; } if ( v21 <= Number ) { if ( v21 == Number ) { disas_a32_extract_strex ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STREXB ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v21 <= Number ) { if ( v21 == Number ) { disas_a32_extract_strex ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STLEXB ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v21 <= Number ) { if ( ! v21 ) { disas_a32_extract_swp ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SWPB ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v21 == Number ) { disas_a32_extract_stl ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( unsigned __int16 ) @@a2@@ >> Number == Number ) result = ( unsigned __int8 ) trans_STLB ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; return result ; } } } } } return Number L ; } if ( v20 == Number ) { disas_a32_extract_ldst_ri8_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STRH_ri ( @@a1@@ , & @@v41@@ ) != Number ; } } } } } } return Number L ; } if ( v12 != Number ) { if ( v12 <= Number ) { if ( ! v12 ) { v13 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v13 == Number ) { disas_a32_extract_s_rrr_shr ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_ORR_rrrr ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v13 <= Number ) { if ( ! v13 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_S_xrr_shr ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( unsigned __int16 ) @@a2@@ >> Number ) result = Number L ; else result = ( unsigned __int8 ) trans_TST_xrrr ( @@a1@@ , & @@v41@@ ) != Number ; } else { v14 = ( @@a2@@ >> Number ) & Number ; if ( v14 == Number ) { disas_a32_extract_rndm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_QADD ( @@a1@@ , & @@v41@@ ) != Number ; } else if ( v14 == Number ) { disas_a32_extract_i16 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_HLT ( @@a1@@ , & @@v41@@ ) != Number ; } else { result = Number L ; } } return result ; } if ( v13 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_S_xrr_shr ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( unsigned __int16 ) @@a2@@ >> Number ) result = Number L ; else result = ( unsigned __int8 ) trans_TEQ_xrrr ( @@a1@@ , & @@v41@@ ) != Number ; } else { v15 = ( @@a2@@ >> Number ) & Number ; if ( v15 == Number ) { disas_a32_extract_i16 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_BKPT ( @@a1@@ , & @@v41@@ ) != Number ; } else if ( v15 == Number ) { disas_a32_extract_rndm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_QSUB ( @@a1@@ , & @@v41@@ ) != Number ; } else if ( v15 ) { disas_a32_extract_rm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_BLX_r ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else { disas_a32_extract_rm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_BX ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } } return result ; } } return Number L ; } disas_a32_extract_s_rxr_shr ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_MOV_rxrr ( @@a1@@ , & @@v41@@ ) != Number ; return result ; } if ( v12 == Number ) { v16 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v16 <= Number ) { if ( v16 == Number ) { disas_a32_extract_ldrex ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_LDAEX ( @@a1@@ , & @@v41@@ ) != Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_LDAEXD_a32 ( @@a1@@ , & @@v41@@ ) != Number ; return Number L ; } if ( v16 <= Number ) { if ( v16 == Number ) { disas_a32_extract_ldrex ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDA ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; return result ; } if ( v16 <= Number ) { if ( v16 == Number ) { disas_a32_extract_ldst_rr_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_LDRSH_rr ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v16 <= Number ) { if ( v16 == Number ) { disas_a32_extract_ldst_rr_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_LDRSB_rr ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v16 <= Number ) { if ( v16 == Number ) { disas_a32_extract_ldst_rr_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_LDRH_rr ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v16 <= Number ) { if ( v16 == Number ) { disas_a32_extract_strex ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_STREX ( @@a1@@ , & @@v41@@ ) != Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_STREXD_a32 ( @@a1@@ , & @@v41@@ ) != Number ; return Number L ; } if ( v16 <= Number ) { if ( v16 == Number ) { disas_a32_extract_strex ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_STLEX ( @@a1@@ , & @@v41@@ ) != Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_STLEXD_a32 ( @@a1@@ , & @@v41@@ ) != Number ; return Number L ; } if ( v16 <= Number ) { if ( v16 == Number ) { disas_a32_extract_stl ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_STL ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; return result ; } if ( v16 <= Number ) { if ( v16 == Number ) { disas_a32_extract_ldst_rr_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STRD_rr ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v16 <= Number ) { if ( v16 == Number ) { disas_a32_extract_ldst_rr_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_LDRD_rr ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v16 <= Number ) { if ( ! v16 ) { disas_a32_extract_swp ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_SWP ( @@a1@@ , & @@v41@@ ) != Number ; return result ; } if ( v16 == Number ) { disas_a32_extract_ldst_rr_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STRH_rr ( @@a1@@ , & @@v41@@ ) != Number ; } } } } } } } } } } } } return Number L ; } disas_a32_extract_ldrex ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_LDREX ( @@a1@@ , & @@v41@@ ) != Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_LDREXD_a32 ( @@a1@@ , & @@v41@@ ) != Number ; return Number L ; } } return Number L ; } v17 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_a32_extract_s_rxr_shr ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_MVN_rxrr ( @@a1@@ , & @@v41@@ ) != Number ; } else { if ( v17 == Number ) { disas_a32_extract_s_rrr_shr ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_BIC_rrrr ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v17 > Number ) return Number L ; if ( ! v17 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_S_xrr_shr ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( unsigned __int16 ) @@a2@@ >> Number ) result = Number L ; else result = ( unsigned __int8 ) trans_CMP_xrrr ( @@a1@@ , & @@v41@@ ) != Number ; } else { v18 = ( @@a2@@ >> Number ) & Number ; if ( v18 == Number ) { disas_a32_extract_rndm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_QDADD ( @@a1@@ , & @@v41@@ ) != Number ; } else if ( v18 == Number ) { disas_a32_extract_i16 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_HVC ( @@a1@@ , & @@v41@@ ) != Number ; } else { result = Number L ; } } return result ; } if ( v17 != Number ) return Number L ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_S_xrr_shr ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( unsigned __int16 ) @@a2@@ >> Number ) result = Number L ; else result = ( unsigned __int8 ) trans_CMN_xrrr ( @@a1@@ , & @@v41@@ ) != Number ; } else { v19 = @@a2@@ & Number ; if ( v19 == Number ) { disas_a32_extract_rdm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( HIWORD ( @@a2@@ ) & Number ) == Number ) result = ( unsigned __int8 ) trans_CLZ ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else { if ( v19 > Number ) goto LABEL_355 ; if ( v19 == Number ) { disas_a32_extract_rndm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_QDSUB ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v19 == Number ) { disas_a32_extract_disas_a32_Fmt_24 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) ( @@a2@@ >> Number ) ) result = Number L ; else result = ( unsigned __int8 ) trans_SMC ( @@a1@@ , & @@v41@@ ) != Number ; } else { LABEL_355 : result = Number L ; } } } } } else { if ( v2 == Number ) { v9 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_a32_extract_s_rxr_shi ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_MOV_rxri ( @@a1@@ , & @@v41@@ ) != Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_MVN_rxri ( @@a1@@ , & @@v41@@ ) != Number ; return Number L ; } if ( v9 == Number ) { disas_a32_extract_s_rrr_shi ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_BIC_rrri ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_ORR_rrri ( @@a1@@ , & @@v41@@ ) != Number ; return result ; } if ( v9 <= Number ) { if ( ! v9 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_S_xrr_shi ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_CMP_xrri ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else { result = ( unsigned __int8 ) trans_TST_xrri ( @@a1@@ , & @@v41@@ ) != Number ; } } else { switch ( ( unsigned __int8 ) @@a2@@ >> Number ) { case Number : if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_a32_extract_disas_a32_Fmt_20 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_MRS_bank ( @@a1@@ , & @@v41@@ ) != Number ; } else { result = Number L ; } } else { disas_a32_extract_disas_a32_Fmt_22 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_MRS_reg ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } break ; case Number : disas_a32_extract_rndm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; v10 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { result = ( unsigned __int8 ) trans_CRC32CW ( @@a1@@ , & @@v41@@ ) != Number ; } else { if ( v10 <= Number ) { if ( v10 == Number ) return ( unsigned __int8 ) trans_CRC32W ( @@a1@@ , & @@v41@@ ) != Number ; if ( v10 <= Number ) { if ( ! v10 ) return ( unsigned __int8 ) trans_CRC32B ( @@a1@@ , & @@v41@@ ) != Number ; if ( v10 == Number ) return ( unsigned __int8 ) trans_CRC32CB ( @@a1@@ , & @@v41@@ ) != Number ; } } result = Number L ; } break ; case Number : disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_SMLALBB ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_SMLABB ( @@a1@@ , & @@v41@@ ) != Number ; break ; case Number : disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_SMLALTB ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_SMLATB ( @@a1@@ , & @@v41@@ ) != Number ; break ; case Number : disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_SMLALBT ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_SMLABT ( @@a1@@ , & @@v41@@ ) != Number ; break ; case Number : disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_SMLALTT ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_SMLATT ( @@a1@@ , & @@v41@@ ) != Number ; break ; default : result = Number L ; break ; } } return result ; } if ( v9 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_S_xrr_shi ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_CMN_xrri ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else { result = ( unsigned __int8 ) trans_TEQ_xrri ( @@a1@@ , & @@v41@@ ) != Number ; } } else { switch ( ( unsigned __int8 ) @@a2@@ >> Number ) { case Number : v11 = ( unsigned __int16 ) @@a2@@ >> Number ; if ( v11 == Number ) { disas_a32_extract_disas_a32_Fmt_23 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_MSR_reg ( @@a1@@ , & @@v41@@ ) != Number ; } else if ( v11 == Number ) { disas_a32_extract_disas_a32_Fmt_21 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_MSR_bank ( @@a1@@ , & @@v41@@ ) != Number ; } else { result = Number L ; } break ; case Number : disas_a32_extract_rm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_BXJ ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; break ; case Number : disas_a32_extract_rndm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_CRC32CH ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else { result = ( unsigned __int8 ) trans_CRC32H ( @@a1@@ , & @@v41@@ ) != Number ; } break ; case Number : disas_a32_extract_disas_a32_Fmt_16 ( ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_ERET ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; break ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_rd0mn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( unsigned __int16 ) @@a2@@ >> Number ) result = Number L ; else result = ( unsigned __int8 ) trans_SMULBB ( @@a1@@ , & @@v41@@ ) != Number ; } else { disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_SMLAWB ( @@a1@@ , & @@v41@@ ) != Number ; } break ; case Number : disas_a32_extract_rd0mn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_SMULTB ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else { result = ( unsigned __int8 ) trans_SMULWB ( @@a1@@ , & @@v41@@ ) != Number ; } break ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_rd0mn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( unsigned __int16 ) @@a2@@ >> Number ) result = Number L ; else result = ( unsigned __int8 ) trans_SMULBT ( @@a1@@ , & @@v41@@ ) != Number ; } else { disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_SMLAWT ( @@a1@@ , & @@v41@@ ) != Number ; } break ; case Number : disas_a32_extract_rd0mn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_SMULTT ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else { result = ( unsigned __int8 ) trans_SMULWT ( @@a1@@ , & @@v41@@ ) != Number ; } break ; default : result = Number L ; break ; } } return result ; } } return Number L ; } if ( v2 > Number ) return Number L ; if ( v2 ) { if ( v2 != Number ) return Number L ; v4 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { v8 = ( @@a2@@ >> Number ) & Number ; if ( v8 == Number ) { disas_a32_extract_ldst_ri8_p0w1 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_LDRSHT_ri ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else if ( v8 == Number ) { disas_a32_extract_ldst_ri8_p0w1 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_LDRSBT_ri ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else if ( v8 ) { disas_a32_extract_ldst_ri8_p0w1 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_LDRHT_ri ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_STRHT_ri ( @@a1@@ , & @@v41@@ ) != Number ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_s_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_SMLAL ( @@a1@@ , & @@v41@@ ) != Number ; } else { disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_MLS ( @@a1@@ , & @@v41@@ ) != Number ; } } else if ( v4 == Number ) { disas_a32_extract_s_rrr_shr ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_RSC_rrrr ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_RSB_rrrr ( @@a1@@ , & @@v41@@ ) != Number ; } else { if ( v4 > Number ) return Number L ; if ( v4 == Number ) { v7 = ( @@a2@@ >> Number ) & Number ; if ( v7 == Number ) { disas_a32_extract_ldst_ri8_pw0 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_LDRSH_ri ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_STRD_ri_a32 ( @@a1@@ , & @@v41@@ ) != Number ; } else if ( v7 == Number ) { disas_a32_extract_ldst_ri8_pw0 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_LDRSB_ri ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_LDRD_ri_a32 ( @@a1@@ , & @@v41@@ ) != Number ; } else if ( v7 ) { disas_a32_extract_ldst_ri8_pw0 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_LDRH_ri ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_STRH_ri ( @@a1@@ , & @@v41@@ ) != Number ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_s_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_SMULL ( @@a1@@ , & @@v41@@ ) != Number ; } else { disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_UMAAL ( @@a1@@ , & @@v41@@ ) != Number ; } return result ; } if ( v4 > Number ) return Number L ; if ( v4 == Number ) { disas_a32_extract_s_rrr_shr ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_SBC_rrrr ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_SUB_rrrr ( @@a1@@ , & @@v41@@ ) != Number ; return result ; } if ( v4 > Number ) return Number L ; if ( v4 == Number ) { v6 = ( @@a2@@ >> Number ) & Number ; if ( v6 == Number ) { disas_a32_extract_ldst_rr_p0w1 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDRSHT_rr ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else if ( v6 == Number ) { disas_a32_extract_ldst_rr_p0w1 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDRSBT_rr ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else if ( v6 ) { disas_a32_extract_ldst_rr_p0w1 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDRHT_rr ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else { result = ( unsigned __int8 ) trans_STRHT_rr ( @@a1@@ , & @@v41@@ ) != Number ; } } else { disas_a32_extract_s_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_UMLAL ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_MLA ( @@a1@@ , & @@v41@@ ) != Number ; } return result ; } if ( v4 > Number ) return Number L ; if ( v4 == Number ) { disas_a32_extract_s_rrr_shr ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_ADC_rrrr ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_EOR_rrrr ( @@a1@@ , & @@v41@@ ) != Number ; return result ; } if ( v4 > Number ) return Number L ; if ( v4 ) { if ( v4 != Number ) return Number L ; v5 = ( @@a2@@ >> Number ) & Number ; if ( v5 == Number ) { disas_a32_extract_ldst_rr_pw0 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDRSH_rr ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else { result = ( unsigned __int8 ) trans_STRD_rr ( @@a1@@ , & @@v41@@ ) != Number ; } } else if ( v5 == Number ) { disas_a32_extract_ldst_rr_pw0 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDRSB_rr ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else { result = ( unsigned __int8 ) trans_LDRD_rr ( @@a1@@ , & @@v41@@ ) != Number ; } } else if ( v5 ) { disas_a32_extract_ldst_rr_pw0 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDRH_rr ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else { result = ( unsigned __int8 ) trans_STRH_rr ( @@a1@@ , & @@v41@@ ) != Number ; } } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_s_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_UMULL ( @@a1@@ , & @@v41@@ ) != Number ; } else { disas_a32_extract_s_rd0mn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( unsigned __int16 ) @@a2@@ >> Number ) result = Number L ; else result = ( unsigned __int8 ) trans_MUL ( @@a1@@ , & @@v41@@ ) != Number ; } } else { disas_a32_extract_s_rrr_shr ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_ADD_rrrr ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_AND_rrrr ( @@a1@@ , & @@v41@@ ) != Number ; } } } else { disas_a32_extract_s_rrr_shi ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; switch ( ( @@a2@@ >> Number ) & Number ) { case Number : result = ( unsigned __int8 ) trans_AND_rrri ( @@a1@@ , & @@v41@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_EOR_rrri ( @@a1@@ , & @@v41@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_SUB_rrri ( @@a1@@ , & @@v41@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_RSB_rrri ( @@a1@@ , & @@v41@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_ADD_rrri ( @@a1@@ , & @@v41@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_ADC_rrri ( @@a1@@ , & @@v41@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_SBC_rrri ( @@a1@@ , & @@v41@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_RSC_rrri ( @@a1@@ , & @@v41@@ ) != Number ; break ; default : result = Number L ; break ; } } } return result ; case Number : switch ( ( @@a2@@ >> Number ) & Number ) { case Number : disas_a32_extract_s_rri_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_AND_rri ( @@a1@@ , & @@v41@@ ) != Number ; case Number : disas_a32_extract_s_rri_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_EOR_rri ( @@a1@@ , & @@v41@@ ) != Number ; case Number : disas_a32_extract_s_rri_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SUB_rri ( @@a1@@ , & @@v41@@ ) != Number ; case Number : disas_a32_extract_s_rri_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_RSB_rri ( @@a1@@ , & @@v41@@ ) != Number ; case Number : disas_a32_extract_s_rri_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_ADD_rri ( @@a1@@ , & @@v41@@ ) != Number ; case Number : disas_a32_extract_s_rri_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_ADC_rri ( @@a1@@ , & @@v41@@ ) != Number ; case Number : disas_a32_extract_s_rri_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SBC_rri ( @@a1@@ , & @@v41@@ ) != Number ; case Number : disas_a32_extract_s_rri_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_RSC_rri ( @@a1@@ , & @@v41@@ ) != Number ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_S_xri_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( unsigned __int16 ) @@a2@@ >> Number ) result = Number L ; else result = ( unsigned __int8 ) trans_TST_xri ( @@a1@@ , & @@v41@@ ) != Number ; } else { disas_a32_extract_mov16 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_MOVW ( @@a1@@ , & @@v41@@ ) != Number ; } return result ; case Number : if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) != Number ) goto LABEL_457 ; if ( ( unsigned __int8 ) @@a2@@ == Number ) { disas_a32_extract_disas_a32_Fmt_16 ( ) ; if ( ( unsigned __int8 ) trans_YIELD ( @@a1@@ , & @@v41@@ ) ) return Number L ; } if ( ( unsigned __int8 ) @@a2@@ == Number ) { disas_a32_extract_disas_a32_Fmt_16 ( ) ; if ( ( unsigned __int8 ) trans_WFE ( @@a1@@ , & @@v41@@ ) ) return Number L ; } if ( ( unsigned __int8 ) @@a2@@ == Number ) { disas_a32_extract_disas_a32_Fmt_16 ( ) ; if ( ( unsigned __int8 ) trans_WFI ( @@a1@@ , & @@v41@@ ) ) return Number L ; } disas_a32_extract_disas_a32_Fmt_16 ( ) ; if ( ! ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v41@@ ) ) { LABEL_457 : disas_a32_extract_msr_i ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; @@v42@@ = Number ; result = ( unsigned __int8 ) trans_MSR_imm ( @@a1@@ , & @@v41@@ ) != Number ; } else { result = Number L ; } } else if ( ( @@a2@@ & Number ) == Number ) { disas_a32_extract_S_xri_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_TEQ_xri ( @@a1@@ , & @@v41@@ ) != Number ; } else { result = Number L ; } break ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_S_xri_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( unsigned __int16 ) @@a2@@ >> Number ) result = Number L ; else result = ( unsigned __int8 ) trans_CMP_xri ( @@a1@@ , & @@v41@@ ) != Number ; } else { disas_a32_extract_mov16 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_MOVT ( @@a1@@ , & @@v41@@ ) != Number ; } return result ; case Number : if ( ( @@a2@@ & Number ) == Number ) { disas_a32_extract_msr_i ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; @@v42@@ = Number ; result = ( unsigned __int8 ) trans_MSR_imm ( @@a1@@ , & @@v41@@ ) != Number ; } else if ( ( @@a2@@ & Number ) == Number ) { disas_a32_extract_S_xri_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_CMN_xri ( @@a1@@ , & @@v41@@ ) != Number ; } else { result = Number L ; } return result ; case Number : disas_a32_extract_s_rri_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_ORR_rri ( @@a1@@ , & @@v41@@ ) != Number ; case Number : disas_a32_extract_s_rxi_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_MOV_rxi ( @@a1@@ , & @@v41@@ ) != Number ; return result ; case Number : disas_a32_extract_s_rri_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_BIC_rri ( @@a1@@ , & @@v41@@ ) != Number ; case Number : disas_a32_extract_s_rxi_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_MVN_rxi ( @@a1@@ , & @@v41@@ ) != Number ; return result ; default : return Number L ; } return result ; case Number : v23 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_a32_extract_ldst_ri12_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_LDRB_ri ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v23 == Number ) { disas_a32_extract_ldst_ri12_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STRB_ri ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v23 > Number ) return Number L ; if ( v23 == Number ) { disas_a32_extract_ldst_ri12_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_LDR_ri ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v23 > Number ) return Number L ; if ( v23 == Number ) { disas_a32_extract_ldst_ri12_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STR_ri ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v23 > Number ) return Number L ; if ( v23 != Number ) { if ( v23 <= Number ) { if ( v23 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_ldst_ri12_p0w1 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STRBT_ri ( @@a1@@ , & @@v41@@ ) != Number ; } else { disas_a32_extract_ldst_ri12_pw0 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STRB_ri ( @@a1@@ , & @@v41@@ ) != Number ; } return result ; } if ( v23 <= Number ) { if ( ! v23 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_ldst_ri12_p0w1 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STRT_ri ( @@a1@@ , & @@v41@@ ) != Number ; } else { disas_a32_extract_ldst_ri12_pw0 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STR_ri ( @@a1@@ , & @@v41@@ ) != Number ; } return result ; } if ( v23 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_ldst_ri12_p0w1 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_LDRT_ri ( @@a1@@ , & @@v41@@ ) != Number ; } else { disas_a32_extract_ldst_ri12_pw0 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_LDR_ri ( @@a1@@ , & @@v41@@ ) != Number ; } return result ; } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_a32_extract_ldst_ri12_p0w1 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_LDRBT_ri ( @@a1@@ , & @@v41@@ ) != Number ; } else { disas_a32_extract_ldst_ri12_pw0 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_LDRB_ri ( @@a1@@ , & @@v41@@ ) != Number ; } return result ; case Number : v24 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { v40 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v40 == Number ) { disas_a32_extract_bfx ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_UBFX ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v40 <= Number ) { if ( v40 == Number ) { disas_a32_extract_disas_a32_Fmt_42 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_BFCI ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v40 <= Number ) { if ( v40 == Number ) { disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_SMLSLDX ( @@a1@@ , & @@v41@@ ) != Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_SMMLSR ( @@a1@@ , & @@v41@@ ) != Number ; return Number L ; } if ( v40 <= Number ) { if ( v40 == Number ) { disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_SMLSLD ( @@a1@@ , & @@v41@@ ) != Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_SMMLS ( @@a1@@ , & @@v41@@ ) != Number ; return Number L ; } if ( v40 <= Number ) { if ( ! v40 ) { disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_SMLALD ( @@a1@@ , & @@v41@@ ) != Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_SMMLA ( @@a1@@ , & @@v41@@ ) != Number ; return Number L ; } if ( v40 == Number ) { disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_SMLALDX ( @@a1@@ , & @@v41@@ ) != Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_SMMLAR ( @@a1@@ , & @@v41@@ ) != Number ; return Number L ; } } } } } return Number L ; } disas_a32_extract_disas_a32_Fmt_16 ( ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_UDF ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else { if ( v24 == Number ) { disas_a32_extract_ldst_rs_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_LDRB_rr ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_STRB_rr ( @@a1@@ , & @@v41@@ ) != Number ; return result ; } if ( v24 > Number ) return Number L ; if ( v24 == Number ) { v39 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_a32_extract_bfx ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SBFX ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v39 <= Number ) { if ( v39 == Number ) { disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_USADA8 ( @@a1@@ , & @@v41@@ ) != Number ; return result ; } if ( v39 <= Number ) { if ( v39 == Number ) { disas_a32_extract_rdmn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_UDIV ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; return result ; } if ( v39 <= Number ) { if ( v39 == Number ) { disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_SMLSDX ( @@a1@@ , & @@v41@@ ) != Number ; return result ; } if ( v39 <= Number ) { if ( v39 == Number ) { disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_SMLSD ( @@a1@@ , & @@v41@@ ) != Number ; return result ; } if ( v39 <= Number ) { if ( ! v39 ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_a32_extract_rdmn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( unsigned __int16 ) @@a2@@ >> Number == Number ) result = ( unsigned __int8 ) trans_SDIV ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else { result = Number L ; } } else { disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_SMLAD ( @@a1@@ , & @@v41@@ ) != Number ; } return result ; } if ( v39 == Number ) { disas_a32_extract_rdamn ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_SMLADX ( @@a1@@ , & @@v41@@ ) != Number ; return result ; } } } } } } return Number L ; } if ( v24 > Number ) return Number L ; if ( v24 == Number ) { disas_a32_extract_ldst_rs_p1w ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_LDR_rr ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_STR_rr ( @@a1@@ , & @@v41@@ ) != Number ; return result ; } if ( v24 > Number ) return Number L ; if ( v24 == Number ) { v33 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v33 == Number ) { disas_a32_extract_sat ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_USAT ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v33 <= Number ) { if ( v33 == Number ) { disas_a32_extract_rrr_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_UXTAB16 ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; return result ; } if ( v33 <= Number ) { if ( v33 == Number ) { disas_a32_extract_rndm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; v37 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_UHSUB8 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v37 == Number ) return ( unsigned __int8 ) trans_UHSUB16 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v37 <= Number ) { if ( v37 == Number ) return ( unsigned __int8 ) trans_UHASX ( @@a1@@ , & @@v41@@ ) != Number ; if ( v37 <= Number ) { if ( v37 == Number ) return ( unsigned __int8 ) trans_UQSUB8 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v37 <= Number ) { if ( v37 == Number ) return ( unsigned __int8 ) trans_UQASX ( @@a1@@ , & @@v41@@ ) != Number ; if ( v37 == Number ) return ( unsigned __int8 ) trans_UQSUB16 ( @@a1@@ , & @@v41@@ ) != Number ; } } } return Number L ; } if ( v33 <= Number ) { if ( v33 == Number ) { disas_a32_extract_rndm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; v36 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_UHADD8 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v36 <= Number ) { if ( v36 == Number ) return ( unsigned __int8 ) trans_UHSAX ( @@a1@@ , & @@v41@@ ) != Number ; if ( v36 <= Number ) { if ( v36 == Number ) return ( unsigned __int8 ) trans_UHADD16 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v36 <= Number ) { if ( v36 == Number ) return ( unsigned __int8 ) trans_UQADD8 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v36 <= Number ) { if ( v36 == Number ) return ( unsigned __int8 ) trans_UQADD16 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v36 == Number ) return ( unsigned __int8 ) trans_UQSAX ( @@a1@@ , & @@v41@@ ) != Number ; } } } } return Number L ; } if ( v33 <= Number ) { if ( ! v33 ) { disas_a32_extract_rndm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; v34 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_UADD8 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v34 > Number ) goto LABEL_655 ; if ( v34 == Number ) return ( unsigned __int8 ) trans_UADD16 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v34 == Number ) result = ( unsigned __int8 ) trans_USAX ( @@a1@@ , & @@v41@@ ) != Number ; else LABEL_655 : result = Number L ; return result ; } if ( v33 == Number ) { disas_a32_extract_rndm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; v35 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_USUB8 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v35 == Number ) return ( unsigned __int8 ) trans_UASX ( @@a1@@ , & @@v41@@ ) != Number ; if ( v35 == Number ) return ( unsigned __int8 ) trans_USUB16 ( @@a1@@ , & @@v41@@ ) != Number ; return Number L ; } } } } } return Number L ; } v38 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v38 <= Number ) { if ( v38 == Number ) { disas_a32_extract_rdm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_RBIT ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; return result ; } if ( v38 <= Number ) { if ( v38 == Number ) { disas_a32_extract_rrr_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_UXTAH ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v38 <= Number ) { if ( v38 == Number ) { disas_a32_extract_rrr_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_UXTAB ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v38 == Number ) { disas_a32_extract_sat16 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_USAT16 ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; return result ; } } } } return Number L ; } disas_a32_extract_rdm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_REVSH ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else { if ( v24 > Number ) return Number L ; if ( v24 == Number ) { v32 = ( @@a2@@ >> Number ) & Number ; if ( v32 == Number ) { disas_a32_extract_ldst_rs_p0w1 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_LDRBT_rr ( @@a1@@ , & @@v41@@ ) != Number ; } else if ( v32 == Number ) { disas_a32_extract_ldst_rs_p0w1 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STRBT_rr ( @@a1@@ , & @@v41@@ ) != Number ; } else if ( v32 ) { disas_a32_extract_ldst_rs_pw0 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_LDRB_rr ( @@a1@@ , & @@v41@@ ) != Number ; } else { disas_a32_extract_ldst_rs_pw0 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STRB_rr ( @@a1@@ , & @@v41@@ ) != Number ; } return result ; } if ( v24 > Number ) return Number L ; if ( ! v24 ) { v25 = ( @@a2@@ >> Number ) & Number ; if ( v25 == Number ) { disas_a32_extract_ldst_rs_p0w1 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_LDRT_rr ( @@a1@@ , & @@v41@@ ) != Number ; } else if ( v25 == Number ) { disas_a32_extract_ldst_rs_p0w1 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STRT_rr ( @@a1@@ , & @@v41@@ ) != Number ; } else if ( v25 ) { disas_a32_extract_ldst_rs_pw0 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_LDR_rr ( @@a1@@ , & @@v41@@ ) != Number ; } else { disas_a32_extract_ldst_rs_pw0 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STR_rr ( @@a1@@ , & @@v41@@ ) != Number ; } return result ; } if ( v24 != Number ) return Number L ; v26 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v26 == Number ) { disas_a32_extract_sat ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SSAT ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v26 <= Number ) { if ( v26 == Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_a32_extract_rrr_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_SXTAB16 ( @@a1@@ , & @@v41@@ ) != Number ; } else if ( ( @@a2@@ & Number ) == Number ) { disas_a32_extract_rndm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_SEL ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } else { result = Number L ; } return result ; } if ( v26 <= Number ) { if ( v26 == Number ) { disas_a32_extract_disas_a32_Fmt_43 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_PKH ( @@a1@@ , & @@v41@@ ) != Number ; return result ; } if ( v26 <= Number ) { if ( v26 == Number ) { disas_a32_extract_rndm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; v30 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_SHSUB8 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v30 == Number ) return ( unsigned __int8 ) trans_SHSUB16 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v30 <= Number ) { if ( v30 == Number ) return ( unsigned __int8 ) trans_SHASX ( @@a1@@ , & @@v41@@ ) != Number ; if ( v30 <= Number ) { if ( v30 == Number ) return ( unsigned __int8 ) trans_QSUB8 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v30 <= Number ) { if ( v30 == Number ) return ( unsigned __int8 ) trans_QASX ( @@a1@@ , & @@v41@@ ) != Number ; if ( v30 == Number ) return ( unsigned __int8 ) trans_QSUB16 ( @@a1@@ , & @@v41@@ ) != Number ; } } } return Number L ; } if ( v26 <= Number ) { if ( v26 == Number ) { disas_a32_extract_rndm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; v29 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_SHADD8 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v29 <= Number ) { if ( v29 == Number ) return ( unsigned __int8 ) trans_SHSAX ( @@a1@@ , & @@v41@@ ) != Number ; if ( v29 <= Number ) { if ( v29 == Number ) return ( unsigned __int8 ) trans_SHADD16 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v29 <= Number ) { if ( v29 == Number ) return ( unsigned __int8 ) trans_QADD8 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v29 <= Number ) { if ( v29 == Number ) return ( unsigned __int8 ) trans_QADD16 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v29 == Number ) return ( unsigned __int8 ) trans_QSAX ( @@a1@@ , & @@v41@@ ) != Number ; } } } } return Number L ; } if ( v26 <= Number ) { if ( ! v26 ) { disas_a32_extract_rndm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; v27 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_SADD8 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v27 > Number ) goto LABEL_552 ; if ( v27 == Number ) return ( unsigned __int8 ) trans_SADD16 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v27 == Number ) result = ( unsigned __int8 ) trans_SSAX ( @@a1@@ , & @@v41@@ ) != Number ; else LABEL_552 : result = Number L ; return result ; } if ( v26 == Number ) { disas_a32_extract_rndm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; v28 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_SSUB8 ( @@a1@@ , & @@v41@@ ) != Number ; if ( v28 == Number ) return ( unsigned __int8 ) trans_SASX ( @@a1@@ , & @@v41@@ ) != Number ; if ( v28 == Number ) return ( unsigned __int8 ) trans_SSUB16 ( @@a1@@ , & @@v41@@ ) != Number ; return Number L ; } } } } } } return Number L ; } v31 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v31 <= Number ) { if ( v31 == Number ) { disas_a32_extract_rdm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_REV ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; return result ; } if ( v31 <= Number ) { if ( v31 == Number ) { disas_a32_extract_rrr_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SXTAH ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v31 <= Number ) { if ( v31 == Number ) { disas_a32_extract_rrr_rot ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SXTAB ( @@a1@@ , & @@v41@@ ) != Number ; } if ( v31 == Number ) { disas_a32_extract_sat16 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_SSAT16 ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; return result ; } } } } return Number L ; } disas_a32_extract_rdm ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_REV16 ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; } } return result ; case Number : disas_a32_extract_disas_a32_Fmt_48 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_LDM_a32 ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_STM ( @@a1@@ , & @@v41@@ ) != Number ; return result ; case Number : disas_a32_extract_branch ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = ( unsigned __int8 ) trans_BL ( @@a1@@ , & @@v41@@ ) != Number ; else result = ( unsigned __int8 ) trans_B ( @@a1@@ , & @@v41@@ ) != Number ; return result ; case Number : disas_a32_extract_disas_a32_Fmt_50 ( @@a1@@ , & @@v41@@ , @@a2@@ ) ; if ( ( HIBYTE ( @@a2@@ ) & Number ) == Number ) result = ( unsigned __int8 ) trans_SVC ( @@a1@@ , & @@v41@@ ) != Number ; else result = Number L ; return result ; default : return Number L ; } }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v42\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s40\"}, {\"n\": \"v41\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s48\"}, {\"n\": \"v43\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"disas_a32_uncond\", \"code\": \"_BOOL8 __fastcall disas_a32_uncond ( __int64 @@a1@@ , unsigned int @@a2@@ ) { _BOOL8 result ; unsigned int v3 ; unsigned int v4 ; unsigned int v5 ; _DWORD @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; switch ( @@a2@@ >> Number ) { case String : if ( ( @@a2@@ & Number ) == Number ) { disas_a32_uncond_extract_disas_a32_uncond_Fmt_3 ( @@a1@@ , @@v6@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_CPS ( @@a1@@ , @@v6@@ ) != Number ; } else if ( ( @@a2@@ & Number ) == Number ) { disas_a32_uncond_extract_disas_a32_uncond_Fmt_5 ( @@a1@@ , @@v6@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_SETEND ( @@a1@@ , @@v6@@ ) != Number ; } else { result = Number L ; } return result ; case String : disas_a32_uncond_extract_disas_a32_uncond_Fmt_4 ( ) ; v3 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { v4 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v4 <= Number ) { if ( v4 == Number ) return ( unsigned __int8 ) trans_ISB ( @@a1@@ , @@v6@@ ) != Number ; if ( v4 <= Number ) { if ( v4 == Number ) return ( unsigned __int8 ) trans_DMB ( @@a1@@ , @@v6@@ ) != Number ; if ( v4 <= Number ) { if ( v4 == Number ) { if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_CLREX ( @@a1@@ , @@v6@@ ) != Number ; else result = Number L ; return result ; } if ( v4 == Number ) return ( unsigned __int8 ) trans_DSB ( @@a1@@ , @@v6@@ ) != Number ; } } } return Number L ; } if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_SB ( @@a1@@ , @@v6@@ ) != Number ; } else if ( v3 == Number ) { if ( ( unsigned __int16 ) @@a2@@ >> Number == Number ) goto LABEL_26 ; result = Number L ; } else { if ( v3 > Number ) return Number L ; if ( v3 == Number ) { if ( ( unsigned __int16 ) @@a2@@ >> Number == Number ) return ( unsigned __int8 ) trans_PLDW ( @@a1@@ , @@v6@@ ) != Number ; result = Number L ; } else { if ( v3 > Number ) return Number L ; if ( v3 == Number ) return ( unsigned __int8 ) trans_PLDW ( @@a1@@ , @@v6@@ ) != Number ; if ( v3 != Number ) return Number L ; if ( ( unsigned __int16 ) @@a2@@ >> Number == Number ) goto LABEL_21 ; result = Number L ; } } return result ; case String : disas_a32_uncond_extract_disas_a32_uncond_Fmt_4 ( ) ; v5 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { if ( ( unsigned __int16 ) @@a2@@ >> Number == Number ) LABEL_26 : result = ( unsigned __int8 ) trans_PLD ( @@a1@@ , @@v6@@ ) != Number ; else result = Number L ; return result ; } if ( v5 > Number ) return Number L ; if ( v5 == Number ) { if ( ( unsigned __int16 ) @@a2@@ >> Number != Number ) return Number L ; return ( unsigned __int8 ) trans_PLDW ( @@a1@@ , @@v6@@ ) != Number ; } if ( v5 > Number ) return Number L ; if ( v5 == Number ) return ( unsigned __int8 ) trans_PLDW ( @@a1@@ , @@v6@@ ) != Number ; if ( v5 != Number ) return Number L ; if ( ( unsigned __int16 ) @@a2@@ >> Number == Number ) LABEL_21 : result = ( unsigned __int8 ) trans_PLI ( @@a1@@ , @@v6@@ ) != Number ; else result = Number L ; return result ; case String : if ( ( @@a2@@ & Number ) == Number ) { disas_a32_uncond_extract_disas_a32_uncond_Fmt_1 ( @@a1@@ , @@v6@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_RFE ( @@a1@@ , @@v6@@ ) != Number ; } else if ( ( @@a2@@ & Number ) == Number ) { disas_a32_uncond_extract_disas_a32_uncond_Fmt_2 ( @@a1@@ , @@v6@@ , @@a2@@ ) ; if ( ( HIWORD ( @@a2@@ ) & Number ) == Number ) result = ( unsigned __int8 ) trans_SRS ( @@a1@@ , @@v6@@ ) != Number ; else result = Number L ; } else { result = Number L ; } return result ; case String : disas_a32_uncond_extract_disas_a32_uncond_Fmt_0 ( @@a1@@ , @@v6@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_BLX_i ( @@a1@@ , @@v6@@ ) != Number ; default : return Number L ; } }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 6, \"s\": 4, \"t\": \"_DWORD\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "thumb_insn_is_16bit", "code": "_BOOL8 __fastcall thumb_insn_is_16bit ( __int64 @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { if ( @@a3@@ >> Number <= Number ) return Number L ; if ( arm_dc_feature ( @@a1@@ , Number ) || arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; return @@a3@@ >> Number != Number || ( unsigned __int64 ) @@a2@@ - * ( _QWORD * ) ( @@a1@@ + Number ) >= ( int ) ( Number - target_page [ Number ] ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}]} | [{"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "pc", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,514 | [
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}"
] |
{"name": "disas_thumb2_insn", "code": "__int64 __fastcall disas_thumb2_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 result ; unsigned int v3 ; unsigned int @@v4@@ ; unsigned int v5 ; char @@v6@@ ; signed int @@i@@ ; __int64 @@v8@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) || arm_dc_feature ( @@a1@@ , Number ) ) { if ( ( @@a2@@ & Number ) != Number && ! arm_dc_feature ( @@a1@@ , Number ) ) return unallocated_encoding ( @@a1@@ ) ; } else { @@v6@@ = Number ; for ( @@i@@ = Number ; ( unsigned int ) @@i@@ <= Number ; ++ @@i@@ ) { if ( ( @@a2@@ & armv6m_mask_63011 [ @@i@@ ] ) == armv6m_insn_63010 [ @@i@@ ] ) { @@v6@@ = Number ; break ; } } if ( @@v6@@ != Number ) return unallocated_encoding ( @@a1@@ ) ; } result = disas_t32 ( @@a1@@ , @@a2@@ ) ; if ( ( _BYTE ) result ) return result ; v3 = ( @@a2@@ >> Number ) & Number ; if ( v3 < Number ) { if ( v3 == Number ) { if ( ( @@a2@@ & Number ) == Number ) { result = disas_neon_ls_insn ( @@a1@@ , @@a2@@ ) ; if ( ! ( _DWORD ) result ) return result ; } return unallocated_encoding ( @@a1@@ ) ; } if ( v3 > Number ) return unallocated_encoding ( @@a1@@ ) ; if ( v3 <= Number ) abort ( ) ; if ( v3 - Number > Number ) return unallocated_encoding ( @@a1@@ ) ; } if ( arm_dc_feature ( @@a1@@ , Number ) ) { if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) != Number ) { if ( ! arm_dc_feature ( @@a1@@ , Number ) || ( @@a2@@ & Number ) != Number ) { if ( ! arm_dc_feature ( @@a1@@ , Number ) || ( ( @@a2@@ >> Number ) & Number ) != Number ) { @@v4@@ = default_exception_el ( @@a1@@ ) ; v5 = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , v5 , @@v4@@ ) ; } result = disas_vfp_insn ( @@a1@@ , @@a2@@ ) ; if ( ! ( _DWORD ) result ) return result ; return unallocated_encoding ( @@a1@@ ) ; } if ( * ( _BYTE * ) ( @@a1@@ + Number ) == Number && ( @@a2@@ & Number ) == Number ) { result = arm_dc_feature ( @@a1@@ , Number ) ; if ( ( _DWORD ) result ) { @@v8@@ = load_reg ( @@a1@@ , HIWORD ( @@a2@@ ) & Number ) ; if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) gen_helper_v7m_vlldm ( cpu_env , @@v8@@ ) ; else gen_helper_v7m_vlstm ( cpu_env , @@v8@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; result = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return result ; } } return unallocated_encoding ( @@a1@@ ) ; } if ( ( @@a2@@ & Number ) == Number && arm_dc_feature ( @@a1@@ , Number ) ) { result = disas_neon_insn_3same_ext ( @@a1@@ , @@a2@@ ) ; if ( ! ( _DWORD ) result ) return result ; return unallocated_encoding ( @@a1@@ ) ; } if ( ( @@a2@@ & Number ) == Number && arm_dc_feature ( @@a1@@ , Number ) ) { result = disas_neon_insn_2reg_scalar_ext ( @@a1@@ , @@a2@@ ) ; if ( ! ( _DWORD ) result ) return result ; return unallocated_encoding ( @@a1@@ ) ; } if ( ( HIBYTE ( @@a2@@ ) & Number ) == Number ) { result = disas_neon_data_insn ( @@a1@@ , @@a2@@ & Number | ( @@a2@@ >> Number ) & Number | Number ) ; if ( ! ( _DWORD ) result ) return result ; return unallocated_encoding ( @@a1@@ ) ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { result = disas_vfp_insn ( @@a1@@ , @@a2@@ ) ; if ( ! ( _DWORD ) result ) return result ; return unallocated_encoding ( @@a1@@ ) ; } if ( ( @@a2@@ & Number ) != Number ) return unallocated_encoding ( @@a1@@ ) ; result = disas_coproc_insn ( @@a1@@ , @@a2@@ ) ; if ( ( _DWORD ) result ) return unallocated_encoding ( @@a1@@ ) ; return result ; }", "source": [{"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r32"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "i", "t": {"T": 1, "n": "signed int", "s": 4}, "location": "s32"}, {"n": "v6", "t": {"T": 1, "n": "char", "s": 1}, "location": "s33"}]} | [{"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r32"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "fptr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "i", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s32"}, {"n": "found", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s33"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,515 | [
"{\"name\": \"extract32\", \"code\": \"__int64 __fastcall extract32 ( unsigned int @@a1@@ , int @@a2@@ , int @@a3@@ ) { if ( @@a2@@ < Number || @@a3@@ <= Number || @@a3@@ > Number - @@a2@@ ) _assert_fail ( String , String , Number , String ) ; return ( @@a1@@ >> @@a2@@ ) & ( Number >> ( Number - @@a3@@ ) ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_v7m_vlstm\", \"code\": \"unsigned __int64 __fastcall gen_helper_v7m_vlstm ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_v7m_vlstm , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_v7m_vlldm\", \"code\": \"unsigned __int64 __fastcall gen_helper_v7m_vlldm ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_v7m_vlldm , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"default_exception_el\", \"code\": \"__int64 __fastcall default_exception_el ( __int64 @@a1@@ ) { __int64 @@result@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) == Number && * ( _BYTE * ) ( @@a1@@ + Number ) ) return Number L ; @@result@@ = * ( unsigned int * ) ( @@a1@@ + Number ) ; if ( ( int ) @@result@@ <= Number ) @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception_insn\", \"code\": \"__int64 __fastcall gen_exception_insn ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , unsigned int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@result@@ ; gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; gen_exception ( @@a3@@ , @@a4@@ , @@a5@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"disas_vfp\", \"code\": \"_BOOL8 __fastcall disas_vfp ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; _BOOL8 result ; unsigned int v4 ; unsigned int v5 ; unsigned int v6 ; unsigned int v7 ; unsigned int v8 ; unsigned int v9 ; unsigned int v10 ; unsigned int v11 ; unsigned int v12 ; unsigned int v13 ; unsigned int v14 ; unsigned int v15 ; _DWORD @@v16@@ [ Number ] ; unsigned __int64 @@v17@@ ; @@v17@@ = __readfsqword ( Number ) ; v2 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { v10 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_0 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { result = Number L ; } } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_1 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_2 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v10 != Number ) { if ( v10 <= Number ) { if ( ! v10 ) { v11 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_22 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v11 != Number ) { if ( v11 <= Number ) { if ( ! v11 ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VMLS_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VMLA_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v11 == Number ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VNMUL_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VMUL_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } return Number L ; } disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDIV_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v10 == Number ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_6 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDUP ( @@a1@@ , @@v16@@ ) != Number ; } else { result = Number L ; } } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_3 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_4 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_5 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } } return Number L ; } v12 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v12 == Number ) { disas_vfp_extract_disas_vfp_Fmt_20 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v12 <= Number ) { if ( ! v12 ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VNMLA_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VNMLS_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v12 == Number ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VSUB_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VADD_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_24 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_imm_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } v13 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_37 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_fix_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v13 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_39 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_dp_int ( @@a1@@ , @@v16@@ ) != Number ; } else if ( ( @@a2@@ & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_33 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_VJCVT ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } else { disas_vfp_extract_disas_vfp_Fmt_35 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_int_dp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v13 > Number ) return Number L ; if ( ! v13 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_28 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCMP_dp ( @@a1@@ , @@v16@@ ) != Number ; } disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v14 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSQRT_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 == Number ) return ( unsigned __int8 ) trans_VNEG_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 > Number ) goto LABEL_195 ; if ( ! v14 ) return ( unsigned __int8 ) trans_VMOV_reg_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 == Number ) result = ( unsigned __int8 ) trans_VABS_dp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_195 : result = Number L ; return result ; } if ( v13 != ( _DWORD ) & loc_20000 ) return Number L ; v15 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != ( _DWORD ) & unk_50000 ) { if ( v15 <= ( unsigned int ) & unk_50000 ) { if ( v15 == Number ) { disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VRINTZ_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VRINTR_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v15 <= Number ) { if ( ! v15 ) { disas_vfp_extract_disas_vfp_Fmt_30 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f64_f16 ( @@a1@@ , @@v16@@ ) != Number ; } if ( v15 == Number ) { disas_vfp_extract_disas_vfp_Fmt_31 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f16_f64 ( @@a1@@ , @@v16@@ ) != Number ; } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_33 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VRINTX_dp ( @@a1@@ , @@v16@@ ) != Number ; } } else { if ( v2 > Number ) return Number L ; if ( v2 != Number ) { if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_16 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VLDM_VSTM_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_12 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDR_VSTR_dp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_15 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VLDM_VSTM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_11 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDR_VSTR_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_13 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDM_VSTM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_9 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMOV_64_sp ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } } else { if ( v2 != Number ) return Number L ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_14 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDM_VSTM_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_10 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMOV_64_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } } return result ; } } } return Number L ; } v4 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_7 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMSR_VMRS ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; return result ; } if ( v4 != Number ) { if ( v4 <= Number ) { if ( v4 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_19 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VFM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDIV_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v4 <= Number ) { if ( v4 == Number ) { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v6 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSUB_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 == Number ) return ( unsigned __int8 ) trans_VADD_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 > Number ) goto LABEL_66 ; if ( ! v6 ) return ( unsigned __int8 ) trans_VMUL_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 == Number ) result = ( unsigned __int8 ) trans_VNMUL_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_66 : result = Number L ; return result ; } if ( v4 <= Number ) { if ( ! v4 ) { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v5 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VNMLA_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 == Number ) return ( unsigned __int8 ) trans_VNMLS_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 > Number ) goto LABEL_52 ; if ( ! v5 ) return ( unsigned __int8 ) trans_VMLA_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 == Number ) result = ( unsigned __int8 ) trans_VMLS_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_52 : result = Number L ; return result ; } if ( v4 == Number ) { disas_vfp_extract_disas_vfp_Fmt_8 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_single ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_21 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_sp ( @@a1@@ , @@v16@@ ) != Number ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_23 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_imm_sp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } v7 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_36 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_fix_sp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v7 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_38 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_sp_int ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_34 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VCVT_int_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v7 > Number ) return Number L ; if ( ! v7 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_27 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCMP_sp ( @@a1@@ , @@v16@@ ) != Number ; } disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v8 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSQRT_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 == Number ) return ( unsigned __int8 ) trans_VNEG_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 > Number ) goto LABEL_96 ; if ( ! v8 ) return ( unsigned __int8 ) trans_VMOV_reg_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 == Number ) result = ( unsigned __int8 ) trans_VABS_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_96 : result = Number L ; return result ; } if ( v7 != ( _DWORD ) & loc_20000 ) return Number L ; v9 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != ( _DWORD ) & unk_50000 ) { if ( v9 <= ( unsigned int ) & unk_50000 ) { if ( v9 == Number ) { disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VRINTZ_sp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VRINTR_sp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v9 <= Number ) { if ( ! v9 ) { disas_vfp_extract_disas_vfp_Fmt_29 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f32_f16 ( @@a1@@ , @@v16@@ ) != Number ; } if ( v9 == Number ) { disas_vfp_extract_disas_vfp_Fmt_29 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f16_f32 ( @@a1@@ , @@v16@@ ) != Number ; } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_32 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VRINTX_sp ( @@a1@@ , @@v16@@ ) != Number ; } } return result ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v16\", \"t\": {\"T\": 2, \"n\": 10, \"s\": 4, \"t\": \"_DWORD\"}, \"location\": \"s48\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"disas_vfp_insn\", \"code\": \"__int64 __fastcall disas_vfp_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) == Number ) { if ( disas_vfp_uncond ( @@a1@@ , @@a2@@ ) ) return Number L ; } else if ( disas_vfp ( @@a1@@ , @@a2@@ ) ) { return Number L ; } return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"disas_neon_ls_insn\", \"code\": \"__int64 __fastcall disas_neon_ls_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; unsigned int v3 ; int v5 ; int v6 ; int v7 ; int v8 ; int v9 ; unsigned int v10 ; unsigned int v11 ; unsigned int v12 ; unsigned int v13 ; int v14 ; int v15 ; int v16 ; int v17 ; int v18 ; int v19 ; int @@v20@@ ; unsigned int v21 ; int v22 ; int v23 ; int v24 ; int v25 ; unsigned int v26 ; int i ; int l ; int m ; int @@j@@ ; int @@v31@@ ; int @@k@@ ; int @@v33@@ ; int @@v34@@ ; int @@v35@@ ; int @@v36@@ ; int @@v37@@ ; int v38 ; int v39 ; int v40 ; int @@v41@@ ; unsigned int @@v42@@ ; unsigned int @@v43@@ ; int @@v44@@ ; int @@v45@@ ; int @@v46@@ ; __int64 v47 ; __int64 v48 ; __int64 v49 ; __int64 v50 ; __int64 v51 ; __int64 @@v52@@ ; __int64 @@v53@@ ; __int64 @@v54@@ ; __int64 @@v55@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { v2 = * ( _DWORD * ) ( @@a1@@ + Number ) ; v3 = syn_simd_access_trap ( Number , Number , Number ) ; gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , v3 , v2 ) ; return Number L ; } if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) return Number L ; if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v20@@ = ( ( unsigned __int16 ) @@a2@@ >> Number ) | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v20@@ = ( unsigned __int16 ) @@a2@@ >> Number ; } @@v34@@ = HIWORD ( @@a2@@ ) & Number ; @@v35@@ = @@a2@@ & Number ; @@v31@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; @@v36@@ = get_mem_index ( @@a1@@ ) ; if ( ( @@a2@@ & Number ) == Number ) { @@v43@@ = ( @@a2@@ >> Number ) & Number ; v24 = ( unsigned __int8 ) @@a2@@ >> Number ; if ( @@v43@@ > Number ) return Number L ; v5 = @@v43@@ & Number ; if ( v5 == Number ) { if ( ( @@a2@@ & Number ) != Number ) return Number L ; } else if ( v5 == Number && ( ( @@a2@@ >> Number ) & Number ) == Number ) { return Number L ; } v38 = * ( ( _DWORD * ) & neon_ls_element_type + Number * ( int ) @@v43@@ ) ; @@v44@@ = * ( ( _DWORD * ) & unk_4D764 + Number * ( int ) @@v43@@ ) ; @@v45@@ = dword_4D768 [ Number * @@v43@@ ] ; if ( v24 == Number && ( @@v45@@ | @@v44@@ ) != Number ) return Number L ; if ( ! ( ( unsigned __int8 ) @@a2@@ >> Number ) ) @@v31@@ = Number ; if ( @@v44@@ == Number && ! @@v31@@ ) v24 = Number ; @@v52@@ = tcg_temp_new_i64 ( ) ; v49 = tcg_temp_new_i32 ( ) ; @@v53@@ = tcg_const_i32 ( ( unsigned int ) ( Number << v24 ) ) ; load_reg_var ( @@a1@@ , v49 , @@v34@@ ) ; for ( i = Number ; i < v38 ; ++ i ) { for ( @@j@@ = Number ; @@j@@ < Number >> v24 ; ++ @@j@@ ) { for ( @@k@@ = Number ; @@k@@ < @@v44@@ ; ++ @@k@@ ) { @@v46@@ = i + @@v20@@ + @@k@@ * @@v45@@ ; if ( ( @@a2@@ & Number ) != Number ) { gen_aa32_ld_i64 ( @@a1@@ , @@v52@@ , v49 , @@v36@@ , @@v31@@ | v24 ) ; neon_store_element64 ( @@v46@@ , @@j@@ , v24 , @@v52@@ ) ; } else { neon_load_element64 ( @@v52@@ , @@v46@@ , @@j@@ , v24 ) ; gen_aa32_st_i64 ( @@a1@@ , @@v52@@ , v49 , @@v36@@ , @@v31@@ | v24 ) ; } tcg_gen_add_i32 ( v49 , v49 , @@v53@@ ) ; } } } tcg_temp_free_i32 ( v49 ) ; tcg_temp_free_i32 ( @@v53@@ ) ; tcg_temp_free_i64 ( @@v52@@ ) ; v21 = Number * @@v44@@ * v38 ; goto LABEL_111 ; } v25 = ( @@a2@@ >> Number ) & Number ; if ( v25 == Number ) { @@v41@@ = ( @@a2@@ >> Number ) & Number ; if ( ( @@a2@@ & Number ) == Number ) return Number L ; v26 = ( unsigned __int8 ) @@a2@@ >> Number ; v39 = ( ( @@a2@@ >> Number ) & Number ) + Number ; if ( v26 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number || ! @@v41@@ ) return Number L ; v26 = Number ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number && @@v41@@ == Number && ! v26 ) return Number L ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number && @@v41@@ == Number ) return Number L ; v50 = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , v50 , @@v34@@ ) ; if ( ( @@a2@@ & Number ) != Number ) v6 = Number ; else v6 = Number ; v22 = v6 ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) v7 = Number ; else v7 = Number * v6 ; @@v42@@ = v7 ; v47 = tcg_temp_new_i32 ( ) ; for ( l = Number ; l < v39 ; ++ l ) { v8 = v26 | * ( _DWORD * ) ( @@a1@@ + Number ) ; v9 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld_i32 ( @@a1@@ , v47 , v50 , v9 , v8 ) ; if ( ( @@v20@@ & Number ) != Number && @@v42@@ == Number ) { v10 = neon_reg_offset ( @@v20@@ , Number ) ; tcg_gen_gvec_dup_i32 ( v26 , v10 , Number L , Number L , v47 ) ; v11 = neon_reg_offset ( @@v20@@ , Number ) ; v12 = neon_reg_offset ( @@v20@@ + Number , Number ) ; tcg_gen_gvec_mov ( Number L , v12 , v11 , Number L , Number L ) ; } else { v13 = neon_reg_offset ( @@v20@@ , Number ) ; tcg_gen_gvec_dup_i32 ( v26 , v13 , @@v42@@ , @@v42@@ , v47 ) ; } tcg_gen_addi_i32 ( v50 , v50 , ( unsigned int ) ( Number << v26 ) ) ; @@v20@@ += v22 ; } tcg_temp_free_i32 ( v47 ) ; tcg_temp_free_i32 ( v50 ) ; v21 = v39 << v26 ; goto LABEL_111 ; } @@v37@@ = ( unsigned __int8 ) @@a2@@ >> Number ; if ( v25 == Number ) { @@v33@@ = ( @@a2@@ >> Number ) & Number ; if ( ( @@a2@@ & Number ) != Number ) v15 = Number ; else v15 = Number ; v23 = v15 ; } else if ( v25 ) { @@v33@@ = ( unsigned __int8 ) @@a2@@ >> Number ; if ( ( @@a2@@ & Number ) != Number ) v14 = Number ; else v14 = Number ; v23 = v14 ; } else { @@v33@@ = ( unsigned __int8 ) @@a2@@ >> Number ; v23 = Number ; } v40 = ( ( @@a2@@ >> Number ) & Number ) + Number ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { if ( v25 == Number && ( @@v37@@ & Number ) == Number ) return Number L ; goto LABEL_102 ; } if ( v40 > Number ) goto LABEL_101 ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { if ( ( @@a2@@ & Number ) != Number ) return Number L ; LABEL_95 : if ( v25 == Number && ( @@v37@@ & Number ) != Number ) return Number L ; goto LABEL_102 ; } if ( v40 > Number ) goto LABEL_101 ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) LABEL_101 : abort ( ) ; goto LABEL_95 ; } if ( ( ( @@v37@@ >> v25 ) & Number ) != Number || v25 == Number && ( ( @@v37@@ & Number ) == Number || ( @@v37@@ & Number ) == Number ) ) return Number L ; LABEL_102 : if ( ( int ) ( v23 * ( ( @@a2@@ >> Number ) & Number ) + @@v20@@ ) > Number ) return Number L ; v48 = tcg_temp_new_i32 ( ) ; v51 = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , v51 , @@v34@@ ) ; for ( m = Number ; m < v40 ; ++ m ) { if ( ( @@a2@@ & Number ) != Number ) { v16 = v25 | * ( _DWORD * ) ( @@a1@@ + Number ) ; v17 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld_i32 ( @@a1@@ , v48 , v51 , v17 , v16 ) ; neon_store_element ( @@v20@@ , @@v33@@ , v25 , v48 ) ; } else { neon_load_element ( v48 , @@v20@@ , @@v33@@ , v25 ) ; v18 = v25 | * ( _DWORD * ) ( @@a1@@ + Number ) ; v19 = get_mem_index ( @@a1@@ ) ; gen_aa32_st_i32 ( @@a1@@ , v48 , v51 , v19 , v18 ) ; } @@v20@@ += v23 ; tcg_gen_addi_i32 ( v51 , v51 , ( unsigned int ) ( Number << v25 ) ) ; } tcg_temp_free_i32 ( v51 ) ; tcg_temp_free_i32 ( v48 ) ; v21 = v40 << v25 ; LABEL_111 : if ( @@v35@@ != Number ) { @@v54@@ = load_reg ( @@a1@@ , @@v34@@ ) ; if ( @@v35@@ == Number ) { tcg_gen_addi_i32 ( @@v54@@ , @@v54@@ , v21 ) ; } else { @@v55@@ = load_reg ( @@a1@@ , @@v35@@ ) ; tcg_gen_add_i32 ( @@v54@@ , @@v54@@ , @@v55@@ ) ; tcg_temp_free_i32 ( @@v55@@ ) ; } store_reg ( @@a1@@ , @@v34@@ , @@v54@@ ) ; } return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v36\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v35\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s108\"}, {\"n\": \"v34\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s112\"}, {\"n\": \"v33\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s116\"}, {\"n\": \"k\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s120\"}, {\"n\": \"v31\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s124\"}, {\"n\": \"j\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s128\"}, {\"n\": \"v20\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s144\"}, {\"n\": \"v55\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v54\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v53\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v52\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v46\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s68\"}, {\"n\": \"v45\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s72\"}, {\"n\": \"v44\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s76\"}, {\"n\": \"v43\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s80\"}, {\"n\": \"v42\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s84\"}, {\"n\": \"v41\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s88\"}, {\"n\": \"v37\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s96\"}]}",
"{\"name\": \"disas_neon_data_insn\", \"code\": \"__int64 __fastcall disas_neon_data_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; unsigned int v3 ; __int64 result ; int v5 ; char * v6 ; char * v7 ; unsigned int @@v8@@ ; unsigned int v9 ; __int64 v10 ; __int64 @@v11@@ ; unsigned int @@v12@@ ; int v13 ; _BOOL4 v14 ; int v15 ; int v16 ; int v17 ; int v18 ; int v19 ; int v20 ; int v21 ; int v22 ; unsigned int v23 ; int v24 ; unsigned int v25 ; __int64 v26 ; __int64 v27 ; int v28 ; int v29 ; int v30 ; __int64 v31 ; int v32 ; unsigned int v33 ; unsigned int v34 ; unsigned int v35 ; int v36 ; unsigned int @@v37@@ ; unsigned int v38 ; unsigned int @@v39@@ ; unsigned int v40 ; bool @@v42@@ ; int @@v43@@ ; int @@v44@@ ; int @@v45@@ ; unsigned int v46 ; int i3 ; int v48 ; unsigned int v49 ; int v50 ; int v51 ; int v52 ; int v53 ; signed int v54 ; int i ; int v56 ; int j ; int i8 ; int i6 ; int i7 ; int i4 ; int i5 ; int i1 ; int nn ; int kk ; int ll ; int mm ; int k ; int l ; int n ; int ii ; int jj ; int @@v73@@ ; int @@v74@@ ; unsigned int v75 ; unsigned int v76 ; unsigned int v77 ; unsigned int v78 ; unsigned int v79 ; int @@i2@@ ; int @@m@@ ; unsigned int @@v82@@ ; int @@v83@@ ; unsigned int @@v84@@ ; int @@v85@@ ; int @@v86@@ ; unsigned int @@v87@@ ; unsigned int @@v88@@ ; unsigned int @@v89@@ ; unsigned int @@v90@@ ; int v91 ; int v92 ; int v93 ; int v94 ; int v95 ; unsigned int @@v96@@ ; int @@v97@@ ; int @@v98@@ ; int @@v99@@ ; int @@v100@@ ; unsigned int @@v101@@ ; int @@v102@@ ; int @@v103@@ ; __int64 v104 ; __int64 v105 ; __int64 v106 ; __int64 v107 ; __int64 v108 ; __int64 v109 ; __int64 v110 ; __int64 v111 ; __int64 v112 ; __int64 v113 ; __int64 v114 ; __int64 v115 ; __int64 v116 ; __int64 v117 ; __int64 v118 ; __int64 v119 ; __int64 v120 ; __int64 v121 ; __int64 v122 ; __int64 v123 ; __int64 v124 ; __int64 v125 ; __int64 v126 ; __int64 v127 ; __int64 v128 ; __int64 v129 ; __int64 v130 ; __int64 v131 ; __int64 v132 ; __int64 v133 ; __int64 v134 ; __int64 v135 ; __int64 v136 ; __int64 v137 ; __int64 v138 ; __int64 v139 ; __int64 v140 ; __int64 v141 ; __int64 v142 ; __int64 v143 ; __int64 v144 ; __int64 v145 ; __int64 v146 ; __int64 v147 ; __int64 v148 ; __int64 v149 ; __int64 v150 ; __int64 v151 ; __int64 v152 ; __int64 v153 ; __int64 v154 ; __int64 v155 ; __int64 v156 ; __int64 v157 ; __int64 v158 ; __int64 v159 ; __int64 v160 ; __int64 v161 ; __int64 v162 ; __int64 v163 ; __int64 v164 ; __int64 v165 ; __int64 v166 ; __int64 v167 ; __int64 v168 ; __int64 v169 ; __int64 v170 ; __int64 v171 ; __int64 @@v172@@ ; __int64 @@v173@@ ; unsigned __int64 @@v174@@ ; unsigned __int64 ( __fastcall * @@v175@@ ) ( __int64 , __int64 , __int64 , __int64 ) ; __int64 @@v176@@ ; unsigned __int64 ( __fastcall * @@v177@@ ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; __int64 v178 ; __int64 v179 ; __int64 @@v180@@ ; __int64 @@v181@@ ; __int64 @@v182@@ ; __int64 @@v183@@ ; __int64 @@v184@@ ; __int64 @@v185@@ ; __int64 @@v186@@ ; __int64 @@v187@@ ; __int64 @@v188@@ ; __int64 @@v189@@ ; __int64 @@v190@@ ; __int64 @@v191@@ ; __int64 @@v192@@ ; __int64 @@v193@@ ; __int64 @@v194@@ ; __int64 @@v195@@ ; __int64 @@v196@@ ; __int64 @@v197@@ ; __int64 @@v198@@ ; __int64 @@v199@@ ; __int64 @@v200@@ ; __int64 @@v201@@ ; __int64 @@v202@@ ; __int64 v203 ; __int64 v204 ; __int64 v205 ; __int64 v206 ; __int64 v207 ; __int64 @@v208@@ ; __int64 @@v209@@ ; __int64 @@v210@@ ; __int64 @@v211@@ ; __int64 @@v212@@ ; __int64 @@v213@@ ; __int64 @@v214@@ ; __int64 @@v215@@ ; __int64 @@v216@@ ; __int64 @@v217@@ ; __int64 @@v218@@ ; __int64 @@v219@@ ; __int64 @@v220@@ ; __int64 @@v221@@ ; __int64 @@v222@@ ; __int64 @@v223@@ ; __int64 @@v224@@ ; __int64 @@v225@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { v2 = * ( _DWORD * ) ( @@a1@@ + Number ) ; v3 = syn_simd_access_trap ( Number , Number , Number ) ; gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , v3 , v2 ) ; return Number L ; } if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) return Number L ; @@v85@@ = ( @@a2@@ & Number ) != Number ; @@v86@@ = HIBYTE ( @@a2@@ ) & Number ; if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v43@@ = ( ( unsigned __int16 ) @@a2@@ >> Number ) | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v43@@ = ( unsigned __int16 ) @@a2@@ >> Number ; } if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v44@@ = HIWORD ( @@a2@@ ) & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v44@@ = HIWORD ( @@a2@@ ) & Number ; } if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v45@@ = @@a2@@ & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v45@@ = @@a2@@ & Number ; } v46 = ( @@a2@@ >> Number ) & Number ; if ( ( @@a2@@ & Number ) != Number ) v5 = Number ; else v5 = Number ; @@v87@@ = v5 ; @@v88@@ = neon_reg_offset ( @@v43@@ , Number ) ; @@v89@@ = neon_reg_offset ( @@v44@@ , Number ) ; @@v90@@ = neon_reg_offset ( @@v45@@ , Number ) ; if ( ( @@a2@@ & Number ) == Number ) { v91 = ( @@a2@@ >> Number ) & Number | ( @@a2@@ >> Number ) & Number ; if ( ( ( ( int ) neon_3r_sizes [ v91 ] >> v46 ) & Number ) == Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number && ( ( ( unsigned __int8 ) @@v45@@ | ( unsigned __int8 ) ( @@v44@@ | @@v43@@ ) ) & Number ) != Number ) return Number L ; switch ( v91 ) { case Number : if ( @@v86@@ ) v6 = ( char * ) & uqadd_op ; else v6 = ( char * ) & sqadd_op ; goto LABEL_76 ; case Number : switch ( v46 | ( Number * @@v86@@ ) ) { case Number : tcg_gen_gvec_and ( Number L , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_andc ( Number L , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_or ( Number L , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_orc ( Number L , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_xor ( Number L , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_bitsel ( Number L , @@v88@@ , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_bitsel ( Number L , @@v88@@ , @@v90@@ , @@v89@@ , @@v88@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_bitsel ( Number L , @@v88@@ , @@v90@@ , @@v88@@ , @@v89@@ , @@v87@@ , @@v87@@ ) ; break ; default : return Number L ; } return Number L ; case Number : if ( @@v86@@ ) v6 = ( char * ) & uqsub_op ; else v6 = ( char * ) & sqsub_op ; LABEL_76 : tcg_gen_gvec_4 ( @@v88@@ , Number L , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ , & v6 [ Number * v46 ] ) ; return Number L ; case Number : @@v8@@ = @@v87@@ ; v9 = @@v90@@ ; v10 = @@v89@@ ; @@v11@@ = @@v88@@ ; if ( @@v86@@ ) @@v12@@ = Number ; else @@v12@@ = Number ; goto LABEL_95 ; case Number : @@v8@@ = @@v87@@ ; v9 = @@v90@@ ; v10 = @@v89@@ ; @@v11@@ = @@v88@@ ; if ( @@v86@@ ) @@v12@@ = Number ; else @@v12@@ = Number ; LABEL_95 : tcg_gen_gvec_cmp ( @@v12@@ , v46 , @@v11@@ , v10 , v9 , @@v8@@ , @@v87@@ ) ; return Number L ; case Number : if ( @@v86@@ ) tcg_gen_gvec_umax ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; else tcg_gen_gvec_smax ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : if ( @@v86@@ ) tcg_gen_gvec_umin ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; else tcg_gen_gvec_smin ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : if ( @@v86@@ ) tcg_gen_gvec_sub ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; else tcg_gen_gvec_add ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : if ( @@v86@@ ) tcg_gen_gvec_cmp ( Number L , v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; else tcg_gen_gvec_3 ( @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ , ( char * ) & cmtst_op + Number * ( int ) v46 ) ; return Number L ; case Number : if ( @@v86@@ ) v7 = ( char * ) & mls_op + Number * ( int ) v46 ; else v7 = ( char * ) & mla_op + Number * ( int ) v46 ; tcg_gen_gvec_3 ( @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ , v7 ) ; return Number L ; case Number : if ( @@v86@@ ) { if ( ! v46 ) goto LABEL_107 ; result = Number L ; } else { tcg_gen_gvec_mul ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; result = Number L ; } return result ; case Number : if ( ! @@v86@@ ) goto LABEL_107 ; if ( v46 == Number ) return do_v81_helper ( @@a1@@ , ( __int64 ) gen_helper_gvec_qrdmlah_s16 , @@v85@@ , @@v43@@ , @@v44@@ , @@v45@@ ) ; if ( v46 == Number ) return do_v81_helper ( @@a1@@ , ( __int64 ) gen_helper_gvec_qrdmlah_s32 , @@v85@@ , @@v43@@ , @@v44@@ , @@v45@@ ) ; return Number L ; case Number : if ( ( @@a2@@ & Number ) == Number ) return Number L ; if ( @@v86@@ ) { if ( ! isar_feature_aa32_sha2 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || v46 == Number ) return Number L ; v163 = vfp_reg_ptr ( Number , @@v43@@ ) ; v168 = vfp_reg_ptr ( Number , @@v44@@ ) ; @@v172@@ = vfp_reg_ptr ( Number , @@v45@@ ) ; if ( v46 == Number ) { gen_helper_crypto_sha256su1 ( v163 , v168 , @@v172@@ ) ; } else if ( v46 ) { gen_helper_crypto_sha256h2 ( v163 , v168 , @@v172@@ ) ; } else { gen_helper_crypto_sha256h ( v163 , v168 , @@v172@@ ) ; } } else { if ( ! isar_feature_aa32_sha1 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; v163 = vfp_reg_ptr ( Number , @@v43@@ ) ; v168 = vfp_reg_ptr ( Number , @@v44@@ ) ; @@v172@@ = vfp_reg_ptr ( Number , @@v45@@ ) ; v205 = tcg_const_i32 ( v46 ) ; gen_helper_crypto_sha1_3reg ( v163 , v168 , @@v172@@ , v205 ) ; tcg_temp_free_i32 ( v205 ) ; } tcg_temp_free_ptr ( v163 ) ; tcg_temp_free_ptr ( v168 ) ; tcg_temp_free_ptr ( @@v172@@ ) ; return Number L ; case Number : if ( @@v86@@ ) { if ( v46 == Number ) return do_v81_helper ( @@a1@@ , ( __int64 ) gen_helper_gvec_qrdmlsh_s16 , @@v85@@ , @@v43@@ , @@v44@@ , @@v45@@ ) ; if ( v46 == Number ) return do_v81_helper ( @@a1@@ , ( __int64 ) gen_helper_gvec_qrdmlsh_s32 , @@v85@@ , @@v43@@ , @@v44@@ , @@v45@@ ) ; return Number L ; } if ( v46 == Number ) return Number L ; LABEL_107 : if ( v46 == Number ) { for ( i = Number ; ; ++ i ) { v13 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v13 <= i ) break ; neon_load_reg64 ( cpu_V0 , i + @@v44@@ ) ; neon_load_reg64 ( cpu_V1 , i + @@v45@@ ) ; if ( v91 == Number ) { if ( @@v86@@ ) gen_helper_neon_qrshl_u64 ( cpu_V0 , cpu_env , cpu_V1 , cpu_V0 ) ; else gen_helper_neon_qrshl_s64 ( cpu_V0 , cpu_env , cpu_V1 , cpu_V0 ) ; } else { if ( v91 > Number ) goto LABEL_127 ; switch ( v91 ) { case Number : if ( @@v86@@ ) gen_helper_neon_rshl_u64 ( cpu_V0 , cpu_V1 , cpu_V0 ) ; else gen_helper_neon_rshl_s64 ( cpu_V0 , cpu_V1 , cpu_V0 ) ; break ; case Number : if ( @@v86@@ ) gen_helper_neon_shl_u64 ( cpu_V0 , cpu_V1 , cpu_V0 ) ; else gen_helper_neon_shl_s64 ( cpu_V0 , cpu_V1 , cpu_V0 ) ; break ; case Number : if ( @@v86@@ ) gen_helper_neon_qshl_u64 ( cpu_V0 , cpu_env , cpu_V1 , cpu_V0 ) ; else gen_helper_neon_qshl_s64 ( cpu_V0 , cpu_env , cpu_V1 , cpu_V0 ) ; break ; default : LABEL_127 : abort ( ) ; } } neon_store_reg64 ( cpu_V0 , i + @@v43@@ ) ; } return Number L ; } @@v74@@ = Number ; switch ( v91 ) { case Number : case Number : case Number : case Number : @@v103@@ = @@v44@@ ; @@v44@@ = @@v45@@ ; @@v45@@ = @@v103@@ ; goto LABEL_153 ; case Number : case Number : case Number : @@v74@@ = Number ; goto LABEL_153 ; case Number : if ( arm_dc_feature ( @@a1@@ , Number ) ) goto LABEL_153 ; return Number L ; case Number : v14 = @@v86@@ && ( ( @@a2@@ >> Number ) & Number ) <= Number ; @@v74@@ = v14 ; goto LABEL_153 ; case Number : if ( @@v86@@ || ! v46 ) goto LABEL_153 ; return Number L ; case Number : if ( @@v86@@ ) goto LABEL_153 ; return Number L ; case Number : @@v74@@ = HIBYTE ( @@a2@@ ) & Number ; goto LABEL_153 ; case Number : if ( ! @@v86@@ || arm_dc_feature ( @@a1@@ , Number ) ) goto LABEL_153 ; return Number L ; default : LABEL_153 : if ( @@v74@@ && ( @@a2@@ & Number ) != Number ) return Number L ; v56 = Number ; while ( Number ) { v16 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v16 <= v56 ) break ; if ( @@v74@@ ) { if ( v56 > Number ) { v104 = neon_load_reg ( @@v45@@ , Number ) ; v128 = neon_load_reg ( @@v45@@ , Number ) ; } else { v104 = neon_load_reg ( @@v44@@ , Number ) ; v128 = neon_load_reg ( @@v44@@ , Number ) ; } } else { v104 = neon_load_reg ( @@v44@@ , v56 ) ; v128 = neon_load_reg ( @@v45@@ , v56 ) ; } switch ( v91 ) { case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_hadd_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hadd_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hadd_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hadd_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hadd_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hadd_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_rhadd_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rhadd_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rhadd_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rhadd_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rhadd_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rhadd_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_hsub_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hsub_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hsub_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hsub_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hsub_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hsub_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_shl_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_shl_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_shl_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_shl_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_shl_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_shl_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_qshl_s8 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qshl_u8 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qshl_s16 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qshl_u16 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qshl_s32 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qshl_u32 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_rshl_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rshl_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rshl_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rshl_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rshl_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rshl_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_qrshl_s8 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qrshl_u8 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qrshl_s16 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qrshl_u16 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qrshl_s32 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qrshl_u32 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_abd_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_abd_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_abd_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_abd_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_abd_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_abd_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_abd_s8 ( v104 , v104 , v128 ) ; goto LABEL_235 ; case Number : gen_helper_neon_abd_u8 ( v104 , v104 , v128 ) ; goto LABEL_235 ; case Number : gen_helper_neon_abd_s16 ( v104 , v104 , v128 ) ; goto LABEL_235 ; case Number : gen_helper_neon_abd_u16 ( v104 , v104 , v128 ) ; goto LABEL_235 ; case Number : gen_helper_neon_abd_s32 ( v104 , v104 , v128 ) ; goto LABEL_235 ; case Number : gen_helper_neon_abd_u32 ( v104 , v104 , v128 ) ; LABEL_235 : tcg_temp_free_i32 ( v128 ) ; v128 = neon_load_reg ( @@v43@@ , v56 ) ; gen_neon_add ( v46 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : gen_helper_neon_mul_p8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_pmax_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmax_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmax_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmax_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : tcg_gen_smax_i32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : tcg_gen_umax_i32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_pmin_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmin_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmin_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmin_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : tcg_gen_smin_i32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : tcg_gen_umin_i32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : if ( @@v86@@ ) { if ( v46 == Number ) { gen_helper_neon_qrdmulh_s16 ( v104 , cpu_env , v104 , v128 ) ; } else { if ( v46 != Number ) abort ( ) ; gen_helper_neon_qrdmulh_s32 ( v104 , cpu_env , v104 , v128 ) ; } } else if ( v46 == Number ) { gen_helper_neon_qdmulh_s16 ( v104 , cpu_env , v104 , v128 ) ; } else { if ( v46 != Number ) abort ( ) ; gen_helper_neon_qdmulh_s32 ( v104 , cpu_env , v104 , v128 ) ; } goto LABEL_312 ; case Number : if ( v46 == Number ) { tcg_gen_add_i32 ( v104 , v104 , v128 ) ; } else if ( v46 ) { gen_helper_neon_padd_u16 ( v104 , v104 , v128 ) ; } else { gen_helper_neon_padd_u8 ( v104 , v104 , v128 ) ; } goto LABEL_312 ; case Number : @@v224@@ = get_fpstatus_ptr ( Number ) ; @@v225@@ = neon_load_reg ( @@v43@@ , v56 ) ; if ( v46 ) gen_helper_vfp_negs ( v104 , v104 ) ; gen_helper_vfp_muladds ( v104 , v104 , v128 , @@v225@@ , @@v224@@ ) ; tcg_temp_free_i32 ( @@v225@@ ) ; tcg_temp_free_ptr ( @@v224@@ ) ; goto LABEL_312 ; case Number : @@v223@@ = get_fpstatus_ptr ( Number ) ; v15 = v46 | ( Number * @@v86@@ ) ; if ( v15 == Number ) { gen_helper_neon_abd_f32 ( v104 , v104 , v128 , @@v223@@ ) ; } else { if ( v15 > Number ) goto LABEL_279 ; if ( v15 == Number ) goto LABEL_276 ; if ( v15 > Number ) goto LABEL_279 ; if ( ! v15 ) { LABEL_276 : gen_helper_vfp_adds ( v104 , v104 , v128 , @@v223@@ ) ; } else { if ( v15 != Number ) LABEL_279 : abort ( ) ; gen_helper_vfp_subs ( v104 , v104 , v128 , @@v223@@ ) ; } } tcg_temp_free_ptr ( @@v223@@ ) ; LABEL_312 : tcg_temp_free_i32 ( v128 ) ; if ( @@v74@@ && @@v43@@ == @@v45@@ ) neon_store_scratch ( v56 , v104 ) ; else neon_store_reg ( @@v43@@ , v56 , v104 ) ; ++ v56 ; break ; case Number : @@v222@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_muls ( v104 , v104 , v128 , @@v222@@ ) ; if ( ! @@v86@@ ) { tcg_temp_free_i32 ( v128 ) ; v128 = neon_load_reg ( @@v43@@ , v56 ) ; if ( v46 ) gen_helper_vfp_subs ( v104 , v128 , v104 , @@v222@@ ) ; else gen_helper_vfp_adds ( v104 , v104 , v128 , @@v222@@ ) ; } tcg_temp_free_ptr ( @@v222@@ ) ; goto LABEL_312 ; case Number : @@v221@@ = get_fpstatus_ptr ( Number ) ; if ( @@v86@@ ) { if ( v46 ) gen_helper_neon_cgt_f32 ( v104 , v104 , v128 , @@v221@@ ) ; else gen_helper_neon_cge_f32 ( v104 , v104 , v128 , @@v221@@ ) ; } else { gen_helper_neon_ceq_f32 ( v104 , v104 , v128 , @@v221@@ ) ; } tcg_temp_free_ptr ( @@v221@@ ) ; goto LABEL_312 ; case Number : @@v220@@ = get_fpstatus_ptr ( Number ) ; if ( v46 ) gen_helper_neon_acgt_f32 ( v104 , v104 , v128 , @@v220@@ ) ; else gen_helper_neon_acge_f32 ( v104 , v104 , v128 , @@v220@@ ) ; tcg_temp_free_ptr ( @@v220@@ ) ; goto LABEL_312 ; case Number : @@v219@@ = get_fpstatus_ptr ( Number ) ; if ( v46 ) gen_helper_vfp_mins ( v104 , v104 , v128 , @@v219@@ ) ; else gen_helper_vfp_maxs ( v104 , v104 , v128 , @@v219@@ ) ; tcg_temp_free_ptr ( @@v219@@ ) ; goto LABEL_312 ; case Number : if ( @@v86@@ ) { @@v218@@ = get_fpstatus_ptr ( Number ) ; if ( v46 ) gen_helper_vfp_minnums ( v104 , v104 , v128 , @@v218@@ ) ; else gen_helper_vfp_maxnums ( v104 , v104 , v128 , @@v218@@ ) ; tcg_temp_free_ptr ( @@v218@@ ) ; } else if ( v46 ) { gen_helper_rsqrts_f32 ( v104 , v104 , v128 , cpu_env ) ; } else { gen_helper_recps_f32 ( v104 , v104 , v128 , cpu_env ) ; } goto LABEL_312 ; default : abort ( ) ; } } if ( @@v74@@ && @@v43@@ == @@v45@@ ) { for ( j = Number ; ; ++ j ) { v17 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v17 <= j ) break ; v105 = neon_load_scratch ( j ) ; neon_store_reg ( @@v43@@ , j , v105 ) ; } } break ; } break ; default : goto LABEL_107 ; } return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { if ( v46 == Number ) { LABEL_722 : if ( @@v86@@ ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) return Number L ; if ( ( @@a2@@ & Number ) == Number || ( @@a2@@ & Number ) != Number && ( @@v43@@ & Number ) != Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { @@v84@@ = Number ; @@v83@@ = ( @@a2@@ >> Number ) & Number ; } else if ( ( @@a2@@ & Number ) != Number ) { @@v84@@ = Number ; @@v83@@ = ( @@a2@@ >> Number ) & Number ; } else { @@v84@@ = Number ; @@v83@@ = ( @@a2@@ >> Number ) & Number ; } if ( ( @@a2@@ & Number ) != Number ) @@v37@@ = Number ; else @@v37@@ = Number ; if ( ( @@a2@@ & Number ) != Number ) v38 = Number ; else v38 = Number ; @@v39@@ = neon_element_offset ( @@v45@@ , @@v83@@ , @@v84@@ ) ; v40 = neon_reg_offset ( @@v43@@ , Number ) ; tcg_gen_gvec_dup_mem ( @@v84@@ , v40 , @@v39@@ , v38 , @@v37@@ ) ; } else { if ( ( int ) ( @@v44@@ + ( ( @@a2@@ >> Number ) & Number ) + Number ) > Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { v126 = neon_load_reg ( @@v43@@ , Number ) ; } else { v126 = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( v126 , Number ) ; } v153 = neon_load_reg ( @@v45@@ , Number ) ; v167 = vfp_reg_ptr ( Number , @@v44@@ ) ; v179 = tcg_const_i32 ( Number * ( ( ( @@a2@@ >> Number ) & Number ) + Number ) ) ; gen_helper_neon_tbl ( v153 , v153 , v126 , v167 , v179 ) ; tcg_temp_free_i32 ( v126 ) ; if ( ( @@a2@@ & Number ) != Number ) { v127 = neon_load_reg ( @@v43@@ , Number ) ; } else { v127 = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( v127 , Number ) ; } v162 = neon_load_reg ( @@v45@@ , Number ) ; gen_helper_neon_tbl ( v162 , v162 , v127 , v167 , v179 ) ; tcg_temp_free_i32 ( v179 ) ; tcg_temp_free_ptr ( v167 ) ; neon_store_reg ( @@v43@@ , Number , v153 ) ; neon_store_reg ( @@v43@@ , Number , v162 ) ; tcg_temp_free_i32 ( v127 ) ; } } else { v95 = ( @@a2@@ >> Number ) & Number | ( @@a2@@ >> Number ) & Number ; v49 = ( @@a2@@ >> Number ) & Number ; if ( ( ( ( int ) neon_2rm_sizes [ v95 ] >> ( ( @@a2@@ >> Number ) & Number ) ) & Number ) == Number ) return Number L ; if ( neon_2rm_is_v8_op ( v95 ) && ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( v95 != Number && v95 != Number && ( @@a2@@ & Number ) != Number && ( ( ( unsigned __int8 ) @@v43@@ | ( unsigned __int8 ) @@v45@@ ) & Number ) != Number ) return Number L ; switch ( v95 ) { case Number : for ( k = Number ; ; ++ k ) { v30 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v30 <= k ) break ; v117 = neon_load_reg ( @@v45@@ , Number * k ) ; v137 = neon_load_reg ( @@v45@@ , Number * k + Number ) ; if ( v49 != Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_swap_half ( v117 ) ; else tcg_gen_bswap32_i32 ( v117 , v117 ) ; } neon_store_reg ( @@v43@@ , Number * k + Number , v117 ) ; if ( v49 != Number ) { if ( v49 ) gen_swap_half ( v137 ) ; else tcg_gen_bswap32_i32 ( v137 , v137 ) ; } neon_store_reg ( @@v43@@ , Number * k , v137 ) ; } return Number L ; case Number : case Number : case Number : case Number : for ( l = Number ; l < @@v85@@ + Number ; ++ l ) { v31 = neon_load_reg ( @@v45@@ , Number * l ) ; gen_neon_widen ( cpu_V0 , v31 , v49 , v95 & Number ) ; v118 = neon_load_reg ( @@v45@@ , Number * l + Number ) ; gen_neon_widen ( cpu_V1 , v118 , v49 , v95 & Number ) ; if ( v49 == Number ) { tcg_gen_add_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_paddl_u32 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; else gen_helper_neon_paddl_u16 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; } if ( v95 > Number ) { neon_load_reg64 ( cpu_V1 , l + @@v43@@ ) ; gen_neon_addl ( v49 ) ; } neon_store_reg64 ( cpu_V0 , l + @@v43@@ ) ; } return Number L ; case Number : case Number : if ( ! isar_feature_aa32_aes ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ( ( ( unsigned __int8 ) @@v43@@ | ( unsigned __int8 ) @@v45@@ ) & Number ) != Number ) { return Number L ; } v164 = vfp_reg_ptr ( Number , @@v43@@ ) ; v169 = vfp_reg_ptr ( Number , @@v45@@ ) ; v33 = extract32 ( @@a2@@ , Number , Number ) ; v161 = tcg_const_i32 ( v33 ) ; if ( v95 == Number ) gen_helper_crypto_aese ( v164 , v169 , v161 ) ; else gen_helper_crypto_aesmc ( v164 , v169 , v161 ) ; tcg_temp_free_ptr ( v164 ) ; tcg_temp_free_ptr ( v169 ) ; tcg_temp_free_i32 ( v161 ) ; return Number L ; case Number : tcg_gen_gvec_not ( Number L , @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : if ( ! isar_feature_aa32_sha1 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ( ( ( unsigned __int8 ) @@v43@@ | ( unsigned __int8 ) @@v45@@ ) & Number ) != Number ) { return Number L ; } v165 = vfp_reg_ptr ( Number , @@v43@@ ) ; v170 = vfp_reg_ptr ( Number , @@v45@@ ) ; gen_helper_crypto_sha1h ( v165 , v170 ) ; tcg_temp_free_ptr ( v165 ) ; tcg_temp_free_ptr ( v170 ) ; return Number L ; case Number : tcg_gen_gvec_abs ( v49 , @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : tcg_gen_gvec_neg ( v49 , @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : if ( v49 != Number ) goto LABEL_853 ; for ( @@m@@ = Number ; ; @@m@@ += Number ) { v32 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v32 <= @@m@@ ) break ; v119 = neon_load_reg ( @@v45@@ , @@m@@ ) ; v138 = neon_load_reg ( @@v43@@ , @@m@@ + Number ) ; neon_store_reg ( @@v45@@ , @@m@@ , v138 ) ; neon_store_reg ( @@v43@@ , @@m@@ + Number , v119 ) ; } return Number L ; case Number : return ( unsigned int ) gen_neon_unzip ( @@v43@@ , @@v45@@ , v49 , @@v85@@ ) != Number ; case Number : return ( unsigned int ) gen_neon_zip ( @@v43@@ , @@v45@@ , v49 , @@v85@@ ) != Number ; case Number : case Number : if ( ( @@v45@@ & Number ) != Number ) return Number L ; v139 = Number L ; for ( n = Number ; n <= Number ; ++ n ) { neon_load_reg64 ( cpu_V0 , n + @@v45@@ ) ; v120 = tcg_temp_new_i32 ( ) ; gen_neon_narrow_op ( v95 == Number , @@v85@@ , v49 , v120 , cpu_V0 ) ; if ( n ) { neon_store_reg ( @@v43@@ , Number , v139 ) ; neon_store_reg ( @@v43@@ , Number , v120 ) ; } else { v139 = v120 ; } } return Number L ; case Number : if ( ( @@a2@@ & Number ) != Number || ( @@v43@@ & Number ) != Number ) return Number L ; v121 = neon_load_reg ( @@v45@@ , Number ) ; v140 = neon_load_reg ( @@v45@@ , Number ) ; for ( ii = Number ; ii <= Number ; ++ ii ) { if ( ii == Number ) v121 = v140 ; gen_neon_widen ( cpu_V0 , v121 , v49 , Number ) ; tcg_gen_shli_i64 ( cpu_V0 , cpu_V0 , Number << v49 ) ; neon_store_reg64 ( cpu_V0 , ii + @@v43@@ ) ; } return Number L ; case Number : if ( ( ( ( unsigned __int8 ) @@v43@@ | ( unsigned __int8 ) @@v45@@ ) & Number ) != Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { if ( ! isar_feature_aa32_sha2 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; } else if ( ! isar_feature_aa32_sha1 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) { return Number L ; } v166 = vfp_reg_ptr ( Number , @@v43@@ ) ; v171 = vfp_reg_ptr ( Number , @@v45@@ ) ; if ( ( @@a2@@ & Number ) != Number ) gen_helper_crypto_sha256su0 ( v166 , v171 ) ; else gen_helper_crypto_sha1su1 ( v166 , v171 ) ; tcg_temp_free_ptr ( v166 ) ; tcg_temp_free_ptr ( v171 ) ; return Number L ; case Number : if ( ! isar_feature_aa32_fp16_spconv ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ( @@a2@@ & Number ) != Number || ( @@v45@@ & Number ) != Number ) return Number L ; @@v182@@ = get_fpstatus_ptr ( Number ) ; @@v183@@ = get_ahp_flag ( ) ; v122 = neon_load_reg ( @@v45@@ , Number ) ; gen_helper_vfp_fcvt_f32_to_f16 ( v122 , v122 , @@v182@@ , @@v183@@ ) ; v141 = neon_load_reg ( @@v45@@ , Number ) ; gen_helper_vfp_fcvt_f32_to_f16 ( v141 , v141 , @@v182@@ , @@v183@@ ) ; tcg_gen_shli_i32 ( v141 , v141 , Number L ) ; tcg_gen_or_i32 ( v141 , v141 , v122 ) ; tcg_temp_free_i32 ( v122 ) ; v123 = neon_load_reg ( @@v45@@ , Number ) ; gen_helper_vfp_fcvt_f32_to_f16 ( v123 , v123 , @@v182@@ , @@v183@@ ) ; v158 = neon_load_reg ( @@v45@@ , Number ) ; neon_store_reg ( @@v43@@ , Number , v141 ) ; gen_helper_vfp_fcvt_f32_to_f16 ( v158 , v158 , @@v182@@ , @@v183@@ ) ; tcg_gen_shli_i32 ( v158 , v158 , Number L ) ; tcg_gen_or_i32 ( v158 , v158 , v123 ) ; neon_store_reg ( @@v43@@ , Number , v158 ) ; tcg_temp_free_i32 ( v123 ) ; tcg_temp_free_i32 ( @@v183@@ ) ; tcg_temp_free_ptr ( @@v182@@ ) ; return Number L ; case Number : if ( ! isar_feature_aa32_fp16_spconv ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ( @@a2@@ & Number ) != Number || ( @@v43@@ & Number ) != Number ) return Number L ; @@v180@@ = get_fpstatus_ptr ( Number ) ; @@v181@@ = get_ahp_flag ( ) ; v159 = tcg_temp_new_i32 ( ) ; v124 = neon_load_reg ( @@v45@@ , Number ) ; v142 = neon_load_reg ( @@v45@@ , Number ) ; tcg_gen_ext16u_i32 ( v159 , v124 ) ; gen_helper_vfp_fcvt_f16_to_f32 ( v159 , v159 , @@v180@@ , @@v181@@ ) ; neon_store_reg ( @@v43@@ , Number , v159 ) ; tcg_gen_shri_i32 ( v124 , v124 , Number L ) ; gen_helper_vfp_fcvt_f16_to_f32 ( v124 , v124 , @@v180@@ , @@v181@@ ) ; neon_store_reg ( @@v43@@ , Number , v124 ) ; v160 = tcg_temp_new_i32 ( ) ; tcg_gen_ext16u_i32 ( v160 , v142 ) ; gen_helper_vfp_fcvt_f16_to_f32 ( v160 , v160 , @@v180@@ , @@v181@@ ) ; neon_store_reg ( @@v43@@ , Number , v160 ) ; tcg_gen_shri_i32 ( v142 , v142 , Number L ) ; gen_helper_vfp_fcvt_f16_to_f32 ( v142 , v142 , @@v180@@ , @@v181@@ ) ; neon_store_reg ( @@v43@@ , Number , v142 ) ; tcg_temp_free_i32 ( @@v181@@ ) ; tcg_temp_free_ptr ( @@v180@@ ) ; break ; default : LABEL_853 : for ( jj = Number ; ; ++ jj ) { v36 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v36 <= jj ) break ; v125 = neon_load_reg ( @@v45@@ , jj ) ; switch ( v95 ) { case Number : if ( v49 ) { if ( v49 != Number ) abort ( ) ; gen_swap_half ( v125 ) ; } else { tcg_gen_bswap32_i32 ( v125 , v125 ) ; } break ; case Number : gen_rev16 ( v125 , v125 ) ; break ; case Number : if ( v49 == Number ) { gen_helper_neon_cls_s32 ( v125 , v125 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_cls_s16 ( v125 , v125 ) ; else gen_helper_neon_cls_s8 ( v125 , v125 ) ; } break ; case Number : if ( v49 == Number ) { tcg_gen_clzi_i32 ( v125 , v125 , Number L ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_clz_u16 ( v125 , v125 ) ; else gen_helper_neon_clz_u8 ( v125 , v125 ) ; } break ; case Number : gen_helper_neon_cnt_u8 ( v125 , v125 ) ; break ; case Number : if ( v49 == Number ) { gen_helper_neon_qabs_s32 ( v125 , cpu_env , v125 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_qabs_s16 ( v125 , cpu_env , v125 ) ; else gen_helper_neon_qabs_s8 ( v125 , cpu_env , v125 ) ; } break ; case Number : if ( v49 == Number ) { gen_helper_neon_qneg_s32 ( v125 , cpu_env , v125 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_qneg_s16 ( v125 , cpu_env , v125 ) ; else gen_helper_neon_qneg_s8 ( v125 , cpu_env , v125 ) ; } break ; case Number : case Number : v143 = tcg_const_i32 ( Number L ) ; if ( v49 == Number ) { gen_helper_neon_cgt_s32 ( v125 , v125 , v143 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_cgt_s16 ( v125 , v125 , v143 ) ; else gen_helper_neon_cgt_s8 ( v125 , v125 , v143 ) ; } tcg_temp_free_i32 ( v143 ) ; if ( v95 == Number ) goto LABEL_898 ; break ; case Number : case Number : v144 = tcg_const_i32 ( Number L ) ; if ( v49 == Number ) { gen_helper_neon_cge_s32 ( v125 , v125 , v144 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_cge_s16 ( v125 , v125 , v144 ) ; else gen_helper_neon_cge_s8 ( v125 , v125 , v144 ) ; } tcg_temp_free_i32 ( v144 ) ; if ( v95 == Number ) LABEL_898 : tcg_gen_not_i32 ( v125 , v125 ) ; break ; case Number : v145 = tcg_const_i32 ( Number L ) ; if ( v49 == Number ) { gen_helper_neon_ceq_u32 ( v125 , v125 , v145 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_ceq_u16 ( v125 , v125 , v145 ) ; else gen_helper_neon_ceq_u8 ( v125 , v125 , v145 ) ; } tcg_temp_free_i32 ( v145 ) ; break ; case Number : @@v202@@ = get_fpstatus_ptr ( Number ) ; v146 = tcg_const_i32 ( Number L ) ; gen_helper_neon_cgt_f32 ( v125 , v125 , v146 , @@v202@@ ) ; tcg_temp_free_i32 ( v146 ) ; tcg_temp_free_ptr ( @@v202@@ ) ; break ; case Number : @@v201@@ = get_fpstatus_ptr ( Number ) ; v147 = tcg_const_i32 ( Number L ) ; gen_helper_neon_cge_f32 ( v125 , v125 , v147 , @@v201@@ ) ; tcg_temp_free_i32 ( v147 ) ; tcg_temp_free_ptr ( @@v201@@ ) ; break ; case Number : @@v200@@ = get_fpstatus_ptr ( Number ) ; v148 = tcg_const_i32 ( Number L ) ; gen_helper_neon_ceq_f32 ( v125 , v125 , v148 , @@v200@@ ) ; tcg_temp_free_i32 ( v148 ) ; tcg_temp_free_ptr ( @@v200@@ ) ; break ; case Number : @@v199@@ = get_fpstatus_ptr ( Number ) ; v149 = tcg_const_i32 ( Number L ) ; gen_helper_neon_cge_f32 ( v125 , v149 , v125 , @@v199@@ ) ; tcg_temp_free_i32 ( v149 ) ; tcg_temp_free_ptr ( @@v199@@ ) ; break ; case Number : @@v198@@ = get_fpstatus_ptr ( Number ) ; v150 = tcg_const_i32 ( Number L ) ; gen_helper_neon_cgt_f32 ( v125 , v150 , v125 , @@v198@@ ) ; tcg_temp_free_i32 ( v150 ) ; tcg_temp_free_ptr ( @@v198@@ ) ; break ; case Number : gen_helper_vfp_abss ( v125 , v125 ) ; break ; case Number : gen_helper_vfp_negs ( v125 , v125 ) ; break ; case Number : v151 = neon_load_reg ( @@v43@@ , jj ) ; neon_store_reg ( @@v45@@ , jj , v151 ) ; break ; case Number : v152 = neon_load_reg ( @@v43@@ , jj ) ; if ( v49 ) { if ( v49 != Number ) abort ( ) ; gen_neon_trn_u16 ( v125 , v152 ) ; } else { gen_neon_trn_u8 ( v125 , v152 ) ; } neon_store_reg ( @@v45@@ , jj , v152 ) ; break ; case Number : case Number : case Number : case Number : case Number : @@v196@@ = get_fpstatus_ptr ( Number ) ; if ( v95 == Number ) @@v82@@ = Number ; else @@v82@@ = fp_decode_rm [ ( v95 >> Number ) & Number ^ Number ] ; v34 = arm_rmode_to_sf ( @@v82@@ ) ; @@v197@@ = tcg_const_i32 ( v34 ) ; gen_helper_set_neon_rmode ( @@v197@@ , @@v197@@ , cpu_env ) ; gen_helper_rints ( v125 , v125 , @@v196@@ ) ; gen_helper_set_neon_rmode ( @@v197@@ , @@v197@@ , cpu_env ) ; tcg_temp_free_ptr ( @@v196@@ ) ; tcg_temp_free_i32 ( @@v197@@ ) ; break ; case Number : @@v195@@ = get_fpstatus_ptr ( Number ) ; gen_helper_rints_exact ( v125 , v125 , @@v195@@ ) ; tcg_temp_free_ptr ( @@v195@@ ) ; break ; case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : @@v42@@ = ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) == Number ; @@v192@@ = get_fpstatus_ptr ( Number ) ; @@v96@@ = fp_decode_rm [ ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ] ; @@v193@@ = tcg_const_i32 ( Number L ) ; v35 = arm_rmode_to_sf ( @@v96@@ ) ; @@v194@@ = tcg_const_i32 ( v35 ) ; gen_helper_set_neon_rmode ( @@v194@@ , @@v194@@ , cpu_env ) ; if ( @@v42@@ ) gen_helper_vfp_tosls ( v125 , v125 , @@v193@@ , @@v192@@ ) ; else gen_helper_vfp_touls ( v125 , v125 , @@v193@@ , @@v192@@ ) ; gen_helper_set_neon_rmode ( @@v194@@ , @@v194@@ , cpu_env ) ; tcg_temp_free_i32 ( @@v194@@ ) ; tcg_temp_free_i32 ( @@v193@@ ) ; tcg_temp_free_ptr ( @@v192@@ ) ; break ; case Number : @@v191@@ = get_fpstatus_ptr ( Number ) ; gen_helper_recpe_u32 ( v125 , v125 , @@v191@@ ) ; tcg_temp_free_ptr ( @@v191@@ ) ; break ; case Number : @@v190@@ = get_fpstatus_ptr ( Number ) ; gen_helper_rsqrte_u32 ( v125 , v125 , @@v190@@ ) ; tcg_temp_free_ptr ( @@v190@@ ) ; break ; case Number : @@v189@@ = get_fpstatus_ptr ( Number ) ; gen_helper_recpe_f32 ( v125 , v125 , @@v189@@ ) ; tcg_temp_free_ptr ( @@v189@@ ) ; break ; case Number : @@v188@@ = get_fpstatus_ptr ( Number ) ; gen_helper_rsqrte_f32 ( v125 , v125 , @@v188@@ ) ; tcg_temp_free_ptr ( @@v188@@ ) ; break ; case Number : @@v187@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_sitos ( v125 , v125 , @@v187@@ ) ; tcg_temp_free_ptr ( @@v187@@ ) ; break ; case Number : @@v186@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_uitos ( v125 , v125 , @@v186@@ ) ; tcg_temp_free_ptr ( @@v186@@ ) ; break ; case Number : @@v185@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_tosizs ( v125 , v125 , @@v185@@ ) ; tcg_temp_free_ptr ( @@v185@@ ) ; break ; case Number : @@v184@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_touizs ( v125 , v125 , @@v184@@ ) ; tcg_temp_free_ptr ( @@v184@@ ) ; break ; default : abort ( ) ; } neon_store_reg ( @@v43@@ , jj , v125 ) ; } return Number L ; } } } else { v79 = ( @@a2@@ >> Number ) & Number ; if ( v79 > Number && ( @@a2@@ & Number ) == Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number && ( ( ( unsigned __int8 ) @@v45@@ | ( unsigned __int8 ) ( @@v44@@ | @@v43@@ ) ) & Number ) != Number ) return Number L ; if ( v79 ) { if ( v79 == Number ) { neon_load_reg64 ( cpu_V0 , @@v44@@ + Number ) ; if ( ( @@a2@@ & Number ) != Number ) neon_load_reg64 ( cpu_V1 , @@v45@@ ) ; } else if ( ( @@a2@@ & Number ) != Number ) { v204 = tcg_temp_new_i64 ( ) ; if ( v79 > Number ) { neon_load_reg64 ( cpu_V0 , @@v44@@ + Number ) ; neon_load_reg64 ( v204 , @@v45@@ ) ; } else { neon_load_reg64 ( cpu_V0 , @@v44@@ ) ; neon_load_reg64 ( v204 , @@v44@@ + Number ) ; } tcg_gen_shri_i64 ( cpu_V0 , cpu_V0 , Number * ( BYTE1 ( @@a2@@ ) & Number ) ) ; tcg_gen_shli_i64 ( cpu_V1 , v204 , Number * ( Number - ( BYTE1 ( @@a2@@ ) & Number ) ) ) ; tcg_gen_or_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; if ( v79 > Number ) { neon_load_reg64 ( cpu_V1 , @@v45@@ + Number ) ; v79 -= Number ; } else { neon_load_reg64 ( cpu_V1 , @@v45@@ ) ; } tcg_gen_shli_i64 ( cpu_V1 , cpu_V1 , Number * ( Number - v79 ) ) ; tcg_gen_shri_i64 ( v204 , v204 , Number * v79 ) ; tcg_gen_or_i64 ( cpu_V1 , cpu_V1 , v204 ) ; tcg_temp_free_i64 ( v204 ) ; } else { neon_load_reg64 ( cpu_V0 , @@v44@@ ) ; tcg_gen_shri_i64 ( cpu_V0 , cpu_V0 , Number * v79 ) ; neon_load_reg64 ( cpu_V1 , @@v45@@ ) ; tcg_gen_shli_i64 ( cpu_V1 , cpu_V1 , Number * ( Number - v79 ) ) ; tcg_gen_or_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; } } else { neon_load_reg64 ( cpu_V0 , @@v44@@ ) ; if ( ( @@a2@@ & Number ) != Number ) neon_load_reg64 ( cpu_V1 , @@v44@@ + Number ) ; } neon_store_reg64 ( cpu_V0 , @@v43@@ ) ; if ( ( @@a2@@ & Number ) != Number ) neon_store_reg64 ( cpu_V1 , @@v43@@ + Number ) ; } return Number L ; } v94 = ( @@a2@@ >> Number ) & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( ! v46 ) return Number L ; switch ( v94 ) { case Number : case Number : case Number : case Number : case Number : goto LABEL_645 ; case Number : case Number : case Number : if ( v46 == Number ) return Number L ; LABEL_645 : if ( @@v86@@ && ( ( ( unsigned __int8 ) @@v44@@ | ( unsigned __int8 ) @@v43@@ ) & Number ) != Number ) return Number L ; v113 = neon_get_scalar ( v46 , @@v45@@ ) ; neon_store_scratch ( Number , v113 ) ; for ( kk = Number ; ; ++ kk ) { v28 = @@v86@@ ? Number : Number ; if ( v28 <= kk ) break ; v114 = neon_load_scratch ( Number ) ; v134 = neon_load_reg ( @@v44@@ , kk ) ; if ( v94 == Number ) { if ( v46 == Number ) gen_helper_neon_qdmulh_s16 ( v114 , cpu_env , v114 , v134 ) ; else gen_helper_neon_qdmulh_s32 ( v114 , cpu_env , v114 , v134 ) ; } else if ( v94 == Number ) { if ( v46 == Number ) gen_helper_neon_qrdmulh_s16 ( v114 , cpu_env , v114 , v134 ) ; else gen_helper_neon_qrdmulh_s32 ( v114 , cpu_env , v114 , v134 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { @@v208@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_muls ( v114 , v114 , v134 , @@v208@@ ) ; tcg_temp_free_ptr ( @@v208@@ ) ; } else if ( v46 == Number ) { tcg_gen_mul_i32 ( v114 , v114 , v134 ) ; } else { gen_helper_neon_mul_u16 ( v114 , v114 , v134 ) ; } tcg_temp_free_i32 ( v134 ) ; if ( ( ( @@a2@@ >> Number ) & Number ) <= Number ) { v135 = neon_load_reg ( @@v43@@ , kk ) ; if ( v94 == Number ) { @@v209@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_subs ( v114 , v135 , v114 , @@v209@@ ) ; tcg_temp_free_ptr ( @@v209@@ ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) > Number ) goto LABEL_673 ; if ( v94 == Number ) { gen_neon_rsb ( v46 , v114 , v135 ) ; } else if ( v94 ) { if ( v94 != Number ) LABEL_673 : abort ( ) ; @@v210@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_adds ( v114 , v114 , v135 , @@v210@@ ) ; tcg_temp_free_ptr ( @@v210@@ ) ; } else { gen_neon_add ( v46 , v114 , v135 ) ; } } tcg_temp_free_i32 ( v135 ) ; } neon_store_reg ( @@v43@@ , kk , v114 ) ; } break ; case Number : case Number : case Number : goto LABEL_683 ; case Number : case Number : case Number : if ( @@v86@@ == Number ) return Number L ; LABEL_683 : if ( ( @@v43@@ & Number ) != Number ) return Number L ; v136 = neon_get_scalar ( v46 , @@v45@@ ) ; v207 = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( v207 , v136 ) ; v156 = neon_load_reg ( @@v44@@ , Number ) ; for ( ll = Number ; ll <= Number ; ++ ll ) { if ( ll ) { v136 = v207 ; gen_neon_mull ( cpu_V0 , v156 , v207 , v46 , @@v86@@ ) ; } else { v115 = neon_load_reg ( @@v44@@ , Number ) ; gen_neon_mull ( cpu_V0 , v115 , v136 , v46 , @@v86@@ ) ; } if ( v94 != Number ) neon_load_reg64 ( cpu_V1 , ll + @@v43@@ ) ; switch ( v94 ) { case Number : goto LABEL_693 ; case Number : case Number : gen_neon_addl_saturate ( cpu_V0 , cpu_V0 , v46 ) ; if ( v94 == Number ) gen_neon_negl ( cpu_V0 , v46 ) ; gen_neon_addl_saturate ( cpu_V0 , cpu_V1 , v46 ) ; break ; case Number : gen_neon_negl ( cpu_V0 , v46 ) ; LABEL_693 : gen_neon_addl ( v46 ) ; break ; case Number : break ; case Number : gen_neon_addl_saturate ( cpu_V0 , cpu_V0 , v46 ) ; break ; default : abort ( ) ; } neon_store_reg64 ( cpu_V0 , ll + @@v43@@ ) ; } return Number L ; case Number : case Number : if ( ! isar_feature_aa32_rdm ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v86@@ && ( ( ( unsigned __int8 ) @@v44@@ | ( unsigned __int8 ) @@v43@@ ) & Number ) != Number ) return Number L ; if ( v94 == Number ) { if ( v46 == Number ) @@v177@@ = gen_helper_neon_qrdmlah_s16 ; else @@v177@@ = gen_helper_neon_qrdmlah_s32 ; } else if ( v46 == Number ) { @@v177@@ = gen_helper_neon_qrdmlsh_s16 ; } else { @@v177@@ = gen_helper_neon_qrdmlsh_s32 ; } v131 = neon_get_scalar ( v46 , @@v45@@ ) ; for ( mm = Number ; ; ++ mm ) { v29 = @@v86@@ ? Number : Number ; if ( v29 <= mm ) break ; v116 = neon_load_reg ( @@v44@@ , mm ) ; v157 = neon_load_reg ( @@v43@@ , mm ) ; @@v177@@ ( v116 , cpu_env , v116 , v131 , v157 ) ; tcg_temp_free_i32 ( v157 ) ; neon_store_reg ( @@v43@@ , mm , v116 ) ; } goto LABEL_468 ; default : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; goto LABEL_722 ; } return Number L ; } @@v97@@ = * ( ( _DWORD * ) & neon_3reg_wide_56205 + Number * v94 ) ; @@v98@@ = * ( ( _DWORD * ) & unk_4E484 + Number * v94 ) ; @@v99@@ = * ( ( _DWORD * ) & unk_4E488 + Number * v94 ) ; @@v100@@ = dword_4E48C [ Number * v94 ] ; if ( ( ( @@v100@@ >> v46 ) & Number ) != Number || ( @@v100@@ & Number ) != Number && @@v86@@ ) return Number L ; if ( @@v98@@ && ( @@v44@@ & Number ) != Number || @@v99@@ && ( @@v45@@ & Number ) != Number || ! @@v99@@ && ( @@v43@@ & Number ) != Number ) return Number L ; if ( v94 == Number && v46 == Number ) { if ( ! isar_feature_aa32_pmull ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v211@@ = tcg_temp_new_i64 ( ) ; @@v212@@ = tcg_temp_new_i64 ( ) ; @@v213@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v211@@ , @@v44@@ ) ; neon_load_reg64 ( @@v212@@ , @@v45@@ ) ; gen_helper_neon_pmull_64_lo ( @@v213@@ , @@v211@@ , @@v212@@ ) ; neon_store_reg64 ( @@v213@@ , @@v43@@ ) ; gen_helper_neon_pmull_64_hi ( @@v213@@ , @@v211@@ , @@v212@@ ) ; neon_store_reg64 ( @@v213@@ , @@v43@@ + Number ) ; tcg_temp_free_i64 ( @@v211@@ ) ; tcg_temp_free_i64 ( @@v212@@ ) ; tcg_temp_free_i64 ( @@v213@@ ) ; return Number L ; } if ( @@v43@@ != @@v45@@ || @@v99@@ ) { if ( @@v43@@ == @@v44@@ && ! @@v98@@ ) { v27 = neon_load_reg ( @@v44@@ , Number ) ; neon_store_scratch ( Number , v27 ) ; } } else { v26 = neon_load_reg ( @@v45@@ , Number ) ; neon_store_scratch ( Number , v26 ) ; } v155 = Number L ; for ( nn = Number ; ; ++ nn ) { if ( nn > Number ) return Number L ; if ( @@v98@@ ) { neon_load_reg64 ( cpu_V0 , nn + @@v44@@ ) ; v111 = Number L ; } else { if ( nn == Number && @@v43@@ == @@v44@@ ) v111 = neon_load_scratch ( Number ) ; else v111 = neon_load_reg ( @@v44@@ , nn ) ; if ( @@v97@@ ) gen_neon_widen ( cpu_V0 , v111 , v46 , @@v86@@ ) ; } if ( @@v99@@ ) { neon_load_reg64 ( cpu_V1 , nn + @@v45@@ ) ; v133 = Number L ; } else { if ( nn == Number && @@v43@@ == @@v45@@ ) v133 = neon_load_scratch ( Number ) ; else v133 = neon_load_reg ( @@v45@@ , nn ) ; if ( @@v97@@ ) gen_neon_widen ( cpu_V1 , v133 , v46 , @@v86@@ ) ; } switch ( v94 ) { case Number : case Number : case Number : gen_neon_addl ( v46 ) ; break ; case Number : case Number : case Number : gen_neon_subl ( v46 ) ; break ; case Number : case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_abdl_s16 ( cpu_V0 , v111 , v133 ) ; break ; case Number : gen_helper_neon_abdl_u16 ( cpu_V0 , v111 , v133 ) ; break ; case Number : gen_helper_neon_abdl_s32 ( cpu_V0 , v111 , v133 ) ; break ; case Number : gen_helper_neon_abdl_u32 ( cpu_V0 , v111 , v133 ) ; break ; case Number : gen_helper_neon_abdl_s64 ( cpu_V0 , v111 , v133 ) ; break ; case Number : gen_helper_neon_abdl_u64 ( cpu_V0 , v111 , v133 ) ; break ; default : abort ( ) ; } tcg_temp_free_i32 ( v133 ) ; tcg_temp_free_i32 ( v111 ) ; break ; case Number : case Number : case Number : case Number : case Number : case Number : gen_neon_mull ( cpu_V0 , v111 , v133 , v46 , @@v86@@ ) ; break ; case Number : gen_helper_neon_mull_p8 ( cpu_V0 , v111 , v133 ) ; tcg_temp_free_i32 ( v133 ) ; tcg_temp_free_i32 ( v111 ) ; break ; default : abort ( ) ; } if ( v94 == Number ) { gen_neon_addl_saturate ( cpu_V0 , cpu_V0 , v46 ) ; neon_store_reg64 ( cpu_V0 , nn + @@v43@@ ) ; continue ; } if ( v94 == Number || ( ( @@a2@@ >> Number ) & Number ) > Number && ( ( @@a2@@ >> Number ) & Number ) <= Number ) break ; if ( v94 != Number && v94 != Number ) goto LABEL_636 ; v112 = tcg_temp_new_i32 ( ) ; if ( @@v86@@ ) { if ( v46 == Number ) { tcg_gen_addi_i64 ( cpu_V0 , cpu_V0 , Number ) ; tcg_gen_extrh_i64_i32 ( v112 , cpu_V0 ) ; } else if ( v46 ) { gen_helper_neon_narrow_round_high_u16 ( v112 , cpu_V0 ) ; } else { gen_helper_neon_narrow_round_high_u8 ( v112 , cpu_V0 ) ; } } else if ( v46 == Number ) { tcg_gen_extrh_i64_i32 ( v112 , cpu_V0 ) ; } else if ( v46 ) { gen_helper_neon_narrow_high_u16 ( v112 , cpu_V0 ) ; } else { gen_helper_neon_narrow_high_u8 ( v112 , cpu_V0 ) ; } if ( nn ) { neon_store_reg ( @@v43@@ , Number , v155 ) ; neon_store_reg ( @@v43@@ , Number , v112 ) ; } else { v155 = v112 ; } LABEL_637 : ; } neon_load_reg64 ( cpu_V1 , nn + @@v43@@ ) ; switch ( v94 ) { case Number : case Number : goto LABEL_615 ; case Number : case Number : gen_neon_addl_saturate ( cpu_V0 , cpu_V0 , v46 ) ; if ( v94 == Number ) gen_neon_negl ( cpu_V0 , v46 ) ; gen_neon_addl_saturate ( cpu_V0 , cpu_V1 , v46 ) ; break ; case Number : gen_neon_negl ( cpu_V0 , v46 ) ; LABEL_615 : gen_neon_addl ( v46 ) ; break ; default : abort ( ) ; } LABEL_636 : neon_store_reg64 ( cpu_V0 , nn + @@v43@@ ) ; goto LABEL_637 ; } if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) != Number && ( @@v43@@ & Number ) != Number ) return Number L ; v93 = ( @@a2@@ >> Number ) & Number ; v78 = ( @@a2@@ >> Number ) & Number | ( @@v86@@ << Number ) | @@a2@@ & Number ; switch ( v93 ) { case Number : case Number : v78 <<= Number ; goto LABEL_530 ; case Number : case Number : v78 <<= Number ; goto LABEL_530 ; case Number : case Number : v78 <<= Number ; goto LABEL_530 ; case Number : case Number : v78 |= v78 << Number ; goto LABEL_530 ; case Number : case Number : v78 = ( v78 << Number ) | ( v78 << Number ) ; goto LABEL_530 ; case Number : v23 = v78 << Number ; LOBYTE ( v23 ) = Number ; v78 = v23 ; goto LABEL_530 ; case Number : v78 = ( v78 << Number ) | Number ; goto LABEL_530 ; case Number : v78 |= ( v78 << Number ) | ( v78 << Number ) | ( v78 << Number ) ; if ( ( @@a2@@ & Number ) != Number ) v78 = ~ v78 ; goto LABEL_530 ; case Number : if ( ( @@a2@@ & Number ) != Number ) return Number L ; if ( ( v78 & Number ) != Number ) v24 = Number ; else v24 = Number ; v78 = ( v78 << Number ) & Number | ( v78 << Number ) & Number | v24 ; LABEL_530 : if ( ( @@a2@@ & Number ) != Number ) v78 = ~ v78 ; @@v101@@ = neon_reg_offset ( @@v43@@ , Number ) ; if ( ( @@a2@@ & Number ) != Number ) v25 = Number ; else v25 = Number ; if ( ( v93 & Number ) != Number && ( ( @@a2@@ >> Number ) & Number ) <= Number ) { if ( ( @@a2@@ & Number ) != Number ) tcg_gen_gvec_andi ( Number L , @@v101@@ , @@v101@@ , v78 , v25 , v25 ) ; else tcg_gen_gvec_ori ( Number L , @@v101@@ , @@v101@@ , v78 , v25 , v25 ) ; } else if ( v93 == Number && ( @@a2@@ & Number ) != Number ) { @@v214@@ = tcg_temp_new_i64 ( ) ; for ( i1 = Number ; i1 <= @@v85@@ ; ++ i1 ) { @@v176@@ = Number L ; for ( @@i2@@ = Number ; @@i2@@ <= Number ; ++ @@i2@@ ) { if ( ( v78 & ( Number << ( Number * i1 + @@i2@@ ) ) ) != Number ) @@v176@@ |= Number L << ( Number * ( unsigned __int8 ) @@i2@@ ) ; } tcg_gen_movi_i64 ( @@v214@@ , @@v176@@ ) ; neon_store_reg64 ( @@v214@@ , i1 + @@v43@@ ) ; } tcg_temp_free_i64 ( @@v214@@ ) ; } else { tcg_gen_gvec_dup32i ( @@v101@@ , v25 , v25 , v78 ) ; } break ; default : goto LABEL_530 ; } return Number L ; } v92 = ( @@a2@@ >> Number ) & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) > Number ) return Number L ; i3 = Number ; } else { for ( i3 = Number ; ( @@a2@@ & ( Number << ( i3 + Number ) ) ) == Number ; -- i3 ) ; } v50 = HIWORD ( @@a2@@ ) & ( ( Number << ( i3 + Number ) ) - Number ) ; if ( ( ( @@a2@@ >> Number ) & Number ) > Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) > Number ) { if ( v92 == Number ) { if ( ( @@a2@@ & Number ) != Number || ( @@v43@@ & Number ) != Number ) return Number L ; v110 = neon_load_reg ( @@v45@@ , Number ) ; v132 = neon_load_reg ( @@v45@@ , Number ) ; for ( i4 = Number ; i4 <= Number ; ++ i4 ) { if ( i4 == Number ) v110 = v132 ; gen_neon_widen ( cpu_V0 , v110 , i3 , @@v86@@ ) ; if ( v50 ) { tcg_gen_shli_i64 ( cpu_V0 , cpu_V0 , v50 ) ; if ( i3 <= Number || ! @@v86@@ ) { if ( i3 ) { if ( i3 == Number ) v77 = Number >> ( Number - ( BYTE2 ( @@a2@@ ) & ( ( Number << ( i3 + Number ) ) - Number ) ) ) ; else v77 = Number >> ( Number - ( BYTE2 ( @@a2@@ ) & ( ( Number << ( i3 + Number ) ) - Number ) ) ) ; } else { v77 = ( Number >> ( Number - v50 ) << Number ) | ( Number >> ( Number - v50 ) ) ; } if ( i3 > Number ) @@v174@@ = v77 ; else @@v174@@ = ( ( unsigned __int64 ) v77 << Number ) | v77 ; tcg_gen_andi_i64 ( cpu_V0 , cpu_V0 , ~ @@v174@@ ) ; } } neon_store_reg64 ( cpu_V0 , i4 + @@v43@@ ) ; } } else { if ( ( ( @@a2@@ >> Number ) & Number ) <= Number ) return Number L ; if ( ( @@a2@@ & Number ) == Number || ( @@a2@@ & Number ) != Number && ( ( ( unsigned __int8 ) @@v45@@ | ( unsigned __int8 ) @@v43@@ ) & Number ) != Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { if ( @@v86@@ ) @@v175@@ = gen_helper_vfp_touls_round_to_zero ; else @@v175@@ = gen_helper_vfp_tosls_round_to_zero ; } else if ( @@v86@@ ) { @@v175@@ = gen_helper_vfp_ultos ; } else { @@v175@@ = gen_helper_vfp_sltos ; } @@v215@@ = get_fpstatus_ptr ( Number ) ; @@v216@@ = tcg_const_i32 ( ( unsigned int ) ( Number - v50 ) ) ; for ( i5 = Number ; ; ++ i5 ) { v22 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v22 <= i5 ) break ; @@v217@@ = neon_load_reg ( @@v45@@ , i5 ) ; @@v175@@ ( @@v217@@ , @@v217@@ , @@v216@@ , @@v215@@ ) ; neon_store_reg ( @@v43@@ , i5 , @@v217@@ ) ; } tcg_temp_free_ptr ( @@v215@@ ) ; tcg_temp_free_i32 ( @@v216@@ ) ; } } else { if ( v92 == Number ) v21 = @@v86@@ == Number ; else v21 = HIBYTE ( @@a2@@ ) & Number ; @@v102@@ = v21 ; if ( ( @@v45@@ & Number ) != Number ) return Number L ; v54 = v50 - ( Number << ( i3 + Number ) ) ; v48 = i3 + Number ; if ( v48 == Number ) { v203 = tcg_const_i64 ( v54 ) ; neon_load_reg64 ( cpu_V0 , @@v45@@ ) ; neon_load_reg64 ( cpu_V1 , @@v45@@ + Number ) ; for ( i6 = Number ; i6 <= Number ; ++ i6 ) { if ( i6 ) @@v173@@ = cpu_V1 ; else @@v173@@ = cpu_V0 ; if ( ( @@a2@@ & Number ) != Number ) { if ( @@v102@@ ) gen_helper_neon_rshl_u64 ( cpu_V0 , @@v173@@ , v203 ) ; else gen_helper_neon_rshl_s64 ( cpu_V0 , @@v173@@ , v203 ) ; } else if ( @@v102@@ ) { gen_helper_neon_shl_u64 ( cpu_V0 , @@v173@@ , v203 ) ; } else { gen_helper_neon_shl_s64 ( cpu_V0 , @@v173@@ , v203 ) ; } v107 = tcg_temp_new_i32 ( ) ; gen_neon_narrow_op ( v92 == Number , @@v86@@ , Number , v107 , cpu_V0 ) ; neon_store_reg ( @@v43@@ , i6 , v107 ) ; } tcg_temp_free_i64 ( v203 ) ; } else { if ( v48 == Number ) v76 = ( ( unsigned __int16 ) v54 << Number ) | ( unsigned __int16 ) v54 ; else v76 = v54 ; v131 = tcg_const_i32 ( v76 ) ; v206 = neon_load_reg ( @@v45@@ + Number , Number ) ; v178 = neon_load_reg ( @@v45@@ + Number , Number ) ; for ( i7 = Number ; i7 <= Number ; ++ i7 ) { if ( i7 ) { v108 = v206 ; gen_neon_shift_narrow ( v48 , v206 , v131 , @@v85@@ , @@v102@@ ) ; } else { v108 = neon_load_reg ( @@v45@@ , Number ) ; gen_neon_shift_narrow ( v48 , v108 , v131 , @@v85@@ , @@v102@@ ) ; } if ( i7 ) { v154 = v178 ; gen_neon_shift_narrow ( v48 , v178 , v131 , @@v85@@ , @@v102@@ ) ; } else { v154 = neon_load_reg ( @@v45@@ , Number ) ; gen_neon_shift_narrow ( v48 , v154 , v131 , @@v85@@ , @@v102@@ ) ; } tcg_gen_concat_i32_i64 ( cpu_V0 , v108 , v154 ) ; tcg_temp_free_i32 ( v108 ) ; tcg_temp_free_i32 ( v154 ) ; v109 = tcg_temp_new_i32 ( ) ; gen_neon_narrow_op ( v92 == Number , @@v86@@ , v48 - Number , v109 , cpu_V0 ) ; neon_store_reg ( @@v43@@ , i7 , v109 ) ; } LABEL_468 : tcg_temp_free_i32 ( v131 ) ; } } return Number L ; } if ( ( @@a2@@ & Number ) != Number && ( ( ( unsigned __int8 ) @@v45@@ | ( unsigned __int8 ) @@v43@@ ) & Number ) != Number ) return Number L ; if ( ! @@v86@@ && ( v92 == Number || v92 == Number ) ) return Number L ; if ( ( ( @@a2@@ >> Number ) & Number ) <= Number ) v50 -= Number << ( i3 + Number ) ; if ( v92 == Number ) { if ( @@v86@@ ) { if ( v50 < Number << i3 ) tcg_gen_gvec_2i ( @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ , v50 , & sli_op [ Number * i3 ] ) ; } else if ( v50 < Number << i3 ) { tcg_gen_gvec_shli ( ( unsigned int ) i3 , @@v88@@ , @@v90@@ , v50 , @@v87@@ , @@v87@@ ) ; } else { tcg_gen_gvec_dup8i ( @@v88@@ , @@v87@@ , @@v87@@ , Number L ) ; } result = Number L ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) > Number ) goto LABEL_382 ; if ( v92 == Number ) { if ( @@v86@@ ) { v53 = - v50 ; if ( v53 < Number << i3 ) tcg_gen_gvec_2i ( @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ , v53 , & sri_op [ Number * i3 ] ) ; result = Number L ; } else { result = Number L ; } } else if ( v92 ) { if ( v92 != Number ) { LABEL_382 : if ( i3 == Number ) { @@v73@@ = @@v85@@ + Number ; } else { if ( ( @@a2@@ & Number ) != Number ) v20 = Number ; else v20 = Number ; @@v73@@ = v20 ; } v75 = dup_const ( ( unsigned int ) i3 , v50 ) ; for ( i8 = Number ; i8 < @@v73@@ ; ++ i8 ) { if ( i3 == Number ) { neon_load_reg64 ( cpu_V0 , i8 + @@v45@@ ) ; tcg_gen_movi_i64 ( cpu_V1 , v75 ) ; if ( v92 == Number ) { if ( @@v86@@ ) gen_helper_neon_qshl_u64 ( cpu_V0 , cpu_env , cpu_V0 , cpu_V1 ) ; else gen_helper_neon_qshl_s64 ( cpu_V0 , cpu_env , cpu_V0 , cpu_V1 ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) <= Number ) { if ( @@v86@@ ) gen_helper_neon_rshl_u64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; else gen_helper_neon_rshl_s64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; } else { gen_helper_neon_qshlu_s64 ( cpu_V0 , cpu_env , cpu_V0 , cpu_V1 ) ; } if ( v92 == Number ) { neon_load_reg64 ( cpu_V1 , i8 + @@v43@@ ) ; tcg_gen_add_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; } neon_store_reg64 ( cpu_V0 , i8 + @@v43@@ ) ; } else { v106 = neon_load_reg ( @@v45@@ , i8 ) ; v129 = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( v129 , v75 ) ; if ( v92 == Number ) { switch ( @@v86@@ | ( Number * i3 ) ) { case Number : gen_helper_neon_qshl_s8 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_qshl_u8 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_qshl_s16 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_qshl_u16 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_qshl_s32 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_qshl_u32 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; default : return Number L ; } } if ( ( ( @@a2@@ >> Number ) & Number ) <= Number ) { switch ( @@v86@@ | ( Number * i3 ) ) { case Number : gen_helper_neon_rshl_s8 ( v106 , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_rshl_u8 ( v106 , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_rshl_s16 ( v106 , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_rshl_u16 ( v106 , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_rshl_s32 ( v106 , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_rshl_u32 ( v106 , v106 , v129 ) ; goto LABEL_429 ; default : return Number L ; } } if ( i3 == Number ) { gen_helper_neon_qshlu_s32 ( v106 , cpu_env , v106 , v129 ) ; } else { if ( i3 > Number ) goto LABEL_420 ; if ( i3 ) { if ( i3 != Number ) LABEL_420 : abort ( ) ; gen_helper_neon_qshlu_s16 ( v106 , cpu_env , v106 , v129 ) ; } else { gen_helper_neon_qshlu_s8 ( v106 , cpu_env , v106 , v129 ) ; } } LABEL_429 : tcg_temp_free_i32 ( v129 ) ; if ( v92 == Number ) { v130 = neon_load_reg ( @@v43@@ , i8 ) ; gen_neon_add ( i3 , v106 , v130 ) ; tcg_temp_free_i32 ( v130 ) ; } neon_store_reg ( @@v43@@ , i8 , v106 ) ; } } return Number L ; } v52 = - v50 ; if ( @@v86@@ ) { if ( v52 < Number << i3 ) tcg_gen_gvec_2i ( @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ , v52 , & usra_op [ Number * i3 ] ) ; } else { v19 = ( Number << i3 ) - Number ; if ( v52 <= v19 ) v19 = v52 ; tcg_gen_gvec_2i ( @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ , v19 , & ssra_op [ Number * i3 ] ) ; } result = Number L ; } else { v51 = - v50 ; if ( @@v86@@ ) { if ( v51 < Number << i3 ) tcg_gen_gvec_shri ( ( unsigned int ) i3 , @@v88@@ , @@v90@@ , v51 , @@v87@@ , @@v87@@ ) ; else tcg_gen_gvec_dup8i ( @@v88@@ , @@v87@@ , @@v87@@ , Number L ) ; } else { v18 = ( Number << i3 ) - Number ; if ( v51 <= v18 ) v18 = v51 ; tcg_gen_gvec_sari ( ( unsigned int ) i3 , @@v88@@ , @@v90@@ , v18 , @@v87@@ , @@v87@@ ) ; } result = Number L ; } } return result ; }\", \"source\": [{\"n\": \"v39\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r104\"}, {\"n\": \"v37\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r112\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r88\"}, {\"n\": \"v217\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s120\"}, {\"n\": \"v216\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s128\"}, {\"n\": \"v215\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s136\"}, {\"n\": \"v214\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s144\"}, {\"n\": \"v213\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s152\"}, {\"n\": \"v212\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s160\"}, {\"n\": \"v211\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s168\"}, {\"n\": \"v210\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s184\"}, {\"n\": \"v209\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s192\"}, {\"n\": \"v208\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s200\"}, {\"n\": \"v202\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s232\"}, {\"n\": \"v201\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s240\"}, {\"n\": \"v200\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s248\"}, {\"n\": \"v199\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s256\"}, {\"n\": \"v198\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s264\"}, {\"n\": \"v197\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s272\"}, {\"n\": \"v196\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s280\"}, {\"n\": \"v195\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s288\"}, {\"n\": \"v194\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s296\"}, {\"n\": \"v193\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s304\"}, {\"n\": \"v192\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s312\"}, {\"n\": \"v191\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s320\"}, {\"n\": \"v190\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s328\"}, {\"n\": \"v189\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s336\"}, {\"n\": \"v188\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s344\"}, {\"n\": \"v187\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s352\"}, {\"n\": \"v186\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s360\"}, {\"n\": \"v185\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s368\"}, {\"n\": \"v184\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s376\"}, {\"n\": \"v225\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v183\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s416\"}, {\"n\": \"v182\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s424\"}, {\"n\": \"v181\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s440\"}, {\"n\": \"v180\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s448\"}, {\"n\": \"v177\", \"t\": {\"T\": 9, \"n\": \"unsigned __int64 (__fastcall *)(__int64 a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5)\"}, \"location\": \"s472\"}, {\"n\": \"v224\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v176\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s480\"}, {\"n\": \"v175\", \"t\": {\"T\": 9, \"n\": \"unsigned __int64 (__fastcall *)(__int64 a1, __int64 a2, __int64 a3, __int64 a4)\"}, \"location\": \"s488\"}, {\"n\": \"v174\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s496\"}, {\"n\": \"v173\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s504\"}, {\"n\": \"v172\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s512\"}, {\"n\": \"v103\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s556\"}, {\"n\": \"v223\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v102\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s560\"}, {\"n\": \"v101\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s568\"}, {\"n\": \"v100\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s576\"}, {\"n\": \"v99\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s580\"}, {\"n\": \"v98\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s584\"}, {\"n\": \"v97\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s588\"}, {\"n\": \"v96\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s592\"}, {\"n\": \"v90\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s604\"}, {\"n\": \"v89\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s608\"}, {\"n\": \"v88\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s612\"}, {\"n\": \"v87\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s616\"}, {\"n\": \"v86\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s620\"}, {\"n\": \"v85\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s624\"}, {\"n\": \"v84\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s628\"}, {\"n\": \"v83\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s632\"}, {\"n\": \"v82\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s636\"}, {\"n\": \"v222\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s64\"}, {\"n\": \"m\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s640\"}, {\"n\": \"i2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s644\"}, {\"n\": \"v74\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s652\"}, {\"n\": \"v73\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s656\"}, {\"n\": \"v45\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s672\"}, {\"n\": \"v44\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s676\"}, {\"n\": \"v43\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s680\"}, {\"n\": \"v42\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s681\"}, {\"n\": \"v221\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s72\"}, {\"n\": \"v220\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s80\"}, {\"n\": \"v219\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s88\"}, {\"n\": \"v218\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s96\"}]}",
"{\"name\": \"disas_neon_insn_3same_ext\", \"code\": \"__int64 __fastcall disas_neon_insn_3same_ext ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 result ; unsigned __int64 ( __fastcall * v3 ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; unsigned __int64 ( __fastcall * v4 ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; unsigned __int64 ( __fastcall * v5 ) ( __int64 , __int64 , __int64 , __int64 ) ; unsigned int @@v6@@ ; unsigned int v7 ; unsigned int v8 ; unsigned int v9 ; char @@v10@@ ; char @@v11@@ ; bool @@v12@@ ; bool @@v13@@ ; int @@v14@@ ; int @@v15@@ ; int @@v16@@ ; unsigned int @@v17@@ ; unsigned int @@v18@@ ; unsigned int @@v19@@ ; unsigned int @@v20@@ ; int @@v21@@ ; int @@v22@@ ; unsigned int @@v23@@ ; unsigned __int64 ( __fastcall * @@v24@@ ) ( __int64 , __int64 , __int64 , __int64 ) ; unsigned __int64 ( __fastcall * @@v25@@ ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; __int64 @@v26@@ ; @@v24@@ = Number L ; @@v25@@ = Number L ; @@v17@@ = Number ; @@v10@@ = Number ; @@v12@@ = ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) != Number ; @@v11@@ = Number ; if ( ( @@a2@@ & Number ) == Number ) { @@v22@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v17@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_vcma ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ! @@v22@@ && ! isar_feature_aa32_fp16_arith ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v22@@ ) v3 = gen_helper_gvec_fcmlas ; else v3 = gen_helper_gvec_fcmlah ; @@v25@@ = v3 ; } else if ( ( @@a2@@ & Number ) == Number ) { @@v21@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v17@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_vcma ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ! @@v21@@ && ! isar_feature_aa32_fp16_arith ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v21@@ ) v4 = gen_helper_gvec_fcadds ; else v4 = gen_helper_gvec_fcaddh ; @@v25@@ = v4 ; } else if ( ( @@a2@@ & Number ) == Number ) { @@v13@@ = ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) != Number ; if ( ! isar_feature_aa32_dp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v13@@ ) v5 = gen_helper_gvec_udot_b ; else v5 = gen_helper_gvec_sdot_b ; @@v24@@ = v5 ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v20@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_fhm ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v10@@ = Number ; @@v17@@ = @@v20@@ ; @@v25@@ = gen_helper_gvec_fmlal_a32 ; @@v11@@ = Number ; } if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v14@@ = ( ( unsigned __int16 ) @@a2@@ >> Number ) | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v14@@ = ( unsigned __int16 ) @@a2@@ >> Number ; } if ( ( ( unsigned __int8 ) @@v14@@ & @@v12@@ ) != Number ) return Number L ; if ( @@v12@@ || @@v10@@ != Number ) { if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v15@@ = HIWORD ( @@a2@@ ) & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v15@@ = HIWORD ( @@a2@@ ) & Number ; } if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v16@@ = @@a2@@ & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v16@@ = @@a2@@ & Number ; } if ( ( @@v12@@ & ( unsigned __int8 ) ( @@v16@@ | @@v15@@ ) & ( ( unsigned __int8 ) @@v10@@ ^ Number ) ) != Number ) return Number L ; @@v18@@ = vfp_reg_offset ( Number , @@v15@@ ) ; @@v19@@ = vfp_reg_offset ( Number , @@v16@@ ) ; } else { @@v18@@ = vfp_reg_offset ( Number , ( @@a2@@ >> Number ) & Number | ( @@a2@@ >> Number ) & Number ) ; @@v19@@ = vfp_reg_offset ( Number , ( Number * ( _BYTE ) @@a2@@ ) & Number | ( @@a2@@ >> Number ) & Number ) ; } if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { @@v6@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; v7 = syn_simd_access_trap ( Number , Number , Number ) ; gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , v7 , @@v6@@ ) ; result = Number L ; } else if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) { result = Number L ; } else { @@v23@@ = Number * ( @@v12@@ + Number ) ; if ( @@v25@@ ) { if ( @@v11@@ ) @@v26@@ = cpu_env ; else @@v26@@ = get_fpstatus_ptr ( Number ) ; v8 = vfp_reg_offset ( Number , @@v14@@ ) ; tcg_gen_gvec_3_ptr ( v8 , @@v18@@ , @@v19@@ , @@v26@@ , @@v23@@ , @@v23@@ , @@v17@@ , @@v25@@ ) ; if ( @@v11@@ != Number ) tcg_temp_free_ptr ( @@v26@@ ) ; } else { v9 = vfp_reg_offset ( Number , @@v14@@ ) ; tcg_gen_gvec_3_ool ( v9 , @@v18@@ , @@v19@@ , @@v23@@ , @@v23@@ , @@v17@@ , @@v24@@ ) ; } result = Number L ; } return result ; }\", \"source\": [{\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v24\", \"t\": {\"T\": 9, \"n\": \"unsigned __int64 (__fastcall *)(__int64 a1, __int64 a2, __int64 a3, __int64 a4)\"}, \"location\": \"s104\"}, {\"n\": \"v23\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s108\"}, {\"n\": \"v22\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s112\"}, {\"n\": \"v21\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s116\"}, {\"n\": \"v20\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s120\"}, {\"n\": \"v19\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s124\"}, {\"n\": \"v18\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s128\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s132\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s136\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s140\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s144\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s145\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s146\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s147\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s148\"}, {\"n\": \"v26\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s88\"}, {\"n\": \"v25\", \"t\": {\"T\": 9, \"n\": \"unsigned __int64 (__fastcall *)(__int64 a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5)\"}, \"location\": \"s96\"}]}",
"{\"name\": \"disas_neon_insn_2reg_scalar_ext\", \"code\": \"__int64 __fastcall disas_neon_insn_2reg_scalar_ext ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 result ; unsigned __int64 ( __fastcall * v3 ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; unsigned __int64 ( __fastcall * v4 ) ( __int64 , __int64 , __int64 , __int64 ) ; unsigned int @@v5@@ ; unsigned int v6 ; unsigned int v7 ; unsigned int v8 ; char @@v9@@ ; char @@v10@@ ; bool @@v11@@ ; int @@v12@@ ; int @@v13@@ ; unsigned int @@v14@@ ; unsigned int @@v15@@ ; unsigned int @@v16@@ ; unsigned int @@v17@@ ; int @@v18@@ ; int @@v19@@ ; int @@v20@@ ; unsigned int @@v21@@ ; int @@v22@@ ; int @@v23@@ ; int @@v24@@ ; int @@v25@@ ; int @@v26@@ ; unsigned int @@v27@@ ; unsigned __int64 ( __fastcall * @@v28@@ ) ( __int64 , __int64 , __int64 , __int64 ) ; unsigned __int64 ( __fastcall * @@v29@@ ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; __int64 @@v30@@ ; @@v28@@ = Number L ; @@v29@@ = Number L ; @@v9@@ = Number ; @@v11@@ = ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) != Number ; @@v10@@ = Number ; if ( ( @@a2@@ & Number ) == Number ) { @@v25@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v26@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_vcma ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v26@@ ) { if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v14@@ = @@a2@@ & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v14@@ = @@a2@@ & Number ; } @@v18@@ = Number ; } else { if ( ! isar_feature_aa32_fp16_arith ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v14@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v18@@ = extract32 ( @@a2@@ , Number , Number ) ; } @@v15@@ = @@v25@@ | ( Number * @@v18@@ ) ; if ( @@v26@@ ) v3 = gen_helper_gvec_fcmlas_idx ; else v3 = gen_helper_gvec_fcmlah_idx ; @@v29@@ = v3 ; } else if ( ( @@a2@@ & Number ) == Number ) { @@v24@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_dp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v24@@ ) v4 = gen_helper_gvec_udot_idx_b ; else v4 = gen_helper_gvec_sdot_idx_b ; @@v28@@ = v4 ; @@v15@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v14@@ = extract32 ( @@a2@@ , Number , Number ) ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v20@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v21@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v22@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v23@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_fhm ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v11@@ ) { @@v14@@ = @@v21@@ ; @@v19@@ = Number * @@v23@@ + @@v22@@ ; } else { @@v14@@ = Number * @@v21@@ + @@v23@@ ; @@v19@@ = @@v22@@ ; } @@v9@@ = Number ; @@v15@@ = @@v20@@ | ( Number * @@v19@@ ) ; @@v29@@ = gen_helper_gvec_fmlal_idx_a32 ; @@v10@@ = Number ; } if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v12@@ = ( ( unsigned __int16 ) @@a2@@ >> Number ) | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v12@@ = ( unsigned __int16 ) @@a2@@ >> Number ; } if ( ( ( unsigned __int8 ) @@v12@@ & @@v11@@ ) != Number ) return Number L ; if ( @@v11@@ || @@v9@@ != Number ) { if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v13@@ = HIWORD ( @@a2@@ ) & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v13@@ = HIWORD ( @@a2@@ ) & Number ; } if ( ( ( unsigned __int8 ) @@v13@@ & @@v11@@ & ( ( unsigned __int8 ) @@v9@@ ^ Number ) ) != Number ) return Number L ; @@v16@@ = vfp_reg_offset ( Number , @@v13@@ ) ; @@v17@@ = vfp_reg_offset ( Number , @@v14@@ ) ; } else { @@v16@@ = vfp_reg_offset ( Number , ( @@a2@@ >> Number ) & Number | ( @@a2@@ >> Number ) & Number ) ; @@v17@@ = vfp_reg_offset ( Number , @@v14@@ ) ; } if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { @@v5@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; v6 = syn_simd_access_trap ( Number , Number , Number ) ; gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , v6 , @@v5@@ ) ; result = Number L ; } else if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) { result = Number L ; } else { @@v27@@ = Number * ( @@v11@@ + Number ) ; if ( @@v29@@ ) { if ( @@v10@@ ) @@v30@@ = cpu_env ; else @@v30@@ = get_fpstatus_ptr ( Number ) ; v7 = vfp_reg_offset ( Number , @@v12@@ ) ; tcg_gen_gvec_3_ptr ( v7 , @@v16@@ , @@v17@@ , @@v30@@ , @@v27@@ , @@v27@@ , @@v15@@ , @@v29@@ ) ; if ( @@v10@@ != Number ) tcg_temp_free_ptr ( @@v30@@ ) ; } else { v8 = vfp_reg_offset ( Number , @@v12@@ ) ; tcg_gen_gvec_3_ool ( v8 , @@v16@@ , @@v17@@ , @@v27@@ , @@v27@@ , @@v15@@ , @@v28@@ ) ; } result = Number L ; } return result ; }\", \"source\": [{\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v25\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v24\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s104\"}, {\"n\": \"v23\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s108\"}, {\"n\": \"v22\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s112\"}, {\"n\": \"v21\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s116\"}, {\"n\": \"v20\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s120\"}, {\"n\": \"v19\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s124\"}, {\"n\": \"v18\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s128\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s132\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s136\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s140\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s144\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s148\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s152\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s153\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s154\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s155\"}, {\"n\": \"v30\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s72\"}, {\"n\": \"v29\", \"t\": {\"T\": 9, \"n\": \"unsigned __int64 (__fastcall *)(__int64 a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5)\"}, \"location\": \"s80\"}, {\"n\": \"v28\", \"t\": {\"T\": 9, \"n\": \"unsigned __int64 (__fastcall *)(__int64 a1, __int64 a2, __int64 a3, __int64 a4)\"}, \"location\": \"s88\"}, {\"n\": \"v27\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s92\"}, {\"n\": \"v26\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s96\"}]}",
"{\"name\": \"disas_coproc_insn\", \"code\": \"__int64 __fastcall disas_coproc_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 result ; unsigned int v4 ; bool v5 ; const char * v6 ; const char * v7 ; const char * v8 ; const char * v9 ; char @@v10@@ ; unsigned int @@v11@@ ; unsigned int @@v12@@ ; unsigned int @@v13@@ ; int @@v14@@ ; unsigned int @@v15@@ ; unsigned int @@v16@@ ; int @@v17@@ ; unsigned int @@v18@@ ; int @@v19@@ ; __int64 @@v20@@ ; __int64 @@v21@@ ; __int64 @@v22@@ ; __int64 @@v23@@ ; __int64 @@v24@@ ; __int64 @@v25@@ ; __int64 @@v26@@ ; __int64 @@v27@@ ; __int64 @@v28@@ ; __int64 @@v29@@ ; __int64 @@v30@@ ; __int64 @@v31@@ ; __int64 @@v32@@ ; __int64 @@v33@@ ; __int64 @@v34@@ ; __int64 v35 ; __int64 v36 ; __int64 @@v37@@ ; @@v16@@ = ( @@a2@@ >> Number ) & Number ; if ( arm_dc_feature ( @@a1@@ , Number ) && ( ( @@a2@@ >> Number ) & Number ) <= Number ) { if ( ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , @@v16@@ , Number ) ) { if ( arm_dc_feature ( @@a1@@ , Number ) ) { result = disas_iwmmxt_insn ( @@a1@@ , @@a2@@ ) ; } else if ( arm_dc_feature ( @@a1@@ , Number ) ) { result = disas_dsp_insn ( @@a1@@ , @@a2@@ ) ; } else { result = Number L ; } } else { result = Number L ; } } else { if ( ( @@a2@@ & Number ) != Number && ( @@a2@@ & Number ) == Number ) return Number L ; @@v17@@ = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { @@v11@@ = HIWORD ( @@a2@@ ) & Number ; @@v12@@ = ( @@a2@@ >> Number ) & Number ; @@v13@@ = ( unsigned __int8 ) @@a2@@ >> Number ; @@v14@@ = Number ; } else { @@v11@@ = Number ; @@v12@@ = ( unsigned __int8 ) @@a2@@ >> Number ; @@v13@@ = Number ; @@v14@@ = HIWORD ( @@a2@@ ) & Number ; } @@v18@@ = ( @@a2@@ >> Number ) & Number ; @@v19@@ = ( unsigned __int16 ) @@a2@@ >> Number ; @@v22@@ = get_arm_cp_reginfo ( * ( _QWORD * ) ( @@a1@@ + Number ) , @@v13@@ | ( @@v17@@ << Number ) | ( @@v11@@ << Number ) | ( ( ( @@a2@@ & Number ) == Number ) << Number ) | ( @@v16@@ << Number ) | ( * ( unsigned __int8 * ) ( @@a1@@ + Number ) << Number ) | ( Number * @@v12@@ ) ) ; if ( @@v22@@ ) { if ( ! cp_access_ok ( * ( _DWORD * ) ( @@a1@@ + Number ) , @@v22@@ , ( @@a2@@ & Number ) != Number ) ) return Number L ; if ( * ( _QWORD * ) ( @@v22@@ + Number ) || arm_dc_feature ( @@a1@@ , Number ) && ( ( @@a2@@ >> Number ) & Number ) <= Number ) { if ( @@v16@@ == Number ) { if ( ( @@a2@@ & Number ) != Number ) @@v15@@ = syn_cp14_rt_trap ( Number , Number , @@v12@@ , @@v13@@ , @@v11@@ , @@v17@@ , @@v19@@ , @@v18@@ , Number ) ; else @@v15@@ = syn_cp14_rrt_trap ( Number , Number , @@v12@@ , @@v17@@ , @@v19@@ , @@v14@@ , @@v18@@ , Number ) ; } else if ( @@v16@@ == Number ) { if ( ( @@a2@@ & Number ) != Number ) @@v15@@ = syn_cp15_rt_trap ( Number , Number , @@v12@@ , @@v13@@ , @@v11@@ , @@v17@@ , @@v19@@ , @@v18@@ , Number ) ; else @@v15@@ = syn_cp15_rrt_trap ( Number , Number , @@v12@@ , @@v17@@ , @@v19@@ , @@v14@@ , @@v18@@ , Number ) ; } else { if ( arm_dc_feature ( @@a1@@ , Number ) ) _assert_fail ( String , String , Number , String ) ; @@v15@@ = syn_uncategorized ( ) ; } gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; @@v23@@ = tcg_const_i64 ( @@v22@@ ) ; @@v24@@ = tcg_const_i32 ( @@v15@@ ) ; @@v25@@ = tcg_const_i32 ( @@v18@@ ) ; gen_helper_access_check_cp_reg ( cpu_env , @@v23@@ , @@v24@@ , @@v25@@ ) ; tcg_temp_free_ptr ( @@v23@@ ) ; tcg_temp_free_i32 ( @@v24@@ ) ; tcg_temp_free_i32 ( @@v25@@ ) ; } else if ( ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ) { gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; } v4 = * ( _DWORD * ) ( @@v22@@ + Number ) & Number ; if ( v4 == Number ) return Number L ; if ( v4 == Number ) { if ( @@v18@@ ) { result = Number L ; } else { gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; result = Number L ; } } else { if ( ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number && ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ) gen_io_start ( ) ; if ( @@v18@@ ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ) { @@v21@@ = tcg_const_i32 ( ( unsigned int ) * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } else if ( * ( _QWORD * ) ( @@v22@@ + Number ) ) { @@v21@@ = tcg_temp_new_i32 ( ) ; @@v33@@ = tcg_const_i64 ( @@v22@@ ) ; gen_helper_get_cp_reg ( @@v21@@ , cpu_env , @@v33@@ ) ; tcg_temp_free_ptr ( @@v33@@ ) ; } else { @@v21@@ = load_cpu_offset ( * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } if ( @@v19@@ == Number ) { gen_set_cpsr ( @@v21@@ , Number ) ; tcg_temp_free_i32 ( @@v21@@ ) ; } else { store_reg ( @@a1@@ , @@v19@@ , @@v21@@ ) ; } } else { if ( ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ) { @@v20@@ = tcg_const_i64 ( * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } else if ( * ( _QWORD * ) ( @@v22@@ + Number ) ) { @@v20@@ = tcg_temp_new_i64 ( ) ; @@v34@@ = tcg_const_i64 ( @@v22@@ ) ; gen_helper_get_cp_reg64 ( @@v20@@ , cpu_env , @@v34@@ ) ; tcg_temp_free_ptr ( @@v34@@ ) ; } else { @@v20@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ld_i64 ( @@v20@@ , cpu_env , * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } v35 = tcg_temp_new_i32 ( ) ; tcg_gen_extrl_i64_i32 ( v35 , @@v20@@ ) ; store_reg ( @@a1@@ , @@v19@@ , v35 ) ; v36 = tcg_temp_new_i32 ( ) ; tcg_gen_extrh_i64_i32 ( v36 , @@v20@@ ) ; tcg_temp_free_i64 ( @@v20@@ ) ; store_reg ( @@a1@@ , @@v14@@ , v36 ) ; } } else { if ( ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { if ( * ( _QWORD * ) ( @@v22@@ + Number ) ) { @@v27@@ = load_reg ( @@a1@@ , @@v19@@ ) ; @@v28@@ = tcg_const_i64 ( @@v22@@ ) ; gen_helper_set_cp_reg ( cpu_env , @@v28@@ , @@v27@@ ) ; tcg_temp_free_ptr ( @@v28@@ ) ; tcg_temp_free_i32 ( @@v27@@ ) ; } else { @@v26@@ = load_reg ( @@a1@@ , @@v19@@ ) ; store_cpu_offset ( @@v26@@ , * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } } else { @@v29@@ = tcg_temp_new_i64 ( ) ; @@v30@@ = load_reg ( @@a1@@ , @@v19@@ ) ; @@v31@@ = load_reg ( @@a1@@ , @@v14@@ ) ; tcg_gen_concat_i32_i64 ( @@v29@@ , @@v30@@ , @@v31@@ ) ; tcg_temp_free_i32 ( @@v30@@ ) ; tcg_temp_free_i32 ( @@v31@@ ) ; if ( * ( _QWORD * ) ( @@v22@@ + Number ) ) { @@v32@@ = tcg_const_i64 ( @@v22@@ ) ; gen_helper_set_cp_reg64 ( cpu_env , @@v32@@ , @@v29@@ ) ; tcg_temp_free_ptr ( @@v32@@ ) ; } else { tcg_gen_st_i64 ( @@v29@@ , cpu_env , * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } tcg_temp_free_i64 ( @@v29@@ ) ; } } v5 = ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number && ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ; @@v10@@ = v5 ; if ( ! @@v18@@ && ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) == Number ) { @@v37@@ = tcg_const_i32 ( * ( unsigned int * ) ( @@a1@@ + Number ) ) ; if ( arm_dc_feature ( @@a1@@ , Number ) ) gen_helper_rebuild_hflags_m32 ( cpu_env , @@v37@@ ) ; else gen_helper_rebuild_hflags_a32 ( cpu_env , @@v37@@ ) ; tcg_temp_free_i32 ( @@v37@@ ) ; @@v10@@ = Number ; } if ( @@v10@@ ) gen_lookup_tb ( @@a1@@ ) ; result = Number L ; } } else { if ( ( @@a2@@ & Number ) != Number ) { if ( qemu_loglevel_mask ( Number ) ) { if ( * ( _BYTE * ) ( @@a1@@ + Number ) ) v8 = String ; else v8 = String ; if ( @@v18@@ ) v9 = String ; else v9 = String ; qemu_log ( String , v9 , @@v16@@ , @@v12@@ , @@v11@@ , @@a2@@ & Number , @@v13@@ , v8 ) ; } } else if ( qemu_loglevel_mask ( Number ) ) { if ( * ( _BYTE * ) ( @@a1@@ + Number ) ) v6 = String ; else v6 = String ; if ( @@v18@@ ) v7 = String ; else v7 = String ; qemu_log ( String , v7 , @@v16@@ , @@v12@@ , @@a2@@ & Number , v6 ) ; } result = Number L ; } } return result ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v24\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s104\"}, {\"n\": \"v23\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s112\"}, {\"n\": \"v22\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s120\"}, {\"n\": \"v21\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s128\"}, {\"n\": \"v20\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s136\"}, {\"n\": \"v19\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s140\"}, {\"n\": \"v18\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s144\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s148\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s156\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s160\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s164\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s168\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s172\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s176\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s177\"}, {\"n\": \"v34\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v33\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v32\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v31\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v30\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v29\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s64\"}, {\"n\": \"v28\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s72\"}, {\"n\": \"v37\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v27\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s80\"}, {\"n\": \"v26\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s88\"}, {\"n\": \"v25\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s96\"}]}",
"{\"name\": \"disas_t32\", \"code\": \"_BOOL8 __fastcall disas_t32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; unsigned int v3 ; unsigned int v4 ; int v5 ; unsigned int v6 ; int v7 ; unsigned int v8 ; unsigned int v9 ; unsigned int v10 ; unsigned int v11 ; unsigned int v12 ; unsigned int v13 ; int v14 ; unsigned int v15 ; int v16 ; unsigned int v17 ; int v18 ; int v19 ; unsigned int v20 ; unsigned int v21 ; unsigned int v22 ; unsigned int v23 ; unsigned int v24 ; _BOOL8 result ; int @@v26@@ ; int @@v27@@ ; int @@v28@@ ; unsigned __int64 @@v29@@ ; @@v29@@ = __readfsqword ( Number ) ; v2 = @@a2@@ >> Number ; if ( @@a2@@ >> Number == Number ) { v12 = HIBYTE ( @@a2@@ ) & Number ; if ( v12 == Number ) { v24 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_UMAAL ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_s0_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_UMLAL ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLSLDX ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLSLD ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLALDX ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLALD ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLALTT ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLALTB ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLALBT ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLALBB ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_s0_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLAL ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rndm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int16 ) @@a2@@ >> Number == Number ) result = ( unsigned __int8 ) trans_UDIV ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; return result ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_s0_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_UMULL ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rndm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int16 ) @@a2@@ >> Number == Number ) result = ( unsigned __int8 ) trans_SDIV ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; return result ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_s0_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMULL ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_USADA8 ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMMLSR ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMMLS ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMMLAR ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMMLA ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLSDX ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLSD ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_rn0dm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_SMULWT ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLAWT ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_rn0dm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_SMULWB ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLAWB ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLADX ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLAD ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_rn0dm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_SMULTT ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLATT ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_rn0dm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_SMULTB ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLATB ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_rn0dm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_SMULBT ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLABT ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( v24 == Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_rn0dm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_SMULBB ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SMLABB ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 <= Number ) { if ( ! v24 ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_s0_rn0dm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_MUL ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_s0_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_MLA ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v24 == Number ) { disas_t32_extract_rnadm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_MLS ( @@a1@@ , & @@v26@@ ) != Number ; } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } return Number L ; } if ( v12 > Number ) return Number L ; if ( v12 != Number ) { if ( v12 ) { v19 = ( @@a2@@ >> Number ) & Number ; if ( v19 == Number ) { if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_ldst_ri_lit ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRSB_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_ldst_ri_pos ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRSB_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_ldst_ri_idx ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRSB_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_ldst_ri_neg ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRSB_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_ldst_ri_unp ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRSBT_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) != Number ) goto LABEL_526 ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_ldst_rr ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ! ( unsigned __int8 ) trans_LDRSB_rr ( @@a1@@ , & @@v26@@ ) ) LABEL_526 : result = Number L ; else result = Number L ; } else { if ( v19 != Number ) return Number L ; if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_ldst_ri_lit ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRSH_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_ldst_ri_pos ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRSH_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_ldst_ri_idx ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRSH_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_ldst_ri_neg ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRSH_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_ldst_ri_unp ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRSHT_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) != Number ) goto LABEL_557 ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_ldst_rr ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ! ( unsigned __int8 ) trans_LDRSH_rr ( @@a1@@ , & @@v26@@ ) ) LABEL_557 : result = Number L ; else result = Number L ; } } else { switch ( ( @@a2@@ >> Number ) & Number ) { case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_t32_extract_ldst_ri_pos ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STRB_ri ( @@a1@@ , & @@v26@@ ) != Number ; } v13 = @@a2@@ & Number ; if ( v13 == Number ) { disas_t32_extract_ldst_ri_idx ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STRB_ri ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v13 > Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { if ( v13 != Number ) return Number L ; v14 = ( @@a2@@ >> Number ) & Number ; if ( v14 == Number ) { disas_t32_extract_ldst_ri_neg ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STRB_ri ( @@a1@@ , & @@v26@@ ) != Number ; } else if ( v14 == Number ) { disas_t32_extract_ldst_ri_unp ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STRBT_ri ( @@a1@@ , & @@v26@@ ) != Number ; } else { result = Number L ; } } else { disas_t32_extract_ldst_rr ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_STRB_rr ( @@a1@@ , & @@v26@@ ) != Number ; } return result ; case Number : if ( ( @@a2@@ & Number ) != Number ) goto LABEL_383 ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_ldst_ri_lit ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRB_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; LABEL_383 : if ( ( @@a2@@ & Number ) == Number ) goto LABEL_389 ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_ldst_ri_pos ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRB_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; LABEL_389 : if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_ldst_ri_idx ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRB_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) != Number ) goto LABEL_398 ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_ldst_ri_neg ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRB_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; LABEL_398 : if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_ldst_ri_unp ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRBT_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) != Number ) goto LABEL_407 ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_ldst_rr ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRB_rr ( @@a1@@ , & @@v26@@ ) ) result = Number L ; else LABEL_407 : result = Number L ; return result ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_t32_extract_ldst_ri_pos ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STRH_ri ( @@a1@@ , & @@v26@@ ) != Number ; } v15 = @@a2@@ & Number ; if ( v15 == Number ) { disas_t32_extract_ldst_ri_idx ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STRH_ri ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v15 > Number ) goto LABEL_424 ; if ( ( @@a2@@ & Number ) != Number ) { if ( v15 == Number ) { v16 = ( @@a2@@ >> Number ) & Number ; if ( v16 == Number ) { disas_t32_extract_ldst_ri_neg ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STRH_ri ( @@a1@@ , & @@v26@@ ) != Number ; } else if ( v16 == Number ) { disas_t32_extract_ldst_ri_unp ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STRHT_ri ( @@a1@@ , & @@v26@@ ) != Number ; } else { result = Number L ; } } else { LABEL_424 : result = Number L ; } } else { disas_t32_extract_ldst_rr ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_STRH_rr ( @@a1@@ , & @@v26@@ ) != Number ; } return result ; case Number : if ( ( @@a2@@ & Number ) != Number ) goto LABEL_431 ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_ldst_ri_lit ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRH_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; LABEL_431 : if ( ( @@a2@@ & Number ) == Number ) goto LABEL_437 ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_ldst_ri_pos ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRH_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; LABEL_437 : if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_ldst_ri_idx ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRH_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) != Number ) goto LABEL_446 ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_ldst_ri_neg ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRH_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; LABEL_446 : if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_ldst_ri_unp ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRHT_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) != Number ) goto LABEL_455 ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_ldst_rr ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRH_rr ( @@a1@@ , & @@v26@@ ) ) result = Number L ; else LABEL_455 : result = Number L ; return result ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_t32_extract_ldst_ri_pos ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STR_ri ( @@a1@@ , & @@v26@@ ) != Number ; } v17 = @@a2@@ & Number ; if ( v17 == Number ) { disas_t32_extract_ldst_ri_idx ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STR_ri ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v17 > Number ) goto LABEL_472 ; if ( ( @@a2@@ & Number ) != Number ) { if ( v17 == Number ) { v18 = ( @@a2@@ >> Number ) & Number ; if ( v18 == Number ) { disas_t32_extract_ldst_ri_neg ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STR_ri ( @@a1@@ , & @@v26@@ ) != Number ; } else if ( v18 == Number ) { disas_t32_extract_ldst_ri_unp ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STRT_ri ( @@a1@@ , & @@v26@@ ) != Number ; } else { result = Number L ; } } else { LABEL_472 : result = Number L ; } } else { disas_t32_extract_ldst_rr ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_STR_rr ( @@a1@@ , & @@v26@@ ) != Number ; } break ; case Number : if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_ldst_ri_lit ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDR_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) != Number ) { disas_t32_extract_ldst_ri_pos ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDR_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_ldst_ri_idx ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDR_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_ldst_ri_neg ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDR_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_ldst_ri_unp ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDRT_ri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } result = Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_ldst_rr ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_LDR_rr ( @@a1@@ , & @@v26@@ ) ) result = Number ; } return result ; default : return Number L ; } } return result ; } v20 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v20 <= Number ) { if ( v20 == Number ) { disas_t32_extract_rndm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; v22 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_UHSAX ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_UQSAX ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_USAX ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_UHSUB16 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_UQSUB16 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_USUB16 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_UHSUB8 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_UQSUB8 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_USUB8 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_UHASX ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_UQASX ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_UASX ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_UHADD16 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_UQADD16 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_UADD16 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 <= Number ) { if ( v22 == Number ) return ( unsigned __int8 ) trans_UHADD8 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 <= Number ) { if ( ! v22 ) return ( unsigned __int8 ) trans_UADD8 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v22 == Number ) return ( unsigned __int8 ) trans_UQADD8 ( @@a1@@ , & @@v26@@ ) != Number ; } } } } } } } } } } } } } } } } return Number L ; } if ( v20 <= Number ) { if ( v20 == Number ) { disas_t32_extract_rndm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; v21 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_SHSAX ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 <= Number ) { if ( v21 == Number ) return ( unsigned __int8 ) trans_QSAX ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 <= Number ) { if ( v21 == Number ) return ( unsigned __int8 ) trans_SSAX ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 <= Number ) { if ( v21 == Number ) return ( unsigned __int8 ) trans_SHSUB16 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 <= Number ) { if ( v21 == Number ) return ( unsigned __int8 ) trans_QSUB16 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 <= Number ) { if ( v21 == Number ) return ( unsigned __int8 ) trans_SSUB16 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 <= Number ) { if ( v21 == Number ) return ( unsigned __int8 ) trans_SHSUB8 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 <= Number ) { if ( v21 == Number ) return ( unsigned __int8 ) trans_QSUB8 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 <= Number ) { if ( v21 == Number ) return ( unsigned __int8 ) trans_SSUB8 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 <= Number ) { if ( v21 == Number ) return ( unsigned __int8 ) trans_SHASX ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 <= Number ) { if ( v21 == Number ) return ( unsigned __int8 ) trans_QASX ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 <= Number ) { if ( v21 == Number ) return ( unsigned __int8 ) trans_SASX ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 <= Number ) { if ( v21 == Number ) return ( unsigned __int8 ) trans_SHADD16 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 <= Number ) { if ( v21 == Number ) return ( unsigned __int8 ) trans_QADD16 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 <= Number ) { if ( v21 == Number ) return ( unsigned __int8 ) trans_SADD16 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 <= Number ) { if ( v21 == Number ) return ( unsigned __int8 ) trans_SHADD8 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 <= Number ) { if ( ! v21 ) return ( unsigned __int8 ) trans_SADD8 ( @@a1@@ , & @@v26@@ ) != Number ; if ( v21 == Number ) return ( unsigned __int8 ) trans_QADD8 ( @@a1@@ , & @@v26@@ ) != Number ; } } } } } } } } } } } } } } } } return Number L ; } if ( v20 <= Number ) { if ( v20 == Number ) { disas_t32_extract_disas_t32_Fmt_4 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_MOV_rxrr ( @@a1@@ , & @@v26@@ ) != Number ; return result ; } if ( v20 == Number ) { disas_t32_extract_rrr_rot ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; switch ( ( @@a2@@ >> Number ) & Number ) { case Number : result = ( unsigned __int8 ) trans_SXTAH ( @@a1@@ , & @@v26@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_UXTAH ( @@a1@@ , & @@v26@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_SXTAB16 ( @@a1@@ , & @@v26@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_UXTAB16 ( @@a1@@ , & @@v26@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_SXTAB ( @@a1@@ , & @@v26@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_UXTAB ( @@a1@@ , & @@v26@@ ) != Number ; break ; default : result = Number L ; break ; } return result ; } } } } return Number L ; } v23 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_rndm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_CRC32CW ( @@a1@@ , & @@v26@@ ) != Number ; } else { if ( v23 <= Number ) { if ( v23 == Number ) { disas_t32_extract_rndm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_CRC32CH ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v23 <= Number ) { if ( v23 == Number ) { disas_t32_extract_rndm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_CRC32CB ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v23 <= Number ) { if ( v23 == Number ) { disas_t32_extract_rndm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_CRC32W ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v23 <= Number ) { if ( v23 == Number ) { disas_t32_extract_rndm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_CRC32H ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v23 <= Number ) { if ( v23 == Number ) { disas_t32_extract_rndm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_CRC32B ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v23 <= Number ) { if ( v23 == Number ) { disas_t32_extract_rdm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_CLZ ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v23 <= Number ) { if ( v23 == Number ) { disas_t32_extract_rndm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SEL ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v23 <= Number ) { if ( v23 == Number ) { disas_t32_extract_rdm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_REVSH ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v23 <= Number ) { if ( v23 == Number ) { disas_t32_extract_rdm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_RBIT ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v23 <= Number ) { if ( v23 == Number ) { disas_t32_extract_rdm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_REV16 ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v23 <= Number ) { if ( v23 == Number ) { disas_t32_extract_rdm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_REV ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v23 <= Number ) { if ( v23 == Number ) { disas_t32_extract_rndm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_QDSUB ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v23 <= Number ) { if ( v23 == Number ) { disas_t32_extract_rndm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_QSUB ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v23 <= Number ) { if ( ! v23 ) { disas_t32_extract_rndm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_QADD ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v23 == Number ) { disas_t32_extract_rndm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_QDADD ( @@a1@@ , & @@v26@@ ) != Number ; } } } } } } } } } } } } } } } result = Number L ; } } else { if ( v2 == Number ) { v3 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_s_rrr_shi ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; v10 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_RSB_rrri ( @@a1@@ , & @@v26@@ ) != Number ; if ( v10 > Number ) goto LABEL_191 ; if ( ! v10 ) return ( unsigned __int8 ) trans_ADC_rrri ( @@a1@@ , & @@v26@@ ) != Number ; if ( v10 == Number ) result = ( unsigned __int8 ) trans_SBC_rrri ( @@a1@@ , & @@v26@@ ) != Number ; else LABEL_191 : result = Number L ; return result ; } if ( v3 <= Number ) { if ( v3 == Number ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) == Number && ( disas_t32_extract_S_xrr_shi ( @@a1@@ , & @@v26@@ , @@a2@@ ) , ( unsigned __int8 ) trans_CMP_xrri ( @@a1@@ , & @@v26@@ ) ) ) { result = Number L ; } else { disas_t32_extract_s_rrr_shi ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_SUB_rrri ( @@a1@@ , & @@v26@@ ) != Number ; } } else { result = Number L ; } } else if ( ( @@a2@@ & Number ) == Number && ( disas_t32_extract_S_xrr_shi ( @@a1@@ , & @@v26@@ , @@a2@@ ) , ( unsigned __int8 ) trans_CMN_xrri ( @@a1@@ , & @@v26@@ ) ) ) { result = Number L ; } else { disas_t32_extract_s_rrr_shi ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_ADD_rrri ( @@a1@@ , & @@v26@@ ) != Number ; } return result ; } if ( v3 <= Number ) { if ( v3 == Number ) { v9 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_3 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_PKH ( @@a1@@ , & @@v26@@ ) != Number ; return result ; } if ( v9 <= Number ) { if ( ! v9 ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_s_rxr_shi ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_MOV_rxri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_s_rrr_shi ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_ORR_rrri ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v9 == Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_s_rxr_shi ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_MVN_rxri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_s_rrr_shi ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_ORN_rrri ( @@a1@@ , & @@v26@@ ) != Number ; } } return Number L ; } if ( v3 <= Number ) { if ( v3 == Number ) { v8 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v8 <= Number ) { if ( ! v8 ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_S_xrr_shi ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_TST_xrri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_s_rrr_shi ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_AND_rrri ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v8 == Number ) { disas_t32_extract_s_rrr_shi ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_BIC_rrri ( @@a1@@ , & @@v26@@ ) != Number ; } } return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_S_xrr_shi ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_TEQ_xrri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_s_rrr_shi ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_EOR_rrri ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v3 <= Number ) { if ( v3 == Number ) { v7 = ( @@a2@@ >> Number ) & Number ; if ( v7 == Number ) { if ( ( @@a2@@ & Number ) == Number && ( disas_t32_extract_disas_t32_Fmt_22 ( ) , ( unsigned __int8 ) trans_SG ( @@a1@@ , & @@v26@@ ) ) ) { result = Number L ; } else { disas_t32_extract_ldstd_ri8 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; @@v28@@ = Number ; @@v27@@ = Number ; result = ( unsigned __int8 ) trans_LDRD_ri_t32 ( @@a1@@ , & @@v26@@ ) != Number ; } } else if ( v7 == Number ) { disas_t32_extract_ldstd_ri8 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; @@v28@@ = Number ; @@v27@@ = Number ; result = ( unsigned __int8 ) trans_STRD_ri_t32 ( @@a1@@ , & @@v26@@ ) != Number ; } else if ( v7 ) { disas_t32_extract_ldstd_ri8 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; @@v28@@ = Number ; @@v27@@ = Number ; result = ( unsigned __int8 ) trans_LDRD_ri_t32 ( @@a1@@ , & @@v26@@ ) != Number ; } else { disas_t32_extract_ldstd_ri8 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; @@v28@@ = Number ; @@v27@@ = Number ; result = ( unsigned __int8 ) trans_STRD_ri_t32 ( @@a1@@ , & @@v26@@ ) != Number ; } return result ; } if ( v3 <= Number ) { if ( v3 == Number ) { v6 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_rfe ( @@a1@@ , ( __int64 ) & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int16 ) @@a2@@ == Number ) { @@v26@@ = Number ; result = ( unsigned __int8 ) trans_RFE ( @@a1@@ , & @@v26@@ ) != Number ; } else { result = Number L ; } } else if ( v6 == Number ) { disas_t32_extract_srs ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { @@v27@@ = Number ; result = ( unsigned __int8 ) trans_SRS ( @@a1@@ , & @@v26@@ ) != Number ; } else { result = Number L ; } } else { if ( v6 > Number ) goto LABEL_129 ; if ( ! v6 ) { disas_t32_extract_ldstm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; @@v27@@ = Number ; @@v26@@ = Number ; return ( unsigned __int8 ) trans_STM_t32 ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v6 == Number ) { disas_t32_extract_ldstm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; @@v27@@ = Number ; @@v26@@ = Number ; result = ( unsigned __int8 ) trans_LDM_t32 ( @@a1@@ , & @@v26@@ ) != Number ; } else { LABEL_129 : result = Number L ; } } return result ; } if ( v3 <= Number ) { if ( ! v3 ) { v4 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_ldstm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; @@v27@@ = Number ; @@v26@@ = Number ; return ( unsigned __int8 ) trans_LDM_t32 ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v4 == Number ) { disas_t32_extract_ldstm ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; @@v27@@ = Number ; @@v26@@ = Number ; return ( unsigned __int8 ) trans_STM_t32 ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v4 <= Number ) { if ( ! v4 ) { disas_t32_extract_srs ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) return Number L ; @@v27@@ = Number ; return ( unsigned __int8 ) trans_SRS ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v4 == Number ) { disas_t32_extract_rfe ( @@a1@@ , ( __int64 ) & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int16 ) @@a2@@ != Number ) return Number L ; @@v26@@ = Number ; return ( unsigned __int8 ) trans_RFE ( @@a1@@ , & @@v26@@ ) != Number ; } } return Number L ; } if ( v3 == Number ) { v5 = ( @@a2@@ >> Number ) & Number ; if ( v5 == Number ) { disas_t32_extract_ldstd_ri8 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; @@v28@@ = Number ; @@v27@@ = Number ; result = ( unsigned __int8 ) trans_LDRD_ri_t32 ( @@a1@@ , & @@v26@@ ) != Number ; } else if ( v5 == Number ) { disas_t32_extract_ldstd_ri8 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; @@v28@@ = Number ; @@v27@@ = Number ; result = ( unsigned __int8 ) trans_STRD_ri_t32 ( @@a1@@ , & @@v26@@ ) != Number ; } else if ( v5 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { switch ( ( unsigned __int8 ) @@a2@@ >> Number ) { case Number : disas_t32_extract_tbranch ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( BYTE1 ( @@a2@@ ) == Number ) result = ( unsigned __int8 ) trans_TBB ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_tbranch ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( BYTE1 ( @@a2@@ ) == Number ) result = ( unsigned __int8 ) trans_TBH ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_ldrex_0 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDREXB ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_ldrex_0 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDREXH ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_ldrex_d ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDREXD_t32 ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_ldrex_0 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDAB ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_ldrex_0 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDAH ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_ldrex_0 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDA ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_ldrex_0 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDAEXB ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_ldrex_0 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDAEXH ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_ldrex_0 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDAEX ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_ldrex_d ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_LDAEXD_t32 ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; default : result = Number L ; break ; } } else { disas_t32_extract_ldrex_i ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_LDREX ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; } } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { switch ( ( unsigned __int8 ) @@a2@@ >> Number ) { case Number : disas_t32_extract_strex_0 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_STREXB ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_strex_0 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_STREXH ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_strex_d ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STREXD_t32 ( @@a1@@ , & @@v26@@ ) != Number ; break ; case Number : disas_t32_extract_ldrex_0 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_STLB ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_ldrex_0 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_STLH ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_ldrex_0 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_STL ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_strex_0 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_STLEXB ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_strex_0 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_STLEXH ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_strex_0 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_STLEX ( @@a1@@ , & @@v26@@ ) != Number ; else result = Number L ; break ; case Number : disas_t32_extract_strex_d ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STLEXD_t32 ( @@a1@@ , & @@v26@@ ) != Number ; break ; default : result = Number L ; break ; } } else if ( ( @@a2@@ & Number ) == Number && ( disas_t32_extract_disas_t32_Fmt_48 ( @@a1@@ , & @@v26@@ , @@a2@@ ) , ( unsigned __int8 ) trans_TT ( @@a1@@ , & @@v26@@ ) ) ) { result = Number L ; } else { disas_t32_extract_strex_i ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_STREX ( @@a1@@ , & @@v26@@ ) != Number ; } return result ; } } } } } } } return Number L ; } if ( v2 != Number ) return Number L ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { switch ( ( @@a2@@ >> Number ) & Number ) { case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_t32_extract_s_rri_rot ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_BIC_rri ( @@a1@@ , & @@v26@@ ) != Number ; } else if ( ( @@a2@@ & Number ) == Number && ( disas_t32_extract_S_xri_rot ( @@a1@@ , & @@v26@@ , @@a2@@ ) , ( unsigned __int8 ) trans_TST_xri ( @@a1@@ , & @@v26@@ ) ) ) { result = Number L ; } else { disas_t32_extract_s_rri_rot ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_AND_rri ( @@a1@@ , & @@v26@@ ) != Number ; } break ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number && ( disas_t32_extract_s_rxi_rot ( @@a1@@ , & @@v26@@ , @@a2@@ ) , ( unsigned __int8 ) trans_MVN_rxi ( @@a1@@ , & @@v26@@ ) ) ) { result = Number L ; } else { disas_t32_extract_s_rri_rot ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_ORN_rri ( @@a1@@ , & @@v26@@ ) != Number ; } } else if ( ( @@a2@@ & Number ) == Number && ( disas_t32_extract_s_rxi_rot ( @@a1@@ , & @@v26@@ , @@a2@@ ) , ( unsigned __int8 ) trans_MOV_rxi ( @@a1@@ , & @@v26@@ ) ) ) { result = Number L ; } else { disas_t32_extract_s_rri_rot ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_ORR_rri ( @@a1@@ , & @@v26@@ ) != Number ; } break ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { result = Number L ; } else if ( ( @@a2@@ & Number ) == Number && ( disas_t32_extract_S_xri_rot ( @@a1@@ , & @@v26@@ , @@a2@@ ) , ( unsigned __int8 ) trans_TEQ_xri ( @@a1@@ , & @@v26@@ ) ) ) { result = Number L ; } else { disas_t32_extract_s_rri_rot ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_EOR_rri ( @@a1@@ , & @@v26@@ ) != Number ; } break ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { result = Number L ; } else if ( ( @@a2@@ & Number ) == Number && ( disas_t32_extract_S_xri_rot ( @@a1@@ , & @@v26@@ , @@a2@@ ) , ( unsigned __int8 ) trans_CMN_xri ( @@a1@@ , & @@v26@@ ) ) ) { result = Number L ; } else { disas_t32_extract_s_rri_rot ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_ADD_rri ( @@a1@@ , & @@v26@@ ) != Number ; } break ; case Number : disas_t32_extract_s_rri_rot ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_SBC_rri ( @@a1@@ , & @@v26@@ ) != Number ; else result = ( unsigned __int8 ) trans_ADC_rri ( @@a1@@ , & @@v26@@ ) != Number ; break ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { if ( ( @@a2@@ & Number ) == Number && ( disas_t32_extract_S_xri_rot ( @@a1@@ , & @@v26@@ , @@a2@@ ) , ( unsigned __int8 ) trans_CMP_xri ( @@a1@@ , & @@v26@@ ) ) ) { result = Number L ; } else { disas_t32_extract_s_rri_rot ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_SUB_rri ( @@a1@@ , & @@v26@@ ) != Number ; } } else { result = Number L ; } break ; case Number : disas_t32_extract_s_rri_rot ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_RSB_rri ( @@a1@@ , & @@v26@@ ) != Number ; break ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { result = Number L ; } else if ( ( @@a2@@ & Number ) == Number && ( disas_t32_extract_disas_t32_Fmt_9 ( @@a1@@ , & @@v26@@ , @@a2@@ ) , ( unsigned __int8 ) trans_ADR ( @@a1@@ , & @@v26@@ ) ) ) { result = Number L ; } else { disas_t32_extract_s0_rri_12 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_ADD_rri ( @@a1@@ , & @@v26@@ ) != Number ; } break ; case Number : disas_t32_extract_mov16 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_MOVW ( @@a1@@ , & @@v26@@ ) != Number ; break ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { if ( ( @@a2@@ & Number ) == Number && ( disas_t32_extract_disas_t32_Fmt_10 ( @@a1@@ , & @@v26@@ , @@a2@@ ) , ( unsigned __int8 ) trans_ADR ( @@a1@@ , & @@v26@@ ) ) ) { result = Number L ; } else { disas_t32_extract_s0_rri_12 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_SUB_rri ( @@a1@@ , & @@v26@@ ) != Number ; } } else { result = Number L ; } break ; case Number : disas_t32_extract_mov16 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_MOVT ( @@a1@@ , & @@v26@@ ) != Number ; break ; case Number : if ( ( @@a2@@ & Number ) != Number ) { result = Number L ; } else if ( ( @@a2@@ & Number ) == Number && ( disas_t32_extract_sat16 ( @@a1@@ , & @@v26@@ , @@a2@@ ) , ( unsigned __int8 ) trans_SSAT16 ( @@a1@@ , & @@v26@@ ) ) ) { result = Number L ; } else { disas_t32_extract_sat ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_SSAT ( @@a1@@ , & @@v26@@ ) != Number ; } break ; case Number : if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_bfi ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_BFCI ( @@a1@@ , & @@v26@@ ) != Number ; } else { result = Number L ; } } else { disas_t32_extract_bfx ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_SBFX ( @@a1@@ , & @@v26@@ ) != Number ; } break ; case Number : if ( ( @@a2@@ & Number ) != Number ) { result = Number L ; } else if ( ( @@a2@@ & Number ) == Number && ( disas_t32_extract_sat16 ( @@a1@@ , & @@v26@@ , @@a2@@ ) , ( unsigned __int8 ) trans_USAT16 ( @@a1@@ , & @@v26@@ ) ) ) { result = Number L ; } else { disas_t32_extract_sat ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_USAT ( @@a1@@ , & @@v26@@ ) != Number ; } break ; case Number : disas_t32_extract_bfx ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_UBFX ( @@a1@@ , & @@v26@@ ) != Number ; break ; default : result = Number L ; break ; } return result ; } v11 = @@a2@@ & Number ; if ( v11 == Number ) { disas_t32_extract_branch24 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_BL ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v11 > Number ) return Number L ; if ( v11 == Number ) { disas_t32_extract_branch24 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_BLX_i ( @@a1@@ , & @@v26@@ ) != Number ; } if ( v11 > Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { if ( v11 == Number ) { disas_t32_extract_branch24 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_B ( @@a1@@ , & @@v26@@ ) != Number ; } return Number L ; } if ( ( @@a2@@ & Number ) != Number ) goto LABEL_350 ; if ( ( @@a2@@ & Number ) == Number ) { if ( ( unsigned __int8 ) @@a2@@ == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_YIELD ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( unsigned __int8 ) @@a2@@ == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_WFE ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( unsigned __int8 ) @@a2@@ == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_WFI ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_23 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_CPS ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_CLREX ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_DSB ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_DMB ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_ISB ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_SB ( @@a1@@ , & @@v26@@ ) ) return Number L ; } } if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_24 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_MRS_bank ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_25 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_MRS_reg ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_26 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_MRS_v7m ( @@a1@@ , & @@v26@@ ) ) return Number L ; } } if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_27 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_MSR_bank ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ! ( _BYTE ) @@a2@@ ) { disas_t32_extract_disas_t32_Fmt_28 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_MSR_reg ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_29 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_MSR_v7m ( @@a1@@ , & @@v26@@ ) ) return Number L ; } } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_30 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_BXJ ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { if ( ! ( _BYTE ) @@a2@@ ) { disas_t32_extract_disas_t32_Fmt_22 ( ) ; if ( ( unsigned __int8 ) trans_ERET ( @@a1@@ , & @@v26@@ ) ) return Number L ; } disas_t32_extract_disas_t32_Fmt_31 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_SUB_rri ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_32 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_SMC ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t32_extract_disas_t32_Fmt_33 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_HVC ( @@a1@@ , & @@v26@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number && ( disas_t32_extract_disas_t32_Fmt_22 ( ) , ( unsigned __int8 ) trans_UDF ( @@a1@@ , & @@v26@@ ) ) ) { result = Number L ; } else { LABEL_350 : disas_t32_extract_disas_t32_Fmt_34 ( @@a1@@ , & @@v26@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_B_cond_thumb ( @@a1@@ , & @@v26@@ ) != Number ; } } return result ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v28\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s24\"}, {\"n\": \"v27\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s44\"}, {\"n\": \"v26\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s48\"}, {\"n\": \"v29\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "disas_thumb_insn", "code": "__int64 __fastcall disas_thumb_insn ( __int64 @@a1@@ , unsigned __int16 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = ( unsigned int ) disas_t16 ( @@a1@@ , @@a2@@ ) ^ Number ; if ( ( _BYTE ) @@result@@ ) @@result@@ = unallocated_encoding ( @@a1@@ ) ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned __int16", "s": 2}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]} | [{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,516 | [
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"disas_t16\", \"code\": \"_BOOL8 __fastcall disas_t16 ( __int64 @@a1@@ , unsigned __int16 @@a2@@ ) { _BOOL8 result ; int v3 ; int v4 ; int v5 ; int v6 ; int v7 ; int v8 ; int v9 ; int v10 ; int v11 ; int @@v12@@ ; int @@v13@@ ; int @@v14@@ ; _BOOL4 @@v15@@ ; int @@v16@@ ; unsigned __int64 @@v17@@ ; @@v17@@ = __readfsqword ( Number ) ; switch ( ( @@a2@@ >> Number ) & Number ) { case Number : disas_t16_extract_shift_i ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; @@v16@@ = ( ( @@a2@@ >> Number ) & Number ) != Number ; return ( unsigned __int8 ) trans_MOV_rxri ( @@a1@@ , & @@v12@@ ) != Number ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { v3 = ( @@a2@@ >> Number ) & Number ; if ( v3 == Number ) { disas_t16_extract_addsub_2i ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_SUB_rri ( @@a1@@ , & @@v12@@ ) != Number ; } else if ( v3 == Number ) { disas_t16_extract_addsub_2i ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_ADD_rri ( @@a1@@ , & @@v12@@ ) != Number ; } else if ( v3 ) { disas_t16_extract_addsub_3 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_SUB_rrri ( @@a1@@ , & @@v12@@ ) != Number ; } else { disas_t16_extract_addsub_3 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_ADD_rrri ( @@a1@@ , & @@v12@@ ) != Number ; } } else { disas_t16_extract_shift_i ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; @@v16@@ = Number ; result = ( unsigned __int8 ) trans_MOV_rxri ( @@a1@@ , & @@v12@@ ) != Number ; } return result ; case Number : disas_t16_extract_arith_1i ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { @@v15@@ = Number ; result = ( unsigned __int8 ) trans_CMP_xri ( @@a1@@ , & @@v12@@ ) != Number ; } else { @@v15@@ = t16_setflags ( @@a1@@ ) ; result = ( unsigned __int8 ) trans_MOV_rxi ( @@a1@@ , & @@v12@@ ) != Number ; } return result ; case Number : disas_t16_extract_arith_1i ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; @@v15@@ = t16_setflags ( @@a1@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_SUB_rri ( @@a1@@ , & @@v12@@ ) != Number ; else result = ( unsigned __int8 ) trans_ADD_rri ( @@a1@@ , & @@v12@@ ) != Number ; return result ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_t16_extract_ldst_spec_i ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; @@v13@@ = Number ; return ( unsigned __int8 ) trans_LDR_ri ( @@a1@@ , & @@v12@@ ) != Number ; } switch ( HIBYTE ( @@a2@@ ) & Number ) { case Number : v4 = ( @@a2@@ >> Number ) & Number ; if ( v4 == Number ) { disas_t16_extract_lxl_shr ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; @@v16@@ = Number ; result = ( unsigned __int8 ) trans_MOV_rxrr ( @@a1@@ , & @@v12@@ ) != Number ; } else if ( v4 == Number ) { disas_t16_extract_lxl_shr ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; @@v16@@ = Number ; result = ( unsigned __int8 ) trans_MOV_rxrr ( @@a1@@ , & @@v12@@ ) != Number ; } else if ( v4 ) { disas_t16_extract_lll_noshr ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_EOR_rrri ( @@a1@@ , & @@v12@@ ) != Number ; } else { disas_t16_extract_lll_noshr ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_AND_rrri ( @@a1@@ , & @@v12@@ ) != Number ; } return result ; case Number : v5 = ( @@a2@@ >> Number ) & Number ; if ( v5 == Number ) { disas_t16_extract_lxl_shr ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; @@v16@@ = Number ; result = ( unsigned __int8 ) trans_MOV_rxrr ( @@a1@@ , & @@v12@@ ) != Number ; } else if ( v5 == Number ) { disas_t16_extract_lll_noshr ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_SBC_rrri ( @@a1@@ , & @@v12@@ ) != Number ; } else if ( v5 ) { disas_t16_extract_lll_noshr ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_ADC_rrri ( @@a1@@ , & @@v12@@ ) != Number ; } else { disas_t16_extract_lxl_shr ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; @@v16@@ = Number ; result = ( unsigned __int8 ) trans_MOV_rxrr ( @@a1@@ , & @@v12@@ ) != Number ; } return result ; case Number : v6 = ( @@a2@@ >> Number ) & Number ; if ( v6 == Number ) { disas_t16_extract_xll_noshr ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_CMN_xrri ( @@a1@@ , & @@v12@@ ) != Number ; } else if ( v6 == Number ) { disas_t16_extract_xll_noshr ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_CMP_xrri ( @@a1@@ , & @@v12@@ ) != Number ; } else if ( v6 ) { disas_t16_extract_disas_t16_Fmt_3 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_RSB_rri ( @@a1@@ , & @@v12@@ ) != Number ; } else { disas_t16_extract_xll_noshr ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_TST_xrri ( @@a1@@ , & @@v12@@ ) != Number ; } return result ; case Number : v7 = ( @@a2@@ >> Number ) & Number ; if ( v7 == Number ) { disas_t16_extract_lll_noshr ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_MVN_rxri ( @@a1@@ , & @@v12@@ ) != Number ; } else if ( v7 == Number ) { disas_t16_extract_lll_noshr ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_BIC_rrri ( @@a1@@ , & @@v12@@ ) != Number ; } else if ( v7 ) { disas_t16_extract_disas_t16_Fmt_4 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_MUL ( @@a1@@ , & @@v12@@ ) != Number ; } else { disas_t16_extract_lll_noshr ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_ORR_rrri ( @@a1@@ , & @@v12@@ ) != Number ; } return result ; case Number : disas_t16_extract_addsub_2h ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; @@v14@@ = Number ; return ( unsigned __int8 ) trans_ADD_rrri ( @@a1@@ , & @@v12@@ ) != Number ; case Number : disas_t16_extract_addsub_2h ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; @@v14@@ = Number ; return ( unsigned __int8 ) trans_CMP_xrri ( @@a1@@ , & @@v12@@ ) != Number ; case Number : disas_t16_extract_addsub_2h ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; @@v14@@ = Number ; return ( unsigned __int8 ) trans_MOV_rxri ( @@a1@@ , & @@v12@@ ) != Number ; case Number : disas_t16_extract_branchr ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; v8 = @@a2@@ & Number ; if ( v8 == Number ) { result = ( unsigned __int8 ) trans_BLXNS ( @@a1@@ , & @@v12@@ ) != Number ; } else { if ( ( @@a2@@ & Number ) <= Number ) { if ( v8 == Number ) return ( unsigned __int8 ) trans_BLX_r ( @@a1@@ , & @@v12@@ ) != Number ; if ( ( @@a2@@ & Number ) <= Number ) { if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_BX ( @@a1@@ , & @@v12@@ ) != Number ; if ( v8 == Number ) return ( unsigned __int8 ) trans_BXNS ( @@a1@@ , & @@v12@@ ) != Number ; } } result = Number L ; } break ; default : return Number L ; } return result ; case Number : disas_t16_extract_ldst_rr ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; switch ( ( @@a2@@ >> Number ) & Number ) { case Number : result = ( unsigned __int8 ) trans_STR_rr ( @@a1@@ , & @@v12@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_STRH_rr ( @@a1@@ , & @@v12@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_STRB_rr ( @@a1@@ , & @@v12@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_LDRSB_rr ( @@a1@@ , & @@v12@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_LDR_rr ( @@a1@@ , & @@v12@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_LDRH_rr ( @@a1@@ , & @@v12@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_LDRB_rr ( @@a1@@ , & @@v12@@ ) != Number ; break ; case Number : result = ( unsigned __int8 ) trans_LDRSH_rr ( @@a1@@ , & @@v12@@ ) != Number ; break ; default : result = Number L ; break ; } return result ; case Number : disas_t16_extract_ldst_ri_4 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) goto LABEL_77 ; goto LABEL_76 ; case Number : disas_t16_extract_ldst_ri_1 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_LDRB_ri ( @@a1@@ , & @@v12@@ ) != Number ; else result = ( unsigned __int8 ) trans_STRB_ri ( @@a1@@ , & @@v12@@ ) != Number ; return result ; case Number : disas_t16_extract_ldst_ri_2 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_LDRH_ri ( @@a1@@ , & @@v12@@ ) != Number ; else result = ( unsigned __int8 ) trans_STRH_ri ( @@a1@@ , & @@v12@@ ) != Number ; return result ; case Number : disas_t16_extract_ldst_spec_i ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; @@v13@@ = Number ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) LABEL_76 : result = ( unsigned __int8 ) trans_LDR_ri ( @@a1@@ , & @@v12@@ ) != Number ; else LABEL_77 : result = ( unsigned __int8 ) trans_STR_ri ( @@a1@@ , & @@v12@@ ) != Number ; return result ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_t16_extract_disas_t16_Fmt_11 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_ADD_rri ( @@a1@@ , & @@v12@@ ) != Number ; } else { disas_t16_extract_disas_t16_Fmt_10 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_ADR ( @@a1@@ , & @@v12@@ ) != Number ; } return result ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { v10 = @@a2@@ & Number ; if ( v10 == Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t16_extract_disas_t16_Fmt_28 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_BKPT ( @@a1@@ , & @@v12@@ ) != Number ; } if ( ( @@a2@@ & Number ) != Number ) goto LABEL_155 ; if ( ( @@a2@@ & Number ) == Number ) { disas_t16_extract_disas_t16_Fmt_25 ( @@a1@@ , ( __int64 ) & @@v12@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_YIELD ( @@a1@@ , & @@v12@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t16_extract_disas_t16_Fmt_25 ( @@a1@@ , ( __int64 ) & @@v12@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_WFE ( @@a1@@ , & @@v12@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t16_extract_disas_t16_Fmt_25 ( @@a1@@ , ( __int64 ) & @@v12@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_WFI ( @@a1@@ , & @@v12@@ ) ) return Number L ; } disas_t16_extract_disas_t16_Fmt_25 ( @@a1@@ , ( __int64 ) & @@v12@@ , @@a2@@ ) ; if ( ! ( unsigned __int8 ) trans_NOP ( @@a1@@ , & @@v12@@ ) ) { LABEL_155 : disas_t16_extract_disas_t16_Fmt_26 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_IT ( @@a1@@ , & @@v12@@ ) != Number ; } else { result = Number L ; } } else { if ( ( @@a2@@ & Number ) > Number ) goto LABEL_156 ; if ( v10 == Number ) { disas_t16_extract_disas_t16_Fmt_31 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_LDM_t16 ( @@a1@@ , & @@v12@@ ) != Number ; } if ( ( @@a2@@ & Number ) > Number ) goto LABEL_156 ; if ( ( @@a2@@ & Number ) == Number ) { disas_t16_extract_disas_t16_Fmt_30 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_STM ( @@a1@@ , & @@v12@@ ) != Number ; } if ( v10 == Number ) { v11 = ( @@a2@@ >> Number ) & Number ; if ( v11 == Number ) { disas_t16_extract_disas_t16_Fmt_21 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_SETEND ( @@a1@@ , & @@v12@@ ) != Number ; else result = Number L ; } else if ( v11 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { result = Number L ; } else { disas_t16_extract_disas_t16_Fmt_22 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_CPS ( @@a1@@ , & @@v12@@ ) ) { result = Number L ; } else { result = Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_t16_extract_disas_t16_Fmt_23 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_CPS_v7m ( @@a1@@ , & @@v12@@ ) ) result = Number ; } } } } else { result = Number L ; } } else { LABEL_156 : result = Number L ; } } } else { if ( ( @@a2@@ & Number ) != Number ) { disas_t16_extract_disas_t16_Fmt_29 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_CBZ ( @@a1@@ , & @@v12@@ ) != Number ; } v9 = @@a2@@ & Number ; if ( v9 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_t16_extract_rdm ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_REVSH ( @@a1@@ , & @@v12@@ ) != Number ; } else { disas_t16_extract_disas_t16_Fmt_27 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_HLT ( @@a1@@ , & @@v12@@ ) != Number ; } } else { if ( ( @@a2@@ & Number ) > Number ) return Number L ; if ( v9 == Number ) { disas_t16_extract_rdm ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_REV16 ( @@a1@@ , & @@v12@@ ) != Number ; else result = ( unsigned __int8 ) trans_REV ( @@a1@@ , & @@v12@@ ) != Number ; return result ; } if ( ( @@a2@@ & Number ) > Number ) return Number L ; if ( v9 == Number ) { disas_t16_extract_extend ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_UXTAB ( @@a1@@ , & @@v12@@ ) != Number ; else result = ( unsigned __int8 ) trans_UXTAH ( @@a1@@ , & @@v12@@ ) != Number ; return result ; } if ( ( @@a2@@ & Number ) > Number ) return Number L ; if ( v9 != Number ) { if ( ( @@a2@@ & Number ) <= Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_t16_extract_addsub_sp_i ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_ADD_rri ( @@a1@@ , & @@v12@@ ) != Number ; } if ( v9 == Number ) { disas_t16_extract_addsub_sp_i ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_SUB_rri ( @@a1@@ , & @@v12@@ ) != Number ; } } return Number L ; } disas_t16_extract_extend ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_SXTAB ( @@a1@@ , & @@v12@@ ) != Number ; else result = ( unsigned __int8 ) trans_SXTAH ( @@a1@@ , & @@v12@@ ) != Number ; } } return result ; case Number : disas_t16_extract_ldstm ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_LDM_t16 ( @@a1@@ , & @@v12@@ ) != Number ; else result = ( unsigned __int8 ) trans_STM ( @@a1@@ , & @@v12@@ ) != Number ; return result ; case Number : if ( ( @@a2@@ & Number ) == Number ) { disas_t16_extract_disas_t16_Fmt_25 ( @@a1@@ , ( __int64 ) & @@v12@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_UDF ( @@a1@@ , & @@v12@@ ) ) return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { disas_t16_extract_disas_t16_Fmt_28 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; if ( ( unsigned __int8 ) trans_SVC ( @@a1@@ , & @@v12@@ ) ) return Number L ; } disas_t16_extract_disas_t16_Fmt_32 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_B_cond_thumb ( @@a1@@ , & @@v12@@ ) != Number ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_t16_extract_disas_t16_Fmt_34 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_BLX_suffix ( @@a1@@ , & @@v12@@ ) != Number ; } else { disas_t16_extract_disas_t16_Fmt_33 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_B ( @@a1@@ , & @@v12@@ ) != Number ; } return result ; case Number : if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_t16_extract_disas_t16_Fmt_34 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_BL_suffix ( @@a1@@ , & @@v12@@ ) != Number ; } else { disas_t16_extract_disas_t16_Fmt_35 ( @@a1@@ , & @@v12@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_BL_BLX_prefix ( @@a1@@ , & @@v12@@ ) != Number ; } return result ; default : return Number L ; } }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int16\", \"s\": 2}, \"location\": \"r64\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s28\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"_BOOL4\", \"s\": 4}, \"location\": \"s32\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s40\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s48\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "insn_crosses_page", "code": "_BOOL8 __fastcall insn_crosses_page ( __int64 @@a1@@ , __int64 @@a2@@ ) { unsigned __int16 @@v3@@ ; @@v3@@ = arm_lduw_code ( @@a1@@ , * ( _QWORD * ) ( @@a2@@ + Number ) , * ( _DWORD * ) ( @@a2@@ + Number ) != Number ) ; return ! thumb_insn_is_16bit ( @@a2@@ , * ( _QWORD * ) ( @@a2@@ + Number ) , @@v3@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int16", "s": 2}, "location": "s2"}]} | [{"n": "env", "t": {"T": 3, "t": "CPUARMState_0"}, "location": "r56"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s2"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,517 | [
"{\"name\": \"arm_lduw_code\", \"code\": \"__int64 __fastcall arm_lduw_code ( __int64 @@a1@@ , __int64 @@a2@@ , unsigned __int8 @@a3@@ ) { char @@v3@@ ; __int64 @@v5@@ ; @@v5@@ = @@a2@@ ; if ( @@a3@@ ) @@v5@@ = @@a2@@ ^ Number ; @@v3@@ = bswap_code ( @@a3@@ ) ; return translator_lduw_swap ( @@a1@@ , @@v5@@ , @@v3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r8\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}]}",
"{\"name\": \"thumb_insn_is_16bit\", \"code\": \"_BOOL8 __fastcall thumb_insn_is_16bit ( __int64 @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { if ( @@a3@@ >> Number <= Number ) return Number L ; if ( arm_dc_feature ( @@a1@@ , Number ) || arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; return @@a3@@ >> Number != Number || ( unsigned __int64 ) @@a2@@ - * ( _QWORD * ) ( @@a1@@ + Number ) >= ( int ) ( Number - target_page [ Number ] ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "arm_tr_init_disas_context", "code": "__int64 __fastcall arm_tr_init_disas_context ( __int64 @@a1@@ , __int64 @@a2@@ ) { bool v2 ; int @@v3@@ ; bool v4 ; __int64 v5 ; int v6 ; __int64 result ; unsigned int @@v8@@ ; unsigned int @@v9@@ ; int @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; @@v11@@ = * ( _QWORD * ) ( @@a2@@ + Number ) ; @@v12@@ = env_archcpu ( @@v11@@ ) ; @@v8@@ = * ( _DWORD * ) ( * ( _QWORD * ) @@a1@@ + Number L ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = @@v12@@ + Number ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; v2 = arm_feature ( @@v11@@ , Number ) && ! arm_el_is_aa64 ( @@v11@@ , Number ) ; * ( _BYTE * ) ( @@a1@@ + Number ) = v2 ; * ( _DWORD * ) ( @@a1@@ + Number ) = extract32 ( @@v8@@ , Number , Number ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = extract32 ( @@v8@@ , Number , Number ) ; if ( ( unsigned int ) extract32 ( @@v8@@ , Number , Number ) ) @@v3@@ = Number ; else @@v3@@ = Number ; * ( _DWORD * ) ( @@a1@@ + Number ) = @@v3@@ ; @@v9@@ = extract32 ( @@v8@@ , Number , Number ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = ( Number * ( _BYTE ) @@v9@@ ) & Number ; * ( _DWORD * ) ( @@a1@@ + Number ) = @@v9@@ >> Number ; @@v10@@ = extract32 ( @@v8@@ , Number , Number ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = core_to_arm_mmu_idx ( @@v11@@ , @@v10@@ ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = arm_mmu_idx_to_el ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = * ( _DWORD * ) ( @@a1@@ + Number ) == Number ; * ( _BYTE * ) ( @@a1@@ + Number ) = ( unsigned int ) extract32 ( @@v8@@ , Number , Number ) != Number ; * ( _DWORD * ) ( @@a1@@ + Number ) = extract32 ( @@v8@@ , Number , Number ) ; * ( _BYTE * ) ( @@a1@@ + Number ) = ( unsigned int ) extract32 ( @@v8@@ , Number , Number ) != Number ; * ( _DWORD * ) ( @@a1@@ + Number ) = extract32 ( @@v8@@ , Number , Number ) ; if ( arm_feature ( @@v11@@ , Number ) ) { * ( _DWORD * ) ( @@a1@@ + Number ) = extract32 ( @@v8@@ , Number , Number ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } else { * ( _DWORD * ) ( @@a1@@ + Number ) = extract32 ( @@v8@@ , Number , Number ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } * ( _BYTE * ) ( @@a1@@ + Number ) = ( unsigned int ) extract32 ( @@v8@@ , Number , Number ) != Number ; v4 = arm_feature ( @@v11@@ , Number ) && ( unsigned __int8 ) regime_is_secure ( @@v11@@ , * ( _DWORD * ) ( @@a1@@ + Number ) ) ; * ( _BYTE * ) ( @@a1@@ + Number ) = v4 ; * ( _BYTE * ) ( @@a1@@ + Number ) = ( unsigned int ) extract32 ( @@v8@@ , Number , Number ) != Number ; * ( _BYTE * ) ( @@a1@@ + Number ) = ( unsigned int ) extract32 ( @@v8@@ , Number , Number ) != Number ; * ( _BYTE * ) ( @@a1@@ + Number ) = ( unsigned int ) extract32 ( @@v8@@ , Number , Number ) != Number ; * ( _BYTE * ) ( @@a1@@ + Number ) = ( unsigned int ) extract32 ( @@v8@@ , Number , Number ) != Number ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) ( @@v12@@ + Number ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) ( @@v11@@ + Number ) ; * ( _BYTE * ) ( @@a1@@ + Number ) = ( unsigned int ) extract32 ( @@v8@@ , Number , Number ) != Number ; * ( _BYTE * ) ( @@a1@@ + Number ) = ( unsigned int ) extract32 ( @@v8@@ , Number , Number ) != Number ; * ( _BYTE * ) ( @@a1@@ + Number ) = Number ; v5 = Number L ; if ( ! arm_feature ( @@v11@@ , Number ) ) { v5 = Number L ; * ( _DWORD * ) ( @@a1@@ + Number ) = extract32 ( @@v8@@ , Number , Number ) ; } * ( _QWORD * ) ( @@a1@@ + Number ) = * ( _QWORD * ) ( @@a1@@ + Number ) & target_page [ Number ] ; if ( is_singlestepping ( @@a1@@ ) ) * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; if ( ! * ( _DWORD * ) ( @@a1@@ + Number ) ) { v6 = * ( _DWORD * ) ( @@a1@@ + Number ) ; if ( ( int ) ( - ( target_page [ Number ] | * ( _QWORD * ) ( @@a1@@ + Number ) ) >> Number ) <= v6 ) v6 = - ( target_page [ Number ] | * ( _QWORD * ) ( @@a1@@ + Number ) ) >> Number ; * ( _DWORD * ) ( @@a1@@ + Number ) = v6 ; } cpu_V0 = tcg_temp_new_i64 ( @@a1@@ , v5 ) ; cpu_V1 = tcg_temp_new_i64 ( @@a1@@ , v5 ) ; result = tcg_temp_new_i64 ( @@a1@@ , v5 ) ; cpu_M0 = result ; return result ; }", "source": [{"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v11", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v10", "t": {"T": 1, "n": "int", "s": 4}, "location": "s40"}, {"n": "v9", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s44"}, {"n": "v8", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s48"}, {"n": "v12", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "", "t": {"T": 10}, "location": "r16"}, {"n": "dcbase", "t": {"T": 3, "t": "DisasContextBase_0"}, "location": "r56"}, {"n": "cs_0", "t": {"T": 3, "t": "CPUState_0"}, "location": "r64"}, {"n": "env", "t": {"T": 3, "t": "CPUARMState_0"}, "location": "s16"}, {"n": "", "t": {"T": 10}, "location": "s40"}, {"n": "condexec", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s44"}, {"n": "tb_flags", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s48"}, {"n": "cpu", "t": {"T": 3, "t": "ARMCPU_0"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,518 | [
"{\"name\": \"extract32\", \"code\": \"__int64 __fastcall extract32 ( unsigned int @@a1@@ , int @@a2@@ , int @@a3@@ ) { if ( @@a2@@ < Number || @@a3@@ <= Number || @@a3@@ > Number - @@a2@@ ) _assert_fail ( String , String , Number , String ) ; return ( @@a1@@ >> @@a2@@ ) & ( Number >> ( Number - @@a3@@ ) ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_feature\", \"code\": \"_BOOL8 __fastcall arm_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_el_is_aa64\", \"code\": \"_BOOL8 __fastcall arm_el_is_aa64 ( __int64 @@a1@@ , int @@a2@@ ) { bool v3 ; bool v4 ; bool @@v5@@ ; if ( @@a2@@ <= Number || @@a2@@ > Number ) _assert_fail ( String , String , Number , String ) ; @@v5@@ = arm_feature ( @@a1@@ , Number ) ; if ( @@a2@@ == Number ) return @@v5@@ ; if ( arm_feature ( @@a1@@ , Number ) ) { v3 = @@v5@@ && ( * ( _QWORD * ) ( @@a1@@ + Number ) & Number ) != Number ; @@v5@@ = v3 ; } if ( @@a2@@ == Number ) return @@v5@@ ; if ( arm_feature ( @@a1@@ , Number ) && ! arm_is_secure_below_el3 ( @@a1@@ ) ) { v4 = @@v5@@ && ( * ( _QWORD * ) ( @@a1@@ + Number ) & Number ) != Number ; @@v5@@ = v4 ; } return @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s1\"}]}",
"{\"name\": \"core_to_arm_mmu_idx\", \"code\": \"__int64 __fastcall core_to_arm_mmu_idx ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@result@@ ; if ( arm_feature ( @@a1@@ , Number ) ) @@result@@ = @@a2@@ | Number ; else @@result@@ = @@a2@@ | Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_mmu_idx_to_el\", \"code\": \"__int64 __fastcall arm_mmu_idx_to_el ( int @@a1@@ ) { if ( ( @@a1@@ & Number ) == Number ) return @@a1@@ & Number ; if ( ( @@a1@@ & Number ) == Number ) return @@a1@@ & Number ; return g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"env_archcpu\", \"code\": \"__int64 __fastcall env_archcpu ( __int64 @@a1@@ ) { return @@a1@@ - Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"regime_is_secure\", \"code\": \"__int64 __fastcall regime_is_secure ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@result@@ ; switch ( @@a2@@ ) { case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : @@result@@ = Number L ; break ; case Number : case Number : case Number : case Number : case Number : case Number : case Number : @@result@@ = Number L ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"is_singlestepping\", \"code\": \"_BOOL8 __fastcall is_singlestepping ( __int64 @@a1@@ ) { return * ( _BYTE * ) ( @@a1@@ + Number ) || * ( _BYTE * ) ( @@a1@@ + Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}"
] |
{"name": "arm_tr_tb_start", "code": "__int64 __fastcall arm_tr_tb_start ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; __int64 @@v3@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) || ( @@result@@ = * ( unsigned int * ) ( @@a1@@ + Number ) , ( _DWORD ) @@result@@ ) ) { @@v3@@ = tcg_temp_new_i32 ( @@a1@@ , @@a2@@ ) ; tcg_gen_movi_i32 ( @@v3@@ , Number ) ; @@result@@ = store_cpu_offset ( @@v3@@ , Number ) ; } return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]} | [{"n": "dcbase", "t": {"T": 3, "t": "DisasContextBase_0"}, "location": "r56"}, {"n": "cpu", "t": {"T": 3, "t": "CPUState_0"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,519 | [
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"store_cpu_offset\", \"code\": \"__int64 __fastcall store_cpu_offset ( __int64 @@a1@@ , int @@a2@@ ) { tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "arm_tr_insn_start", "code": "__int64 __fastcall arm_tr_insn_start ( __int64 @@a1@@ ) { __int64 @@v1@@ ; __int64 v2 ; __int64 @@v3@@ ; __int64 @@result@@ ; @@v1@@ = ( Number * * ( _DWORD * ) ( @@a1@@ + Number ) ) | ( * ( int * ) ( @@a1@@ + Number ) >> Number ) ; v2 = * ( _QWORD * ) ( @@a1@@ + Number ) ; tcg_gen_insn_start ( v2 , @@v1@@ , Number L ) ; @@result@@ = tcg_last_op ( v2 , @@v1@@ , @@v3@@ ) ; * ( _QWORD * ) ( @@a1@@ + Number ) = @@result@@ ; return @@result@@ ; }", "source": [{"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "v1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]} | [{"n": "", "t": {"T": 10}, "location": "r16"}, {"n": "dcbase", "t": {"T": 3, "t": "DisasContextBase_0"}, "location": "r56"}, {"n": "cpu", "t": {"T": 3, "t": "CPUState_0"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}] | data1/train-shard-4.tar | 0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl | 1,520 | [
"{\"name\": \"tcg_gen_insn_start\", \"code\": \"__int64 __fastcall tcg_gen_insn_start ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3 ( Number L , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
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