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-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fadd_3_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fadd_3_full_dsp_32;
ARCHITECTURE ANN_ap_fadd_3_full_dsp_32_arch OF ANN_ap_fadd_3_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fadd_3_full_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fadd_3_full_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fadd_3_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fadd_3_full_dsp_32;
ARCHITECTURE ANN_ap_fadd_3_full_dsp_32_arch OF ANN_ap_fadd_3_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fadd_3_full_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fadd_3_full_dsp_32_arch;
|
--
-- user_app.vhd - user application code
--
-- This module is an implementation of the 'user_app' component that can be
-- commanded to perform a memory test of some or all of the memory banks.
--
-- SYNTHESIZABLE
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
library work;
use work.memif.all;
use work.memory_common.all;
use work.user_defs.all;
entity user_app is
port(
rst : in std_logic; -- Reset from memory clock domain
clk : in std_logic; -- Clock from memory clock domain
-- To/from local bus interface
reg_in : in std_logic_vector(31 downto 0); -- Incoming register write values
reg_wr : in std_logic_vector(255 downto 0); -- Byte write enables for 'reg_in'
reg_out : out std_logic_vector(2047 downto 0); -- Outgoing register values
-- To/from memory banks
valid : in control_vector_t(max_num_bank - 1 downto 0);
q : in data_vector_t(max_num_bank - 1 downto 0);
qtag : in tag_vector_t(max_num_bank - 1 downto 0);
ready : in control_vector_t(max_num_bank - 1 downto 0);
req : out control_vector_t(max_num_bank - 1 downto 0);
ce : out control_vector_t(max_num_bank - 1 downto 0);
w : out control_vector_t(max_num_bank - 1 downto 0);
a : out address_vector_t(max_num_bank - 1 downto 0);
tag : out tag_vector_t(max_num_bank - 1 downto 0);
d : out data_vector_t(max_num_bank - 1 downto 0);
be : out be_vector_t(max_num_bank - 1 downto 0));
end entity;
architecture mixed of user_app is
type user_vector_t is array(0 to 63) of std_logic_vector(31 downto 0);
signal user_out : user_vector_t;
type user_wr_vector_t is array(0 to 63) of std_logic_vector(3 downto 0);
signal user_wr : user_wr_vector_t;
signal user_enable : std_logic;
signal refresh : std_logic;
signal image_size : std_logic_vector(rd_width(0)- 1 downto 0);
signal image_width : std_logic_vector(9 downto 0);
signal user_flag : std_logic;
signal pos_x : std_logic_vector(9 downto 0);
signal pos_y : std_logic_vector(9 downto 0);
signal debug_signal0 : std_logic_vector(rd_width(0)- 1 downto 0);
signal debug_signal1 : std_logic_vector(rd_width(0)- 1 downto 0);
signal debug_signal2 : std_logic_vector(rd_width(0)- 1 downto 0);
signal debug_signal3 : std_logic_vector(rd_width(0)- 1 downto 0);
signal is_end : std_logic;
constant user_bank_present : boolean_vector_t :=
(0 => true, 1 => true, others => false);
component filter
generic(
ADDRESS_WIDTH : natural;
DATA_WIDTH : natural;
TAG_WIDTH : natural);
port(
request0 : out std_logic;
request1 : out std_logic;
command_entry0 : out std_logic;
command_entry1 : out std_logic;
write_enable1 : out std_logic;
address0 : out std_logic_vector(max_address_width - 1 downto 0);
address1 : out std_logic_vector(max_address_width - 1 downto 0);
tag0 : out std_logic_vector(tag_width - 1 downto 0);
data_out1 : out std_logic_vector(bank_width(1) - 1 downto 0);
is_end : out std_logic;
debug_signal0 : out std_logic_vector(31 downto 0);
debug_signal1 : out std_logic_vector(31 downto 0);
debug_signal2 : out std_logic_vector(31 downto 0);
debug_signal3 : out std_logic_vector(31 downto 0);
valid0 : in std_logic;
valid1 : in std_logic;
query0 : in std_logic_vector(bank_width(0) - 1 downto 0);
qtag0 : in std_logic_vector(tag_width - 1 downto 0);
ready0 : in std_logic;
ready1 : in std_logic;
image_size : in std_logic_vector(32 - 1 downto 0);
image_width : in std_logic_vector(9 downto 0);
user_flag : in std_logic;
pos_x : in std_logic_vector(9 downto 0);
pos_y : in std_logic_vector(9 downto 0);
refresh : in std_logic;
reset : in std_logic;
clock : in std_logic);
end component;
begin
-- Divide 'reg_wr' into an array of 64 x 4-bit vectors for easy access
gen_user_in : for i in 0 to 63 generate
user_wr(i) <= reg_wr(4 * i + 3 downto 4 * i);
end generate;
-- Combine the 64 32-bit registers of 'user_out' into the vector 'reg_out'
gen_reg_out : for i in 0 to 63 generate
reg_out(32 * i + 31 downto 32 * i) <= user_out(i);
end generate;
set_refresh: process(rst, clk) begin
if rst = '1' then
refresh <= '0';
elsif clk'event and clk = '1' then
if user_wr(0)(0) = '1' then
refresh <= reg_in(0);
end if;
end if;
end process;
set_user_enable: process(rst, clk) begin
if rst = '1' then
user_enable <= '0';
elsif clk'event and clk = '1' then
if user_wr(1)(0) = '1' then
user_enable <= reg_in(0);
end if;
end if;
end process;
set_image_size : process(rst, clk) begin
if rst = '1' then
image_size <= (others => '0');
elsif clk'event and clk = '1' then
for j in 0 to 3 loop
if user_wr(2)(j) = '1' then
image_size(8 * j + 7 downto 8 * j) <= reg_in(8 * j + 7 downto 8 * j);
end if;
end loop;
end if;
end process;
set_image_width : process(rst, clk) begin
if rst = '1' then
image_width <= (others => '0');
elsif clk'event and clk = '1' then
if user_wr(3)(0) = '1' then
image_width(7 downto 0) <= reg_in(7 downto 0);
end if;
if user_wr(3)(1) = '1' then
image_width(9 downto 8) <= reg_in(9 downto 8);
end if;
end if;
end process;
set_user_flag : process(rst, clk) begin
if rst = '1' then
user_flag <= '0';
elsif clk'event and clk = '1' then
if user_wr(4)(0) = '1' then
user_flag <= reg_in(0);
end if;
end if;
end process;
set_pos_x : process(rst, clk) begin
if rst = '1' then
pos_x <= (others => '0');
elsif clk'event and clk = '1' then
if user_wr(5)(0) = '1' then
pos_x(7 downto 0) <= reg_in(7 downto 0);
end if;
if user_wr(5)(1) = '1' then
pos_x(9 downto 8) <= reg_in(9 downto 8);
end if;
end if;
end process;
set_pos_y : process(rst, clk) begin
if rst = '1' then
pos_y <= (others => '0');
elsif clk'event and clk = '1' then
if user_wr(6)(0) = '1' then
pos_y(7 downto 0) <= reg_in(7 downto 0);
end if;
if user_wr(6)(1) = '1' then
pos_y(9 downto 8) <= reg_in(9 downto 8);
end if;
end if;
end process;
user_out(0)(0) <= refresh;
user_out(0)(31 downto 1) <= (others => '0');
user_out(1)(0) <= user_enable;
user_out(1)(31 downto 1) <= (others => '0');
user_out(2) <= image_size;
user_out(3)(9 downto 0) <= image_width;
user_out(3)(31 downto 10) <= (others => '0');
user_out(4)(0) <= user_flag;
user_out(4)(31 downto 1) <= (others => '0');
user_out(5)(9 downto 0) <= pos_x;
user_out(5)(31 downto 10) <= (others => '0');
user_out(6)(9 downto 0) <= pos_y;
user_out(6)(31 downto 10) <= (others => '0');
user_out(32)(0) <= is_end;
user_out(32)(31 downto 1) <= (others => '0');
user_out(60) <= debug_signal0;
user_out(61) <= debug_signal1;
user_out(62) <= debug_signal2;
user_out(63) <= debug_signal3;
-- Unused regisers return undefined
user_out(7 to 31) <= (others => (others => '0'));
-- user_out(33 to 61) <= (others => (others => '-'));
user_out(33 to 59) <= (others => (others => '0'));
w(0) <= '0';
tag(1) <= (others => '0');
d(0) <= (others => '0');
d(1)(max_data_width - 1 downto bank_width(1)) <= (others => '0');
be(0) <= (others => '1');
be(1) <= (others => '1');
filter0 : filter
generic map(
ADDRESS_WIDTH => max_address_width,
DATA_WIDTH => bank_width(0),
TAG_WIDTH => tag_width)
port map(
request0 => req(0),
request1 => req(1),
command_entry0 => ce(0),
command_entry1 => ce(1),
write_enable1 => w(1),
address0 => a(0),
address1 => a(1),
tag0 => tag(0),
data_out1 => d(1)(bank_width(0) - 1 downto 0),
is_end => is_end,
debug_signal0 => debug_signal0,
debug_signal1 => debug_signal1,
debug_signal2 => debug_signal2,
debug_signal3 => debug_signal3,
valid0 => valid(0),
valid1 => valid(1),
query0 => q(0)(bank_width(0) - 1 downto 0),
qtag0 => qtag(0),
ready0 => ready(0),
ready1 => ready(1),
image_size => image_size,
image_width => image_width,
user_flag => user_flag,
pos_x => pos_x,
pos_y => pos_y,
refresh => refresh,
reset => rst,
clock => clk);
gen_memory_test : for i in 0 to max_num_bank - 1 generate
-- Generate dummy code for nonexistent memory banks
gen_dummy : if not user_bank_present(i) generate
req(i) <= '0';
ce(i) <= '0';
w(i) <= '-';
a(i) <= (others => '-');
tag(i) <= (others => '-');
d(i) <= (others => '-');
be(i) <= (others => '-');
end generate;
end generate;
-- gen_memory_test : for i in 0 to max_num_bank - 1 generate
-- req(i) <= '0';
-- ce(i) <= '0';
-- w(i) <= '-';
-- a(i) <= (others => '-');
-- tag(i) <= (others => '-');
-- d(i) <= (others => '-');
-- be(i) <= (others => '-');
-- end generate;
end architecture;
|
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
-- use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity scc is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
busy : out std_logic; -- 0 processing, 1 otherwise
done : out std_logic; -- 1 done processing, 0 other
-- SCC Parameters
color_in : in std_logic_vector(63 downto 0); -- Color all nodes in the SCC with that color
scc_addr_in : in std_logic_vector(63 downto 0);
nextv_out : out std_logic_vector(63 downto 0); -- Possible start node for next SCC
-- Graph/ReversedGraph Pointers
n_in : in std_logic_vector(63 downto 0);
graph_info_in : in std_logic_vector(63 downto 0);
rgraph_info_in : in std_logic_vector(63 downto 0);
-- Reach queues pointers
fw_addr_in : in std_logic_vector(63 downto 0);
fw_count_in : in std_logic_vector(63 downto 0);
bw_addr_in : in std_logic_vector(63 downto 0);
bw_count_in : in std_logic_vector(63 downto 0);
-- ae-to-ae signals
ae_id : in std_logic_vector(1 downto 0); -- Application Engine ID
nxtae_rx_data : in std_logic_vector(31 downto 0);
nxtae_rx_vld : in std_logic;
prvae_rx_data : in std_logic_vector(31 downto 0);
prvae_rx_vld : in std_logic;
nxtae_tx_data : out std_logic_vector(31 downto 0);
nxtae_tx_vld : out std_logic;
prvae_tx_data : out std_logic_vector(31 downto 0);
prvae_tx_vld : out std_logic;
-- MC0 port signals
mc0_req_ld : out std_logic;
mc0_req_st : out std_logic;
mc0_req_size : out std_logic_vector(1 downto 0);
mc0_req_vaddr : out std_logic_vector(47 downto 0);
mc0_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc0_req_flush : out std_logic;
mc0_rd_rq_stall : in std_logic;
mc0_wr_rq_stall : in std_logic;
mc0_rsp_push : in std_logic;
mc0_rsp_stall : out std_logic;
mc0_rsp_data : in std_logic_vector(63 downto 0);
mc0_rsp_rdctl : in std_logic_vector(31 downto 0);
mc0_rsp_flush_cmplt : in std_logic;
-- MC1 port signals
mc1_req_ld : out std_logic;
mc1_req_st : out std_logic;
mc1_req_size : out std_logic_vector(1 downto 0);
mc1_req_vaddr : out std_logic_vector(47 downto 0);
mc1_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc1_req_flush : out std_logic;
mc1_rd_rq_stall : in std_logic;
mc1_wr_rq_stall : in std_logic;
mc1_rsp_push : in std_logic;
mc1_rsp_stall : out std_logic;
mc1_rsp_data : in std_logic_vector(63 downto 0);
mc1_rsp_rdctl : in std_logic_vector(31 downto 0);
mc1_rsp_flush_cmplt : in std_logic;
-- MC2 port signals
mc2_req_ld : out std_logic;
mc2_req_st : out std_logic;
mc2_req_size : out std_logic_vector(1 downto 0);
mc2_req_vaddr : out std_logic_vector(47 downto 0);
mc2_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc2_req_flush : out std_logic;
mc2_rd_rq_stall : in std_logic;
mc2_wr_rq_stall : in std_logic;
mc2_rsp_push : in std_logic;
mc2_rsp_stall : out std_logic;
mc2_rsp_data : in std_logic_vector(63 downto 0);
mc2_rsp_rdctl : in std_logic_vector(31 downto 0);
mc2_rsp_flush_cmplt : in std_logic;
-- MC3 port signals
mc3_req_ld : out std_logic;
mc3_req_st : out std_logic;
mc3_req_size : out std_logic_vector(1 downto 0);
mc3_req_vaddr : out std_logic_vector(47 downto 0);
mc3_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc3_req_flush : out std_logic;
mc3_rd_rq_stall : in std_logic;
mc3_wr_rq_stall : in std_logic;
mc3_rsp_push : in std_logic;
mc3_rsp_stall : out std_logic;
mc3_rsp_data : in std_logic_vector(63 downto 0);
mc3_rsp_rdctl : in std_logic_vector(31 downto 0);
mc3_rsp_flush_cmplt : in std_logic;
-- MC4 port signals
mc4_req_ld : out std_logic;
mc4_req_st : out std_logic;
mc4_req_size : out std_logic_vector(1 downto 0);
mc4_req_vaddr : out std_logic_vector(47 downto 0);
mc4_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc4_req_flush : out std_logic;
mc4_rd_rq_stall : in std_logic;
mc4_wr_rq_stall : in std_logic;
mc4_rsp_push : in std_logic;
mc4_rsp_stall : out std_logic;
mc4_rsp_data : in std_logic_vector(63 downto 0);
mc4_rsp_rdctl : in std_logic_vector(31 downto 0);
mc4_rsp_flush_cmplt : in std_logic;
-- MC5 port signals
mc5_req_ld : out std_logic;
mc5_req_st : out std_logic;
mc5_req_size : out std_logic_vector(1 downto 0);
mc5_req_vaddr : out std_logic_vector(47 downto 0);
mc5_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc5_req_flush : out std_logic;
mc5_rd_rq_stall : in std_logic;
mc5_wr_rq_stall : in std_logic;
mc5_rsp_push : in std_logic;
mc5_rsp_stall : out std_logic;
mc5_rsp_data : in std_logic_vector(63 downto 0);
mc5_rsp_rdctl : in std_logic_vector(31 downto 0);
mc5_rsp_flush_cmplt : in std_logic;
-- MC6 port signals
mc6_req_ld : out std_logic;
mc6_req_st : out std_logic;
mc6_req_size : out std_logic_vector(1 downto 0);
mc6_req_vaddr : out std_logic_vector(47 downto 0);
mc6_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc6_req_flush : out std_logic;
mc6_rd_rq_stall : in std_logic;
mc6_wr_rq_stall : in std_logic;
mc6_rsp_push : in std_logic;
mc6_rsp_stall : out std_logic;
mc6_rsp_data : in std_logic_vector(63 downto 0);
mc6_rsp_rdctl : in std_logic_vector(31 downto 0);
mc6_rsp_flush_cmplt : in std_logic;
-- MC7 port signals
mc7_req_ld : out std_logic;
mc7_req_st : out std_logic;
mc7_req_size : out std_logic_vector(1 downto 0);
mc7_req_vaddr : out std_logic_vector(47 downto 0);
mc7_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc7_req_flush : out std_logic;
mc7_rd_rq_stall : in std_logic;
mc7_wr_rq_stall : in std_logic;
mc7_rsp_push : in std_logic;
mc7_rsp_stall : out std_logic;
mc7_rsp_data : in std_logic_vector(63 downto 0);
mc7_rsp_rdctl : in std_logic_vector(31 downto 0);
mc7_rsp_flush_cmplt : in std_logic;
-- MC8 port signals
mc8_req_ld : out std_logic;
mc8_req_st : out std_logic;
mc8_req_size : out std_logic_vector(1 downto 0);
mc8_req_vaddr : out std_logic_vector(47 downto 0);
mc8_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc8_req_flush : out std_logic;
mc8_rd_rq_stall : in std_logic;
mc8_wr_rq_stall : in std_logic;
mc8_rsp_push : in std_logic;
mc8_rsp_stall : out std_logic;
mc8_rsp_data : in std_logic_vector(63 downto 0);
mc8_rsp_rdctl : in std_logic_vector(31 downto 0);
mc8_rsp_flush_cmplt : in std_logic;
-- MC9 port signals
mc9_req_ld : out std_logic;
mc9_req_st : out std_logic;
mc9_req_size : out std_logic_vector(1 downto 0);
mc9_req_vaddr : out std_logic_vector(47 downto 0);
mc9_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc9_req_flush : out std_logic;
mc9_rd_rq_stall : in std_logic;
mc9_wr_rq_stall : in std_logic;
mc9_rsp_push : in std_logic;
mc9_rsp_stall : out std_logic;
mc9_rsp_data : in std_logic_vector(63 downto 0);
mc9_rsp_rdctl : in std_logic_vector(31 downto 0);
mc9_rsp_flush_cmplt : in std_logic;
-- MC10 port signals
mc10_req_ld : out std_logic;
mc10_req_st : out std_logic;
mc10_req_size : out std_logic_vector(1 downto 0);
mc10_req_vaddr : out std_logic_vector(47 downto 0);
mc10_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc10_req_flush : out std_logic;
mc10_rd_rq_stall : in std_logic;
mc10_wr_rq_stall : in std_logic;
mc10_rsp_push : in std_logic;
mc10_rsp_stall : out std_logic;
mc10_rsp_data : in std_logic_vector(63 downto 0);
mc10_rsp_rdctl : in std_logic_vector(31 downto 0);
mc10_rsp_flush_cmplt: in std_logic;
-- MC11 port signals
mc11_req_ld : out std_logic;
mc11_req_st : out std_logic;
mc11_req_size : out std_logic_vector(1 downto 0);
mc11_req_vaddr : out std_logic_vector(47 downto 0);
mc11_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc11_req_flush : out std_logic;
mc11_rd_rq_stall : in std_logic;
mc11_wr_rq_stall : in std_logic;
mc11_rsp_push : in std_logic;
mc11_rsp_stall : out std_logic;
mc11_rsp_data : in std_logic_vector(63 downto 0);
mc11_rsp_rdctl : in std_logic_vector(31 downto 0);
mc11_rsp_flush_cmplt: in std_logic;
-- MC12 port signals
mc12_req_ld : out std_logic;
mc12_req_st : out std_logic;
mc12_req_size : out std_logic_vector(1 downto 0);
mc12_req_vaddr : out std_logic_vector(47 downto 0);
mc12_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc12_req_flush : out std_logic;
mc12_rd_rq_stall : in std_logic;
mc12_wr_rq_stall : in std_logic;
mc12_rsp_push : in std_logic;
mc12_rsp_stall : out std_logic;
mc12_rsp_data : in std_logic_vector(63 downto 0);
mc12_rsp_rdctl : in std_logic_vector(31 downto 0);
mc12_rsp_flush_cmplt: in std_logic;
-- MC13 port signals
mc13_req_ld : out std_logic;
mc13_req_st : out std_logic;
mc13_req_size : out std_logic_vector(1 downto 0);
mc13_req_vaddr : out std_logic_vector(47 downto 0);
mc13_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc13_req_flush : out std_logic;
mc13_rd_rq_stall : in std_logic;
mc13_wr_rq_stall : in std_logic;
mc13_rsp_push : in std_logic;
mc13_rsp_stall : out std_logic;
mc13_rsp_data : in std_logic_vector(63 downto 0);
mc13_rsp_rdctl : in std_logic_vector(31 downto 0);
mc13_rsp_flush_cmplt: in std_logic;
-- MC14 port signals
mc14_req_ld : out std_logic;
mc14_req_st : out std_logic;
mc14_req_size : out std_logic_vector(1 downto 0);
mc14_req_vaddr : out std_logic_vector(47 downto 0);
mc14_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc14_req_flush : out std_logic;
mc14_rd_rq_stall : in std_logic;
mc14_wr_rq_stall : in std_logic;
mc14_rsp_push : in std_logic;
mc14_rsp_stall : out std_logic;
mc14_rsp_data : in std_logic_vector(63 downto 0);
mc14_rsp_rdctl : in std_logic_vector(31 downto 0);
mc14_rsp_flush_cmplt: in std_logic;
-- MC15 port signals
mc15_req_ld : out std_logic;
mc15_req_st : out std_logic;
mc15_req_size : out std_logic_vector(1 downto 0);
mc15_req_vaddr : out std_logic_vector(47 downto 0);
mc15_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc15_req_flush : out std_logic;
mc15_rd_rq_stall : in std_logic;
mc15_wr_rq_stall : in std_logic;
mc15_rsp_push : in std_logic;
mc15_rsp_stall : out std_logic;
mc15_rsp_data : in std_logic_vector(63 downto 0);
mc15_rsp_rdctl : in std_logic_vector(31 downto 0);
mc15_rsp_flush_cmplt: in std_logic
);
end entity;
architecture arch of scc is
component scc_kernel is
port (
-- control signals
clk : in std_logic;
rst : in std_logic;
enable : in std_logic;
busy : out std_logic; -- 0 processing, 1 otherwise
done : out std_logic; -- 1 done processing, 0 other
-- Kernel Parameters
kernel_id : in unsigned(7 downto 0); -- Kernel ID
ae_id : in std_logic_vector(1 downto 0); -- Application Engine ID
kernels_count : in unsigned(7 downto 0);
-- kernels communication signals
kernel_tx_vld : out std_logic; -- 1 if found nextv
kernel_tx_nextv : out std_logic_vector(63 downto 0);
kernel_rx_vld : in std_logic;
kernel_rx_nextv : in std_logic_vector(63 downto 0);
-- Input Graph Prameters (Represented in Custom CSR)
N : in std_logic_vector(63 downto 0);
graph_info : in std_logic_vector(63 downto 0);
rgraph_info : in std_logic_vector(63 downto 0);
-- SCC intersection parameters
color : in std_logic_vector(63 downto 0); -- Color to be used to color nodes
fw_queue : in std_logic_vector(63 downto 0); -- FW Reach queue pointer (could be FW or BW reach queue)
fw_count : in std_logic_vector(63 downto 0); -- Number of nodes in FW reach queue
bw_queue : in std_logic_vector(63 downto 0); -- BW Reach queue pointer (could be FW or BW reach queue)
bw_count : in std_logic_vector(63 downto 0); -- Number of nodes in BW reach queue
scc_results : in std_logic_vector(63 downto 0); -- Where we store the color of each node
-- Parameters for next kernel
nxtk_rst : out std_logic;
nxtk_enable : out std_logic;
nextk_busy : in std_logic;
nextk_done : in std_logic;
nxtk_N : out std_logic_vector(63 downto 0);
nxtk_graph_info : out std_logic_vector(63 downto 0);
nxtk_rgraph_info : out std_logic_vector(63 downto 0);
nxtk_color : out std_logic_vector(63 downto 0);
nxtk_fw_queue : out std_logic_vector(63 downto 0);
nxtk_fw_count : out std_logic_vector(63 downto 0);
nxtk_bw_queue : out std_logic_vector(63 downto 0);
nxtk_bw_count : out std_logic_vector(63 downto 0);
nxtk_scc_results : out std_logic_vector(63 downto 0);
-- MC request port signals
mc_req_ld : out std_logic;
mc_req_st : out std_logic;
mc_req_size : out std_logic_vector(1 downto 0);
mc_req_vaddr : out std_logic_vector(47 downto 0);
mc_req_wrd_rdctl : out std_logic_vector(63 downto 0);
mc_rd_rq_stall : in std_logic;
mc_wr_rq_stall : in std_logic;
-- MC response port signals
mc_rsp_push : in std_logic;
mc_rsp_stall : out std_logic;
mc_rsp_data : in std_logic_vector(63 downto 0);
mc_rsp_rdctl : in std_logic_vector(31 downto 0);
-- MC flush signals
mc_req_flush : out std_logic;
mc_rsp_flush_cmplt : in std_logic
);
end component;
-- Input signals
signal n : std_logic_vector(63 downto 0);
signal color : std_logic_vector(63 downto 0);
signal scc_addr : std_logic_vector(63 downto 0);
signal graph_info : std_logic_vector(63 downto 0);
signal rgraph_info : std_logic_vector(63 downto 0);
signal fw_addr : std_logic_vector(63 downto 0);
signal fw_count : std_logic_vector(63 downto 0);
signal bw_addr : std_logic_vector(63 downto 0);
signal bw_count : std_logic_vector(63 downto 0);
-- Master Process Signals
signal r_rst : std_logic;
signal r_enable : std_logic;
signal kernels_count : unsigned(7 downto 0) := x"20"; -- 64 kernels = 0x40 , 32 kernels = 0x32
type state is (st_idle, st_start, st_wait, st_busy, st_done);
signal scc_state : state;
-- Kernels control signals
signal kernels_enable : std_logic;
signal kernels_done : std_logic;
signal kernels_busy : std_logic;
-- Kernel-to-kernel communication signals
type array_of_slv64 is array (0 to 15) of std_logic_vector(63 downto 0);
signal kernel_tx_vld : std_logic_vector(15 downto 0);
signal kernel_tx_nextv : array_of_slv64;
signal nxtk_rst : std_logic_vector(15 downto 0);
signal nxtk_enable : std_logic_vector(15 downto 0);
signal nextk_busy : std_logic_vector(15 downto 0);
signal nextk_done : std_logic_vector(15 downto 0);
signal nxtk_N : array_of_slv64;
signal nxtk_graph_info : array_of_slv64;
signal nxtk_rgraph_info : array_of_slv64;
signal nxtk_color : array_of_slv64;
signal nxtk_fw_queue : array_of_slv64;
signal nxtk_fw_count : array_of_slv64;
signal nxtk_bw_queue : array_of_slv64;
signal nxtk_bw_count : array_of_slv64;
signal nxtk_scc_results : array_of_slv64;
signal master_tx_vld : std_logic;
signal master_tx_nextv : std_logic_vector(63 downto 0);
signal k2k_start : std_logic;
signal k0_rx_vld : std_logic;
begin
-- CyGraph Kernel 0
k0 : scc_kernel
port map (
-- control signals
clk => clk,
rst => r_rst,
enable => kernels_enable,
busy => kernels_busy,
done => kernels_done,
-- Kernel Parameters
kernel_id => x"00",
ae_id => ae_id,
kernels_count => kernels_count,
-- kernels communication signals
kernel_tx_vld => kernel_tx_vld(0),
kernel_tx_nextv => kernel_tx_nextv(0),
kernel_rx_vld => k0_rx_vld,
kernel_rx_nextv => master_tx_nextv,
-- Input Graph Prameters (Represented in Custom CSR)
N => n,
graph_info => graph_info,
rgraph_info => rgraph_info,
-- SCC intersection parameters
color => color,
fw_queue => fw_addr,
fw_count => fw_count,
bw_queue => bw_addr,
bw_count => bw_count,
scc_results => scc_addr,
-- Parameters for next kernel
nxtk_rst => nxtk_rst(0),
nxtk_enable => nxtk_enable(0),
nextk_busy => nextk_busy(0),
nextk_done => nextk_done(0),
nxtk_N => nxtk_N(0),
nxtk_graph_info => nxtk_graph_info(0),
nxtk_rgraph_info => nxtk_rgraph_info(0),
nxtk_color => nxtk_color(0),
nxtk_fw_queue => nxtk_fw_queue(0),
nxtk_fw_count => nxtk_fw_count(0),
nxtk_bw_queue => nxtk_bw_queue(0),
nxtk_bw_count => nxtk_bw_count(0),
nxtk_scc_results => nxtk_scc_results(0),
-- MC0 request port signals
mc_req_ld => mc0_req_ld,
mc_req_st => mc0_req_st,
mc_req_size => mc0_req_size,
mc_req_vaddr => mc0_req_vaddr,
mc_req_wrd_rdctl => mc0_req_wrd_rdctl,
mc_rd_rq_stall => mc0_rd_rq_stall,
mc_wr_rq_stall => mc0_wr_rq_stall,
-- MC0 response port signals
mc_rsp_push => mc0_rsp_push,
mc_rsp_stall => mc0_rsp_stall,
mc_rsp_data => mc0_rsp_data,
mc_rsp_rdctl => mc0_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc0_req_flush,
mc_rsp_flush_cmplt => mc0_rsp_flush_cmplt
);
-- CyGraph Kernel 1
k1 : scc_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(0),
enable => nxtk_enable(0),
busy => nextk_busy(0),
done => nextk_done(0),
-- Kernel Parameters
kernel_id => x"01",
ae_id => ae_id,
kernels_count => kernels_count,
-- kernels communication signals
kernel_tx_vld => kernel_tx_vld(1),
kernel_tx_nextv => kernel_tx_nextv(1),
kernel_rx_vld => kernel_tx_vld(0),
kernel_rx_nextv => kernel_tx_nextv(0),
-- Input Graph Prameters (Represented in Custom CSR)
N => nxtk_N(0),
graph_info => nxtk_graph_info(0),
rgraph_info => nxtk_rgraph_info(0),
-- SCC intersection parameters
color => nxtk_color(0),
fw_queue => nxtk_fw_queue(0),
fw_count => nxtk_fw_count(0),
bw_queue => nxtk_bw_queue(0),
bw_count => nxtk_bw_count(0),
scc_results => nxtk_scc_results(0),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(1),
nxtk_enable => nxtk_enable(1),
nextk_busy => nextk_busy(1),
nextk_done => nextk_done(1),
nxtk_N => nxtk_N(1),
nxtk_graph_info => nxtk_graph_info(1),
nxtk_rgraph_info => nxtk_rgraph_info(1),
nxtk_color => nxtk_color(1),
nxtk_fw_queue => nxtk_fw_queue(1),
nxtk_fw_count => nxtk_fw_count(1),
nxtk_bw_queue => nxtk_bw_queue(1),
nxtk_bw_count => nxtk_bw_count(1),
nxtk_scc_results => nxtk_scc_results(1),
-- MC1 request port signals
mc_req_ld => mc1_req_ld,
mc_req_st => mc1_req_st,
mc_req_size => mc1_req_size,
mc_req_vaddr => mc1_req_vaddr,
mc_req_wrd_rdctl => mc1_req_wrd_rdctl,
mc_rd_rq_stall => mc1_rd_rq_stall,
mc_wr_rq_stall => mc1_wr_rq_stall,
-- MC1 response port signals
mc_rsp_push => mc1_rsp_push,
mc_rsp_stall => mc1_rsp_stall,
mc_rsp_data => mc1_rsp_data,
mc_rsp_rdctl => mc1_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc1_req_flush,
mc_rsp_flush_cmplt => mc1_rsp_flush_cmplt
);
-- CyGraph Kernel 2
k2 : scc_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(1),
enable => nxtk_enable(1),
busy => nextk_busy(1),
done => nextk_done(1),
-- Kernel Parameters
kernel_id => x"02",
ae_id => ae_id,
kernels_count => kernels_count,
-- kernels communication signals
kernel_tx_vld => kernel_tx_vld(2),
kernel_tx_nextv => kernel_tx_nextv(2),
kernel_rx_vld => kernel_tx_vld(1),
kernel_rx_nextv => kernel_tx_nextv(1),
-- Input Graph Prameters (Represented in Custom CSR)
N => nxtk_N(1),
graph_info => nxtk_graph_info(1),
rgraph_info => nxtk_rgraph_info(1),
-- SCC intersection parameters
color => nxtk_color(1),
fw_queue => nxtk_fw_queue(1),
fw_count => nxtk_fw_count(1),
bw_queue => nxtk_bw_queue(1),
bw_count => nxtk_bw_count(1),
scc_results => nxtk_scc_results(1),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(2),
nxtk_enable => nxtk_enable(2),
nextk_busy => nextk_busy(2),
nextk_done => nextk_done(2),
nxtk_N => nxtk_N(2),
nxtk_graph_info => nxtk_graph_info(2),
nxtk_rgraph_info => nxtk_rgraph_info(2),
nxtk_color => nxtk_color(2),
nxtk_fw_queue => nxtk_fw_queue(2),
nxtk_fw_count => nxtk_fw_count(2),
nxtk_bw_queue => nxtk_bw_queue(2),
nxtk_bw_count => nxtk_bw_count(2),
nxtk_scc_results => nxtk_scc_results(2),
-- MC2 request port signals
mc_req_ld => mc2_req_ld,
mc_req_st => mc2_req_st,
mc_req_size => mc2_req_size,
mc_req_vaddr => mc2_req_vaddr,
mc_req_wrd_rdctl => mc2_req_wrd_rdctl,
mc_rd_rq_stall => mc2_rd_rq_stall,
mc_wr_rq_stall => mc2_wr_rq_stall,
-- MC2 response port signals
mc_rsp_push => mc2_rsp_push,
mc_rsp_stall => mc2_rsp_stall,
mc_rsp_data => mc2_rsp_data,
mc_rsp_rdctl => mc2_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc2_req_flush,
mc_rsp_flush_cmplt => mc2_rsp_flush_cmplt
);
-- CyGraph Kernel 3
k3 : scc_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(2),
enable => nxtk_enable(2),
busy => nextk_busy(2),
done => nextk_done(2),
-- Kernel Parameters
kernel_id => x"03",
ae_id => ae_id,
kernels_count => kernels_count,
-- kernels communication signals
kernel_tx_vld => kernel_tx_vld(3),
kernel_tx_nextv => kernel_tx_nextv(3),
kernel_rx_vld => kernel_tx_vld(2),
kernel_rx_nextv => kernel_tx_nextv(2),
-- Input Graph Prameters (Represented in Custom CSR)
N => nxtk_N(2),
graph_info => nxtk_graph_info(2),
rgraph_info => nxtk_rgraph_info(2),
-- SCC intersection parameters
color => nxtk_color(2),
fw_queue => nxtk_fw_queue(2),
fw_count => nxtk_fw_count(2),
bw_queue => nxtk_bw_queue(2),
bw_count => nxtk_bw_count(2),
scc_results => nxtk_scc_results(2),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(3),
nxtk_enable => nxtk_enable(3),
nextk_busy => nextk_busy(3),
nextk_done => nextk_done(3),
nxtk_N => nxtk_N(3),
nxtk_graph_info => nxtk_graph_info(3),
nxtk_rgraph_info => nxtk_rgraph_info(3),
nxtk_color => nxtk_color(3),
nxtk_fw_queue => nxtk_fw_queue(3),
nxtk_fw_count => nxtk_fw_count(3),
nxtk_bw_queue => nxtk_bw_queue(3),
nxtk_bw_count => nxtk_bw_count(3),
nxtk_scc_results => nxtk_scc_results(3),
-- MC3 request port signals
mc_req_ld => mc3_req_ld,
mc_req_st => mc3_req_st,
mc_req_size => mc3_req_size,
mc_req_vaddr => mc3_req_vaddr,
mc_req_wrd_rdctl => mc3_req_wrd_rdctl,
mc_rd_rq_stall => mc3_rd_rq_stall,
mc_wr_rq_stall => mc3_wr_rq_stall,
-- MC3 response port signals
mc_rsp_push => mc3_rsp_push,
mc_rsp_stall => mc3_rsp_stall,
mc_rsp_data => mc3_rsp_data,
mc_rsp_rdctl => mc3_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc3_req_flush,
mc_rsp_flush_cmplt => mc3_rsp_flush_cmplt
);
-- CyGraph Kernel 4
k4 : scc_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(3),
enable => nxtk_enable(3),
busy => nextk_busy(3),
done => nextk_done(3),
-- Kernel Parameters
kernel_id => x"04",
ae_id => ae_id,
kernels_count => kernels_count,
-- kernels communication signals
kernel_tx_vld => kernel_tx_vld(4),
kernel_tx_nextv => kernel_tx_nextv(4),
kernel_rx_vld => kernel_tx_vld(3),
kernel_rx_nextv => kernel_tx_nextv(3),
-- Input Graph Prameters (Represented in Custom CSR)
N => nxtk_N(3),
graph_info => nxtk_graph_info(3),
rgraph_info => nxtk_rgraph_info(3),
-- SCC intersection parameters
color => nxtk_color(3),
fw_queue => nxtk_fw_queue(3),
fw_count => nxtk_fw_count(3),
bw_queue => nxtk_bw_queue(3),
bw_count => nxtk_bw_count(3),
scc_results => nxtk_scc_results(3),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(4),
nxtk_enable => nxtk_enable(4),
nextk_busy => nextk_busy(4),
nextk_done => nextk_done(4),
nxtk_N => nxtk_N(4),
nxtk_graph_info => nxtk_graph_info(4),
nxtk_rgraph_info => nxtk_rgraph_info(4),
nxtk_color => nxtk_color(4),
nxtk_fw_queue => nxtk_fw_queue(4),
nxtk_fw_count => nxtk_fw_count(4),
nxtk_bw_queue => nxtk_bw_queue(4),
nxtk_bw_count => nxtk_bw_count(4),
nxtk_scc_results => nxtk_scc_results(4),
-- MC4 request port signals
mc_req_ld => mc4_req_ld,
mc_req_st => mc4_req_st,
mc_req_size => mc4_req_size,
mc_req_vaddr => mc4_req_vaddr,
mc_req_wrd_rdctl => mc4_req_wrd_rdctl,
mc_rd_rq_stall => mc4_rd_rq_stall,
mc_wr_rq_stall => mc4_wr_rq_stall,
-- MC4 response port signals
mc_rsp_push => mc4_rsp_push,
mc_rsp_stall => mc4_rsp_stall,
mc_rsp_data => mc4_rsp_data,
mc_rsp_rdctl => mc4_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc4_req_flush,
mc_rsp_flush_cmplt => mc4_rsp_flush_cmplt
);
-- CyGraph Kernel 5
k5 : scc_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(4),
enable => nxtk_enable(4),
busy => nextk_busy(4),
done => nextk_done(4),
-- Kernel Parameters
kernel_id => x"05",
ae_id => ae_id,
kernels_count => kernels_count,
-- kernels communication signals
kernel_tx_vld => kernel_tx_vld(5),
kernel_tx_nextv => kernel_tx_nextv(5),
kernel_rx_vld => kernel_tx_vld(4),
kernel_rx_nextv => kernel_tx_nextv(4),
-- Input Graph Prameters (Represented in Custom CSR)
N => nxtk_N(4),
graph_info => nxtk_graph_info(4),
rgraph_info => nxtk_rgraph_info(4),
-- SCC intersection parameters
color => nxtk_color(4),
fw_queue => nxtk_fw_queue(4),
fw_count => nxtk_fw_count(4),
bw_queue => nxtk_bw_queue(4),
bw_count => nxtk_bw_count(4),
scc_results => nxtk_scc_results(4),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(5),
nxtk_enable => nxtk_enable(5),
nextk_busy => nextk_busy(5),
nextk_done => nextk_done(5),
nxtk_N => nxtk_N(5),
nxtk_graph_info => nxtk_graph_info(5),
nxtk_rgraph_info => nxtk_rgraph_info(5),
nxtk_color => nxtk_color(5),
nxtk_fw_queue => nxtk_fw_queue(5),
nxtk_fw_count => nxtk_fw_count(5),
nxtk_bw_queue => nxtk_bw_queue(5),
nxtk_bw_count => nxtk_bw_count(5),
nxtk_scc_results => nxtk_scc_results(5),
-- MC1 request port signals
mc_req_ld => mc5_req_ld,
mc_req_st => mc5_req_st,
mc_req_size => mc5_req_size,
mc_req_vaddr => mc5_req_vaddr,
mc_req_wrd_rdctl => mc5_req_wrd_rdctl,
mc_rd_rq_stall => mc5_rd_rq_stall,
mc_wr_rq_stall => mc5_wr_rq_stall,
-- MC1 response port signals
mc_rsp_push => mc5_rsp_push,
mc_rsp_stall => mc5_rsp_stall,
mc_rsp_data => mc5_rsp_data,
mc_rsp_rdctl => mc5_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc5_req_flush,
mc_rsp_flush_cmplt => mc5_rsp_flush_cmplt
);
-- CyGraph Kernel 6
k6 : scc_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(5),
enable => nxtk_enable(5),
busy => nextk_busy(5),
done => nextk_done(5),
-- Kernel Parameters
kernel_id => x"06",
ae_id => ae_id,
kernels_count => kernels_count,
-- kernels communication signals
kernel_tx_vld => kernel_tx_vld(6),
kernel_tx_nextv => kernel_tx_nextv(6),
kernel_rx_vld => kernel_tx_vld(5),
kernel_rx_nextv => kernel_tx_nextv(5),
-- Input Graph Prameters (Represented in Custom CSR)
N => nxtk_N(5),
graph_info => nxtk_graph_info(5),
rgraph_info => nxtk_rgraph_info(5),
-- SCC intersection parameters
color => nxtk_color(5),
fw_queue => nxtk_fw_queue(5),
fw_count => nxtk_fw_count(5),
bw_queue => nxtk_bw_queue(5),
bw_count => nxtk_bw_count(5),
scc_results => nxtk_scc_results(5),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(6),
nxtk_enable => nxtk_enable(6),
nextk_busy => nextk_busy(6),
nextk_done => nextk_done(6),
nxtk_N => nxtk_N(6),
nxtk_graph_info => nxtk_graph_info(6),
nxtk_rgraph_info => nxtk_rgraph_info(6),
nxtk_color => nxtk_color(6),
nxtk_fw_queue => nxtk_fw_queue(6),
nxtk_fw_count => nxtk_fw_count(6),
nxtk_bw_queue => nxtk_bw_queue(6),
nxtk_bw_count => nxtk_bw_count(6),
nxtk_scc_results => nxtk_scc_results(6),
-- MC6 request port signals
mc_req_ld => mc6_req_ld,
mc_req_st => mc6_req_st,
mc_req_size => mc6_req_size,
mc_req_vaddr => mc6_req_vaddr,
mc_req_wrd_rdctl => mc6_req_wrd_rdctl,
mc_rd_rq_stall => mc6_rd_rq_stall,
mc_wr_rq_stall => mc6_wr_rq_stall,
-- MC6 response port signals
mc_rsp_push => mc6_rsp_push,
mc_rsp_stall => mc6_rsp_stall,
mc_rsp_data => mc6_rsp_data,
mc_rsp_rdctl => mc6_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc6_req_flush,
mc_rsp_flush_cmplt => mc6_rsp_flush_cmplt
);
-- CyGraph Kernel 7
k7 : scc_kernel
port map (
-- control signals
clk => clk,
rst => nxtk_rst(6),
enable => nxtk_enable(6),
busy => nextk_busy(6),
done => nextk_done(6),
-- Kernel Parameters
kernel_id => x"07",
ae_id => ae_id,
kernels_count => kernels_count,
-- kernels communication signals
kernel_tx_vld => kernel_tx_vld(7),
kernel_tx_nextv => kernel_tx_nextv(7),
kernel_rx_vld => kernel_tx_vld(6),
kernel_rx_nextv => kernel_tx_nextv(6),
-- Input Graph Prameters (Represented in Custom CSR)
N => nxtk_N(6),
graph_info => nxtk_graph_info(6),
rgraph_info => nxtk_rgraph_info(6),
-- SCC intersection parameters
color => nxtk_color(6),
fw_queue => nxtk_fw_queue(6),
fw_count => nxtk_fw_count(6),
bw_queue => nxtk_bw_queue(6),
bw_count => nxtk_bw_count(6),
scc_results => nxtk_scc_results(6),
-- Parameters for next kernel
nxtk_rst => nxtk_rst(7),
nxtk_enable => nxtk_enable(7),
nextk_busy => nextk_busy(7),
nextk_done => nextk_done(7),
nxtk_N => nxtk_N(7),
nxtk_graph_info => nxtk_graph_info(7),
nxtk_rgraph_info => nxtk_rgraph_info(7),
nxtk_color => nxtk_color(7),
nxtk_fw_queue => nxtk_fw_queue(7),
nxtk_fw_count => nxtk_fw_count(7),
nxtk_bw_queue => nxtk_bw_queue(7),
nxtk_bw_count => nxtk_bw_count(7),
nxtk_scc_results => nxtk_scc_results(7),
-- MC7 request port signals
mc_req_ld => mc7_req_ld,
mc_req_st => mc7_req_st,
mc_req_size => mc7_req_size,
mc_req_vaddr => mc7_req_vaddr,
mc_req_wrd_rdctl => mc7_req_wrd_rdctl,
mc_rd_rq_stall => mc7_rd_rq_stall,
mc_wr_rq_stall => mc7_wr_rq_stall,
-- MC7 response port signals
mc_rsp_push => mc7_rsp_push,
mc_rsp_stall => mc7_rsp_stall,
mc_rsp_data => mc7_rsp_data,
mc_rsp_rdctl => mc7_rsp_rdctl,
-- MC flush signals
mc_req_flush => mc7_req_flush,
mc_rsp_flush_cmplt => mc7_rsp_flush_cmplt
);
prvae_tx_vld <= '0';
prvae_tx_data <= (others => '0');
nextk_busy(7) <= '0';
nextk_done(7) <= '1';
nextk_busy(15) <= '0';
nextk_done(15) <= '1';
-- Reset unused MC ports
mc8_req_ld <= '0';
mc8_req_st <= '0';
mc8_req_size <= (others => '0');
mc8_req_vaddr <= (others => '0');
mc8_req_wrd_rdctl <= (others => '0');
mc8_req_flush <= '0';
mc8_rsp_stall <= '0';
mc9_req_ld <= '0';
mc9_req_st <= '0';
mc9_req_size <= (others => '0');
mc9_req_vaddr <= (others => '0');
mc9_req_wrd_rdctl <= (others => '0');
mc9_req_flush <= '0';
mc9_rsp_stall <= '0';
mc10_req_ld <= '0';
mc10_req_st <= '0';
mc10_req_size <= (others => '0');
mc10_req_vaddr <= (others => '0');
mc10_req_wrd_rdctl <= (others => '0');
mc10_req_flush <= '0';
mc10_rsp_stall <= '0';
mc11_req_ld <= '0';
mc11_req_st <= '0';
mc11_req_size <= (others => '0');
mc11_req_vaddr <= (others => '0');
mc11_req_wrd_rdctl <= (others => '0');
mc11_req_flush <= '0';
mc11_rsp_stall <= '0';
mc12_req_ld <= '0';
mc12_req_st <= '0';
mc12_req_size <= (others => '0');
mc12_req_vaddr <= (others => '0');
mc12_req_wrd_rdctl <= (others => '0');
mc12_req_flush <= '0';
mc12_rsp_stall <= '0';
mc13_req_ld <= '0';
mc13_req_st <= '0';
mc13_req_size <= (others => '0');
mc13_req_vaddr <= (others => '0');
mc13_req_wrd_rdctl <= (others => '0');
mc13_req_flush <= '0';
mc13_rsp_stall <= '0';
mc14_req_ld <= '0';
mc14_req_st <= '0';
mc14_req_size <= (others => '0');
mc14_req_vaddr <= (others => '0');
mc14_req_wrd_rdctl <= (others => '0');
mc14_req_flush <= '0';
mc14_rsp_stall <= '0';
mc15_req_ld <= '0';
mc15_req_st <= '0';
mc15_req_size <= (others => '0');
mc15_req_vaddr <= (others => '0');
mc15_req_wrd_rdctl <= (others => '0');
mc15_req_flush <= '0';
mc15_rsp_stall <= '0';
rst_control : process (clk, rst)
begin
if (rising_edge(clk)) then
if (rst = '1') then
-- reset data
r_rst <= '1';
r_enable <= '0';
n <= (others => '0');
color <= (others => '0');
scc_addr <= (others => '0');
graph_info <= (others => '0');
rgraph_info <= (others => '0');
fw_addr <= (others => '0');
fw_count <= (others => '0');
bw_addr <= (others => '0');
bw_count <= (others => '0');
else
r_rst <= '0';
if (enable = '1') then
r_enable <= '1';
n <= n_in;
color <= color_in;
scc_addr <= scc_addr_in;
graph_info <= graph_info_in;
rgraph_info <= rgraph_info_in;
fw_addr <= fw_addr_in;
fw_count <= fw_count_in;
bw_addr <= bw_addr_in;
bw_count <= bw_count_in;
else
r_enable <= '0';
end if;
end if;
end if;
end process;
ae_ae : process (clk, r_rst)
begin
if (rising_edge(clk)) then
if (r_rst = '1') then
nxtae_tx_vld <= '0';
nxtae_tx_data <= (others => '0');
master_tx_nextv <= (others => '0');
nextv_out <= (others => '0');
k0_rx_vld <= '0';
else
-- Control output
if (scc_state = st_start) then
nextv_out <= (others => '0');
elsif (kernel_tx_vld(7) = '1') then
nextv_out <= x"00000000" & std_logic_vector(kernel_tx_nextv(7)(31 downto 0));
end if;
-- Control nxtae_tx_vld, nxtae_tx_data
if (scc_state = st_start or scc_state = st_done or scc_state = st_idle) then
nxtae_tx_vld <= '0';
nxtae_tx_data <= (others => '0');
else
nxtae_tx_vld <= kernel_tx_vld(7);
nxtae_tx_data <= kernel_tx_nextv(7)(31 downto 0);
end if;
-- Control k0_rx_vld, master_tx_nextv
if (scc_state = st_start) then
k0_rx_vld <= '0';
master_tx_nextv <= (others => '0');
else
if (ae_id = "00") then
k0_rx_vld <= master_tx_vld;
if (prvae_rx_vld = '1') then
master_tx_nextv <= x"00000000" & prvae_rx_data(31 downto 0);
end if;
elsif (prvae_rx_vld = '1') then
k0_rx_vld <= '1';
master_tx_nextv <= x"00000000" & prvae_rx_data(31 downto 0);
else
k0_rx_vld <= '0';
end if;
end if;
end if;
end if;
end process; -- ae_ae
master : process(clk, r_rst)
begin
if rising_edge(clk) then
if (r_rst = '1') then
busy <= '0';
done <= '0';
scc_state <= st_idle;
kernels_enable <= '0';
else
case (scc_state) is
when st_idle =>
done <= '0';
if (r_enable = '1') then
busy <= '1';
kernels_enable <= '1'; -- set enable early, to allow k2k process in kernel to work
scc_state <= st_start;
else
busy <= '0';
kernels_enable <= '0';
scc_state <= st_idle;
end if ;
when st_start =>
if (kernels_busy = '0') then
kernels_enable <= '0';
scc_state <= st_wait;
else
scc_state <= st_start;
end if;
when st_wait =>
kernels_enable <= '0';
scc_state <= st_busy;
when st_busy =>
if (kernels_busy = '0') then
scc_state <= st_done;
else
scc_state <= st_busy;
end if;
-- Cygraph is done
when st_done =>
done <= '1';
busy <= '0';
scc_state <= st_idle;
when others =>
scc_state <= st_idle;
end case;
end if; -- end if rst
end if; -- end if clk
end process; -- master
-- Kernel-to-kenrel process
--- Start and control the kernel_tx_vld signals
k2k : process (clk, r_rst)
begin
if (rising_edge(clk)) then
if (r_rst = '1') then
k2k_start <= '0';
master_tx_vld <= '0';
else
-- If kernel idle, reset signals
if (scc_state = st_start) then
k2k_start <= '0';
master_tx_vld <= '0';
else
-- If the start of the level, issue a vld signal
if (k2k_start = '0') then
master_tx_vld <= '0';
k2k_start <= '1';
else
-- if valid signal, pass it to next kernel in the ring
if (prvae_rx_vld = '1') then
master_tx_vld <= '1';
else
master_tx_vld <= '0';
end if;
end if;
end if; -- end if kernel state
end if; -- end if rst
end if; -- end if clk
end process; -- Kernel-to-kernel communication
end architecture;
|
-- Copyright (c) 2015 by David Goncalves <davegoncalves@gmail.com>
-- See licence.txt for details
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_adc_fir_lowpass IS
END tb_adc_fir_lowpass;
ARCHITECTURE behavior OF tb_adc_fir_lowpass IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fir_filter
PORT(
sclr : IN std_logic;
clk : IN std_logic;
nd : IN std_logic;
rfd : OUT std_logic;
rdy : OUT std_logic;
data_valid : OUT std_logic;
din : IN std_logic_vector(24 downto 0);
dout : OUT std_logic_vector(40 downto 0)
);
END COMPONENT;
--Inputs
signal sclr : std_logic := '0';
signal clk : std_logic := '0';
signal nd : std_logic := '0';
signal din : std_logic_vector(24 downto 0) := (others => '0');
--Outputs
signal rfd : std_logic;
signal rdy : std_logic;
signal data_valid : std_logic;
signal dout : std_logic_vector(40 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fir_filter PORT MAP (
sclr => sclr,
clk => clk,
nd => nd,
rfd => rfd,
rdy => rdy,
data_valid => data_valid,
din => din,
dout => dout
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
sclr <= '1';
nd <= '1';
wait for clk_period*10;
sclr <= '0';
-- insert stimulus here
wait for clk_period*10;
din <= (others => '0');
wait for clk_period*10;
din <= (others => '1');
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psl.all;
use work.functions.all;
package dma_package is
----------------------------------------------------------------------------------------------------------------------- dma parameters
constant DMA_SIZE_WIDTH : natural := 32; -- number of bits for dma size port - should be log2 of largest request
constant DMA_ID_WIDTH : natural := 32; -- number of bits for unique id field - should be log2 of total requests
constant DMA_READ_QUEUE_DEPTH : natural := 8; -- number of address bits for read queues
constant DMA_WRITE_QUEUE_DEPTH : natural := 8; -- number of address bits for write queues
constant DMA_WRITE_BUFFER_DEPTH : natural := 8; -- number of address bits for write buffers - should be larger than write queue depth if requests are mostly more than one cacheline
constant DMA_DATA_WIDTH : natural := 1024; -- number of bits for dma data port - don't change
constant DMA_READ_ENGINES : natural := 1; -- number of stream engines for reading
constant DMA_WRITE_ENGINES : natural := 1; -- number of stream engines for writing
constant DMA_READ_CREDITS : natural := 32; -- number of credits used for reading - recommended to be (31 or 32) - sum of credits can't exceed 64
constant DMA_WRITE_CREDITS : natural := 32; -- number of credits used for writing - recommended to be (32 or 33) - sum of credits can't exceed 64
constant DMA_TOUCH_COUNT : natural := 1; -- should be smaller than number of cachelines in page (512 by default on POWER8)
constant DMA_READ_TOUCH : std_logic := '0'; -- '1' enables pre-touching pages for large read requests
constant DMA_WRITE_TOUCH : std_logic := '0'; -- '1' enables pre-touching pages for large write requests
constant DMA_WRITE_PRIORITY : std_logic := '1'; -- '1' enables write priority - '0' enables read priority
constant DMA_TAG_WIDTH : natural := PSL_TAG_WIDTH - 1;
constant DMA_READ_CREDITS_WIDTH : natural := log2(DMA_READ_CREDITS) + 1;
constant DMA_WRITE_CREDITS_WIDTH : natural := log2(DMA_WRITE_CREDITS) + 1;
constant DMA_READ_ENGINES_WIDTH : natural := log2(DMA_READ_ENGINES) + 1;
constant DMA_WRITE_ENGINES_WIDTH : natural := log2(DMA_WRITE_ENGINES) + 1;
----------------------------------------------------------------------------------------------------------------------- io
type dma_read_request is record
valid : std_logic;
stream : std_logic_vector(DMA_READ_ENGINES - 1 downto 0);
address : unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
size : unsigned(DMA_SIZE_WIDTH - 1 downto 0);
end record;
type dma_read_response is record
valid : std_logic;
id : unsigned(DMA_ID_WIDTH - 1 downto 0);
stream : std_logic_vector(DMA_READ_ENGINES - 1 downto 0);
data : std_logic_vector(DMA_DATA_WIDTH - 1 downto 0);
full : std_logic_vector(DMA_READ_ENGINES - 1 downto 0);
end record;
type dma_write_request_item is record
valid : std_logic;
stream : std_logic_vector(DMA_WRITE_ENGINES - 1 downto 0);
address : unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
size : unsigned(DMA_SIZE_WIDTH - 1 downto 0);
end record;
type dma_write_data_item is record
valid : std_logic;
stream : std_logic_vector(DMA_WRITE_ENGINES - 1 downto 0);
data : std_logic_vector(DMA_DATA_WIDTH - 1 downto 0);
end record;
type dma_write_request is record
request : dma_write_request_item;
data : dma_write_data_item;
end record;
type dma_write_response is record
valid : std_logic;
id : unsigned(DMA_ID_WIDTH - 1 downto 0);
stream : std_logic_vector(DMA_WRITE_ENGINES - 1 downto 0);
full : std_logic_vector(DMA_WRITE_ENGINES - 1 downto 0);
end record;
type dma_cd_in is record
read : dma_read_request;
write : dma_write_request;
end record;
type dma_dc_out is record
id : unsigned(DMA_ID_WIDTH - 1 downto 0);
read : dma_read_response;
write : dma_write_response;
end record;
type dma_in is record
cr : cr_in;
-- c : psl_command_in;
b : psl_buffer_in;
r : psl_response_in;
cd : dma_cd_in;
end record;
type dma_out is record
c : psl_command_out;
b : psl_buffer_out;
dc : dma_dc_out;
end record;
----------------------------------------------------------------------------------------------------------------------- stream engines
type request_item is record
id : unsigned(DMA_ID_WIDTH - 1 downto 0);
address : unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
size : unsigned(DMA_SIZE_WIDTH - 1 downto 0);
end record;
type touch_control is record
touch : std_logic;
count : unsigned(PSL_ERAT_WIDTH - 1 downto 0);
address : unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
end record;
type read_stream_engine is record
request : request_item;
hold : unsigned(DMA_READ_ENGINES_WIDTH - 1 downto 0);
touch : touch_control;
end record;
type write_stream_engine is record
request : request_item;
hold : unsigned(DMA_WRITE_ENGINES_WIDTH - 1 downto 0);
touch : touch_control;
end record;
type read_stream_engines is array (0 to DMA_READ_ENGINES - 1) of read_stream_engine;
type write_stream_engines is array (0 to DMA_WRITE_ENGINES - 1) of write_stream_engine;
type read_stream_engines_control is record
free : std_logic_vector(DMA_READ_ENGINES - 1 downto 0);
active_count : unsigned(DMA_READ_ENGINES_WIDTH - 1 downto 0);
ready : std_logic_vector(DMA_READ_ENGINES - 1 downto 0);
pull_engine : natural;
pull_stream : std_logic_vector(DMA_READ_ENGINES - 1 downto 0);
engine : read_stream_engines;
end record;
type write_stream_engines_control is record
free : std_logic_vector(DMA_WRITE_ENGINES - 1 downto 0);
active_count : unsigned(DMA_WRITE_ENGINES_WIDTH - 1 downto 0);
ready : std_logic_vector(DMA_WRITE_ENGINES - 1 downto 0);
pull_engine : natural;
pull_stream : std_logic_vector(DMA_WRITE_ENGINES - 1 downto 0);
engine : write_stream_engines;
end record;
----------------------------------------------------------------------------------------------------------------------- queues
type queue_item is record
data : unsigned(DMA_ID_WIDTH + PSL_ADDRESS_WIDTH + DMA_SIZE_WIDTH - 1 downto 0);
request : request_item;
empty : std_logic;
full : std_logic;
end record;
type read_queues is array (0 to DMA_READ_ENGINES - 1) of queue_item;
type write_queues is array (0 to DMA_WRITE_ENGINES - 1) of queue_item;
type write_buffer_item is record
data : std_logic_vector(DMA_DATA_WIDTH - 1 downto 0);
full : std_logic;
empty : std_logic;
end record;
type write_buffers is array (0 to DMA_WRITE_ENGINES - 1) of write_buffer_item;
type write_buffer_control is array (0 to DMA_WRITE_ENGINES - 1) of unsigned(DMA_WRITE_BUFFER_DEPTH - 1 downto 0);
----------------------------------------------------------------------------------------------------------------------- tag control
type tag_control is record
available : std_logic;
tag : unsigned(DMA_TAG_WIDTH downto 0);
end record;
----------------------------------------------------------------------------------------------------------------------- response buffer
type response_buffer_control is record
put_flip : std_logic;
pull_flip : std_logic;
pull_address : unsigned(DMA_TAG_WIDTH downto 0);
status : std_logic_vector(2 ** DMA_TAG_WIDTH - 1 downto 0);
end record;
type read_buffer_item is record
data0 : std_logic_vector(PSL_DATA_WIDTH - 1 downto 0);
data1 : std_logic_vector(PSL_DATA_WIDTH - 1 downto 0);
end record;
----------------------------------------------------------------------------------------------------------------------- command history
type read_history_item is record
data : unsigned(DMA_ID_WIDTH + DMA_READ_ENGINES downto 0);
id : unsigned(DMA_ID_WIDTH - 1 downto 0);
stream : unsigned(DMA_READ_ENGINES - 1 downto 0);
touch : std_logic;
end record;
type write_history_item is record
data : unsigned(DMA_ID_WIDTH + DMA_WRITE_ENGINES downto 0);
id : unsigned(DMA_ID_WIDTH - 1 downto 0);
stream : unsigned(DMA_WRITE_ENGINES - 1 downto 0);
touch : std_logic;
end record;
----------------------------------------------------------------------------------------------------------------------- internals
type dma_int is record
id : unsigned(DMA_ID_WIDTH - 1 downto 0);
read : std_logic;
read_touch : std_logic;
write : std_logic;
write_touch : std_logic;
read_credits : unsigned(DMA_READ_CREDITS_WIDTH - 1 downto 0);
write_credits : unsigned(DMA_WRITE_CREDITS_WIDTH - 1 downto 0);
wqb : write_buffer_control;
rt : tag_control;
wt : tag_control;
rse : read_stream_engines_control;
wse : write_stream_engines_control;
rb : response_buffer_control;
wb : response_buffer_control;
o : dma_out;
end record;
----------------------------------------------------------------------------------------------------------------------- externals
type dma_ext is record
rq : read_queues;
wq : write_queues;
wqb : write_buffers;
rb : read_buffer_item;
wb : write_buffer_item;
rh : read_history_item;
wh : write_history_item;
end record;
procedure dma_reset (signal r : inout dma_int);
----------------------------------------------------------------------------------------------------------------------- read procedures
procedure read_byte (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0)
);
procedure read_byte (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
stream : in natural
);
procedure read_bytes (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural
);
procedure read_bytes (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0)
);
procedure read_bytes (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural;
stream : in natural
);
procedure read_bytes (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0);
stream : in natural
);
procedure read_cacheline (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0)
);
procedure read_cacheline (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
stream : in natural
);
procedure read_cachelines (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural
);
procedure read_cachelines (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0)
);
procedure read_cachelines (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural;
stream : in natural
);
procedure read_cachelines (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0);
stream : in natural
);
----------------------------------------------------------------------------------------------------------------------- write procedures
procedure write_byte (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in std_logic_vector(7 downto 0)
);
procedure write_byte (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in unsigned(7 downto 0)
);
procedure write_byte (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in std_logic_vector(7 downto 0);
stream : in natural
);
procedure write_byte (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in unsigned(7 downto 0);
stream : in natural
);
procedure write_bytes (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural
);
procedure write_bytes (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0)
);
procedure write_bytes (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural;
stream : in natural
);
procedure write_bytes (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0);
stream : in natural
);
procedure write_cachelines (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0);
stream : in natural
);
procedure write_cachelines (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural;
stream : in natural
);
procedure write_cachelines (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0)
);
procedure write_cachelines (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural
);
procedure write_cacheline (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in std_logic_vector(DMA_DATA_WIDTH - 1 downto 0);
stream : in natural
);
procedure write_cacheline (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in unsigned(DMA_DATA_WIDTH - 1 downto 0);
stream : in natural
);
procedure write_cacheline (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in std_logic_vector(DMA_DATA_WIDTH - 1 downto 0)
);
procedure write_cacheline (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in unsigned(DMA_DATA_WIDTH - 1 downto 0)
);
procedure write_data (
variable write : out dma_write_data_item;
data : in std_logic_vector
);
procedure write_data (
variable write : out dma_write_data_item;
data : in unsigned
);
procedure write_data (
variable write : out dma_write_data_item;
data : in std_logic_vector;
stream : in natural
);
procedure write_data (
variable write : out dma_write_data_item;
data : in unsigned;
stream : in natural
);
end package dma_package;
package body dma_package is
----------------------------------------------------------------------------------------------------------------------- reset procedure
procedure dma_reset (signal r : inout dma_int) is
begin
r.id <= (others => '0');
r.read <= '0';
r.read_touch <= '0';
r.write <= '0';
r.write_touch <= '0';
r.read_credits <= u(DMA_READ_CREDITS, DMA_READ_CREDITS_WIDTH);
r.write_credits <= u(DMA_WRITE_CREDITS, DMA_WRITE_CREDITS_WIDTH);
r.wqb <= (others => (others => '0'));
r.rt.available <= '1';
r.rt.tag <= (others => '0');
r.wt.available <= '1';
r.wt.tag <= (others => '0');
r.rse.free <= (others => '1');
r.rse.ready <= (others => '0');
r.rse.active_count <= (others => '0');
r.rse.pull_engine <= 0;
r.rse.pull_stream <= (others => '0');
for stream in 0 to DMA_READ_ENGINES - 1 loop
r.rse.engine(stream).hold <= (others => '0');
end loop;
r.wse.free <= (others => '1');
r.wse.ready <= (others => '0');
r.wse.active_count <= (others => '0');
r.wse.pull_engine <= 0;
r.wse.pull_stream <= (others => '0');
for stream in 0 to DMA_WRITE_ENGINES - 1 loop
r.wse.engine(stream).hold <= (others => '0');
end loop;
r.rb.put_flip <= '1';
r.rb.pull_flip <= '1';
r.rb.pull_address <= (others => '0');
r.rb.status <= (others => '0');
r.wb.put_flip <= '1';
r.wb.pull_flip <= '1';
r.wb.pull_address <= (others => '0');
r.wb.status <= (others => '0');
end procedure dma_reset;
----------------------------------------------------------------------------------------------------------------------- read procedures
procedure read_bytes (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0);
stream : in natural
) is
begin
read.valid := '1';
read.address := address;
read.size := n;
read.stream := (others => '0');
read.stream(stream) := '1';
end procedure read_bytes;
procedure read_bytes (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural;
stream : in natural
) is
begin
read_bytes (read, address, u(n, DMA_SIZE_WIDTH), stream);
end procedure read_bytes;
procedure read_bytes (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0)
) is
begin
read_bytes (read, address, n, 0);
end procedure read_bytes;
procedure read_bytes (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural
) is
begin
read_bytes (read, address, u(n, DMA_SIZE_WIDTH), 0);
end procedure read_bytes;
procedure read_byte (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
stream : in natural
) is
begin
read_bytes (read, address, u(1, DMA_SIZE_WIDTH), stream);
end procedure read_byte;
procedure read_byte (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0)
) is
begin
read_bytes (read, address, u(1, DMA_SIZE_WIDTH), 0);
end procedure read_byte;
procedure read_cachelines (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural;
stream : in natural
) is
begin
read_bytes (read, address, u(n*PSL_CACHELINE_SIZE, DMA_SIZE_WIDTH), stream);
end procedure read_cachelines;
procedure read_cachelines (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0);
stream : in natural
) is
begin
read_cachelines (read, address, idx(n), stream);
end procedure read_cachelines;
procedure read_cachelines (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0)
) is
begin
read_cachelines (read, address, n, 0);
end procedure read_cachelines;
procedure read_cachelines (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural
) is
begin
read_cachelines (read, address, n, 0);
end procedure read_cachelines;
procedure read_cacheline (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
stream : in natural
) is
begin
read_cachelines (read, address, 1, stream);
end procedure read_cacheline;
procedure read_cacheline (
variable read : out dma_read_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0)
) is
begin
read_cachelines (read, address, 1, 0);
end procedure read_cacheline;
----------------------------------------------------------------------------------------------------------------------- write procedures
procedure write_data (
variable write : out dma_write_data_item;
data : in std_logic_vector;
stream : in natural
) is
begin
write.valid := '1';
write.stream := (others => '0');
write.stream(stream) := '1';
write.data(data'range) := data;
end procedure write_data;
procedure write_data (
variable write : out dma_write_data_item;
data : in unsigned;
stream : in natural
) is
begin
write_data (write, slv(data), stream);
end procedure write_data;
procedure write_data (
variable write : out dma_write_data_item;
data : in std_logic_vector
) is
begin
write_data (write, data, 0);
end procedure write_data;
procedure write_data (
variable write : out dma_write_data_item;
data : in unsigned
) is
begin
write_data (write, slv(data), 0);
end procedure write_data;
procedure write_bytes (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0);
stream : in natural
) is
begin
write.valid := '1';
write.address := address;
write.size := n;
write.stream := (others => '0');
write.stream(stream) := '1';
end procedure write_bytes;
procedure write_bytes (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural;
stream : in natural
) is
begin
write_bytes (write, address, u(n, DMA_SIZE_WIDTH), stream);
end procedure write_bytes;
procedure write_bytes (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural
) is
begin
write_bytes (write, address, n, 0);
end procedure write_bytes;
procedure write_bytes (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0)
) is
begin
write_bytes (write, address, n, 0);
end procedure write_bytes;
procedure write_byte (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in std_logic_vector(7 downto 0);
stream : in natural
) is
begin
write_bytes (write.request, address, u(1, DMA_SIZE_WIDTH), stream);
write_data (write.data, data, stream);
end procedure write_byte;
procedure write_byte (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in unsigned(7 downto 0);
stream : in natural
) is
begin
write_bytes (write.request, address, u(1, DMA_SIZE_WIDTH), stream);
write_data (write.data, data, stream);
end procedure write_byte;
procedure write_byte (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in std_logic_vector(7 downto 0)
) is
begin
write_bytes (write.request, address, u(1, DMA_SIZE_WIDTH), 0);
write_data (write.data, data, 0);
end procedure write_byte;
procedure write_byte (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in unsigned(7 downto 0)
) is
begin
write_bytes (write.request, address, u(1, DMA_SIZE_WIDTH), 0);
write_data (write.data, data, 0);
end procedure write_byte;
procedure write_cachelines (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural;
stream : in natural
) is
begin
write_bytes (write, address, u(n*PSL_CACHELINE_SIZE, DMA_SIZE_WIDTH), stream);
end procedure write_cachelines;
procedure write_cachelines (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0);
stream : in natural
) is
begin
write_cachelines (write, address, idx(n), stream);
end procedure write_cachelines;
procedure write_cachelines (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in natural
) is
begin
write_cachelines (write, address, n, 0);
end procedure write_cachelines;
procedure write_cachelines (
variable write : out dma_write_request_item;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
n : in unsigned(DMA_SIZE_WIDTH - 1 downto 0)
) is
begin
write_cachelines (write, address, n, 0);
end procedure write_cachelines;
procedure write_cacheline (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in std_logic_vector(DMA_DATA_WIDTH - 1 downto 0);
stream : in natural
) is
begin
write_cachelines (write.request, address, 1, stream);
write_data (write.data, data, stream);
end procedure write_cacheline;
procedure write_cacheline (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in unsigned(DMA_DATA_WIDTH - 1 downto 0);
stream : in natural
) is
begin
write_cachelines (write.request, address, 1, stream);
write_data (write.data, data, stream);
end procedure write_cacheline;
procedure write_cacheline (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in std_logic_vector(DMA_DATA_WIDTH - 1 downto 0)
) is
begin
write_cachelines (write.request, address, 1, 0);
write_data (write.data, data, 0);
end procedure write_cacheline;
procedure write_cacheline (
variable write : out dma_write_request;
address : in unsigned(PSL_ADDRESS_WIDTH - 1 downto 0);
data : in unsigned(DMA_DATA_WIDTH - 1 downto 0)
) is
begin
write_cachelines (write.request, address, 1, 0);
write_data (write.data, data, 0);
end procedure write_cacheline;
end package body dma_package;
|
architecture RTL of FIFO is
constant c_con1 : std_logic_vector(-1 to -4);
type t_typ1 is range -2 to -4;
begin
a <= b + c;
a <= b - c;
a <= b / c;
a <= b * c;
a <= b ** c;
a <= (b) + (c);
a <= (b) - (c);
a <= (b) / (c);
a <= (b) * (c);
a <= (b) ** (c);
-- violations below
a <= b + c;
a <= b + c;
a <= b + c;
a <= b - c;
a <= b - c;
a <= b - c;
a <= b / c;
a <= b / c;
a <= b / c;
a <= b * c;
a <= b * c;
a <= b * c;
a <= b ** c;
a <= b ** c;
a <= b ** c;
a <= (b) + (c);
a <= (b) + (c);
a <= (b) + (c);
a <= (b) - (c);
a <= (b) - (c);
a <= (b) - (c);
a <= (b) / (c);
a <= (b) / (c);
a <= (b) / (c);
a <= (b) * (c);
a <= (b) * (c);
a <= (b) * (c);
a <= (b) ** (c);
a <= (b) ** (c);
a <= (b) ** (c);
a(N - 1 downto 0);
a(N + 1 downto 0);
end architecture RTL;
architecture RTL of FIFO is
constant c_con2 : t_type := (
-900, -- comment 1
-901, -- comment 2
-902, -- comment 3
+903, -- comment 4
-904 -- comment 5
);
constant c_con3 : t_type := (
-12.36e-47,
45.67e+67,
58.6729e1093,
-2346.7921e90,
401e56
);
begin
end architecture RTL;
architecture RTL of FIFO is
begin
a(c + d) <= '0';
a(c - d) <= '0';
a(c / d) <= '0';
a(c * d) <= '0';
a(c ** d) <= '0';
a(c + d) <= '0';
a(c - d) <= '0';
a(c / d) <= '0';
a(c * d) <= '0';
a(c ** d) <= '0';
a(c + d) <= '0';
a(c - d) <= '0';
a(c / d) <= '0';
a(c * d) <= '0';
a(c ** d) <= '0';
a(c + d) <= '0';
a(c - d) <= '0';
a(c / d) <= '0';
a(c * d) <= '0';
a(c ** d) <= '0';
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/24 18:34:19
-- Nombre del módulo: metronomo - Behavioral
-- Comentarios adicionales:
-- Este divisor de frecuencia toma sus valores de una memoria ROM que contiene
-- los valores de los contadores. Por lo tanto, el rango de frecuencias depende
-- de la ROM.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity metronomo is
PORT (
clk : in STD_LOGIC; -- Reloj de entrada de 50MHz.
reset : in STD_LOGIC; -- Señal de reset.
btn_inc : in STD_LOGIC; -- Incrementa la cantidad de BPM.
btn_dec : in STD_LOGIC; -- Decrementa la cantidad de BPM.
d7s : out STD_LOGIC_VECTOR(7 downto 0);
MUX : out STD_LOGIC_VECTOR(3 downto 0);
clk_out : out STD_LOGIC -- Reloj de salida.
);
end metronomo;
architecture Behavioral of metronomo is
-- Señal para comunicación entre ROM y divisor con ROM.
signal escala: STD_LOGIC_VECTOR(27 downto 0);
-- Señal para el reloj de 3.125MHz (como entrada a divisor con ROM).
signal clk3M125: STD_LOGIC := '0';
-- Señal para el reloj de 5Hz (como entrada al contador).
signal clk5Hz: STD_LOGIC := '0';
-- Bit para habilitar, o no, la lectura de la ROM.
signal rom_en: STD_LOGIC := '0';
-- Señal para almacenar la dirección a leer de la ROM.
signal direccion: STD_LOGIC_VECTOR(8 downto 0);
-- Señal para almacenar la cantidad de BPM.
signal bpm: STD_LOGIC_VECTOR(8 downto 0);
-- Señal para pasar un número binario a BCD.
signal num_bcd: STD_LOGIC_VECTOR(10 downto 0);
-- Dígitos BCD para ser mostrados como siete segmentos.
signal D0, D1, D2, D3: STD_LOGIC_VECTOR(3 downto 0);
begin
-- Reloj de 3.125MHz, que será la entrada para el divisor
-- de frecuencia implementado con la ROM.
clk3M125Hz_i: entity work.clk3M125Hz(Behavioral)
PORT MAP(clk, reset, clk3M125);
-- Reloj de 200Hz, que será la entrada al contador (para evitar un
-- conteo súper rápido que no se ve).
clk5Hz_i: entity work.clk5Hz(Behavioral)
PORT MAP(clk, reset, clk5Hz);
-- Contador de 0 a 499, con valor inicial en 59 (equivalente en
-- este sistema a 60BPM), que apunta a la dirección ROM.
contador_dir_i: entity work.contador_up_down_0_499(Behavioral)
PORT MAP(clk5Hz, reset, btn_inc, btn_dec, direccion);
-- Divisor de frecuencia que entrega una salida de 1 a 512
-- pulsos por minuto, según la dirección de la ROM.
-- En general: BPM = DIRECCION + 1.
clk_rom_i: entity work.clk_rom(Behavioral)
PORT MAP(clk3M125, reset, escala, clk_out);
rom512_28b_i: entity work.rom512_28b(Behavioral)
PORT MAP(clk, rom_en, direccion, escala);
-- Convertidor de binario a BCD a siete segmentos.
-- Se encarga de recibir la cantidad de BPM en binario,
-- convertirla a tres dígitos en BCD, y enviar esos datos
-- a los visualizadores de siete segmentos.
bin2bcd9_i: entity bin2bcd9(Behavioral)
PORT MAP(bpm, num_bcd);
d7s_i: entity work.siete_segmentos_4bits_completo(Behavioral)
PORT MAP(clk, reset, D0, D1, D2, D3, d7s, MUX);
-- La cantidad de BPM es igual a la dirección más uno.
bpm <= direccion + 1;
-- La ROM está habilitada siempre y cuando no esté en reset.
rom_en <= NOT reset;
-- Se asignan las señales que representarán los datos en siete segmentos.
D3 <= "0000";
D2 <= "0" & num_bcd(10 downto 8);
D1 <= num_bcd(7 downto 4);
D0 <= num_bcd(3 downto 0);
end Behavioral; |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/04/24 18:34:19
-- Nombre del módulo: metronomo - Behavioral
-- Comentarios adicionales:
-- Este divisor de frecuencia toma sus valores de una memoria ROM que contiene
-- los valores de los contadores. Por lo tanto, el rango de frecuencias depende
-- de la ROM.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity metronomo is
PORT (
clk : in STD_LOGIC; -- Reloj de entrada de 50MHz.
reset : in STD_LOGIC; -- Señal de reset.
btn_inc : in STD_LOGIC; -- Incrementa la cantidad de BPM.
btn_dec : in STD_LOGIC; -- Decrementa la cantidad de BPM.
d7s : out STD_LOGIC_VECTOR(7 downto 0);
MUX : out STD_LOGIC_VECTOR(3 downto 0);
clk_out : out STD_LOGIC -- Reloj de salida.
);
end metronomo;
architecture Behavioral of metronomo is
-- Señal para comunicación entre ROM y divisor con ROM.
signal escala: STD_LOGIC_VECTOR(27 downto 0);
-- Señal para el reloj de 3.125MHz (como entrada a divisor con ROM).
signal clk3M125: STD_LOGIC := '0';
-- Señal para el reloj de 5Hz (como entrada al contador).
signal clk5Hz: STD_LOGIC := '0';
-- Bit para habilitar, o no, la lectura de la ROM.
signal rom_en: STD_LOGIC := '0';
-- Señal para almacenar la dirección a leer de la ROM.
signal direccion: STD_LOGIC_VECTOR(8 downto 0);
-- Señal para almacenar la cantidad de BPM.
signal bpm: STD_LOGIC_VECTOR(8 downto 0);
-- Señal para pasar un número binario a BCD.
signal num_bcd: STD_LOGIC_VECTOR(10 downto 0);
-- Dígitos BCD para ser mostrados como siete segmentos.
signal D0, D1, D2, D3: STD_LOGIC_VECTOR(3 downto 0);
begin
-- Reloj de 3.125MHz, que será la entrada para el divisor
-- de frecuencia implementado con la ROM.
clk3M125Hz_i: entity work.clk3M125Hz(Behavioral)
PORT MAP(clk, reset, clk3M125);
-- Reloj de 200Hz, que será la entrada al contador (para evitar un
-- conteo súper rápido que no se ve).
clk5Hz_i: entity work.clk5Hz(Behavioral)
PORT MAP(clk, reset, clk5Hz);
-- Contador de 0 a 499, con valor inicial en 59 (equivalente en
-- este sistema a 60BPM), que apunta a la dirección ROM.
contador_dir_i: entity work.contador_up_down_0_499(Behavioral)
PORT MAP(clk5Hz, reset, btn_inc, btn_dec, direccion);
-- Divisor de frecuencia que entrega una salida de 1 a 512
-- pulsos por minuto, según la dirección de la ROM.
-- En general: BPM = DIRECCION + 1.
clk_rom_i: entity work.clk_rom(Behavioral)
PORT MAP(clk3M125, reset, escala, clk_out);
rom512_28b_i: entity work.rom512_28b(Behavioral)
PORT MAP(clk, rom_en, direccion, escala);
-- Convertidor de binario a BCD a siete segmentos.
-- Se encarga de recibir la cantidad de BPM en binario,
-- convertirla a tres dígitos en BCD, y enviar esos datos
-- a los visualizadores de siete segmentos.
bin2bcd9_i: entity bin2bcd9(Behavioral)
PORT MAP(bpm, num_bcd);
d7s_i: entity work.siete_segmentos_4bits_completo(Behavioral)
PORT MAP(clk, reset, D0, D1, D2, D3, d7s, MUX);
-- La cantidad de BPM es igual a la dirección más uno.
bpm <= direccion + 1;
-- La ROM está habilitada siempre y cuando no esté en reset.
rom_en <= NOT reset;
-- Se asignan las señales que representarán los datos en siete segmentos.
D3 <= "0000";
D2 <= "0" & num_bcd(10 downto 8);
D1 <= num_bcd(7 downto 4);
D0 <= num_bcd(3 downto 0);
end Behavioral; |
-------------------------------------------------------------------------------
-- Department of Computer Engineering and Communications
-- Author: LPRS2 <lprs2@rt-rk.com>
--
-- Module Name: vga_sync
--
-- Description:
--
-- Implementation of VGA synchronization
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity vga_sync is
generic (
HORIZONTAL_RES : natural := 800;
VERTICAL_RES : natural := 600;
FRAME_SIZE : natural := 4
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
show_frame_i : in std_logic;
--
direct_mode_i : in std_logic; -- 0 - text and graphics interface mode, 1 - direct mode (direct force RGB component)
dir_red_i : in std_logic_vector(7 downto 0);
dir_green_i : in std_logic_vector(7 downto 0);
dir_blue_i : in std_logic_vector(7 downto 0);
--
active_pixel_i : in std_logic;
foreground_color_i : in std_logic_vector(23 downto 0);
background_color_i : in std_logic_vector(23 downto 0);
frame_color_i : in std_logic_vector(23 downto 0);
red_o : out std_logic_vector(7 downto 0);
green_o : out std_logic_vector(7 downto 0);
blue_o : out std_logic_vector(7 downto 0);
pixel_row_o : out std_logic_vector (10 downto 0);
pixel_column_o : out std_logic_vector (10 downto 0);
horiz_sync_o : out std_logic;
vert_sync_o : out std_logic;
psave_o : out std_logic;
blank_o : out std_logic;
pix_clk_o : out std_logic;
sync_o : out std_logic
);
end vga_sync;
architecture rtl of vga_sync is
signal horiz_sync_r : std_logic;
signal vert_sync_r : std_logic;
signal enable_s : std_logic;
signal h_count_r : std_logic_vector( 10 downto 0 );
signal v_count_r : std_logic_vector( 10 downto 0 );
signal horiz_sync_out_d_r : std_logic;
signal vert_sync_out_d_r : std_logic;
signal psave_d_r : std_logic;
signal blank_d_r : std_logic;
signal sync_d_r : std_logic;
-- signali za registrovanje izlaza
signal red_r : std_logic_vector(7 downto 0);
signal green_r : std_logic_vector(7 downto 0);
signal blue_r : std_logic_vector(7 downto 0);
signal horiz_sync_out_r : std_logic;
signal vert_sync_out_r : std_logic;
signal pixel_row_r : std_logic_vector(10 downto 0);
signal pixel_column_r : std_logic_vector(10 downto 0);
signal psave_r : std_logic;
signal blank_r : std_logic;
signal sync_r : std_logic;
-- konstatne horizontalne sinhronizacije
signal h_pixels : integer range 0 to 2047;
signal h_frontporch : integer range 0 to 2047;
signal h_sync_time : integer range 0 to 2047;
signal h_backporch : integer range 0 to 2047;
-- konstatne vertikalne sinhronizacije
signal v_lines : integer range 0 to 2047;
signal v_frontporch : integer range 0 to 2047;
signal v_sync_time : integer range 0 to 2047;
signal v_backporch : integer range 0 to 2047;
signal active_frame : std_logic;
begin
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
-- definisanje parametara potrebnih za sihronizacione signale
-- ovi parametri zavise od rezolucije
res_0 : if ( HORIZONTAL_RES = 64 and VERTICAL_RES = 48 ) generate
h_pixels <= 64;
h_frontporch <= 2 ;
h_sync_time <= 2 ;
h_backporch <= 2 ;
v_lines <= 48;
v_frontporch <= 2 ;
v_sync_time <= 2 ;
v_backporch <= 2 ;
end generate res_0;
res_1 : if ( HORIZONTAL_RES = 640 and VERTICAL_RES = 480 ) generate
h_pixels <= 640;
h_frontporch <= 16 ;
h_sync_time <= 96 ;
h_backporch <= 40 ;
v_lines <= 480;
v_frontporch <= 11 ;
v_sync_time <= 2 ;
v_backporch <= 31 ;
end generate res_1;
res_2 : if ( HORIZONTAL_RES = 800 and VERTICAL_RES = 600 ) generate
h_pixels <= 800;
h_frontporch <= 56 ;
h_sync_time <= 120;
h_backporch <= 64 ;
v_lines <= 600;
v_frontporch <= 37 ;
v_sync_time <= 6 ;
v_backporch <= 23 ;
end generate res_2;
res_3 : if ( HORIZONTAL_RES = 1024 and VERTICAL_RES = 768 ) generate
h_pixels <= 1024;
h_frontporch <= 24 ;
h_sync_time <= 136 ;
h_backporch <= 144 ;
v_lines <= 768 ;
v_frontporch <= 3 ;
v_sync_time <= 6 ;
v_backporch <= 29 ;
end generate res_3;
res_4 : if ( HORIZONTAL_RES = 1152 and VERTICAL_RES = 864 ) generate
h_pixels <= 1152;
h_frontporch <= 64 ;
h_sync_time <= 128 ;
h_backporch <= 256 ;
v_lines <= 864 ;
v_frontporch <= 1 ;
v_sync_time <= 3 ;
v_backporch <= 32 ;
end generate res_4;
res_5 : if ( HORIZONTAL_RES = 1280 and VERTICAL_RES = 1024 ) generate
h_pixels <= 1280;
h_frontporch <= 48 ;
h_sync_time <= 112 ;
h_backporch <= 248 ;
v_lines <= 1024;
v_frontporch <= 1 ;
v_sync_time <= 3 ;
v_backporch <= 38 ;
end generate res_5;
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
--
-- |<--- active region --->|<----------- blanking region ---------->|<--- active region --->|<----------- blanking region ---------->|
-- | (pixels) | | (pixels) | |
-- | (lines) | | (lines) | |
-- | | | | |
-- ----+---------- ... --------+------------- --------------+---------- ... --------+------------- --------------+--
-- | | | | | | | | | |
-- | | |<--front |<---sync |<---back | |<--front |<---sync |<---back |
-- | | | porch-->| time--->| porch--->| | porch-->| time--->| porch--->|
------ | | --------------- | | --------------- |
-- | | | | |
-- |<------------------- period ----------------------------------->|<------------------- period ----------------------------------->|
--
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
-- broji od nule do pune velicine linije
process(clk_i)
begin
if ( clk_i'event and clk_i = '1' ) then
if ( rst_n_i = '0' ) then h_count_r <= (others => '0');
else
if ( h_count_r < ( h_sync_time + h_pixels + h_frontporch + h_backporch) ) then h_count_r <= h_count_r + 1;
else h_count_r <= (others => '0');
end if;
end if;
end if;
end process;
-- generise hsyncb : nula je nad hor sync_o
process(clk_i)
begin
if ( clk_i'event and clk_i = '1') then
if ( rst_n_i = '0') then horiz_sync_r <= '1';
else
if ( (h_count_r >= (h_frontporch + h_pixels)) and (h_count_r < (h_pixels + h_frontporch + h_sync_time) )) then horiz_sync_r <= '0';
else horiz_sync_r <= '1';
end if;
end if;
end if;
end process;
-- uvecava vcnt na rastucu ivicu hor sync_o
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( rst_n_i = '0' ) then v_count_r <= (others => '0');
else
if ( h_count_r = h_pixels + h_frontporch + h_sync_time ) then
if ( v_count_r < (v_sync_time + v_lines + v_frontporch + v_backporch) ) then v_count_r <= v_count_r + 1;
else v_count_r <= (others => '0');
end if;
end if;
end if;
end if;
end process;
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ( rst_n_i = '0' ) then vert_sync_r <= '1';
else
if ( h_count_r = h_pixels + h_frontporch + h_sync_time ) then
if (v_count_r >= (v_lines + v_frontporch) and v_count_r < (v_lines + v_frontporch + v_sync_time)) then vert_sync_r <= '0';
else vert_sync_r <= '1';
end if;
end if;
end if;
end if;
end process;
process (h_count_r,v_count_r,h_pixels, v_lines)
begin
if ( (h_count_r >= h_pixels) or (v_count_r >= v_lines) ) then enable_s <= '0';
else enable_s <= '1';
end if;
end process;
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------
-- registrovanje signala
reg_outputs_1:process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_n_i = '0') then
horiz_sync_out_r <= '0';
vert_sync_out_r <= '0';
psave_r <= '0';
blank_r <= '0';
sync_r <= '0';
horiz_sync_out_d_r <= '0';
vert_sync_out_d_r <= '0';
psave_d_r <= '0';
blank_d_r <= '0';
sync_d_r <= '0';
else
horiz_sync_out_d_r <= horiz_sync_r ;
vert_sync_out_d_r <= vert_sync_r ;
psave_d_r <= '1' ;
blank_d_r <= enable_s ;
sync_d_r <= vert_sync_r and horiz_sync_r;
horiz_sync_out_r <= horiz_sync_out_d_r;
vert_sync_out_r <= vert_sync_out_d_r ;
psave_r <= psave_d_r ;
blank_r <= blank_d_r ;
sync_r <= sync_d_r ;
end if;
end if;
end process reg_outputs_1;
reg_outputs_2:process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_n_i = '0') then
red_r <= (others => '0');
green_r <= (others => '0');
blue_r <= (others => '0');
else
if ( enable_s = '1' ) then
if (direct_mode_i = '1') then
red_r <= dir_red_i;
green_r <= dir_green_i;
blue_r <= dir_blue_i;
elsif (show_frame_i = '1' and active_frame = '1') then
red_r <= frame_color_i(23 downto 16);
green_r <= frame_color_i(15 downto 8);
blue_r <= frame_color_i(7 downto 0);
elsif (active_pixel_i = '1') then
red_r <= foreground_color_i(23 downto 16);
green_r <= foreground_color_i(15 downto 8);
blue_r <= foreground_color_i(7 downto 0);
else
red_r <= background_color_i(23 downto 16);
green_r <= background_color_i(15 downto 8);
blue_r <= background_color_i(7 downto 0);
end if;
end if;
end if;
end if;
end process reg_outputs_2;
process (v_count_r,h_count_r)begin
if (--okvir
v_count_r < FRAME_SIZE or
v_count_r > (VERTICAL_RES - FRAME_SIZE-1) or
h_count_r < FRAME_SIZE or
h_count_r > (HORIZONTAL_RES - FRAME_SIZE-1)) then
active_frame <= '1';
else
active_frame <= '0';
end if;
end process;
-- povezivanje signala na izlaz
red_o <= red_r ;
green_o <= green_r ;
blue_o <= blue_r ;
horiz_sync_o <= horiz_sync_out_r;
vert_sync_o <= vert_sync_out_r ;
pixel_row_o <= v_count_r ;
pixel_column_o <= h_count_r ;
psave_o <= psave_r ;
blank_o <= blank_r ;
pix_clk_o <= clk_i ;
sync_o <= sync_r ;
end rtl;
|
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Implements a shift register of a given size.
library ieee;
use ieee.std_logic_1164.all;
entity shift_reg is
generic (
WIDTH : positive := 8
);
port (
rst : in std_logic;
clk : in std_logic;
load : in std_logic;
lsb : in std_logic;
output : out std_logic_vector(WIDTH-1 downto 0)
);
end shift_reg;
architecture BHV of shift_reg is
signal reg : std_logic_vector(WIDTH-1 downto 0);
begin
process(clk, rst, load, lsb)
begin
if(rst = '1') then
-- Reset to default value
reg <= (others => '0');
elsif(rising_edge(clk)) then
if(load = '1') then
reg <= reg(WIDTH-2 downto 0) & lsb; -- shift in the new LSB
else
reg <= reg;
end if;
end if;
end process;
-- Break out the register's value
output <= reg;
end BHV;
|
entity ENT00001_Test_Bench is
end entity ENT00001_Test_Bench;
architecture arch of ENT00001_Test_Bench is
constant CYCLES : integer := 1000;
signal clk : integer := 0;
signal sig1 : integer := 0;
signal sig2 : integer := 1;
begin
terminator : process(clk)
begin
if clk >= CYCLES then
assert false report "end of simulation" severity failure;
-- else
-- report "tick";
end if;
end process;
sig1 <= sig1 + sig2 after 1 us;
clk <= clk + 1 after 1 us;
end;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package MVL4 is
type MVL4_ulogic is ('X', '0', '1', 'Z'); -- unresolved logic type
type MVL4_ulogic_vector is array (natural range <>) of MVL4_ulogic;
function resolve_MVL4 ( contribution : MVL4_ulogic_vector )
return MVL4_ulogic;
subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
-- code from book (in text)
type MVL4_logic_vector is array (natural range <>) of MVL4_logic;
-- end code from book
end package MVL4;
--------------------------------------------------
package body MVL4 is
type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
constant resolution_table : table :=
-- 'X' '0' '1' 'Z'
-- ------------------
( ( 'X', 'X', 'X', 'X' ), -- 'X'
( 'X', '0', 'X', '0' ), -- '0'
( 'X', 'X', '1', '1' ), -- '1'
( 'X', '0', '1', 'Z' ) ); -- 'Z'
function resolve_MVL4 ( contribution : MVL4_ulogic_vector )
return MVL4_ulogic is
variable result : MVL4_ulogic := 'Z';
begin
for index in contribution'range loop
result := resolution_table(result, contribution(index));
end loop;
return result;
end function resolve_MVL4;
end package body MVL4;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package MVL4 is
type MVL4_ulogic is ('X', '0', '1', 'Z'); -- unresolved logic type
type MVL4_ulogic_vector is array (natural range <>) of MVL4_ulogic;
function resolve_MVL4 ( contribution : MVL4_ulogic_vector )
return MVL4_ulogic;
subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
-- code from book (in text)
type MVL4_logic_vector is array (natural range <>) of MVL4_logic;
-- end code from book
end package MVL4;
--------------------------------------------------
package body MVL4 is
type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
constant resolution_table : table :=
-- 'X' '0' '1' 'Z'
-- ------------------
( ( 'X', 'X', 'X', 'X' ), -- 'X'
( 'X', '0', 'X', '0' ), -- '0'
( 'X', 'X', '1', '1' ), -- '1'
( 'X', '0', '1', 'Z' ) ); -- 'Z'
function resolve_MVL4 ( contribution : MVL4_ulogic_vector )
return MVL4_ulogic is
variable result : MVL4_ulogic := 'Z';
begin
for index in contribution'range loop
result := resolution_table(result, contribution(index));
end loop;
return result;
end function resolve_MVL4;
end package body MVL4;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package MVL4 is
type MVL4_ulogic is ('X', '0', '1', 'Z'); -- unresolved logic type
type MVL4_ulogic_vector is array (natural range <>) of MVL4_ulogic;
function resolve_MVL4 ( contribution : MVL4_ulogic_vector )
return MVL4_ulogic;
subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
-- code from book (in text)
type MVL4_logic_vector is array (natural range <>) of MVL4_logic;
-- end code from book
end package MVL4;
--------------------------------------------------
package body MVL4 is
type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
constant resolution_table : table :=
-- 'X' '0' '1' 'Z'
-- ------------------
( ( 'X', 'X', 'X', 'X' ), -- 'X'
( 'X', '0', 'X', '0' ), -- '0'
( 'X', 'X', '1', '1' ), -- '1'
( 'X', '0', '1', 'Z' ) ); -- 'Z'
function resolve_MVL4 ( contribution : MVL4_ulogic_vector )
return MVL4_ulogic is
variable result : MVL4_ulogic := 'Z';
begin
for index in contribution'range loop
result := resolution_table(result, contribution(index));
end loop;
return result;
end function resolve_MVL4;
end package body MVL4;
|
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 35728)
`protect data_block
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`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:39:06 05/11/2015
-- Design Name:
-- Module Name: module_rom - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use STD.TEXTIO.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity module_ROM is
port (
clk_ROM: in std_logic;
M_ROM: in std_logic;
nROM_EN: in std_logic;
addr: in std_logic_vector(11 downto 0);
datao: out std_logic_vector(7 downto 0);
do: out std_logic);
end module_rom;
architecture Behavioral of module_ROM is
type matrix is array (integer range<>) of std_logic_vector(7 downto 0);
signal rom:matrix (0 to 2**12-1);
procedure load_rom(signal data_word:out matrix) is
file romfile: text open read_mode is "romfile2.dat";
variable lbuf: line;
variable i: integer := 0;
variable fdata: std_logic_vector(7 downto 0);
begin
for m in 0 to 15 loop
for n in 0 to 15 loop
for o in 0 to 15 loop
if not endfile(romfile) then
readline(romfile, lbuf);
read(lbuf, fdata);
data_word(i) <= fdata;
i := i + 1;
end if;
end loop;
end loop;
end loop;
end procedure;
begin
load_rom(rom);
process(clk_ROM, M_ROM, nROM_EN)
begin
if rising_edge(clk_ROM) then
if M_ROM = '1' and nROM_EN = '0' then
datao <= rom(conv_integer(addr));
do <= '1';
else
datao <= (others => 'Z');
do <= '0';
end if;
end if;
end process;
end Behavioral;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:35:24 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/win_1/win_sim_netlist.vhdl
-- Design : win
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win_bindec is
port (
ena_array : out STD_LOGIC_VECTOR ( 1 downto 0 );
addra : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of win_bindec : entity is "bindec";
end win_bindec;
architecture STRUCTURE of win_bindec is
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => addra(1),
I1 => addra(0),
O => ena_array(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => addra(1),
I1 => addra(0),
O => ena_array(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 8 downto 0 );
addra : in STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of win_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end win_blk_mem_gen_mux;
architecture STRUCTURE of win_blk_mem_gen_mux is
signal sel_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\douta[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(7),
I5 => sel_pipe_d1(0),
O => douta(7)
);
\douta[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOPADOP(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(0),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(0),
I5 => sel_pipe_d1(0),
O => douta(8)
);
\douta[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0),
I5 => sel_pipe_d1(0),
O => douta(0)
);
\douta[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(1),
I5 => sel_pipe_d1(0),
O => douta(1)
);
\douta[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(2),
I5 => sel_pipe_d1(0),
O => douta(2)
);
\douta[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(3),
I5 => sel_pipe_d1(0),
O => douta(3)
);
\douta[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(4),
I5 => sel_pipe_d1(0),
O => douta(4)
);
\douta[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(5),
I5 => sel_pipe_d1(0),
O => douta(5)
);
\douta[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AACCAACCF0FFF000"
)
port map (
I0 => DOADO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6),
I3 => sel_pipe_d1(1),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(6),
I5 => sel_pipe_d1(0),
O => douta(6)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of win_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end win_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of win_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000010000000200000000000000000000280000000000018000000820000",
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INIT_37 => X"0000000008000000000200000000008000000000200000000004000000000200",
INIT_38 => X"4000000000000000000000000000000000000000000000000000400000000010",
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INIT_3A => X"0400000000000000000000000C00002200100000000400000000000300000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => douta(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \win_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \win_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \win_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \win_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"000000000000000C000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000007C00000000000000000003C00000000000000000001C00000",
INITP_02 => X"0000000000000003FC0000000000000000001FC0000000000000000000FC0000",
INITP_03 => X"0000000000000001FFE000000000000000000FFC0000000000000000007FC000",
INITP_04 => X"00000000000000007FFE000000000000000007FFE000000000000000003FFE00",
INITP_05 => X"00000000000000000FFFE00000000000000000FFFE00000000000000000FFFE0",
INITP_06 => X"000000000000000003FFF000000000000000000FFFE00000000000000000FFFE",
INITP_07 => X"80000000000000003E3FF8000000000000000083FFC000000000000000003FFF",
INITP_08 => X"0000000000000001FFFFE000000000000000007FFFE00000000000000003E3FF",
INITP_09 => X"0000000000000001FF0000000000000000000FF8FC00000000000000003FFFFC",
INITP_0A => X"1FFFFF0000000000FC80003FFF000000000007FC0001FFE000000000003FE000",
INITP_0B => X"9FFFFFFF380000007E003EFFFFFFE400000003F803E7FFFFFE400000001FC000",
INITP_0C => X"CFFFFFFFFE600000061FFE7FFFFFFFCE00000079DFF3FFFFFFFDE0000007E03F",
INITP_0D => X"E7FFFFFFFFF80000001FFF3FFFFFFFFF80000001FFF9FFFFFFFFF800000043FF",
INITP_0E => X"FDFFFFFFFFFF8000000FFFE7FFFFFFFFF80000007FFE7FFFFFFFFF80000003FF",
INITP_0F => X"FF3F9FFFFFFF3E00000FFFF9FFFFFFFFFF8000007FFF9FFFFFFFFFF8000003FF",
INIT_00 => X"9E9E9E9E00009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_01 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_02 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_03 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00EEAA009E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_04 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_05 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_06 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0066FE32009E",
INIT_07 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_08 => X"9E9E9E9E9E00EEBAFE32009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_09 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0A => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E22AA98FEFE10009E9E9E9E9E9E9E9E9E",
INIT_0C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0D => X"FE10009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0066FEFEFE",
INIT_0F => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_10 => X"9E9E9E9E9E9E00EE98FEFEFEFE10009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_11 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_12 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_13 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E228898FEFEFEFEFE10009E9E9E9E9E",
INIT_14 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_15 => X"FEFEFEFEFE10009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_16 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0088FEFE",
INIT_17 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_18 => X"9E9E9E9E9E9E9E00EE98FEFEFEFEFEFEFE10009E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_19 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_1A => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_1B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E4488BAFEFEFEFEFEFEFEFE546622",
INIT_1C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_1D => X"FEFEFEFEFEFEFEFEFEFEBA44009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_1E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00AAFE",
INIT_1F => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_20 => X"9E9E9E9E9E9E9E9E00EE98FEFEFEFEFEFEFEFEFEFEFEFE66009E9E9E9E9E9E9E",
INIT_21 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_22 => X"FEFEDC44009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_23 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000BAFEFEFEFEFEFEFEFEFEFE",
INIT_24 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_25 => X"0098FEFEFEFEFEFEFEFEFEFEFEFEDC44009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_26 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00",
INIT_27 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_28 => X"9E9E9E9E9E9E9E9E9E9E00AA10DCFEFEFEFEFEFEFEFEFEFEFEFEDC44009E9E9E",
INIT_29 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2A => X"FEFEFEFEFEFEDC44009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00EEFEFEFEFEFEFEFEFE",
INIT_2C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2D => X"9E9E00EEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDC44009E9E9E9E9E9E9E9E9E9E9E",
INIT_2E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2F => X"009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_30 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E00CCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE44",
INIT_31 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_32 => X"FEFEFEFEFEFEFEFEFEDCBA66009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_33 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00EEFEFEFEFE",
INIT_34 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_35 => X"009E9E9E004476DCFEFEFEFEFEFEFEFEFEFEFEFEAA6666AAAA9E9E9E9E9E9E9E",
INIT_36 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_37 => X"000000AAEE9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_38 => X"9E9E9E9E9E9E9E9E9E9E9E44AA449E9E0044DCFEFEFEFEFEFEFEFEFEFEFEBA10",
INIT_39 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_3A => X"FEFEFEFEFEFEFEFEFEFECC009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_3B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00AAFECC009E0044BAFE",
INIT_3C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_3D => X"9E0010BAFEBA32000022BAFEFEFEFEFEFEFEFEFEDCAA449E9E9E9E9E9E9E9E9E",
INIT_3E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_3F => X"10009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_40 => X"9E9E9E9E9E9E9E00000000004488BAFEFEFEDCAA88CCDCFEFEFEFEFEFEFEFEBA",
INIT_41 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_42 => X"FEFEFEFEFEFEFEFEFEFEFECC009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_43 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000000000AAFEFEFEFEFEFEFE",
INIT_44 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_45 => X"54545454BAFEFEFEFEFEFEFEFEFEFEFEFEFE98AAAAAAAA449E9E9E9E9E9E9E9E",
INIT_46 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000CC54",
INIT_47 => X"0000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_48 => X"9E9E9E9E9E9E9E20404052FEFEFEFEFEFE9898BAFEFEFEFEFEFE98989898EE00",
INIT_49 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_4A => X"FEFEFEFEFEDC4400000044669E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_4B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00A02020B2FEFEFEFEFE540000AA",
INIT_4C => X"0000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_4D => X"4040668EFCFEFE1088000044CCCCCCCCCCAA0000000000000000000000000000",
INIT_4E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0020A020",
INIT_4F => X"000022444444444444444444444444009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_50 => X"9E9E9E9E9E9E9E9E2080404020202042FCDE9822009E9E9E0000000000000000",
INIT_51 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_52 => X"9E9E9E9E9E9E9E9E9E9E9E000000AADCDCDCDCDCDCDCDCDCDCDCBA4400000000",
INIT_53 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000C020404020202064FE54229E",
INIT_54 => X"FEFEFEFEFEFEFE32EEEEEEAA0000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_55 => X"204020204040E0A20EAA009E9E9E00000000000000000088EEEE76FEFEFEFEFE",
INIT_56 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0040A0",
INIT_57 => X"00222210FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE982222220000229E9E",
INIT_58 => X"9E9E9E9E9E9E9E9E9E008040402020404020600000009E9E9E9E222222222200",
INIT_59 => X"FEFEFEFEBABA3200EEBA2200009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_5A => X"00000000000032BABADC5400CCBABADCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_5B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000C020404020204000402000",
INIT_5C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDCCCEE32EEEECC009E9E9E9E9E9E",
INIT_5D => X"00006020204040E0600000000066CCCCCCCCDCFEFE9810CC76FEFEFEFEFEFEFE",
INIT_5E => X"CC22BAFEFE66009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00",
INIT_5F => X"FE8844FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_60 => X"9E9E9E9E9E9E9E9E9E9E9E0000004020404020600000000000EEFEFEFEFEFEFE",
INIT_61 => X"FEFEFEFEFEFEFEFEFEFEFEFEBA546610FEBA10009E9E9E9E9E9E9E9E9E9E9E9E",
INIT_62 => X"9400E00296DCFEFEFEFEFE9844EE98FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_63 => X"009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000404060E02010",
INIT_64 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEAAAA54FE7600",
INIT_65 => X"9E9E9E00000020A0C0A28A9AFA402062D4FAFEFEFEFE76EE8876FEFEFEFEFEFE",
INIT_66 => X"FEFEFEFEFEFEFEEE00BA54009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_67 => X"FEFE6666FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_68 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000C0000088FEFED8422020208EFEFE",
INIT_69 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA54AA66009E9E9E9E9E9E9E9E",
INIT_6A => X"7698FEFEFCD66820008CFEFE7666EE98FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_6B => X"FE4400009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E40A878",
INIT_6C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_6D => X"9E9E9E9E9E9E9E9E9E20E8F8FEFEFEFEFEFEB26868B2FE98EE6698FEFEFEFEFE",
INIT_6E => X"FEFEFEFEFEFEFEFEFEFEFEFEDC4400009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_6F => X"FEFEDC44AAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_70 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000E04040D6FEFEFEFEFEFEFE",
INIT_71 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDC4400009E9E9E9E",
INIT_72 => X"C0204020D8FEFEFEFEFEFEFEFEFEFE0066FEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_73 => X"FEFEFEFEDC440000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0040",
INIT_74 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_75 => X"9E9E9E9E9E9E9E9E9E0044C240402040B2FAFEFEFEFEFEFEFEDC7688EEFEFEFE",
INIT_76 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDC44000000009E9E9E9E9E9E9E9E9E9E",
INIT_77 => X"FEFEFEFEFE102276FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_78 => X"00009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0022BAB220202020206AFEFE",
INIT_79 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDC440000",
INIT_7A => X"AA54FEB2202020202066FEFEFEFEFEFEFEEE00BAFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_7B => X"FEFEFEFEDCBAFEFEDC88220000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00",
INIT_7C => X"FEFEFEFEFEDCBAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_7D => X"9E9E9E9E9E9E9E9E9E9E004454FEFEB2442020202068FEFEFEFEFEFEBAEE44BA",
INIT_7E => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFECC44BAFEFEDC1000009E9E9E9E9E9E9E",
INIT_7F => X"2066FEFEFEFEFEBA44CCDCFEFEFEFEFEFEAA66DCFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \win_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \win_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"FFEFCFFFE68791F00007FFFF3F7FFFF1FEFE00003FFFF3F1FFFFBFE7E00001FF",
INITP_01 => X"FFF007FFFDC679F900007FFF8FBFFFDCE798700007FFFCFCFFFE4C790F00007F",
INITP_02 => X"FFFC1FFFFFE79FF0FC000FFFC03FFFFDC67E670000FFFE00FFFFDC27DFB0000F",
INITP_03 => X"3FFFFFFFFFFFFFFCFFE003FFF1FFFFFFF83FFFFC003FFF83FFFFFE79FF9FC003",
INITP_04 => X"03FFFFFFFFBFFFFFFFFE003FFFFFFFFFFFFFFFFFE003FFFFFFFFFFFFFF8FFE00",
INITP_05 => X"003FFFFFFFF9FFFFFCFFE003FFFFFFFF3FFFFFFFFE003FFFFFFFF3FFFFFFFFE0",
INITP_06 => X"000FFFFFFFFFF07FFE73F8007FFFFFFFFE0FFFC73FC007FFFFFFFFCFFFFC83FE",
INITP_07 => X"EE01FFFFFFFFFFFC7FFCFEC01FFFFFFFFFFFC7FF87EC01FFFFFFFFFFF3FFF73F",
INITP_08 => X"C1FC3FFFFFFFFFFFFF3FFF8F83FFFFFFFFFFFFF7FFF8F83FFFFFFFFFFFF8FFFF",
INITP_09 => X"000003C7FFFFFFE0FFFE0000043E7FFFFFFC1FFFE00000E3FFFFFFFF8FFFFC7F",
INITP_0A => X"000000000000000000000000000000000000000000000000601FF000000003C0",
INITP_0B => X"2000010000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"040000BA00000000000000200005800000000000008000002600000000000000",
INITP_0D => X"30000007A00000000000000000003A00000000000040000003A0000000000000",
INITP_0E => X"7F100003FA000000000008F100001FA0000000000067880004FA000000000000",
INITP_0F => X"3FF20002FFA00000000005FF100017FA00000000002FF000007FA00000000001",
INIT_00 => X"FEFE54009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0044BAFEFEFEFEDA442020",
INIT_01 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE10EE10FEFEFEFEFEFEFEDCEECC10FEFE",
INIT_02 => X"00AA32FEFEFEFEFEFE6620206AB4FEFEFEFEFEDC00AAFEFEFEFEFEBAEEAAEEFE",
INIT_03 => X"FEFEFEFEFEDC760010FEDCFEFEFE5422009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_04 => X"44EEFEFEFEFEDC320054FEFEFEFEFEFEFEFEFEFEFEFEFEDCDCFEFE9844000076",
INIT_05 => X"9E9E9E9E9E9E9E9E9E9E9E000054FEFEFEFEFEFEFC442040D8FEFEFEFEFEFE98",
INIT_06 => X"FEFEFECC88FE106698EE0044EEFEFEFEFECC8898EE444432FEFEDC9888009E9E",
INIT_07 => X"FC440040D6FEFEFEFEFE106676DCFEFEFEFE886698DCFEFEFEFEFEFEFEFEFEFE",
INIT_08 => X"EE00004432FEFEFE88009E9E9E9E9E9E9E9E9E9E9E9E9E000054FEFEFEFEFEFE",
INIT_09 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEBA32AAEEFEAA00FEBAAA0088FEFEFEFE6644FE",
INIT_0A => X"9E9E9E9E0032FEFEFEFEFEFEFE904620D6FEFEFEFE324400FEFEFEFEBA10AAEE",
INIT_0B => X"BAFEFE2288FEFEFEFE8844FE100000002298FEFE88009E9E9E9E9E9E9E9E9E9E",
INIT_0C => X"76000044BAFEFEFE100076FEFEFEFEFEFEFEFEFEFEFEFEFEFE540032FEFEAA22",
INIT_0D => X"88009E9E9E9E9E9E9E9E9E9E9E9E9E000054FEFEFEFEFEFEFEFEB240D6FEFEFE",
INIT_0E => X"FEFEFEFEFE540032FEFECC006654FE4488FEFEFEFE6622FEDC9898989866EEFE",
INIT_0F => X"FEFEFEFEFEFEFCD8FCFEFE104400000066664444AA76FEFEFEFEFEFEFEFEFEFE",
INIT_10 => X"FE10AA32BAFEFEDC548810FE88009E9E9E9E9E9E9E9E9E9E9E9E008876DCFEFE",
INIT_11 => X"32FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE540032FEFECC0000EEFE2288FEFEFE",
INIT_12 => X"9E9E9E9E9E9E0088FEFEFEFEFEFEFEFEFEFEFEFEFEDC54660000000000008888",
INIT_13 => X"FEFEEE000010FE44AAFEFEFEFEFE9800EEFEFEEE0098FEFE88009E9E9E9E9E9E",
INIT_14 => X"FE7600000000000000EEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE540032",
INIT_15 => X"54FEFEFE9810009E9E9E9E9E9E9E9E9E9E9E0088FEFEFEFEFEFEFEFEFEFEFEFE",
INIT_16 => X"FEFEFEFEFEFEFEFEFEDC76AAAAFEDC9898EE663298FEFEFEFEFEFE54CC6666CC",
INIT_17 => X"FEFEFEFEFEFEFEFEFEFEFEFEFE7600000000AA7676BAFEFEFEFEFEFEFEFEFEFE",
INIT_18 => X"FEFEFEFEFEFEFEFE32444432FEFEFEFEFE7600009E9E9E9E9E9E9E9E9E001098",
INIT_19 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEEE6654989898EE66DC",
INIT_1A => X"809E9E9E9E9E9E9E000098FEFEFEFEFEFEFEFEFEFEFEFEFE98EE0044888876FE",
INIT_1B => X"FEFEFEFE9800000000EEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE760020",
INIT_1C => X"FEFEFEFE88000032FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_1D => X"76FEFEFEFEFEFEFEFEDC3286209E9E9E9E9E9E9E000076FEFEFEFEFEFEFEFEFE",
INIT_1E => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE3232323298FEFEFEFEFEFEFE108888",
INIT_1F => X"000076FEFEFEFEFEFEFEFEFEFEFEFEFE543232DCFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_20 => X"FEFEFEFEFEFEFEFEFECC222232FEFEFEFEFEFEFEFEFEFECC009E9E9E9E9E9E9E",
INIT_21 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_22 => X"FEFEFEAC009E9E9E9E9E9E9E000076FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_23 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDCDCFEFEFEFEFEFEFEFE",
INIT_24 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_25 => X"FEFEFEFEFEFEFEFEFEFEFEFEF2EEEEA4009E9E9E9E9E9E9E000076FEFEFEFEFE",
INIT_26 => X"FEFEFEFEFEFEFEFE54EEDCFEFEFEFEFEFEFEFEF4EEEEEEF0FEFEFEFEFEFEFEFE",
INIT_27 => X"9E9E9E9E000076FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_28 => X"E0E0E0E2F6FCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFAE4E0E0A0009E9E9E",
INIT_29 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEAA00BAFEFEFEFEFEFEFEFAE8",
INIT_2A => X"FEFEF4E2E0E0E0A0009E9E9E9E9E9E9E000076FEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_2B => X"AA00DCFEFEFEFEFEFEF6E4E0E0E0E0E0E2F0FEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_2C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_2D => X"FEFE3254FE76F0F01032FEFEFEFEF2E0E0E0E0C0009E9E9E9E9E9E00000076FE",
INIT_2E => X"FEFEFEFEFEFEFEFEFEFEFEFE54CCCC76FEFEFEFEFEF4E0E0E0E0E0E0E0ECFEFE",
INIT_2F => X"009E9E9E9E9E9E0044EEBAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_30 => X"FEF6E0E0E0E0E0E0E0EEFEFEFEFE4466DCCA00000022BAFEFEFEF4E2E0E0C0A0",
INIT_31 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDC22AADCDCDCDC",
INIT_32 => X"8022BAFEFEFEFCF8E68060409E9E9E9E9E9E9E00CCFEFEFEFEFEFEFEFEFEFEFE",
INIT_33 => X"FEFEFEFEFEFE98EE222222449CF8E0E0E0E0E0E0E0ECFEFEFEFE660044228080",
INIT_34 => X"AAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_35 => X"EAF4FEFEFEFE10660040E0E0C002BAFEFEFEFEFE68C0009E9E9E9E9E9E9E9E00",
INIT_36 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE76888888AAF050EEE4E0E0E0E0",
INIT_37 => X"88009E9E9E9E9E9E9E9E00AA32FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_38 => X"FEFEFEFE6668FEECE0E0E0E4FCFEFEFEFEFEFE760020E0E0C024BCFEFEFEFEDC",
INIT_39 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_3A => X"76A64040EC98FEFEFEFE54663432009E9E9E9E9E9E0022BAFEFEFEFEFEFEFEFE",
INIT_3B => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE98106640C2F8FAFAFEFEFEFEFEFEFEDE",
INIT_3C => X"9E0000BAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_3D => X"AC365678FEFEFEFEFEFEFEFEFE12686876FEFEFEFEFE100098DCAA449E9E9E9E",
INIT_3E => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA6668",
INIT_3F => X"FEFE320076FEFEAA009E9E9E0066AABAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_40 => X"FEFEFEFEFEFEFEFEFEFEFEFE98000044BAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_41 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_42 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEEE440076FEFE9810009E9E00EEFEFEFEFEFEFE",
INIT_43 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE5454328832FEFE",
INIT_44 => X"DC88449E00EEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_45 => X"FEFEFEFEFEFEFEDC66AA7676BAFEFEFEFEFEFEFEFEFE987654222288BAFEFEFE",
INIT_46 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA7676DCFEFEFEFEFEFEFE",
INIT_47 => X"FEDC44000000AAFEFEFEFEFEFEFECC0000EEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_48 => X"FEAA000032FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE100000CCFEFEFEFEFEFEFE",
INIT_49 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_4A => X"FEBA322222CCCCCCCCCCCCCCCCAA0000000088EECCCCCCCC32FE100000EEFEFE",
INIT_4B => X"FEFEFEFEFEFEFEFEFEFEFEFEFE98EE0066CCCC76FEFEFEFEFEFEFEFEFEFEFEFE",
INIT_4C => X"000000004498CC0000EEFEFEFEFE32CCCCBAFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_4D => X"98989898989898989898DCFEFEFEBA440000000000000000000000009E9E9E00",
INIT_4E => X"FEFEFEFEFEFEFEFEBA98989898989898989898989898989898BA7600000000AA",
INIT_4F => X"9E9E9E9E9E9E9E9E9E9E9E9E9E0000009E22229E00EEFEBA989866000010BAFE",
INIT_50 => X"222222222222229E9E9E9E002222222222222222222232FEFE322200009E9E9E",
INIT_51 => X"0010FE882222009E9E2288FEFEFEFEFEFEFEFEFEAA2222222222222222222222",
INIT_52 => X"000088EEEE6600009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E009E9E009E9E",
INIT_53 => X"440000000000000000000000000000000000009E9E9E9E9E0000000000000000",
INIT_54 => X"9E9E9E9E9E9E9E9E9E9E9E9E0088EE0000009E9E9E9E22EEEEEEEEEEEEEEEEEE",
INIT_55 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000009E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_56 => X"9E9E9E0000000000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_57 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000009E9E9E",
INIT_58 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_59 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_5A => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_5B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_5C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_5D => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_5E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_5F => X"4444339E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E11669E9E9E9E9E9E9E",
INIT_60 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E6644",
INIT_61 => X"9E9E33CCEE10999E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_62 => X"9E9E9E9E9E9E9E9E99EE00000000EE9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_63 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_64 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E994454FE22EE9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_65 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9ECC0000000022339E9E9E9E9E",
INIT_66 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_67 => X"2200000022999E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E336676FEDC22119E",
INIT_68 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E88",
INIT_69 => X"9E9E9E9EEE22DCFEBA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_6A => X"9E9E9E9E9E9E9E9E9E99EE0000000000449E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_6B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_6C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE66DCFEBA22119E9E9E9E9E9E9E9E9E",
INIT_6D => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE222200000000229E9E9E",
INIT_6E => X"BA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_6F => X"88EEBABACC000000229E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E88EEBAFEFE",
INIT_70 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_71 => X"9E9E9E9E9E99EECC98FEFEFEBA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_72 => X"9E9E9E9E9E9E9E9E9E3311EECC98FEFE10000066119E9E9E9E9E9E9E9E9E9E9E",
INIT_73 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_74 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE66DCFEFEFEFEBA22119E9E9E9E9E",
INIT_75 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E99442266DCFEFEFEEE000011",
INIT_76 => X"FEFEFEFEBA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_77 => X"4476BABAFEFEFEFEEE0000119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E88EEBAFE",
INIT_78 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E33",
INIT_79 => X"9E9E9E9E9E9E9E9E2210FEFEFEFEFEFEBA22119E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_7A => X"9E9E9E9E9E9E9E9E9E9E33CC10FEFEFEFEFEFEFEEE0000EE9E9E9E9E9E9E9E9E",
INIT_7B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_7C => X"EE0022119E9E9E9E9E9E9E9E9E9E9E9E9E9E9EBB4410FEFEFEFEFEFEBA22119E",
INIT_7D => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EBB4432FEFEFEFEFEFEFEFE",
INIT_7E => X"76DCFEFEFEFEFEFEBA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_7F => X"668876DCFEFEFEFEFEFEFEFEEE22779E9E9E9E9E9E9E9E9E9E9E9E9E9E9E3366",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => addra(12),
I1 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \win_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \win_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"FDFF80001FFA00000000003FF00003FFA000000003E3FF00004FFA0000000000",
INITP_01 => X"FFFFD0000FFFC00000023FFFFE80007FFC0000001C3FDFF0001BFFB000000001",
INITP_02 => X"FFFFFE800BFFFC000008FFFFFFC0005FFFC0000071FFFFF80001FFFC0000001F",
INITP_03 => X"FFFFFFFD0083FFC00003FFFFFFFF8003FFFC0000C7FFFFFFE4003FFFC000007F",
INITP_04 => X"FFFFFF0FFA07CFFE0001FFFFFFFFFF0039FFC000EFFFFFFFFFC8101FFC00007F",
INITP_05 => X"DFFFFFC73FC1F9FFA007FFFFFFFC73FC0FCFFA7F87FFFFFFE0FF9EFCFFC0003F",
INITP_06 => X"E7FFFFFE0FFF3F9FE0401F3FFFFFC07FF3F9FE0007FDFFFFFC73FE1F9FFA007F",
INITP_07 => X"FEFF0FFFFFFF8FF7E200100FFFFFFFFFFC7F9FD0000E7FFFFFF0FFF3F9FE0200",
INITP_08 => X"0013C73FDFFFF7FE720000003C73FFFFFF9FE780000007F07FFFFFF8FE7E0000",
INITP_09 => X"0000FF07FEF7FCFFCF4000000FC03F1FFFE7FE74000001BC33F9FFFE7FE74000",
INITP_0A => X"00000FFFFF1CFFFFFCF8000000FFFFFE07F3FFCF8000000FF0FFE67FDFFCF600",
INITP_0B => X"400000FFFFFE3FFFFFCFE800000FFFFC1CFFFFFCFE800000FFFFF1CFFFFFCFD0",
INITP_0C => X"FC000013FFFFFFFFFFFCFFD00000FFFFFFFFFFFFCFF000000FFFFFE3FFFFFCFE",
INITP_0D => X"7FD00000C7FFFF8FFFFFC7FD000003FFFFFE7FFFFCFFD00000BFFFFFFFFFFFCF",
INITP_0E => X"C9E800000007FFFFFFFFFC1E70000003FFFFFFFFFFC1F10000007FFFF9FFFFFC",
INITP_0F => X"F2740000000CFFFFFFFFFF87200000014FFFFFFFFFFC9C000000087FFFFFFFFF",
INIT_00 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E88",
INIT_01 => X"9E9E9E9E9E9E9E9E9E55EEEEFEFEFEFEFEFEFEFEBA22119E9E9E9E9E9E9E9E9E",
INIT_02 => X"9E9E9E9E9E9E9933333311000022FEFEFEFEFEFEFEFEFEFEEE449E9E9E9E9E9E",
INIT_03 => X"BA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_04 => X"FEFEFEFEEE449E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEFEFEFEFEFEFEFE",
INIT_05 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE00000000000044BAFEFEFEFEFE",
INIT_06 => X"9E22EEFEFEFEFEFEFEFEFEFEBA00119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_07 => X"9898989898764410FEFEFEFEFEFEFEFE10229E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_08 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E88666666EE98",
INIT_09 => X"9E9E9E9E9E9E9E9E9E9E9EBB11CC76FEFEFEFEFEFEFEFEFEDCEE10339E9E9E9E",
INIT_0A => X"9E9E9E553311AACCCCCC76FEFEFEFEFEFEFECC54FEFEFEFEFEFEFE54EEEE9E9E",
INIT_0B => X"FEFEFEFEFEFEEE009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0C => X"FEFEFEFEFEFEBA22339E9E9E9E9E9E9E9E9E9E9E9E9E9EEE44DCFEFEFEFEFEFE",
INIT_0D => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9EBB220044DCFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_0E => X"9E9E88EEBAFEFEFEFEFEFEFEFEFEFEFEFEFEEE009E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE3288779E9E9E9E9E9E9E9E9E9E9E9E",
INIT_10 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E8866667698BAFEFE",
INIT_11 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E0010FEFEFEFEFEFEFEFEFEFEFEFEFEFEEE00",
INIT_12 => X"9E553311AACCEEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFECC449E",
INIT_13 => X"FEFEFEFEFEFEFEFEFEFEEE009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_14 => X"FEFEFEFEFEFEFEFEFE10449E9E9E9E9E9E9E9E9E9E9E9E9E9EBB4410FEFEFEFE",
INIT_15 => X"9E9E9E9E9E9E9E9E9E9E9E9EBB220044DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_16 => X"9E9E9E9E338876DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEEE009E9E9E9E9E9E9E9E",
INIT_17 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDC7666559E9E9E9E9E9E9E",
INIT_18 => X"FEFEEE009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EAA6666549898FEFEFEFE",
INIT_19 => X"FEFEFEEEEE559E9E9E9E9E9E9E9E9E9EEE44FEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_1A => X"BB11AACCEEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_1B => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEEE009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_1C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE10449E9E9E9E9E9E9E9E9E9EEE22BAFE",
INIT_1D => X"9E9E9E9E9E9E9E9E9E9E9E9EEE44DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_1E => X"9E9E9E9E9E9E9E9E11004444446654FEFEFEFEFEFEFEFEFEFEFEEE009E9E9E9E",
INIT_1F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEDC546655",
INIT_20 => X"FEFEFEFEFEFEEE009E9E9E9E9E9E9E9E9E9E9E9E9E9E9EAAEE98FEFEFEFEFEFE",
INIT_21 => X"FEFEFEFEFEFEFEFEFEFEEEEE779E9E9E9E9E9E55880088886600EEFEFEFEFEFE",
INIT_22 => X"B75511AA76FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_23 => X"0044DCFEDC22EEFEFEFEFEFEFEFEFEFEFEFEEE009E9E9E9E9E9E9E9E9E9E9E9E",
INIT_24 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE10449E9E9E9E9E9E22",
INIT_25 => X"9E9E9E9E9E9E9E9E9E9E9E9EC84044DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_26 => X"FEFEFEDC5466559E9E9E9E22CC98FEFEFE98CC88DCFEFEFEFEFEFEFEFEFE1000",
INIT_27 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE5466444488FEFEFEFE",
INIT_28 => X"BAFEFEFEFEFEFEFEFE54EEAA9E9E9E9E9E9E9E9E9EAA666600CA98FEFEFEFEFE",
INIT_29 => X"FEFE5488006688AA3298FEFEFEFEFEFEFEEEEE555555112210FEFEFEFEFECC00",
INIT_2A => X"33AAAAAAAA76FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_2B => X"0000000010FEFEFEFEFECC22DCFEFEFEFEFEFEFEBA22119E9EBB555555555555",
INIT_2C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEBA220022DDFFBB00EEFEFEFEFEFEFEFEFEEE00",
INIT_2D => X"DC22119E9EEE00000000000022DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_2E => X"00CCFEFEFEFEFEFEFEFEEE0000000054DCFEFEFEDC88EE98FEFEFEFEFEFEFEFE",
INIT_2F => X"FEFE6610FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA220044FFFFFF",
INIT_30 => X"BA00EEFEFEFEFEFEFEFEFEBA32CC779E442200000000000044FEFEFEFEFEFEFE",
INIT_31 => X"FEFEFEFEFEBA22002233551100EEFEFEFEFEFEFEFEFE54880044CCFEFEFEFEFE",
INIT_32 => X"000000002232BAFEFEFEFEFE98108832FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_33 => X"FEFEFEBA00EEFEFEFEFEFEFEBA00EEFEFEFEFEFEFEFEFEEE449E9E9E88220000",
INIT_34 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA2200000000000010FEFEFEFEFEFE",
INIT_35 => X"FEFEFEEE229E9E9E9E110000000000000000EEFEFEFEFEFECC22DCFEFEFEFEFE",
INIT_36 => X"0000000054DCFEFEF4E8E8E8EAFEFEFE00EEFEFEFEFEFEFEBA00EEFEFEFEFEFE",
INIT_37 => X"FEFEFE88CC76FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE98AA",
INIT_38 => X"FEFEFEFEDC00CCFEFEFEFEFEFEFE76EECC9E9E9E9E9E550000000000000022AA",
INIT_39 => X"FEFEFEFEFEFEFEFEFEFEFE54AAAAAACCFEFEFEF6E8E0E0E0E0F2B43200EEFEFE",
INIT_3A => X"9E9E9ECCAAAAAA440000000032543200EEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_3B => X"E0E0E0E0E0E0E0000010FEFEFEFEFEFEBA22EEFEFEFEFEFEFEBA22119E9E9E9E",
INIT_3C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFAE2",
INIT_3D => X"FEFEFEAA8888559E9E9E9E9E9E9E9E9E9E9E9E11000000000000000010FEFEFE",
INIT_3E => X"FEFEFEFEFEFEFEFEFEFEFAE2E0E0E0E0C0A0200054BAFEFEFEFEFE328854BAFE",
INIT_3F => X"777777777777552210FEFEFEFEFEFEFEAA66666654FEFEFEFEFEFEFEFEFEFEFE",
INIT_40 => X"FEFEFEFEFEFEFEAA00DCFEFEFEBA3288AACC9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_41 => X"EE76FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFAE2E0E0E0E0C00024CC",
INIT_42 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E28AC76FEFEFEFEBA3200228888",
INIT_43 => X"FEFEFAE2E0E0E0E0A000F0FEFEFEFEFEFEFEFECC22DCFEFEFEEE449E9E9E9E9E",
INIT_44 => X"0622DCFEFEFEEE000011FFFFCC00BAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_45 => X"22DCFEDCAAEE999E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E32",
INIT_46 => X"FE3288DCFEFEFEFEFEFEFEFEFEFEFAE0E0E0E0208254BCFEFEFEFEFEFEFEFECC",
INIT_47 => X"9E9E9E9E9E9E9E9E9E9E9EBFCC00BAFEFEFEEE000033FFFFEF00BAFEFEFEFEFE",
INIT_48 => X"02DEFEFEFEFEFEFEFEFEFECC00BAFEBA00119E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_49 => X"00AA77778800BAFEFEFEFEFE766600DCFEFEFEFEFEFEFEFEFEFEFCECE4E0E0A0",
INIT_4A => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9910CCDCFEFEFEEE00",
INIT_4B => X"FEFEFEFEFEFEFEFEEEE0E0C022DCFEFEFEFEFEFEFEFEFECC22DCFEBA22119E9E",
INIT_4C => X"9E9E9E2210FEFEFEFEFEEE00000000000022DCFEFEFEFEBA220022DCFEFEFEFE",
INIT_4D => X"FEDCAAEE76FEFEBA00119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_4E => X"FEFEFEFE7676548854FEFE32AADCFEFEFEFEFEFEFCF480C876FEFEFEFEFEFEFE",
INIT_4F => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEFEFEFEBA3200000000AA76FEFE",
INIT_50 => X"9A346834FEFEFEFEFEFEFEFEFEBA00EEFEFEFEDCAA10779E9E9E9E9E9E9E9E9E",
INIT_51 => X"FEFEFEFEAA88888876FEFEFEFEFEFEFEFEFEFE006856766600BAFEFEFEFEFEFE",
INIT_52 => X"FEEE449E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEFE",
INIT_53 => X"0000000022DCFEFEFEFEFEFECC22DCFEFEFEFEFEFEFEFEFEFEBA00EEFEFEFEFE",
INIT_54 => X"9E9E9E9E9E9E9E2210FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA22",
INIT_55 => X"FEFEFEFEFEBA00EEFEFEFEFEFEEE229E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_56 => X"FEFEFEFEFEFEFEFECC88A8404000008A76FEFEFEFEFEFEFE9854FEFEFEFEFEFE",
INIT_57 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEFEFEFEFEFEFEFEFEFE",
INIT_58 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA00EEFEFEFEFEFE54AA559E9E9E9E",
INIT_59 => X"10FEFEFEFEF6F6F6F6FCFEFEFEFEFEFEFEFEBA32000000E0E0E000F0FEFEFEFE",
INIT_5A => X"FEFEFEFEFEFEBA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E22",
INIT_5B => X"000020C0E0A000F0FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA00EE",
INIT_5C => X"9E9E9E9E9E9E9E9E9E9E9E2210FEFEFEFCE2E0E0E0F0FEFEFEFEFEFEFEFEEE00",
INIT_5D => X"FEFEFEFEFEFEFEFEFEBA00EEFEFEFEFEFEFEDC00119E9E9E9E9E9E9E9E9E9E9E",
INIT_5E => X"E0E4ECFCFEFEFEFEFEFEBA5454765280608032BAFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_5F => X"EE999E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEF4E8E0E0E0",
INIT_60 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA00EEFEFEFEFEFEFEDCAA",
INIT_61 => X"9E9E9E2210FEFEECE0E0E0E0E0E0E0FAFEFEFEFEFEFEFEFEFEFEFE8A688AFEFE",
INIT_62 => X"FEBA00EEFEFEFEFEFEFEFEFEEE449E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_63 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_64 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEEEE0E0E0E0E0E0E2FCFEFEFEFE",
INIT_65 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEBA00EEFEFEFEFEFEFEFEFEBA32AA559E9E9E9E",
INIT_66 => X"E0E0E0E0E0E0E0FAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_67 => X"FEFEFEFEFEDC22EE9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E77EECCDEEE",
INIT_68 => X"FEFEFEBA76FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA00EEFEFEFEFE",
INIT_69 => X"9E9E9E9E9E9E9E9E1102DEF6E6E0E0E0E0E2EAFCFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_6A => X"FEFEFEFEFEBA00EEFEFEFEFEFEFEFEFEFEBA22119E9E9E9E9E9E9E9E9E9E9E9E",
INIT_6B => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFECC22DCFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_6C => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE22DCFEFAE2E0E0E0EEFEFE",
INIT_6D => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA2244CCFEFEFEFEFEFEFEFEDC2211",
INIT_6E => X"BB33A8AACCF4F4F4F4FAFEFEFEFEFEFEFEFEFEFEFEFEFEFE328888CC54FEFEFE",
INIT_6F => X"4254BAFEFEFEFEFEBA5464319E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_70 => X"FEFEFEFE32444454FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA2200",
INIT_71 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9EAA886856DEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_72 => X"FEFEFEFEFEFEFEFEFEBA2262E600F0FEFEFEFEFEEE00E6959E9E9E9E9E9E9E9E",
INIT_73 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_74 => X"CE55B7DD9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E4410FE",
INIT_75 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA2262E600EEFEFEFEFECC",
INIT_76 => X"9E9E9E9E9E9E9E9E9E4422AA8854FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_77 => X"FEDC22820800EEFEFEDC5466559E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_78 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_79 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E558822004432FEFEFEFEFEFE",
INIT_7A => X"FEFEFEFEFEFEFEFEFEFEFEFEFEDC02E68C00EEFEFE10229E9E9E9E9E9E9E9E9E",
INIT_7B => X"44DCEE00BAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_7C => X"CCEE779E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E11",
INIT_7D => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE54AA8A86A63098DC",
INIT_7E => X"9E9E9E9E9E9E9E9E9E9EEEEE76FEEE22DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_7F => X"FEFEFEFECC002E6600DEFEBA00119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[10]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \douta[11]\(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => addra(13),
I1 => addra(12),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \win_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \win_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"FF1F4000000BCFFFFFFFFFF0F40000001CFFFFFFFFFF2740000001CFFFFFFFFF",
INITP_01 => X"FFFBF4000000FCFFFFFFFFFF3F00000003CFFFFFFFFFF3F40000003CFFFFFFFF",
INITP_02 => X"FFFFCF0000000FCFFFFFFFFFFCE4000000FCFFFFFFFFFFCC0000000FCFFFFFFF",
INITP_03 => X"FFFFFF74000000FCFFFFFFFFFFFF4000000FCFFFFFFFFFFCF4000000FCFFFFFF",
INITP_04 => X"FFFFFFE6400000138FFFFFFFFFFE70000000FCFFFFFFFFFFE74000000FCFFFFF",
INITP_05 => X"FFFFFFFE400000003AFFFFFFFFFFE4000000042FFFFFFFFFFE48000000B8FFFF",
INITP_06 => X"FFFFFFFFC2000000000FFFFFFFFFFE1000000000FFFFFFFFFFE4000000000FFF",
INITP_07 => X"FFFFFFFFC80000000000FFFFFFFFFC40000000000FFFFFFFFFFA0000000000FF",
INITP_08 => X"1FFFFFFFFFC00000000009FFFFFFFFF900000000017FFFFFFFFF00000000002F",
INITP_09 => X"0FF800200FFF80000000027FC0FC01FFF20000000003FFE00FFFFE0000000000",
INITP_0A => X"0000000000200000000000180200003C00C000000003FF0000043FFE00000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_01 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0010FEFECC22DCFEFEFE",
INIT_02 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFECE00ACC402BCFEBA22119E9E9E9E9E9E",
INIT_03 => X"9E9E2210FEFECC22DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_04 => X"54FEFEBA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_05 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEEE0082EA",
INIT_06 => X"9E9E9E9E9E9E9E9E9E9E9E9E55CC3298FEFECC22DCFEFEFEFEFEFEFEFEFEFEFE",
INIT_07 => X"FEFEFEFEFEFEFEFEEE004454FEFEFEBA22119E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_08 => X"DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_09 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE22FEFEFEFECC22",
INIT_0A => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFECC00BAFEFEFEFEBA22119E9E",
INIT_0B => X"9E9E9E9EEE22DCFEFEFECC22DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_0C => X"AA00FEFEFEFEFEDC22EE9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_0D => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_0E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EEE1054FEFEFEFECC22DCFEFEFEFEFEFEFE",
INIT_0F => X"FEFEFEFEFEFEFEFEFEFEFEFE106676DCFEFEDC7688559E9E9E9E9E9E9E9E9E9E",
INIT_10 => X"FEFECC22DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_11 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0010FEFEFE",
INIT_12 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA22EEFEFEF044",
INIT_13 => X"9E9E9E9E9E9E9E2210FEFEFEFEFECC22DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_14 => X"FEFEFEFEFEDC00A48C8C04A0CC779E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_15 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_16 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEFEFEFECC22DCFEFEFE",
INIT_17 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA02604020402020EE9E9E9E9E9E9E",
INIT_18 => X"10FEFEFEFEFECC22DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_19 => X"4020400020119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E22",
INIT_1A => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEBA0260",
INIT_1B => X"9E9E9E9E9E9E9E9E9E9E9E2210FEFEFEFEFECC22DCFEFEFEFEFEFEFEFEFEFEFE",
INIT_1C => X"FEFEFEFEFEFEFEFEFEFE32284040400020119E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_1D => X"DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_1E => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEFEFEFECC22",
INIT_1F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE90E020400020119E9E",
INIT_20 => X"9E9E9E2210FEFEFEFEFECC00BAFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_21 => X"FEFEFEEE0000600020119E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_22 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_23 => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E2210FEFEFEFEFECC00BAFEFEFEFEFEFEFE",
INIT_24 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFECE0000602020EE9E9E9E9E9E9E9E9E9E9E",
INIT_25 => X"FEEE4422DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_26 => X"64339E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E55EEEEFEFE",
INIT_27 => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEEE000040E0",
INIT_28 => X"9E9E9E9E9E9E9E9E334476BA76662244DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_29 => X"FEFEFEFEFEFEFEEE0020A042BB9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2A => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_2B => X"9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E994422449E1122DCFEFEFE",
INIT_2C => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEEE0020A0449E9E9E9E9E9E9E9E",
INIT_2D => X"9E9E3311559E1122DCFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFE",
INIT_2E => X"0020A0229E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E",
INIT_2F => X"FEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEFEEE",
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INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => DOPADOP(0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of win_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end win_blk_mem_gen_prim_width;
architecture STRUCTURE of win_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.win_blk_mem_gen_prim_wrapper_init
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \win_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \win_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\win_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(1 downto 0) => dina(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_width__parameterized1\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \win_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \win_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\win_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_width__parameterized2\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \win_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \win_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\win_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_width__parameterized3\ is
port (
\douta[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\douta[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \win_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \win_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\win_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
\douta[10]\(7 downto 0) => \douta[10]\(7 downto 0),
\douta[11]\(0) => \douta[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \win_blk_mem_gen_prim_width__parameterized4\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPADOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \win_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \win_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \win_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\win_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
DOPADOP(0) => DOPADOP(0),
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of win_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end win_blk_mem_gen_generic_cstr;
architecture STRUCTURE of win_blk_mem_gen_generic_cstr is
signal ena_array : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_8\ : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.win_bindec
port map (
addra(1 downto 0) => addra(13 downto 12),
ena_array(1) => ena_array(3),
ena_array(0) => ena_array(0)
);
\has_mux_a.A\: entity work.win_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7) => \ramloop[3].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6) => \ramloop[3].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5) => \ramloop[3].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4) => \ramloop[3].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3) => \ramloop[3].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2) => \ramloop[3].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1) => \ramloop[3].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0) => \ramloop[3].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[4].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[4].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[4].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[4].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[4].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[4].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[4].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(7) => \ramloop[2].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(6) => \ramloop[2].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(5) => \ramloop[2].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(4) => \ramloop[2].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(3) => \ramloop[2].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(2) => \ramloop[2].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(1) => \ramloop[2].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[2].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[3].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(0) => \ramloop[4].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\(0) => \ramloop[2].ram.r_n_8\,
DOADO(7) => \ramloop[5].ram.r_n_0\,
DOADO(6) => \ramloop[5].ram.r_n_1\,
DOADO(5) => \ramloop[5].ram.r_n_2\,
DOADO(4) => \ramloop[5].ram.r_n_3\,
DOADO(3) => \ramloop[5].ram.r_n_4\,
DOADO(2) => \ramloop[5].ram.r_n_5\,
DOADO(1) => \ramloop[5].ram.r_n_6\,
DOADO(0) => \ramloop[5].ram.r_n_7\,
DOPADOP(0) => \ramloop[5].ram.r_n_8\,
addra(1 downto 0) => addra(13 downto 12),
clka => clka,
douta(8 downto 0) => douta(11 downto 3)
);
\ramloop[0].ram.r\: entity work.win_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(0) => dina(0),
douta(0) => douta(0),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\win_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(1 downto 0) => dina(2 downto 1),
douta(1 downto 0) => douta(2 downto 1),
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\win_blk_mem_gen_prim_width__parameterized1\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[2].ram.r_n_0\,
\douta[10]\(6) => \ramloop[2].ram.r_n_1\,
\douta[10]\(5) => \ramloop[2].ram.r_n_2\,
\douta[10]\(4) => \ramloop[2].ram.r_n_3\,
\douta[10]\(3) => \ramloop[2].ram.r_n_4\,
\douta[10]\(2) => \ramloop[2].ram.r_n_5\,
\douta[10]\(1) => \ramloop[2].ram.r_n_6\,
\douta[10]\(0) => \ramloop[2].ram.r_n_7\,
\douta[11]\(0) => \ramloop[2].ram.r_n_8\,
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\win_blk_mem_gen_prim_width__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[3].ram.r_n_0\,
\douta[10]\(6) => \ramloop[3].ram.r_n_1\,
\douta[10]\(5) => \ramloop[3].ram.r_n_2\,
\douta[10]\(4) => \ramloop[3].ram.r_n_3\,
\douta[10]\(3) => \ramloop[3].ram.r_n_4\,
\douta[10]\(2) => \ramloop[3].ram.r_n_5\,
\douta[10]\(1) => \ramloop[3].ram.r_n_6\,
\douta[10]\(0) => \ramloop[3].ram.r_n_7\,
\douta[11]\(0) => \ramloop[3].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[4].ram.r\: entity work.\win_blk_mem_gen_prim_width__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
\douta[10]\(7) => \ramloop[4].ram.r_n_0\,
\douta[10]\(6) => \ramloop[4].ram.r_n_1\,
\douta[10]\(5) => \ramloop[4].ram.r_n_2\,
\douta[10]\(4) => \ramloop[4].ram.r_n_3\,
\douta[10]\(3) => \ramloop[4].ram.r_n_4\,
\douta[10]\(2) => \ramloop[4].ram.r_n_5\,
\douta[10]\(1) => \ramloop[4].ram.r_n_6\,
\douta[10]\(0) => \ramloop[4].ram.r_n_7\,
\douta[11]\(0) => \ramloop[4].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[5].ram.r\: entity work.\win_blk_mem_gen_prim_width__parameterized4\
port map (
DOADO(7) => \ramloop[5].ram.r_n_0\,
DOADO(6) => \ramloop[5].ram.r_n_1\,
DOADO(5) => \ramloop[5].ram.r_n_2\,
DOADO(4) => \ramloop[5].ram.r_n_3\,
DOADO(3) => \ramloop[5].ram.r_n_4\,
DOADO(2) => \ramloop[5].ram.r_n_5\,
DOADO(1) => \ramloop[5].ram.r_n_6\,
DOADO(0) => \ramloop[5].ram.r_n_7\,
DOPADOP(0) => \ramloop[5].ram.r_n_8\,
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(11 downto 3),
ena_array(0) => ena_array(3),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of win_blk_mem_gen_top : entity is "blk_mem_gen_top";
end win_blk_mem_gen_top;
architecture STRUCTURE of win_blk_mem_gen_top is
begin
\valid.cstr\: entity work.win_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
clka : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of win_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end win_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of win_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.win_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of win_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of win_blk_mem_gen_v8_3_5 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of win_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of win_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of win_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of win_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of win_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of win_blk_mem_gen_v8_3_5 : entity is "5";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of win_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of win_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of win_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of win_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 6.227751 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of win_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of win_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of win_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of win_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of win_blk_mem_gen_v8_3_5 : entity is "win.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of win_blk_mem_gen_v8_3_5 : entity is "win.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of win_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of win_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of win_blk_mem_gen_v8_3_5 : entity is 15120;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of win_blk_mem_gen_v8_3_5 : entity is 15120;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of win_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of win_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of win_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of win_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of win_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of win_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of win_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of win_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of win_blk_mem_gen_v8_3_5 : entity is 15120;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of win_blk_mem_gen_v8_3_5 : entity is 15120;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of win_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of win_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of win_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of win_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of win_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of win_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of win_blk_mem_gen_v8_3_5 : entity is "yes";
end win_blk_mem_gen_v8_3_5;
architecture STRUCTURE of win_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.win_blk_mem_gen_v8_3_5_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity win is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of win : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of win : entity is "win,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of win : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of win : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end win;
architecture STRUCTURE of win is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "5";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 6.227751 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "win.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "win.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 15120;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 15120;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 15120;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 15120;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.win_blk_mem_gen_v8_3_5
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => B"00000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
--------------------------------------------
-- Project: YARR
-- Author: Timon Heim (timon.heim@cern.ch)
-- Description: Top module for YARR on SPEC
-- Dependencies: -
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.board_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity yarr is
port
(
-- On board 20MHz oscillator
clk20_vcxo_i : in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
pll25dac_sync_n : out std_logic; -- 25MHz VCXO
pll20dac_sync_n : out std_logic; -- 20MHz VCXO
plldac_din : out std_logic;
plldac_sclk : out std_logic;
-- From GN4124 Local bus
L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
clk_125m_pllref_n_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
GPIO : out std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+
P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data
P2L_DFRAME : in std_logic; -- Receive Frame
P2L_VALID : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready
RX_ERROR : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data
L2P_DFRAME : out std_logic; -- Transmit Data Frame
L2P_VALID : out std_logic; -- Transmit Data Valid
L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-
L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+
L2P_EDB : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
L2P_RDY : in std_logic; -- Tx Buffer Full Flag
L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
TX_ERROR : in std_logic; -- Transmit Error
VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
-- Font panel LEDs
led_red_o : out std_logic;
led_green_o : out std_logic;
-- Auxiliary pins
AUX_LEDS_O : out std_logic_vector(3 downto 0);
AUX_BUTTONS_I : in std_logic_vector(1 downto 0);
-- PCB version
pcb_ver_i : in std_logic_vector(3 downto 0);
-- DDR3
DDR3_CAS_N : out std_logic;
DDR3_CK_P : out std_logic;
DDR3_CK_N : out std_logic;
DDR3_CKE : out std_logic;
DDR3_LDM : out std_logic;
DDR3_LDQS_N : inout std_logic;
DDR3_LDQS_P : inout std_logic;
DDR3_ODT : out std_logic;
DDR3_RAS_N : out std_logic;
DDR3_RESET_N : out std_logic;
DDR3_UDM : out std_logic;
DDR3_UDQS_N : inout std_logic;
DDR3_UDQS_P : inout std_logic;
DDR3_WE_N : out std_logic;
DDR3_RZQ : inout std_logic;
DDR3_ZIO : inout std_logic;
DDR3_A : out std_logic_vector(13 downto 0);
DDR3_BA : out std_logic_vector(2 downto 0);
DDR3_DQ : inout std_logic_vector(15 downto 0);
---------------------------------------------------------
-- FMC
---------------------------------------------------------
DAC_LD : out std_logic;
INJ_SW : out std_logic;
DAC_DIN : out std_logic;
DAC_CLK : out std_logic;
DAC_CS : out std_logic;
TRIGGER_P : out std_logic;
TRIGGER_N : out std_logic;
CLK_DATA_P : out std_logic;
CLK_DATA_N : out std_logic;
RST_0_P : out std_logic;
RST_0_N : out std_logic;
CLK_CNFG_P : out std_logic;
CLK_CNFG_N : out std_logic;
PIX_D_CNFG_P : out std_logic;
PIX_D_CNFG_N : out std_logic;
LD_CNFG_P : out std_logic;
LD_CNFG_N : out std_logic;
CLK_BX_P : out std_logic;
CLK_BX_N : out std_logic;
RST_1_P : out std_logic;
RST_1_N : out std_logic;
EN_PIX_SR_CNFG_P : out std_logic;
EN_PIX_SR_CNFG_N : out std_logic;
SI_CNFG_P : out std_logic;
SI_CNFG_N : out std_logic;
SO_CNFG_P : in std_logic;
SO_CNFG_N : in std_logic;
HIT_OR_P : in std_logic;
HIT_OR_N : in std_logic;
OUT_DATA_P : in std_logic;
OUT_DATA_N : in std_logic;
EXT_4_P : out std_logic;
EXT_4_N : out std_logic;
EXT_3_P : in std_logic;
EXT_3_N : in std_logic;
EXT_2_P : out std_logic;
EXT_2_N : out std_logic;
EXT_1_P : in std_logic;
EXT_1_N : in std_logic;
IO_0 : out std_logic;
IO_1 : in std_logic
);
end yarr;
architecture rtl of yarr is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
COMPONENT fe65p2_addon
PORT(
clk_i : IN std_logic;
rst_n : IN std_logic;
serial_in : IN std_logic;
clk_rx_i : IN std_logic;
clk_bx_o : OUT std_logic;
trig_o : OUT std_logic;
clk_cnfg_o : OUT std_logic;
en_pix_sr_cnfg_o : OUT std_logic;
ld_cnfg_o : OUT std_logic;
si_cnfg_o : OUT std_logic;
pix_d_cnfg_o : OUT std_logic;
clk_data_o : OUT std_logic;
rst_0_o : OUT std_logic;
rst_1_o : OUT std_logic;
dac_sclk_o : OUT std_logic;
dac_sdi_o : OUT std_logic;
dac_ld_o : OUT std_logic;
dac_cs_o : OUT std_logic;
inj_sw_o : OUT std_logic
);
END COMPONENT;
component gn4124_core
port
(
---------------------------------------------------------
-- Control and status
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
status_o : out std_logic_vector(31 downto 0); -- Core status output
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
-- P2L Control
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
-- L2P Control
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
---------------------------------------------------------
-- Interrupt interface
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i : in std_logic;
dma_reg_adr_i : in std_logic_vector(31 downto 0);
dma_reg_dat_i : in std_logic_vector(31 downto 0);
dma_reg_sel_i : in std_logic_vector(3 downto 0);
dma_reg_stb_i : in std_logic;
dma_reg_we_i : in std_logic;
dma_reg_cyc_i : in std_logic;
dma_reg_dat_o : out std_logic_vector(31 downto 0);
dma_reg_ack_o : out std_logic;
dma_reg_stall_o : out std_logic;
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i : in std_logic;
csr_adr_o : out std_logic_vector(31 downto 0);
csr_dat_o : out std_logic_vector(31 downto 0);
csr_sel_o : out std_logic_vector(3 downto 0);
csr_stb_o : out std_logic;
csr_we_o : out std_logic;
csr_cyc_o : out std_logic;
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
csr_err_i : in std_logic;
csr_rty_i : in std_logic;
csr_int_i : in std_logic;
---------------------------------------------------------
-- DMA interface (Pipelined wishbone master)
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0);
dma_sel_o : out std_logic_vector(3 downto 0);
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic;
dma_dat_i : in std_logic_vector(31 downto 0);
dma_ack_i : in std_logic;
dma_stall_i : in std_logic;
dma_err_i : in std_logic;
dma_rty_i : in std_logic;
dma_int_i : in std_logic
);
end component; -- gn4124_core
component wb_addr_decoder
generic
(
g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address)
g_WB_SLAVES_NB : integer := 2
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i : in std_logic_vector(31 downto 0); -- Address
wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out
wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wbm_stb_i : in std_logic; -- Strobe
wbm_we_i : in std_logic; -- Write
wbm_cyc_i : in std_logic; -- Cycle
wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in
wbm_ack_o : out std_logic; -- Acknowledge
wbm_stall_o : out std_logic; -- Stall
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o : out std_logic_vector(31 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge
wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall
);
end component wb_addr_decoder;
component wb_tx_core
generic (
g_NUM_TX : integer range 1 to 32 := c_TX_CHANNELS
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- TX
tx_clk_i : in std_logic;
tx_data_o : out std_logic_vector(g_NUM_TX-1 downto 0);
trig_pulse_o : out std_logic;
-- Async
ext_trig_i : in std_logic
);
end component;
component wb_rx_core
generic (
g_NUM_RX : integer range 1 to 32 := c_RX_CHANNELS
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- RX IN
rx_clk_i : in std_logic;
rx_serdes_clk_i : in std_logic;
rx_data_i : in std_logic_vector(g_NUM_RX-1 downto 0);
trig_tag_i : in std_logic_vector(31 downto 0);
-- RX OUT (sync to sys_clk)
rx_valid_o : out std_logic;
rx_data_o : out std_logic_vector(31 downto 0);
busy_o : out std_logic;
debug_o : out std_logic_vector(31 downto 0)
);
end component;
component wb_rx_bridge is
port (
-- Sys Connect
sys_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Wishbone DMA Master Interface
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0);
dma_dat_i : in std_logic_vector(31 downto 0);
dma_cyc_o : out std_logic;
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_ack_i : in std_logic;
dma_stall_i : in std_logic;
-- Rx Interface
rx_data_i : in std_logic_vector(31 downto 0);
rx_valid_i : in std_logic;
-- Status in
trig_pulse_i : in std_logic;
-- Status out
irq_o : out std_logic;
busy_o : out std_logic
);
end component;
component i2c_master_wb_top
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
arst_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(7 downto 0);
wb_dat_o : out std_logic_vector(7 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_inta_o: out std_logic;
scl : inout std_logic;
sda : inout std_logic
);
end component;
component wb_trigger_logic
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- To/From outside world
ext_trig_i : in std_logic_vector(3 downto 0);
ext_trig_o : out std_logic;
ext_busy_i : in std_logic;
ext_busy_o : out std_logic;
-- Eudet TLU
eudet_clk_o : out std_logic;
eudet_busy_o : out std_logic;
eudet_trig_i : in std_logic;
eudet_rst_i : in std_logic;
-- To/From inside world
clk_i : in std_logic;
trig_tag : out std_logic_vector(31 downto 0);
debug_o : out std_logic_vector(31 downto 0)
);
end component;
component ddr3_ctrl
generic(
--! Bank and port size selection
g_BANK_PORT_SELECT : string := "SPEC_BANK3_32B_32B";
--! Core's clock period in ps
g_MEMCLK_PERIOD : integer := 3000;
--! If TRUE, uses Xilinx calibration core (Input term, DQS centering)
g_CALIB_SOFT_IP : string := "TRUE";
--! User ports addresses maping (BANK_ROW_COLUMN or ROW_BANK_COLUMN)
g_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--! Simulation mode
g_SIMULATION : string := "FALSE";
--! DDR3 data port width
g_NUM_DQ_PINS : integer := 16;
--! DDR3 address port width
g_MEM_ADDR_WIDTH : integer := 14;
--! DDR3 bank address width
g_MEM_BANKADDR_WIDTH : integer := 3;
--! Wishbone port 0 data mask size (8-bit granularity)
g_P0_MASK_SIZE : integer := 4;
--! Wishbone port 0 data width
g_P0_DATA_PORT_SIZE : integer := 32;
--! Port 0 byte address width
g_P0_BYTE_ADDR_WIDTH : integer := 30;
--! Wishbone port 1 data mask size (8-bit granularity)
g_P1_MASK_SIZE : integer := 4;
--! Wishbone port 1 data width
g_P1_DATA_PORT_SIZE : integer := 32;
--! Port 1 byte address width
g_P1_BYTE_ADDR_WIDTH : integer := 30
);
port(
----------------------------------------------------------------------------
-- Clock, control and status
----------------------------------------------------------------------------
--! Clock input
clk_i : in std_logic;
--! Reset input (active low)
rst_n_i : in std_logic;
--! Status output
status_o : out std_logic_vector(31 downto 0);
----------------------------------------------------------------------------
-- DDR3 interface
----------------------------------------------------------------------------
--! DDR3 data bus
ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0);
--! DDR3 address bus
ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0);
--! DDR3 bank address
ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0);
--! DDR3 row address strobe
ddr3_ras_n_o : out std_logic;
--! DDR3 column address strobe
ddr3_cas_n_o : out std_logic;
--! DDR3 write enable
ddr3_we_n_o : out std_logic;
--! DDR3 on-die termination
ddr3_odt_o : out std_logic;
--! DDR3 reset
ddr3_rst_n_o : out std_logic;
--! DDR3 clock enable
ddr3_cke_o : out std_logic;
--! DDR3 lower byte data mask
ddr3_dm_o : out std_logic;
--! DDR3 upper byte data mask
ddr3_udm_o : out std_logic;
--! DDR3 lower byte data strobe (pos)
ddr3_dqs_p_b : inout std_logic;
--! DDR3 lower byte data strobe (neg)
ddr3_dqs_n_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_p_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_n_b : inout std_logic;
--! DDR3 clock (pos)
ddr3_clk_p_o : out std_logic;
--! DDR3 clock (neg)
ddr3_clk_n_o : out std_logic;
--! MCB internal termination calibration resistor
ddr3_rzq_b : inout std_logic;
--! MCB internal termination calibration
ddr3_zio_b : inout std_logic;
----------------------------------------------------------------------------
-- Wishbone bus - Port 0
----------------------------------------------------------------------------
--! Wishbone bus clock
wb0_clk_i : in std_logic;
--! Wishbone bus byte select
wb0_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
--! Wishbone bus cycle select
wb0_cyc_i : in std_logic;
--! Wishbone bus cycle strobe
wb0_stb_i : in std_logic;
--! Wishbone bus write enable
wb0_we_i : in std_logic;
--! Wishbone bus address
wb0_addr_i : in std_logic_vector(31 downto 0);
--! Wishbone bus data input
wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus data output
wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus acknowledge
wb0_ack_o : out std_logic;
--! Wishbone bus stall (for pipelined mode)
wb0_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Status - Port 0
----------------------------------------------------------------------------
--! Command FIFO empty
p0_cmd_empty_o : out std_logic;
--! Command FIFO full
p0_cmd_full_o : out std_logic;
--! Read FIFO full
p0_rd_full_o : out std_logic;
--! Read FIFO empty
p0_rd_empty_o : out std_logic;
--! Read FIFO count
p0_rd_count_o : out std_logic_vector(6 downto 0);
--! Read FIFO overflow
p0_rd_overflow_o : out std_logic;
--! Read FIFO error (pointers unsynchronized, reset required)
p0_rd_error_o : out std_logic;
--! Write FIFO full
p0_wr_full_o : out std_logic;
--! Write FIFO empty
p0_wr_empty_o : out std_logic;
--! Write FIFO count
p0_wr_count_o : out std_logic_vector(6 downto 0);
--! Write FIFO underrun
p0_wr_underrun_o : out std_logic;
--! Write FIFO error (pointers unsynchronized, reset required)
p0_wr_error_o : out std_logic;
----------------------------------------------------------------------------
-- Wishbone bus - Port 1
----------------------------------------------------------------------------
--! Wishbone bus clock
wb1_clk_i : in std_logic;
--! Wishbone bus byte select
wb1_sel_i : in std_logic_vector(g_P1_MASK_SIZE - 1 downto 0);
--! Wishbone bus cycle select
wb1_cyc_i : in std_logic;
--! Wishbone bus cycle strobe
wb1_stb_i : in std_logic;
--! Wishbone bus write enable
wb1_we_i : in std_logic;
--! Wishbone bus address
wb1_addr_i : in std_logic_vector(31 downto 0);
--! Wishbone bus data input
wb1_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus data output
wb1_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus acknowledge
wb1_ack_o : out std_logic;
--! Wishbone bus stall (for pipelined mode)
wb1_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Status - Port 1
----------------------------------------------------------------------------
--! Command FIFO empty
p1_cmd_empty_o : out std_logic;
--! Command FIFO full
p1_cmd_full_o : out std_logic;
--! Read FIFO full
p1_rd_full_o : out std_logic;
--! Read FIFO empty
p1_rd_empty_o : out std_logic;
--! Read FIFO count
p1_rd_count_o : out std_logic_vector(6 downto 0);
--! Read FIFO overflow
p1_rd_overflow_o : out std_logic;
--! Read FIFO error (pointers unsynchronized, reset required)
p1_rd_error_o : out std_logic;
--! Write FIFO full
p1_wr_full_o : out std_logic;
--! Write FIFO empty
p1_wr_empty_o : out std_logic;
--! Write FIFO count
p1_wr_count_o : out std_logic_vector(6 downto 0);
--! Write FIFO underrun
p1_wr_underrun_o : out std_logic;
--! Write FIFO error (pointers unsynchronized, reset required)
p1_wr_error_o : out std_logic
);
end component ddr3_ctrl;
component clk_gen
port
(-- Clock in ports
CLK_40_IN : in std_logic;
CLKFB_IN : in std_logic;
-- Clock out ports
CLK_640 : out std_logic;
CLK_160 : out std_logic;
CLK_80 : out std_logic;
CLK_40 : out std_logic;
CLK_40_90 : out std_logic;
CLKFB_OUT : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
component ila
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
TRIG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
end component;
component ila_icon
PORT (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
end component;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_BAR0_APERTURE : integer := 18; -- nb of bits for 32-bit word address
constant c_CSR_WB_SLAVES_NB : integer := 16; -- upper 4 bits used for addressing slave
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- System clock
signal sys_clk : std_logic;
-- IO clocks
signal CLK_40 : std_logic;
signal CLK_80 : std_logic;
signal CLK_125 : std_logic;
signal CLK_160 : std_logic;
signal CLK_640 : std_logic;
signal CLK_40_buf : std_logic;
signal CLK_40_90_buf : std_logic;
signal CLK_80_buf : std_logic;
signal CLK_160_buf : std_logic;
signal CLK_640_buf : std_logic;
signal ioclk_fb : std_logic;
-- System clock generation
signal sys_clk_in : std_logic;
signal sys_clk_40_buf : std_logic;
signal sys_clk_200_buf : std_logic;
signal sys_clk_40 : std_logic;
signal sys_clk_200 : std_logic;
signal sys_clk_fb : std_logic;
signal sys_clk_pll_locked : std_logic;
-- DDR3 clock
signal ddr_clk : std_logic;
signal ddr_clk_buf : std_logic;
signal locked : std_logic;
signal locked_v : std_logic_vector(1 downto 0);
signal rst_n : std_logic;
-- LCLK from GN4124 used as system clock
signal l_clk : std_logic;
-- P2L colck PLL status
signal p2l_pll_locked : std_logic;
-- CSR wishbone bus (master)
signal wbm_adr : std_logic_vector(31 downto 0);
signal wbm_dat_i : std_logic_vector(31 downto 0);
signal wbm_dat_o : std_logic_vector(31 downto 0);
signal wbm_sel : std_logic_vector(3 downto 0);
signal wbm_cyc : std_logic;
signal wbm_stb : std_logic;
signal wbm_we : std_logic;
signal wbm_ack : std_logic;
signal wbm_stall : std_logic;
-- CSR wishbone bus (slaves)
signal wb_adr : std_logic_vector(31 downto 0);
signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0) := (others => '0');
signal wb_dat_o : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0');
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0');
signal wb_stall : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0');
-- DMA wishbone bus
signal dma_adr : std_logic_vector(31 downto 0);
signal dma_dat_i : std_logic_vector(31 downto 0);
signal dma_dat_o : std_logic_vector(31 downto 0);
signal dma_sel : std_logic_vector(3 downto 0);
signal dma_cyc : std_logic;
signal dma_stb : std_logic;
signal dma_we : std_logic;
signal dma_ack : std_logic;
signal dma_stall : std_logic;
signal ram_we : std_logic;
-- DMAbus RX bridge
signal rx_dma_adr : std_logic_vector(31 downto 0);
signal rx_dma_dat_o : std_logic_vector(31 downto 0);
signal rx_dma_dat_i : std_logic_vector(31 downto 0);
signal rx_dma_cyc : std_logic;
signal rx_dma_stb : std_logic;
signal rx_dma_we : std_logic;
signal rx_dma_ack : std_logic;
signal rx_dma_stall : std_logic;
-- Interrupts stuff
signal irq_sources : std_logic_vector(1 downto 0);
signal irq_to_gn4124 : std_logic;
signal irq_out : std_logic;
-- CSR whisbone slaves for test
signal dummy_stat_reg_1 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_2 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_3 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_switch : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_1 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_2 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_3 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_led : std_logic_vector(31 downto 0);
-- I2C
signal scl_t : std_logic;
signal sda_t : std_logic;
-- Trigger logic
signal int_busy_t : std_logic;
signal trig_tag_t : std_logic_vector(31 downto 0);
signal int_trig_t : std_logic;
signal eudet_trig_t : std_logic;
signal eudet_clk_t : std_logic;
signal eudet_rst_t : std_logic;
signal eudet_busy_t : std_logic;
-- FOR TESTS
signal debug : std_logic_vector(31 downto 0);
signal clk_div_cnt : unsigned(3 downto 0);
signal clk_div : std_logic;
-- LED
signal led_cnt : unsigned(24 downto 0);
signal led_en : std_logic;
signal led_k2000 : unsigned(2 downto 0);
signal led_pps : std_logic;
signal leds : std_logic_vector(3 downto 0);
-- ILA
signal CONTROL : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal TRIG0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG0_t : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG1_t : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG2_t : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal debug_dma : std_logic_vector(31 downto 0);
signal ddr_status : std_logic_vector(31 downto 0);
signal gn4124_core_Status : std_logic_vector(31 downto 0);
signal tx_data_o : std_logic_vector(0 downto 0);
signal trig_pulse : std_logic;
signal fe_cmd_o : std_logic_vector(c_TX_CHANNELS-1 downto 0);
signal fe_clk_o : std_logic_vector(c_TX_CHANNELS-1 downto 0);
signal fe_data_i : std_logic_vector(c_RX_CHANNELS-1 downto 0);
signal rx_data : std_logic_vector(31 downto 0);
signal rx_valid : std_logic;
signal rx_busy : std_logic;
-- FMC
signal dac_ld_t : std_logic;
signal inj_sw_t : std_logic;
signal dac_din_t : std_logic;
signal dac_clk_t : std_logic;
signal dac_cs_t : std_logic;
signal trigger_t : std_logic;
signal clk_data_t : std_logic;
signal rst_0_t : std_logic;
signal clk_cnfg_t : std_logic;
signal pix_d_cnfg_t : std_logic;
signal ld_cnfg_t : std_logic;
signal clk_bx_t : std_logic;
signal rst_1_t : std_logic;
signal en_pix_sr_cnfg_t : std_logic;
signal si_cnfg_t : std_logic;
signal so_cnfg_t : std_logic;
signal hit_or_t : std_logic;
signal out_data_t : std_logic;
begin
-- Buffers
dac_ld <= dac_ld_t;
inj_sw <= inj_sw_t;
dac_din <= dac_din_t;
dac_clk <= dac_clk_t;
dac_cs <= dac_cs_t;
trigger_buf : OBUFDS port map (O => trigger_n, OB => trigger_p, I => not trigger_t); -- inv
clk_datar_buf : OBUFDS port map (O => clk_data_p, OB => clk_data_n, I => clk_data_t);
rst_0_buf : OBUFDS port map (O => rst_0_n, OB => rst_0_p, I => not rst_0_t); -- inv
clk_cnfg_buf : OBUFDS port map (O => clk_cnfg_n, OB => clk_cnfg_p, I => clk_cnfg_t); --inv
pix_d_cnfg_buf : OBUFDS port map (O => pix_d_cnfg_p, OB => pix_d_cnfg_n, I => pix_d_cnfg_t);
ld_cnfg_buf : OBUFDS port map (O => ld_cnfg_p, OB => ld_cnfg_n, I => ld_cnfg_t);
clk_bx_buf : OBUFDS port map (O => clk_bx_p, OB => clk_bx_n, I => clk_bx_t);
en_pix_sr_cnfg_buf : OBUFDS port map (O => en_pix_sr_cnfg_n, OB => en_pix_sr_cnfg_p, I => not en_pix_sr_cnfg_t); -- inv
rst_1_buf : OBUFDS port map (O => rst_1_n, OB => rst_1_p, I => not rst_1_t); --inv
si_cnfg_buf : OBUFDS port map (O => si_cnfg_p, OB => si_cnfg_n, I => si_cnfg_t);
eudet_clk_buf : OBUFDS port map (O => EXT_4_P, OB => EXT_4_N, I => not eudet_clk_t);
eudet_busy_buf : OBUFDS port map (O => EXT_2_P, OB => EXT_2_N, I => eudet_busy_t);
so_cnfg_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => so_cnfg_t, I => so_cnfg_p, IB => so_cnfg_n);
hit_or_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => hit_or_t, I => hit_or_p, IB => hit_or_n);
out_data_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => out_data_t, I => out_data_p, IB => out_data_n);
eudet_rst_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => eudet_rst_t, I => EXT_3_P, IB => EXT_3_N);
eudet_trig_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => eudet_trig_t, I => EXT_1_P, IB => EXT_1_N);
fe_data_i(0) <= not out_data_t;
------------------------------------------------------------------------------
-- Local clock from gennum LCLK
------------------------------------------------------------------------------
IBUFGDS_gn_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DIFF_SSTL18_I"
)
port map (
O => l_clk, -- Clock buffer output
I => L_CLKp, -- Diff_p clock buffer input (connect directly to top-level port)
IB => L_CLKn -- Diff_n clock buffer input (connect directly to top-level port)
);
IBUFGDS_pll_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_25"
)
port map (
O => CLK_125, -- Clock buffer output
I => clk_125m_pllref_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
cmp_fe65p2_addon: fe65p2_addon PORT MAP(
clk_i => CLK_40,
rst_n => rst_n,
serial_in => fe_cmd_o(0),
clk_rx_i => CLK_40,
clk_bx_o => clk_bx_t,
trig_o => trigger_t,
clk_cnfg_o => clk_cnfg_t,
en_pix_sr_cnfg_o => en_pix_sr_cnfg_t,
ld_cnfg_o => ld_cnfg_t,
si_cnfg_o => si_cnfg_t,
pix_d_cnfg_o => pix_d_cnfg_t,
clk_data_o => clk_data_t,
rst_0_o => rst_0_t,
rst_1_o => rst_1_t,
dac_sclk_o => dac_clk_t,
dac_sdi_o => dac_din_t,
dac_ld_o => dac_ld_t,
dac_cs_o => dac_cs_t,
inj_sw_o => inj_sw_t
);
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map
(
---------------------------------------------------------
-- Control and status
rst_n_a_i => rst_n,
status_o => gn4124_core_status,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
l2p_edb_o => L2P_EDB,
-- L2P Control
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => irq_sources,
irq_p_i => irq_to_gn4124,
irq_p_o => irq_out,
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => sys_clk,
dma_reg_adr_i => wb_adr,
dma_reg_dat_i => wb_dat_o,
dma_reg_sel_i => wb_sel,
dma_reg_stb_i => wb_stb,
dma_reg_we_i => wb_we,
dma_reg_cyc_i => wb_cyc(0),
dma_reg_dat_o => wb_dat_i(31 downto 0),
dma_reg_ack_o => wb_ack(0),
dma_reg_stall_o => wb_stall(0),
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i => sys_clk,
csr_adr_o => wbm_adr,
csr_dat_o => wbm_dat_o,
csr_sel_o => wbm_sel,
csr_stb_o => wbm_stb,
csr_we_o => wbm_we,
csr_cyc_o => wbm_cyc,
csr_dat_i => wbm_dat_i,
csr_ack_i => wbm_ack,
csr_stall_i => wbm_stall,
csr_err_i => '0',
csr_rty_i => '0',
csr_int_i => '0',
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
dma_clk_i => sys_clk,
dma_adr_o => dma_adr,
dma_dat_o => dma_dat_o,
dma_sel_o => dma_sel,
dma_stb_o => dma_stb,
dma_we_o => dma_we,
dma_cyc_o => dma_cyc,
dma_dat_i => dma_dat_i,
dma_ack_i => dma_ack,
dma_stall_i => dma_stall,
dma_err_i => '0',
dma_rty_i => '0',
dma_int_i => '0'
);
GPIO(0) <= irq_out;
GPIO(1) <= '0';
------------------------------------------------------------------------------
-- CSR wishbone address decoder
------------------------------------------------------------------------------
cmp_csr_wb_addr_decoder : wb_addr_decoder
generic map (
g_WINDOW_SIZE => c_BAR0_APERTURE,
g_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB
)
port map (
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => sys_clk,
rst_n_i => rst_n,
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i => wbm_adr,
wbm_dat_i => wbm_dat_o,
wbm_sel_i => wbm_sel,
wbm_stb_i => wbm_stb,
wbm_we_i => wbm_we,
wbm_cyc_i => wbm_cyc,
wbm_dat_o => wbm_dat_i,
wbm_ack_o => wbm_ack,
wbm_stall_o => wbm_stall,
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o => wb_adr,
wb_dat_o => wb_dat_o,
wb_sel_o => wb_sel,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_cyc_o => wb_cyc,
wb_dat_i => wb_dat_i,
wb_ack_i => wb_ack,
wb_stall_i => wb_stall
);
------------------------------------------------------------------------------
-- CSR wishbone bus slaves
------------------------------------------------------------------------------
-- cmp_dummy_stat_regs : dummy_stat_regs_wb_slave
-- port map(
-- rst_n_i => rst_n,
-- wb_clk_i => sys_clk,
-- wb_addr_i => wb_adr(1 downto 0),
-- wb_data_i => wb_dat_o,
-- wb_data_o => wb_dat_i(63 downto 32),
-- wb_cyc_i => wb_cyc(1),
-- wb_sel_i => wb_sel,
-- wb_stb_i => wb_stb,
-- wb_we_i => wb_we,
-- wb_ack_o => wb_ack(1),
-- dummy_stat_reg_1_i => dummy_stat_reg_1,
-- dummy_stat_reg_2_i => dummy_stat_reg_2,
-- dummy_stat_reg_3_i => dummy_stat_reg_3,
-- dummy_stat_reg_switch_i => dummy_stat_reg_switch
-- );
cmp_wb_tx_core : wb_tx_core port map
(
-- Sys connect
wb_clk_i => sys_clk,
rst_n_i => rst_n,
-- Wishbone slave interface
wb_adr_i => wb_adr,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(63 downto 32),
wb_cyc_i => wb_cyc(1),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(1),
wb_stall_o => wb_stall(1),
-- TX
tx_clk_i => CLK_40,
tx_data_o => fe_cmd_o,
trig_pulse_o => trig_pulse,
ext_trig_i => int_trig_t
);
cmp_wb_rx_core: wb_rx_core PORT MAP(
wb_clk_i => sys_clk,
rst_n_i => rst_n,
wb_adr_i => wb_adr,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(95 downto 64),
wb_cyc_i => wb_cyc(2),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(2),
wb_stall_o => wb_stall(2),
rx_clk_i => CLK_40,
rx_serdes_clk_i => CLK_160,
rx_data_i => fe_data_i,
rx_valid_o => rx_valid,
rx_data_o => rx_data,
trig_tag_i => trig_tag_t,
busy_o => open,
debug_o => debug
);
cmp_wb_rx_bridge : wb_rx_bridge port map (
-- Sys Connect
sys_clk_i => sys_clk,
rst_n_i => rst_n,
-- Wishbone slave interface
wb_adr_i => wb_adr,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(127 downto 96),
wb_cyc_i => wb_cyc(3),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(3),
wb_stall_o => wb_stall(3),
-- Wishbone DMA Master Interface
dma_clk_i => sys_clk,
dma_adr_o => rx_dma_adr,
dma_dat_o => rx_dma_dat_o,
dma_dat_i => rx_dma_dat_i,
dma_cyc_o => rx_dma_cyc,
dma_stb_o => rx_dma_stb,
dma_we_o => rx_dma_we,
dma_ack_i => rx_dma_ack,
dma_stall_i => rx_dma_stall,
-- Rx Interface (sync to sys_clk)
rx_data_i => rx_data,
rx_valid_i => rx_valid,
-- Status in
trig_pulse_i => trig_pulse,
-- Status out
irq_o => open,
busy_o => rx_busy
);
wb_dat_i(159 downto 136) <= (others => '0');
cmp_i2c_master : i2c_master_wb_top
port map (
wb_clk_i => sys_clk,
wb_rst_i => not rst_n,
arst_i => rst_n,
wb_adr_i => wb_adr(2 downto 0),
wb_dat_i => wb_dat_o(7 downto 0),
wb_dat_o => wb_dat_i(135 downto 128),
wb_we_i => wb_we,
wb_stb_i => wb_stb,
wb_cyc_i => wb_cyc(4),
wb_ack_o => wb_ack(4),
wb_inta_o => open,
scl => open,
sda => open
);
cmp_wb_trigger_logic: wb_trigger_logic PORT MAP(
wb_clk_i => sys_clk,
rst_n_i => rst_n,
wb_adr_i => wb_adr(31 downto 0),
wb_dat_i => wb_dat_o(31 downto 0),
wb_dat_o => wb_dat_i(191 downto 160),
wb_cyc_i => wb_cyc(5),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(5),
ext_trig_i => "00" & IO_1 & not hit_or_t,
ext_trig_o => open,
ext_busy_i => '0',
ext_busy_o => IO_0,
eudet_clk_o => eudet_clk_t,
eudet_busy_o => eudet_busy_t,
eudet_trig_i => eudet_trig_t,
eudet_rst_i => eudet_rst_t,
clk_i => CLK_40,
trig_tag => trig_tag_t
);
--wb_stall(1) <= '0' when wb_cyc(1) = '0' else not(wb_ack(1));
-- wb_stall(2) <= '0' when wb_cyc(2) = '0' else not(wb_ack(2));
-- dummy_stat_reg_1 <= X"DEADBABE";
-- dummy_stat_reg_2 <= X"BEEFFACE";
-- dummy_stat_reg_3 <= X"12345678";
-- dummy_stat_reg_switch <= X"0000000" & "000" & p2l_pll_locked;
led_red_o <= dummy_ctrl_reg_led(0);
led_green_o <= dummy_ctrl_reg_led(1);
-- TRIG0(31 downto 0) <= (others => '0');
TRIG1(31 downto 0) <= (others => '0');
TRIG2(31 downto 0) <= (others => '0');
-- TRIG0(12 downto 0) <= (others => '0');
--TRIG1(31 downto 0) <= rx_dma_dat_o;
--TRIG1(31 downto 0) <= dma_dat_i;
-- TRIG1(31 downto 0) <= gn4124_core_status;
-- TRIG2(31 downto 0) <= ddr_status;
-- TRIG0(13) <= rx_dma_cyc;
-- TRIG0(14) <= rx_dma_stb;
-- TRIG0(15) <= rx_dma_we;
-- TRIG0(16) <= rx_dma_ack;
-- TRIG0(17) <= rx_dma_stall;
-- TRIG0(18) <= dma_cyc;
-- TRIG0(19) <= dma_stb;
-- TRIG0(20) <= dma_we;
-- TRIG0(21) <= dma_ack;
-- TRIG0(22) <= dma_stall;
-- TRIG0(23) <= irq_out;
-- TRIG0(24) <= rx_busy;
-- TRIG0(31 downto 25) <= (others => '0');
-- TRIG0(0) <= rx_valid;
-- TRIG0(1) <= fe_cmd_o(0);
-- TRIG0(2) <= trig_pulse;
-- TRIG0(3) <= fe_cmd_o(0);
-- TRIG0(31 downto 4) <= (others => '0');
-- TRIG1 <= rx_data;
-- TRIG2 <= debug;
-- TRIG0(0) <= scl;
-- TRIG0(1) <= sda;
-- TRIG0(2) <= wb_stb;
-- TRIG0(3) <= wb_ack(4);
-- TRIG0(31 downto 4) <= (others => '0');
-- TRIG1 <= wb_adr;
-- TRIG2 <= wb_dat_o;
TRIG0(14 downto 0) <= trig_tag_t(14 downto 0);
TRIG0(15) <= int_trig_t;
TRIG0(16) <= eudet_trig_t;
TRIG0(17) <= eudet_clk_t;
TRIG0(18) <= eudet_busy_t;
TRIG0(19) <= trigger_t;
TRIG0(20) <= hit_or_t;
ila_i : ila
port map (
CONTROL => CONTROL,
CLK => CLK_40,
-- CLK => sys_clk,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2);
ila_icon_i : ila_icon
port map (
CONTROL0 => CONTROL);
------------------------------------------------------------------------------
-- Interrupt stuff
------------------------------------------------------------------------------
-- just forward irq pulses for test
irq_to_gn4124 <= irq_sources(1) or irq_sources(0);
------------------------------------------------------------------------------
-- FOR TEST
------------------------------------------------------------------------------
p_led_cnt : process (L_RST_N, sys_clk)
begin
if L_RST_N = '0' then
led_cnt <= (others => '1');
led_en <= '1';
elsif rising_edge(sys_clk) then
led_cnt <= led_cnt - 1;
led_en <= led_cnt(23);
end if;
end process p_led_cnt;
led_pps <= led_cnt(23) and not(led_en);
p_led_k2000 : process (sys_clk, L_RST_N)
begin
if L_RST_N = '0' then
led_k2000 <= (others => '0');
leds <= "0001";
elsif rising_edge(sys_clk) then
if led_pps = '1' then
if led_k2000(2) = '0' then
if leds /= "1000" then
leds <= leds(2 downto 0) & '0';
end if;
else
if leds /= "0001" then
leds <= '0' & leds(3 downto 1);
end if;
end if;
led_k2000 <= led_k2000 + 1;
end if;
end if;
end process p_led_k2000;
AUX_LEDS_O <= not(leds);
--AUX_LEDS_O(0) <= led_en;
--AUX_LEDS_O(1) <= not(led_en);
--AUX_LEDS_O(2) <= '1';
--AUX_LEDS_O(3) <= '0';
rst_n <= (L_RST_N and sys_clk_pll_locked and locked);
cmp_clk_gen : clk_gen
port map (
-- Clock in ports
CLK_40_IN => sys_clk_40,
CLKFB_IN => ioclk_fb,
-- Clock out ports
CLK_640 => CLK_640_buf,
CLK_160 => CLK_160_buf,
CLK_80 => CLK_80_buf,
CLK_40 => CLK_40_buf,
CLK_40_90 => CLK_40_90_buf,
CLKFB_OUT => ioclk_fb,
-- Status and control signals
RESET => not L_RST_N,
LOCKED => locked
);
BUFPLL_640 : BUFPLL
generic map (
DIVIDE => 4, -- DIVCLK divider (1-8)
ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE)
)
port map (
IOCLK => CLK_640, -- 1-bit output: Output I/O clock
LOCK => open, -- 1-bit output: Synchronized LOCK output
SERDESSTROBE => open, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
GCLK => CLK_160, -- 1-bit input: BUFG clock input
LOCKED => locked, -- 1-bit input: LOCKED input from PLL
PLLIN => clk_640_buf -- 1-bit input: Clock input from PLL
);
cmp_ioclk_160_buf : BUFG
port map (
O => CLK_160,
I => CLK_160_buf);
cmp_ioclk_80_buf : BUFG
port map (
O => CLK_80,
I => CLK_80_buf);
cmp_ioclk_40_buf : BUFG
port map (
O => CLK_40,
I => CLK_40_buf);
------------------------------------------------------------------------------
-- Clocks distribution from 20MHz TCXO
-- 40.000 MHz IO driver clock
-- 200.000 MHz fast system clock
-- 333.333 MHz DDR3 clock
------------------------------------------------------------------------------
sys_clk <= l_clk;
-- AD5662BRMZ-1 DAC output powers up to 0V. The output remains valid until a
-- write sequence arrives to the DAC.
-- To avoid spurious writes, the DAC interface outputs are fixed to safe values.
pll25dac_sync_n <= '1';
pll20dac_sync_n <= '1';
plldac_din <= '0';
plldac_sclk <= '0';
cmp_sys_clk_buf : IBUFG
port map (
I => clk20_vcxo_i,
O => sys_clk_in);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 25,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 5,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => sys_clk_fb,
CLKOUT0 => sys_clk_40_buf,
CLKOUT1 => sys_clk_200_buf,
CLKOUT2 => ddr_clk_buf,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_clk_pll_locked,
RST => '0',
CLKFBIN => sys_clk_fb,
CLKIN => sys_clk_in);
cmp_clk_125_buf : BUFG
port map (
O => sys_clk_40,
I => sys_clk_40_buf);
cmp_clk_200_buf : BUFG
port map (
O => sys_clk_200,
I => sys_clk_200_buf);
cmp_ddr_clk_buf : BUFG
port map (
O => ddr_clk,
I => ddr_clk_buf);
cmp_ddr3_ctrl: ddr3_ctrl PORT MAP(
clk_i => ddr_clk,
rst_n_i => rst_n,
status_o => ddr_status,
ddr3_dq_b => DDR3_DQ,
ddr3_a_o => DDR3_A,
ddr3_ba_o => DDR3_BA,
ddr3_ras_n_o => DDR3_RAS_N,
ddr3_cas_n_o => DDR3_CAS_N,
ddr3_we_n_o => DDR3_WE_N,
ddr3_odt_o => DDR3_ODT,
ddr3_rst_n_o => DDR3_RESET_N,
ddr3_cke_o => DDR3_CKE,
ddr3_dm_o => DDR3_LDM,
ddr3_udm_o => DDR3_UDM,
ddr3_dqs_p_b => DDR3_LDQS_P,
ddr3_dqs_n_b => DDR3_LDQS_N,
ddr3_udqs_p_b => DDR3_UDQS_P,
ddr3_udqs_n_b => DDR3_UDQS_N,
ddr3_clk_p_o => DDR3_CK_P,
ddr3_clk_n_o => DDR3_CK_N,
ddr3_rzq_b => DDR3_RZQ,
ddr3_zio_b => DDR3_ZIO,
wb0_clk_i => sys_clk,
wb0_sel_i => dma_sel,
wb0_cyc_i => dma_cyc,
wb0_stb_i => dma_stb,
wb0_we_i => dma_we,
wb0_addr_i => dma_adr,
wb0_data_i => dma_dat_o,
wb0_data_o => dma_dat_i,
wb0_ack_o => dma_ack,
wb0_stall_o => dma_stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => open,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_clk_i => sys_clk,
wb1_sel_i => "1111",
wb1_cyc_i => rx_dma_cyc,
wb1_stb_i => rx_dma_stb,
wb1_we_i => rx_dma_we,
wb1_addr_i => rx_dma_adr,
wb1_data_i => rx_dma_dat_o,
wb1_data_o => rx_dma_dat_i,
wb1_ack_o => rx_dma_ack,
wb1_stall_o => rx_dma_stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
end rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity ControlUnit is
Port ( OP : in STD_LOGIC_VECTOR (1 downto 0);
OP3 : in STD_LOGIC_VECTOR (5 downto 0);
ALUOP : out STD_LOGIC_VECTOR (5 downto 0));
end ControlUnit;
architecture Behavioral of ControlUnit is
begin
ALUOP <= OP3;
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity AddSubNDemo is
port( SW : in std_logic_vector(17 downto 0);
KEY : in std_logic;
LEDR : out std_logic_vector(13 downto 0));
end AddSubNDemo;
architecture Shell of AddSubNDemo is
begin
AddSubNDemo: entity work.MultiAddSub(Structural)
port map(op0 => SW(3 downto 0),
op1 => SW(7 downto 4),
op2 => SW(12 downto 8),
op3 => SW(17 downto 13),
sub => KEY,
cout0=>LEDR(4),
cout1=>LEDR(13),
res0=>LEDR(3 downto 0),
res1=>LEDR(12 downto 8));
end Shell; |
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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NOtMYJnj+oOCu0SQHO3zN3LAAHTPcV6k04tKgQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 24752)
`protect data_block
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`protect end_protected
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY shadow_pixel IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END shadow_pixel;
ARCHITECTURE shadow_pixel_arch OF shadow_pixel IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF shadow_pixel_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF shadow_pixel_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF shadow_pixel_arch : ARCHITECTURE IS "shadow_pixel,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF shadow_pixel_arch: ARCHITECTURE IS "shadow_pixel,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=shadow" &
"_pixel.mif,C_INIT_FILE=shadow_pixel.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=1080,C_READ_DEPTH_A=1080,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12," &
"C_WRITE_DEPTH_B=1080,C_READ_DEPTH_B=1080,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0" &
",C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.5913 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "shadow_pixel.mif",
C_INIT_FILE => "shadow_pixel.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 1080,
C_READ_DEPTH_A => 1080,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 1080,
C_READ_DEPTH_B => 1080,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.5913 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END shadow_pixel_arch;
|
entity test is
end entity test;
architecture test_arch of test is
-- constant size : integer := 10;
signal clk : integer := 0;
signal s1 : integer := 0;
begin
main: process
constant xzz : integer := 10;
variable aone : integer := 1;
begin
report "simple letprocess";
s1 <= clk + aone;
assert false report "end of simulation" severity failure;
end process;
end architecture test_arch;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7168)
`protect data_block
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`protect end_protected
|
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate FOR_LABEL;
IF_LABEL : if a = '1' generate
end generate IF_LABEL;
CASE_LABEL : case data generate
end generate CASE_LABEL;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
end generate FOR_LABEL;
IF_LABEL : if a = '1' generate
end generate IF_LABEL;
CASE_LABEL : case data generate
end generate CASE_LABEL;
-- Nested generates
LABEL_1 : for i in 0 to 7 generate
LABEL_2 : if a = '1' generate
LABEL_3 : case data generate
end generate LABEL_3;
LABEL_4 : for i in 1 to 8 generate
end generate LABEL_4;
end generate LABEL_2;
LABEL_5 : if b = '1' generate
LABEL_6 : case data generate
end generate LABEL_6;
LABEL_7 : for i in 1 to 8 generate
end generate LABEL_7;
end generate LABEL_5;
end generate LABEL_1;
end;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_171 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_171;
architecture augh of add_171 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_171 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_171;
architecture augh of add_171 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
-- megafunction wizard: %ALTGX_RECONFIG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: alt_c3gxb_reconfig
-- ============================================================
-- File Name: gxReconfig.vhd
-- Megafunction Name(s):
-- alt_c3gxb_reconfig
--
-- Simulation Library Files(s):
-- altera_mf;lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--alt_c3gxb_reconfig CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone IV GX" ENABLE_BUF_CAL="TRUE" NUMBER_OF_CHANNELS=4 NUMBER_OF_RECONFIG_PORTS=1 RECONFIG_FROMGXB_WIDTH=5 RECONFIG_TOGXB_WIDTH=4 busy reconfig_clk reconfig_fromgxb reconfig_togxb
--VERSION_BEGIN 13.0 cbx_alt_c3gxb_reconfig 2013:06:12:18:03:43:SJ cbx_alt_cal 2013:06:12:18:03:43:SJ cbx_alt_dprio 2013:06:12:18:03:43:SJ cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_lpm_shiftreg 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
--alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
--VERSION_BEGIN 13.0 cbx_alt_dprio 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_shiftreg 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 102
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY gxReconfig_alt_dprio_v5k IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
busy : OUT STD_LOGIC;
datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => '0');
dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
dpclk : IN STD_LOGIC;
dpriodisable : OUT STD_LOGIC;
dprioin : OUT STD_LOGIC;
dprioload : OUT STD_LOGIC;
dprioout : IN STD_LOGIC;
quad_address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
rden : IN STD_LOGIC := '0';
reset : IN STD_LOGIC := '0';
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
END gxReconfig_alt_dprio_v5k;
ARCHITECTURE RTL OF gxReconfig_alt_dprio_v5k IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON";
SIGNAL wire_addr_shift_reg_d : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_addr_shift_reg_asdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL addr_shift_reg : STD_LOGIC_VECTOR(31 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF addr_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
SIGNAL wire_addr_shift_reg_w_q_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL in_data_shift_reg : STD_LOGIC_VECTOR(15 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF in_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
SIGNAL wire_rd_out_data_shift_reg_d : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_rd_out_data_shift_reg_asdata : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL rd_out_data_shift_reg : STD_LOGIC_VECTOR(15 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF rd_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
SIGNAL wire_rd_out_data_shift_reg_w_q_range387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_d : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL startup_cntr : STD_LOGIC_VECTOR(2 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF startup_cntr : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
SIGNAL wire_startup_cntr_ena : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range453w458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range456w463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range456w466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range449w451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range449w465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range449w455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_lg_w_q_range456w459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_q_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_q_range453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_startup_cntr_w_q_range456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL state_mc_reg : STD_LOGIC_VECTOR(2 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF state_mc_reg : SIGNAL IS "POWER_UP_LEVEL=LOW";
SIGNAL wire_state_mc_reg_w_q_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_mc_reg_w_q_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_mc_reg_w_q_range82w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_wr_out_data_shift_reg_d : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_wr_out_data_shift_reg_asdata : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wr_out_data_shift_reg : STD_LOGIC_VECTOR(31 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF wr_out_data_shift_reg : SIGNAL IS "PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW";
SIGNAL wire_wr_out_data_shift_reg_w_q_range322w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pre_amble_cmpr_w_lg_w_lg_agb211w388w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pre_amble_cmpr_w_lg_w_lg_agb211w323w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pre_amble_cmpr_w_lg_agb211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_pre_amble_cmpr_aeb : STD_LOGIC;
SIGNAL wire_pre_amble_cmpr_agb : STD_LOGIC;
SIGNAL wire_pre_amble_cmpr_datab : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_rd_data_output_cmpr_ageb : STD_LOGIC;
SIGNAL wire_rd_data_output_cmpr_alb : STD_LOGIC;
SIGNAL wire_rd_data_output_cmpr_datab : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_state_mc_cmpr_aeb : STD_LOGIC;
SIGNAL wire_state_mc_cmpr_datab : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_state_mc_counter_cnt_en : STD_LOGIC;
SIGNAL wire_dprio_w_lg_write_state32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_mc_counter_q : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_state_mc_decode_eq : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_dprioin_mux_dataout : STD_LOGIC;
SIGNAL wire_dprio_w_lg_w_lg_w_lg_s0_to_050w51w52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_s1_to_069w70w71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_s2_to_085w86w87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_wren38w61w74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_wren38w61w62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_wr_addr_state210w213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_rd_data_output_state389w390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_wr_data_state324w325w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_s0_to_050w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_s1_to_069w70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_s2_to_085w86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_wren38w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_wren38w39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_wren38w56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_w_lg_rden445w446w447w448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_wr_addr_state210w213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_idle_state75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_idle_state57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_idle_state64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_idle_state41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_idle_state78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_rd_data_output_state389w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wr_data_state324w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s0_to_050w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s0_to_149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s1_to_069w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s1_to_168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s2_to_085w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s2_to_184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_startup_done443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_startup_idle444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wren38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wren_data60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_w_lg_rden445w446w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_rden36w37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_w_lg_rden445w446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_rden36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_rden445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_rdinc73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_rdinc55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s0_to_153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s1_to_172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_s2_to_188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wr_addr_state210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wren63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wren40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_w_lg_wren77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL busy_state : STD_LOGIC;
SIGNAL idle_state : STD_LOGIC;
SIGNAL rd_addr_done : STD_LOGIC;
SIGNAL rd_addr_state : STD_LOGIC;
SIGNAL rd_data_done : STD_LOGIC;
SIGNAL rd_data_input_state : STD_LOGIC;
SIGNAL rd_data_output_state : STD_LOGIC;
SIGNAL rd_data_state : STD_LOGIC;
SIGNAL rdinc : STD_LOGIC;
SIGNAL read_state : STD_LOGIC;
SIGNAL s0_to_0 : STD_LOGIC;
SIGNAL s0_to_1 : STD_LOGIC;
SIGNAL s1_to_0 : STD_LOGIC;
SIGNAL s1_to_1 : STD_LOGIC;
SIGNAL s2_to_0 : STD_LOGIC;
SIGNAL s2_to_1 : STD_LOGIC;
SIGNAL startup_done : STD_LOGIC;
SIGNAL startup_idle : STD_LOGIC;
SIGNAL wr_addr_done : STD_LOGIC;
SIGNAL wr_addr_state : STD_LOGIC;
SIGNAL wr_data_done : STD_LOGIC;
SIGNAL wr_data_state : STD_LOGIC;
SIGNAL write_state : STD_LOGIC;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT lpm_counter
GENERIC
(
lpm_avalue : STRING := "0";
lpm_direction : STRING := "DEFAULT";
lpm_modulus : NATURAL := 0;
lpm_port_updown : STRING := "PORT_CONNECTIVITY";
lpm_pvalue : STRING := "0";
lpm_svalue : STRING := "0";
lpm_width : NATURAL;
lpm_type : STRING := "lpm_counter"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aload : IN STD_LOGIC := '0';
aset : IN STD_LOGIC := '0';
cin : IN STD_LOGIC := '1';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
cnt_en : IN STD_LOGIC := '1';
cout : OUT STD_LOGIC;
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
eq : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
sclr : IN STD_LOGIC := '0';
sload : IN STD_LOGIC := '0';
sset : IN STD_LOGIC := '0';
updown : IN STD_LOGIC := '1'
);
END COMPONENT;
COMPONENT lpm_decode
GENERIC
(
LPM_DECODES : NATURAL;
LPM_PIPELINE : NATURAL := 0;
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_decode"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
enable : IN STD_LOGIC := '1';
eq : OUT STD_LOGIC_VECTOR(LPM_DECODES-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
wire_dprio_w_lg_w_lg_w_lg_s0_to_050w51w52w(0) <= wire_dprio_w_lg_w_lg_s0_to_050w51w(0) AND wire_state_mc_reg_w_q_range47w(0);
wire_dprio_w_lg_w_lg_w_lg_s1_to_069w70w71w(0) <= wire_dprio_w_lg_w_lg_s1_to_069w70w(0) AND wire_state_mc_reg_w_q_range66w(0);
wire_dprio_w_lg_w_lg_w_lg_s2_to_085w86w87w(0) <= wire_dprio_w_lg_w_lg_s2_to_085w86w(0) AND wire_state_mc_reg_w_q_range82w(0);
wire_dprio_w_lg_w_lg_w_lg_wren38w61w74w(0) <= wire_dprio_w_lg_w_lg_wren38w61w(0) AND wire_dprio_w_lg_rdinc73w(0);
wire_dprio_w_lg_w_lg_w_lg_wren38w61w62w(0) <= wire_dprio_w_lg_w_lg_wren38w61w(0) AND rden;
wire_dprio_w_lg_w_lg_w_lg_wr_addr_state210w213w214w(0) <= wire_dprio_w_lg_w_lg_wr_addr_state210w213w(0) AND wire_pre_amble_cmpr_agb;
wire_dprio_w_lg_w_lg_rd_data_output_state389w390w(0) <= wire_dprio_w_lg_rd_data_output_state389w(0) AND wire_pre_amble_cmpr_agb;
wire_dprio_w_lg_w_lg_wr_data_state324w325w(0) <= wire_dprio_w_lg_wr_data_state324w(0) AND wire_pre_amble_cmpr_agb;
wire_dprio_w_lg_w_lg_s0_to_050w51w(0) <= wire_dprio_w_lg_s0_to_050w(0) AND wire_dprio_w_lg_s0_to_149w(0);
wire_dprio_w_lg_w_lg_s1_to_069w70w(0) <= wire_dprio_w_lg_s1_to_069w(0) AND wire_dprio_w_lg_s1_to_168w(0);
wire_dprio_w_lg_w_lg_s2_to_085w86w(0) <= wire_dprio_w_lg_s2_to_085w(0) AND wire_dprio_w_lg_s2_to_184w(0);
wire_dprio_w_lg_w_lg_wren38w61w(0) <= wire_dprio_w_lg_wren38w(0) AND wire_dprio_w_lg_wren_data60w(0);
wire_dprio_w_lg_w_lg_wren38w39w(0) <= wire_dprio_w_lg_wren38w(0) AND wire_dprio_w_lg_w_lg_rden36w37w(0);
wire_dprio_w_lg_w_lg_wren38w56w(0) <= wire_dprio_w_lg_wren38w(0) AND wire_dprio_w_lg_rdinc55w(0);
wire_dprio_w_lg_w_lg_w_lg_w_lg_rden445w446w447w448w(0) <= wire_dprio_w_lg_w_lg_w_lg_rden445w446w447w(0) AND wire_dprio_w_lg_startup_done443w(0);
wire_dprio_w_lg_w_lg_wr_addr_state210w213w(0) <= wire_dprio_w_lg_wr_addr_state210w(0) AND wire_addr_shift_reg_w_q_range209w(0);
wire_dprio_w_lg_idle_state75w(0) <= idle_state AND wire_dprio_w_lg_w_lg_w_lg_wren38w61w74w(0);
wire_dprio_w_lg_idle_state57w(0) <= idle_state AND wire_dprio_w_lg_w_lg_wren38w56w(0);
wire_dprio_w_lg_idle_state64w(0) <= idle_state AND wire_dprio_w_lg_wren63w(0);
wire_dprio_w_lg_idle_state41w(0) <= idle_state AND wire_dprio_w_lg_wren40w(0);
wire_dprio_w_lg_idle_state78w(0) <= idle_state AND wire_dprio_w_lg_wren77w(0);
wire_dprio_w_lg_rd_data_output_state389w(0) <= rd_data_output_state AND wire_rd_out_data_shift_reg_w_q_range387w(0);
wire_dprio_w_lg_wr_data_state324w(0) <= wr_data_state AND wire_wr_out_data_shift_reg_w_q_range322w(0);
wire_dprio_w_lg_s0_to_050w(0) <= NOT s0_to_0;
wire_dprio_w_lg_s0_to_149w(0) <= NOT s0_to_1;
wire_dprio_w_lg_s1_to_069w(0) <= NOT s1_to_0;
wire_dprio_w_lg_s1_to_168w(0) <= NOT s1_to_1;
wire_dprio_w_lg_s2_to_085w(0) <= NOT s2_to_0;
wire_dprio_w_lg_s2_to_184w(0) <= NOT s2_to_1;
wire_dprio_w_lg_startup_done443w(0) <= NOT startup_done;
wire_dprio_w_lg_startup_idle444w(0) <= NOT startup_idle;
wire_dprio_w_lg_wren38w(0) <= NOT wren;
wire_dprio_w_lg_wren_data60w(0) <= NOT wren_data;
wire_dprio_w_lg_w_lg_w_lg_rden445w446w447w(0) <= wire_dprio_w_lg_w_lg_rden445w446w(0) OR wire_dprio_w_lg_startup_idle444w(0);
wire_dprio_w_lg_w_lg_rden36w37w(0) <= wire_dprio_w_lg_rden36w(0) OR wren_data;
wire_dprio_w_lg_w_lg_rden445w446w(0) <= wire_dprio_w_lg_rden445w(0) OR rdinc;
wire_dprio_w_lg_rden36w(0) <= rden OR rdinc;
wire_dprio_w_lg_rden445w(0) <= rden OR wren;
wire_dprio_w_lg_rdinc73w(0) <= rdinc OR rden;
wire_dprio_w_lg_rdinc55w(0) <= rdinc OR wren_data;
wire_dprio_w_lg_s0_to_153w(0) <= s0_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s0_to_050w51w52w(0);
wire_dprio_w_lg_s1_to_172w(0) <= s1_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s1_to_069w70w71w(0);
wire_dprio_w_lg_s2_to_188w(0) <= s2_to_1 OR wire_dprio_w_lg_w_lg_w_lg_s2_to_085w86w87w(0);
wire_dprio_w_lg_wr_addr_state210w(0) <= wr_addr_state OR rd_addr_state;
wire_dprio_w_lg_wren63w(0) <= wren OR wire_dprio_w_lg_w_lg_w_lg_wren38w61w62w(0);
wire_dprio_w_lg_wren40w(0) <= wren OR wire_dprio_w_lg_w_lg_wren38w39w(0);
wire_dprio_w_lg_wren77w(0) <= wren OR wren_data;
busy <= busy_state;
busy_state <= (write_state OR read_state);
dataout <= in_data_shift_reg;
dpriodisable <= (NOT wire_startup_cntr_w_lg_w_q_range456w466w(0));
dprioin <= wire_dprioin_mux_dataout;
dprioload <= (NOT (wire_startup_cntr_w_lg_w_q_range449w455w(0) AND (NOT startup_cntr(2))));
idle_state <= wire_state_mc_decode_eq(0);
rd_addr_done <= (rd_addr_state AND wire_state_mc_cmpr_aeb);
rd_addr_state <= (wire_state_mc_decode_eq(5) AND startup_done);
rd_data_done <= (rd_data_state AND wire_state_mc_cmpr_aeb);
rd_data_input_state <= (wire_rd_data_output_cmpr_ageb AND rd_data_state);
rd_data_output_state <= (wire_rd_data_output_cmpr_alb AND rd_data_state);
rd_data_state <= (wire_state_mc_decode_eq(7) AND startup_done);
rdinc <= '0';
read_state <= (rd_addr_state OR rd_data_state);
s0_to_0 <= ((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done));
s0_to_1 <= ((wire_dprio_w_lg_idle_state41w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
s1_to_0 <= (((wr_data_state AND wr_data_done) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state64w(0));
s1_to_1 <= ((wire_dprio_w_lg_idle_state57w(0) OR (wr_addr_state AND wr_addr_done)) OR (rd_addr_state AND rd_addr_done));
s2_to_0 <= ((((wr_addr_state AND wr_addr_done) OR (wr_data_state AND wr_data_done)) OR (rd_data_state AND rd_data_done)) OR wire_dprio_w_lg_idle_state78w(0));
s2_to_1 <= (wire_dprio_w_lg_idle_state75w(0) OR (rd_addr_state AND rd_addr_done));
startup_done <= (wire_startup_cntr_w_lg_w_q_range456w463w(0) AND startup_cntr(1));
startup_idle <= (wire_startup_cntr_w_lg_w_q_range449w451w(0) AND (NOT (startup_cntr(2) XOR startup_cntr(1))));
wr_addr_done <= (wr_addr_state AND wire_state_mc_cmpr_aeb);
wr_addr_state <= (wire_state_mc_decode_eq(1) AND startup_done);
wr_data_done <= (wr_data_state AND wire_state_mc_cmpr_aeb);
wr_data_state <= (wire_state_mc_decode_eq(3) AND startup_done);
write_state <= (wr_addr_state OR wr_data_state);
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(0) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(0) <= wire_addr_shift_reg_asdata(0);
ELSE addr_shift_reg(0) <= wire_addr_shift_reg_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(1) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(1) <= wire_addr_shift_reg_asdata(1);
ELSE addr_shift_reg(1) <= wire_addr_shift_reg_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(2) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(2) <= wire_addr_shift_reg_asdata(2);
ELSE addr_shift_reg(2) <= wire_addr_shift_reg_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(3) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(3) <= wire_addr_shift_reg_asdata(3);
ELSE addr_shift_reg(3) <= wire_addr_shift_reg_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(4) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(4) <= wire_addr_shift_reg_asdata(4);
ELSE addr_shift_reg(4) <= wire_addr_shift_reg_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(5) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(5) <= wire_addr_shift_reg_asdata(5);
ELSE addr_shift_reg(5) <= wire_addr_shift_reg_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(6) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(6) <= wire_addr_shift_reg_asdata(6);
ELSE addr_shift_reg(6) <= wire_addr_shift_reg_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(7) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(7) <= wire_addr_shift_reg_asdata(7);
ELSE addr_shift_reg(7) <= wire_addr_shift_reg_d(7);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(8) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(8) <= wire_addr_shift_reg_asdata(8);
ELSE addr_shift_reg(8) <= wire_addr_shift_reg_d(8);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(9) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(9) <= wire_addr_shift_reg_asdata(9);
ELSE addr_shift_reg(9) <= wire_addr_shift_reg_d(9);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(10) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(10) <= wire_addr_shift_reg_asdata(10);
ELSE addr_shift_reg(10) <= wire_addr_shift_reg_d(10);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(11) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(11) <= wire_addr_shift_reg_asdata(11);
ELSE addr_shift_reg(11) <= wire_addr_shift_reg_d(11);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(12) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(12) <= wire_addr_shift_reg_asdata(12);
ELSE addr_shift_reg(12) <= wire_addr_shift_reg_d(12);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(13) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(13) <= wire_addr_shift_reg_asdata(13);
ELSE addr_shift_reg(13) <= wire_addr_shift_reg_d(13);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(14) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(14) <= wire_addr_shift_reg_asdata(14);
ELSE addr_shift_reg(14) <= wire_addr_shift_reg_d(14);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(15) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(15) <= wire_addr_shift_reg_asdata(15);
ELSE addr_shift_reg(15) <= wire_addr_shift_reg_d(15);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(16) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(16) <= wire_addr_shift_reg_asdata(16);
ELSE addr_shift_reg(16) <= wire_addr_shift_reg_d(16);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(17) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(17) <= wire_addr_shift_reg_asdata(17);
ELSE addr_shift_reg(17) <= wire_addr_shift_reg_d(17);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(18) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(18) <= wire_addr_shift_reg_asdata(18);
ELSE addr_shift_reg(18) <= wire_addr_shift_reg_d(18);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(19) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(19) <= wire_addr_shift_reg_asdata(19);
ELSE addr_shift_reg(19) <= wire_addr_shift_reg_d(19);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(20) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(20) <= wire_addr_shift_reg_asdata(20);
ELSE addr_shift_reg(20) <= wire_addr_shift_reg_d(20);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(21) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(21) <= wire_addr_shift_reg_asdata(21);
ELSE addr_shift_reg(21) <= wire_addr_shift_reg_d(21);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(22) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(22) <= wire_addr_shift_reg_asdata(22);
ELSE addr_shift_reg(22) <= wire_addr_shift_reg_d(22);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(23) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(23) <= wire_addr_shift_reg_asdata(23);
ELSE addr_shift_reg(23) <= wire_addr_shift_reg_d(23);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(24) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(24) <= wire_addr_shift_reg_asdata(24);
ELSE addr_shift_reg(24) <= wire_addr_shift_reg_d(24);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(25) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(25) <= wire_addr_shift_reg_asdata(25);
ELSE addr_shift_reg(25) <= wire_addr_shift_reg_d(25);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(26) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(26) <= wire_addr_shift_reg_asdata(26);
ELSE addr_shift_reg(26) <= wire_addr_shift_reg_d(26);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(27) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(27) <= wire_addr_shift_reg_asdata(27);
ELSE addr_shift_reg(27) <= wire_addr_shift_reg_d(27);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(28) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(28) <= wire_addr_shift_reg_asdata(28);
ELSE addr_shift_reg(28) <= wire_addr_shift_reg_d(28);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(29) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(29) <= wire_addr_shift_reg_asdata(29);
ELSE addr_shift_reg(29) <= wire_addr_shift_reg_d(29);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(30) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(30) <= wire_addr_shift_reg_asdata(30);
ELSE addr_shift_reg(30) <= wire_addr_shift_reg_d(30);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN addr_shift_reg(31) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN addr_shift_reg(31) <= wire_addr_shift_reg_asdata(31);
ELSE addr_shift_reg(31) <= wire_addr_shift_reg_d(31);
END IF;
END IF;
END PROCESS;
wire_addr_shift_reg_asdata <= ( "00" & "00" & "0" & quad_address(8 DOWNTO 0) & "10" & address);
wire_addr_shift_reg_d <= ( addr_shift_reg(30 DOWNTO 0) & "0");
wire_addr_shift_reg_w_q_range209w(0) <= addr_shift_reg(31);
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN in_data_shift_reg <= (OTHERS => '0');
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (rd_data_input_state = '1') THEN in_data_shift_reg <= ( in_data_shift_reg(14 DOWNTO 0) & dprioout);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(0) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_asdata(0);
ELSE rd_out_data_shift_reg(0) <= wire_rd_out_data_shift_reg_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(1) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_asdata(1);
ELSE rd_out_data_shift_reg(1) <= wire_rd_out_data_shift_reg_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(2) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_asdata(2);
ELSE rd_out_data_shift_reg(2) <= wire_rd_out_data_shift_reg_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(3) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_asdata(3);
ELSE rd_out_data_shift_reg(3) <= wire_rd_out_data_shift_reg_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(4) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_asdata(4);
ELSE rd_out_data_shift_reg(4) <= wire_rd_out_data_shift_reg_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(5) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_asdata(5);
ELSE rd_out_data_shift_reg(5) <= wire_rd_out_data_shift_reg_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(6) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_asdata(6);
ELSE rd_out_data_shift_reg(6) <= wire_rd_out_data_shift_reg_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(7) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_asdata(7);
ELSE rd_out_data_shift_reg(7) <= wire_rd_out_data_shift_reg_d(7);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(8) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_asdata(8);
ELSE rd_out_data_shift_reg(8) <= wire_rd_out_data_shift_reg_d(8);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(9) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_asdata(9);
ELSE rd_out_data_shift_reg(9) <= wire_rd_out_data_shift_reg_d(9);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(10) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_asdata(10);
ELSE rd_out_data_shift_reg(10) <= wire_rd_out_data_shift_reg_d(10);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(11) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_asdata(11);
ELSE rd_out_data_shift_reg(11) <= wire_rd_out_data_shift_reg_d(11);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(12) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_asdata(12);
ELSE rd_out_data_shift_reg(12) <= wire_rd_out_data_shift_reg_d(12);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(13) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_asdata(13);
ELSE rd_out_data_shift_reg(13) <= wire_rd_out_data_shift_reg_d(13);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(14) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_asdata(14);
ELSE rd_out_data_shift_reg(14) <= wire_rd_out_data_shift_reg_d(14);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN rd_out_data_shift_reg(15) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_asdata(15);
ELSE rd_out_data_shift_reg(15) <= wire_rd_out_data_shift_reg_d(15);
END IF;
END IF;
END PROCESS;
wire_rd_out_data_shift_reg_asdata <= ( "00" & "1" & "1" & "0" & quad_address & "10");
wire_rd_out_data_shift_reg_d <= ( rd_out_data_shift_reg(14 DOWNTO 0) & "0");
wire_rd_out_data_shift_reg_w_q_range387w(0) <= rd_out_data_shift_reg(15);
PROCESS (dpclk)
BEGIN
IF (dpclk = '1' AND dpclk'event) THEN
IF (wire_startup_cntr_ena(0) = '1') THEN
IF (reset = '1') THEN startup_cntr(0) <= '0';
ELSE startup_cntr(0) <= wire_startup_cntr_d(0);
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (dpclk)
BEGIN
IF (dpclk = '1' AND dpclk'event) THEN
IF (wire_startup_cntr_ena(1) = '1') THEN
IF (reset = '1') THEN startup_cntr(1) <= '0';
ELSE startup_cntr(1) <= wire_startup_cntr_d(1);
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (dpclk)
BEGIN
IF (dpclk = '1' AND dpclk'event) THEN
IF (wire_startup_cntr_ena(2) = '1') THEN
IF (reset = '1') THEN startup_cntr(2) <= '0';
ELSE startup_cntr(2) <= wire_startup_cntr_d(2);
END IF;
END IF;
END IF;
END PROCESS;
wire_startup_cntr_d <= ( wire_startup_cntr_w_lg_w_q_range456w459w & wire_startup_cntr_w_lg_w_q_range449w455w & wire_startup_cntr_w_lg_w_q_range449w451w);
loop0 : FOR i IN 0 TO 2 GENERATE
wire_startup_cntr_ena(i) <= wire_dprio_w_lg_w_lg_w_lg_w_lg_rden445w446w447w448w(0);
END GENERATE loop0;
wire_startup_cntr_w_lg_w_q_range453w458w(0) <= wire_startup_cntr_w_q_range453w(0) AND wire_startup_cntr_w_q_range449w(0);
wire_startup_cntr_w_lg_w_q_range456w463w(0) <= wire_startup_cntr_w_q_range456w(0) AND wire_startup_cntr_w_lg_w_q_range449w451w(0);
wire_startup_cntr_w_lg_w_q_range456w466w(0) <= wire_startup_cntr_w_q_range456w(0) AND wire_startup_cntr_w_lg_w_q_range449w465w(0);
wire_startup_cntr_w_lg_w_q_range449w451w(0) <= NOT wire_startup_cntr_w_q_range449w(0);
wire_startup_cntr_w_lg_w_q_range449w465w(0) <= wire_startup_cntr_w_q_range449w(0) OR wire_startup_cntr_w_q_range453w(0);
wire_startup_cntr_w_lg_w_q_range449w455w(0) <= wire_startup_cntr_w_q_range449w(0) XOR wire_startup_cntr_w_q_range453w(0);
wire_startup_cntr_w_lg_w_q_range456w459w(0) <= wire_startup_cntr_w_q_range456w(0) XOR wire_startup_cntr_w_lg_w_q_range453w458w(0);
wire_startup_cntr_w_q_range449w(0) <= startup_cntr(0);
wire_startup_cntr_w_q_range453w(0) <= startup_cntr(1);
wire_startup_cntr_w_q_range456w(0) <= startup_cntr(2);
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN state_mc_reg <= (OTHERS => '0');
ELSIF (dpclk = '1' AND dpclk'event) THEN state_mc_reg <= ( wire_dprio_w_lg_s2_to_188w & wire_dprio_w_lg_s1_to_172w & wire_dprio_w_lg_s0_to_153w);
END IF;
END PROCESS;
wire_state_mc_reg_w_q_range47w(0) <= state_mc_reg(0);
wire_state_mc_reg_w_q_range66w(0) <= state_mc_reg(1);
wire_state_mc_reg_w_q_range82w(0) <= state_mc_reg(2);
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(0) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_asdata(0);
ELSE wr_out_data_shift_reg(0) <= wire_wr_out_data_shift_reg_d(0);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(1) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_asdata(1);
ELSE wr_out_data_shift_reg(1) <= wire_wr_out_data_shift_reg_d(1);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(2) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_asdata(2);
ELSE wr_out_data_shift_reg(2) <= wire_wr_out_data_shift_reg_d(2);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(3) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_asdata(3);
ELSE wr_out_data_shift_reg(3) <= wire_wr_out_data_shift_reg_d(3);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(4) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_asdata(4);
ELSE wr_out_data_shift_reg(4) <= wire_wr_out_data_shift_reg_d(4);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(5) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_asdata(5);
ELSE wr_out_data_shift_reg(5) <= wire_wr_out_data_shift_reg_d(5);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(6) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_asdata(6);
ELSE wr_out_data_shift_reg(6) <= wire_wr_out_data_shift_reg_d(6);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(7) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_asdata(7);
ELSE wr_out_data_shift_reg(7) <= wire_wr_out_data_shift_reg_d(7);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(8) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_asdata(8);
ELSE wr_out_data_shift_reg(8) <= wire_wr_out_data_shift_reg_d(8);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(9) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_asdata(9);
ELSE wr_out_data_shift_reg(9) <= wire_wr_out_data_shift_reg_d(9);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(10) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_asdata(10);
ELSE wr_out_data_shift_reg(10) <= wire_wr_out_data_shift_reg_d(10);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(11) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_asdata(11);
ELSE wr_out_data_shift_reg(11) <= wire_wr_out_data_shift_reg_d(11);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(12) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_asdata(12);
ELSE wr_out_data_shift_reg(12) <= wire_wr_out_data_shift_reg_d(12);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(13) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_asdata(13);
ELSE wr_out_data_shift_reg(13) <= wire_wr_out_data_shift_reg_d(13);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(14) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_asdata(14);
ELSE wr_out_data_shift_reg(14) <= wire_wr_out_data_shift_reg_d(14);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(15) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_asdata(15);
ELSE wr_out_data_shift_reg(15) <= wire_wr_out_data_shift_reg_d(15);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(16) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_asdata(16);
ELSE wr_out_data_shift_reg(16) <= wire_wr_out_data_shift_reg_d(16);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(17) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_asdata(17);
ELSE wr_out_data_shift_reg(17) <= wire_wr_out_data_shift_reg_d(17);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(18) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_asdata(18);
ELSE wr_out_data_shift_reg(18) <= wire_wr_out_data_shift_reg_d(18);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(19) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_asdata(19);
ELSE wr_out_data_shift_reg(19) <= wire_wr_out_data_shift_reg_d(19);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(20) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_asdata(20);
ELSE wr_out_data_shift_reg(20) <= wire_wr_out_data_shift_reg_d(20);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(21) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_asdata(21);
ELSE wr_out_data_shift_reg(21) <= wire_wr_out_data_shift_reg_d(21);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(22) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_asdata(22);
ELSE wr_out_data_shift_reg(22) <= wire_wr_out_data_shift_reg_d(22);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(23) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_asdata(23);
ELSE wr_out_data_shift_reg(23) <= wire_wr_out_data_shift_reg_d(23);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(24) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_asdata(24);
ELSE wr_out_data_shift_reg(24) <= wire_wr_out_data_shift_reg_d(24);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(25) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_asdata(25);
ELSE wr_out_data_shift_reg(25) <= wire_wr_out_data_shift_reg_d(25);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(26) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_asdata(26);
ELSE wr_out_data_shift_reg(26) <= wire_wr_out_data_shift_reg_d(26);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(27) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_asdata(27);
ELSE wr_out_data_shift_reg(27) <= wire_wr_out_data_shift_reg_d(27);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(28) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_asdata(28);
ELSE wr_out_data_shift_reg(28) <= wire_wr_out_data_shift_reg_d(28);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(29) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_asdata(29);
ELSE wr_out_data_shift_reg(29) <= wire_wr_out_data_shift_reg_d(29);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(30) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_asdata(30);
ELSE wr_out_data_shift_reg(30) <= wire_wr_out_data_shift_reg_d(30);
END IF;
END IF;
END PROCESS;
PROCESS (dpclk, reset)
BEGIN
IF (reset = '1') THEN wr_out_data_shift_reg(31) <= '0';
ELSIF (dpclk = '1' AND dpclk'event) THEN
IF (wire_pre_amble_cmpr_aeb = '1') THEN wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_asdata(31);
ELSE wr_out_data_shift_reg(31) <= wire_wr_out_data_shift_reg_d(31);
END IF;
END IF;
END PROCESS;
wire_wr_out_data_shift_reg_asdata <= ( "00" & "01" & "0" & quad_address(8 DOWNTO 0) & "10" & datain);
wire_wr_out_data_shift_reg_d <= ( wr_out_data_shift_reg(30 DOWNTO 0) & "0");
wire_wr_out_data_shift_reg_w_q_range322w(0) <= wr_out_data_shift_reg(31);
wire_pre_amble_cmpr_w_lg_w_lg_agb211w388w(0) <= wire_pre_amble_cmpr_w_lg_agb211w(0) AND rd_data_output_state;
wire_pre_amble_cmpr_w_lg_w_lg_agb211w323w(0) <= wire_pre_amble_cmpr_w_lg_agb211w(0) AND wr_data_state;
wire_pre_amble_cmpr_w_lg_agb211w(0) <= NOT wire_pre_amble_cmpr_agb;
wire_pre_amble_cmpr_datab <= "011111";
pre_amble_cmpr : lpm_compare
GENERIC MAP (
LPM_WIDTH => 6
)
PORT MAP (
aeb => wire_pre_amble_cmpr_aeb,
agb => wire_pre_amble_cmpr_agb,
dataa => wire_state_mc_counter_q,
datab => wire_pre_amble_cmpr_datab
);
wire_rd_data_output_cmpr_datab <= "110000";
rd_data_output_cmpr : lpm_compare
GENERIC MAP (
LPM_WIDTH => 6
)
PORT MAP (
ageb => wire_rd_data_output_cmpr_ageb,
alb => wire_rd_data_output_cmpr_alb,
dataa => wire_state_mc_counter_q,
datab => wire_rd_data_output_cmpr_datab
);
wire_state_mc_cmpr_datab <= (OTHERS => '1');
state_mc_cmpr : lpm_compare
GENERIC MAP (
LPM_WIDTH => 6
)
PORT MAP (
aeb => wire_state_mc_cmpr_aeb,
dataa => wire_state_mc_counter_q,
datab => wire_state_mc_cmpr_datab
);
wire_state_mc_counter_cnt_en <= wire_dprio_w_lg_write_state32w(0);
wire_dprio_w_lg_write_state32w(0) <= write_state OR read_state;
state_mc_counter : lpm_counter
GENERIC MAP (
lpm_port_updown => "PORT_UNUSED",
lpm_width => 6
)
PORT MAP (
clock => dpclk,
cnt_en => wire_state_mc_counter_cnt_en,
q => wire_state_mc_counter_q,
sclr => reset
);
state_mc_decode : lpm_decode
GENERIC MAP (
LPM_DECODES => 8,
LPM_WIDTH => 3
)
PORT MAP (
data => state_mc_reg,
eq => wire_state_mc_decode_eq
);
wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state210w213w214w(0) OR (wire_pre_amble_cmpr_w_lg_agb211w(0) AND wire_dprio_w_lg_wr_addr_state210w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state324w325w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb211w323w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state389w390w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb211w388w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
END RTL; --gxReconfig_alt_dprio_v5k
LIBRARY altera_mf;
USE altera_mf.all;
--synthesis_resources = alt_cal_c3gxb 1 lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 114
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY gxReconfig_alt_c3gxb_reconfig_qrm IS
PORT
(
busy : OUT STD_LOGIC;
reconfig_clk : IN STD_LOGIC;
reconfig_fromgxb : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END gxReconfig_alt_c3gxb_reconfig_qrm;
ARCHITECTURE RTL OF gxReconfig_alt_c3gxb_reconfig_qrm IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0";
SIGNAL wire_calibration_c3gxb_w_lg_busy8w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_calibration_c3gxb_w_lg_busy7w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_calibration_c3gxb_busy : STD_LOGIC;
SIGNAL wire_calibration_c3gxb_dprio_addr : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_calibration_c3gxb_dprio_dataout : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_calibration_c3gxb_dprio_rden : STD_LOGIC;
SIGNAL wire_calibration_c3gxb_dprio_wren : STD_LOGIC;
SIGNAL wire_calibration_c3gxb_quad_addr : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_calibration_c3gxb_reset : STD_LOGIC;
SIGNAL wire_w_lg_offset_cancellation_reset5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_calibration_c3gxb_retain_addr : STD_LOGIC;
SIGNAL wire_dprio_address : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_dprio_busy : STD_LOGIC;
SIGNAL wire_dprio_datain : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_dprio_dataout : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL wire_dprio_dpriodisable : STD_LOGIC;
SIGNAL wire_dprio_dprioin : STD_LOGIC;
SIGNAL wire_dprio_dprioload : STD_LOGIC;
SIGNAL wire_dprio_rden : STD_LOGIC;
SIGNAL wire_calibration_c3gxb_w_lg_busy9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dprio_wren : STD_LOGIC;
SIGNAL wire_calibration_c3gxb_w_lg_busy10w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL address_pres_reg : STD_LOGIC_VECTOR(11 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
ATTRIBUTE ALTERA_ATTRIBUTE OF address_pres_reg : SIGNAL IS "PRESERVE_REGISTER=ON";
SIGNAL cal_busy : STD_LOGIC;
SIGNAL cal_dprioout_wire : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL cal_testbuses : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL channel_address : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL dprio_address : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL offset_cancellation_reset : STD_LOGIC;
SIGNAL quad_address : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL reconfig_reset_all : STD_LOGIC;
COMPONENT alt_cal_c3gxb
GENERIC
(
CHANNEL_ADDRESS_WIDTH : NATURAL := 1;
NUMBER_OF_CHANNELS : NATURAL;
SIM_MODEL_MODE : STRING := "FALSE";
lpm_type : STRING := "alt_cal_c3gxb"
);
PORT
(
busy : OUT STD_LOGIC;
cal_error : OUT STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0);
clock : IN STD_LOGIC;
dprio_addr : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dprio_busy : IN STD_LOGIC;
dprio_datain : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dprio_dataout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dprio_rden : OUT STD_LOGIC;
dprio_wren : OUT STD_LOGIC;
quad_addr : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
remap_addr : IN STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
reset : IN STD_LOGIC := '0';
retain_addr : OUT STD_LOGIC;
start : IN STD_LOGIC := '0';
testbuses : IN STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT gxReconfig_alt_dprio_v5k
PORT
(
address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
busy : OUT STD_LOGIC;
datain : IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
dataout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dpclk : IN STD_LOGIC;
dpriodisable : OUT STD_LOGIC;
dprioin : OUT STD_LOGIC;
dprioload : OUT STD_LOGIC;
dprioout : IN STD_LOGIC;
quad_address : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
rden : IN STD_LOGIC := '0';
reset : IN STD_LOGIC := '0';
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
END COMPONENT;
BEGIN
busy <= cal_busy;
cal_busy <= wire_calibration_c3gxb_busy;
cal_dprioout_wire(0) <= ( reconfig_fromgxb(0));
cal_testbuses <= ( reconfig_fromgxb(4 DOWNTO 1));
channel_address <= wire_calibration_c3gxb_dprio_addr(14 DOWNTO 12);
dprio_address <= ( wire_calibration_c3gxb_dprio_addr(15) & address_pres_reg(2 DOWNTO 0) & wire_calibration_c3gxb_dprio_addr(11 DOWNTO 0));
offset_cancellation_reset <= '0';
quad_address <= wire_calibration_c3gxb_quad_addr;
reconfig_reset_all <= '0';
reconfig_togxb <= ( wire_calibration_c3gxb_busy & wire_dprio_dprioload & wire_dprio_dpriodisable & wire_dprio_dprioin);
loop1 : FOR i IN 0 TO 15 GENERATE
wire_calibration_c3gxb_w_lg_busy8w(i) <= wire_calibration_c3gxb_busy AND dprio_address(i);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 15 GENERATE
wire_calibration_c3gxb_w_lg_busy7w(i) <= wire_calibration_c3gxb_busy AND wire_calibration_c3gxb_dprio_dataout(i);
END GENERATE loop2;
wire_calibration_c3gxb_reset <= wire_w_lg_offset_cancellation_reset5w(0);
wire_w_lg_offset_cancellation_reset5w(0) <= offset_cancellation_reset OR reconfig_reset_all;
calibration_c3gxb : alt_cal_c3gxb
GENERIC MAP (
CHANNEL_ADDRESS_WIDTH => 2,
NUMBER_OF_CHANNELS => 4,
SIM_MODEL_MODE => "FALSE"
)
PORT MAP (
busy => wire_calibration_c3gxb_busy,
clock => reconfig_clk,
dprio_addr => wire_calibration_c3gxb_dprio_addr,
dprio_busy => wire_dprio_busy,
dprio_datain => wire_dprio_dataout,
dprio_dataout => wire_calibration_c3gxb_dprio_dataout,
dprio_rden => wire_calibration_c3gxb_dprio_rden,
dprio_wren => wire_calibration_c3gxb_dprio_wren,
quad_addr => wire_calibration_c3gxb_quad_addr,
remap_addr => address_pres_reg,
reset => wire_calibration_c3gxb_reset,
retain_addr => wire_calibration_c3gxb_retain_addr,
testbuses => cal_testbuses
);
wire_dprio_address <= wire_calibration_c3gxb_w_lg_busy8w;
wire_dprio_datain <= wire_calibration_c3gxb_w_lg_busy7w;
wire_dprio_rden <= wire_calibration_c3gxb_w_lg_busy9w(0);
wire_calibration_c3gxb_w_lg_busy9w(0) <= wire_calibration_c3gxb_busy AND wire_calibration_c3gxb_dprio_rden;
wire_dprio_wren <= wire_calibration_c3gxb_w_lg_busy10w(0);
wire_calibration_c3gxb_w_lg_busy10w(0) <= wire_calibration_c3gxb_busy AND wire_calibration_c3gxb_dprio_wren;
dprio : gxReconfig_alt_dprio_v5k
PORT MAP (
address => wire_dprio_address,
busy => wire_dprio_busy,
datain => wire_dprio_datain,
dataout => wire_dprio_dataout,
dpclk => reconfig_clk,
dpriodisable => wire_dprio_dpriodisable,
dprioin => wire_dprio_dprioin,
dprioload => wire_dprio_dprioload,
dprioout => cal_dprioout_wire(0),
quad_address => address_pres_reg(11 DOWNTO 3),
rden => wire_dprio_rden,
reset => reconfig_reset_all,
wren => wire_dprio_wren,
wren_data => wire_calibration_c3gxb_retain_addr
);
PROCESS (reconfig_clk, reconfig_reset_all)
BEGIN
IF (reconfig_reset_all = '1') THEN address_pres_reg <= (OTHERS => '0');
ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
END IF;
END PROCESS;
END RTL; --gxReconfig_alt_c3gxb_reconfig_qrm
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY gxReconfig IS
PORT
(
reconfig_clk : IN STD_LOGIC ;
reconfig_fromgxb : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
busy : OUT STD_LOGIC ;
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END gxReconfig;
ARCHITECTURE RTL OF gxreconfig IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
ATTRIBUTE clearbox_macroname: string;
ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "alt_c3gxb_reconfig";
ATTRIBUTE clearbox_defparam: string;
ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "cbx_blackbox_list=-lpm_mux;intended_device_family=Cyclone IV GX;number_of_channels=4;number_of_reconfig_ports=1;enable_buf_cal=true;reconfig_fromgxb_width=5;reconfig_togxb_width=4;";
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT gxReconfig_alt_c3gxb_reconfig_qrm
PORT (
busy : OUT STD_LOGIC ;
reconfig_clk : IN STD_LOGIC ;
reconfig_fromgxb : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
busy <= sub_wire0;
reconfig_togxb <= sub_wire1(3 DOWNTO 0);
gxReconfig_alt_c3gxb_reconfig_qrm_component : gxReconfig_alt_c3gxb_reconfig_qrm
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
busy => sub_wire0,
reconfig_togxb => sub_wire1
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADCE NUMERIC "0"
-- Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
-- Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: PMA NUMERIC "0"
-- Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
-- Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "1"
-- Retrieval info: CONSTANT: enable_buf_cal STRING "true"
-- Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "5"
-- Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 INPUT NODEFVAL "reconfig_fromgxb[4..0]"
-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 5 0 reconfig_fromgxb 0 0 5 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL gxReconfig.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gxReconfig.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gxReconfig.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gxReconfig.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL GXReconfig_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gxReconfig_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
|
--! @file vendor.vhd
--! @brief Functions optimized depending on part vendor
--! @author Scott Teal (Scott@Teals.org)
--! @date 2013-11-13
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fixed_pkg.all;
package vendor_pkg is
--! Delay (in clock cycles) between input and output of
--! complex_multiply_sfixed and complex_multiply_signed.
constant complex_multiply_delay : positive := 4;
component complex_multiply_sfixed is
port (
clk : in std_logic; --! System clock
rst : in std_logic; --! Reset signal
a_r : in sfixed; --! Real component of A
a_i : in sfixed; --! Imaginary component of A
b_r : in sfixed; --! Real component of B
b_i : in sfixed; --! Imaginary component of B
c_r : out sfixed; --! Real component of C
c_i : out sfixed --! Imaginary component of C
);
end component;
end vendor_pkg;
package body vendor_pkg is
end package body;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.avblabs_common_pkg.all;
entity dvb_ts is
port (
rst : in std_logic;
clk : in std_logic;
-- control
address : in std_logic_vector(8 downto 0);
byteenable : in std_logic_vector(3 downto 0);
writedata : in std_logic_vector(31 downto 0);
write : in std_logic;
readdata : out std_logic_vector(31 downto 0);
read : in std_logic;
waitrequest : out std_logic;
--
interrupt : out std_logic;
cam_bypass : in std_logic;
-- input port 1
dvb_in0_dsop : in std_logic;
dvb_in0_data : in std_logic_vector(7 downto 0);
dvb_in0_dval : in std_logic;
-- input port 2
dvb_in1_dsop : in std_logic;
dvb_in1_data : in std_logic_vector(7 downto 0);
dvb_in1_dval : in std_logic;
-- input port 3
dvb_in2_dsop : in std_logic;
dvb_in2_data : in std_logic_vector(7 downto 0);
dvb_in2_dval : in std_logic;
-- CAM port
cam_baseclk : in std_logic;
cam_mclki : out std_logic;
cam_mdi : out std_logic_vector(7 downto 0);
cam_mival : out std_logic;
cam_mistrt : out std_logic;
cam_mclko : in std_logic;
cam_mdo : in std_logic_vector(7 downto 0);
cam_moval : in std_logic;
cam_mostrt : in std_logic;
-- output port (DMA)
dvb_out_dsop : out std_logic;
dvb_out_data : out std_logic_vector(7 downto 0);
dvb_out_dval : out std_logic
);
end entity;
architecture rtl of dvb_ts is
constant REG_CLKDIV : natural := 0;
constant REG_SRCSEL : natural := 1;
signal clkdiv : std_logic_vector(3 downto 0);
signal srcsel : std_logic_vector(1 downto 0);
signal cam_dsop : std_logic;
signal cam_data : std_logic_vector(7 downto 0);
signal cam_dval : std_logic;
signal swts_dsop : std_logic;
signal swts_data : std_logic_vector(7 downto 0);
signal swts_dval : std_logic;
signal mux_dsop : std_logic;
signal mux_data : std_logic_vector(7 downto 0);
signal mux_dval : std_logic;
signal filter_dsop : std_logic;
signal filter_data : std_logic_vector(7 downto 0);
signal filter_dval : std_logic;
signal pid_tbl_read : std_logic;
signal pid_tbl_write : std_logic;
signal pid_tbl_rddata : std_logic_vector(31 downto 0);
signal pid_tbl_waitreq : std_logic;
begin
-- control
pid_tbl_write <= write and address(8);
pid_tbl_read <= read and address(8);
waitrequest <= pid_tbl_waitreq;
readdata <= pid_tbl_rddata when address(8) else
X"0000000" & clkdiv when not address(0) else
X"0000000" & "00" & srcsel;
interrupt <= '0';
process (rst, clk)
begin
if rising_edge(clk) then
if write and byteenable(0) then
if not address(0) and not address(8) then
clkdiv <= writedata(clkdiv'range);
end if;
if address(0) and not address(8) then
srcsel <= writedata(srcsel'range);
end if;
end if;
end if;
if rst then
clkdiv <= (others => '0');
srcsel <= (others => '0');
end if;
end process;
-- input demux
process (rst, clk)
begin
if rising_edge(clk) then
case srcsel is
when "00" =>
mux_dsop <= dvb_in0_dsop;
mux_data <= dvb_in0_data;
mux_dval <= dvb_in0_dval;
when "01" =>
mux_dsop <= dvb_in1_dsop;
mux_data <= dvb_in1_data;
mux_dval <= dvb_in1_dval;
when "10" =>
mux_dsop <= dvb_in2_dsop;
mux_data <= dvb_in2_data;
mux_dval <= dvb_in2_dval;
when others =>
mux_dsop <= swts_dsop;
mux_data <= swts_data;
mux_dval <= swts_dval;
end case;
end if;
if rst then
mux_dsop <= '0';
mux_data <= (others => '0');
mux_dval <= '0';
end if;
end process;
FILTER_0 : entity work.dvb_ts_filter
port map (
rst => rst,
clk => clk,
--
pid_tbl_addr => address(7 downto 0),
pid_tbl_be => byteenable,
pid_tbl_wrdata => writedata,
pid_tbl_write => pid_tbl_write,
pid_tbl_rddata => pid_tbl_rddata,
pid_tbl_read => pid_tbl_read,
pid_tbl_waitreq => pid_tbl_waitreq,
--
dvb_in_dsop => mux_dsop,
dvb_in_data => mux_data,
dvb_in_dval => mux_dval,
--
dvb_out_dsop => filter_dsop,
dvb_out_data => filter_data,
dvb_out_dval => filter_dval
);
CAM_OUT_0 : entity work.dvb_ts_shaper
port map (
rst => rst,
clk => clk,
--
bypass_test => cam_bypass,
--
clkdiv => X"2",
--
dvb_indrdy => open,
dvb_indata => filter_data,
dvb_indsop => filter_dsop,
dvb_indval => filter_dval,
-- stream domain
dvb_clk => cam_baseclk,
--
dvb_out_clk => cam_mclki,
dvb_out_data => cam_mdi,
dvb_out_dval => cam_mival,
dvb_out_dsop => cam_mistrt
);
CAM_IN_0 : entity work.dvb_ts_sync
port map (
ts_clk => cam_mclko,
ts_strt => cam_mostrt,
ts_dval => cam_moval,
ts_data => cam_mdo,
--
rst => rst,
clk => clk,
--
strt => cam_dsop,
data => cam_data,
dval => cam_dval
);
-- CAM bypass cotrol
process (rst, clk)
begin
if rising_edge(clk) then
if cam_bypass then
dvb_out_dsop <= filter_dsop;
dvb_out_data <= filter_data;
dvb_out_dval <= filter_dval;
else
dvb_out_dsop <= cam_dsop;
dvb_out_data <= cam_data;
dvb_out_dval <= cam_dval;
end if;
end if;
if rst then
dvb_out_dsop <= '0';
dvb_out_data <= (others => '0');
dvb_out_dval <= '0';
end if;
end process;
end architecture;
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo (orinaudo@gmail.com)
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram_0 is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 8);
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram_0 is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"afafafafafafafafafafafafafafafaf2308000c241400ac273c243c243c273c",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf",
INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
INIT_04 => X"8c343c00af03af270003278f0300ac008f34af0000000014008f8fafaf03af27",
INIT_05 => X"008f000c2400142480008f0010af03afaf270003278f0300ac008f3c00103000",
INIT_06 => X"008f8f0010af24af03afaf270003278f8f030000140080008f000c000080af24",
INIT_07 => X"03000004008faf24008f000c0024008f0010000c0024008f00102c008faf3000",
INIT_08 => X"0c000080af24008f0010af27000c8f008f002727afafaf03afaf270003278f8f",
INIT_09 => X"3c03af270003278f8f030000140080008fa0248faf24008f0014248024008f00",
INIT_0A => X"0000000003278f8f030000008c3c0010000c0003afaf270003278f0330008c34",
INIT_0B => X"243c000c343c243c24000c343c243c24000c243c000c243c000c243c03afaf27",
INIT_0C => X"24243c243c243caf243caf24000c24243c243c243caf243caf24000c243c000c",
INIT_0D => X"000c343c243c243c243caf243caf24000c343c243c243c243caf243caf24000c",
INIT_0E => X"243c000c000c243c000c243c000c000c243c000c243c000c000c243c000c243c",
INIT_0F => X"3c000c243c0010000c243c0014008c3c000c243c000c243c000c000c243c000c",
INIT_10 => X"af240010af24afaf03afaf270003278f8f0300000c24000c0024008c3c000c24",
INIT_11 => X"0c8f24000010008f001400008f8faf24008f0010af001400000014008f8f0010",
INIT_12 => X"24008faf240010008f8c002400008f3c000c0024008c002400008f3c000c2400",
INIT_13 => X"0c243c0010ac3c24008c3c000c243c0014248f001428008faf24008f000c24af",
INIT_14 => X"0087000c24000c8faf00008f870010a7afafafaf03afaf270003278f8f030000",
INIT_15 => X"0087a730240097af240010008f8c00008f000087000c24000c00008c00008f00",
INIT_16 => X"000c243c0010ac3c24008c3c000c243c0014248f000c8f2400000c243c001428",
INIT_17 => X"87000c24000c8faf0000008f870010a7afafafafaf03afaf270003278f8f0300",
INIT_18 => X"87a730240097af240010008f8c00008f000087000c24000c00008c00008f0000",
INIT_19 => X"008c00008f000087000c24000c8faf0000008f2400870010a7000c2400142800",
INIT_1A => X"000c240014280087a730240097af240010008f8c00008f000087000c24000c00",
INIT_1B => X"000c00008c00008f0000343c87000c24000c8faf0000000014008f870010a724",
INIT_1C => X"24000c240014280087a730240097af240010008f8c00008f0000343c87000c24",
INIT_1D => X"0c24000c00008c00008f0000343c87000c24000c8faf00000014008f870010a7",
INIT_1E => X"2400000c243c0014280087a730240097af240010008f8c00008f0000343c8700",
INIT_1F => X"af270003278f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c8f",
INIT_20 => X"0c24000c00008c002400008f3c000c24000c8faf00008f8f0010afafaf2403af",
INIT_21 => X"008f8f0010af000c24001428008faf24008faf240010008f8c002400008f3c00",
INIT_22 => X"10008f8c002400008f3c000c24000c00008c002400008f3c000c24000c8faf00",
INIT_23 => X"0010ac3c24008c3c000c243c0014248f000c243c001428008faf24008faf2400",
INIT_24 => X"8f0000008fa000278f0000008f0010afaf03afaf270003278f8f0300000c243c",
INIT_25 => X"00af008000278f0010af001428008faf24008fac008f002700008fa400270000",
INIT_26 => X"10008f8c002400008f3c000c24000c0024008c002400008f3c000c24000c8f24",
INIT_27 => X"24000c0024008c002400008f3c000c24000c8f2400af0084002700008faf2400",
INIT_28 => X"3c000c24000c8f2400af008c002700008faf240010008f8c002400008f3c000c",
INIT_29 => X"8faf24008faf240010008f8c002400008f3c000c24000c0024008c002400008f",
INIT_2A => X"8f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c243c00142800",
INIT_2B => X"000c24000c00008c3c000c24000c8faf00008f8fafaf24af2403afaf27000327",
INIT_2C => X"8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f8c3c",
INIT_2D => X"008f8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f",
INIT_2E => X"240010008f8c243c000c24000c00008c243c000c24000c8faf00008faf240010",
INIT_2F => X"008faf240010008f8c243c000c24000c00008c243c000c24000c8faf24008faf",
INIT_30 => X"0014248f000c243caf240010008f8c243c000c00008c243c000c24000c8faf24",
INIT_31 => X"28008c3caf03af27000003278f8f0300000c243c0010ac3c24008c3c000c243c",
INIT_32 => X"a324af03af270003278f0324001000ac3c24008c3cac008f0024003c8c3c0010",
INIT_33 => X"14003c8c340010240010248c3c00100083a4248fa3001000102400100094008f",
INIT_34 => X"af270003278f0324a4008fa30010ac3cac243cac3cac008c3c240018008c3c00",
INIT_35 => X"0010240010248c3c00100083a4248fa3001000102400100094008fa324afaf03",
INIT_36 => X"3cac0024003c8c248c3c001028008c3c0004008f0010008faf008c34af008c34",
INIT_37 => X"af008fafaf03af270003278f0324a4008fa30010ac243cac3cac3cac3c24008c",
INIT_38 => X"10afafafafaf03afaf270003278f038f00140080a00080af24008faf24008f00",
INIT_39 => X"8f8faf240010af240010248f0004008fa3001428008faf24008fa02400278f00",
INIT_3A => X"008f001028008faf0000000014008f8faf00000014008f8f0010af24af000000",
INIT_3B => X"1000008c008f00008f240014008fa000278f0000302430008f00100000302430",
INIT_3C => X"8f0010008c008fa02400278faf24008f0014248f0000100004008faf24008f00",
INIT_3D => X"2700248c008f0010ac008f00008f24000c8f0000008f2700100000008f248c00",
INIT_3E => X"af03af270003278f0300ac343c343cafaf03af270003278f8f0300000c8f0000",
INIT_3F => X"008fafaf03af270003278f038f0014008faf00008f24008faf302c008f0010af"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"b8afaeadacabaaa9a8a7a6a5a4a3a2a1bd000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594",
INIT_04 => X"42420200c4a0bebd00e0bdbec0004300c302c2000007624000c2c3c5c4a0bebd",
INIT_05 => X"00c20000040062024300c20000c4a0bebfbd00e0bdbec0004300c30200404200",
INIT_06 => X"00c2c30000c202c4a0bebfbd00e0bdbebfc0000040004200c20000400042c343",
INIT_07 => X"c000004100c2c24200c20000404200c200000000404200c200404200c2c24243",
INIT_08 => X"00400042c34300c20000c2c20000c440c660c2c3c6c5c4a0bebfbd00e0bdbebf",
INIT_09 => X"02a0bebd00e0bdbebfc0000040004200c24303c2c24200c2006202434200c200",
INIT_0A => X"00000000e0bdbebfc002020042020040000000a0bebfbd00e0bdbec042004242",
INIT_0B => X"44020000440245020600004402450206000044020000440200004402a0bebfbd",
INIT_0C => X"04450246024702a24202a202000004450246024702a24202a202000044020000",
INIT_0D => X"00004402450246024702a24202a20200004402450246024702a24202a2020000",
INIT_0E => X"4402000000004402000044020000000044020000440200000000440200004402",
INIT_0F => X"0200004402000000004402004000420200004402000044020000000044020000",
INIT_10 => X"c2020000c202c0c0a0bebfbd00e0bdbebfc00000000400004005004202000044",
INIT_11 => X"00c40500004000c200406200c2c3c24200c20000c000400007624000c2c30000",
INIT_12 => X"4200c2c202006200c24362420300c30200004005004262420300c30200000400",
INIT_13 => X"004402000043024300420200004402006202c300404200c2c24200c2000004c2",
INIT_14 => X"00c20000040000c4c24300c3c20000c0c0c6c5c4a0bebfbd00e0bdbebfc00000",
INIT_15 => X"00c2c2424200c2c202006200c2436200c30200c200000400004000426200c302",
INIT_16 => X"00004402000043024300420200004402006202c30000c4050000004402004042",
INIT_17 => X"c20000040000c4c2006200c2c30000c0c0c7c6c5c4a0bebfbd00e0bdbebfc000",
INIT_18 => X"c2c2424200c2c202006200c2436200c30200c200000400004000426200c30200",
INIT_19 => X"00426200c30200c20000040000c4c2006200c24300c20000c000000400404200",
INIT_1A => X"00000400404200c2c2424200c2c202006200c2436200c30200c2000004000040",
INIT_1B => X"00004000426200c302624202c30000040000c4c2000007624000c3c20000c202",
INIT_1C => X"0200000400404200c2c2424200c2c202006200c2436200c302624202c3000004",
INIT_1D => X"000400004000426200c302624202c30000040000c4c20007624000c3c20000c2",
INIT_1E => X"05000000440200404200c2c2424200c2c202006200c2436200c302624202c300",
INIT_1F => X"bfbd00e0bdbebfc00000004402000043024300420200004402006202c30000c4",
INIT_20 => X"0004000040004262420300c3020000040000c4c26200c2c30000c0c0c202a0be",
INIT_21 => X"00c2c30000c000000400404200c2c24200c2c202006200c24362420300c30200",
INIT_22 => X"6200c24362420300c302000004000040004262420300c3020000040000c4c262",
INIT_23 => X"000043024300420200004402006202c30000440200404200c2c24200c2c20200",
INIT_24 => X"c2030200c24382c4c2030200c20000c0c0a0bebfbd00e0bdbebfc00000004402",
INIT_25 => X"00c2004262c3c20000c000404200c2c24200c24300c362c30200c24382c40200",
INIT_26 => X"6200c24362420300c30200000400004005004262420300c3020000040000c405",
INIT_27 => X"0400004005004262420300c3020000040000c40500c2004262c30200c2c20200",
INIT_28 => X"020000040000c40500c2004262c30200c2c202006200c24362420300c3020000",
INIT_29 => X"c2c24200c2c202006200c24362420300c30200000400004005004262420300c3",
INIT_2A => X"bebfc00000004402000043024300420200004402006202c30000440200404200",
INIT_2B => X"0000040000400042020000040000c4c26200c2c3c0c202c202a0bebfbd00e0bd",
INIT_2C => X"434202000004000040004242020000040000c4c26200c2c3c202006200c24302",
INIT_2D => X"00c2434202000004000040004242020000040000c4c26200c2c3c202006200c2",
INIT_2E => X"02006200c2434202000004000040004242020000040000c4c20200c2c2020062",
INIT_2F => X"00c2c202006200c2434202000004000040004242020000040000c4c24200c2c2",
INIT_30 => X"006202c300004402c202006200c2434202000040004242020000040000c4c242",
INIT_31 => X"42004202c4a0bebd0000e0bdbebfc00000004402000043024300420200004402",
INIT_32 => X"c202c4a0bebd00e0bdbec0020000004302430042024300c36242030243020040",
INIT_33 => X"40620243020000020062024302004000c24303c2c000000043030040004200c2",
INIT_34 => X"bebd00e0bdbec0024000c2c00000400243030240024300630302004000420200",
INIT_35 => X"0000020062024302004000c24303c2c000000043030040004200c2c202c0c4a0",
INIT_36 => X"02438242040243024402004042004202004000c2004000c2c2004202c2004202",
INIT_37 => X"c200c2c5c4a0bebd00e0bdbec0024000c2c00000430302400240024302430042",
INIT_38 => X"00c0c7c6c5c4a0bebfbd00e0bdbec0c200400042430063c46400c3c34300c200",
INIT_39 => X"c2c3c2020000c202006202c3004100c2c000404200c2c24200c2430362c3c200",
INIT_3A => X"00c200404200c2c2000007624000c3c2c20007624000c3c20000c202c2006200",
INIT_3B => X"4062004200c26200c203004000c26283c4c3020242424200c200000202424242",
INIT_3C => X"c20040004200c2430362c3c2c24200c2006202c3000000004100c2c24200c200",
INIT_3D => X"c362034200c200004300c26200c2030000c4406200c2c30040628200c2044300",
INIT_3E => X"c4a0bebd00e0bdbec0004363034202c5c4a0bebd00e0bdbebfc0000000c44062",
INIT_3F => X"00c2c5c4a0bebd00e0bdbec0c2004000c2c26200c34200c2c2424200c20000c0"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000000000000000ff00000800ff1800350035003300b200",
INIT_01 => X"000000000000000000000000000000000000072000002000d800d800ff700000",
INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000",
INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000200000f000ff00000000e800000000800010100000000000000000f000ff",
INIT_05 => X"0000000000000000000000000000f00000ff00000000e8000000002000ff0000",
INIT_06 => X"0000000000000000f00000ff0000000000e80000ff0000000000002000000000",
INIT_07 => X"e80000ff000000ff000000002000000000000000200000000000000000000010",
INIT_08 => X"0020000000000000000000000007002800380000000000f00000ff0000000000",
INIT_09 => X"20f000ff0000000000e80000ff0000000000000000ff000000000000ff000000",
INIT_0A => X"0000000000000000e8161600002000ff000100f00000ff00000000e800000000",
INIT_0B => X"2a00000256922700000002561227000000002a0000002a0000002a00f00000ff",
INIT_0C => X"032800280028000028000000000200280028002800002800000000002a000000",
INIT_0D => X"0002230029002900290000290000000002430028002900290000290000000002",
INIT_0E => X"2a00000400002a0000002a00000500002a0000002a00000300002a0000002a00",
INIT_0F => X"0000002b00000000002b00000000330000002b0000002b00000200002a000000",
INIT_10 => X"0000000000000000f00000ff0000000000e8000000000001200030330000002b",
INIT_11 => X"010000300000000000ff10000000000000000000000000100000000000000000",
INIT_12 => X"0000000000000000000010241800000000012000300010241800000000000000",
INIT_13 => X"002b00000033000000330000002b000000000000ff0300000000000000000000",
INIT_14 => X"0000000000000000001000000000000000000000f00000ff0000000000e80000",
INIT_15 => X"000000ff00000000000000000000100000100000000000000020000010000010",
INIT_16 => X"00002b00000033000000330000002b0000000000000100003000002b0000ff00",
INIT_17 => X"000000000000000010000000000000000000000000f00000ff0000000000e800",
INIT_18 => X"0000ff0000000000000000000010000010000000000000002000001000001000",
INIT_19 => X"0000100000100000000000000000001000000001000000000000000000ff0000",
INIT_1A => X"00000000ff00000000ff00000000000000000000100000100000000000000020",
INIT_1B => X"00002000001000001010ff3f0000000000000000101000000000000000000000",
INIT_1C => X"0000000000ff00000000ff000000000000000000001000001010ff3f00000000",
INIT_1D => X"000000002000001000001010ff3f000000000000000010000000000000000000",
INIT_1E => X"003000002b0000ff00000000ff000000000000000000001000001010ff3f0000",
INIT_1F => X"00ff0000000000e80000002b00000033000000330000002b0000000000000100",
INIT_20 => X"000000002000001029180000000000000000000010000000000000000012f000",
INIT_21 => X"00000000000000000000ff000000000000000000000000000010291800000000",
INIT_22 => X"00000000102a180000000000000000200000102a180000000000000000000010",
INIT_23 => X"000033000000330000002b000000000000002c0000ff00000000000000000000",
INIT_24 => X"001c1c0000001000001e1e000000000000f00000ff0000000000e80000002b00",
INIT_25 => X"3000000010000000000000ff0000000000000000000010001000000010001000",
INIT_26 => X"00000000102c18000000000000000120003000102c1800000000000000010000",
INIT_27 => X"00000120003000102c1800000000000000010000300000001000100000000000",
INIT_28 => X"000000000001000030000000100010000000000000000000102c180000000000",
INIT_29 => X"000000000000000000000000102c18000000000000000120003000102c180000",
INIT_2A => X"0000e80000002b00000033000000330000002b000000000000002c0000ff0000",
INIT_2B => X"000000000020002c0000000000000000100000000000430012f00000ff000000",
INIT_2C => X"002c0000000000002000002c0000000000000000100000000000000000002c00",
INIT_2D => X"0000002c0000000000002000002c000000000000000010000000000000000000",
INIT_2E => X"0000000000002c0000000000002000002c000000000000000010000000000000",
INIT_2F => X"0000000000000000002c0000000000002000002c000000000000000000000000",
INIT_30 => X"0000000000002c00000000000000002c0000002000002c0000000000000000ff",
INIT_31 => X"0000330000f000ff000000000000e80000002b00000033000000330000002b00",
INIT_32 => X"000000f000ff00000000e8ff0000103300000033000000001035180033000000",
INIT_33 => X"0010400080000000000000320000000000000000000000000000000000000000",
INIT_34 => X"00ff00000000e8000000000000ff33003300003200000035007f000000330000",
INIT_35 => X"00000000000033000000000000000000000000000000000000000000000000f0",
INIT_36 => X"000010352000007f330000000000330000000000000000000000008000000080",
INIT_37 => X"0000000000f000ff00000000e8000000000000ff330000330032003300000033",
INIT_38 => X"000000000000f00000ff00000000e80000ff0000000000000000000000000000",
INIT_39 => X"000000ff0000000000000000000000000000ff00000000000000000010000000",
INIT_3A => X"0000000000000000101000000000000000100000000000000000000000100000",
INIT_3B => X"0010000000001800000000000000001800001616000000000000001616000000",
INIT_3C => X"00000000000000000010000000ff00000000ff0000000000ff000000ff000000",
INIT_3D => X"0010000000000000000000180000000006002810000000000010100000000000",
INIT_3E => X"00f000ff00000000e80000fc0000200000f000ff0000000000e8000006002810",
INIT_3F => X"00000000f000ff00000000e80000ff000000100000ff00000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"4c4844403c3834302c2824201c181410980e00ac04fd2a001800b0000000f001",
INIT_01 => X"504c4844403c3834302c2824201c18141000cc2410200060125c1058fc005450",
INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854",
INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410",
INIT_04 => X"00200000082504f80008100c2500000000100012100d1b020014101410250cf0",
INIT_05 => X"001800980d00040a000018001318251014e80008080425000000080000fa0200",
INIT_06 => X"001020001e101c2025181ce00008181014250000e90000001800982500001801",
INIT_07 => X"250000e0001010fc0010009825570014000700982530001400090a0014140f06",
INIT_08 => X"9825000010010010001810140016a025a42514a8a8a4a025989c60000820181c",
INIT_09 => X"002504f80008a0989c250000e400000010000d1010ff001000080a00ff001000",
INIT_0A => X"000000000818101425030000000000fd003c00251014e8000808042501000020",
INIT_0B => X"8000008878348c0002008878340c000100ae680000ae540000ae3c0025181ce0",
INIT_0C => X"2184009c00b40010d800140200e7070c0024003c00106000140100ae680000ae",
INIT_0D => X"00e7450174008c00a40010c800140400e72105fc0014002c00105000140300e7",
INIT_0E => X"f800008b00ae680000aee000006300ae680000aec80000fe00ae680000aea800",
INIT_0F => X"0000ae5000001300ae4800000700100000ae380000ae2800001400ae680000ae",
INIT_10 => X"1403004b10031c18252024d8000820181c250000980a0005250a25100000ae5c",
INIT_11 => X"05100a250026001400eb2a00101414020014000b140004100d1a020014100011",
INIT_12 => X"0100181c0100030010002170800018000005250a250021708000180000983a00",
INIT_13 => X"ae9c00000510000100100000ae7400000d011c00b2e800101002001000982018",
INIT_14 => X"001000983a00d4181807002810002c1014302c28252024d80008282024250000",
INIT_15 => X"001010ff0100101401000300180021002c80001000982000d425000021002c80",
INIT_16 => X"00aee400000510000100100000aed800000d01140005300a2500aec40000d120",
INIT_17 => X"1000983a00d418181218002810002d101434302c28252024d800082820242500",
INIT_18 => X"1010ff0100101401000300180021002c80001000982000d425000021002c8000",
INIT_19 => X"000021003080001000983a00d4181812180028230010002f1000980a00d00600",
INIT_1A => X"00980a00ce06001010ff0100101401000300180021003080001000982000d425",
INIT_1B => X"00d42500002100348021ffff1000983a00d4181812100d1a0200281000341001",
INIT_1C => X"0100980a00c90a001010ff010010140100030018002100348021ffff10009820",
INIT_1D => X"982000d42500002100388021ffff1000983a00d41818100d1a02002810003310",
INIT_1E => X"0a2500aef00000ca0a001010ff010010140100030018002100388021ffff1000",
INIT_1F => X"24d80008282024250000aee400000510000100100000aed800000d011400053c",
INIT_20 => X"982000d425000021ec8000100000983a00d41c1c21001018002b101418342520",
INIT_21 => X"001018002b1000980a00d20a00101001001014010003001c0021ec8000100000",
INIT_22 => X"03001c0021148000100000982000d425000021148000100000983a00d41c1c23",
INIT_23 => X"000510000100100000aed800000d011400ae140000d20a001010010010140100",
INIT_24 => X"10030000100c21101003000010001f1014259094680008282024250000aee400",
INIT_25 => X"2518000c21101000871000de0a0010100100103c001021108000101c21104000",
INIT_26 => X"030018002158800010000098200005250a250021588000100000983a0005180a",
INIT_27 => X"200005250a250021588000100000983a0005180a2518001c2110400010140100",
INIT_28 => X"0000983a0005180a2518003c2110800010140100030018002158800010000098",
INIT_29 => X"10100100101401000300180021588000100000980a0005250a25002158800010",
INIT_2A => X"9094250000aee400000510000100100000aed800000d011400ae300000760a00",
INIT_2B => X"00982000d42500800000983a00d41c1c240018141018211434252024d8000898",
INIT_2C => X"04800000982000d4250004800000983a00d41c1c2500181410010003001c8000",
INIT_2D => X"001c08800000982000d4250008800000983a00d41c1c2600181410010003001c",
INIT_2E => X"010003001c0c800000982000d425000c800000983a00d41c1c27001410010003",
INIT_2F => X"001410010003001c10800000982000d4250010800000983a00d41c1c12001410",
INIT_30 => X"000d011000ae400010010003001c14800000d4250014800000983a00d41c1cee",
INIT_31 => X"0f002400082504f8000008282024250000aee400000510000100100000aed800",
INIT_32 => X"000110250cf00008080425ff0002252400010024000000082130800024000013",
INIT_33 => X"0b24000000001f01000401f0000006000000321000002a000732000600000010",
INIT_34 => X"14e80008100c25030000100000d82c00280100f00000003000fc000600240000",
INIT_35 => X"003401000401280000060000005d1800003f00075d0006000000180001041825",
INIT_36 => X"00002170800000fc200000100f00200000160008001a00040800000004000004",
INIT_37 => X"0000101410250cf00008181425030000180000c32c01002800f0002000010020",
INIT_38 => X"0a104c48444025383cc00008100c250000f20000000000140100141001001000",
INIT_39 => X"184018ff0003180100050a48000500402f00f30f001010010010102021101000",
INIT_3A => X"0010000a0a00101c12100d1b02001c4810100d1b02001c48003e140e1c121800",
INIT_3B => X"0b2a0000004c2300140f000c001c102110140300ff57ff001000080300ff30ff",
INIT_3C => X"4c000b0000004c102d21101414ff0014000aff1800000200c0001414ff001400",
INIT_3D => X"20230f00004c000c00004c2300140f00f844252100142000122a2300140f0000",
INIT_3E => X"10250cf000080804250000180360000c082504f8000840383c250000f8442521",
INIT_3F => X"00080c082504f80008100c250000f1001010240010ff001000ff010000000d00"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"00008f8faf000c8faf0000008f00008fafaf03afaf270003278f030000008f00",
INIT_01 => X"8f0000003c8fac008fac008fac008f30008fafafafafaf03af270003278f8f03",
INIT_02 => X"0010248f001428008faf24008faf00008f0030003000008f8c008f0010afac00",
INIT_03 => X"10240014008f8f001024001000008f8c008f001024001000008f8c008f001024",
INIT_04 => X"03af270003278f0300008faf03af270003278f0300001024001028008c008f00",
INIT_05 => X"343c000c243c000c343c34af24afaf03afafaf27000003278f030000343c8faf",
INIT_06 => X"240004008c340010ac24ac343c24ae000c242424000c243cac008f343caf008c",
INIT_07 => X"008fae000c242424000c24000c0024008f000c243c0014248faf000c8faf008c",
INIT_08 => X"00000000000003278f8f8f0300000c00142c008fac008f24af000c8f0010af24",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000102040912000000",
INIT_0F => X"fffffffffffffffffffffffffffffffffffffffffffffefcf9f2e4c992000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000606060606050000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000010101010101000000",
INIT_14 => X"3d3d3d3d3d3d676620740a0a747320650a000000000000000000000000000000",
INIT_15 => X"694c7363726d69546e616f6269546f6175206467730a00696920746c6c67730a",
INIT_16 => X"4e490a007420696c54004546455000454d500a6469540030617261736d657061",
INIT_17 => X"544c4c0a0a53200a4c2000454e490a0044414f4c41454e490a0044414f4c4145",
INIT_18 => X"0000000000000000000054204945540a54204d0a542043422f440a2054494920",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000102040912000000000000000000000000000000",
INIT_1F => X"fffffffffffffffffffffefcf9f2e4c992000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000606060606050000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000010101010101000000000000000000000000000000",
INIT_24 => X"7566542055000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000072756570695300736e61756369670a0a727475526e2068616e",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"6200c2c3c20000c4c2430300c30200c2c5c4a0bebfbd00e0bdbec0620200c202",
INIT_01 => X"c240026202c34000c24000c24300c24300c2c0c7c6c5c4a0bebd00e0bdbebfc0",
INIT_02 => X"006202c300404200c2c24200c2c24300c2404202424300c24300c20000c04300",
INIT_03 => X"0002006200c2c300000200404300c24300c200000200404300c24300c2000002",
INIT_04 => X"a0bebd00e0bdbec00200c2c4a0bebd00e0bdbec000000002004042004200c200",
INIT_05 => X"4202000044020000440205c202c5c4a0b0bebfbd0000e0bdbec002624202c3c4",
INIT_06 => X"0200400042020000400243630302020000040510000044024300c34202c20042",
INIT_07 => X"00c20200000405100000040000400500c200004402006202c3c20000c4c20042",
INIT_08 => X"000000000000e0bdb0bebfc000000000404200c24300c302c20000c40000c242",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"00000000000000000000000000000000010204091224489123468d1a34000000",
INIT_0F => X"fffffffffffffffffffffffffffffefcf9f2e4c99224489123468d1a34000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000003030303030300000000000000",
INIT_12 => X"02010000000000000000000000000000010101020515100b0500fb1a150f0a05",
INIT_13 => X"0000000000000000000000000000000000000000000001504f4e4d4c4b050403",
INIT_14 => X"0a3d3d3d3d3d0a747369540a656d707247000000000000000000000000000000",
INIT_15 => X"6e69736379656e65737470696e656e63622f6920740a006f762f69697420740a",
INIT_16 => X"554d0a0073746c206f00444144410053414c0a6f6e6500306e206c206220726c",
INIT_17 => X"4949540a0a45500a4546005347460a0021534e414c52554d0a0021494e414c52",
INIT_18 => X"0000000000000000000020544f52200a20544f0a2054545420450a00454f562f",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"00000000010204091224489123468d1a34000000000000000000000000000000",
INIT_1F => X"fffffefcf9f2e4c99224489123468d1a34000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000003030303030300000000000000000000000000000000000000",
INIT_22 => X"00000000010101020515100b0500fb1a150f0a05000000000000000000000000",
INIT_23 => X"0000000000000000000001504f4e4d4c4b050403020100000000000000000000",
INIT_24 => X"20203a5441000000000000000000000000000000000000000000000000000000",
INIT_25 => X"00000000000000206d74616e65007420746e6f6e690a006b2074542074696420",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"100000000000070000101f00001000000000f00000ff00000000e8101400001f",
INIT_01 => X"001814100f000000000000000000000000000000000000f000ff0000000000e8",
INIT_02 => X"0000000000ff0000000000000000100000180010001000000000000000000000",
INIT_03 => X"0000000000000000000000001000000000000000000000100000000000000000",
INIT_04 => X"f000ff00000000e817000000f000ff00000000e8100000000000000000000000",
INIT_05 => X"00200000320000007801e100000000f0000000ff0000000000e81010ff1f0000",
INIT_06 => X"7f00000000800000007f00ff0f7f00000700007f000032000000000020000000",
INIT_07 => X"000000000700007f000000000120003000000032000000000000000800000000",
INIT_08 => X"0000000000000000000000e810000100ff0000000000007f0000080000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0101010101010101010101010101010000000000000000000000000000000000",
INIT_0B => X"0202020201010101010101010101010101010101010101010101010101010101",
INIT_0C => X"0202020202020202020202020202020202020202020202020202020202020202",
INIT_0D => X"0303030303030303030303030303030303030303030303030303030303030202",
INIT_0E => X"0000000000000000010204091224489123468d1a3468d1a2458a152b56030303",
INIT_0F => X"fffffffffffffefcf9f2e4c99224489123468d1a3468d1a2458a152b56000000",
INIT_10 => X"0000000000000000000000000000000000080808080707000000000000ffffff",
INIT_11 => X"000000000000000000000000000000000101039e9b9794918e0f0c0906030000",
INIT_12 => X"46230000000000000000000095a8c0e00d50c1a1439e5b17d4914e4f0cc98643",
INIT_13 => X"1212121212000000000000000000202429303a48619123c7a4815d3a17b08d69",
INIT_14 => X"003d3d3d3d3d0069686e650073616c6165121212121212121212121212121212",
INIT_15 => X"67730a65206d67730a69657467730a7474206e616954006e69206f63696d6954",
INIT_16 => X"4d4550003a65656674002149215300542041006e6773003020746c73656e696c",
INIT_17 => X"4f43494d0044410044410054205453000a53205443204d4550000a4c20544320",
INIT_18 => X"0000000000000000000000454e414f420045524d00454f5253524100534e4920",
INIT_19 => X"00000000000000000000000000000000000000000000000000001212ed515302",
INIT_1A => X"0101010000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0101010101010101010101010101010101010101010101010101010101010101",
INIT_1C => X"0202020202020202020202020202020202020202020202020101010101010101",
INIT_1D => X"0303030303030303030303030303030303030202020202020202020202020202",
INIT_1E => X"1224489123468d1a3468d1a2458a152b56030303030303030303030303030303",
INIT_1F => X"9224489123468d1a3468d1a2458a152b56000000000000000000000001020409",
INIT_20 => X"0000000000080808080707000000000000fffffffffffffffffffefcf9f2e4c9",
INIT_21 => X"000000000101039e9b9794918e0f0c0906030000000000000000000000000000",
INIT_22 => X"95a8c0e00d50c1a1439e5b17d4914e4f0cc98643000000000000000000000000",
INIT_23 => X"0000202429303a48619123c7a4815d3a17b08d69462300000000000000000000",
INIT_24 => X"6379204552121212121212121212121212121212121212121200000000000000",
INIT_25 => X"0000000000000000622063676e000a7469696d676e4200737770205568732072",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"250014101400dc101025400020400024242025181ce000080804252500000c00",
INIT_01 => X"20250224ff1000001c000018000014ff0010041c181410250cf0000820181c25",
INIT_02 => X"0004010400ea080000000100000421000425ff2b010700000000140013000000",
INIT_03 => X"0c04000400181c00140300042a002400001c001f0200042a0024000018002a01",
INIT_04 => X"2504f80008080425420008082504f80008100c25250002050004020000002000",
INIT_05 => X"500000ae6c000080407d0010013c38252c3034c80000080804254224feff0808",
INIT_06 => X"fc002e000000003300fc00fffffc0000f90103fc00aea8000000143000140000",
INIT_07 => X"00100000f90103fc00980a0005250a251000aecc00001a011c1c009118180000",
INIT_08 => X"0b070503000008382c30342525006000ca650010000020fc20009d1800091001",
INIT_09 => X"9d97958b89837f716d6b67656159534f4947433d3b352f2b29251f1d1713110d",
INIT_0A => X"5b514b3d393733251b19150f0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a3",
INIT_0B => X"231d0b09fdf7f3ebe7dfd3cfcdc9c1bbb7b1afa5a399918d857f7b756f67615d",
INIT_0C => X"efe7e3ddd7cfc5bdb3aba5a195938d878381776b69655f5957514b413b39332d",
INIT_0D => X"d1cbc7b9b3ada9a1978f8b7773716d5f5b5955473d3b37352b291d130501f9f5",
INIT_0E => X"010204091224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78e5dfd7",
INIT_0F => X"f9f2e4c99224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78000000",
INIT_10 => X"070001020301010000000101010102030718110a03fcf5231c150e0700fffefc",
INIT_11 => X"0000010303010100010059647285a0c80b90212807e6c5a483a5846342210007",
INIT_12 => X"8a4500030103030001000100ae6472856dc80b90212807e6c5a483a584634221",
INIT_13 => X"38373635340005010300010001005d689c8b41d117a245c8833ef9b46f5914cf",
INIT_14 => X"003d3d3d3d3d006e696773007420616c6e2b2c2d2e2f30313233343d3c3b3a39",
INIT_15 => X"20740073616f2074006f722020740069727367646e65000a73646e6170756e65",
INIT_16 => X"422052002073646161000a4c00530020545300652074000a3168656d72756d20",
INIT_17 => X"4e4150550021530021490020544948000a4550495543422052000a4546495543",
INIT_18 => X"0908070605040302010000535354504900535945005352415520440054205344",
INIT_19 => X"6159534f4947433d3b352f2b29251f1d1713110d0b07050300002246cb153520",
INIT_1A => X"0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a39d97958b89837f716d6b6765",
INIT_1B => X"cdc9c1bbb7b1afa5a399918d857f7b756f67615d5b514b3d393733251b19150f",
INIT_1C => X"95938d878381776b69655f5957514b413b39332d231d0b09fdf7f3ebe7dfd3cf",
INIT_1D => X"73716d5f5b5955473d3b37352b291d130501f9f5efe7e3ddd7cfc5bdb3aba5a1",
INIT_1E => X"3468d1a2458a152b56ac59b367cf9e3c78e5dfd7d1cbc7b9b3ada9a1978f8b77",
INIT_1F => X"3468d1a2458a152b56ac59b367cf9e3c78000000010204091224489123468d1a",
INIT_20 => X"010102030718110a03fcf5231c150e0700fffefcf9f2e4c99224489123468d1a",
INIT_21 => X"7285a0c80b90212807e6c5a483a5846342210007070001020301010000000101",
INIT_22 => X"ae6472856dc80b90212807e6c5a483a584634221000001030301010001005964",
INIT_23 => X"01005d689c8b41d117a245c8833ef9b46f5914cf8a4500030103030001000100",
INIT_24 => X"616f4953542b2c2d2e2f30313233343d3c3b3a39383736353400050103000100",
INIT_25 => X"0000000100000000656e6b2064000a656f636d206e6500216f756f41652c7465",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo (orinaudo@gmail.com)
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram_0 is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 8);
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram_0 is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"afafafafafafafafafafafafafafafaf2308000c241400ac273c243c243c273c",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf",
INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
INIT_04 => X"8c343c00af03af270003278f0300ac008f34af0000000014008f8fafaf03af27",
INIT_05 => X"008f000c2400142480008f0010af03afaf270003278f0300ac008f3c00103000",
INIT_06 => X"008f8f0010af24af03afaf270003278f8f030000140080008f000c000080af24",
INIT_07 => X"03000004008faf24008f000c0024008f0010000c0024008f00102c008faf3000",
INIT_08 => X"0c000080af24008f0010af27000c8f008f002727afafaf03afaf270003278f8f",
INIT_09 => X"3c03af270003278f8f030000140080008fa0248faf24008f0014248024008f00",
INIT_0A => X"0000000003278f8f030000008c3c0010000c0003afaf270003278f0330008c34",
INIT_0B => X"243c000c343c243c24000c343c243c24000c243c000c243c000c243c03afaf27",
INIT_0C => X"24243c243c243caf243caf24000c24243c243c243caf243caf24000c243c000c",
INIT_0D => X"000c343c243c243c243caf243caf24000c343c243c243c243caf243caf24000c",
INIT_0E => X"243c000c000c243c000c243c000c000c243c000c243c000c000c243c000c243c",
INIT_0F => X"3c000c243c0010000c243c0014008c3c000c243c000c243c000c000c243c000c",
INIT_10 => X"af240010af24afaf03afaf270003278f8f0300000c24000c0024008c3c000c24",
INIT_11 => X"0c8f24000010008f001400008f8faf24008f0010af001400000014008f8f0010",
INIT_12 => X"24008faf240010008f8c002400008f3c000c0024008c002400008f3c000c2400",
INIT_13 => X"0c243c0010ac3c24008c3c000c243c0014248f001428008faf24008f000c24af",
INIT_14 => X"0087000c24000c8faf00008f870010a7afafafaf03afaf270003278f8f030000",
INIT_15 => X"0087a730240097af240010008f8c00008f000087000c24000c00008c00008f00",
INIT_16 => X"000c243c0010ac3c24008c3c000c243c0014248f000c8f2400000c243c001428",
INIT_17 => X"87000c24000c8faf0000008f870010a7afafafafaf03afaf270003278f8f0300",
INIT_18 => X"87a730240097af240010008f8c00008f000087000c24000c00008c00008f0000",
INIT_19 => X"008c00008f000087000c24000c8faf0000008f2400870010a7000c2400142800",
INIT_1A => X"000c240014280087a730240097af240010008f8c00008f000087000c24000c00",
INIT_1B => X"000c00008c00008f0000343c87000c24000c8faf0000000014008f870010a724",
INIT_1C => X"24000c240014280087a730240097af240010008f8c00008f0000343c87000c24",
INIT_1D => X"0c24000c00008c00008f0000343c87000c24000c8faf00000014008f870010a7",
INIT_1E => X"2400000c243c0014280087a730240097af240010008f8c00008f0000343c8700",
INIT_1F => X"af270003278f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c8f",
INIT_20 => X"0c24000c00008c002400008f3c000c24000c8faf00008f8f0010afafaf2403af",
INIT_21 => X"008f8f0010af000c24001428008faf24008faf240010008f8c002400008f3c00",
INIT_22 => X"10008f8c002400008f3c000c24000c00008c002400008f3c000c24000c8faf00",
INIT_23 => X"0010ac3c24008c3c000c243c0014248f000c243c001428008faf24008faf2400",
INIT_24 => X"8f0000008fa000278f0000008f0010afaf03afaf270003278f8f0300000c243c",
INIT_25 => X"00af008000278f0010af001428008faf24008fac008f002700008fa400270000",
INIT_26 => X"10008f8c002400008f3c000c24000c0024008c002400008f3c000c24000c8f24",
INIT_27 => X"24000c0024008c002400008f3c000c24000c8f2400af0084002700008faf2400",
INIT_28 => X"3c000c24000c8f2400af008c002700008faf240010008f8c002400008f3c000c",
INIT_29 => X"8faf24008faf240010008f8c002400008f3c000c24000c0024008c002400008f",
INIT_2A => X"8f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c243c00142800",
INIT_2B => X"000c24000c00008c3c000c24000c8faf00008f8fafaf24af2403afaf27000327",
INIT_2C => X"8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f8c3c",
INIT_2D => X"008f8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f",
INIT_2E => X"240010008f8c243c000c24000c00008c243c000c24000c8faf00008faf240010",
INIT_2F => X"008faf240010008f8c243c000c24000c00008c243c000c24000c8faf24008faf",
INIT_30 => X"0014248f000c243caf240010008f8c243c000c00008c243c000c24000c8faf24",
INIT_31 => X"28008c3caf03af27000003278f8f0300000c243c0010ac3c24008c3c000c243c",
INIT_32 => X"a324af03af270003278f0324001000ac3c24008c3cac008f0024003c8c3c0010",
INIT_33 => X"14003c8c340010240010248c3c00100083a4248fa3001000102400100094008f",
INIT_34 => X"af270003278f0324a4008fa30010ac3cac243cac3cac008c3c240018008c3c00",
INIT_35 => X"0010240010248c3c00100083a4248fa3001000102400100094008fa324afaf03",
INIT_36 => X"3cac0024003c8c248c3c001028008c3c0004008f0010008faf008c34af008c34",
INIT_37 => X"af008fafaf03af270003278f0324a4008fa30010ac243cac3cac3cac3c24008c",
INIT_38 => X"10afafafafaf03afaf270003278f038f00140080a00080af24008faf24008f00",
INIT_39 => X"8f8faf240010af240010248f0004008fa3001428008faf24008fa02400278f00",
INIT_3A => X"008f001028008faf0000000014008f8faf00000014008f8f0010af24af000000",
INIT_3B => X"1000008c008f00008f240014008fa000278f0000302430008f00100000302430",
INIT_3C => X"8f0010008c008fa02400278faf24008f0014248f0000100004008faf24008f00",
INIT_3D => X"2700248c008f0010ac008f00008f24000c8f0000008f2700100000008f248c00",
INIT_3E => X"af03af270003278f0300ac343c343cafaf03af270003278f8f0300000c8f0000",
INIT_3F => X"008fafaf03af270003278f038f0014008faf00008f24008faf302c008f0010af"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"b8afaeadacabaaa9a8a7a6a5a4a3a2a1bd000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594",
INIT_04 => X"42420200c4a0bebd00e0bdbec0004300c302c2000007624000c2c3c5c4a0bebd",
INIT_05 => X"00c20000040062024300c20000c4a0bebfbd00e0bdbec0004300c30200404200",
INIT_06 => X"00c2c30000c202c4a0bebfbd00e0bdbebfc0000040004200c20000400042c343",
INIT_07 => X"c000004100c2c24200c20000404200c200000000404200c200404200c2c24243",
INIT_08 => X"00400042c34300c20000c2c20000c440c660c2c3c6c5c4a0bebfbd00e0bdbebf",
INIT_09 => X"02a0bebd00e0bdbebfc0000040004200c24303c2c24200c2006202434200c200",
INIT_0A => X"00000000e0bdbebfc002020042020040000000a0bebfbd00e0bdbec042004242",
INIT_0B => X"44020000440245020600004402450206000044020000440200004402a0bebfbd",
INIT_0C => X"04450246024702a24202a202000004450246024702a24202a202000044020000",
INIT_0D => X"00004402450246024702a24202a20200004402450246024702a24202a2020000",
INIT_0E => X"4402000000004402000044020000000044020000440200000000440200004402",
INIT_0F => X"0200004402000000004402004000420200004402000044020000000044020000",
INIT_10 => X"c2020000c202c0c0a0bebfbd00e0bdbebfc00000000400004005004202000044",
INIT_11 => X"00c40500004000c200406200c2c3c24200c20000c000400007624000c2c30000",
INIT_12 => X"4200c2c202006200c24362420300c30200004005004262420300c30200000400",
INIT_13 => X"004402000043024300420200004402006202c300404200c2c24200c2000004c2",
INIT_14 => X"00c20000040000c4c24300c3c20000c0c0c6c5c4a0bebfbd00e0bdbebfc00000",
INIT_15 => X"00c2c2424200c2c202006200c2436200c30200c200000400004000426200c302",
INIT_16 => X"00004402000043024300420200004402006202c30000c4050000004402004042",
INIT_17 => X"c20000040000c4c2006200c2c30000c0c0c7c6c5c4a0bebfbd00e0bdbebfc000",
INIT_18 => X"c2c2424200c2c202006200c2436200c30200c200000400004000426200c30200",
INIT_19 => X"00426200c30200c20000040000c4c2006200c24300c20000c000000400404200",
INIT_1A => X"00000400404200c2c2424200c2c202006200c2436200c30200c2000004000040",
INIT_1B => X"00004000426200c302624202c30000040000c4c2000007624000c3c20000c202",
INIT_1C => X"0200000400404200c2c2424200c2c202006200c2436200c302624202c3000004",
INIT_1D => X"000400004000426200c302624202c30000040000c4c20007624000c3c20000c2",
INIT_1E => X"05000000440200404200c2c2424200c2c202006200c2436200c302624202c300",
INIT_1F => X"bfbd00e0bdbebfc00000004402000043024300420200004402006202c30000c4",
INIT_20 => X"0004000040004262420300c3020000040000c4c26200c2c30000c0c0c202a0be",
INIT_21 => X"00c2c30000c000000400404200c2c24200c2c202006200c24362420300c30200",
INIT_22 => X"6200c24362420300c302000004000040004262420300c3020000040000c4c262",
INIT_23 => X"000043024300420200004402006202c30000440200404200c2c24200c2c20200",
INIT_24 => X"c2030200c24382c4c2030200c20000c0c0a0bebfbd00e0bdbebfc00000004402",
INIT_25 => X"00c2004262c3c20000c000404200c2c24200c24300c362c30200c24382c40200",
INIT_26 => X"6200c24362420300c30200000400004005004262420300c3020000040000c405",
INIT_27 => X"0400004005004262420300c3020000040000c40500c2004262c30200c2c20200",
INIT_28 => X"020000040000c40500c2004262c30200c2c202006200c24362420300c3020000",
INIT_29 => X"c2c24200c2c202006200c24362420300c30200000400004005004262420300c3",
INIT_2A => X"bebfc00000004402000043024300420200004402006202c30000440200404200",
INIT_2B => X"0000040000400042020000040000c4c26200c2c3c0c202c202a0bebfbd00e0bd",
INIT_2C => X"434202000004000040004242020000040000c4c26200c2c3c202006200c24302",
INIT_2D => X"00c2434202000004000040004242020000040000c4c26200c2c3c202006200c2",
INIT_2E => X"02006200c2434202000004000040004242020000040000c4c20200c2c2020062",
INIT_2F => X"00c2c202006200c2434202000004000040004242020000040000c4c24200c2c2",
INIT_30 => X"006202c300004402c202006200c2434202000040004242020000040000c4c242",
INIT_31 => X"42004202c4a0bebd0000e0bdbebfc00000004402000043024300420200004402",
INIT_32 => X"c202c4a0bebd00e0bdbec0020000004302430042024300c36242030243020040",
INIT_33 => X"40620243020000020062024302004000c24303c2c000000043030040004200c2",
INIT_34 => X"bebd00e0bdbec0024000c2c00000400243030240024300630302004000420200",
INIT_35 => X"0000020062024302004000c24303c2c000000043030040004200c2c202c0c4a0",
INIT_36 => X"02438242040243024402004042004202004000c2004000c2c2004202c2004202",
INIT_37 => X"c200c2c5c4a0bebd00e0bdbec0024000c2c00000430302400240024302430042",
INIT_38 => X"00c0c7c6c5c4a0bebfbd00e0bdbec0c200400042430063c46400c3c34300c200",
INIT_39 => X"c2c3c2020000c202006202c3004100c2c000404200c2c24200c2430362c3c200",
INIT_3A => X"00c200404200c2c2000007624000c3c2c20007624000c3c20000c202c2006200",
INIT_3B => X"4062004200c26200c203004000c26283c4c3020242424200c200000202424242",
INIT_3C => X"c20040004200c2430362c3c2c24200c2006202c3000000004100c2c24200c200",
INIT_3D => X"c362034200c200004300c26200c2030000c4406200c2c30040628200c2044300",
INIT_3E => X"c4a0bebd00e0bdbec0004363034202c5c4a0bebd00e0bdbebfc0000000c44062",
INIT_3F => X"00c2c5c4a0bebd00e0bdbec0c2004000c2c26200c34200c2c2424200c20000c0"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000000000000000ff00000800ff1800350035003300b200",
INIT_01 => X"000000000000000000000000000000000000072000002000d800d800ff700000",
INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000",
INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000200000f000ff00000000e800000000800010100000000000000000f000ff",
INIT_05 => X"0000000000000000000000000000f00000ff00000000e8000000002000ff0000",
INIT_06 => X"0000000000000000f00000ff0000000000e80000ff0000000000002000000000",
INIT_07 => X"e80000ff000000ff000000002000000000000000200000000000000000000010",
INIT_08 => X"0020000000000000000000000007002800380000000000f00000ff0000000000",
INIT_09 => X"20f000ff0000000000e80000ff0000000000000000ff000000000000ff000000",
INIT_0A => X"0000000000000000e8161600002000ff000100f00000ff00000000e800000000",
INIT_0B => X"2a00000256922700000002561227000000002a0000002a0000002a00f00000ff",
INIT_0C => X"032800280028000028000000000200280028002800002800000000002a000000",
INIT_0D => X"0002230029002900290000290000000002430028002900290000290000000002",
INIT_0E => X"2a00000400002a0000002a00000500002a0000002a00000300002a0000002a00",
INIT_0F => X"0000002b00000000002b00000000330000002b0000002b00000200002a000000",
INIT_10 => X"0000000000000000f00000ff0000000000e8000000000001200030330000002b",
INIT_11 => X"010000300000000000ff10000000000000000000000000100000000000000000",
INIT_12 => X"0000000000000000000010241800000000012000300010241800000000000000",
INIT_13 => X"002b00000033000000330000002b000000000000ff0300000000000000000000",
INIT_14 => X"0000000000000000001000000000000000000000f00000ff0000000000e80000",
INIT_15 => X"000000ff00000000000000000000100000100000000000000020000010000010",
INIT_16 => X"00002b00000033000000330000002b0000000000000100003000002b0000ff00",
INIT_17 => X"000000000000000010000000000000000000000000f00000ff0000000000e800",
INIT_18 => X"0000ff0000000000000000000010000010000000000000002000001000001000",
INIT_19 => X"0000100000100000000000000000001000000001000000000000000000ff0000",
INIT_1A => X"00000000ff00000000ff00000000000000000000100000100000000000000020",
INIT_1B => X"00002000001000001010ff3f0000000000000000101000000000000000000000",
INIT_1C => X"0000000000ff00000000ff000000000000000000001000001010ff3f00000000",
INIT_1D => X"000000002000001000001010ff3f000000000000000010000000000000000000",
INIT_1E => X"003000002b0000ff00000000ff000000000000000000001000001010ff3f0000",
INIT_1F => X"00ff0000000000e80000002b00000033000000330000002b0000000000000100",
INIT_20 => X"000000002000001029180000000000000000000010000000000000000012f000",
INIT_21 => X"00000000000000000000ff000000000000000000000000000010291800000000",
INIT_22 => X"00000000102a180000000000000000200000102a180000000000000000000010",
INIT_23 => X"000033000000330000002b000000000000002c0000ff00000000000000000000",
INIT_24 => X"001c1c0000001000001e1e000000000000f00000ff0000000000e80000002b00",
INIT_25 => X"3000000010000000000000ff0000000000000000000010001000000010001000",
INIT_26 => X"00000000102c18000000000000000120003000102c1800000000000000010000",
INIT_27 => X"00000120003000102c1800000000000000010000300000001000100000000000",
INIT_28 => X"000000000001000030000000100010000000000000000000102c180000000000",
INIT_29 => X"000000000000000000000000102c18000000000000000120003000102c180000",
INIT_2A => X"0000e80000002b00000033000000330000002b000000000000002c0000ff0000",
INIT_2B => X"000000000020002c0000000000000000100000000000430012f00000ff000000",
INIT_2C => X"002c0000000000002000002c0000000000000000100000000000000000002c00",
INIT_2D => X"0000002c0000000000002000002c000000000000000010000000000000000000",
INIT_2E => X"0000000000002c0000000000002000002c000000000000000010000000000000",
INIT_2F => X"0000000000000000002c0000000000002000002c000000000000000000000000",
INIT_30 => X"0000000000002c00000000000000002c0000002000002c0000000000000000ff",
INIT_31 => X"0000330000f000ff000000000000e80000002b00000033000000330000002b00",
INIT_32 => X"000000f000ff00000000e8ff0000103300000033000000001035180033000000",
INIT_33 => X"0010400080000000000000320000000000000000000000000000000000000000",
INIT_34 => X"00ff00000000e8000000000000ff33003300003200000035007f000000330000",
INIT_35 => X"00000000000033000000000000000000000000000000000000000000000000f0",
INIT_36 => X"000010352000007f330000000000330000000000000000000000008000000080",
INIT_37 => X"0000000000f000ff00000000e8000000000000ff330000330032003300000033",
INIT_38 => X"000000000000f00000ff00000000e80000ff0000000000000000000000000000",
INIT_39 => X"000000ff0000000000000000000000000000ff00000000000000000010000000",
INIT_3A => X"0000000000000000101000000000000000100000000000000000000000100000",
INIT_3B => X"0010000000001800000000000000001800001616000000000000001616000000",
INIT_3C => X"00000000000000000010000000ff00000000ff0000000000ff000000ff000000",
INIT_3D => X"0010000000000000000000180000000006002810000000000010100000000000",
INIT_3E => X"00f000ff00000000e80000fc0000200000f000ff0000000000e8000006002810",
INIT_3F => X"00000000f000ff00000000e80000ff000000100000ff00000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"4c4844403c3834302c2824201c181410980e00ac04fd2a001800b0000000f001",
INIT_01 => X"504c4844403c3834302c2824201c18141000cc2410200060125c1058fc005450",
INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854",
INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410",
INIT_04 => X"00200000082504f80008100c2500000000100012100d1b020014101410250cf0",
INIT_05 => X"001800980d00040a000018001318251014e80008080425000000080000fa0200",
INIT_06 => X"001020001e101c2025181ce00008181014250000e90000001800982500001801",
INIT_07 => X"250000e0001010fc0010009825570014000700982530001400090a0014140f06",
INIT_08 => X"9825000010010010001810140016a025a42514a8a8a4a025989c60000820181c",
INIT_09 => X"002504f80008a0989c250000e400000010000d1010ff001000080a00ff001000",
INIT_0A => X"000000000818101425030000000000fd003c00251014e8000808042501000020",
INIT_0B => X"8000008878348c0002008878340c000100ae680000ae540000ae3c0025181ce0",
INIT_0C => X"2184009c00b40010d800140200e7070c0024003c00106000140100ae680000ae",
INIT_0D => X"00e7450174008c00a40010c800140400e72105fc0014002c00105000140300e7",
INIT_0E => X"f800008b00ae680000aee000006300ae680000aec80000fe00ae680000aea800",
INIT_0F => X"0000ae5000001300ae4800000700100000ae380000ae2800001400ae680000ae",
INIT_10 => X"1403004b10031c18252024d8000820181c250000980a0005250a25100000ae5c",
INIT_11 => X"05100a250026001400eb2a00101414020014000b140004100d1a020014100011",
INIT_12 => X"0100181c0100030010002170800018000005250a250021708000180000983a00",
INIT_13 => X"ae9c00000510000100100000ae7400000d011c00b2e800101002001000982018",
INIT_14 => X"001000983a00d4181807002810002c1014302c28252024d80008282024250000",
INIT_15 => X"001010ff0100101401000300180021002c80001000982000d425000021002c80",
INIT_16 => X"00aee400000510000100100000aed800000d01140005300a2500aec40000d120",
INIT_17 => X"1000983a00d418181218002810002d101434302c28252024d800082820242500",
INIT_18 => X"1010ff0100101401000300180021002c80001000982000d425000021002c8000",
INIT_19 => X"000021003080001000983a00d4181812180028230010002f1000980a00d00600",
INIT_1A => X"00980a00ce06001010ff0100101401000300180021003080001000982000d425",
INIT_1B => X"00d42500002100348021ffff1000983a00d4181812100d1a0200281000341001",
INIT_1C => X"0100980a00c90a001010ff010010140100030018002100348021ffff10009820",
INIT_1D => X"982000d42500002100388021ffff1000983a00d41818100d1a02002810003310",
INIT_1E => X"0a2500aef00000ca0a001010ff010010140100030018002100388021ffff1000",
INIT_1F => X"24d80008282024250000aee400000510000100100000aed800000d011400053c",
INIT_20 => X"982000d425000021ec8000100000983a00d41c1c21001018002b101418342520",
INIT_21 => X"001018002b1000980a00d20a00101001001014010003001c0021ec8000100000",
INIT_22 => X"03001c0021148000100000982000d425000021148000100000983a00d41c1c23",
INIT_23 => X"000510000100100000aed800000d011400ae140000d20a001010010010140100",
INIT_24 => X"10030000100c21101003000010001f1014259094680008282024250000aee400",
INIT_25 => X"2518000c21101000871000de0a0010100100103c001021108000101c21104000",
INIT_26 => X"030018002158800010000098200005250a250021588000100000983a0005180a",
INIT_27 => X"200005250a250021588000100000983a0005180a2518001c2110400010140100",
INIT_28 => X"0000983a0005180a2518003c2110800010140100030018002158800010000098",
INIT_29 => X"10100100101401000300180021588000100000980a0005250a25002158800010",
INIT_2A => X"9094250000aee400000510000100100000aed800000d011400ae300000760a00",
INIT_2B => X"00982000d42500800000983a00d41c1c240018141018211434252024d8000898",
INIT_2C => X"04800000982000d4250004800000983a00d41c1c2500181410010003001c8000",
INIT_2D => X"001c08800000982000d4250008800000983a00d41c1c2600181410010003001c",
INIT_2E => X"010003001c0c800000982000d425000c800000983a00d41c1c27001410010003",
INIT_2F => X"001410010003001c10800000982000d4250010800000983a00d41c1c12001410",
INIT_30 => X"000d011000ae400010010003001c14800000d4250014800000983a00d41c1cee",
INIT_31 => X"0f002400082504f8000008282024250000aee400000510000100100000aed800",
INIT_32 => X"000110250cf00008080425ff0002252400010024000000082130800024000013",
INIT_33 => X"0b24000000001f01000401f0000006000000321000002a000732000600000010",
INIT_34 => X"14e80008100c25030000100000d82c00280100f00000003000fc000600240000",
INIT_35 => X"003401000401280000060000005d1800003f00075d0006000000180001041825",
INIT_36 => X"00002170800000fc200000100f00200000160008001a00040800000004000004",
INIT_37 => X"0000101410250cf00008181425030000180000c32c01002800f0002000010020",
INIT_38 => X"0a104c48444025383cc00008100c250000f20000000000140100141001001000",
INIT_39 => X"184018ff0003180100050a48000500402f00f30f001010010010102021101000",
INIT_3A => X"0010000a0a00101c12100d1b02001c4810100d1b02001c48003e140e1c121800",
INIT_3B => X"0b2a0000004c2300140f000c001c102110140300ff57ff001000080300ff30ff",
INIT_3C => X"4c000b0000004c102d21101414ff0014000aff1800000200c0001414ff001400",
INIT_3D => X"20230f00004c000c00004c2300140f00f844252100142000122a2300140f0000",
INIT_3E => X"10250cf000080804250000180360000c082504f8000840383c250000f8442521",
INIT_3F => X"00080c082504f80008100c250000f1001010240010ff001000ff010000000d00"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"00008f8faf000c8faf0000008f00008fafaf03afaf270003278f030000008f00",
INIT_01 => X"8f0000003c8fac008fac008fac008f30008fafafafafaf03af270003278f8f03",
INIT_02 => X"0010248f001428008faf24008faf00008f0030003000008f8c008f0010afac00",
INIT_03 => X"10240014008f8f001024001000008f8c008f001024001000008f8c008f001024",
INIT_04 => X"03af270003278f0300008faf03af270003278f0300001024001028008c008f00",
INIT_05 => X"343c000c243c000c343c34af24afaf03afafaf27000003278f030000343c8faf",
INIT_06 => X"240004008c340010ac24ac343c24ae000c242424000c243cac008f343caf008c",
INIT_07 => X"008fae000c242424000c24000c0024008f000c243c0014248faf000c8faf008c",
INIT_08 => X"00000000000003278f8f8f0300000c00142c008fac008f24af000c8f0010af24",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000102040912000000",
INIT_0F => X"fffffffffffffffffffffffffffffffffffffffffffffefcf9f2e4c992000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000606060606050000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000010101010101000000",
INIT_14 => X"3d3d3d3d3d3d676620740a0a747320650a000000000000000000000000000000",
INIT_15 => X"694c7363726d69546e616f6269546f6175206467730a00696920746c6c67730a",
INIT_16 => X"4e490a007420696c54004546455000454d500a6469540030617261736d657061",
INIT_17 => X"544c4c0a0a53200a4c2000454e490a0044414f4c41454e490a0044414f4c4145",
INIT_18 => X"0000000000000000000054204945540a54204d0a542043422f440a2054494920",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000102040912000000000000000000000000000000",
INIT_1F => X"fffffffffffffffffffffefcf9f2e4c992000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000606060606050000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000010101010101000000000000000000000000000000",
INIT_24 => X"7566542055000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000072756570695300736e61756369670a0a727475526e2068616e",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"6200c2c3c20000c4c2430300c30200c2c5c4a0bebfbd00e0bdbec0620200c202",
INIT_01 => X"c240026202c34000c24000c24300c24300c2c0c7c6c5c4a0bebd00e0bdbebfc0",
INIT_02 => X"006202c300404200c2c24200c2c24300c2404202424300c24300c20000c04300",
INIT_03 => X"0002006200c2c300000200404300c24300c200000200404300c24300c2000002",
INIT_04 => X"a0bebd00e0bdbec00200c2c4a0bebd00e0bdbec000000002004042004200c200",
INIT_05 => X"4202000044020000440205c202c5c4a0b0bebfbd0000e0bdbec002624202c3c4",
INIT_06 => X"0200400042020000400243630302020000040510000044024300c34202c20042",
INIT_07 => X"00c20200000405100000040000400500c200004402006202c3c20000c4c20042",
INIT_08 => X"000000000000e0bdb0bebfc000000000404200c24300c302c20000c40000c242",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"00000000000000000000000000000000010204091224489123468d1a34000000",
INIT_0F => X"fffffffffffffffffffffffffffffefcf9f2e4c99224489123468d1a34000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000003030303030300000000000000",
INIT_12 => X"02010000000000000000000000000000010101020515100b0500fb1a150f0a05",
INIT_13 => X"0000000000000000000000000000000000000000000001504f4e4d4c4b050403",
INIT_14 => X"0a3d3d3d3d3d0a747369540a656d707247000000000000000000000000000000",
INIT_15 => X"6e69736379656e65737470696e656e63622f6920740a006f762f69697420740a",
INIT_16 => X"554d0a0073746c206f00444144410053414c0a6f6e6500306e206c206220726c",
INIT_17 => X"4949540a0a45500a4546005347460a0021534e414c52554d0a0021494e414c52",
INIT_18 => X"0000000000000000000020544f52200a20544f0a2054545420450a00454f562f",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"00000000010204091224489123468d1a34000000000000000000000000000000",
INIT_1F => X"fffffefcf9f2e4c99224489123468d1a34000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000003030303030300000000000000000000000000000000000000",
INIT_22 => X"00000000010101020515100b0500fb1a150f0a05000000000000000000000000",
INIT_23 => X"0000000000000000000001504f4e4d4c4b050403020100000000000000000000",
INIT_24 => X"20203a5441000000000000000000000000000000000000000000000000000000",
INIT_25 => X"00000000000000206d74616e65007420746e6f6e690a006b2074542074696420",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"100000000000070000101f00001000000000f00000ff00000000e8101400001f",
INIT_01 => X"001814100f000000000000000000000000000000000000f000ff0000000000e8",
INIT_02 => X"0000000000ff0000000000000000100000180010001000000000000000000000",
INIT_03 => X"0000000000000000000000001000000000000000000000100000000000000000",
INIT_04 => X"f000ff00000000e817000000f000ff00000000e8100000000000000000000000",
INIT_05 => X"00200000320000007801e100000000f0000000ff0000000000e81010ff1f0000",
INIT_06 => X"7f00000000800000007f00ff0f7f00000700007f000032000000000020000000",
INIT_07 => X"000000000700007f000000000120003000000032000000000000000800000000",
INIT_08 => X"0000000000000000000000e810000100ff0000000000007f0000080000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0101010101010101010101010101010000000000000000000000000000000000",
INIT_0B => X"0202020201010101010101010101010101010101010101010101010101010101",
INIT_0C => X"0202020202020202020202020202020202020202020202020202020202020202",
INIT_0D => X"0303030303030303030303030303030303030303030303030303030303030202",
INIT_0E => X"0000000000000000010204091224489123468d1a3468d1a2458a152b56030303",
INIT_0F => X"fffffffffffffefcf9f2e4c99224489123468d1a3468d1a2458a152b56000000",
INIT_10 => X"0000000000000000000000000000000000080808080707000000000000ffffff",
INIT_11 => X"000000000000000000000000000000000101039e9b9794918e0f0c0906030000",
INIT_12 => X"46230000000000000000000095a8c0e00d50c1a1439e5b17d4914e4f0cc98643",
INIT_13 => X"1212121212000000000000000000202429303a48619123c7a4815d3a17b08d69",
INIT_14 => X"003d3d3d3d3d0069686e650073616c6165121212121212121212121212121212",
INIT_15 => X"67730a65206d67730a69657467730a7474206e616954006e69206f63696d6954",
INIT_16 => X"4d4550003a65656674002149215300542041006e6773003020746c73656e696c",
INIT_17 => X"4f43494d0044410044410054205453000a53205443204d4550000a4c20544320",
INIT_18 => X"0000000000000000000000454e414f420045524d00454f5253524100534e4920",
INIT_19 => X"00000000000000000000000000000000000000000000000000001212ed515302",
INIT_1A => X"0101010000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0101010101010101010101010101010101010101010101010101010101010101",
INIT_1C => X"0202020202020202020202020202020202020202020202020101010101010101",
INIT_1D => X"0303030303030303030303030303030303030202020202020202020202020202",
INIT_1E => X"1224489123468d1a3468d1a2458a152b56030303030303030303030303030303",
INIT_1F => X"9224489123468d1a3468d1a2458a152b56000000000000000000000001020409",
INIT_20 => X"0000000000080808080707000000000000fffffffffffffffffffefcf9f2e4c9",
INIT_21 => X"000000000101039e9b9794918e0f0c0906030000000000000000000000000000",
INIT_22 => X"95a8c0e00d50c1a1439e5b17d4914e4f0cc98643000000000000000000000000",
INIT_23 => X"0000202429303a48619123c7a4815d3a17b08d69462300000000000000000000",
INIT_24 => X"6379204552121212121212121212121212121212121212121200000000000000",
INIT_25 => X"0000000000000000622063676e000a7469696d676e4200737770205568732072",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"250014101400dc101025400020400024242025181ce000080804252500000c00",
INIT_01 => X"20250224ff1000001c000018000014ff0010041c181410250cf0000820181c25",
INIT_02 => X"0004010400ea080000000100000421000425ff2b010700000000140013000000",
INIT_03 => X"0c04000400181c00140300042a002400001c001f0200042a0024000018002a01",
INIT_04 => X"2504f80008080425420008082504f80008100c25250002050004020000002000",
INIT_05 => X"500000ae6c000080407d0010013c38252c3034c80000080804254224feff0808",
INIT_06 => X"fc002e000000003300fc00fffffc0000f90103fc00aea8000000143000140000",
INIT_07 => X"00100000f90103fc00980a0005250a251000aecc00001a011c1c009118180000",
INIT_08 => X"0b070503000008382c30342525006000ca650010000020fc20009d1800091001",
INIT_09 => X"9d97958b89837f716d6b67656159534f4947433d3b352f2b29251f1d1713110d",
INIT_0A => X"5b514b3d393733251b19150f0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a3",
INIT_0B => X"231d0b09fdf7f3ebe7dfd3cfcdc9c1bbb7b1afa5a399918d857f7b756f67615d",
INIT_0C => X"efe7e3ddd7cfc5bdb3aba5a195938d878381776b69655f5957514b413b39332d",
INIT_0D => X"d1cbc7b9b3ada9a1978f8b7773716d5f5b5955473d3b37352b291d130501f9f5",
INIT_0E => X"010204091224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78e5dfd7",
INIT_0F => X"f9f2e4c99224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78000000",
INIT_10 => X"070001020301010000000101010102030718110a03fcf5231c150e0700fffefc",
INIT_11 => X"0000010303010100010059647285a0c80b90212807e6c5a483a5846342210007",
INIT_12 => X"8a4500030103030001000100ae6472856dc80b90212807e6c5a483a584634221",
INIT_13 => X"38373635340005010300010001005d689c8b41d117a245c8833ef9b46f5914cf",
INIT_14 => X"003d3d3d3d3d006e696773007420616c6e2b2c2d2e2f30313233343d3c3b3a39",
INIT_15 => X"20740073616f2074006f722020740069727367646e65000a73646e6170756e65",
INIT_16 => X"422052002073646161000a4c00530020545300652074000a3168656d72756d20",
INIT_17 => X"4e4150550021530021490020544948000a4550495543422052000a4546495543",
INIT_18 => X"0908070605040302010000535354504900535945005352415520440054205344",
INIT_19 => X"6159534f4947433d3b352f2b29251f1d1713110d0b07050300002246cb153520",
INIT_1A => X"0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a39d97958b89837f716d6b6765",
INIT_1B => X"cdc9c1bbb7b1afa5a399918d857f7b756f67615d5b514b3d393733251b19150f",
INIT_1C => X"95938d878381776b69655f5957514b413b39332d231d0b09fdf7f3ebe7dfd3cf",
INIT_1D => X"73716d5f5b5955473d3b37352b291d130501f9f5efe7e3ddd7cfc5bdb3aba5a1",
INIT_1E => X"3468d1a2458a152b56ac59b367cf9e3c78e5dfd7d1cbc7b9b3ada9a1978f8b77",
INIT_1F => X"3468d1a2458a152b56ac59b367cf9e3c78000000010204091224489123468d1a",
INIT_20 => X"010102030718110a03fcf5231c150e0700fffefcf9f2e4c99224489123468d1a",
INIT_21 => X"7285a0c80b90212807e6c5a483a5846342210007070001020301010000000101",
INIT_22 => X"ae6472856dc80b90212807e6c5a483a584634221000001030301010001005964",
INIT_23 => X"01005d689c8b41d117a245c8833ef9b46f5914cf8a4500030103030001000100",
INIT_24 => X"616f4953542b2c2d2e2f30313233343d3c3b3a39383736353400050103000100",
INIT_25 => X"0000000100000000656e6b2064000a656f636d206e6500216f756f41652c7465",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo (orinaudo@gmail.com)
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram_0 is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 8);
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram_0 is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"afafafafafafafafafafafafafafafaf2308000c241400ac273c243c243c273c",
INIT_01 => X"8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f8f230c008c8c3caf00af00af2340afaf",
INIT_02 => X"acacacac0003373cac038cac8cac8cac8c243c40034040033423038f038f8f8f",
INIT_03 => X"000300ac0300000034038c8c8c8c8c8c8c8c8c8c8c8c3403acacacacacacacac",
INIT_04 => X"8c343c00af03af270003278f0300ac008f34af0000000014008f8fafaf03af27",
INIT_05 => X"008f000c2400142480008f0010af03afaf270003278f0300ac008f3c00103000",
INIT_06 => X"008f8f0010af24af03afaf270003278f8f030000140080008f000c000080af24",
INIT_07 => X"03000004008faf24008f000c0024008f0010000c0024008f00102c008faf3000",
INIT_08 => X"0c000080af24008f0010af27000c8f008f002727afafaf03afaf270003278f8f",
INIT_09 => X"3c03af270003278f8f030000140080008fa0248faf24008f0014248024008f00",
INIT_0A => X"0000000003278f8f030000008c3c0010000c0003afaf270003278f0330008c34",
INIT_0B => X"243c000c343c243c24000c343c243c24000c243c000c243c000c243c03afaf27",
INIT_0C => X"24243c243c243caf243caf24000c24243c243c243caf243caf24000c243c000c",
INIT_0D => X"000c343c243c243c243caf243caf24000c343c243c243c243caf243caf24000c",
INIT_0E => X"243c000c000c243c000c243c000c000c243c000c243c000c000c243c000c243c",
INIT_0F => X"3c000c243c0010000c243c0014008c3c000c243c000c243c000c000c243c000c",
INIT_10 => X"af240010af24afaf03afaf270003278f8f0300000c24000c0024008c3c000c24",
INIT_11 => X"0c8f24000010008f001400008f8faf24008f0010af001400000014008f8f0010",
INIT_12 => X"24008faf240010008f8c002400008f3c000c0024008c002400008f3c000c2400",
INIT_13 => X"0c243c0010ac3c24008c3c000c243c0014248f001428008faf24008f000c24af",
INIT_14 => X"0087000c24000c8faf00008f870010a7afafafaf03afaf270003278f8f030000",
INIT_15 => X"0087a730240097af240010008f8c00008f000087000c24000c00008c00008f00",
INIT_16 => X"000c243c0010ac3c24008c3c000c243c0014248f000c8f2400000c243c001428",
INIT_17 => X"87000c24000c8faf0000008f870010a7afafafafaf03afaf270003278f8f0300",
INIT_18 => X"87a730240097af240010008f8c00008f000087000c24000c00008c00008f0000",
INIT_19 => X"008c00008f000087000c24000c8faf0000008f2400870010a7000c2400142800",
INIT_1A => X"000c240014280087a730240097af240010008f8c00008f000087000c24000c00",
INIT_1B => X"000c00008c00008f0000343c87000c24000c8faf0000000014008f870010a724",
INIT_1C => X"24000c240014280087a730240097af240010008f8c00008f0000343c87000c24",
INIT_1D => X"0c24000c00008c00008f0000343c87000c24000c8faf00000014008f870010a7",
INIT_1E => X"2400000c243c0014280087a730240097af240010008f8c00008f0000343c8700",
INIT_1F => X"af270003278f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c8f",
INIT_20 => X"0c24000c00008c002400008f3c000c24000c8faf00008f8f0010afafaf2403af",
INIT_21 => X"008f8f0010af000c24001428008faf24008faf240010008f8c002400008f3c00",
INIT_22 => X"10008f8c002400008f3c000c24000c00008c002400008f3c000c24000c8faf00",
INIT_23 => X"0010ac3c24008c3c000c243c0014248f000c243c001428008faf24008faf2400",
INIT_24 => X"8f0000008fa000278f0000008f0010afaf03afaf270003278f8f0300000c243c",
INIT_25 => X"00af008000278f0010af001428008faf24008fac008f002700008fa400270000",
INIT_26 => X"10008f8c002400008f3c000c24000c0024008c002400008f3c000c24000c8f24",
INIT_27 => X"24000c0024008c002400008f3c000c24000c8f2400af0084002700008faf2400",
INIT_28 => X"3c000c24000c8f2400af008c002700008faf240010008f8c002400008f3c000c",
INIT_29 => X"8faf24008faf240010008f8c002400008f3c000c24000c0024008c002400008f",
INIT_2A => X"8f8f0300000c243c0010ac3c24008c3c000c243c0014248f000c243c00142800",
INIT_2B => X"000c24000c00008c3c000c24000c8faf00008f8fafaf24af2403afaf27000327",
INIT_2C => X"8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f8c3c",
INIT_2D => X"008f8c243c000c24000c00008c243c000c24000c8faf00008f8faf240010008f",
INIT_2E => X"240010008f8c243c000c24000c00008c243c000c24000c8faf00008faf240010",
INIT_2F => X"008faf240010008f8c243c000c24000c00008c243c000c24000c8faf24008faf",
INIT_30 => X"0014248f000c243caf240010008f8c243c000c00008c243c000c24000c8faf24",
INIT_31 => X"28008c3caf03af27000003278f8f0300000c243c0010ac3c24008c3c000c243c",
INIT_32 => X"a324af03af270003278f0324001000ac3c24008c3cac008f0024003c8c3c0010",
INIT_33 => X"14003c8c340010240010248c3c00100083a4248fa3001000102400100094008f",
INIT_34 => X"af270003278f0324a4008fa30010ac3cac243cac3cac008c3c240018008c3c00",
INIT_35 => X"0010240010248c3c00100083a4248fa3001000102400100094008fa324afaf03",
INIT_36 => X"3cac0024003c8c248c3c001028008c3c0004008f0010008faf008c34af008c34",
INIT_37 => X"af008fafaf03af270003278f0324a4008fa30010ac243cac3cac3cac3c24008c",
INIT_38 => X"10afafafafaf03afaf270003278f038f00140080a00080af24008faf24008f00",
INIT_39 => X"8f8faf240010af240010248f0004008fa3001428008faf24008fa02400278f00",
INIT_3A => X"008f001028008faf0000000014008f8faf00000014008f8f0010af24af000000",
INIT_3B => X"1000008c008f00008f240014008fa000278f0000302430008f00100000302430",
INIT_3C => X"8f0010008c008fa02400278faf24008f0014248f0000100004008faf24008f00",
INIT_3D => X"2700248c008f0010ac008f00008f24000c8f0000008f2700100000008f248c00",
INIT_3E => X"af03af270003278f0300ac343c343cafaf03af270003278f8f0300000c8f0000",
INIT_3F => X"008fafaf03af270003278f038f0014008faf00008f24008faf302c008f0010af"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"b8afaeadacabaaa9a8a7a6a5a4a3a2a1bd000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"b9b8afaeadacabaaa9a8a7a6a5a4a3a2a1a50086c6c406bb00bb00ba5a1abfb9",
INIT_02 => X"9392919000405a1a06e0a606a606a606a6a50584e0029b401bbd60bb60bbbabf",
INIT_03 => X"00e000c4e0000085a2e09f9d9c9e979695949392919002e09f9d9c9e97969594",
INIT_04 => X"42420200c4a0bebd00e0bdbec0004300c302c2000007624000c2c3c5c4a0bebd",
INIT_05 => X"00c20000040062024300c20000c4a0bebfbd00e0bdbec0004300c30200404200",
INIT_06 => X"00c2c30000c202c4a0bebfbd00e0bdbebfc0000040004200c20000400042c343",
INIT_07 => X"c000004100c2c24200c20000404200c200000000404200c200404200c2c24243",
INIT_08 => X"00400042c34300c20000c2c20000c440c660c2c3c6c5c4a0bebfbd00e0bdbebf",
INIT_09 => X"02a0bebd00e0bdbebfc0000040004200c24303c2c24200c2006202434200c200",
INIT_0A => X"00000000e0bdbebfc002020042020040000000a0bebfbd00e0bdbec042004242",
INIT_0B => X"44020000440245020600004402450206000044020000440200004402a0bebfbd",
INIT_0C => X"04450246024702a24202a202000004450246024702a24202a202000044020000",
INIT_0D => X"00004402450246024702a24202a20200004402450246024702a24202a2020000",
INIT_0E => X"4402000000004402000044020000000044020000440200000000440200004402",
INIT_0F => X"0200004402000000004402004000420200004402000044020000000044020000",
INIT_10 => X"c2020000c202c0c0a0bebfbd00e0bdbebfc00000000400004005004202000044",
INIT_11 => X"00c40500004000c200406200c2c3c24200c20000c000400007624000c2c30000",
INIT_12 => X"4200c2c202006200c24362420300c30200004005004262420300c30200000400",
INIT_13 => X"004402000043024300420200004402006202c300404200c2c24200c2000004c2",
INIT_14 => X"00c20000040000c4c24300c3c20000c0c0c6c5c4a0bebfbd00e0bdbebfc00000",
INIT_15 => X"00c2c2424200c2c202006200c2436200c30200c200000400004000426200c302",
INIT_16 => X"00004402000043024300420200004402006202c30000c4050000004402004042",
INIT_17 => X"c20000040000c4c2006200c2c30000c0c0c7c6c5c4a0bebfbd00e0bdbebfc000",
INIT_18 => X"c2c2424200c2c202006200c2436200c30200c200000400004000426200c30200",
INIT_19 => X"00426200c30200c20000040000c4c2006200c24300c20000c000000400404200",
INIT_1A => X"00000400404200c2c2424200c2c202006200c2436200c30200c2000004000040",
INIT_1B => X"00004000426200c302624202c30000040000c4c2000007624000c3c20000c202",
INIT_1C => X"0200000400404200c2c2424200c2c202006200c2436200c302624202c3000004",
INIT_1D => X"000400004000426200c302624202c30000040000c4c20007624000c3c20000c2",
INIT_1E => X"05000000440200404200c2c2424200c2c202006200c2436200c302624202c300",
INIT_1F => X"bfbd00e0bdbebfc00000004402000043024300420200004402006202c30000c4",
INIT_20 => X"0004000040004262420300c3020000040000c4c26200c2c30000c0c0c202a0be",
INIT_21 => X"00c2c30000c000000400404200c2c24200c2c202006200c24362420300c30200",
INIT_22 => X"6200c24362420300c302000004000040004262420300c3020000040000c4c262",
INIT_23 => X"000043024300420200004402006202c30000440200404200c2c24200c2c20200",
INIT_24 => X"c2030200c24382c4c2030200c20000c0c0a0bebfbd00e0bdbebfc00000004402",
INIT_25 => X"00c2004262c3c20000c000404200c2c24200c24300c362c30200c24382c40200",
INIT_26 => X"6200c24362420300c30200000400004005004262420300c3020000040000c405",
INIT_27 => X"0400004005004262420300c3020000040000c40500c2004262c30200c2c20200",
INIT_28 => X"020000040000c40500c2004262c30200c2c202006200c24362420300c3020000",
INIT_29 => X"c2c24200c2c202006200c24362420300c30200000400004005004262420300c3",
INIT_2A => X"bebfc00000004402000043024300420200004402006202c30000440200404200",
INIT_2B => X"0000040000400042020000040000c4c26200c2c3c0c202c202a0bebfbd00e0bd",
INIT_2C => X"434202000004000040004242020000040000c4c26200c2c3c202006200c24302",
INIT_2D => X"00c2434202000004000040004242020000040000c4c26200c2c3c202006200c2",
INIT_2E => X"02006200c2434202000004000040004242020000040000c4c20200c2c2020062",
INIT_2F => X"00c2c202006200c2434202000004000040004242020000040000c4c24200c2c2",
INIT_30 => X"006202c300004402c202006200c2434202000040004242020000040000c4c242",
INIT_31 => X"42004202c4a0bebd0000e0bdbebfc00000004402000043024300420200004402",
INIT_32 => X"c202c4a0bebd00e0bdbec0020000004302430042024300c36242030243020040",
INIT_33 => X"40620243020000020062024302004000c24303c2c000000043030040004200c2",
INIT_34 => X"bebd00e0bdbec0024000c2c00000400243030240024300630302004000420200",
INIT_35 => X"0000020062024302004000c24303c2c000000043030040004200c2c202c0c4a0",
INIT_36 => X"02438242040243024402004042004202004000c2004000c2c2004202c2004202",
INIT_37 => X"c200c2c5c4a0bebd00e0bdbec0024000c2c00000430302400240024302430042",
INIT_38 => X"00c0c7c6c5c4a0bebfbd00e0bdbec0c200400042430063c46400c3c34300c200",
INIT_39 => X"c2c3c2020000c202006202c3004100c2c000404200c2c24200c2430362c3c200",
INIT_3A => X"00c200404200c2c2000007624000c3c2c20007624000c3c20000c202c2006200",
INIT_3B => X"4062004200c26200c203004000c26283c4c3020242424200c200000202424242",
INIT_3C => X"c20040004200c2430362c3c2c24200c2006202c3000000004100c2c24200c200",
INIT_3D => X"c362034200c200004300c26200c2030000c4406200c2c30040628200c2044300",
INIT_3E => X"c4a0bebd00e0bdbec0004363034202c5c4a0bebd00e0bdbebfc0000000c44062",
INIT_3F => X"00c2c5c4a0bebd00e0bdbec0c2004000c2c26200c34200c2c2424200c20000c0"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"00000000000000000000000000000000ff00000800ff1800350035003300b200",
INIT_01 => X"000000000000000000000000000000000000072000002000d800d800ff700000",
INIT_02 => X"0000000000000010000000000000000000010060006060000000000000000000",
INIT_03 => X"0000000000201000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000200000f000ff00000000e800000000800010100000000000000000f000ff",
INIT_05 => X"0000000000000000000000000000f00000ff00000000e8000000002000ff0000",
INIT_06 => X"0000000000000000f00000ff0000000000e80000ff0000000000002000000000",
INIT_07 => X"e80000ff000000ff000000002000000000000000200000000000000000000010",
INIT_08 => X"0020000000000000000000000007002800380000000000f00000ff0000000000",
INIT_09 => X"20f000ff0000000000e80000ff0000000000000000ff000000000000ff000000",
INIT_0A => X"0000000000000000e8161600002000ff000100f00000ff00000000e800000000",
INIT_0B => X"2a00000256922700000002561227000000002a0000002a0000002a00f00000ff",
INIT_0C => X"032800280028000028000000000200280028002800002800000000002a000000",
INIT_0D => X"0002230029002900290000290000000002430028002900290000290000000002",
INIT_0E => X"2a00000400002a0000002a00000500002a0000002a00000300002a0000002a00",
INIT_0F => X"0000002b00000000002b00000000330000002b0000002b00000200002a000000",
INIT_10 => X"0000000000000000f00000ff0000000000e8000000000001200030330000002b",
INIT_11 => X"010000300000000000ff10000000000000000000000000100000000000000000",
INIT_12 => X"0000000000000000000010241800000000012000300010241800000000000000",
INIT_13 => X"002b00000033000000330000002b000000000000ff0300000000000000000000",
INIT_14 => X"0000000000000000001000000000000000000000f00000ff0000000000e80000",
INIT_15 => X"000000ff00000000000000000000100000100000000000000020000010000010",
INIT_16 => X"00002b00000033000000330000002b0000000000000100003000002b0000ff00",
INIT_17 => X"000000000000000010000000000000000000000000f00000ff0000000000e800",
INIT_18 => X"0000ff0000000000000000000010000010000000000000002000001000001000",
INIT_19 => X"0000100000100000000000000000001000000001000000000000000000ff0000",
INIT_1A => X"00000000ff00000000ff00000000000000000000100000100000000000000020",
INIT_1B => X"00002000001000001010ff3f0000000000000000101000000000000000000000",
INIT_1C => X"0000000000ff00000000ff000000000000000000001000001010ff3f00000000",
INIT_1D => X"000000002000001000001010ff3f000000000000000010000000000000000000",
INIT_1E => X"003000002b0000ff00000000ff000000000000000000001000001010ff3f0000",
INIT_1F => X"00ff0000000000e80000002b00000033000000330000002b0000000000000100",
INIT_20 => X"000000002000001029180000000000000000000010000000000000000012f000",
INIT_21 => X"00000000000000000000ff000000000000000000000000000010291800000000",
INIT_22 => X"00000000102a180000000000000000200000102a180000000000000000000010",
INIT_23 => X"000033000000330000002b000000000000002c0000ff00000000000000000000",
INIT_24 => X"001c1c0000001000001e1e000000000000f00000ff0000000000e80000002b00",
INIT_25 => X"3000000010000000000000ff0000000000000000000010001000000010001000",
INIT_26 => X"00000000102c18000000000000000120003000102c1800000000000000010000",
INIT_27 => X"00000120003000102c1800000000000000010000300000001000100000000000",
INIT_28 => X"000000000001000030000000100010000000000000000000102c180000000000",
INIT_29 => X"000000000000000000000000102c18000000000000000120003000102c180000",
INIT_2A => X"0000e80000002b00000033000000330000002b000000000000002c0000ff0000",
INIT_2B => X"000000000020002c0000000000000000100000000000430012f00000ff000000",
INIT_2C => X"002c0000000000002000002c0000000000000000100000000000000000002c00",
INIT_2D => X"0000002c0000000000002000002c000000000000000010000000000000000000",
INIT_2E => X"0000000000002c0000000000002000002c000000000000000010000000000000",
INIT_2F => X"0000000000000000002c0000000000002000002c000000000000000000000000",
INIT_30 => X"0000000000002c00000000000000002c0000002000002c0000000000000000ff",
INIT_31 => X"0000330000f000ff000000000000e80000002b00000033000000330000002b00",
INIT_32 => X"000000f000ff00000000e8ff0000103300000033000000001035180033000000",
INIT_33 => X"0010400080000000000000320000000000000000000000000000000000000000",
INIT_34 => X"00ff00000000e8000000000000ff33003300003200000035007f000000330000",
INIT_35 => X"00000000000033000000000000000000000000000000000000000000000000f0",
INIT_36 => X"000010352000007f330000000000330000000000000000000000008000000080",
INIT_37 => X"0000000000f000ff00000000e8000000000000ff330000330032003300000033",
INIT_38 => X"000000000000f00000ff00000000e80000ff0000000000000000000000000000",
INIT_39 => X"000000ff0000000000000000000000000000ff00000000000000000010000000",
INIT_3A => X"0000000000000000101000000000000000100000000000000000000000100000",
INIT_3B => X"0010000000001800000000000000001800001616000000000000001616000000",
INIT_3C => X"00000000000000000010000000ff00000000ff0000000000ff000000ff000000",
INIT_3D => X"0010000000000000000000180000000006002810000000000010100000000000",
INIT_3E => X"00f000ff00000000e80000fc0000200000f000ff0000000000e8000006002810",
INIT_3F => X"00000000f000ff00000000e80000ff000000100000ff00000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"4c4844403c3834302c2824201c181410980e00ac04fd2a001800b0000000f001",
INIT_01 => X"504c4844403c3834302c2824201c18141000cc2410200060125c1058fc005450",
INIT_02 => X"0c08040000083c0048080c440840043c006000000800000801681360115c5854",
INIT_03 => X"00080c000810121900082c2824201c1814100c08040000082c2824201c181410",
INIT_04 => X"00200000082504f80008100c2500000000100012100d1b020014101410250cf0",
INIT_05 => X"001800980d00040a000018001318251014e80008080425000000080000fa0200",
INIT_06 => X"001020001e101c2025181ce00008181014250000e90000001800982500001801",
INIT_07 => X"250000e0001010fc0010009825570014000700982530001400090a0014140f06",
INIT_08 => X"9825000010010010001810140016a025a42514a8a8a4a025989c60000820181c",
INIT_09 => X"002504f80008a0989c250000e400000010000d1010ff001000080a00ff001000",
INIT_0A => X"000000000818101425030000000000fd003c00251014e8000808042501000020",
INIT_0B => X"8000008878348c0002008878340c000100ae680000ae540000ae3c0025181ce0",
INIT_0C => X"2184009c00b40010d800140200e7070c0024003c00106000140100ae680000ae",
INIT_0D => X"00e7450174008c00a40010c800140400e72105fc0014002c00105000140300e7",
INIT_0E => X"f800008b00ae680000aee000006300ae680000aec80000fe00ae680000aea800",
INIT_0F => X"0000ae5000001300ae4800000700100000ae380000ae2800001400ae680000ae",
INIT_10 => X"1403004b10031c18252024d8000820181c250000980a0005250a25100000ae5c",
INIT_11 => X"05100a250026001400eb2a00101414020014000b140004100d1a020014100011",
INIT_12 => X"0100181c0100030010002170800018000005250a250021708000180000983a00",
INIT_13 => X"ae9c00000510000100100000ae7400000d011c00b2e800101002001000982018",
INIT_14 => X"001000983a00d4181807002810002c1014302c28252024d80008282024250000",
INIT_15 => X"001010ff0100101401000300180021002c80001000982000d425000021002c80",
INIT_16 => X"00aee400000510000100100000aed800000d01140005300a2500aec40000d120",
INIT_17 => X"1000983a00d418181218002810002d101434302c28252024d800082820242500",
INIT_18 => X"1010ff0100101401000300180021002c80001000982000d425000021002c8000",
INIT_19 => X"000021003080001000983a00d4181812180028230010002f1000980a00d00600",
INIT_1A => X"00980a00ce06001010ff0100101401000300180021003080001000982000d425",
INIT_1B => X"00d42500002100348021ffff1000983a00d4181812100d1a0200281000341001",
INIT_1C => X"0100980a00c90a001010ff010010140100030018002100348021ffff10009820",
INIT_1D => X"982000d42500002100388021ffff1000983a00d41818100d1a02002810003310",
INIT_1E => X"0a2500aef00000ca0a001010ff010010140100030018002100388021ffff1000",
INIT_1F => X"24d80008282024250000aee400000510000100100000aed800000d011400053c",
INIT_20 => X"982000d425000021ec8000100000983a00d41c1c21001018002b101418342520",
INIT_21 => X"001018002b1000980a00d20a00101001001014010003001c0021ec8000100000",
INIT_22 => X"03001c0021148000100000982000d425000021148000100000983a00d41c1c23",
INIT_23 => X"000510000100100000aed800000d011400ae140000d20a001010010010140100",
INIT_24 => X"10030000100c21101003000010001f1014259094680008282024250000aee400",
INIT_25 => X"2518000c21101000871000de0a0010100100103c001021108000101c21104000",
INIT_26 => X"030018002158800010000098200005250a250021588000100000983a0005180a",
INIT_27 => X"200005250a250021588000100000983a0005180a2518001c2110400010140100",
INIT_28 => X"0000983a0005180a2518003c2110800010140100030018002158800010000098",
INIT_29 => X"10100100101401000300180021588000100000980a0005250a25002158800010",
INIT_2A => X"9094250000aee400000510000100100000aed800000d011400ae300000760a00",
INIT_2B => X"00982000d42500800000983a00d41c1c240018141018211434252024d8000898",
INIT_2C => X"04800000982000d4250004800000983a00d41c1c2500181410010003001c8000",
INIT_2D => X"001c08800000982000d4250008800000983a00d41c1c2600181410010003001c",
INIT_2E => X"010003001c0c800000982000d425000c800000983a00d41c1c27001410010003",
INIT_2F => X"001410010003001c10800000982000d4250010800000983a00d41c1c12001410",
INIT_30 => X"000d011000ae400010010003001c14800000d4250014800000983a00d41c1cee",
INIT_31 => X"0f002400082504f8000008282024250000aee400000510000100100000aed800",
INIT_32 => X"000110250cf00008080425ff0002252400010024000000082130800024000013",
INIT_33 => X"0b24000000001f01000401f0000006000000321000002a000732000600000010",
INIT_34 => X"14e80008100c25030000100000d82c00280100f00000003000fc000600240000",
INIT_35 => X"003401000401280000060000005d1800003f00075d0006000000180001041825",
INIT_36 => X"00002170800000fc200000100f00200000160008001a00040800000004000004",
INIT_37 => X"0000101410250cf00008181425030000180000c32c01002800f0002000010020",
INIT_38 => X"0a104c48444025383cc00008100c250000f20000000000140100141001001000",
INIT_39 => X"184018ff0003180100050a48000500402f00f30f001010010010102021101000",
INIT_3A => X"0010000a0a00101c12100d1b02001c4810100d1b02001c48003e140e1c121800",
INIT_3B => X"0b2a0000004c2300140f000c001c102110140300ff57ff001000080300ff30ff",
INIT_3C => X"4c000b0000004c102d21101414ff0014000aff1800000200c0001414ff001400",
INIT_3D => X"20230f00004c000c00004c2300140f00f844252100142000122a2300140f0000",
INIT_3E => X"10250cf000080804250000180360000c082504f8000840383c250000f8442521",
INIT_3F => X"00080c082504f80008100c250000f1001010240010ff001000ff010000000d00"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"00008f8faf000c8faf0000008f00008fafaf03afaf270003278f030000008f00",
INIT_01 => X"8f0000003c8fac008fac008fac008f30008fafafafafaf03af270003278f8f03",
INIT_02 => X"0010248f001428008faf24008faf00008f0030003000008f8c008f0010afac00",
INIT_03 => X"10240014008f8f001024001000008f8c008f001024001000008f8c008f001024",
INIT_04 => X"03af270003278f0300008faf03af270003278f0300001024001028008c008f00",
INIT_05 => X"343c000c243c000c343c34af24afaf03afafaf27000003278f030000343c8faf",
INIT_06 => X"240004008c340010ac24ac343c24ae000c242424000c243cac008f343caf008c",
INIT_07 => X"008fae000c242424000c24000c0024008f000c243c0014248faf000c8faf008c",
INIT_08 => X"00000000000003278f8f8f0300000c00142c008fac008f24af000c8f0010af24",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000102040912000000",
INIT_0F => X"fffffffffffffffffffffffffffffffffffffffffffffefcf9f2e4c992000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000606060606050000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000010101010101000000",
INIT_14 => X"3d3d3d3d3d3d676620740a0a747320650a000000000000000000000000000000",
INIT_15 => X"694c7363726d69546e616f6269546f6175206467730a00696920746c6c67730a",
INIT_16 => X"4e490a007420696c54004546455000454d500a6469540030617261736d657061",
INIT_17 => X"544c4c0a0a53200a4c2000454e490a0044414f4c41454e490a0044414f4c4145",
INIT_18 => X"0000000000000000000054204945540a54204d0a542043422f440a2054494920",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000102040912000000000000000000000000000000",
INIT_1F => X"fffffffffffffffffffffefcf9f2e4c992000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000606060606050000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000010101010101000000000000000000000000000000",
INIT_24 => X"7566542055000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000072756570695300736e61756369670a0a727475526e2068616e",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"6200c2c3c20000c4c2430300c30200c2c5c4a0bebfbd00e0bdbec0620200c202",
INIT_01 => X"c240026202c34000c24000c24300c24300c2c0c7c6c5c4a0bebd00e0bdbebfc0",
INIT_02 => X"006202c300404200c2c24200c2c24300c2404202424300c24300c20000c04300",
INIT_03 => X"0002006200c2c300000200404300c24300c200000200404300c24300c2000002",
INIT_04 => X"a0bebd00e0bdbec00200c2c4a0bebd00e0bdbec000000002004042004200c200",
INIT_05 => X"4202000044020000440205c202c5c4a0b0bebfbd0000e0bdbec002624202c3c4",
INIT_06 => X"0200400042020000400243630302020000040510000044024300c34202c20042",
INIT_07 => X"00c20200000405100000040000400500c200004402006202c3c20000c4c20042",
INIT_08 => X"000000000000e0bdb0bebfc000000000404200c24300c302c20000c40000c242",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"00000000000000000000000000000000010204091224489123468d1a34000000",
INIT_0F => X"fffffffffffffffffffffffffffffefcf9f2e4c99224489123468d1a34000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000ffffff",
INIT_11 => X"0000000000000000000000000000000000000003030303030300000000000000",
INIT_12 => X"02010000000000000000000000000000010101020515100b0500fb1a150f0a05",
INIT_13 => X"0000000000000000000000000000000000000000000001504f4e4d4c4b050403",
INIT_14 => X"0a3d3d3d3d3d0a747369540a656d707247000000000000000000000000000000",
INIT_15 => X"6e69736379656e65737470696e656e63622f6920740a006f762f69697420740a",
INIT_16 => X"554d0a0073746c206f00444144410053414c0a6f6e6500306e206c206220726c",
INIT_17 => X"4949540a0a45500a4546005347460a0021534e414c52554d0a0021494e414c52",
INIT_18 => X"0000000000000000000020544f52200a20544f0a2054545420450a00454f562f",
INIT_19 => X"00000000000000000000000000000000000000000000000000000000ff000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"00000000010204091224489123468d1a34000000000000000000000000000000",
INIT_1F => X"fffffefcf9f2e4c99224489123468d1a34000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000ffffffffffffffffffffffffffffff",
INIT_21 => X"0000000000000003030303030300000000000000000000000000000000000000",
INIT_22 => X"00000000010101020515100b0500fb1a150f0a05000000000000000000000000",
INIT_23 => X"0000000000000000000001504f4e4d4c4b050403020100000000000000000000",
INIT_24 => X"20203a5441000000000000000000000000000000000000000000000000000000",
INIT_25 => X"00000000000000206d74616e65007420746e6f6e690a006b2074542074696420",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"100000000000070000101f00001000000000f00000ff00000000e8101400001f",
INIT_01 => X"001814100f000000000000000000000000000000000000f000ff0000000000e8",
INIT_02 => X"0000000000ff0000000000000000100000180010001000000000000000000000",
INIT_03 => X"0000000000000000000000001000000000000000000000100000000000000000",
INIT_04 => X"f000ff00000000e817000000f000ff00000000e8100000000000000000000000",
INIT_05 => X"00200000320000007801e100000000f0000000ff0000000000e81010ff1f0000",
INIT_06 => X"7f00000000800000007f00ff0f7f00000700007f000032000000000020000000",
INIT_07 => X"000000000700007f000000000120003000000032000000000000000800000000",
INIT_08 => X"0000000000000000000000e810000100ff0000000000007f0000080000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0101010101010101010101010101010000000000000000000000000000000000",
INIT_0B => X"0202020201010101010101010101010101010101010101010101010101010101",
INIT_0C => X"0202020202020202020202020202020202020202020202020202020202020202",
INIT_0D => X"0303030303030303030303030303030303030303030303030303030303030202",
INIT_0E => X"0000000000000000010204091224489123468d1a3468d1a2458a152b56030303",
INIT_0F => X"fffffffffffffefcf9f2e4c99224489123468d1a3468d1a2458a152b56000000",
INIT_10 => X"0000000000000000000000000000000000080808080707000000000000ffffff",
INIT_11 => X"000000000000000000000000000000000101039e9b9794918e0f0c0906030000",
INIT_12 => X"46230000000000000000000095a8c0e00d50c1a1439e5b17d4914e4f0cc98643",
INIT_13 => X"1212121212000000000000000000202429303a48619123c7a4815d3a17b08d69",
INIT_14 => X"003d3d3d3d3d0069686e650073616c6165121212121212121212121212121212",
INIT_15 => X"67730a65206d67730a69657467730a7474206e616954006e69206f63696d6954",
INIT_16 => X"4d4550003a65656674002149215300542041006e6773003020746c73656e696c",
INIT_17 => X"4f43494d0044410044410054205453000a53205443204d4550000a4c20544320",
INIT_18 => X"0000000000000000000000454e414f420045524d00454f5253524100534e4920",
INIT_19 => X"00000000000000000000000000000000000000000000000000001212ed515302",
INIT_1A => X"0101010000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0101010101010101010101010101010101010101010101010101010101010101",
INIT_1C => X"0202020202020202020202020202020202020202020202020101010101010101",
INIT_1D => X"0303030303030303030303030303030303030202020202020202020202020202",
INIT_1E => X"1224489123468d1a3468d1a2458a152b56030303030303030303030303030303",
INIT_1F => X"9224489123468d1a3468d1a2458a152b56000000000000000000000001020409",
INIT_20 => X"0000000000080808080707000000000000fffffffffffffffffffefcf9f2e4c9",
INIT_21 => X"000000000101039e9b9794918e0f0c0906030000000000000000000000000000",
INIT_22 => X"95a8c0e00d50c1a1439e5b17d4914e4f0cc98643000000000000000000000000",
INIT_23 => X"0000202429303a48619123c7a4815d3a17b08d69462300000000000000000000",
INIT_24 => X"6379204552121212121212121212121212121212121212121200000000000000",
INIT_25 => X"0000000000000000622063676e000a7469696d676e4200737770205568732072",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"250014101400dc101025400020400024242025181ce000080804252500000c00",
INIT_01 => X"20250224ff1000001c000018000014ff0010041c181410250cf0000820181c25",
INIT_02 => X"0004010400ea080000000100000421000425ff2b010700000000140013000000",
INIT_03 => X"0c04000400181c00140300042a002400001c001f0200042a0024000018002a01",
INIT_04 => X"2504f80008080425420008082504f80008100c25250002050004020000002000",
INIT_05 => X"500000ae6c000080407d0010013c38252c3034c80000080804254224feff0808",
INIT_06 => X"fc002e000000003300fc00fffffc0000f90103fc00aea8000000143000140000",
INIT_07 => X"00100000f90103fc00980a0005250a251000aecc00001a011c1c009118180000",
INIT_08 => X"0b070503000008382c30342525006000ca650010000020fc20009d1800091001",
INIT_09 => X"9d97958b89837f716d6b67656159534f4947433d3b352f2b29251f1d1713110d",
INIT_0A => X"5b514b3d393733251b19150f0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a3",
INIT_0B => X"231d0b09fdf7f3ebe7dfd3cfcdc9c1bbb7b1afa5a399918d857f7b756f67615d",
INIT_0C => X"efe7e3ddd7cfc5bdb3aba5a195938d878381776b69655f5957514b413b39332d",
INIT_0D => X"d1cbc7b9b3ada9a1978f8b7773716d5f5b5955473d3b37352b291d130501f9f5",
INIT_0E => X"010204091224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78e5dfd7",
INIT_0F => X"f9f2e4c99224489123468d1a3468d1a2458a152b56ac59b367cf9e3c78000000",
INIT_10 => X"070001020301010000000101010102030718110a03fcf5231c150e0700fffefc",
INIT_11 => X"0000010303010100010059647285a0c80b90212807e6c5a483a5846342210007",
INIT_12 => X"8a4500030103030001000100ae6472856dc80b90212807e6c5a483a584634221",
INIT_13 => X"38373635340005010300010001005d689c8b41d117a245c8833ef9b46f5914cf",
INIT_14 => X"003d3d3d3d3d006e696773007420616c6e2b2c2d2e2f30313233343d3c3b3a39",
INIT_15 => X"20740073616f2074006f722020740069727367646e65000a73646e6170756e65",
INIT_16 => X"422052002073646161000a4c00530020545300652074000a3168656d72756d20",
INIT_17 => X"4e4150550021530021490020544948000a4550495543422052000a4546495543",
INIT_18 => X"0908070605040302010000535354504900535945005352415520440054205344",
INIT_19 => X"6159534f4947433d3b352f2b29251f1d1713110d0b07050300002246cb153520",
INIT_1A => X"0d0701fbf1efe9e5e3dfd3c7c5c1bfb5b3ada7a39d97958b89837f716d6b6765",
INIT_1B => X"cdc9c1bbb7b1afa5a399918d857f7b756f67615d5b514b3d393733251b19150f",
INIT_1C => X"95938d878381776b69655f5957514b413b39332d231d0b09fdf7f3ebe7dfd3cf",
INIT_1D => X"73716d5f5b5955473d3b37352b291d130501f9f5efe7e3ddd7cfc5bdb3aba5a1",
INIT_1E => X"3468d1a2458a152b56ac59b367cf9e3c78e5dfd7d1cbc7b9b3ada9a1978f8b77",
INIT_1F => X"3468d1a2458a152b56ac59b367cf9e3c78000000010204091224489123468d1a",
INIT_20 => X"010102030718110a03fcf5231c150e0700fffefcf9f2e4c99224489123468d1a",
INIT_21 => X"7285a0c80b90212807e6c5a483a5846342210007070001020301010000000101",
INIT_22 => X"ae6472856dc80b90212807e6c5a483a584634221000001030301010001005964",
INIT_23 => X"01005d689c8b41d117a245c8833ef9b46f5914cf8a4500030103030001000100",
INIT_24 => X"616f4953542b2c2d2e2f30313233343d3c3b3a39383736353400050103000100",
INIT_25 => X"0000000100000000656e6b2064000a656f636d206e6500216f756f41652c7465",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_04a is
end entity inline_04a;
----------------------------------------------------------------
architecture test of inline_04a is
begin
process is
-- code from book:
type stimulus_record is record
stimulus_time : time;
stimulus_value : real_vector(0 to 3);
end record stimulus_record;
type stimulus_ptr is access stimulus_record;
variable bus_stimulus : stimulus_ptr;
-- end of code from book
begin
bus_stimulus := new stimulus_record;
bus_stimulus.all := stimulus_record'(20 ns, real_vector'(0.0, 5.0, 0.0, 42.0) );
report time'image(bus_stimulus.all.stimulus_time);
report time'image(bus_stimulus.stimulus_time);
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_04a is
end entity inline_04a;
----------------------------------------------------------------
architecture test of inline_04a is
begin
process is
-- code from book:
type stimulus_record is record
stimulus_time : time;
stimulus_value : real_vector(0 to 3);
end record stimulus_record;
type stimulus_ptr is access stimulus_record;
variable bus_stimulus : stimulus_ptr;
-- end of code from book
begin
bus_stimulus := new stimulus_record;
bus_stimulus.all := stimulus_record'(20 ns, real_vector'(0.0, 5.0, 0.0, 42.0) );
report time'image(bus_stimulus.all.stimulus_time);
report time'image(bus_stimulus.stimulus_time);
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_04a is
end entity inline_04a;
----------------------------------------------------------------
architecture test of inline_04a is
begin
process is
-- code from book:
type stimulus_record is record
stimulus_time : time;
stimulus_value : real_vector(0 to 3);
end record stimulus_record;
type stimulus_ptr is access stimulus_record;
variable bus_stimulus : stimulus_ptr;
-- end of code from book
begin
bus_stimulus := new stimulus_record;
bus_stimulus.all := stimulus_record'(20 ns, real_vector'(0.0, 5.0, 0.0, 42.0) );
report time'image(bus_stimulus.all.stimulus_time);
report time'image(bus_stimulus.stimulus_time);
wait;
end process;
end architecture test;
|
-----------------------------------------------------------------------------------------------------------
--
-- COMPONENTS PACKAGE
--
-- This package contains several frequently used basic cop_components.
--
-- Created by Claudio Brunelli, 2004
--
-----------------------------------------------------------------------------------------------------------
--Copyright (c) 2004, Tampere University of Technology.
--All rights reserved.
--Redistribution and use in source and binary forms, with or without modification,
--are permitted provided that the following conditions are met:
--* Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--* Neither the name of Tampere University of Technology nor the names of its
-- contributors may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--THIS HARDWARE DESCRIPTION OR SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
--CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND NONINFRINGEMENT AND
--FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
--OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
--EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
--PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
--BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--ARISING IN ANY WAY OUT OF THE USE OF THIS HARDWARE DESCRIPTION OR SOFTWARE, EVEN
--IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------------------------------------
--
-- OE_register
--
-- General purpose register, "reg_width" wide. WRITE ENABLE, OUTPUT ENABLE and RESET commands are provided.
-- Default content at RESET is "zero". WRITE ENABLE, OUTPUT ENABLE and RESET commands polarity are
-- specified by dedicated constants defined in "cop_definitions" package.
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity OE_register is
generic(reg_width: Integer := word_width);
port( clk : in Std_logic;
reset : in Std_logic;
we : in Std_logic;
oe : in Std_logic;
data_in : in Std_logic_vector(reg_width-1 downto 0);
data_out : out Std_logic_vector(reg_width-1 downto 0) );
end OE_register;
architecture rtl of OE_register is
signal regout: std_logic_vector(reg_width-1 downto 0);
begin
process(clk, reset)
begin
if reset = reset_active then
regout <= Conv_std_logic_vector(0, reg_width);
elsif CLK'EVENT and CLK='1' then
if we = we_active then
regout <= data_in;
end if;
end if;
end process;
process (oe, regout)
begin
if oe = oe_active then
data_out <= regout;
else
data_out <= (others => 'Z');
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- WE_register
--
-- General purpose register, "reg_width" wide. WRITE ENABLE and RESET commands are provided.
-- Default content at RESET is "zero". WRITE ENABLE and RESET commands polarity are
-- specified by dedicated constants defined in "cop_definitions" package.
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity WE_register is
generic(reg_width: Integer := word_width);
port( clk : in Std_logic;
reset : in Std_logic;
we : in Std_logic;
data_in : in Std_logic_vector(reg_width-1 downto 0);
data_out : out Std_logic_vector(reg_width-1 downto 0) );
end WE_register;
architecture rtl of WE_register is
begin
process(clk, reset)
begin
if reset = reset_active then
data_out <= Conv_std_logic_vector(0, reg_width);
elsif CLK'EVENT and CLK='1' then
if we = we_active then data_out <= data_in;
end if;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- SIMPLE DATA REGISTER
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity data_register is
generic(reg_width: integer :=8);
port(
clk : in Std_logic;
reset : in Std_logic;
data_in : in Std_logic_vector(reg_width-1 downto 0);
data_out : out Std_logic_vector(reg_width-1 downto 0)
);
end data_register;
architecture rtl of data_register is
begin
process(clk, reset)
begin
if reset = reset_active then
data_out <= Conv_std_logic_vector(0,reg_width);
elsif CLK'EVENT and CLK='1' then
data_out <= data_in;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- NOP REGISTER
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity nop_register is
generic(reg_width: integer :=word_width);
port(
clk : in Std_logic;
reset : in Std_logic;
data_in : in Std_logic_vector(reg_width-1 downto 0);
data_out : out Std_logic_vector(reg_width-1 downto 0)
);
end nop_register;
architecture rtl of nop_register is
begin
process(clk, reset)
begin
if reset = reset_active then
data_out <= "00000000000000000000000000001000"; -- NOP configuration
elsif CLK'EVENT and CLK='1' then
data_out <= data_in;
end if;
end process;
end rtl;
----------------------------------------------------------------------------------------------------------
--
-- D-type Flip-Flop provided with Write Enable command
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity WEDFF is
port( clk : in Std_logic;
reset : in Std_logic;
we : in Std_logic;
d : in Std_logic;
q : out Std_logic );
end WEDFF;
architecture rtl of WEDFF is
begin
process(clk, reset)
begin
if reset = reset_active then
q <= '0';
elsif CLK'EVENT and CLK='1' then
if we = we_active then
q <= d;
end if;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- D-type Flip-Flop reset
-- value ='0'
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity data_ff is
port( clk : in Std_logic;
reset : in Std_logic;
d : in Std_logic;
q : out Std_logic );
end data_ff;
architecture rtl of data_ff is
begin
process(clk, reset)
begin
if reset = reset_active then
q <= '0';
elsif CLK'EVENT and CLK='1' then
q <= d;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- D-type Flip-Flop reset value = '1'
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity data_ff_1 is
port( clk : in Std_logic;
reset : in Std_logic;
d : in Std_logic;
q : out Std_logic );
end data_ff_1;
architecture rtl of data_ff_1 is
begin
process(clk, reset)
begin
if reset = reset_active then
q <= '1';
elsif CLK'EVENT and CLK='1' then
q <= d;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- DECODER 3:8
--
-- The output addressed by dec_addr is the only one to get an "high" logic value
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity decoder3_8 is
port( dec_addr : in std_logic_vector(2 downto 0);
dec_out : out std_logic_vector(7 downto 0) );
end decoder3_8;
architecture rtl of decoder3_8 is
begin
process(dec_addr)
begin
dec_out(7) <= (dec_addr(2) and dec_addr(1) and dec_addr(0));
dec_out(6) <= (dec_addr(2) and dec_addr(1) and not (dec_addr(0)));
dec_out(5) <= (dec_addr(2) and not (dec_addr(1)) and dec_addr(0));
dec_out(4) <= (dec_addr(2) and not (dec_addr(1)) and not (dec_addr(0)));
dec_out(3) <= (not(dec_addr(2)) and dec_addr(1) and dec_addr(0));
dec_out(2) <= (not(dec_addr(2)) and dec_addr(1) and not(dec_addr(0)));
dec_out(1) <= (not(dec_addr(2)) and not(dec_addr(1)) and dec_addr(0));
dec_out(0) <= (not(dec_addr(2)) and not(dec_addr(1)) and not(dec_addr(0)));
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- TRISTATE BUFFER
--
-- It's a tristate buffer which is "buffer_width" wide. Output is set to Hi-Z value when its output enable
-- control pin is set to "oe_active" value.
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity tristate_buffer is
generic(width : integer := buffer_width);
port(
tristate_buffer_oe : in std_logic;
tristate_buffer_data_in : in std_logic_vector(buffer_width-1 downto 0);
tristate_buffer_data_out : out std_logic_vector(buffer_width-1 downto 0)
);
end tristate_buffer ;
architecture rtl of tristate_buffer is
begin
process (tristate_buffer_oe, tristate_buffer_data_in)
begin
if tristate_buffer_oe = oe_active then
tristate_buffer_data_out <= tristate_buffer_data_in;
else
tristate_buffer_data_out <= (others => 'Z');
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- 8_INPUTS MULTIPLEXER
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.cop_definitions.all;
entity MY_8IN_MUX is
generic (width : integer :=word_width);
port( in_a : in Std_logic_vector(width-1 downto 0);
in_b : in Std_logic_vector(width-1 downto 0);
in_c : in Std_logic_vector(width-1 downto 0);
in_d : in Std_logic_vector(width-1 downto 0);
in_e : in Std_logic_vector(width-1 downto 0);
in_f : in Std_logic_vector(width-1 downto 0);
in_g : in Std_logic_vector(width-1 downto 0);
in_h : in Std_logic_vector(width-1 downto 0);
sel : in Std_logic_vector(2 downto 0);
output : out Std_logic_vector(width-1 downto 0) );
end MY_8IN_MUX;
architecture rtl of MY_8IN_MUX is
begin
process(in_a,in_b,in_c,in_d,in_e,in_f,in_g,in_h,sel)
begin
if sel = "000" then
output <= in_a;
elsif sel = "001" then
output <= in_b;
elsif sel = "010" then
output <= in_c;
elsif sel = "011" then
output <= in_d;
elsif sel = "100" then
output <= in_e;
elsif sel = "101" then
output <= in_f;
elsif sel = "110" then
output <= in_g;
else
output <= in_h;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- CTRL_LOGIC MULTIPLEXER
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.cop_definitions.all;
entity DELAY_SELECT_MUX is
generic (width : integer := 8);
port( in_a : in Std_logic_vector(width-1 downto 0);
in_b : in Std_logic_vector(width-1 downto 0);
in_c : in Std_logic_vector(width-1 downto 0);
in_d : in Std_logic_vector(width-1 downto 0);
in_e : in Std_logic_vector(width-1 downto 0);
in_f : in Std_logic_vector(width-1 downto 0);
in_g : in Std_logic_vector(width-1 downto 0);
in_h : in Std_logic_vector(width-1 downto 0);
sel : in Std_logic_vector(6 downto 0);
output : out Std_logic_vector(width-1 downto 0)
);
end DELAY_SELECT_MUX;
architecture rtl of DELAY_SELECT_MUX is
begin
process(in_a,in_b,in_c,in_d,in_e,in_f,in_g,in_h,sel)
begin
if sel = "0000001" then
output <= in_b;
elsif sel = "0000010" then
output <= in_c;
elsif sel = "0000100" then
output <= in_d;
elsif sel = "0001000" then
output <= in_e;
elsif sel = "0010000" then
output <= in_f;
elsif sel = "0100000" then
output <= in_g;
elsif sel = "1000000" then
output <= in_h;
else
output <= in_a;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- 2_INPUTS MULTIPLEXER
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.cop_definitions.all;
entity MY_MUX is
generic (width : integer :=8);
port( in_a : in Std_logic_vector(width-1 downto 0);
in_b : in Std_logic_vector(width-1 downto 0);
sel : in Std_logic;
output : out Std_logic_vector(width-1 downto 0) );
end MY_MUX;
architecture rtl of MY_MUX is
begin
process(in_a,in_b,sel)
begin
if sel = '0' then
output <= in_a;
else
output <= in_b;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- 2_INPUTS MULTIPLEXER (1 bit-wide inputs)
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.cop_definitions.all;
entity SIMPLE_MUX_2 is
port( in_a : in Std_logic;
in_b : in Std_logic;
sel : in Std_logic;
output : out Std_logic );
end SIMPLE_MUX_2;
architecture rtl of SIMPLE_MUX_2 is
begin
process(in_a,in_b,sel)
begin
if sel = '0' then
output <= in_a;
else
output <= in_b;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- REGISTER DELAY CHAIN (ctrl_logic)
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity register_chain is
generic ( length : integer := m;
width : integer := n );
port( clk : in std_logic;
reset : in std_logic;
enable : in Std_logic;
reg_chain_in : in Std_logic_vector(width-1 downto 0);
reg_chain_out : out bus_mxn );
end register_chain;
architecture rtl of register_chain is
signal ctrl_internal_bus : bus_mxn;
begin
ctrl_internal_bus(0) <= reg_chain_in;
WRBCK_DELAY_CHAIN: for i in 0 to (length-1) generate
process(clk, reset)
begin
if reset = reset_active then
ctrl_internal_bus(i+1) <= conv_std_logic_vector(0, width);
elsif CLK'EVENT and CLK='1' then
if enable = we_active then
ctrl_internal_bus(i+1) <= ctrl_internal_bus(i);
end if;
end if;
end process;
end generate WRBCK_DELAY_CHAIN;
reg_chain_out <= ctrl_internal_bus;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- SIMPLE REGISTER DELAY CHAIN
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity simple_register_chain is
generic ( length : integer := m;
width : integer := n );
port( clk : in std_logic;
reset : in std_logic;
enable : in Std_logic;
reg_chain_in : in Std_logic_vector(width-1 downto 0);
reg_chain_out : out Std_logic_vector(width-1 downto 0) );
end simple_register_chain;
architecture rtl of simple_register_chain is
type bus_lengthXwidth is array (length downto 0) of std_logic_vector(width-1 downto 0);
signal ctrl_internal_bus : bus_lengthXwidth;
begin
ctrl_internal_bus(0) <= reg_chain_in;
WRBCK_DELAY_CHAIN: for i in 0 to (length-1) generate
process(clk, reset)
begin
if reset = reset_active then
ctrl_internal_bus(i+1) <= conv_std_logic_vector(0, width);
elsif CLK'EVENT and CLK='1' then
if enable = we_active then
ctrl_internal_bus(i+1) <= ctrl_internal_bus(i);
end if;
end if;
end process;
end generate WRBCK_DELAY_CHAIN;
reg_chain_out <= ctrl_internal_bus(length);
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- FF DELAY CHAIN
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity ff_variable_chain is
generic ( length : integer := m);
port( clk : in std_logic;
reset : in std_logic;
enable : in Std_logic;
ff_chain_in : in Std_logic;
ff_chain_out : out Std_logic_vector(length downto 0) );
end ff_variable_chain;
architecture rtl of ff_variable_chain is
signal ctrl_internal_bus : Std_logic_vector(length downto 0);
begin
ctrl_internal_bus(0) <= ff_chain_in;
VARIABLE_DELAY_CHAIN: for i in 0 to (length-1) generate
process(clk, reset)
begin
if reset = reset_active then
ctrl_internal_bus(i+1) <= '0';
elsif CLK'EVENT and CLK='1' then
if enable = we_active then
ctrl_internal_bus(i+1) <= ctrl_internal_bus(i);
end if;
end if;
end process;
end generate VARIABLE_DELAY_CHAIN;
ff_chain_out <= ctrl_internal_bus;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- SIMPLE FF DELAY CHAIN
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity ff_chain is
generic ( length : integer := m );
port( clk : in std_logic;
reset : in std_logic;
enable : in Std_logic;
ff_chain_in : in Std_logic;
ff_chain_out : out std_logic );
end ff_chain;
architecture rtl of ff_chain is
signal ff_chain_internal_signals : std_logic_vector(length downto 0);
begin
ff_chain_internal_signals(0) <= ff_chain_in;
WRBCK_DELAY_CHAIN: for i in 0 to (length-1) generate
process(clk, reset)
begin
if reset = reset_active then
ff_chain_internal_signals(i+1) <= '0';
elsif CLK'EVENT and CLK='1' then
if enable = we_active then
ff_chain_internal_signals(i+1) <= ff_chain_internal_signals(i);
end if;
end if;
end process;
end generate WRBCK_DELAY_CHAIN;
ff_chain_out <= ff_chain_internal_signals(length);
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- PACKAGE HEADER
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.cop_definitions.all;
package cop_components is
component OE_register
generic(reg_width: Integer := word_width);
port( clk : in Std_logic;
reset : in Std_logic;
we : in Std_logic;
oe : in Std_logic;
data_in : in Std_logic_vector(reg_width-1 downto 0);
data_out : out Std_logic_vector(reg_width-1 downto 0) );
end component;
component WE_register
generic(reg_width: Integer := word_width);
port( clk : in Std_logic;
reset : in Std_logic;
we : in Std_logic;
data_in : in Std_logic_vector(reg_width-1 downto 0);
data_out : out Std_logic_vector(reg_width-1 downto 0) );
end component;
component data_register
generic(reg_width: Integer);
port( clk : in Std_logic;
reset : in Std_logic;
data_in : in Std_logic_vector(reg_width-1 downto 0);
data_out : out Std_logic_vector(reg_width-1 downto 0) );
end component;
component nop_register
generic(reg_width: integer :=word_width);
port(
clk : in Std_logic;
reset : in Std_logic;
data_in : in Std_logic_vector(reg_width-1 downto 0);
data_out : out Std_logic_vector(reg_width-1 downto 0)
);
end component;
component WEDFF
port( clk : in Std_logic;
reset : in Std_logic;
we : in Std_logic;
d : in Std_logic;
q : out Std_logic );
end component;
component data_ff
port( clk : in Std_logic;
reset : in Std_logic;
d : in Std_logic;
q : out Std_logic );
end component;
component data_ff_1
port( clk : in Std_logic;
reset : in Std_logic;
d : in Std_logic;
q : out Std_logic );
end component;
component decoder3_8
port( dec_addr : in std_logic_vector(2 downto 0);
dec_out : out std_logic_vector(7 downto 0) );
end component;
component tristate_buffer
generic(width : integer := buffer_width);
port( tristate_buffer_oe : in std_logic;
tristate_buffer_data_in : in std_logic_vector(buffer_width-1 downto 0);
tristate_buffer_data_out : out std_logic_vector(buffer_width-1 downto 0) );
end component;
component MY_8IN_MUX
generic (width : integer :=word_width);
port( in_a : in Std_logic_vector(width-1 downto 0);
in_b : in Std_logic_vector(width-1 downto 0);
in_c : in Std_logic_vector(width-1 downto 0);
in_d : in Std_logic_vector(width-1 downto 0);
in_e : in Std_logic_vector(width-1 downto 0);
in_f : in Std_logic_vector(width-1 downto 0);
in_g : in Std_logic_vector(width-1 downto 0);
in_h : in Std_logic_vector(width-1 downto 0);
sel : in Std_logic_vector(2 downto 0);
output : out Std_logic_vector(width-1 downto 0) );
end component;
component DELAY_SELECT_MUX
generic (width : integer := 8);
port( in_a : in Std_logic_vector(width-1 downto 0);
in_b : in Std_logic_vector(width-1 downto 0);
in_c : in Std_logic_vector(width-1 downto 0);
in_d : in Std_logic_vector(width-1 downto 0);
in_e : in Std_logic_vector(width-1 downto 0);
in_f : in Std_logic_vector(width-1 downto 0);
in_g : in Std_logic_vector(width-1 downto 0);
in_h : in Std_logic_vector(width-1 downto 0);
sel : in Std_logic_vector(6 downto 0);
output : out Std_logic_vector(width-1 downto 0)
);
end component;
component MY_MUX
generic ( width : integer);
port(in_a : in Std_logic_vector(word_width-1 downto 0);
in_b : in Std_logic_vector(word_width-1 downto 0);
sel : in Std_logic;
output : out Std_logic_vector(word_width-1 downto 0) );
end component;
component SIMPLE_MUX_2
port( in_a : in Std_logic;
in_b : in Std_logic;
sel : in Std_logic;
output : out Std_logic );
end component;
component register_chain
generic ( length : integer := m;
width : integer := n );
port( clk : in std_logic;
reset : in std_logic;
enable : in Std_logic;
reg_chain_in : in Std_logic_vector(n-1 downto 0);
reg_chain_out : out bus_mxn );
end component;
component simple_register_chain
generic ( length : integer := m;
width : integer := n );
port( clk : in std_logic;
reset : in std_logic;
enable : in Std_logic;
reg_chain_in : in Std_logic_vector(width-1 downto 0);
reg_chain_out : out Std_logic_vector(width-1 downto 0) );
end component;
component ff_variable_chain
generic ( length : integer := m);
port( clk : in std_logic;
reset : in std_logic;
enable : in Std_logic;
ff_chain_in : in Std_logic;
ff_chain_out : out Std_logic_vector(length downto 0) );
end component;
component ff_chain
generic ( length : integer := m );
port( clk : in std_logic;
reset : in std_logic;
enable : in Std_logic;
ff_chain_in : in Std_logic;
ff_chain_out : out std_logic );
end component;
end cop_components;
package body cop_components is
end cop_components;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_k3_k4_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_k3_k4_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_k3_k4_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_k3_k4_e
--
architecture rtl of inst_k3_k4_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity opcode_decoder is
PORT( CLK_I : IN std_logic;
T2 : IN std_logic;
CLR : IN std_logic;
CE : IN std_logic;
OPCODE : IN std_logic_vector(7 downto 0);
OP_CYC : IN cycle;
INT : IN std_logic;
RRZ : IN std_logic;
OP_CAT : OUT op_category;
-- select signals
D_SX : out std_logic_vector(1 downto 0); -- ALU select X
D_SY : out std_logic_vector(3 downto 0); -- ALU select Y
D_OP : out std_logic_vector(4 downto 0); -- ALU operation
D_SA : out std_logic_vector(4 downto 0); -- select address
D_SMQ : out std_logic;
-- write enable/select signal
D_WE_RR : out std_logic;
D_WE_LL : out std_logic;
D_WE_M : out std_logic;
D_WE_SP : out SP_OP;
-- input/output
IO_RD : out std_logic;
IO_WR : out std_logic;
PC_OP : out std_logic_vector(2 downto 0);
LAST_M : out std_logic; -- last M cycle of an opcode
HLT : out std_logic
);
end opcode_decoder;
architecture Behavioral of opcode_decoder is
function pc(A : std_logic;
OP : std_logic_vector(2 downto 0)) return std_logic_vector is
begin
if (A = '1') then return OP;
else return PC_NEXT;
end if;
end;
function hadr( A : std_logic;
ADR : std_logic_vector(4 downto 0)) return std_logic_vector is
begin
return ADR(4 downto 1) & A;
end;
function mix(A : std_logic) return std_logic_vector is
begin
if (A = '1') then return ALU_X_MIX_Y;
else return ALU_MOVE_Y;
end if;
end;
function sp(A : std_logic;
OP : SP_OP) return SP_OP is
begin
if (A = '1') then return OP;
else return SP_NOP;
end if;
end;
signal LAST : cycle;
signal ENABLE_INT : std_logic;
signal DISABLE_INT : std_logic;
signal DISABLE_CNT : std_logic_vector(3 downto 0);
signal HALT_REQ : std_logic;
signal UNHALT_REQ : std_logic;
signal HALTED : std_logic;
signal SERVE_INT : std_logic;
signal INT_ACK : std_logic;
begin
LAST_M <= '1' when (OP_CYC = LAST) else '0';
HLT <= HALTED;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (T2 = '1') then
if (CLR = '1') then
DISABLE_CNT <= "0001"; -- 1 x disabled
INT_ACK <= '0';
HALTED <= '0';
elsif (CE = '1') then
if (DISABLE_INT = '1') then
DISABLE_CNT <= DISABLE_CNT + 1;
elsif (ENABLE_INT = '1' and DISABLE_CNT /= 0) then
DISABLE_CNT <= DISABLE_CNT - 1;
end if;
if (UNHALT_REQ = '1') then
HALTED <= '0';
elsif (HALT_REQ = '1') then
HALTED <= '1';
end if;
INT_ACK <= SERVE_INT;
end if;
end if;
end if;
end process;
process(OPCODE, OP_CYC, INT, RRZ, INT_ACK, DISABLE_CNT, HALTED)
variable IS_M1 : std_logic;
variable IS_M2, IS_M1_M2 : std_logic;
variable IS_M3, IS_M2_M3 : std_logic;
variable IS_M4, IS_M3_M4 : std_logic;
variable IS_M5 : std_logic;
begin
if (OP_CYC = M1) then IS_M1 := '1'; else IS_M1 := '0'; end if;
if (OP_CYC = M2) then IS_M2 := '1'; else IS_M2 := '0'; end if;
if (OP_CYC = M3) then IS_M3 := '1'; else IS_M3 := '0'; end if;
if (OP_CYC = M4) then IS_M4 := '1'; else IS_M4 := '0'; end if;
if (OP_CYC = M5) then IS_M5 := '1'; else IS_M5 := '0'; end if;
IS_M1_M2 := IS_M1 or IS_M2;
IS_M2_M3 := IS_M2 or IS_M3;
IS_M3_M4 := IS_M3 or IS_M4;
-- default: NOP
--
OP_CAT <= undef;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_OP <= "00000";
D_SA <= "00000";
D_SMQ <= '0';
D_WE_RR <= '0';
D_WE_LL <= '0';
D_WE_M <= '0';
D_WE_SP <= SP_NOP;
IO_RD <= '0';
IO_WR <= '0';
PC_OP <= PC_NEXT;
LAST <= M1; -- default: single cycle opcode (M1 only)
ENABLE_INT <= '0';
DISABLE_INT <= '0';
HALT_REQ <= '0';
UNHALT_REQ <= '0';
SERVE_INT <= '0';
if ((IS_M1 = '1' and INT = '1' and DISABLE_CNT = "0000") -- new INT or
or INT_ACK = '1' ) then -- continue INT
OP_CAT <= INTR;
LAST <= M2;
SERVE_INT <= IS_M1; -- assert INT_ACK in M2
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY0; -- PC + 0 (current PC)
D_SA <= ADR_dSP;
PC_OP <= pc(IS_M1, PC_INT);
D_WE_M <= IS_M1_M2;
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
DISABLE_INT <= '1';
UNHALT_REQ <= '1';
elsif (HALTED = '1') then
OP_CAT <= HALT_WAIT;
LAST <= M2;
PC_OP <= PC_WAIT;
elsif (OPCODE(7) = '1') then
case OPCODE(6 downto 4) is
when "010" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_UQ;
D_WE_RR <= IS_M1;
when "011" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_UQ;
D_WE_RR <= IS_M1;
when "100" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SQ;
D_WE_RR <= IS_M1;
when "101" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_SQ;
D_WE_RR <= IS_M1; -- !! RR
when "110" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UQ;
D_WE_LL <= IS_M1;
when "111" =>
case OPCODE(3 downto 0) is
when "0100" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "0101" =>
OP_CAT <= ADD_RR_I;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "0110" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "0111" =>
OP_CAT <= SUB_RR_I;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "1000" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3;
when "1001" =>
OP_CAT <= MOVE_I_RR;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_RR <= IS_M2;
when "1010" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_I16;
LAST <= M3;
D_WE_RR <= IS_M3; -- SEQ sets RR !
when "1011" =>
OP_CAT <= SEQ_LL_I;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_RR <= IS_M2; -- SEQ sets RR !
when "1100" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_I16;
LAST <= M3;
D_WE_LL <= IS_M3;
when "1101" =>
OP_CAT <= MOVE_I_LL;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SI8;
LAST <= M2;
D_WE_LL <= IS_M2;
when others => -- undefined
end case;
when others => -- undefined
end case;
else
case OPCODE(6 downto 0) is
-- 00000000000000000000000000000000000000000000000000000000000000000000
when "0000000" =>
OP_CAT <= HALT;
HALT_REQ <= '1';
PC_OP <= PC_WAIT;
when "0000001" =>
OP_CAT <= NOP;
when "0000010" =>
OP_CAT <= JMP_i;
LAST <= M3;
PC_OP <= pc(IS_M2, PC_JMP);
when "0000011" =>
OP_CAT <= JMP_RRNZ_i;
LAST <= M3;
PC_OP <= pc(IS_M2 and not RRZ, PC_JMP);
when "0000100" =>
OP_CAT <= JMP_RRZ_i;
LAST <= M3;
PC_OP <= pc(IS_M2 and RRZ, PC_JMP);
when "0000101" =>
OP_CAT <= CALL_i;
LAST <= M3;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY3; -- PC + 3
D_SA <= ADR_dSP;
PC_OP <= pc(IS_M2, PC_JMP);
D_WE_M <= IS_M1_M2;
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
when "0000110" =>
OP_CAT <= CALL_RR;
LAST <= M2;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_PC;
D_SY <= SY_SY1; -- PC + 1
D_SA <= ADR_dSP;
PC_OP <= pc(IS_M1, PC_JPRR);
D_WE_M <= IS_M1_M2;
D_SMQ <= IS_M1;
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
when "0000111" | "1111000" =>
if (OPCODE(0) = '1') then
OP_CAT <= RET;
else
OP_CAT <= RETI;
ENABLE_INT <= '1';
end if;
LAST <= M5;
D_SA <= ADR_SPi; -- read address: (SP)+
D_WE_SP <= sp(IS_M1_M2, SP_INC);
case OP_CYC is
when M1 => PC_OP <= PC_WAIT;
when M2 => PC_OP <= PC_WAIT;
when M3 => PC_OP <= PC_RETL;
when M4 => PC_OP <= PC_RETH;
when others =>
end case;
when "0001000" =>
OP_CAT <= MOVE_SPi_RR;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
LAST <= M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_WE_RR <= IS_M2_M3;
D_WE_SP <= sp(IS_M1_M2, SP_INC);
D_OP <= mix(IS_M3);
when "0001001" =>
OP_CAT <= MOVE_SPi_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_SPi;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
when "0001010" =>
OP_CAT <= MOVE_SPi_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_RR <= IS_M2;
when "0001011" =>
OP_CAT <= MOVE_SPi_LL;
LAST <= M3;
D_SX <= SX_LL;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_WE_SP <= sp(IS_M1_M2, SP_INC);
D_WE_LL <= IS_M2_M3;
D_OP <= mix(IS_M3);
when "0001100" =>
OP_CAT <= MOVE_SPi_LS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_SPi;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_LL <= IS_M2;
when "0001101" =>
OP_CAT <= MOVE_SPi_LU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_SPi;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1, SP_INC);
D_WE_LL <= IS_M2;
when "0001110" =>
OP_CAT <= MOVE_RR_dSP;
LAST <= M2;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
PC_OP <= pc(IS_M1, PC_WAIT);
D_WE_SP <= sp(IS_M1_M2, SP_LOAD);
D_SMQ <= IS_M1;
D_WE_M <= IS_M1_M2;
when "0001111" =>
OP_CAT <= MOVE_R_dSP;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_SP <= SP_LOAD;
D_WE_M <= '1';
-- 11111111111111111111111111111111111111111111111111111111111111111111
when "0010000" =>
OP_CAT <= AND_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_AND_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010001" =>
OP_CAT <= AND_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_AND_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010010" =>
OP_CAT <= OR_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010011" =>
OP_CAT <= OR_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010100" =>
OP_CAT <= XOR_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010101" =>
OP_CAT <= XOR_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0010110" =>
OP_CAT <= SEQ_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0010111" =>
OP_CAT <= SEQ_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0011000" =>
OP_CAT <= SNE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_NE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011001" =>
OP_CAT <= SNE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_NE_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0011010" =>
OP_CAT <= SGE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_GE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011011" =>
OP_CAT <= SGE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_GE_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0011100" =>
OP_CAT <= SGT_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_GT_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011101" =>
OP_CAT <= SGT_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_GT_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0011110" =>
OP_CAT <= SLE_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LE_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0011111" =>
OP_CAT <= SLE_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LE_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
-- 22222222222222222222222222222222222222222222222222222222222222222222
when "0100000" =>
OP_CAT <= SLT_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LT_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100001" =>
OP_CAT <= SLT_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LT_Y;
D_SX <= SX_RR;
D_SY <= SY_SI8;
D_WE_RR <= IS_M1;
when "0100010" =>
OP_CAT <= SHS_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_HS_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100011" =>
OP_CAT <= SHS_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_HS_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0100100" =>
OP_CAT <= SHI_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_HI_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100101" =>
OP_CAT <= SHI_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_HI_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0100110" =>
OP_CAT <= SLS_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LS_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0100111" =>
OP_CAT <= SLS_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LS_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0101000" =>
OP_CAT <= SLO_RR_i;
LAST <= M3; -- wait for ##
D_OP <= ALU_X_LO_Y;
D_SX <= SX_RR;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "0101001" =>
OP_CAT <= SLO_RR_i;
LAST <= M2; -- wait for #
D_OP <= ALU_X_LO_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "0101010" =>
OP_CAT <= ADD_SP_I;
LAST <= M3; -- wait for ##
D_OP <= ALU_ANY;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_SA <= ADR_16SP_L;
D_WE_SP <= sp(IS_M2, SP_LOAD);
when "0101011" =>
OP_CAT <= ADD_SP_I;
LAST <= M2; -- wait for #
D_OP <= ALU_ANY;
D_SX <= SX_ANY;
D_SY <= SY_ANY;
D_SA <= ADR_8SP_L;
D_WE_SP <= sp(IS_M1, SP_LOAD);
when "0101100" =>
OP_CAT <= CLRW_dSP;
LAST <= M2;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_ANY;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_SP <= SP_LOAD;
D_WE_M <= '1';
PC_OP <= pc(IS_M1, PC_WAIT);
when "0101101" =>
OP_CAT <= CLRB_dSP;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_ANY;
D_SY <= SY_SY0;
D_SA <= ADR_dSP;
D_WE_SP <= SP_LOAD;
D_WE_M <= IS_M1;
when "0101110" =>
OP_CAT <= IN_ci_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_IO;
D_SA <= ADR_IO;
IO_RD <= IS_M2;
D_WE_RR <= IS_M2;
when "0101111" =>
OP_CAT <= OUT_R_ci;
LAST <= M2;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_IO;
IO_WR <= IS_M2;
-- 33333333333333333333333333333333333333333333333333333333333333333333
when "0110000" =>
OP_CAT <= AND_LL_RR;
D_OP <= ALU_X_AND_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110001" =>
OP_CAT <= OR_LL_RR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110010" =>
OP_CAT <= XOR_LL_RR;
D_OP <= ALU_X_XOR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110011" =>
OP_CAT <= SEQ_LL_RR;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110100" =>
OP_CAT <= SNE_LL_RR;
D_OP <= ALU_X_NE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110101" =>
OP_CAT <= SGE_LL_RR;
D_OP <= ALU_X_GE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110110" =>
OP_CAT <= SGT_LL_RR;
D_OP <= ALU_X_GT_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0110111" =>
OP_CAT <= SLE_LL_RR;
D_OP <= ALU_X_LE_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111000" =>
OP_CAT <= SLT_LL_RR;
D_OP <= ALU_X_LT_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111001" =>
OP_CAT <= SHS_LL_RR;
D_OP <= ALU_X_HS_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111010" =>
OP_CAT <= SHI_LL_RR;
D_OP <= ALU_X_HI_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111011" =>
OP_CAT <= SLS_LL_RR;
D_OP <= ALU_X_LS_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111100" =>
OP_CAT <= SLO_LL_RR;
D_OP <= ALU_X_LO_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111101" =>
OP_CAT <= LNOT_RR;
D_OP <= ALU_X_EQ_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_WE_RR <= IS_M1;
when "0111110" =>
OP_CAT <= NEG_RR;
D_OP <= ALU_NEG_Y;
D_SX <= SX_ANY;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "0111111" =>
OP_CAT <= NOT_RR;
D_OP <= ALU_NOT_Y;
D_SX <= SX_ANY;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
-- 44444444444444444444444444444444444444444444444444444444444444444444
when "1000000" =>
OP_CAT <= MOVE_LL_RR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_WE_RR <= IS_M1;
when "1000001" =>
OP_CAT <= MOVE_LL_cRR;
LAST <= M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_SA <= hadr(IS_M2, ADR_cRR_H);
D_SMQ <= IS_M2;
D_WE_M <= IS_M1_M2;
when "1000010" =>
OP_CAT <= MOVE_L_cRR;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_LL;
D_SY <= SY_SY0;
D_SA <= ADR_cRR_L;
D_WE_M <= IS_M1;
when "1000011" =>
OP_CAT <= MOVE_RR_LL;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_WE_LL <= IS_M1;
when "1000100" =>
OP_CAT <= MOVE_RR_cLL;
LAST <= M2;
PC_OP <= pc(IS_M1, PC_WAIT);
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= hadr(IS_M2, ADR_cLL_H);
D_SMQ <= IS_M2;
D_WE_M <= IS_M1_M2;
when "1000101" =>
OP_CAT <= MOVE_R_cLL;
D_OP <= ALU_X_OR_Y;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_SA <= ADR_cLL_L;
D_WE_M <= IS_M1;
when "1000110" =>
OP_CAT <= MOVE_cRR_RR;
LAST <= M3;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_WE_RR <= not IS_M1; -- M2 or M3
PC_OP <= pc(IS_M1_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_SA <= hadr(IS_M2, ADR_cRR_H);
when "1000111" =>
OP_CAT <= MOVE_cRR_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cRR_L;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
when "1001000" =>
OP_CAT <= MOVE_cRR_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cRR_L;
D_WE_RR <= IS_M2;
PC_OP <= pc(IS_M1, PC_WAIT);
when "1001001" =>
OP_CAT <= MOVE_ci_RR;
LAST <= M4;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_WE_RR <= IS_M3_M4;
D_SA <= hadr(IS_M3, ADR_cI16_H);
when "1001010" =>
OP_CAT <= MOVE_ci_RS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cI16_L;
D_WE_RR <= IS_M3;
when "1001011" =>
OP_CAT <= MOVE_ci_RU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cI16_L;
D_WE_RR <= IS_M3;
when "1001100" =>
OP_CAT <= MOVE_ci_LL;
LAST <= M4;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_SA <= hadr(IS_M3, ADR_cI16_H);
D_WE_LL <= IS_M3_M4;
when "1001101" =>
OP_CAT <= MOVE_ci_LS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_SM;
D_SA <= ADR_cI16_L;
D_WE_LL <= IS_M3;
when "1001110" =>
OP_CAT <= MOVE_ci_LU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_cI16_L;
D_WE_LL <= IS_M3;
when "1001111" =>
OP_CAT <= MOVE_RR_SP;
D_SA <= ADR_cRR_L;
D_WE_SP <= SP_LOAD;
-- 55555555555555555555555555555555555555555555555555555555555555555555
when "1010000" =>
-- spare
when "1010001" =>
-- spare
when "1010010" =>
OP_CAT <= LSL_RR_i;
LAST <= M2;
D_OP <= ALU_X_LSL_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010011" =>
OP_CAT <= ASR_RR_i;
LAST <= M2;
D_OP <= ALU_X_ASR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010100" =>
OP_CAT <= LSR_RR_i;
LAST <= M2;
D_OP <= ALU_X_LSR_Y;
D_SX <= SX_RR;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1010101" =>
OP_CAT <= LSL_LL_RR;
D_OP <= ALU_X_LSL_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1010110" =>
OP_CAT <= ASR_LL_RR;
D_OP <= ALU_X_ASR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1010111" =>
OP_CAT <= LSR_LL_RR;
D_OP <= ALU_X_LSR_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011000" =>
OP_CAT <= ADD_LL_RR;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011001" =>
OP_CAT <= SUB_LL_RR;
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1011010" =>
OP_CAT <= MOVE_RR_ci;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_WE_M <= not IS_M1; -- M2 or M3
D_SA <= hadr(IS_M3, ADR_cI16_H);
D_SMQ <= IS_M3;
when "1011011" =>
OP_CAT <= MOVE_R_ci;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_WE_M <= IS_M2;
D_SA <= ADR_cI16_L;
when "1011100" => -- long offset / long move
OP_CAT <= MOVE_RR_uSP;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_WE_M <= not IS_M1;
D_SMQ <= IS_M3;
D_SA <= hadr(IS_M3, ADR_16SP_H);
when "1011101" => -- short offset / long move
OP_CAT <= MOVE_RR_uSP;
LAST <= M2;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_WE_M <= IS_M1_M2;
D_SMQ <= IS_M2;
D_SA <= hadr(IS_M2, ADR_8SP_H);
when "1011110" => -- long offset / short move
OP_CAT <= MOVE_R_uSP;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_WE_M <= IS_M2;
D_OP <= ALU_X_OR_Y;
D_SA <= ADR_16SP_L;
when "1011111" => -- short offset / short move
OP_CAT <= MOVE_R_uSP;
LAST <= M2;
D_SX <= SX_RR;
D_SY <= SY_SY0;
D_OP <= ALU_X_OR_Y;
D_WE_M <= IS_M1;
D_OP <= ALU_X_OR_Y;
D_SA <= ADR_8SP_L;
-- 66666666666666666666666666666666666666666666666666666666666666666666
when "1100000" => -- long offset, long move
OP_CAT <= MOVE_uSP_RR;
LAST <= M4;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M3_M4);
D_WE_RR <= IS_M3_M4;
D_SA <= hadr(IS_M3, ADR_16SP_H);
when "1100001" => -- short offset, long move
OP_CAT <= MOVE_uSP_RR;
LAST <= M3;
D_SX <= SX_RR;
D_SY <= SY_UM;
PC_OP <= pc(IS_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_WE_RR <= IS_M2_M3;
D_SA <= hadr(IS_M2, ADR_8SP_H);
when "1100010" => -- long offset, short move
OP_CAT <= MOVE_uSP_RS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_16SP_L;
D_WE_RR <= IS_M3;
when "1100011" => -- short offset, short move
OP_CAT <= MOVE_uSP_RS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_8SP_L;
D_WE_RR <= IS_M2;
when "1100100" => -- long offset, short move
OP_CAT <= MOVE_uSP_RU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_16SP_L;
D_WE_RR <= IS_M3;
when "1100101" => -- short offset, short move
OP_CAT <= MOVE_uSP_RU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_8SP_L;
D_WE_RR <= IS_M2;
when "1100110" => -- long offset, long move
OP_CAT <= MOVE_uSP_LL;
LAST <= M4;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M3, PC_WAIT);
D_OP <= mix(IS_M4);
D_WE_LL <= IS_M3_M4;
D_SA <= hadr(IS_M3, ADR_8SP_H);
when "1100111" => -- short offset, long move
OP_CAT <= MOVE_uSP_LL;
LAST <= M3;
D_SX <= SX_LL;
D_SY <= SY_UM;
PC_OP <= pc(IS_M2, PC_WAIT);
D_OP <= mix(IS_M3);
D_WE_LL <= IS_M2_M3;
D_SA <= hadr(IS_M2, ADR_8SP_H);
when "1101000" => -- long offset, short move
OP_CAT <= MOVE_uSP_LS;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_16SP_L;
D_WE_LL <= IS_M3;
when "1101001" => -- short offset, short move
OP_CAT <= MOVE_uSP_LS;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_SM;
D_SA <= ADR_8SP_L;
D_WE_LL <= IS_M2;
when "1101010" => -- long offset, short move
OP_CAT <= MOVE_uSP_LU;
LAST <= M3;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_16SP_L;
D_WE_LL <= IS_M3;
when "1101011" => -- short offset, short move
OP_CAT <= MOVE_uSP_LU;
LAST <= M2;
D_OP <= ALU_MOVE_Y;
D_SX <= SX_RR;
D_SY <= SY_UM;
D_SA <= ADR_8SP_L;
D_WE_LL <= IS_M2;
when "1101100" =>
OP_CAT <= LEA_uSP_RR;
LAST <= M3;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_SP;
D_SY <= SY_I16;
D_WE_RR <= IS_M2;
when "1101101" =>
OP_CAT <= LEA_uSP_RR;
LAST <= M2;
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_SP;
D_SY <= SY_UI8;
D_WE_RR <= IS_M1;
when "1101110" =>
OP_CAT <= MOVE_dRR_dLL;
LAST <= M3;
D_WE_RR <= IS_M1;
D_WE_M <= IS_M2;
D_WE_LL <= IS_M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
case OP_CYC is
when M1 => -- decrement RR
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_RR;
D_SY <= SY_SY1;
D_SA <= ADR_dRR;
when M2 => -- write read memory
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_dLL;
when others => -- decrement LL
D_OP <= ALU_X_SUB_Y;
D_SX <= SX_LL;
D_SY <= SY_SY1;
end case;
when "1101111" =>
OP_CAT <= MOVE_RRi_LLi;
LAST <= M3;
D_WE_RR <= IS_M1;
D_WE_M <= IS_M2;
D_WE_LL <= IS_M3;
PC_OP <= pc(IS_M1_M2, PC_WAIT);
case OP_CYC is
when M1 => -- decrement RR
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_RR;
D_SY <= SY_SY1;
D_SA <= ADR_RRi;
when M2 => -- write read memory
D_OP <= ALU_MOVE_Y;
D_SX <= SX_ANY;
D_SY <= SY_UM;
D_SA <= ADR_dLL;
when others => -- decrement LL
D_OP <= ALU_X_ADD_Y;
D_SX <= SX_LL;
D_SY <= SY_SY1;
end case;
-- 77777777777777777777777777777777777777777777777777777777777777777777
when "1110000" =>
OP_CAT <= MUL_IS;
D_OP <= ALU_MUL_IS;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110001" =>
OP_CAT <= MUL_IU;
D_OP <= ALU_MUL_IU;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110010" =>
OP_CAT <= DIV_IS;
D_OP <= ALU_DIV_IS;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110011" =>
OP_CAT <= DIV_IU;
D_OP <= ALU_DIV_IU;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110100" =>
OP_CAT <= MD_STEP;
D_OP <= ALU_MD_STP;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110101" =>
OP_CAT <= MD_FIN;
D_OP <= ALU_MD_FIN;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110110" =>
OP_CAT <= MOD_FIN;
D_OP <= ALU_MOD_FIN;
D_SX <= SX_LL;
D_SY <= SY_RR;
D_WE_RR <= IS_M1;
when "1110111" =>
OP_CAT <= EI;
ENABLE_INT <= '1';
when "1111001" =>
OP_CAT <= DI;
DISABLE_INT <= '1';
-- undefined --------------------------------------------------------
when others =>
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: madd - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
-- calculates a*b+c
entity madd is -- latency = mul core latency + 1 if add incl
generic (
MUL_LATENCY : integer := 3;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
INCLUDE_ADD : boolean := false;
C_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
c : in std_logic_vector(C_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end madd;
architecture Behavioral of madd is
constant INT_BITWIDTH : integer := A_BITWIDTH+B_BITWIDTH+1;
type data_delay_type is array(0 to MUL_LATENCY-1) of std_logic_vector(C_BITWIDTH-1 downto 0);
function sext(val : std_logic_vector; length : integer) return std_logic_vector is
variable val_msb : std_logic;
variable result : std_logic_vector(length-1 downto 0);
begin
val_msb := val(val'length-1);
result(val'length-1 downto 0) := val;
result(length-1 downto val'length) := (others => val_msb);
return result;
end sext;
component mul
port (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(A_BITWIDTH-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(B_BITWIDTH DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(A_BITWIDTH+B_BITWIDTH-1 DOWNTO 0)
);
end component;
component addorsub is
generic (
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
signal tmp_pout : std_logic_vector(A_BITWIDTH+B_BITWIDTH-1 downto 0);
signal pout : std_logic_vector(INT_BITWIDTH-1 downto 0);
signal summand_1 : signed(INT_BITWIDTH-1 downto 0);
signal summand_2 : signed(INT_BITWIDTH-1 downto 0);
signal sum_reg : signed(INT_BITWIDTH-1 downto 0);
signal delay_line : std_logic_vector(0 to MUL_LATENCY+1-1);
signal data_delay_line : data_delay_type;
begin
-- compensate mul latency
delay_line_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
delay_line <= (others => '0');
else
delay_line(0) <= nd;
delay_line(1 to MUL_LATENCY+1-1) <= delay_line(0 to MUL_LATENCY+1-2);
end if;
end if;
end process delay_line_proc;
G_N_ADD : if INCLUDE_ADD = false generate
mul_inst : mul
port map (
clk => clk,
a => a,
b => b,
p => tmp_pout
);
pout <= sext(tmp_pout,INT_BITWIDTH);
res <= pout(INT_BITWIDTH-1 downto INT_BITWIDTH-RES_BITWIDTH);
rdy <= delay_line(MUL_LATENCY-1);
end generate G_N_ADD;
G_ADD : if INCLUDE_ADD = true generate
mul_inst : mul
port map (
clk => clk,
a => a,
b => b,
p => tmp_pout
);
data_delay_proc : process(clk)
begin
if rising_edge(clk) then
data_delay_line(0) <= c;
data_delay_line(1 to MUL_LATENCY-1) <= data_delay_line(0 to MUL_LATENCY-2);
end if;
end process data_delay_proc;
summand_1 <= signed(sext(data_delay_line(MUL_LATENCY-1),INT_BITWIDTH));
summand_2 <= signed(sext(tmp_pout,INT_BITWIDTH));
sum_reg_proc : process(clk)
begin
if rising_edge(clk) then
sum_reg <= summand_1 + summand_2;
end if;
end process sum_reg_proc;
-- addorsub_inst : addorsub
-- generic map(
-- A_BITWIDTH => A_BITWIDTH+B_BITWIDTH,
-- B_BITWIDTH => C_BITWIDTH,
-- RES_BITWIDTH => INT_BITWIDTH
-- )
-- port map (
-- clk => clk,
-- sclr => sclr,
-- nd => delay_line(MUL_LATENCY-1),
-- sub => '0',
-- a => tmp_pout,
-- b => data_delay_line(MUL_LATENCY-1),
-- res => pout,
-- rdy => rdy
-- );
--
res <= std_logic_vector(sum_reg(INT_BITWIDTH-1 downto INT_BITWIDTH-RES_BITWIDTH));
rdy <= delay_line(MUL_LATENCY+1-1);
end generate G_ADD;
end Behavioral;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:30:38)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir1_hype_entity;
ARCHITECTURE fir1_hype_description OF fir1_hype_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 and input1;
register2 := input2 and input2;
register3 := input3 and input3;
WHEN "00000010" =>
register2 := register2 * register3;
register3 := input4 and input4;
register4 := input5 and input5;
register5 := input6 and input6;
register6 := input7 and input7;
WHEN "00000011" =>
register4 := register4 * register6;
register6 := input8 and input8;
register7 := input9 and input9;
register8 := input10 and input10;
register9 := input11 and input11;
register10 := input12 and input12;
register3 := register3 * register5;
WHEN "00000100" =>
register5 := register9 * register6;
register6 := input13 and input13;
register1 := register1 * register10;
register2 := register2 + register3;
register3 := register7 * register8;
register7 := input14 and input14;
register8 := input15 and input15;
WHEN "00000101" =>
register7 := register8 * register7;
register3 := register4 + register3;
register4 := input16 and input16;
WHEN "00000110" =>
register4 := register4 * register6;
register6 := input17 and input17;
register8 := input18 and input18;
register9 := input19 and input19;
register1 := register5 + register1;
register2 := register2 + register7;
register5 := input20 and input20;
WHEN "00000111" =>
register5 := register8 * register5;
register6 := register6 * register9;
register7 := input21 and input21;
register8 := input22 and input22;
WHEN "00001000" =>
register7 := register7 * register8;
WHEN "00001001" =>
register2 := register7 + register2;
WHEN "00001010" =>
register1 := register1 + register2;
WHEN "00001011" =>
register1 := register1 + register6;
WHEN "00001100" =>
register1 := register3 + register1;
WHEN "00001101" =>
register1 := register1 + register4;
WHEN "00001110" =>
register1 := register5 + register1;
WHEN "00001111" =>
output1 <= register1 and register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir1_hype_description; |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_10.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_03_10 is
end entity test_bench_03_10;
architecture test_edge_triggered_register_check_timing of test_bench_03_10 is
signal clock : bit := '0';
signal d_in, d_out : real := 0.0;
begin
dut : entity work.edge_triggered_register(check_timing)
port map ( clock => clock, d_in => d_in, d_out => d_out );
stumulus : process is
begin
wait for 20 ns;
d_in <= 1.0; wait for 10 ns;
clock <= '1', '0' after 10 ns; wait for 20 ns;
d_in <= 2.0; wait for 10 ns;
clock <= '1', '0' after 5 ns; wait for 20 ns;
d_in <= 3.0; wait for 10 ns;
clock <= '1', '0' after 4 ns; wait for 20 ns;
wait;
end process stumulus;
end architecture test_edge_triggered_register_check_timing;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_10.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_03_10 is
end entity test_bench_03_10;
architecture test_edge_triggered_register_check_timing of test_bench_03_10 is
signal clock : bit := '0';
signal d_in, d_out : real := 0.0;
begin
dut : entity work.edge_triggered_register(check_timing)
port map ( clock => clock, d_in => d_in, d_out => d_out );
stumulus : process is
begin
wait for 20 ns;
d_in <= 1.0; wait for 10 ns;
clock <= '1', '0' after 10 ns; wait for 20 ns;
d_in <= 2.0; wait for 10 ns;
clock <= '1', '0' after 5 ns; wait for 20 ns;
d_in <= 3.0; wait for 10 ns;
clock <= '1', '0' after 4 ns; wait for 20 ns;
wait;
end process stumulus;
end architecture test_edge_triggered_register_check_timing;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_10.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_03_10 is
end entity test_bench_03_10;
architecture test_edge_triggered_register_check_timing of test_bench_03_10 is
signal clock : bit := '0';
signal d_in, d_out : real := 0.0;
begin
dut : entity work.edge_triggered_register(check_timing)
port map ( clock => clock, d_in => d_in, d_out => d_out );
stumulus : process is
begin
wait for 20 ns;
d_in <= 1.0; wait for 10 ns;
clock <= '1', '0' after 10 ns; wait for 20 ns;
d_in <= 2.0; wait for 10 ns;
clock <= '1', '0' after 5 ns; wait for 20 ns;
d_in <= 3.0; wait for 10 ns;
clock <= '1', '0' after 4 ns; wait for 20 ns;
wait;
end process stumulus;
end architecture test_edge_triggered_register_check_timing;
|
--! Comment 1
library ieee;
--! Comment 1.5
use ieee.std_logic_1164.all;
--! Comment 2
library ieee;
--! Comment 2.5
use ieee.std_logic_1164.all;
--! Comment 3
--! Comment 3.5
use ieee.std_logic_1164.all;
--! Comment 4
--! Comment 5
architecture rtl of fifo is
begin
some_label : case D_DEPTH generate
-- When comment
-- When comment
when 0 =>
-- Comment 10
b <= 0;
-- When Comment 2
-- When Comment 2
when 1 =>
end generate some_label;
end architecture rtl;
|
-- $Id$
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: avmb_dummy - syn
-- Description: avmb minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_avmb
-- Target Devices: generic
-- Tool versions: xst 13.4; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-02-24 ??? Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity avmb_fusp_dummy is -- AvnetMB dummy (base+fusp; loopback)
-- implements avmb_fusp_aif
port (
I_CLK40 : in slbit; -- 40 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- mb switches
I_BTN : in slv1; -- mb button
O_LED : out slv4; -- mb leds
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end avmb_fusp_dummy;
architecture syn of avmb_fusp_dummy is
begin
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
entity repro01 is
port (a, b, c : in std_logic;
z : out std_logic);
end repro01;
architecture behav of repro01 is
subtype logic is std_logic;
type my_rec is record
a : std_logic_vector(7 downto 0);
end record;
subtype my_rec2 is my_rec;
begin
process(A, B, C)
variable temp : logic;
begin
temp := A and B;
Z <= temp or C;
end process;
end behav;
|
-------------------------------------------------------------------------------
--
-- The Port 1 unit.
-- Implements the Port 1 logic.
--
-- $Id: p1.vhd,v 1.5 2005-06-11 10:08:43 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t48_pack.word_t;
entity t48_p1 is
port (
-- Global Interface -------------------------------------------------------
clk_i : in std_logic;
res_i : in std_logic;
en_clk_i : in boolean;
-- T48 Bus Interface ------------------------------------------------------
data_i : in word_t;
data_o : out word_t;
write_p1_i : in boolean;
read_p1_i : in boolean;
read_reg_i : in boolean;
-- Port 1 Interface -------------------------------------------------------
p1_i : in word_t;
p1_o : out word_t;
p1_low_imp_o : out std_logic
);
end t48_p1;
use work.t48_pack.clk_active_c;
use work.t48_pack.res_active_c;
use work.t48_pack.bus_idle_level_c;
architecture rtl of t48_p1 is
-- the port output register
signal p1_q : word_t;
-- the low impedance marker
signal low_imp_q : std_logic;
begin
-----------------------------------------------------------------------------
-- Process p1_reg
--
-- Purpose:
-- Implements the port output register.
--
p1_reg: process (res_i, clk_i)
begin
if res_i = res_active_c then
p1_q <= (others => '1');
low_imp_q <= '0';
elsif clk_i'event and clk_i = clk_active_c then
if en_clk_i then
if write_p1_i then
p1_q <= data_i;
low_imp_q <= '1';
else
low_imp_q <= '0';
end if;
end if;
end if;
end process p1_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process p1_data
--
-- Purpose:
-- Generates the T48 bus data.
--
p1_data: process (read_p1_i,
p1_i,
read_reg_i,
p1_q)
begin
data_o <= (others => bus_idle_level_c);
if read_p1_i then
if read_reg_i then
data_o <= p1_q;
else
data_o <= p1_i;
end if;
end if;
end process p1_data;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping.
-----------------------------------------------------------------------------
p1_o <= p1_q;
p1_low_imp_o <= low_imp_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2004/07/11 16:51:33 arniml
-- cleanup copyright notice
--
-- Revision 1.3 2004/05/17 14:37:53 arniml
-- reorder data_o generation
--
-- Revision 1.2 2004/03/29 19:39:58 arniml
-- rename pX_limp to pX_low_imp
--
-- Revision 1.1 2004/03/23 21:31:52 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- W I S H B O N E V A R I A B L E F R E Q U E N C Y D I V I D E R
-- (wb_fdiv.vhd)
--
-- @author Simon Gansen
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.interfaces.all;
use work.constants.all;
-------------------------------------------------------------------------------
entity wb_fdiv is
-------------------------------------------------------------------------------
generic (
USER_CLK : Boolean := false
);
port (
-- wishbone
wbs_in : in wbs_in_type;
wbs_out : out wbs_out_type;
-- user pins
clk_in : in std_logic := '-'; -- optional alternative clock input
clk_out : out std_logic
);
end wb_fdiv;
-------------------------------------------------------------------------------
architecture mixed of wb_fdiv is
-------------------------------------------------------------------------------
signal divide_s : std_logic_vector(WB_DW-1 downto 0);
signal raw_clk_s : std_logic;
signal div_clk_s : std_logic;
begin
-- select raw clock using USER_CLK generic
raw_clk_s <= clk_in when USER_CLK else wbs_in.clk;
----------------------------------------------------------------------------
WISHBONE_SLAVE : entity work.wbs_single_reg
----------------------------------------------------------------------------
port map (
wbs_in => wbs_in,
wbs_out => wbs_out,
register_out => divide_s
);
----------------------------------------------------------------------------
FDIV : process(divide_s, raw_clk_s)
----------------------------------------------------------------------------
variable cnt : integer range 0 to 255 := 0;
variable cmp : integer range 0 to 255;
begin
cmp := to_integer(unsigned(divide_s));
-- clk_out is deactivated when divider is 0
if (cmp = 0) then
div_clk_s <= '0';
-- decrement cmp since counting from 0
cmp := cmp - 1;
-- toggle clk_out when cnt reaches cmp
elsif (rising_edge(raw_clk_s)) then
if (cnt < cmp) then
cnt := cnt + 1;
else
div_clk_s <= not div_clk_s;
cnt := 0;
end if;
end if;
end process FDIV;
----------------------------------------------------------------------------
CLK_OUT_BUFFER : BUFG
----------------------------------------------------------------------------
port map (
O => clk_out,
I => div_clk_s
);
end mixed;
|
------------------------------------------------------------------------------
--
-- This vhdl module is a template for creating IP testbenches using the IBM
-- BFM toolkits. It provides a fixed interface to the subsystem testbench.
--
-- DO NOT CHANGE THE entity name, architecture name, generic parameter
-- declaration or port declaration of this file. You may add components,
-- instances, constants, signals, etc. as you wish.
--
-- See IBM Bus Functional Model Toolkit User's Manual for more information
-- on the BFMs.
--
------------------------------------------------------------------------------
-- xps_osif_tb.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: xps_osif_tb.vhd
-- Version: 2.01.a
-- Description: IP testbench
-- Date: Thu Jul 23 14:47:35 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library xps_osif_v2_01_a;
library burst_ram_v2_01_a;
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity xps_osif_tb is
------------------------------------------
-- DO NOT CHANGE THIS GENERIC DECLARATION
------------------------------------------
generic
(
C_FIFO_DWIDTH : natural := 32;
C_DCR_BASEADDR : std_logic_vector := "0000000000";
C_DCR_HIGHADDR : std_logic_vector := "0000000011";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_REGISTER_OSIF_PORTS : integer := 1; -- route OSIF ports through registers
C_DCR_ILA : integer := 0; -- 0: no debug ILA, 1: include debug chipscope ILA for DCR debugging
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 64;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
);
------------------------------------------
-- DO NOT CHANGE THIS PORT DECLARATION
------------------------------------------
port
(
-- PLB (v4.6) bus interface, do not add or delete
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- BFM synchronization bus interface
SYNCH_IN : in std_logic_vector(0 to 31) := (others => '0');
SYNCH_OUT : out std_logic_vector(0 to 31) := (others => '0')
);
end entity xps_osif_tb;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture testbench of xps_osif_tb is
--USER testbench signal declarations added here as you wish
------------------------------------------
-- Signal to hook up master detected error and synch bus
------------------------------------------
signal sig_dev_mderr : std_logic;
------------------------------------------
-- Standard constants for bfl/vhdl communication
------------------------------------------
constant NOP : integer := 0;
constant START : integer := 1;
constant STOP : integer := 2;
constant WAIT_IN : integer := 3;
constant WAIT_OUT : integer := 4;
constant ASSERT_IN : integer := 5;
constant ASSERT_OUT : integer := 6;
constant ASSIGN_IN : integer := 7;
constant ASSIGN_OUT : integer := 8;
constant RESET_WDT : integer := 9;
constant MST_ERROR : integer := 30;
constant INTERRUPT : integer := 31;
signal PLB_Clk : std_logic;
signal PLB_Rst : std_logic;
signal busy_local : std_logic;
signal task_interrupt : std_logic;
signal task_busy : std_logic;
signal task_blocking : std_logic;
signal task_clk : std_logic;
signal task_reset : std_logic;
signal task_os2task_vec : std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
signal task_os2task_vec_i : std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
signal task_task2os_vec : std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
signal task_os2task : osif_os2task_t;
signal task_task2os : osif_task2os_t;
signal burstAddr : std_logic_vector(0 to 13);
signal burstWrData : std_logic_vector(0 to 63);
signal burstRdData : std_logic_vector(0 to 63);
signal burstWE : std_logic;
signal burstBE : std_logic_vector(0 to 7);
signal task2burst_Addr : std_logic_vector(0 to 11);
signal task2burst_Data : std_logic_vector(0 to 31);
signal burst2task_Data : std_logic_vector(0 to 31);
signal task2burst_WE : std_logic;
signal VDEC_YCrCb : std_logic_vector(9 downto 2);
signal VDEC_LLC : std_logic;
signal VDEC_Rst : std_logic;
signal VDEC_OE : std_logic;
signal VDEC_PwrDn : std_logic;
---------
-- FIFO control and data lines
---------
signal fifo_clk : std_logic;
signal fifo_reset : std_logic;
signal fifo_read_remove : std_logic;
signal fifo_read_data : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifo_read_ready : std_logic;
signal fifo_write_add : std_logic;
signal fifo_write_data : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifo_write_ready : std_logic;
-- for simulation
signal fifo_read_add : std_logic;
signal fifo_read_datain : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifo_read_empty : std_logic;
signal fifo_read_full : std_logic;
signal fifo_read_valid : std_logic;
signal fifo_write_remove : std_logic;
signal fifo_write_dataout : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifo_write_empty : std_logic;
signal fifo_write_full : std_logic;
signal fifo_write_valid : std_logic;
---------
-- DCR stimuli
---------
signal dcrAck : std_logic;
signal dcrDBus_in : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal dcrABus : std_logic_vector(0 to C_DCR_AWIDTH-1);
signal dcrDBus_out : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal dcrRead : std_logic;
signal dcrWrite : std_logic;
signal dcrICON : std_logic_vector(35 downto 0); -- chipscope
constant C_GND_TASK_DATA : std_logic_vector(0 to 31) := (others => '0');
constant C_GND_TASK_ADDR : std_logic_vector(0 to 11) := (others => '0');
begin
------------------------------------------
-- Instance of IP under test.
-- Communication with the BFL is by using SYNCH_IN/SYNCH_OUT signals.
------------------------------------------
UUT : entity xps_osif_v2_01_a.xps_osif
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
C_BURST_AWIDTH => 14,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_FAMILY => C_FAMILY,
C_DCR_BASEADDR => C_DCR_BASEADDR,
C_DCR_HIGHADDR => C_DCR_HIGHADDR,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
C_DCR_ILA => C_DCR_ILA,
C_MPLB_AWIDTH =>C_MPLB_AWIDTH,
C_MPLB_DWIDTH =>C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH =>C_MPLB_NATIVE_DWIDTH,
C_MPLB_P2P =>C_MPLB_P2P,
C_MPLB_SMALLEST_SLAVE =>C_MPLB_SMALLEST_SLAVE,
C_MPLB_CLK_PERIOD_PS =>C_MPLB_CLK_PERIOD_PS
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
interrupt => task_interrupt,
busy => task_busy,
blocking => task_blocking,
-- task interface
task_clk => task_clk,
task_reset => task_reset,
osif_os2task_vec => task_os2task_vec,
osif_task2os_vec => task_task2os_vec,
-- burst mem interface
burstAddr => burstAddr,
burstWrData => burstWrData,
burstRdData => burstRdData,
burstWE => burstWE,
burstBE => burstBE,
-- "real" FIFO access signals
fifo_clk => fifo_clk,
fifo_reset => fifo_reset,
fifo_read_en => fifo_read_remove,
fifo_read_data => fifo_read_data,
fifo_read_ready => fifo_read_ready,
fifo_write_en => fifo_write_add,
fifo_write_data => fifo_write_data,
fifo_write_ready => fifo_write_ready,
-- MAP USER PORTS ABOVE THIS LINE ------------------
o_dcrAck => dcrAck,
o_dcrDBus => dcrDBus_in,
i_dcrABus => dcrABus,
i_dcrDBus => dcrDBus_out,
i_dcrRead => dcrRead,
i_dcrWrite => dcrWrite,
i_dcrICON => dcrICON,
-- sys_clk => PLB_Clk,
-- sys_reset => PLB_Rst,
-- SPLB_Clk => SPLB_Clk,
-- SPLB_Rst => SPLB_Rst ,
-- PLB_ABus => PLB_ABus,
-- PLB_UABus => PLB_UABus,
-- PLB_PAValid => PLB_PAValid,
-- PLB_SAValid => PLB_SAValid,
-- PLB_rdPrim => PLB_rdPrim,
-- PLB_wrPrim => PLB_wrPrim,
-- PLB_masterID => PLB_masterID,
-- PLB_abort => PLB_abort,
-- PLB_busLock => PLB_busLock,
-- PLB_RNW => PLB_RNW,
-- PLB_BE => PLB_BE,
-- PLB_MSize => PLB_MSize,
-- PLB_size => PLB_size ,
-- PLB_type => PLB_type,
-- PLB_lockErr => PLB_lockErr,
-- PLB_wrDBus => PLB_wrDBus,
-- PLB_wrBurst => PLB_wrBurst,
-- PLB_rdBurst => PLB_rdBurst,
-- PLB_wrPendReq => PLB_wrPendReq,
-- PLB_rdPendReq => PLB_rdPendReq,
-- PLB_wrPendPri => PLB_wrPendPri,
-- PLB_rdPendPri => PLB_rdPendPri,
-- PLB_reqPri => PLB_reqPri,
-- PLB_TAttribute => PLB_TAttribute,
-- Sl_addrAck => Sl_addrAck,
-- Sl_SSize => Sl_SSize,
-- Sl_wait => Sl_wait,
-- Sl_rearbitrate => Sl_rearbitrate,
-- Sl_wrDAck => Sl_wrDAck,
-- Sl_wrComp => Sl_wrComp,
-- Sl_wrBTerm => Sl_wrBTerm,
-- Sl_rdDBus => Sl_rdDBus,
-- Sl_rdWdAddr => Sl_rdWdAddr,
-- Sl_rdDAck => Sl_rdDAck,
-- Sl_rdComp => Sl_rdComp,
-- Sl_rdBTerm => Sl_rdBTerm ,
-- Sl_MBusy => Sl_MBusy,
-- Sl_MWrErr => Sl_MWrErr,
-- Sl_MRdErr => Sl_MRdErr,
-- Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock ,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst =>M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm
);
PLB_Clk <= MPLB_Clk;
PLB_Rst <= MPLB_Rst;
------------------------------------------
-- user task
------------------------------------------
dont_register_osif_ports : if C_REGISTER_OSIF_PORTS = 0 generate
task_os2task_vec_i <= task_os2task_vec;
task_task2os_vec <= to_std_logic_vector(task_task2os);
end generate;
register_osif_ports : if C_REGISTER_OSIF_PORTS /= 0 generate
register_osif_ports_proc: process(task_clk)
begin
if rising_edge(task_clk) then
task_os2task_vec_i <= task_os2task_vec;
task_task2os_vec <= to_std_logic_vector(task_task2os);
end if;
end process;
end generate;
task_os2task <= to_osif_os2task_t(task_os2task_vec_i or (X"0000000000" & busy_local & "000000"));
-- task_inst: User task instatiation
-- %%%USER_TASK%%%
------------------------------------------
-- Hook up UUT MD_error to synch_out bit for Master Detected Error status monitor
------------------------------------------
SYNCH_OUT(MST_ERROR) <= sig_dev_mderr;
------------------------------------------
-- Zero out the unused synch_out bits
------------------------------------------
SYNCH_OUT(10 to 31) <= (others => '0');
------------------------------------------
-- Test bench code itself
--
-- The test bench itself can be arbitrarily complex and may include
-- hierarchy as the designer sees fit
------------------------------------------
TEST_PROCESS : process
begin
SYNCH_OUT(NOP) <= '0';
SYNCH_OUT(START) <= '0';
SYNCH_OUT(STOP) <= '0';
SYNCH_OUT(WAIT_IN) <= '0';
SYNCH_OUT(WAIT_OUT) <= '0';
SYNCH_OUT(ASSERT_IN) <= '0';
SYNCH_OUT(ASSERT_OUT) <= '0';
SYNCH_OUT(ASSIGN_IN) <= '0';
SYNCH_OUT(ASSIGN_OUT) <= '0';
SYNCH_OUT(RESET_WDT) <= '0';
-- initializations
-- wait for reset to stabalize after power-up
wait for 200 ns;
-- wait for end of reset
wait until (SPLB_Rst'EVENT and SPLB_Rst = '0');
assert FALSE report "*** Real simulation starts here ***" severity NOTE;
-- wait for reset to be completed
wait for 200 ns;
------------------------------------------
-- Test User Logic IP Master
------------------------------------------
-- send out start signal to begin testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '1';
-- assert FALSE report "*** Start User Logic IP Master Read Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '0';
-- wait for awhile for wait_out signal to let user logic master complete master read ...
wait until (SYNCH_IN(WAIT_OUT)'EVENT and SYNCH_IN(WAIT_OUT) = '1');
-- assert FALSE report "*** User Logic is doing master read transaction now ***" severity NOTE;
wait for 1 us;
-- send out wait_in signal to continue testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '1';
-- assert FALSE report "*** Continue User Logic IP Master Write Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '0';
-- wait for awhile for wait_out signal to let user logic master complete master write ...
wait until (SYNCH_IN(WAIT_OUT)'EVENT and SYNCH_IN(WAIT_OUT) = '1');
-- assert FALSE report "*** User Logic is doing master write transaction now ***" severity NOTE;
wait for 1 us;
-- send out wait_in signal to continue testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '1';
-- assert FALSE report "*** Continue the rest of User Logic IP Master Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '0';
-- wait stop signal for end of testing ...
wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
-- assert FALSE report "*** User Logic IP Master Test Complete ***" severity NOTE;
wait for 1 us;
------------------------------------------
-- Test User I/Os and other features
------------------------------------------
--USER code added here to stimulate any user I/Os
wait;
end process TEST_PROCESS;
dcr_sim : process is
procedure OSIF_WRITE( where : in std_logic_vector(0 to 1);
what : in std_logic_vector(0 to C_DCR_DWIDTH-1) ) is
begin
dcrABus(C_DCR_AWIDTH-2 to C_DCR_AWIDTH-1) <= where;
dcrDBus_out <= what;
wait until rising_edge(PLB_Clk);
dcrWrite <= '1';
wait until rising_edge(PLB_Clk) and dcrAck = '1';
dcrWrite <= '0';
end procedure;
procedure OSIF_READ( where : in std_logic_vector(0 to 1);
variable what : out std_logic_vector(0 to C_DCR_DWIDTH-1) ) is
begin
dcrABus(C_DCR_AWIDTH-2 to C_DCR_AWIDTH-1) <= where;
wait until rising_edge(PLB_Clk);
dcrRead <= '1';
wait until rising_edge(PLB_Clk) and dcrAck = '1';
what := dcrDBus_in;
dcrRead <= '0';
end procedure;
constant OSIF_REG_COMMAND : std_logic_vector(0 to 1) := "00";
constant OSIF_REG_DATA : std_logic_vector(0 to 1) := "01";
constant OSIF_REG_DONE : std_logic_vector(0 to 1) := "10";
constant OSIF_REG_DATAX : std_logic_vector(0 to 1) := "10";
constant OSIF_REG_SIGNATURE : std_logic_vector(0 to 1) := "11";
constant OSIF_CMDNEW : std_logic_vector(0 to C_DCR_DWIDTH-1) := X"FFFFFFFF";
variable dummy : std_logic_vector(0 to C_DCR_DWIDTH-1);
begin
-- initializations
-- wait for reset to stabalize after power-up
wait for 200 ns;
-- wait for end of reset
wait until (PLB_Rst'EVENT and PLB_Rst = '0');
dcrABus <= C_DCR_BASEADDR;
dcrDBus_out <= (others => '0');
dcrICON <= (others => '0');
dcrRead <= '0';
dcrWrite <= '0';
-- sst-generated code starts here
-- %%%SST_TESTBENCH_START%%%
-- %%%SST_TESTBENCH_END%%%
-- end of sst-generated code
wait for 1 us;
wait;
end process;
-- simulate RAM
burst_ram_i : entity burst_ram_v2_01_a.burst_ram
generic map (
G_PORTA_AWIDTH => 12,
G_PORTA_DWIDTH => 32,
G_PORTA_PORTS => 1,
G_PORTB_AWIDTH => 11,
G_PORTB_DWIDTH => 64,
G_PORTB_USE_BE => 1
)
port map (
addra => task2burst_Addr,
addrax => C_GND_TASK_ADDR,
addrb => burstAddr(0 to 10), -- RAM is addressing 64Bit values
clka => task_clk,
clkax => '0',
clkb => task_clk,
dina => task2burst_Data,
dinax => C_GND_TASK_DATA,
dinb => burstWrData,
douta => burst2task_Data,
doutax => open,
doutb => burstRdData,
wea => task2burst_WE,
weax => '0',
web => burstWE,
ena => '1',
enax => '0',
enb => '1',
beb => burstBE
);
-- simulate FIFOs
fifo_left : entity work.fifo
port map (
clk => fifo_clk,
din => fifo_read_datain,
rd_en => fifo_read_remove,
rst => fifo_reset,
wr_en => fifo_read_add,
dout => fifo_read_data,
empty => fifo_read_empty,
full => fifo_read_full,
valid => fifo_read_valid);
fifo_read_ready <= (not fifo_read_empty) or fifo_read_valid ;
fifo_right : entity work.fifo
port map (
clk => fifo_clk,
din => fifo_write_data,
rd_en => fifo_write_remove,
rst => fifo_reset,
wr_en => fifo_write_add,
dout => fifo_write_dataout,
empty => fifo_write_empty,
full => fifo_write_full,
valid => fifo_write_valid);
fifo_write_ready <= not(fifo_write_full);
fifo_fill : process(fifo_clk, fifo_reset)
variable counter : std_logic_vector(0 to C_FIFO_DWIDTH-1);
begin
if fifo_reset = '1' then
counter := (others => '0');
fifo_read_add <= '0';
fifo_read_datain <= (others => '0');
elsif rising_edge(fifo_clk) then
fifo_read_add <= '0';
-- only write on every second clock
if fifo_read_full = '0' and fifo_read_add = '0' and counter < 16 then
fifo_read_datain <= counter;
counter := counter + 1;
fifo_read_add <= '1';
end if;
end if;
end process;
-- infer latch for local busy signal
-- needed for asynchronous communication between thread and OSIF
busy_local_gen : process(task_reset, task_task2os.request, task_os2task.ack)
begin
if task_reset = '1' then
busy_local <= '0';
elsif task_task2os.request = '1' then
busy_local <= '1';
elsif task_os2task.ack = '1' then
busy_local <= '0';
end if;
end process;
end architecture testbench;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: blk_mem_gen_v7_3_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY blk_mem_gen_v7_3_tb IS
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_tb_ARCH OF blk_mem_gen_v7_3_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
blk_mem_gen_v7_3_synth_inst:ENTITY work.blk_mem_gen_v7_3_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
----------------------------------------------------------------------
---- ----
---- iteration_synth.vhd ----
---- ----
---- This file is part of the turbo decoder IP core project ----
---- http://www.opencores.org/projects/turbocodes/ ----
---- ----
---- Author(s): ----
---- - David Brochart(dbrochart@opencores.org) ----
---- ----
---- All additional information is available in the README.txt ----
---- file. ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2005 Authors ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
architecture SYNTH of ITERATION is
signal zout1 : ARRAY4c;
signal zout2 : ARRAY4c;
signal zout1perm : ARRAY4c;
signal zoutint1 : ARRAY4c;
signal zout2int : ARRAY4c;
signal tmp0 : std_logic_vector(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto 0);
signal tmp1 : std_logic_vector(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto 0);
signal tmp2 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
signal tmp3 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
signal tmp4 : std_logic_vector(SIG_WIDTH * 4 - 1 downto 0);
signal tmp5 : std_logic_vector(SIG_WIDTH * 4 - 1 downto 0);
signal tmp6 : std_logic_vector(Z_WIDTH * 4 - 1 downto 0);
signal tmp7 : std_logic_vector(Z_WIDTH * 4 - 1 downto 0);
signal tmp8 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
signal tmp9 : std_logic_vector(SIG_WIDTH * 6 - 1 downto 0);
signal tmp10 : std_logic_vector(SIG_WIDTH * 8 - 1 downto 0);
signal tmp11 : std_logic_vector(SIG_WIDTH * 8 - 1 downto 0);
signal abdel1perm : ARRAY2a;
signal abdel1permint : ARRAY2a;
signal adel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal bdel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal ydel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wdel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yintdel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wintdel1 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal adel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal bdel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal ydel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wdel2 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal adecint : std_logic;
signal bdecint : std_logic;
signal adel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal bdel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal ydel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wdel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yintdel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wintdel3 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal yintdel4 : std_logic_vector(SIG_WIDTH - 1 downto 0);
signal wintdel4 : std_logic_vector(SIG_WIDTH - 1 downto 0);
begin
SOVA_I0 : SOVA
port map (
CLK => clk,
RST => rst,
ANOISY => a,
BNOISY => b,
YNOISY => y,
WNOISY => w,
ZIN => zin,
ZOUT => zout1,
ACLEAN => aDec,
BCLEAN => bDec
);
ZPERMUT_I0 : ZPERMUT
generic map (
FLIP => (TREL1_LEN + TREL2_LEN + 2 + delay + 1) mod 2
)
port map (
FLIPFLOP => flipflop,
Z => zout1,
ZPERM => zout1perm
);
tmp0 <= zout1perm(0) & zout1perm(1) & zout1perm(2) & zout1perm(3) & abdel1perm(0) & abdel1perm(1);
INTERLEAVER_I0 : INTERLEAVER
generic map (
DELAY => TREL1_LEN + TREL2_LEN + 2 + delay,
WAY => 0
)
port map (
CLK => clk,
RST => rst,
D => tmp0,
Q => tmp1
);
zoutint1(0) <= tmp1(Z_WIDTH * 4 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 3 + SIG_WIDTH * 2);
zoutint1(1) <= tmp1(Z_WIDTH * 3 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 2 + SIG_WIDTH * 2);
zoutint1(2) <= tmp1(Z_WIDTH * 2 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 1 + SIG_WIDTH * 2);
zoutint1(3) <= tmp1(Z_WIDTH * 1 + SIG_WIDTH * 2 - 1 downto Z_WIDTH * 0 + SIG_WIDTH * 2);
abdel1permint(0) <= tmp1(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
abdel1permint(1) <= tmp1(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
tmp2 <= a & b & y & w & yInt & wInt;
DELAYER_I0 : DELAYER
generic map (
DELAY => TREL1_LEN + TREL2_LEN
)
port map (
CLK => clk,
RST => rst,
D => tmp2,
Q => tmp3
);
adel1 <= tmp3(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
bdel1 <= tmp3(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
ydel1 <= tmp3(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
wdel1 <= tmp3(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
yintdel1 <= tmp3(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
wintdel1 <= tmp3(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
ABPERMUT_I0 : ABPERMUT
generic map (
FLIP => (TREL1_LEN + TREL2_LEN + 2 + delay + 1) mod 2
)
port map (
FLIPFLOP => flipflop,
A => adel1,
B => bdel1,
ABPERM => abdel1perm
);
tmp4 <= adel1 & bdel1 & ydel1 & wdel1;
DELAYER_I1 : DELAYER
generic map (
DELAY => FRSIZE
)
port map (
CLK => clk,
RST => rst,
D => tmp4,
Q => tmp5
);
adel2 <= tmp5(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
bdel2 <= tmp5(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
ydel2 <= tmp5(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
wdel2 <= tmp5(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
SOVA_I1 : SOVA
port map (
CLK => clk,
RST => rst,
ANOISY => abdel1permint(1),
BNOISY => abdel1permint(0),
YNOISY => yintdel1,
WNOISY => wintdel1,
ZIN => zoutint1,
ZOUT => zout2,
ACLEAN => adecint,
BCLEAN => bdecint
);
tmp6 <= zout2(0) & zout2(1) & zout2(2) & zout2(3);
DEINTERLEAVER_I0 : INTERLEAVER
generic map (
DELAY => 2 * (TREL1_LEN + TREL2_LEN + 2) + FRSIZE + delay,
WAY => 1
)
port map (
CLK => clk,
RST => rst,
D => tmp6,
Q => tmp7
);
zout2int(0) <= tmp7(Z_WIDTH * 4 - 1 downto Z_WIDTH * 3);
zout2int(1) <= tmp7(Z_WIDTH * 3 - 1 downto Z_WIDTH * 2);
zout2int(2) <= tmp7(Z_WIDTH * 2 - 1 downto Z_WIDTH * 1);
zout2int(3) <= tmp7(Z_WIDTH * 1 - 1 downto Z_WIDTH * 0);
ZPERMUT_I1 : ZPERMUT
generic map (
FLIP => (2 * (TREL1_LEN + TREL2_LEN + 2) + FRSIZE + delay) mod 2
)
port map (
FLIPFLOP => flipflop,
Z => zout2int,
ZPERM => zout
);
tmp8 <= adel2 & bdel2 & ydel2 & wdel2 & yintdel1 & wintdel1;
DELAYER_I2 : DELAYER
generic map (
DELAY => TREL1_LEN + TREL2_LEN
)
port map (
CLK => clk,
RST => rst,
D => tmp8,
Q => tmp9
);
adel3 <= tmp9(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
bdel3 <= tmp9(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
ydel3 <= tmp9(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
wdel3 <= tmp9(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
yintdel3 <= tmp9(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
wintdel3 <= tmp9(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
tmp10 <= adel3 & bdel3 & ydel3 & wdel3 & yintdel3 & wintdel3 & yintdel4 & wintdel4;
DELAYER_I3 : DELAYER
generic map (
DELAY => FRSIZE
)
port map (
CLK => clk,
RST => rst,
D => tmp10,
Q => tmp11
);
aDel <= tmp11(SIG_WIDTH * 8 - 1 downto SIG_WIDTH * 7);
bDel <= tmp11(SIG_WIDTH * 7 - 1 downto SIG_WIDTH * 6);
yDel <= tmp11(SIG_WIDTH * 6 - 1 downto SIG_WIDTH * 5);
wDel <= tmp11(SIG_WIDTH * 5 - 1 downto SIG_WIDTH * 4);
yintdel4 <= tmp11(SIG_WIDTH * 4 - 1 downto SIG_WIDTH * 3);
wintdel4 <= tmp11(SIG_WIDTH * 3 - 1 downto SIG_WIDTH * 2);
yIntDel <= tmp11(SIG_WIDTH * 2 - 1 downto SIG_WIDTH * 1);
wIntDel <= tmp11(SIG_WIDTH * 1 - 1 downto SIG_WIDTH * 0);
end architecture SYNTH;
|
-- $Id: rbd_usracc.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: rbd_usracc - syn
-- Description: rbus dev: return usr_access register (bitfile+jtag timestamp)
--
-- Dependencies: xlib/usr_access_unisim
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2015.4-2018.2; ghdl 0.33-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-04-02 758 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 0 ua0 r/-/- use_accress lsb
-- 1 ua1 r/-/- use_accress msb
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.rblib.all;
use work.rbdlib.all;
entity rbd_usracc is -- rbus dev: return usr_access register
generic (
RB_ADDR : slv16 := rbaddr_usracc);
port (
CLK : in slbit; -- clock
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type -- rbus: response
);
end entity rbd_usracc;
architecture syn of rbd_usracc is
signal R_SEL : slbit := '0';
signal DATA : slv32 := (others=>'0');
begin
RBSEL : rb_sel
generic map (
RB_ADDR => RB_ADDR,
SAWIDTH => 1)
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
SEL => R_SEL
);
UA : usr_access_unisim
port map (DATA => DATA);
proc_next : process (R_SEL, RB_MREQ, DATA)
variable irb_ack : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
begin
irb_ack := '0';
irb_err := '0';
irb_dout := (others=>'0');
-- rbus transactions
if R_SEL = '1' then
irb_ack := RB_MREQ.re or RB_MREQ.we;
if RB_MREQ.we = '1' then
irb_err := '1';
end if;
if RB_MREQ.re = '1' then
case (RB_MREQ.addr(0)) is
when '0' => irb_dout := DATA(15 downto 0);
when '1' => irb_dout := DATA(31 downto 16);
when others => null;
end case;
end if;
end if;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= '0';
end process proc_next;
end syn;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram
-- File: syncram.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous 1-port ram with tech selection
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
use work.gencomp.all;
use work.allmem.all;
entity syncram is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits: integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none
);
end;
architecture rtl of syncram is
constant nctrl : integer := abits + (TESTIN_WIDTH-2) + 2;
signal rena, wena : std_logic;
signal dataoutx, databp, testdata : std_logic_vector((dbits -1) downto 0);
constant SCANTESTBP : boolean := (testen = 1) and syncram_add_scan_bypass(tech)=1;
signal xenable, xwrite: std_ulogic;
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
signal customclkx: std_ulogic;
begin
xenable <= enable and not testin(TESTIN_WIDTH-2) when testen/=0 else enable;
xwrite <= write and not testin(TESTIN_WIDTH-2) when testen/=0 else write;
-- RAM bypass for scan
scanbp : if SCANTESTBP generate
comb : process (address, datain, enable, write, testin)
variable tmp : std_logic_vector((dbits -1) downto 0);
variable ctrlsigs : std_logic_vector((nctrl -1) downto 0);
begin
ctrlsigs := testin(TESTIN_WIDTH-3 downto 0) & write & enable & address;
tmp := datain;
for i in 0 to nctrl-1 loop
tmp(i mod dbits) := tmp(i mod dbits) xor ctrlsigs(i);
end loop;
testdata <= tmp;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
databp <= testdata;
end if;
end process;
dmuxout : for i in 0 to dbits-1 generate
x0: grmux2 generic map (tech)
port map (dataoutx(i), databp(i), testin(TESTIN_WIDTH-1), dataout(i));
end generate;
end generate;
custominx <= (others => '0');
customclkx <= '0';
nocust: if syncram_has_customif(tech)=0 generate
customoutx <= (others => '0');
end generate;
noscanbp : if not SCANTESTBP generate dataout <= dataoutx; end generate;
inf : if tech = inferred generate
x0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, write);
end generate;
xcv : if (tech = virtex) generate
x0 : virtex_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
xc2v : if (is_unisim(tech) = 1) and (tech /= virtex) generate
x0 : unisim_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
vir : if tech = memvirage generate
x0 : virage_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
atrh : if tech = atc18rha generate
x0 : atc18rha_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite,
testin(TESTIN_WIDTH-1 downto TESTIN_WIDTH-4));
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
proa : if tech = proasic generate
x0 : proasic_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
igl2 : if tech = igloo2 generate
x0 : igloo2_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
umc18 : if tech = umc generate
x0 : umc_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
rhu : if tech = rhumc generate
x0 : rhumc_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
saed : if tech = saed32 generate
x0 : saed32_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
rhs : if tech = rhs65 generate
x0 : rhs65_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, enable, write,
testin(TESTIN_WIDTH-8),testin(TESTIN_WIDTH-3),
custominx(0),customoutx(0),
testin(TESTIN_WIDTH-4),testin(TESTIN_WIDTH-5),testin(TESTIN_WIDTH-6),
customclkx,testin(TESTIN_WIDTH-7),'0',
customoutx(1), customoutx(7 downto 2));
customoutx(customoutx'high downto 8) <= (others => '0');
end generate;
dar : if tech = dare generate
x0 : dare_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
proa3 : if tech = apa3 generate
x0 : proasic3_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
proa3e : if tech = apa3e generate
x0 : proasic3e_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
proa3l : if tech = apa3l generate
x0 : proasic3l_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
fus : if tech = actfus generate
x0 : fusion_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
ihp : if tech = ihp25 generate
x0 : ihp25_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite);
end generate;
ihprh : if tech = ihp25rh generate
x0 : ihp25rh_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite);
end generate;
alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or
(tech = stratix3) or (tech = stratix4) or (tech = cyclone3) generate
x0 : altera_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite);
end generate;
rht : if tech = rhlib18t generate
x0 : rh_lib18t_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite, testin(TESTIN_WIDTH-3 downto TESTIN_WIDTH-4));
end generate;
lat : if tech = lattice generate
x0 : ec_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite);
end generate;
ut025 : if tech = ut25 generate
x0 : ut025crh_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
ut09 : if tech = ut90 generate
x0 : ut90nhbd_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite, testin(TESTIN_WIDTH-3));
end generate;
ut13 : if tech = ut130 generate
x0 : ut130hbd_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
pere : if tech = peregrine generate
x0 : peregrine_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
arti : if tech = memartisan generate
x0 : artisan_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
cust1 : if tech = custom1 generate
x0 : custom1_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
ecl : if tech = eclipse generate
rena <= xenable and not write;
wena <= xenable and write;
x0 : eclipse_syncram_2p generic map(abits, dbits)
port map(clk, rena, address, dataoutx, clk, address,
datain, wena);
end generate;
virage90 : if tech = memvirage90 generate
x0 : virage90_syncram generic map(abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
nex : if tech = easic90 generate
x0 : nextreme_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
smic : if tech = smic013 generate
x0 : smic13_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
tm65gplu : if tech = tm65gplus generate
x0 : tm65gplus_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
cmos9sfx : if tech = cmos9sf generate
x0 : cmos9sf_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
n2x : if tech = easic45 generate
x0 : n2x_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
rh13t : if tech = rhlib13t generate
x0 : rh_lib13t_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite, testin(TESTIN_WIDTH-3 downto TESTIN_WIDTH-4));
end generate;
-- pragma translate_off
noram : if has_sram(tech) = 0 generate
x : process
begin
assert false report "syncram: technology " & tech_table(tech) &
" not supported"
severity failure;
wait;
end process;
end generate;
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram: " & tost(2**abits) & "x" & tost(dbits) &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
chk : if GRLIB_CONFIG_ARRAY(grlib_syncram_selftest_enable) /= 0 generate
chkblk: block
signal refdo: std_logic_vector(dbits-1 downto 0);
signal pren: std_ulogic;
signal paddr: std_logic_vector(abits-1 downto 0);
begin
refram : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, refdo, write);
p: process(clk)
begin
if rising_edge(clk) then
assert pren/='1' or refdo=dataoutx or is_x(refdo) or is_x(paddr)
report "Read mismatch addr=" & tost(paddr) & " impl=" & tost(dataoutx) & " ref=" & tost(refdo)
severity error;
pren <= enable and not write;
paddr <= address;
end if;
end process;
end block;
end generate;
-- pragma translate_on
end;
|
---------------------------------------------------------------------------
-- Company : Vim Inc
-- Author(s) : Fabien Marteau
--
-- Creation Date : 19/10/2008
-- File : xilinx_one_port_ram_async.vhd
--
-- Abstract : Xilinx behavioural template for ram
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- For bram
Library UNISIM;
use UNISIM.vcomponents.all;
---------------------------------------------------------------------------
Entity xilinx_one_port_ram_async is
---------------------------------------------------------------------------
generic
(
ADDR_WIDTH : integer := 10;
DATA_WIDTH : integer := 16
);
port
(
clk : in std_logic;
we : in std_logic ;
addr : in std_logic_vector( ADDR_WIDTH - 1 downto 0);
din : in std_logic_vector( DATA_WIDTH - 1 downto 0);
dout : out std_logic_vector( DATA_WIDTH - 1 downto 0)
);
end entity;
---------------------------------------------------------------------------
Architecture xilinx_one_port_ram_async_1 of xilinx_one_port_ram_async is
---------------------------------------------------------------------------
-- type ram_type is array (2**ADDR_WIDTH-1 downto 0)
-- of std_logic_vector( DATA_WIDTH-1 downto 0);
-- signal ram: ram_type;
-- signal addr_reg : std_logic_vector( ADDR_WIDTH-1 downto 0);
begin
-- process (clk)
-- begin
-- if (clk'event and clk = '1') then
-- if (we='1') then
-- ram(to_integer(unsigned(addr)))<= din;
-- end if;
-- addr_reg <= addr;
-- end if;
-- end process;
-- dout <= ram(to_integer(unsigned(addr_reg)));
-- RAMB16_S18: Virtex-II/II-Pro, Spartan-3/3E 1k x 16 + 2 Parity bits Single-Port RAM
-- Xilinx HDL Language Template, version 10.1.3
RAMB16_S18_inst : RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
-- The following INIT_xx declarations specify the intial contents of the RAM
-- Address 0 to 255
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 256 to 511
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 767
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 768 to 1023
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INITP_xx are for the parity bits
-- Address 0 to 255
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 256 to 511
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 512 to 767
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- Address 768 to 1023
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DO => dout, -- 16-bit Data Output
DOP => open, -- 2-bit parity Output
ADDR => addr, -- 10-bit Address Input
CLK => clk, -- Clock
DI => din, -- 16-bit Data Input
DIP => "00", -- 2-bit parity Input
EN => '1', -- RAM Enable Input
SSR => '0', -- Synchronous Set/Reset Input
WE => we -- Write Enable Input
);
end architecture xilinx_one_port_ram_async_1;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: utt.fr:hls:doHistStretch:1.0
-- IP Revision: 1606210026
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_doHistStretch_0_0 IS
PORT (
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
outStream_TVALID : OUT STD_LOGIC;
outStream_TREADY : IN STD_LOGIC;
outStream_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
outStream_TDEST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
outStream_TKEEP : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TSTRB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TUSER : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
outStream_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TID : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END design_1_doHistStretch_0_0;
ARCHITECTURE design_1_doHistStretch_0_0_arch OF design_1_doHistStretch_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_doHistStretch_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT doHistStretch IS
GENERIC (
C_S_AXI_CTRL_BUS_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_BUS_DATA_WIDTH : INTEGER
);
PORT (
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inStream_TDEST : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
inStream_TKEEP : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TUSER : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
inStream_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
inStream_TID : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
outStream_TVALID : OUT STD_LOGIC;
outStream_TREADY : IN STD_LOGIC;
outStream_TDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
outStream_TDEST : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
outStream_TKEEP : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TSTRB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TUSER : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
outStream_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outStream_TID : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT doHistStretch;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_doHistStretch_0_0_arch: ARCHITECTURE IS "doHistStretch,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_doHistStretch_0_0_arch : ARCHITECTURE IS "design_1_doHistStretch_0_0,doHistStretch,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_CTRL_BUS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_CTRL_BUS RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF inStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 inStream TID";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TVALID";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TREADY";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TDATA";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TDEST";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TUSER";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TLAST";
ATTRIBUTE X_INTERFACE_INFO OF outStream_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 outStream TID";
BEGIN
U0 : doHistStretch
GENERIC MAP (
C_S_AXI_CTRL_BUS_ADDR_WIDTH => 5,
C_S_AXI_CTRL_BUS_DATA_WIDTH => 32
)
PORT MAP (
s_axi_CTRL_BUS_AWADDR => s_axi_CTRL_BUS_AWADDR,
s_axi_CTRL_BUS_AWVALID => s_axi_CTRL_BUS_AWVALID,
s_axi_CTRL_BUS_AWREADY => s_axi_CTRL_BUS_AWREADY,
s_axi_CTRL_BUS_WDATA => s_axi_CTRL_BUS_WDATA,
s_axi_CTRL_BUS_WSTRB => s_axi_CTRL_BUS_WSTRB,
s_axi_CTRL_BUS_WVALID => s_axi_CTRL_BUS_WVALID,
s_axi_CTRL_BUS_WREADY => s_axi_CTRL_BUS_WREADY,
s_axi_CTRL_BUS_BRESP => s_axi_CTRL_BUS_BRESP,
s_axi_CTRL_BUS_BVALID => s_axi_CTRL_BUS_BVALID,
s_axi_CTRL_BUS_BREADY => s_axi_CTRL_BUS_BREADY,
s_axi_CTRL_BUS_ARADDR => s_axi_CTRL_BUS_ARADDR,
s_axi_CTRL_BUS_ARVALID => s_axi_CTRL_BUS_ARVALID,
s_axi_CTRL_BUS_ARREADY => s_axi_CTRL_BUS_ARREADY,
s_axi_CTRL_BUS_RDATA => s_axi_CTRL_BUS_RDATA,
s_axi_CTRL_BUS_RRESP => s_axi_CTRL_BUS_RRESP,
s_axi_CTRL_BUS_RVALID => s_axi_CTRL_BUS_RVALID,
s_axi_CTRL_BUS_RREADY => s_axi_CTRL_BUS_RREADY,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt,
inStream_TVALID => inStream_TVALID,
inStream_TREADY => inStream_TREADY,
inStream_TDATA => inStream_TDATA,
inStream_TDEST => inStream_TDEST,
inStream_TKEEP => inStream_TKEEP,
inStream_TSTRB => inStream_TSTRB,
inStream_TUSER => inStream_TUSER,
inStream_TLAST => inStream_TLAST,
inStream_TID => inStream_TID,
outStream_TVALID => outStream_TVALID,
outStream_TREADY => outStream_TREADY,
outStream_TDATA => outStream_TDATA,
outStream_TDEST => outStream_TDEST,
outStream_TKEEP => outStream_TKEEP,
outStream_TSTRB => outStream_TSTRB,
outStream_TUSER => outStream_TUSER,
outStream_TLAST => outStream_TLAST,
outStream_TID => outStream_TID
);
END design_1_doHistStretch_0_0_arch;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of ent_a
--
-- Generated
-- by: wig
-- on: Wed Nov 2 10:48:49 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-struct-a.vhd,v 1.2 2005/11/02 14:29:09 wig Exp $
-- $Date: 2005/11/02 14:29:09 $
-- $Log: ent_a-struct-a.vhd,v $
-- Revision 1.2 2005/11/02 14:29:09 wig
-- Remove extra ; from port map if port has comment
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.66 2005/10/24 15:43:48 wig Exp
--
-- Generator: mix_0.pl Revision: 1.38 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of ent_a
--
architecture struct of ent_a is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_aa -- is i_padframe / hier inst_aa inst_aa inst_a
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
ramd_oe_i : in std_ulogic_vector(31 downto 0); -- bad conection bits detected
ramd_oe_i_r : in std_ulogic_vector(31 downto 0); -- reverse order
ramdm_oe_i : in std_ulogic_vector(3 downto 0); -- bad conection bits detected
ramdm_oe_i_r : in std_ulogic_vector(3 downto 0) -- reverse order
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab -- is i_vgca / hier inst_ab inst_ab inst_a
-- No Generated Generics
port (
-- Generated Port for Entity ent_ab
p_mix_sig_20051018d_go : out std_ulogic_vector(31 downto 0);
p_mix_sigrev_20051018d_go : out std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity ent_ab
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_20051018d : std_ulogic_vector(31 downto 0);
signal sigrev_20051018d : std_ulogic_vector(31 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa -- is i_padframe / hier inst_aa inst_aa inst_a
port map (
ramd_oe_i => sig_20051018d, -- bad conection bits detected
ramd_oe_i_r => sigrev_20051018d, -- reverse order
ramdm_oe_i(1 downto 0) => sig_20051018d(8 downto 7), -- bad conection bits detected
ramdm_oe_i(3 downto 2) => sig_20051018d(24 downto 23), -- bad conection bits detected
ramdm_oe_i_r(1 downto 0) => sigrev_20051018d(8 downto 7), -- reverse order
ramdm_oe_i_r(3 downto 2) => sigrev_20051018d(24 downto 23) -- reverse order
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab -- is i_vgca / hier inst_ab inst_ab inst_a
port map (
p_mix_sig_20051018d_go => sig_20051018d, -- bad conection bits detected
p_mix_sigrev_20051018d_go => sigrev_20051018d -- reverse order
);
-- End of Generated Instance Port Map for inst_ab
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_functions
---- Version: 1.0.0
---- Description:
---- TO BE DONE
-------------------------------
---- Author(s):
---- Guillaume Rembert
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/12/28: initial release
---- 2016/10/20: added reverse_std_logic_vector function + rework sim_generate_random_std_logic_vector for > 32 bits vectors
---- 2016/11/17: added convert_boolean_to_std_logic function
---- 2017/01/15: added convert_std_logic_vector_array_to_std_logic_vector
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.ccsds_rxtx_types.all;
package ccsds_rxtx_functions is
-- synthetizable functions
function convert_boolean_to_std_logic(input: in boolean) return std_logic;
function convert_std_logic_vector_array_to_std_logic_vector(std_logic_vector_array_in: in std_logic_vector_array; current_row: in integer) return std_logic_vector;
function reverse_std_logic_vector (input: in std_logic_vector) return std_logic_vector;
-- simulation / testbench only functions
function convert_std_logic_vector_to_hexa_ascii(input: in std_logic_vector) return string;
procedure sim_generate_random_std_logic_vector(vector_size : in integer; seed1 : inout positive; seed2 : inout positive; result : out std_logic_vector);
end ccsds_rxtx_functions;
package body ccsds_rxtx_functions is
function convert_boolean_to_std_logic(input: in boolean) return std_logic is
begin
if (input = true) then
return '1';
else
return '0';
end if;
end convert_boolean_to_std_logic;
function convert_std_logic_vector_array_to_std_logic_vector(std_logic_vector_array_in: in std_logic_vector_array; current_row: in integer) return std_logic_vector is
variable result: std_logic_vector(std_logic_vector_array_in'range(2));
begin
for i in std_logic_vector_array_in'range(2) loop
result(i) := std_logic_vector_array_in(current_row, i);
-- report "Read: " & std_logic'image(std_logic_vector_array_in(current_row, i)) severity note;
end loop;
return result;
end;
function reverse_std_logic_vector (input: in std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(input'range);
alias output: std_logic_vector(input'REVERSE_RANGE) is input;
begin
for vector_pointer in output'range loop
result(vector_pointer) := output(vector_pointer);
end loop;
return result;
end;
function convert_std_logic_vector_to_hexa_ascii(input: in std_logic_vector) return string is
constant words_number: integer := input'length/4;
variable result: string(words_number-1 downto 0);
variable word: std_logic_vector(3 downto 0);
begin
for vector_word_pointer in words_number-1 downto 0 loop
word := input((vector_word_pointer+1)*4-1 downto vector_word_pointer*4);
case word is
when "0000" =>
result(vector_word_pointer) := '0';
when "0001" =>
result(vector_word_pointer) := '1';
when "0010" =>
result(vector_word_pointer) := '2';
when "0011" =>
result(vector_word_pointer) := '3';
when "0100" =>
result(vector_word_pointer) := '4';
when "0101" =>
result(vector_word_pointer) := '5';
when "0110" =>
result(vector_word_pointer) := '6';
when "0111" =>
result(vector_word_pointer) := '7';
when "1000" =>
result(vector_word_pointer) := '8';
when "1001" =>
result(vector_word_pointer) := '9';
when "1010" =>
result(vector_word_pointer) := 'a';
when "1011" =>
result(vector_word_pointer) := 'b';
when "1100" =>
result(vector_word_pointer) := 'c';
when "1101" =>
result(vector_word_pointer) := 'd';
when "1110" =>
result(vector_word_pointer) := 'e';
when "1111" =>
result(vector_word_pointer) := 'f';
when others =>
result(vector_word_pointer) := '?';
end case;
-- report "Converted " & integer'image(to_integer(resize(unsigned(word),16))) & " to " & result(vector_word_pointer) severity note;
end loop;
return result;
end;
procedure sim_generate_random_std_logic_vector(vector_size : in integer; seed1 : inout positive; seed2 : inout positive; result : out std_logic_vector) is
variable rand: real := 0.0;
variable temp: std_logic_vector(31 downto 0);
begin
if (vector_size < 32) then
uniform(seed1, seed2, rand);
rand := rand*(2**(real(vector_size))-1.0);
result := std_logic_vector(to_unsigned(integer(rand),vector_size));
else
uniform(seed1, seed2, rand);
for vector_pointer in 0 to vector_size-1 loop
uniform(seed1, seed2, rand);
rand := rand*(2**(real(31))-1.0);
temp := std_logic_vector(to_unsigned(integer(rand),32));
result(vector_pointer) := temp(0);
end loop;
end if;
end sim_generate_random_std_logic_vector;
end ccsds_rxtx_functions;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - sergeykhbr@gmail.com
--! @brief Controller of the GPIOs with the AMBA AXI4 interface.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity nasti_gpio is
generic (
xindex : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out nasti_slave_config_type;
i : in nasti_slave_in_type;
o : out nasti_slave_out_type;
i_dip : in std_logic_vector(3 downto 0);
o_led : out std_logic_vector(7 downto 0)
);
end;
architecture arch_nasti_gpio of nasti_gpio is
constant xconfig : nasti_slave_config_type := (
xindex => xindex,
xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_GPIO,
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES
);
type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
of integer;
type bank_type is record
led : std_logic_vector(31 downto 0);
dip : std_logic_vector(31 downto 0);
reg32_2 : std_logic_vector(31 downto 0);
reg32_3 : std_logic_vector(31 downto 0);
reg32_4 : std_logic_vector(31 downto 0);
reg32_5 : std_logic_vector(31 downto 0);
reg32_6 : std_logic_vector(31 downto 0);
end record;
type registers is record
bank_axi : nasti_slave_bank_type;
bank0 : bank_type;
end record;
constant RESET_VALUE : registers := (
NASTI_SLAVE_BANK_RESET,
((others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'))
);
signal r, rin : registers;
begin
comblogic : process(i, i_dip, r, nrst)
variable v : registers;
variable raddr_reg : local_addr_array_type;
variable waddr_reg : local_addr_array_type;
variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
begin
v := r;
procedureAxi4(i, xconfig, r.bank_axi, v.bank_axi);
for n in 0 to CFG_WORDS_ON_BUS-1 loop
raddr_reg(n) := conv_integer(r.bank_axi.raddr(n)(11 downto 2));
tmp := (others => '0');
case raddr_reg(n) is
when 0 => tmp := r.bank0.led;
when 1 => tmp := r.bank0.dip;
when 2 => tmp := r.bank0.reg32_2;
when 3 => tmp := r.bank0.reg32_3;
when 4 => tmp := r.bank0.reg32_4;
when 5 => tmp := r.bank0.reg32_5;
when 6 => tmp := r.bank0.reg32_6;
when others =>
end case;
rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
if i.w_valid = '1' and
r.bank_axi.wstate = wtrans and
r.bank_axi.wresp = NASTI_RESP_OKAY then
wstrb := i.w_strb;
for n in 0 to CFG_WORDS_ON_BUS-1 loop
waddr_reg(n) := conv_integer(r.bank_axi.waddr(n)(11 downto 2));
tmp := i.w_data(32*(n+1)-1 downto 32*n);
if conv_integer(wstrb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n)) /= 0 then
case waddr_reg(n) is
when 0 => v.bank0.led := tmp;
--when 1 => v.bank0.dip := tmp;
when 2 => v.bank0.reg32_2 := tmp;
when 3 => v.bank0.reg32_3 := tmp;
when 4 => v.bank0.reg32_4 := tmp;
when 5 => v.bank0.reg32_5 := tmp;
when 6 => v.bank0.reg32_6 := tmp;
when others =>
end case;
end if;
end loop;
end if;
o <= functionAxi4Output(r.bank_axi, rdata);
v.bank0.dip(3 downto 0) := i_dip;
if nrst = '0' then
v := RESET_VALUE;
end if;
rin <= v;
end process;
cfg <= xconfig;
o_led <= r.bank0.led(7 downto 0);
-- registers:
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end;
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2009 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
--
-- Pipelined divider usign restoring algorithm
-- total pipe length is (sig_width + 1)
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity dspdiv is
generic (
sig_width : integer := 16);
port (
--@inputs
num : in std_logic_vector((2*sig_width - 1) downto 0);
den : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
--@outputs;
q : out std_logic_vector((sig_width - 1) downto 0);
r : out std_logic_vector((2*sig_width - 3) downto 0)
);
end dspdiv;
--=----------------------------------------------------------------------------
architecture archi_dspdiv of dspdiv is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_div_length : integer := sig_width - 1;
constant c_work_length : integer := 2*c_div_length;
constant c_trial_length : integer := c_div_length + 2;
constant c_trial_overflow : integer := c_trial_length - 2;
constant c_trial_sign : integer := c_trial_length - 1;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
type t_work_pipe is array(0 to c_div_length) of std_logic_vector((c_work_length - 1) downto 0);
type t_trial_pipe is array(0 to c_div_length) of unsigned((c_trial_length - 1) downto 0);
--type t_trial_pipe is array(0 to c_div_length) of std_logic_vector((c_trial_length - 1) downto 0);
type t_val_pipe is array(0 to c_div_length - 1) of std_logic_vector((c_div_length - 1) downto 0);
type t_bit_pipe is array(0 to c_div_length - 1) of std_logic;
signal s_r : t_work_pipe;
signal s_trial_r : t_trial_pipe;
signal s_d : t_val_pipe;
signal s_q : t_val_pipe;
signal s_sign : t_bit_pipe;
signal s_overflow : t_bit_pipe;
signal s_overflow_cur : t_bit_pipe;
signal s_num_abs : signed((2*sig_width - 1) downto 0);
signal s_num_sign : std_logic;
signal s_den_abs : signed((sig_width - 1) downto 0);
signal s_den_sign : std_logic;
signal s_sign_last : std_logic;
--
-- SIgnals for debug
--
signal s_d0 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d1 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d2 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d3 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d4 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d5 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d6 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d7 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d8 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d9 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d10 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d11 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d12 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d13 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d14 : std_logic_vector((c_div_length - 1) downto 0);
--signal s_d15 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q0 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q1 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q2 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q3 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q4 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q5 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q6 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q7 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q8 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q9 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q10 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q11 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q12 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q13 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q14 : std_logic_vector((c_div_length - 1) downto 0);
--signal s_q15 : std_logic_vector((c_div_length - 1) downto 0);
signal s_r0 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r1 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r2 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r3 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r4 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r5 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r6 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r7 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r8 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r9 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r10 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r11 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r12 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r13 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r14 : std_logic_vector((c_work_length - 1) downto 0);
--signal s_r15 : std_logic_vector((c_work_length - 1) downto 0);
signal s_trial_r0 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r1 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r2 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r3 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r4 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r5 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r6 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r7 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r8 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r9 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r10 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r11 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r12 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r13 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r14 : unsigned((c_trial_length - 1) downto 0);
--signal s_trial_r15 : unsigned((c_trial_length - 1) downto 0);
begin -- archs_dspdiv
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_div : process (clk)
begin -- process p_div
if rising_edge(clk) then -- rising clock edge
-- s_r(0)((c_div_length - 1) downto 0)<= num(2*sig_width - 2 downto (2*sig_width - c_div_length - 1));
-- s_r(0)((c_work_length - 1) downto c_div_length) <= (others => '0');
s_r(0) <= std_logic_vector(s_num_abs((c_work_length - 1) downto 0));
s_d(0) <= std_logic_vector(s_den_abs((c_div_length - 1) downto 0));
s_sign(0) <= s_num_sign xor s_den_sign;
-- fill unused lines with 0 for simulation
for i in 0 to c_div_length - 2 loop
-- propagation of quotient bits previously computed
s_q(i)((c_div_length - i - 2) downto 0) <= (others => '0');
end loop;
-- pipe
for i in 1 to c_div_length - 1 loop
s_sign(i) <= s_sign(i - 1);
s_d(i) <= s_d(i - 1);
-- propagation of quotient bits previously computed
s_q(i)((c_div_length - 1) downto (c_div_length - i)) <= s_q(i - 1)((c_div_length - 1) downto (c_div_length - i));
-- test for overflow (denominator too small)
s_overflow(i) <= s_overflow(i - 1) or s_overflow_cur(i);
end loop;
s_overflow(0) <= s_overflow_cur(0);
s_sign_last <= s_sign(c_div_length - 1);
for i in 0 to c_div_length - 1 loop
if s_trial_r(i)(c_trial_length - 1) = '0' then --if >= 0
s_r(i + 1)((c_work_length - 1) downto c_div_length) <= std_logic_vector(s_trial_r(i)(c_div_length - 1 downto 0)); -- store trial reminder
s_q(i)(c_div_length - 1 - i) <= '1';
else
-- restore s_r and shift one bit left (R <- 2R)
s_r(i + 1)((c_work_length - 1) downto c_div_length) <= s_r(i)(c_work_length - 2 downto c_div_length - 1);
s_q(i)(c_div_length - 1 - i) <= '0';
end if;
-- The lower part of the remainder is just shifted
s_r(i + 1)((c_div_length - 1) downto 0) <= s_r(i)((c_div_length - 2) downto 0) & '0';
end loop;
end if;
end process p_div;
p_sign : process (num,den)
begin -- process p_sign
if den(sig_width - 1) = '0' then
s_den_abs <= signed(den);
s_den_sign <= '0';
else
s_den_abs <= -signed(den);
s_den_sign <= '1';
end if;
if num(2*sig_width - 1) = '0' then
s_num_abs <= signed(num);
s_num_sign <= '0';
else
s_num_abs <= -signed(num);
s_num_sign <= '1';
end if;
end process p_sign;
p_out_reg : process (clk)
begin -- process p_out_reg
if rising_edge(clk) then -- rising clock edge
if s_overflow(c_div_length - 1) = '1' then
q(sig_width - 2 downto 0) <= (others => '1');
q(sig_width - 1) <= '0';
r <= (others => '0');
elsif s_sign_last = '0' then
r <= s_r(c_div_length - 1);
q <= '0' & s_q(c_div_length - 1);
else
r <= s_r(c_div_length - 1);
q <= std_logic_vector(-signed('0' & s_q(c_div_length - 1)));
end if;
end if;
end process p_out_reg;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
computtrial : for i in 0 to c_div_length - 1 generate
-- compute the trial reminder (substractions) (Rt <- 2R - D)
-- substract performed only on the left part of s_r
-- s_trial_r(i) <= std_logic_vector(
-- unsigned('0' & std_logic_vector(s_r(i)((c_work_length - 1) downto (c_work_length - c_div_length - 1))))
-- - unsigned("00" & std_logic_vector(s_d(i))));
s_trial_r(i) <=
('0' & unsigned(s_r(i)((c_work_length - 1) downto (c_work_length - c_div_length - 1))))
- ("00" & unsigned(s_d(i)));
end generate computtrial;
overflow_cur : for i in 0 to c_div_length - 1 generate
s_overflow_cur(i) <= not s_trial_r(i)(c_trial_sign) and s_trial_r(i)(c_trial_overflow);
end generate overflow_cur;
------------------------------------------------------------------------------
--
-- Details on signals shift for the computation of trial remainder
--
------------------------------------------------------------------------------
--
-- Operation performed : Rtrial(n) = 2R(n - 1) - Den << N
--
-- ----------------------------------------------------------------
-- bits 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
-- numbers: 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0
-- ----------------------------------------------------------------
--|
--| | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
--| s_r (shifted) | 0| r(n-1) |
--| | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
--|
--| | - - - - - - - - - - - - - - -
--| s_d (shifted) | 0 0| denominator |0 0 0 0 0 0 0 0 0 0 0 0 0 0
--| | - - - - - - - - - - - - - - -
--|
--| | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
--| s_trial_r | |s|o| |
--| | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
--
--
-- if s = 1 (negative value) : restore previous remainder
-- if o = 1 and s = 0 : the denominator is too small : quotient is infinity
-- if o = 0 and s = 0 : the difference is the new remainder : R(n) <= Rtrial(n)
--
--
-- Signals for debug
--
s_d0 <= s_d(0);
s_d1 <= s_d(1);
s_d2 <= s_d(2);
s_d3 <= s_d(3);
s_d4 <= s_d(4);
s_d5 <= s_d(5);
s_d6 <= s_d(6);
s_d7 <= s_d(7);
s_d8 <= s_d(8);
s_d9 <= s_d(9);
s_d10 <= s_d(10);
s_d11 <= s_d(11);
s_d12 <= s_d(12);
s_d13 <= s_d(13);
s_d14 <= s_d(14);
--s_d15 <= s_d(15);
s_q0 <= s_q(0);
s_q1 <= s_q(1);
s_q2 <= s_q(2);
s_q3 <= s_q(3);
s_q4 <= s_q(4);
s_q5 <= s_q(5);
s_q6 <= s_q(6);
s_q7 <= s_q(7);
s_q8 <= s_q(8);
s_q9 <= s_q(9);
s_q10 <= s_q(10);
s_q11 <= s_q(11);
s_q12 <= s_q(12);
s_q13 <= s_q(13);
s_q14 <= s_q(14);
--s_q15 <= s_q(15);
s_r0 <= s_r(0);
s_r1 <= s_r(1);
s_r2 <= s_r(2);
s_r3 <= s_r(3);
s_r4 <= s_r(4);
s_r5 <= s_r(5);
s_r6 <= s_r(6);
s_r7 <= s_r(7);
s_r8 <= s_r(8);
s_r9 <= s_r(9);
s_r10 <= s_r(10);
s_r11 <= s_r(11);
s_r12 <= s_r(12);
s_r13 <= s_r(13);
s_r14 <= s_r(14);
--s_r15 <= s_r(15);
s_trial_r0 <= s_trial_r(0);
s_trial_r1 <= s_trial_r(1);
s_trial_r2 <= s_trial_r(2);
s_trial_r3 <= s_trial_r(3);
s_trial_r4 <= s_trial_r(4);
s_trial_r5 <= s_trial_r(5);
s_trial_r6 <= s_trial_r(6);
s_trial_r7 <= s_trial_r(7);
s_trial_r8 <= s_trial_r(8);
s_trial_r9 <= s_trial_r(9);
s_trial_r10 <= s_trial_r(10);
s_trial_r11 <= s_trial_r(11);
s_trial_r12 <= s_trial_r(12);
s_trial_r13 <= s_trial_r(13);
s_trial_r14 <= s_trial_r(14);
--s_trial_r15 <= s_trial_r(15);
end archi_dspdiv;
-------------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2009 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
--
-- Pipelined divider usign restoring algorithm
-- total pipe length is (sig_width + 1)
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity dspdiv is
generic (
sig_width : integer := 16);
port (
--@inputs
num : in std_logic_vector((2*sig_width - 1) downto 0);
den : in std_logic_vector((sig_width - 1) downto 0);
clk : in std_logic;
--@outputs;
q : out std_logic_vector((sig_width - 1) downto 0);
r : out std_logic_vector((2*sig_width - 3) downto 0)
);
end dspdiv;
--=----------------------------------------------------------------------------
architecture archi_dspdiv of dspdiv is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_div_length : integer := sig_width - 1;
constant c_work_length : integer := 2*c_div_length;
constant c_trial_length : integer := c_div_length + 2;
constant c_trial_overflow : integer := c_trial_length - 2;
constant c_trial_sign : integer := c_trial_length - 1;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
type t_work_pipe is array(0 to c_div_length) of std_logic_vector((c_work_length - 1) downto 0);
type t_trial_pipe is array(0 to c_div_length) of unsigned((c_trial_length - 1) downto 0);
--type t_trial_pipe is array(0 to c_div_length) of std_logic_vector((c_trial_length - 1) downto 0);
type t_val_pipe is array(0 to c_div_length - 1) of std_logic_vector((c_div_length - 1) downto 0);
type t_bit_pipe is array(0 to c_div_length - 1) of std_logic;
signal s_r : t_work_pipe;
signal s_trial_r : t_trial_pipe;
signal s_d : t_val_pipe;
signal s_q : t_val_pipe;
signal s_sign : t_bit_pipe;
signal s_overflow : t_bit_pipe;
signal s_overflow_cur : t_bit_pipe;
signal s_num_abs : signed((2*sig_width - 1) downto 0);
signal s_num_sign : std_logic;
signal s_den_abs : signed((sig_width - 1) downto 0);
signal s_den_sign : std_logic;
signal s_sign_last : std_logic;
--
-- SIgnals for debug
--
signal s_d0 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d1 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d2 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d3 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d4 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d5 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d6 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d7 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d8 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d9 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d10 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d11 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d12 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d13 : std_logic_vector((c_div_length - 1) downto 0);
signal s_d14 : std_logic_vector((c_div_length - 1) downto 0);
--signal s_d15 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q0 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q1 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q2 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q3 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q4 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q5 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q6 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q7 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q8 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q9 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q10 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q11 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q12 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q13 : std_logic_vector((c_div_length - 1) downto 0);
signal s_q14 : std_logic_vector((c_div_length - 1) downto 0);
--signal s_q15 : std_logic_vector((c_div_length - 1) downto 0);
signal s_r0 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r1 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r2 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r3 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r4 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r5 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r6 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r7 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r8 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r9 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r10 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r11 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r12 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r13 : std_logic_vector((c_work_length - 1) downto 0);
signal s_r14 : std_logic_vector((c_work_length - 1) downto 0);
--signal s_r15 : std_logic_vector((c_work_length - 1) downto 0);
signal s_trial_r0 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r1 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r2 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r3 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r4 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r5 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r6 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r7 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r8 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r9 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r10 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r11 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r12 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r13 : unsigned((c_trial_length - 1) downto 0);
signal s_trial_r14 : unsigned((c_trial_length - 1) downto 0);
--signal s_trial_r15 : unsigned((c_trial_length - 1) downto 0);
begin -- archs_dspdiv
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
--=---------------------------------------------------------------------------
p_div : process (clk)
begin -- process p_div
if rising_edge(clk) then -- rising clock edge
-- s_r(0)((c_div_length - 1) downto 0)<= num(2*sig_width - 2 downto (2*sig_width - c_div_length - 1));
-- s_r(0)((c_work_length - 1) downto c_div_length) <= (others => '0');
s_r(0) <= std_logic_vector(s_num_abs((c_work_length - 1) downto 0));
s_d(0) <= std_logic_vector(s_den_abs((c_div_length - 1) downto 0));
s_sign(0) <= s_num_sign xor s_den_sign;
-- fill unused lines with 0 for simulation
for i in 0 to c_div_length - 2 loop
-- propagation of quotient bits previously computed
s_q(i)((c_div_length - i - 2) downto 0) <= (others => '0');
end loop;
-- pipe
for i in 1 to c_div_length - 1 loop
s_sign(i) <= s_sign(i - 1);
s_d(i) <= s_d(i - 1);
-- propagation of quotient bits previously computed
s_q(i)((c_div_length - 1) downto (c_div_length - i)) <= s_q(i - 1)((c_div_length - 1) downto (c_div_length - i));
-- test for overflow (denominator too small)
s_overflow(i) <= s_overflow(i - 1) or s_overflow_cur(i);
end loop;
s_overflow(0) <= s_overflow_cur(0);
s_sign_last <= s_sign(c_div_length - 1);
for i in 0 to c_div_length - 1 loop
if s_trial_r(i)(c_trial_length - 1) = '0' then --if >= 0
s_r(i + 1)((c_work_length - 1) downto c_div_length) <= std_logic_vector(s_trial_r(i)(c_div_length - 1 downto 0)); -- store trial reminder
s_q(i)(c_div_length - 1 - i) <= '1';
else
-- restore s_r and shift one bit left (R <- 2R)
s_r(i + 1)((c_work_length - 1) downto c_div_length) <= s_r(i)(c_work_length - 2 downto c_div_length - 1);
s_q(i)(c_div_length - 1 - i) <= '0';
end if;
-- The lower part of the remainder is just shifted
s_r(i + 1)((c_div_length - 1) downto 0) <= s_r(i)((c_div_length - 2) downto 0) & '0';
end loop;
end if;
end process p_div;
p_sign : process (num,den)
begin -- process p_sign
if den(sig_width - 1) = '0' then
s_den_abs <= signed(den);
s_den_sign <= '0';
else
s_den_abs <= -signed(den);
s_den_sign <= '1';
end if;
if num(2*sig_width - 1) = '0' then
s_num_abs <= signed(num);
s_num_sign <= '0';
else
s_num_abs <= -signed(num);
s_num_sign <= '1';
end if;
end process p_sign;
p_out_reg : process (clk)
begin -- process p_out_reg
if rising_edge(clk) then -- rising clock edge
if s_overflow(c_div_length - 1) = '1' then
q(sig_width - 2 downto 0) <= (others => '1');
q(sig_width - 1) <= '0';
r <= (others => '0');
elsif s_sign_last = '0' then
r <= s_r(c_div_length - 1);
q <= '0' & s_q(c_div_length - 1);
else
r <= s_r(c_div_length - 1);
q <= std_logic_vector(-signed('0' & s_q(c_div_length - 1)));
end if;
end if;
end process p_out_reg;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
computtrial : for i in 0 to c_div_length - 1 generate
-- compute the trial reminder (substractions) (Rt <- 2R - D)
-- substract performed only on the left part of s_r
-- s_trial_r(i) <= std_logic_vector(
-- unsigned('0' & std_logic_vector(s_r(i)((c_work_length - 1) downto (c_work_length - c_div_length - 1))))
-- - unsigned("00" & std_logic_vector(s_d(i))));
s_trial_r(i) <=
('0' & unsigned(s_r(i)((c_work_length - 1) downto (c_work_length - c_div_length - 1))))
- ("00" & unsigned(s_d(i)));
end generate computtrial;
overflow_cur : for i in 0 to c_div_length - 1 generate
s_overflow_cur(i) <= not s_trial_r(i)(c_trial_sign) and s_trial_r(i)(c_trial_overflow);
end generate overflow_cur;
------------------------------------------------------------------------------
--
-- Details on signals shift for the computation of trial remainder
--
------------------------------------------------------------------------------
--
-- Operation performed : Rtrial(n) = 2R(n - 1) - Den << N
--
-- ----------------------------------------------------------------
-- bits 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
-- numbers: 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0
-- ----------------------------------------------------------------
--|
--| | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
--| s_r (shifted) | 0| r(n-1) |
--| | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
--|
--| | - - - - - - - - - - - - - - -
--| s_d (shifted) | 0 0| denominator |0 0 0 0 0 0 0 0 0 0 0 0 0 0
--| | - - - - - - - - - - - - - - -
--|
--| | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
--| s_trial_r | |s|o| |
--| | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
--
--
-- if s = 1 (negative value) : restore previous remainder
-- if o = 1 and s = 0 : the denominator is too small : quotient is infinity
-- if o = 0 and s = 0 : the difference is the new remainder : R(n) <= Rtrial(n)
--
--
-- Signals for debug
--
s_d0 <= s_d(0);
s_d1 <= s_d(1);
s_d2 <= s_d(2);
s_d3 <= s_d(3);
s_d4 <= s_d(4);
s_d5 <= s_d(5);
s_d6 <= s_d(6);
s_d7 <= s_d(7);
s_d8 <= s_d(8);
s_d9 <= s_d(9);
s_d10 <= s_d(10);
s_d11 <= s_d(11);
s_d12 <= s_d(12);
s_d13 <= s_d(13);
s_d14 <= s_d(14);
--s_d15 <= s_d(15);
s_q0 <= s_q(0);
s_q1 <= s_q(1);
s_q2 <= s_q(2);
s_q3 <= s_q(3);
s_q4 <= s_q(4);
s_q5 <= s_q(5);
s_q6 <= s_q(6);
s_q7 <= s_q(7);
s_q8 <= s_q(8);
s_q9 <= s_q(9);
s_q10 <= s_q(10);
s_q11 <= s_q(11);
s_q12 <= s_q(12);
s_q13 <= s_q(13);
s_q14 <= s_q(14);
--s_q15 <= s_q(15);
s_r0 <= s_r(0);
s_r1 <= s_r(1);
s_r2 <= s_r(2);
s_r3 <= s_r(3);
s_r4 <= s_r(4);
s_r5 <= s_r(5);
s_r6 <= s_r(6);
s_r7 <= s_r(7);
s_r8 <= s_r(8);
s_r9 <= s_r(9);
s_r10 <= s_r(10);
s_r11 <= s_r(11);
s_r12 <= s_r(12);
s_r13 <= s_r(13);
s_r14 <= s_r(14);
--s_r15 <= s_r(15);
s_trial_r0 <= s_trial_r(0);
s_trial_r1 <= s_trial_r(1);
s_trial_r2 <= s_trial_r(2);
s_trial_r3 <= s_trial_r(3);
s_trial_r4 <= s_trial_r(4);
s_trial_r5 <= s_trial_r(5);
s_trial_r6 <= s_trial_r(6);
s_trial_r7 <= s_trial_r(7);
s_trial_r8 <= s_trial_r(8);
s_trial_r9 <= s_trial_r(9);
s_trial_r10 <= s_trial_r(10);
s_trial_r11 <= s_trial_r(11);
s_trial_r12 <= s_trial_r(12);
s_trial_r13 <= s_trial_r(13);
s_trial_r14 <= s_trial_r(14);
--s_trial_r15 <= s_trial_r(15);
end archi_dspdiv;
-------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
-- axi_hthread_reset_core.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: axi_hthread_reset_core.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Jun 24 19:32:07 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.soft_reset;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_hthread_reset_core_v1_00_a;
use axi_hthread_reset_core_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity axi_hthread_reset_core is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"0000FFFF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
reset_port0 : out std_logic;
reset_response_port0 : in std_logic;
reset_port1 : out std_logic;
reset_response_port1 : in std_logic;
reset_port2 : out std_logic;
reset_response_port2 : in std_logic;
reset_port3 : out std_logic;
reset_response_port3 : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_hthread_reset_core;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_hthread_reset_core is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR, -- soft reset space high address
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant RST_NUM_CE : integer := 1;
constant USER_SLV_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG + RST_NUM_CE;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (RST_NUM_CE), -- number of ce for soft reset space
1 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 8;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant RST_CS_INDEX : integer := 0;
constant RST_CE_INDEX : integer := USER_NUM_REG;
constant USER_SLV_CS_INDEX : integer := 1;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_Bus2IP_Reset : std_logic;
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v3_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity axi_hthread_reset_core_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
reset_port0 => reset_port0,
reset_response_port0 => reset_response_port0,
reset_port1 => reset_port1,
reset_response_port1 => reset_response_port1,
reset_port2 => reset_port2,
reset_response_port2 => reset_response_port2,
reset_port3 => reset_port3,
reset_response_port3 => reset_response_port3,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => rst_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS (1 downto 0) is
when "01" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "10" => ipif_IP2Bus_Data <= (others => '0');
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
ipif_Bus2IP_Reset <= not ipif_Bus2IP_Resetn;
end IMP;
|
--------------------------------------------------------------------------------
--
-- Title : cl_text.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Game block for main text
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.ctrl_types_pkg.array8x8;
entity cl_text is
generic(
constant yend : std_logic_vector(4 downto 0):="11000";
constant ystart : std_logic_vector(4 downto 0):="10000";
constant xend : std_logic_vector(6 downto 0):="0011000";
constant xstart : std_logic_vector(6 downto 0):="0010000"
);
port(
-- system signals:
clk : in std_logic;
reset : in std_logic;
-- control signals:
addr_rnd : in std_logic_vector(4 downto 0);
display : in std_logic;
cntgames : in std_logic;
win : in std_logic;
lose : in std_logic;
game : in std_logic;
flash : in std_logic_vector(2 downto 0);
-- vga XoY:
x_char : in std_logic_vector(9 downto 0);
y_char : in std_logic_vector(8 downto 0);
-- out color scheme:
rgb : out std_logic_vector(2 downto 0)
);
end cl_text;
architecture cl_text of cl_text is
component ctrl_8x16_rom is
port(
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end component;
component cl_select_text is
port(
x_char : in std_logic_vector(6 downto 0);
y_char : in std_logic_vector(4 downto 0);
win : in std_logic;
lose : in std_logic;
game : in std_logic;
cntgames: in std_logic;
addr_rnd: in std_logic_vector(4 downto 0);
ch_data : out std_logic_vector(7 downto 0)
);
end component;
signal x_in : std_logic_vector(6 downto 0);
signal y_in : std_logic_vector(4 downto 0);
signal data : std_logic;
signal x_rev : std_logic_vector(2 downto 0);
signal x_del : std_logic_vector(2 downto 0);
signal color : std_logic_vector(2 downto 0):="111";
signal addr_rom : std_logic_vector(10 downto 0);
signal data_rom : std_logic_vector(7 downto 0);
signal data_box : std_logic_vector(7 downto 0);
begin
x_in <= x_char(9 downto 3);
y_in <= y_char(8 downto 4);
x_select_text: cl_select_text
port map (
x_char => x_in,
y_char => y_in,
win => win,
lose => lose,
game => game,
cntgames=> cntgames,
addr_rnd=> addr_rnd,
ch_data => data_box
);
addr_rom <= data_box(6 downto 0) & y_char(3 downto 0) when rising_edge(clk);
x_char_rom: ctrl_8x16_rom
port map (
clk => clk,
addr => addr_rom,
data => data_rom
);
g_rev: for ii in 0 to 2 generate
begin
x_rev(ii) <= not x_char(ii) when rising_edge(clk);
end generate;
x_del <= x_rev when rising_edge(clk);
color <= flash when (x_in > "0011001") and (y_in = "10000") else "100" when (y_in < "00111") else "010";
pr_sw_sel: process(clk, reset) is
begin
if reset = '0' then
data <= '0';
elsif rising_edge(clk) then
if display = '0' then
data <= '0';
else
data <= data_rom(to_integer(unsigned(x_del)));
end if;
end if;
end process;
g_rgb: for ii in 0 to 2 generate
begin
rgb(ii) <= data and color(ii);
end generate;
end cl_text; |
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.0.111.2
-- Module Version: 5.8
--/usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n fmexg_fifo_8k_1025 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo3c00f -type ebfifo -depth 8192 -width 12 -rwidth 12 -no_enable -pe 10 -pf 1025
-- Tue May 7 19:11:06 2019
library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library MACHXO3L;
use MACHXO3L.components.all;
-- synopsys translate_on
entity fmexg_fifo_8k_1025 is
port (
Data: in std_logic_vector(11 downto 0);
WrClock: in std_logic;
RdClock: in std_logic;
WrEn: in std_logic;
RdEn: in std_logic;
Reset: in std_logic;
RPReset: in std_logic;
Q: out std_logic_vector(11 downto 0);
Empty: out std_logic;
Full: out std_logic;
AlmostEmpty: out std_logic;
AlmostFull: out std_logic);
end fmexg_fifo_8k_1025;
architecture Structure of fmexg_fifo_8k_1025 is
-- internal signal declarations
signal scuba_vhi: std_logic;
signal Empty_int: std_logic;
signal Full_int: std_logic;
signal scuba_vlo: std_logic;
-- local component declarations
component VHI
port (Z: out std_logic);
end component;
component VLO
port (Z: out std_logic);
end component;
component FIFO8KB
generic (FULLPOINTER1 : in String; FULLPOINTER : in String;
AFPOINTER1 : in String; AFPOINTER : in String;
AEPOINTER1 : in String; AEPOINTER : in String;
ASYNC_RESET_RELEASE : in String; RESETMODE : in String;
GSR : in String; CSDECODE_R : in String;
CSDECODE_W : in String; REGMODE : in String;
DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
DI12: in std_logic; DI13: in std_logic;
DI14: in std_logic; DI15: in std_logic;
DI16: in std_logic; DI17: in std_logic;
CSW0: in std_logic; CSW1: in std_logic;
CSR0: in std_logic; CSR1: in std_logic;
FULLI: in std_logic; EMPTYI: in std_logic;
WE: in std_logic; RE: in std_logic; ORE: in std_logic;
CLKW: in std_logic; CLKR: in std_logic; RST: in std_logic;
RPRST: in std_logic; DO0: out std_logic;
DO1: out std_logic; DO2: out std_logic;
DO3: out std_logic; DO4: out std_logic;
DO5: out std_logic; DO6: out std_logic;
DO7: out std_logic; DO8: out std_logic;
DO9: out std_logic; DO10: out std_logic;
DO11: out std_logic; DO12: out std_logic;
DO13: out std_logic; DO14: out std_logic;
DO15: out std_logic; DO16: out std_logic;
DO17: out std_logic; EF: out std_logic;
AEF: out std_logic; AFF: out std_logic; FF: out std_logic);
end component;
attribute syn_keep : boolean;
attribute NGD_DRC_MASK : integer;
attribute NGD_DRC_MASK of Structure : architecture is 1;
begin
-- component instantiation statements
fmexg_fifo_8k_1025_0_11: FIFO8KB
generic map (FULLPOINTER1=> "0b01111111111111", FULLPOINTER=> "0b10000000000000",
AFPOINTER1=> "0b00010000000000", AFPOINTER=> "0b00010000000001",
AEPOINTER1=> "0b00000000001011", AEPOINTER=> "0b00000000001010",
ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC",
REGMODE=> "NOREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11",
DATA_WIDTH_R=> 1, DATA_WIDTH_W=> 1)
port map (DI0=>scuba_vlo, DI1=>Data(0), DI2=>scuba_vlo,
DI3=>scuba_vlo, DI4=>scuba_vlo, DI5=>scuba_vlo,
DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>Data(0),
DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
CSW0=>scuba_vhi, CSW1=>scuba_vhi, CSR0=>scuba_vhi,
CSR1=>scuba_vhi, FULLI=>Full_int, EMPTYI=>Empty_int,
WE=>WrEn, RE=>RdEn, ORE=>RdEn, CLKW=>WrClock, CLKR=>RdClock,
RST=>Reset, RPRST=>RPReset, DO0=>Q(0), DO1=>open, DO2=>open,
DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open,
DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open,
DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open,
EF=>Empty_int, AEF=>AlmostEmpty, AFF=>AlmostFull,
FF=>Full_int);
fmexg_fifo_8k_1025_1_10: FIFO8KB
generic map (FULLPOINTER1=> "0b00000000000000", FULLPOINTER=> "0b11111111111111",
AFPOINTER1=> "0b00000000000000", AFPOINTER=> "0b11111111111111",
AEPOINTER1=> "0b00000000000000", AEPOINTER=> "0b11111111111111",
ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC",
REGMODE=> "NOREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11",
DATA_WIDTH_R=> 1, DATA_WIDTH_W=> 1)
port map (DI0=>scuba_vlo, DI1=>Data(1), DI2=>scuba_vlo,
DI3=>scuba_vlo, DI4=>scuba_vlo, DI5=>scuba_vlo,
DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>Data(1),
DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
CSW0=>scuba_vhi, CSW1=>scuba_vhi, CSR0=>scuba_vhi,
CSR1=>scuba_vhi, FULLI=>Full_int, EMPTYI=>Empty_int,
WE=>WrEn, RE=>RdEn, ORE=>RdEn, CLKW=>WrClock, CLKR=>RdClock,
RST=>Reset, RPRST=>RPReset, DO0=>Q(1), DO1=>open, DO2=>open,
DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open,
DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open,
DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open,
EF=>open, AEF=>open, AFF=>open, FF=>open);
fmexg_fifo_8k_1025_2_9: FIFO8KB
generic map (FULLPOINTER1=> "0b00000000000000", FULLPOINTER=> "0b11111111111111",
AFPOINTER1=> "0b00000000000000", AFPOINTER=> "0b11111111111111",
AEPOINTER1=> "0b00000000000000", AEPOINTER=> "0b11111111111111",
ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC",
REGMODE=> "NOREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11",
DATA_WIDTH_R=> 1, DATA_WIDTH_W=> 1)
port map (DI0=>scuba_vlo, DI1=>Data(2), DI2=>scuba_vlo,
DI3=>scuba_vlo, DI4=>scuba_vlo, DI5=>scuba_vlo,
DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>Data(2),
DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
CSW0=>scuba_vhi, CSW1=>scuba_vhi, CSR0=>scuba_vhi,
CSR1=>scuba_vhi, FULLI=>Full_int, EMPTYI=>Empty_int,
WE=>WrEn, RE=>RdEn, ORE=>RdEn, CLKW=>WrClock, CLKR=>RdClock,
RST=>Reset, RPRST=>RPReset, DO0=>Q(2), DO1=>open, DO2=>open,
DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open,
DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open,
DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open,
EF=>open, AEF=>open, AFF=>open, FF=>open);
fmexg_fifo_8k_1025_3_8: FIFO8KB
generic map (FULLPOINTER1=> "0b00000000000000", FULLPOINTER=> "0b11111111111111",
AFPOINTER1=> "0b00000000000000", AFPOINTER=> "0b11111111111111",
AEPOINTER1=> "0b00000000000000", AEPOINTER=> "0b11111111111111",
ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC",
REGMODE=> "NOREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11",
DATA_WIDTH_R=> 1, DATA_WIDTH_W=> 1)
port map (DI0=>scuba_vlo, DI1=>Data(3), DI2=>scuba_vlo,
DI3=>scuba_vlo, DI4=>scuba_vlo, DI5=>scuba_vlo,
DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>Data(3),
DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
CSW0=>scuba_vhi, CSW1=>scuba_vhi, CSR0=>scuba_vhi,
CSR1=>scuba_vhi, FULLI=>Full_int, EMPTYI=>Empty_int,
WE=>WrEn, RE=>RdEn, ORE=>RdEn, CLKW=>WrClock, CLKR=>RdClock,
RST=>Reset, RPRST=>RPReset, DO0=>Q(3), DO1=>open, DO2=>open,
DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open,
DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open,
DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open,
EF=>open, AEF=>open, AFF=>open, FF=>open);
fmexg_fifo_8k_1025_4_7: FIFO8KB
generic map (FULLPOINTER1=> "0b00000000000000", FULLPOINTER=> "0b11111111111111",
AFPOINTER1=> "0b00000000000000", AFPOINTER=> "0b11111111111111",
AEPOINTER1=> "0b00000000000000", AEPOINTER=> "0b11111111111111",
ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC",
REGMODE=> "NOREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11",
DATA_WIDTH_R=> 1, DATA_WIDTH_W=> 1)
port map (DI0=>scuba_vlo, DI1=>Data(4), DI2=>scuba_vlo,
DI3=>scuba_vlo, DI4=>scuba_vlo, DI5=>scuba_vlo,
DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>Data(4),
DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
CSW0=>scuba_vhi, CSW1=>scuba_vhi, CSR0=>scuba_vhi,
CSR1=>scuba_vhi, FULLI=>Full_int, EMPTYI=>Empty_int,
WE=>WrEn, RE=>RdEn, ORE=>RdEn, CLKW=>WrClock, CLKR=>RdClock,
RST=>Reset, RPRST=>RPReset, DO0=>Q(4), DO1=>open, DO2=>open,
DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open,
DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open,
DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open,
EF=>open, AEF=>open, AFF=>open, FF=>open);
fmexg_fifo_8k_1025_5_6: FIFO8KB
generic map (FULLPOINTER1=> "0b00000000000000", FULLPOINTER=> "0b11111111111111",
AFPOINTER1=> "0b00000000000000", AFPOINTER=> "0b11111111111111",
AEPOINTER1=> "0b00000000000000", AEPOINTER=> "0b11111111111111",
ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC",
REGMODE=> "NOREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11",
DATA_WIDTH_R=> 1, DATA_WIDTH_W=> 1)
port map (DI0=>scuba_vlo, DI1=>Data(5), DI2=>scuba_vlo,
DI3=>scuba_vlo, DI4=>scuba_vlo, DI5=>scuba_vlo,
DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>Data(5),
DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
CSW0=>scuba_vhi, CSW1=>scuba_vhi, CSR0=>scuba_vhi,
CSR1=>scuba_vhi, FULLI=>Full_int, EMPTYI=>Empty_int,
WE=>WrEn, RE=>RdEn, ORE=>RdEn, CLKW=>WrClock, CLKR=>RdClock,
RST=>Reset, RPRST=>RPReset, DO0=>Q(5), DO1=>open, DO2=>open,
DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open,
DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open,
DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open,
EF=>open, AEF=>open, AFF=>open, FF=>open);
fmexg_fifo_8k_1025_6_5: FIFO8KB
generic map (FULLPOINTER1=> "0b00000000000000", FULLPOINTER=> "0b11111111111111",
AFPOINTER1=> "0b00000000000000", AFPOINTER=> "0b11111111111111",
AEPOINTER1=> "0b00000000000000", AEPOINTER=> "0b11111111111111",
ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC",
REGMODE=> "NOREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11",
DATA_WIDTH_R=> 1, DATA_WIDTH_W=> 1)
port map (DI0=>scuba_vlo, DI1=>Data(6), DI2=>scuba_vlo,
DI3=>scuba_vlo, DI4=>scuba_vlo, DI5=>scuba_vlo,
DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>Data(6),
DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
CSW0=>scuba_vhi, CSW1=>scuba_vhi, CSR0=>scuba_vhi,
CSR1=>scuba_vhi, FULLI=>Full_int, EMPTYI=>Empty_int,
WE=>WrEn, RE=>RdEn, ORE=>RdEn, CLKW=>WrClock, CLKR=>RdClock,
RST=>Reset, RPRST=>RPReset, DO0=>Q(6), DO1=>open, DO2=>open,
DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open,
DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open,
DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open,
EF=>open, AEF=>open, AFF=>open, FF=>open);
fmexg_fifo_8k_1025_7_4: FIFO8KB
generic map (FULLPOINTER1=> "0b00000000000000", FULLPOINTER=> "0b11111111111111",
AFPOINTER1=> "0b00000000000000", AFPOINTER=> "0b11111111111111",
AEPOINTER1=> "0b00000000000000", AEPOINTER=> "0b11111111111111",
ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC",
REGMODE=> "NOREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11",
DATA_WIDTH_R=> 1, DATA_WIDTH_W=> 1)
port map (DI0=>scuba_vlo, DI1=>Data(7), DI2=>scuba_vlo,
DI3=>scuba_vlo, DI4=>scuba_vlo, DI5=>scuba_vlo,
DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>Data(7),
DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
CSW0=>scuba_vhi, CSW1=>scuba_vhi, CSR0=>scuba_vhi,
CSR1=>scuba_vhi, FULLI=>Full_int, EMPTYI=>Empty_int,
WE=>WrEn, RE=>RdEn, ORE=>RdEn, CLKW=>WrClock, CLKR=>RdClock,
RST=>Reset, RPRST=>RPReset, DO0=>Q(7), DO1=>open, DO2=>open,
DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open,
DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open,
DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open,
EF=>open, AEF=>open, AFF=>open, FF=>open);
fmexg_fifo_8k_1025_8_3: FIFO8KB
generic map (FULLPOINTER1=> "0b00000000000000", FULLPOINTER=> "0b11111111111111",
AFPOINTER1=> "0b00000000000000", AFPOINTER=> "0b11111111111111",
AEPOINTER1=> "0b00000000000000", AEPOINTER=> "0b11111111111111",
ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC",
REGMODE=> "NOREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11",
DATA_WIDTH_R=> 1, DATA_WIDTH_W=> 1)
port map (DI0=>scuba_vlo, DI1=>Data(8), DI2=>scuba_vlo,
DI3=>scuba_vlo, DI4=>scuba_vlo, DI5=>scuba_vlo,
DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>Data(8),
DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
CSW0=>scuba_vhi, CSW1=>scuba_vhi, CSR0=>scuba_vhi,
CSR1=>scuba_vhi, FULLI=>Full_int, EMPTYI=>Empty_int,
WE=>WrEn, RE=>RdEn, ORE=>RdEn, CLKW=>WrClock, CLKR=>RdClock,
RST=>Reset, RPRST=>RPReset, DO0=>Q(8), DO1=>open, DO2=>open,
DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open,
DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open,
DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open,
EF=>open, AEF=>open, AFF=>open, FF=>open);
fmexg_fifo_8k_1025_9_2: FIFO8KB
generic map (FULLPOINTER1=> "0b00000000000000", FULLPOINTER=> "0b11111111111111",
AFPOINTER1=> "0b00000000000000", AFPOINTER=> "0b11111111111111",
AEPOINTER1=> "0b00000000000000", AEPOINTER=> "0b11111111111111",
ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC",
REGMODE=> "NOREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11",
DATA_WIDTH_R=> 1, DATA_WIDTH_W=> 1)
port map (DI0=>scuba_vlo, DI1=>Data(9), DI2=>scuba_vlo,
DI3=>scuba_vlo, DI4=>scuba_vlo, DI5=>scuba_vlo,
DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>Data(9),
DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
CSW0=>scuba_vhi, CSW1=>scuba_vhi, CSR0=>scuba_vhi,
CSR1=>scuba_vhi, FULLI=>Full_int, EMPTYI=>Empty_int,
WE=>WrEn, RE=>RdEn, ORE=>RdEn, CLKW=>WrClock, CLKR=>RdClock,
RST=>Reset, RPRST=>RPReset, DO0=>Q(9), DO1=>open, DO2=>open,
DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open,
DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open,
DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open,
EF=>open, AEF=>open, AFF=>open, FF=>open);
fmexg_fifo_8k_1025_10_1: FIFO8KB
generic map (FULLPOINTER1=> "0b00000000000000", FULLPOINTER=> "0b11111111111111",
AFPOINTER1=> "0b00000000000000", AFPOINTER=> "0b11111111111111",
AEPOINTER1=> "0b00000000000000", AEPOINTER=> "0b11111111111111",
ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC",
REGMODE=> "NOREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11",
DATA_WIDTH_R=> 1, DATA_WIDTH_W=> 1)
port map (DI0=>scuba_vlo, DI1=>Data(10), DI2=>scuba_vlo,
DI3=>scuba_vlo, DI4=>scuba_vlo, DI5=>scuba_vlo,
DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>Data(10),
DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
CSW0=>scuba_vhi, CSW1=>scuba_vhi, CSR0=>scuba_vhi,
CSR1=>scuba_vhi, FULLI=>Full_int, EMPTYI=>Empty_int,
WE=>WrEn, RE=>RdEn, ORE=>RdEn, CLKW=>WrClock, CLKR=>RdClock,
RST=>Reset, RPRST=>RPReset, DO0=>Q(10), DO1=>open, DO2=>open,
DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open,
DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open,
DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open,
EF=>open, AEF=>open, AFF=>open, FF=>open);
scuba_vhi_inst: VHI
port map (Z=>scuba_vhi);
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
fmexg_fifo_8k_1025_11_0: FIFO8KB
generic map (FULLPOINTER1=> "0b00000000000000", FULLPOINTER=> "0b11111111111111",
AFPOINTER1=> "0b00000000000000", AFPOINTER=> "0b11111111111111",
AEPOINTER1=> "0b00000000000000", AEPOINTER=> "0b11111111111111",
ASYNC_RESET_RELEASE=> "SYNC", GSR=> "DISABLED", RESETMODE=> "ASYNC",
REGMODE=> "NOREG", CSDECODE_R=> "0b11", CSDECODE_W=> "0b11",
DATA_WIDTH_R=> 1, DATA_WIDTH_W=> 1)
port map (DI0=>scuba_vlo, DI1=>Data(11), DI2=>scuba_vlo,
DI3=>scuba_vlo, DI4=>scuba_vlo, DI5=>scuba_vlo,
DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>Data(11),
DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
CSW0=>scuba_vhi, CSW1=>scuba_vhi, CSR0=>scuba_vhi,
CSR1=>scuba_vhi, FULLI=>Full_int, EMPTYI=>Empty_int,
WE=>WrEn, RE=>RdEn, ORE=>RdEn, CLKW=>WrClock, CLKR=>RdClock,
RST=>Reset, RPRST=>RPReset, DO0=>Q(11), DO1=>open, DO2=>open,
DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open,
DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open,
DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open,
EF=>open, AEF=>open, AFF=>open, FF=>open);
Empty <= Empty_int;
Full <= Full_int;
end Structure;
-- synopsys translate_off
library MACHXO3L;
configuration Structure_CON of fmexg_fifo_8k_1025 is
for Structure
for all:VHI use entity MACHXO3L.VHI(V); end for;
for all:VLO use entity MACHXO3L.VLO(V); end for;
for all:FIFO8KB use entity MACHXO3L.FIFO8KB(V); end for;
end for;
end Structure_CON;
-- synopsys translate_on
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/fft_16_bit.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Model base rate: 0.2
-- Target subsystem base rate: 0.2
--
--
-- Clock Enable Sample Time
-- -------------------------------------------------------------
-- ce_out 0.2
-- -------------------------------------------------------------
--
--
-- Output Signal Clock Enable Sample Time
-- -------------------------------------------------------------
-- Out1_re ce_out 0.2
-- Out1_im ce_out 0.2
-- Out2 ce_out 0.2
-- -------------------------------------------------------------
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: fft_16_bit
-- Source Path: fft_16_bit
-- Hierarchy Level: 0
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.fft_16_bit_pkg.ALL;
ENTITY fft_16_bit IS
PORT( clk : IN std_logic;
reset : IN std_logic;
clk_enable : IN std_logic;
In1 : IN vector_of_std_logic_vector16(0 TO 15); -- uint16 [16]
ce_out : OUT std_logic;
Out1_re : OUT vector_of_std_logic_vector21(0 TO 15); -- sfix21 [16]
Out1_im : OUT vector_of_std_logic_vector21(0 TO 15); -- sfix21 [16]
Out2 : OUT std_logic
);
END fft_16_bit;
ARCHITECTURE rtl OF fft_16_bit IS
-- Component Declarations
COMPONENT FFT_HDL_Optimized
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dataIn : IN vector_of_std_logic_vector16(0 TO 15); -- uint16 [16]
validIn : IN std_logic;
dataOut_re : OUT vector_of_std_logic_vector21(0 TO 15); -- sfix21 [16]
dataOut_im : OUT vector_of_std_logic_vector21(0 TO 15); -- sfix21 [16]
validOut : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : FFT_HDL_Optimized
USE ENTITY work.FFT_HDL_Optimized(rtl);
-- Signals
SIGNAL Constant_out1 : std_logic;
SIGNAL FFT_HDL_Optimized_out1_re : vector_of_std_logic_vector21(0 TO 15); -- ufix21 [16]
SIGNAL FFT_HDL_Optimized_out1_im : vector_of_std_logic_vector21(0 TO 15); -- ufix21 [16]
SIGNAL FFT_HDL_Optimized_out2 : std_logic;
BEGIN
u_FFT_HDL_Optimized : FFT_HDL_Optimized
PORT MAP( clk => clk,
reset => reset,
enb => clk_enable,
dataIn => In1, -- uint16 [16]
validIn => Constant_out1,
dataOut_re => FFT_HDL_Optimized_out1_re, -- sfix21 [16]
dataOut_im => FFT_HDL_Optimized_out1_im, -- sfix21 [16]
validOut => FFT_HDL_Optimized_out2
);
Constant_out1 <= '1';
ce_out <= clk_enable;
Out1_re <= FFT_HDL_Optimized_out1_re;
Out1_im <= FFT_HDL_Optimized_out1_im;
Out2 <= FFT_HDL_Optimized_out2;
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity complete_pic is
generic(
IID_WIDTH : integer := 3;
REG_SIZE : integer := 9;
CMD_WIDTH : integer := 4;
C_NUM_INTERRUPTS : integer := 8
);
port
(
--User Interface Port(s)
msg_chan_channelDataIn : out std_logic_vector(0 to (8 - 1));
msg_chan_channelDataOut : in std_logic_vector(0 to (8 - 1));
msg_chan_exists : in std_logic;
msg_chan_full : in std_logic;
msg_chan_channelRead : out std_logic;
msg_chan_channelWrite : out std_logic;
go : in std_logic;
ack : out std_logic;
TID_IN : in std_logic_vector(0 to 7);
IID_IN : in std_logic_vector(0 to IID_WIDTH - 1);
CMD_IN : in std_logic_vector(0 to CMD_WIDTH - 1);
RET_OUT : out std_logic_vector(0 to 7);
TID_OUT : out std_logic_vector(0 to 7);
--Controller Port(s)
interrupts_in : in std_logic_vector(0 to C_NUM_INTERRUPTS - 1);
clock_sig : in std_logic;
reset_sig : in std_logic
);
end entity complete_pic;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of complete_pic is
-- Component Definitions
COMPONENT PIC
GENERIC(
IID_WIDTH : integer := 3;
REG_SIZE : integer := 9;
CMD_WIDTH : integer := 4;
C_NUM_INTERRUPTS : integer := 8
);
PORT(
msg_chan_channelDataIn : OUT std_logic_vector(0 to 7);
msg_chan_channelDataOut : IN std_logic_vector(0 to 7);
msg_chan_exists : IN std_logic;
msg_chan_full : IN std_logic;
msg_chan_channelRead : OUT std_logic;
msg_chan_channelWrite : OUT std_logic;
go : IN std_logic;
ack : OUT std_logic;
TID_IN : IN std_logic_vector(0 to 7);
IID_IN : IN std_logic_vector(0 to IID_WIDTH-1);
CMD_IN : IN std_logic_vector(0 to CMD_WIDTH-1);
RUPT_IN : IN std_logic_vector(0 to C_NUM_INTERRUPTS-1);
IER_OUT : OUT std_logic_vector(0 to C_NUM_INTERRUPTS-1);
IAR_OUT : OUT std_logic_vector(0 to C_NUM_INTERRUPTS-1);
RET_OUT : OUT std_logic_vector(0 to 7);
TID_OUT : OUT std_logic_vector(0 to 7);
clock_sig : IN std_logic;
reset_sig : IN std_logic
);
END COMPONENT;
COMPONENT INTC
generic(
C_NUM_INTERRUPTS : integer := 8;
NEW_IID_WIDTH : integer := 3
);
PORT(
interrupts_in : IN std_logic_vector(0 to C_NUM_INTERRUPTS-1);
ier_in : IN std_logic_vector(0 to C_NUM_INTERRUPTS-1);
iar_in : IN std_logic_vector(0 to C_NUM_INTERRUPTS-1);
interrupts_out : OUT std_logic_vector(0 to C_NUM_INTERRUPTS-1);
clock_sig : IN std_logic;
reset_sig : IN std_logic
);
END COMPONENT;
-- Signal Definitions
signal IER_sig : std_logic_vector(0 to C_NUM_INTERRUPTS-1);
signal IAR_sig : std_logic_vector(0 to C_NUM_INTERRUPTS-1);
signal PEND_sig : std_logic_vector(0 to C_NUM_INTERRUPTS-1);
-- Calculate the log base 2 of some natural number. This function can be
-- used to determine the minimum number of bits needed to represent the
-- given natural number.
function log2( n : in natural ) return positive is
begin
if n <= 2 then
return 1;
else
return 1 + log2(n/2);
end if;
end function log2;
begin
-- Component Interconnection
PIC_LOGIC : PIC
generic map(
IID_WIDTH => IID_WIDTH,
REG_SIZE => REG_SIZE,
CMD_WIDTH => CMD_WIDTH,
C_NUM_INTERRUPTS => C_NUM_INTERRUPTS
)
port map(
msg_chan_channelDataIn => msg_chan_channelDataIn,
msg_chan_channelDataOut => msg_chan_channelDataOut,
msg_chan_exists => msg_chan_exists,
msg_chan_full => msg_chan_full,
msg_chan_channelRead => msg_chan_channelRead,
msg_chan_channelWrite => msg_chan_channelWrite,
go => go,
ack => ack,
TID_IN => TID_IN,
IID_IN => IID_IN,
CMD_IN => CMD_IN,
RUPT_IN => PEND_sig,
IER_OUT => IER_sig,
IAR_OUT => IAR_sig,
RET_OUT => RET_OUT,
TID_OUT => TID_OUT,
clock_sig => clock_sig,
reset_sig => reset_sig
);
INTC_LOGIC : INTC
generic map(
NEW_IID_WIDTH => IID_WIDTH,
C_NUM_INTERRUPTS => C_NUM_INTERRUPTS
)
port map(
interrupts_in => interrupts_in,
ier_in => IER_sig,
iar_in => IAR_sig,
interrupts_out => PEND_sig,
clock_sig => clock_sig,
reset_sig => reset_sig
);
end architecture implementation;
|
----------------------------------------------------------------------------------
-- Company: TU Vienna
-- Engineer: Georg Blemenschitz
--
-- Create Date: 21:57:29 01/28/2010
-- Design Name: SPI
-- Module Name: SPIControl - RTL
-- Description: Control module for SPI
--
-- Revision:
-- Revision 0.01 - File Created
--
-- Associated Testbench:
-- tb_SPIControl.vhd
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.Utils.all;
entity SPIControl is
Generic (
DataWidth : integer range 2 to 64 := 8);
Port (
Reset_n : in STD_LOGIC;
Clk : in STD_LOGIC;
-- SPI config param
CPOL_i : in STD_LOGIC;
CPHA_i : in STD_LOGIC;
-- SPI clock output
SCK_o : out STD_LOGIC;
-- SPI control signals
Transmission_o : out STD_LOGIC;
EnFrqDivider_o : out STD_LOGIC;
NextStep_i : in STD_LOGIC;
LdShifter_o : out STD_LOGIC;
EnShift_o : out STD_LOGIC;
EnSample_o : out STD_LOGIC;
WrFIFOEmpty_i : in STD_LOGIC;
RdWriteFIFO_o : out STD_LOGIC;
RdFIFOFull_i : in STD_LOGIC;
LdReadFIFO_o : out STD_LOGIC);
end SPIControl;
|
entity tb_asgn06 is
end tb_asgn06;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn06 is
signal s0 : std_logic;
signal clk : std_logic;
signal r : std_logic_vector (65 downto 0);
begin
dut: entity work.asgn06
port map (clk => clk, s0 => s0, r => r);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
s0 <= '0';
pulse;
assert r (0) = '1' severity failure;
assert r (64 downto 1) = x"ffff_eeee_dddd_cccc" severity failure;
assert r (65) = '1' severity failure;
s0 <= '1';
pulse;
assert r (0) = '0' severity failure;
assert r (64 downto 1) = x"ffff_eeee_dddd_cc9c" severity failure;
assert r (65) = '0' severity failure;
wait;
end process;
end behav;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
pcie_target_simulation : integer := 0; -- set to 1 to test pci express, only if pcie_target is enabled
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := 40;
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(15 downto 0);
signal button : std_logic_vector(3 downto 0) := "0000";
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal ctsn1, rtsn1 : std_ulogic;
signal ctsn2, rtsn2 : std_ulogic;
signal phy_mii_data: std_logic; -- ethernet PHY interface
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_mii_int_n : std_ulogic;
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr3_tdqs_n : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_reset_n: std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal sysace_mpa : std_logic_vector(6 downto 0);
signal sysace_mpce : std_ulogic;
signal sysace_mpirq : std_ulogic;
signal sysace_mpoe : std_ulogic;
signal sysace_mpwe : std_ulogic;
signal sysace_d : std_logic_vector(7 downto 0);
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(3 downto 0); -- I/O port
signal led : std_logic_vector(3 downto 0); -- I/O port
constant lresp : boolean := false;
-----------------------------------------------------FOR PCIE---------------
function REF_CLK_HALF_CYCLE(FREQ_SEL : integer) return integer is
begin
case FREQ_SEL is
when 0 => return 5000; -- 100 MHz / 5000 ps half-cycle
when 1 => return 4000; -- 125 MHz / 4000 ps half-cycle
when others => return 1; -- invalid case
end case;
end REF_CLK_HALF_CYCLE;
component xilinx_pcie_2_0_rport_v6 is
generic
(
REF_CLK_FREQ : integer := 0;
ALLOW_X8_GEN2 : boolean := FALSE;
PL_FAST_TRAIN : boolean := FALSE;
LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
DEVICE_ID : bit_vector := X"0007";
LINK_CAP_MAX_LINK_WIDTH : bit_vector := X"08";
LTSSM_MAX_LINK_WIDTH : bit_vector := X"08";
LINK_CAP_MAX_LINK_WIDTH_int : integer := 8;
LINK_CTRL2_TARGET_LINK_SPEED : bit_vector := X"2";
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
USER_CLK_FREQ : integer := 3;
VC0_TX_LASTPACKET : integer := 31;
VC0_RX_RAM_LIMIT : bit_vector := X"03FF";
VC0_TOTAL_CREDITS_CD : integer := 154;
VC0_TOTAL_CREDITS_PD : integer := 154
);
port (
sys_clk : in std_logic;
sys_reset_n : in std_logic;
pci_exp_rxn : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_rxp : in std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_txn : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0);
pci_exp_txp : out std_logic_vector((LINK_CAP_MAX_LINK_WIDTH_int - 1) downto 0)
);
end component xilinx_pcie_2_0_rport_v6;
component sys_clk_gen is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk : out std_logic
);
end component sys_clk_gen;
component sys_clk_gen_ds is
generic
(
HALFCYCLE : integer := 500;
OFFSET : integer := 0
);
port
(
sys_clk_p : out std_logic;
sys_clk_n : out std_logic
);
end component sys_clk_gen_ds;
--
-- System reset
--
signal sys_reset_n : std_logic;
--
-- System clocks
--
signal rp_sys_clk : std_logic;
signal ep_sys_clk_p : std_logic;
signal ep_sys_clk_n : std_logic;
--
-- PCI-Express Serial Interconnect
--
signal ep_pci_exp_txn : std_logic_vector(0 downto 0);
signal ep_pci_exp_txp : std_logic_vector(0 downto 0);
signal rp_pci_exp_txn : std_logic_vector(0 downto 0);
signal rp_pci_exp_txp : std_logic_vector(0 downto 0);
--
-- Misc. signals
--
signal led_0 : std_logic;
signal led_1 : std_logic;
signal led_2 : std_logic;
-----------------------------------------------pcie end--------------
begin
-- clock and reset
clk27 <= not clk27 after ct * 1 ns;
clk33 <= not clk33 after 15 ns;
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch <= "0000";
---------------------pcie----------------------------------------------
pcie_sim: if pcie_target_simulation = 1 generate
RP : xilinx_pcie_2_0_rport_v6
generic map (
REF_CLK_FREQ => 1,
PL_FAST_TRAIN => TRUE,
ALLOW_X8_GEN2 => FALSE,
LINK_CAP_MAX_LINK_SPEED => X"1",
DEVICE_ID => X"0007",
LINK_CAP_MAX_LINK_WIDTH => X"01",
LTSSM_MAX_LINK_WIDTH => X"01",
LINK_CAP_MAX_LINK_WIDTH_int => 1,
LINK_CTRL2_TARGET_LINK_SPEED => X"1",
DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2,
USER_CLK_FREQ => 3,
VC0_TX_LASTPACKET => 31,
VC0_RX_RAM_LIMIT => X"03FF",
VC0_TOTAL_CREDITS_CD => 154,
VC0_TOTAL_CREDITS_PD => 154
)
port map (
-- SYS Inteface
sys_clk => rp_sys_clk,
sys_reset_n => sys_reset_n,
-- PCI-Express Interface
pci_exp_txn => rp_pci_exp_txn,
pci_exp_txp => rp_pci_exp_txp,
pci_exp_rxn => ep_pci_exp_txn,
pci_exp_rxp => ep_pci_exp_txp
);
--
-- Generate system clocks and reset
--
CLK_GEN_RP : sys_clk_gen
generic map (
HALFCYCLE => REF_CLK_HALF_CYCLE(1),
OFFSET => 0
)
port map (
sys_clk => rp_sys_clk
);
CLK_GEN_EP : sys_clk_gen_ds
generic map (
HALFCYCLE => REF_CLK_HALF_CYCLE(1),
OFFSET => 0
)
port map (
sys_clk_p => ep_sys_clk_p,
sys_clk_n => ep_sys_clk_n
);
BOARD_INIT : process
begin
report("[" & time'image(now) & "] : System Reset Asserted...");
sys_reset_n <= '0';
for n in 0 to 499 loop
wait until rising_edge(ep_sys_clk_p);
end loop;
report("[" & time'image(now) & "] : System Reset De-asserted...");
sys_reset_n <= '1';
wait until falling_edge(sys_reset_n); -- forever
end process BOARD_INIT;
end generate;
--------------------------------------pcie---------------------------
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk27, clk200p, clk200n, clk33, address(24 downto 1),
data, oen, writen, romsn,
ddr_clk, ddr_clkb, ddr_cke, ddr_odt, ddr_reset_n, ddr_we, ddr_ras, ddr_cas, ddr_dm,
ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_rzq, ddr_zio,
txd1, rxd1, ctsn1, rtsn1, button,
switch, led,
phy_gtx_clk, phy_mii_data, phy_tx_clk, phy_rx_clk,
phy_rx_data, phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data,
phy_tx_en, phy_tx_er, phy_mii_clk, phy_rst_n, phy_mii_int_n,
iic_scl, iic_sda, ddc_scl, ddc_sda,
dvi_iic_scl, dvi_iic_sda,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
spi_sel_n, spi_clk, spi_mosi, ep_pci_exp_txn(0), ep_pci_exp_txp(0), rp_pci_exp_txn(0),
rp_pci_exp_txp(0), ep_sys_clk_p, ep_sys_clk_n, sys_reset_n,
sysace_mpa, sysace_mpce, sysace_mpirq, sysace_mpoe,
sysace_mpwe, sysace_d
);
-- prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
-- port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
-- writen, oen);
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 24, fname => promfile)
port map (address(24 downto 1), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
address(0) <= '0';
u1 : ddr3ram
generic map (
width => 16, abits => 13, fname => sdramfile,
speedbin => 3,
ldguard => 1
)
port map (
ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb, odt => ddr_odt,
rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, resetn => ddr_reset_n,
dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn,
doload => led(2)
);
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
phy_mii_data <= 'H';
p0: phy
generic map (address => 7)
port map(phy_rst_n, phy_mii_data, phy_tx_clk, phy_rx_clk, phy_rx_data,
phy_dv, phy_rx_er, phy_col, phy_crs, phy_tx_data, phy_tx_en,
phy_tx_er, phy_mii_clk, phy_gtx_clk);
end generate;
sysace_mpirq <= '0';
sysace_d <= (others => 'Z');
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
end ;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file counter16.vhd when simulating
-- the core, counter16. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY counter16 IS
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END counter16;
ARCHITECTURE counter16_a OF counter16 IS
-- synthesis translate_off
COMPONENT wrapped_counter16
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_counter16 USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
GENERIC MAP (
c_ainit_val => "0",
c_ce_overrides_sync => 0,
c_count_by => "1",
c_count_mode => 0,
c_count_to => "1",
c_fb_latency => 0,
c_has_ce => 0,
c_has_load => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_has_thresh0 => 0,
c_implementation => 0,
c_latency => 1,
c_load_low => 0,
c_restrict_count => 0,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_thresh0_value => "1",
c_verbosity => 0,
c_width => 16,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_counter16
PORT MAP (
clk => clk,
q => q
);
-- synthesis translate_on
END counter16_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file counter16.vhd when simulating
-- the core, counter16. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY counter16 IS
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END counter16;
ARCHITECTURE counter16_a OF counter16 IS
-- synthesis translate_off
COMPONENT wrapped_counter16
PORT (
clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_counter16 USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
GENERIC MAP (
c_ainit_val => "0",
c_ce_overrides_sync => 0,
c_count_by => "1",
c_count_mode => 0,
c_count_to => "1",
c_fb_latency => 0,
c_has_ce => 0,
c_has_load => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_has_thresh0 => 0,
c_implementation => 0,
c_latency => 1,
c_load_low => 0,
c_restrict_count => 0,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_thresh0_value => "1",
c_verbosity => 0,
c_width => 16,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_counter16
PORT MAP (
clk => clk,
q => q
);
-- synthesis translate_on
END counter16_a;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc948.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00948ent IS
END c06s01b00x00p10n01i00948ent;
ARCHITECTURE c06s01b00x00p10n01i00948arch OF c06s01b00x00p10n01i00948ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
type R2 is record
RE2: R1;
end record;
variable V1: BOOLEAN;
BEGIN
V1 := R2'(RE2=>R1'(RE1=>TRUE)).RE2.RE1;
-- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s01b00x00p10n01i00948 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00948arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc948.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00948ent IS
END c06s01b00x00p10n01i00948ent;
ARCHITECTURE c06s01b00x00p10n01i00948arch OF c06s01b00x00p10n01i00948ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
type R2 is record
RE2: R1;
end record;
variable V1: BOOLEAN;
BEGIN
V1 := R2'(RE2=>R1'(RE1=>TRUE)).RE2.RE1;
-- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s01b00x00p10n01i00948 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00948arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc948.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00948ent IS
END c06s01b00x00p10n01i00948ent;
ARCHITECTURE c06s01b00x00p10n01i00948arch OF c06s01b00x00p10n01i00948ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
end record;
type R2 is record
RE2: R1;
end record;
variable V1: BOOLEAN;
BEGIN
V1 := R2'(RE2=>R1'(RE1=>TRUE)).RE2.RE1;
-- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s01b00x00p10n01i00948 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00948arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.03.2014 15:08:57
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
Port ( clk_raw : in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (7 downto 0);
btn : in STD_LOGIC_VECTOR (4 downto 0);
led : out STD_LOGIC_VECTOR (7 downto 0);
VGA_DATA : out STD_LOGIC_VECTOR (11 downto 0);
VGA_HSYNC : out STD_LOGIC;
VGA_VSYNC : out STD_LOGIC
);
end top;
architecture Behavioral of top is
constant vga_width : integer := 1920;
constant vga_height : integer := 1200;
constant dds_mag : integer := 16;
constant delay_length : integer := 14;
constant xwidth : integer := log2(vga_width);
constant ywidth : integer := log2(vga_height);
constant str_chars: integer := 50;
signal dbtn : std_logic_vector(4 downto 0);
signal clk_100MHz: std_logic;
signal clk_250MHz: std_logic;
signal ch1_x: std_logic_vector(xwidth-1 downto 0);
signal ch1_y: std_logic_vector(ywidth-1 downto 0);
signal ch1_trigger: std_logic_vector(ywidth-1 downto 0);
signal ch1_update: std_logic;
signal ch2_x: std_logic_vector(xwidth-1 downto 0);
signal ch2_y: std_logic_vector(ywidth-1 downto 0);
signal ch2_trigger: std_logic_vector(ywidth-1 downto 0);
signal ch2_update: std_logic;
signal mag: std_logic_vector(ywidth-1 downto 0);
signal mostsig: std_logic_vector(5 downto 0);
signal offset: std_logic_vector(ywidth-1 downto 0);
signal trigger1_enable: std_logic;
signal str : String(1 to str_chars);
signal str_std : std_logic_vector(8*str_chars-1 downto 0);
signal vline: std_logic_vector(ywidth-1 downto 0);
signal vline_clear: std_logic;
signal vline_enb: std_logic;
signal vline_enb_buf: std_logic;
signal delay_index: integer range 0 to 13 ;
signal amplitude : std_logic_vector(1 downto 0);
signal phase : std_logic_vector(15 downto 0);
signal dds_out: std_logic_vector(31 downto 0);
alias sine_raw: std_logic_vector(15 downto 0) is dds_out(15 downto 0);
alias cosine_raw: std_logic_vector(15 downto 0) is dds_out(31 downto 16);
signal sine_out: std_logic_vector(dds_mag-1 downto 0);
signal cosine_out: std_logic_vector(dds_mag-1 downto 0);
signal signed_ch1 :std_logic_vector(dds_mag-1 downto 0);
signal signed_ch2 :std_logic_vector(ywidth-1 downto 0);
signal scaled_ch1 :std_logic_vector(dds_mag-1 downto 0);
signal scaled_ch2 :std_logic_vector(ywidth-1 downto 0);
signal sw_buffer : std_logic_vector(7 downto 0);
signal valid: std_logic;
signal nums_of_zeros: integer;
signal w: integer;
signal fe: integer;
signal fir_input: STD_LOGIC_VECTOR(15 DOWNTO 0);
signal fir_output: STD_LOGIC_VECTOR(39 DOWNTO 0);
signal fir_valid: std_logic;
signal fir_ready: std_logic;
signal fir_extracted: std_logic_vector(15 downto 0);
signal time_val: std_logic_vector(6 downto 0);
signal s_axis_active: std_logic;
-----------------------------------------------------------------------
-- DUT signals
----------------------------------------------------------------------
-- Config slave channel signals
signal s_axis_config_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_config_tready : std_logic := '1'; -- slave is ready
signal s_axis_config_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload
-- Data slave channel signals
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
signal s_axis_data_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- data payload
signal s_axis_data_tlast : std_logic := '0'; -- indicates end of packet
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tready : std_logic := '1'; -- slave is ready
signal m_axis_data_tdata : std_logic_vector(63 downto 0) := (others => '0'); -- data payload
signal m_axis_data_tuser : std_logic_vector(15 downto 0) := (others => '0'); -- user-defined payload
signal m_axis_data_tlast : std_logic := '0'; -- indicates end of packet
-- Event signals
signal event_frame_started : std_logic := '0';
signal event_tlast_unexpected : std_logic := '0';
signal event_tlast_missing : std_logic := '0';
signal event_status_channel_halt : std_logic := '0';
signal event_data_in_channel_halt : std_logic := '0';
signal event_data_out_channel_halt : std_logic := '0';
alias fft_out_re : std_logic_vector(28 downto 0) is m_axis_data_tdata(28 downto 0);
alias fft_out_im : std_logic_vector(28 downto 0) is m_axis_data_tdata(60 downto 32);
alias fft_out_index:std_logic_vector(11 downto 0) is m_axis_data_tuser(11 downto 0);
signal fft_out_index_buf:std_logic_vector(11*delay_length-1 downto 0);
signal ch1_y_fft_in: std_logic_vector(15 downto 0);
signal sqr_re_i, sqr_im_i : std_logic_vector(28 downto 0);
signal sqr_re_o, sqr_im_o : std_logic_vector(57 downto 0);
signal sqr_summed: std_logic_vector(57 downto 0);
signal scale_sig: std_logic_vector(ywidth-1 downto 0);
signal top_6: std_logic_vector(5 downto 0);
signal mem_out_data,mem_out_data_buf : std_logic_vector(11 downto 0);
signal mem_out_address: std_logic_vector(11 downto 0);
signal white_noise: std_logic_vector(15 downto 0);
component clk_base is
port (
clk_raw : in STD_LOGIC;
clk_250MHz : out STD_LOGIC;
clk_100MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end component;
COMPONENT fir
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0)
);
END COMPONENT;
COMPONENT fft
PORT (
aclk : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_frame_started : OUT STD_LOGIC;
event_tlast_unexpected:OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_status_channel_halt : OUT STD_LOGIC;
event_data_in_channel_halt : OUT STD_LOGIC;
event_data_out_channel_halt : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT multi_fft PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(28 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(57 DOWNTO 0)
);
END COMPONENT;
COMPONENT blk_mem_gen_0
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
component trigger is
generic(
vga_width:integer := 1280;
vga_height:integer := 1024
);
Port ( clk_100MHz : in STD_LOGIC;
enable: in STD_LOGIC;
input: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
value: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
valid: out STD_LOGIC;
output: out STD_LOGIC_VECTOR(log2(vga_width)-1 downto 0);
time_val: in STD_LOGIC_VECTOR(6 downto 0)
);
end component;
component cro is
generic(
vga_width:integer := 1280;
vga_height:integer := 1024
);
Port ( clk_100MHz : in STD_LOGIC;
ch1_x: in STD_LOGIC_VECTOR(log2(vga_width)-1 downto 0);
ch1_y: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
ch1_update: in STD_LOGIC;
ch2_x: in STD_LOGIC_VECTOR(log2(vga_width)-1 downto 0);
ch2_y: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
ch2_update: in STD_LOGIC;
vline: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0);
vline_enb: in std_logic;
str: in std_logic_vector(8*50-1 downto 0);
VGA_DATA : out STD_LOGIC_VECTOR (11 downto 0);
VGA_HSYNC : out STD_LOGIC;
VGA_VSYNC : out STD_LOGIC
);
end component;
COMPONENT dds
PORT (
aclk : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
type modstate is (set_amplitude,set_phase,set_ch1_trigger,set_bits,set_fe,set_delay);
signal state : modstate;
begin
clk_base1: clk_base port map(clk_raw, clk_250MHz, clk_100MHz, open);
cro1: cro generic map(vga_width,vga_height) port map(clk_100MHz,ch1_x,ch1_y,ch1_update,ch2_x,ch2_y,ch2_update,vline,vline_enb_buf,str_std,VGA_DATA,VGA_HSYNC,VGA_VSYNC);
trigger1: trigger generic map(vga_width,vga_height) port map(clk_100MHz,trigger1_enable,ch1_y,ch1_trigger,ch1_update,ch1_x,(others=>'0'));
--trigger2: trigger generic map(vga_width,vga_height) port map(clk_100MHz,ch2_y,ch2_trigger,ch2_update,ch2_x,(others=>'0'));
dbounce1: debounce port map(clk_100MHz, btn(0), dbtn(0));
dbounce2: debounce port map(clk_100MHz, btn(4), dbtn(4));
dbounce3: debounce port map(clk_100MHz, btn(1), dbtn(1));
dbounce4: debounce port map(clk_100MHz, btn(3), dbtn(3));
--dbounce5: debounce port map(clk_100MHz, btn(2), dbtn(2));
prn1: prn32 generic map(n=>16) port map(clk_100MHz,white_noise);
fir1: fir
PORT MAP (
aclk => clk_100MHz,
s_axis_data_tvalid => '1',
s_axis_data_tready => fir_ready,
s_axis_data_tdata => fir_input,
m_axis_data_tvalid => fir_valid,
m_axis_data_tdata => fir_output
);
bitshift_div1: bitshift_div generic map(size=>dds_mag) port map(amplitude,signed_ch1,scaled_ch1);
sig_gen: dds
PORT MAP (
aclk => clk_100MHz,
s_axis_phase_tvalid => '1',
s_axis_phase_tdata => phase,
m_axis_data_tvalid => valid,
m_axis_data_tdata => dds_out
);
re_sqr: multi_fft
PORT MAP (
CLK => clk_100MHz,
A => sqr_re_i,
B => sqr_re_i,
P => sqr_re_o
);
im_sqr: multi_fft
PORT MAP (
CLK => clk_100MHz,
A => sqr_im_i,
B => sqr_im_i,
P => sqr_im_o
);
fft1: fft
PORT MAP (
aclk => clk_100MHz,
s_axis_config_tdata => X"01", -- fwd_inv
s_axis_config_tvalid => '1',
s_axis_config_tready => s_axis_config_tready,
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => s_axis_data_tlast,
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tlast => m_axis_data_tlast,
event_frame_started => event_frame_started,
event_tlast_unexpected => event_tlast_unexpected,
event_tlast_missing => event_tlast_missing,
event_status_channel_halt => event_status_channel_halt,
event_data_in_channel_halt => event_data_in_channel_halt,
event_data_out_channel_halt => event_data_out_channel_halt
);
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
end if;
end process;
process(clk_100MHz)
variable TMP : std_logic;
begin
if(clk_100MHz'event and clk_100MHz='1')then
TMP := '0';
for I in 57 downto 0 loop
if (TMP = '0' and sqr_summed(I) = '1') then
nums_of_zeros <= I;
TMP :='1';
mag <= std_logic_vector( to_unsigned( (nums_of_zeros)*20, ywidth));
case I IS
when 6 to 57 => mostsig <= sqr_summed(I downto I-5);
when 5 => mostsig <= "0"&sqr_summed(I downto I-4);
when 4 => mostsig <= "00"&sqr_summed(I downto I-3);
when 3 => mostsig <= "000"&sqr_summed(I downto I-2);
when 2 => mostsig <= "0000"&sqr_summed(I downto I-1);
when 1 => mostsig <= "00000"&sqr_summed(I downto I-0);
when 0 => mostsig <= (others=>'0');
end case;
end if;
end loop;
case mostsig is
when std_logic_vector(to_unsigned(0,6)) => scale_sig <= std_logic_vector(to_unsigned(0,ywidth)) ;
when std_logic_vector(to_unsigned(1,6)) => scale_sig <= std_logic_vector(to_unsigned(0,ywidth)) ;
when std_logic_vector(to_unsigned(2,6)) => scale_sig <= std_logic_vector(to_unsigned(1,ywidth)) ;
when std_logic_vector(to_unsigned(3,6)) => scale_sig <= std_logic_vector(to_unsigned(1,ywidth)) ;
when std_logic_vector(to_unsigned(4,6)) => scale_sig <= std_logic_vector(to_unsigned(1,ywidth)) ;
when std_logic_vector(to_unsigned(5,6)) => scale_sig <= std_logic_vector(to_unsigned(2,ywidth)) ;
when std_logic_vector(to_unsigned(6,6)) => scale_sig <= std_logic_vector(to_unsigned(2,ywidth)) ;
when std_logic_vector(to_unsigned(7,6)) => scale_sig <= std_logic_vector(to_unsigned(2,ywidth)) ;
when std_logic_vector(to_unsigned(8,6)) => scale_sig <= std_logic_vector(to_unsigned(3,ywidth)) ;
when std_logic_vector(to_unsigned(9,6)) => scale_sig <= std_logic_vector(to_unsigned(3,ywidth)) ;
when std_logic_vector(to_unsigned(10,6)) => scale_sig <= std_logic_vector(to_unsigned(3,ywidth)) ;
when std_logic_vector(to_unsigned(11,6)) => scale_sig <= std_logic_vector(to_unsigned(3,ywidth)) ;
when std_logic_vector(to_unsigned(12,6)) => scale_sig <= std_logic_vector(to_unsigned(4,ywidth)) ;
when std_logic_vector(to_unsigned(13,6)) => scale_sig <= std_logic_vector(to_unsigned(4,ywidth)) ;
when std_logic_vector(to_unsigned(14,6)) => scale_sig <= std_logic_vector(to_unsigned(4,ywidth)) ;
when std_logic_vector(to_unsigned(15,6)) => scale_sig <= std_logic_vector(to_unsigned(5,ywidth)) ;
when std_logic_vector(to_unsigned(16,6)) => scale_sig <= std_logic_vector(to_unsigned(5,ywidth)) ;
when std_logic_vector(to_unsigned(17,6)) => scale_sig <= std_logic_vector(to_unsigned(5,ywidth)) ;
when std_logic_vector(to_unsigned(18,6)) => scale_sig <= std_logic_vector(to_unsigned(6,ywidth)) ;
when std_logic_vector(to_unsigned(19,6)) => scale_sig <= std_logic_vector(to_unsigned(6,ywidth)) ;
when std_logic_vector(to_unsigned(20,6)) => scale_sig <= std_logic_vector(to_unsigned(6,ywidth)) ;
when std_logic_vector(to_unsigned(21,6)) => scale_sig <= std_logic_vector(to_unsigned(7,ywidth)) ;
when std_logic_vector(to_unsigned(22,6)) => scale_sig <= std_logic_vector(to_unsigned(7,ywidth)) ;
when std_logic_vector(to_unsigned(23,6)) => scale_sig <= std_logic_vector(to_unsigned(7,ywidth)) ;
when std_logic_vector(to_unsigned(24,6)) => scale_sig <= std_logic_vector(to_unsigned(8,ywidth)) ;
when std_logic_vector(to_unsigned(25,6)) => scale_sig <= std_logic_vector(to_unsigned(8,ywidth)) ;
when std_logic_vector(to_unsigned(26,6)) => scale_sig <= std_logic_vector(to_unsigned(8,ywidth)) ;
when std_logic_vector(to_unsigned(27,6)) => scale_sig <= std_logic_vector(to_unsigned(9,ywidth)) ;
when std_logic_vector(to_unsigned(28,6)) => scale_sig <= std_logic_vector(to_unsigned(9,ywidth)) ;
when std_logic_vector(to_unsigned(29,6)) => scale_sig <= std_logic_vector(to_unsigned(9,ywidth)) ;
when std_logic_vector(to_unsigned(30,6)) => scale_sig <= std_logic_vector(to_unsigned(10,ywidth)) ;
when std_logic_vector(to_unsigned(31,6)) => scale_sig <= std_logic_vector(to_unsigned(10,ywidth)) ;
when std_logic_vector(to_unsigned(32,6)) => scale_sig <= std_logic_vector(to_unsigned(10,ywidth)) ;
when std_logic_vector(to_unsigned(33,6)) => scale_sig <= std_logic_vector(to_unsigned(10,ywidth)) ;
when std_logic_vector(to_unsigned(34,6)) => scale_sig <= std_logic_vector(to_unsigned(11,ywidth)) ;
when std_logic_vector(to_unsigned(35,6)) => scale_sig <= std_logic_vector(to_unsigned(11,ywidth)) ;
when std_logic_vector(to_unsigned(36,6)) => scale_sig <= std_logic_vector(to_unsigned(11,ywidth)) ;
when std_logic_vector(to_unsigned(37,6)) => scale_sig <= std_logic_vector(to_unsigned(12,ywidth)) ;
when std_logic_vector(to_unsigned(38,6)) => scale_sig <= std_logic_vector(to_unsigned(12,ywidth)) ;
when std_logic_vector(to_unsigned(39,6)) => scale_sig <= std_logic_vector(to_unsigned(12,ywidth)) ;
when std_logic_vector(to_unsigned(40,6)) => scale_sig <= std_logic_vector(to_unsigned(13,ywidth)) ;
when std_logic_vector(to_unsigned(41,6)) => scale_sig <= std_logic_vector(to_unsigned(13,ywidth)) ;
when std_logic_vector(to_unsigned(42,6)) => scale_sig <= std_logic_vector(to_unsigned(13,ywidth)) ;
when std_logic_vector(to_unsigned(43,6)) => scale_sig <= std_logic_vector(to_unsigned(14,ywidth)) ;
when std_logic_vector(to_unsigned(44,6)) => scale_sig <= std_logic_vector(to_unsigned(14,ywidth)) ;
when std_logic_vector(to_unsigned(45,6)) => scale_sig <= std_logic_vector(to_unsigned(14,ywidth)) ;
when std_logic_vector(to_unsigned(46,6)) => scale_sig <= std_logic_vector(to_unsigned(15,ywidth)) ;
when std_logic_vector(to_unsigned(47,6)) => scale_sig <= std_logic_vector(to_unsigned(15,ywidth)) ;
when std_logic_vector(to_unsigned(48,6)) => scale_sig <= std_logic_vector(to_unsigned(15,ywidth)) ;
when std_logic_vector(to_unsigned(49,6)) => scale_sig <= std_logic_vector(to_unsigned(16,ywidth)) ;
when std_logic_vector(to_unsigned(50,6)) => scale_sig <= std_logic_vector(to_unsigned(16,ywidth)) ;
when std_logic_vector(to_unsigned(51,6)) => scale_sig <= std_logic_vector(to_unsigned(16,ywidth)) ;
when std_logic_vector(to_unsigned(52,6)) => scale_sig <= std_logic_vector(to_unsigned(17,ywidth)) ;
when std_logic_vector(to_unsigned(53,6)) => scale_sig <= std_logic_vector(to_unsigned(17,ywidth)) ;
when std_logic_vector(to_unsigned(54,6)) => scale_sig <= std_logic_vector(to_unsigned(17,ywidth)) ;
when std_logic_vector(to_unsigned(55,6)) => scale_sig <= std_logic_vector(to_unsigned(17,ywidth)) ;
when std_logic_vector(to_unsigned(56,6)) => scale_sig <= std_logic_vector(to_unsigned(18,ywidth)) ;
when std_logic_vector(to_unsigned(57,6)) => scale_sig <= std_logic_vector(to_unsigned(18,ywidth)) ;
when std_logic_vector(to_unsigned(58,6)) => scale_sig <= std_logic_vector(to_unsigned(18,ywidth)) ;
when std_logic_vector(to_unsigned(59,6)) => scale_sig <= std_logic_vector(to_unsigned(19,ywidth)) ;
when std_logic_vector(to_unsigned(60,6)) => scale_sig <= std_logic_vector(to_unsigned(19,ywidth)) ;
when std_logic_vector(to_unsigned(61,6)) => scale_sig <= std_logic_vector(to_unsigned(19,ywidth)) ;
when std_logic_vector(to_unsigned(62,6)) => scale_sig <= std_logic_vector(to_unsigned(20,ywidth)) ;
when std_logic_vector(to_unsigned(63,6)) => scale_sig <= std_logic_vector(to_unsigned(20,ywidth)) ;
end case;
end if;
end process;
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
fir_input <= white_noise;
fir_extracted <= fir_output(fe + 15 downto fe);
end if;
end process;
-- signal str : String(1 to 50) := "hold time violation";
-- signal str_std : std_logic_vector(8*50-1 downto 0);
GEN_str_buf: for I in 0 to 49 generate
str_std(I*8+7 downto I*8) <= char2std(str(I+1));
end generate;
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
--led <= str_test;
ch2_update <= '1';
--ch2_y <= vga_height/2;
ch2_y <= mag + scale_sig;--(sqr_summed((ywidth-1)+w downto w));
--ch2_x <= fft_out_index(10 downto 0);
ch1_y_fft_in <= scaled_ch1;
ch1_y <= scaled_ch1(scaled_ch1'length-1 downto (scaled_ch1'length-1)-(ch1_y'length)+1);
--ch2_y <= signed_ch2;
if(sw(0) = '0')then
signed_ch1 <= std_logic_vector(signed(sine_raw));
trigger1_enable <= '1';
else
trigger1_enable <= '0';
if(sw(1) = '0')then
signed_ch1 <= std_logic_vector(signed(white_noise));
else
signed_ch1 <= std_logic_vector(signed(fir_extracted));
end if;
end if;
--signed_ch2 <= std_logic_vector(resize(signed(cosine_raw),ywidth));
end if;
end process;
-- input
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
-- led(0) <= s_axis_active;
-- led(1) <= s_axis_data_tvalid;
-- led(2) <= m_axis_data_tvalid;
-- led(3) <= m_axis_data_tready;
-- led(4) <= s_axis_data_tready;
-- led(5) <= event_status_channel_halt;
-- led(6) <= event_data_in_channel_halt;
--led(7) <= event_data_out_channel_halt;
sqr_summed <= sqr_re_o + sqr_im_o;
if(s_axis_active = '1')then
s_axis_data_tlast <= '0';
end if;
if( s_axis_data_tready = '1' and s_axis_active = '0' and ch1_x = "000000000000")then
s_axis_data_tvalid <= '1';
s_axis_active <= '1';
s_axis_data_tdata(15 downto 0) <= ch1_y_fft_in;
end if;
if(s_axis_active = '1' and ch1_x /= "000000000000")then
s_axis_data_tdata(15 downto 0) <= ch1_y_fft_in;
elsif(s_axis_active = '1' and ch1_x > 4096)then
s_axis_data_tvalid <= '0';
s_axis_active <= '0';
elsif(s_axis_active = '1' and ch1_x = 4096)then
s_axis_data_tlast <= '1';
end if;
end if;
end process;-- output fft
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
ch2_x <= fft_out_index_buf(11*delay_length-1 downto 11*(delay_length-1)); -- pop
--ch2_y <= sqr_summed(57 downto 47);
if( m_axis_data_tvalid = '1' )then
sqr_re_i <= fft_out_re;
sqr_im_i <= fft_out_im;
if(fft_out_index < 4096/2)then
fft_out_index_buf <= fft_out_index_buf(11*(delay_length-1)-1 downto 0) & (fft_out_index(10 downto 0)); --push
else
fft_out_index_buf <= (others=>'1'); -- off screen
end if;
-- if(m_axis_data_tlast = '1')then
-- end if;
end if;
end if;
end process;
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
vline_enb_buf <= vline_enb;
end if;
end process;
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
--set values
case state is
when set_amplitude =>
str <= "set amplitude ";
vline_enb <= '0';
if(dbtn(0) = '1')then
amplitude <= amplitude + 1;
elsif(dbtn(4) = '1')then
amplitude <= amplitude - 1;
end if;
when set_phase =>
str <= "set phase ";
vline_enb <= '0';
if(dbtn(0) = '1')then
phase <= phase + 1;
elsif(dbtn(4) = '1')then
phase <= phase - 1;
end if;
when set_ch1_trigger =>
str <= "set ch1 trigger ";
vline_enb <= '1';
vline <= ch1_trigger;
if(dbtn(0) = '1')then
ch1_trigger <= ch1_trigger + 1;
elsif(dbtn(4) = '1')then
ch1_trigger <= ch1_trigger - 1;
end if;
when set_bits =>
str <= "set fft index ";
vline_enb <= '0';
if(dbtn(0) = '1')then
w <= w + 1;
elsif(dbtn(4) = '1')then
w <= w - 1;
end if;
when set_fe =>
str <= "set filter index ";
vline_enb <= '0';
if(dbtn(0) = '1')then
fe <= fe + 1;
elsif(dbtn(4) = '1')then
fe <= fe - 1;
end if;
when set_delay =>
str <= "set delay index ";
vline_enb <= '0';
if(dbtn(0) = '1')then
delay_index <= delay_index + 1;
elsif(dbtn(4) = '1')then
delay_index <= delay_index - 1;
end if;
end case;
end if;
end process;
process(clk_100MHz) begin
if(clk_100MHz'event and clk_100MHz='1')then
--change mode
if(dbtn(1) = '1')then
case state is
when set_amplitude =>
state <= set_phase;
when set_phase =>
state <= set_ch1_trigger;
when set_ch1_trigger =>
state <= set_bits;
when set_bits =>
state <= set_fe;
when set_fe =>
state <= set_delay;
when set_delay =>
state <= set_amplitude;
end case;
elsif(dbtn(3) = '1')then
case state is
when set_amplitude =>
state <= set_delay;
when set_phase =>
state <= set_amplitude;
when set_ch1_trigger =>
state <= set_phase;
when set_bits =>
state <= set_ch1_trigger;
when set_fe =>
state <= set_bits;
when set_delay =>
state <= set_fe;
end case;
end if;
sw_buffer <= sw;
end if;
end process;
end Behavioral;
|
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.11.10:36:05
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE is
port (
data_en : in std_logic := '0'; -- data_en.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
col : in std_logic_vector(31 downto 0) := (others => '0'); -- col.wire
ctrl_en : in std_logic := '0'; -- ctrl_en.wire
colorbar : out std_logic_vector(23 downto 0); -- colorbar.wire
counter : in std_logic_vector(23 downto 0) := (others => '0') -- counter.wire
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNWEIMU3MK;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_bus_build_GNI6E4JZ66 is
generic (
width : natural := 8
);
port (
output : out std_logic_vector(2 downto 0); -- wire
in0 : in std_logic := 'X'; -- wire
in1 : in std_logic := 'X'; -- wire
in2 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_bus_build_GNI6E4JZ66;
component alt_dspbuilder_divider_GNKAPZN5MO is
generic (
Signed : natural := 0;
width : natural := 8;
pipeline : natural := 0
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
denom : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
numer : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
quotient : out std_logic_vector(width-1 downto 0); -- wire
remain : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_divider_GNKAPZN5MO;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNJ7D74ANQ;
component alt_dspbuilder_constant_GNKT7L5CDY is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNKT7L5CDY;
component alt_dspbuilder_if_statement_GNIV4UP6ZO is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNIV4UP6ZO;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_if_statement_GNMQPB5LUF is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNMQPB5LUF;
component alt_dspbuilder_if_statement_GNZR777PB6 is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNZR777PB6;
component alt_dspbuilder_constant_GNUWBUDS4L is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNUWBUDS4L;
component alt_dspbuilder_constant_GNJ2DIDH6N is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNJ2DIDH6N;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_constant_GNNCFWNIJI is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNCFWNIJI;
component alt_dspbuilder_if_statement_GNWHMBR6GA is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNWHMBR6GA;
component alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic (
delay : positive := 1;
signal_type : string := "Impulse";
impulse_width : positive := 1
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
result : out std_logic; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_single_pulse_GN2XGKTRR3;
component StateMachineEditor1 is
port (
clock : in std_logic := 'X'; -- clk
col_select : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
data : out std_logic_vector(23 downto 0); -- wire
data_en : in std_logic := 'X'; -- wire
reset : in std_logic := 'X' -- wire
);
end component StateMachineEditor1;
component alt_dspbuilder_counter_GNZKRIGTBB is
generic (
use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "0";
use_sload : string := "false";
use_sclr : string := "false";
use_cout : string := "false";
modulus : integer := 256;
use_cnt_ena : string := "false";
width : natural := 8;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0"
);
port (
aclr : in std_logic := 'X'; -- clk
aload : in std_logic := 'X'; -- wire
aset : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cnt_ena : in std_logic := 'X'; -- wire
cout : out std_logic; -- wire
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
direction : in std_logic := 'X'; -- wire
ena : in std_logic := 'X'; -- wire
q : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X'; -- wire
sload : in std_logic := 'X'; -- wire
sset : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_counter_GNZKRIGTBB;
component alt_dspbuilder_multiplier_GNEIWYOKUR is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "AUTO";
Signed : natural := 0;
OutputMsb : integer := 8;
aWidth : natural := 8;
bWidth : natural := 8;
OutputLsb : integer := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
dataa : in std_logic_vector(aWidth-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(bWidth-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(OutputMsb-OutputLsb+1-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_multiplier_GNEIWYOKUR;
component alt_dspbuilder_cast_GN7PRGDOVA is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7PRGDOVA;
component alt_dspbuilder_cast_GNCPEUNC4M is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCPEUNC4M;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
component alt_dspbuilder_cast_GNLHWQIRQK is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNLHWQIRQK;
signal pipelined_adder3user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder3user_aclrGND:output -> Pipelined_Adder3:user_aclr
signal pipelined_adder3enavcc_output_wire : std_logic; -- Pipelined_Adder3enaVCC:output -> Pipelined_Adder3:ena
signal divideruser_aclrgnd_output_wire : std_logic; -- Divideruser_aclrGND:output -> Divider:user_aclr
signal dividerenavcc_output_wire : std_logic; -- DividerenaVCC:output -> Divider:ena
signal single_pulse1sclrgnd_output_wire : std_logic; -- Single_Pulse1sclrGND:output -> Single_Pulse1:sclr
signal single_pulse1enavcc_output_wire : std_logic; -- Single_Pulse1enaVCC:output -> Single_Pulse1:ena
signal multiplieruser_aclrgnd_output_wire : std_logic; -- Multiplieruser_aclrGND:output -> Multiplier:user_aclr
signal multiplierenavcc_output_wire : std_logic; -- MultiplierenaVCC:output -> Multiplier:ena
signal constant9_output_wire : std_logic_vector(23 downto 0); -- Constant9:output -> Counter1:data
signal constant8_output_wire : std_logic_vector(23 downto 0); -- Constant8:output -> Divider:denom
signal counter1_q_wire : std_logic_vector(23 downto 0); -- Counter1:q -> [If_Statement1:a, If_Statement2:a, If_Statement3:a, If_Statement:a]
signal divider_quotient_wire : std_logic_vector(23 downto 0); -- Divider:quotient -> [If_Statement1:b, If_Statement:b, Multiplier:dataa]
signal if_statement_true_wire : std_logic; -- If_Statement:true -> Bus_Builder:in0
signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Bus_Builder:in1
signal if_statement2_true_wire : std_logic; -- If_Statement2:true -> Bus_Builder:in2
signal counter_0_output_wire : std_logic_vector(23 downto 0); -- counter_0:output -> If_Statement5:a
signal if_statement3_true_wire : std_logic; -- If_Statement3:true -> Logical_Bit_Operator12:data0
signal data_en_0_output_wire : std_logic; -- data_en_0:output -> [Logical_Bit_Operator12:data1, Logical_Bit_Operator8:data0, State_Machine_Editor1:data_en]
signal ctrl_en_0_output_wire : std_logic; -- ctrl_en_0:output -> Logical_Bit_Operator7:data0
signal logical_bit_operator12_result_wire : std_logic; -- Logical_Bit_Operator12:result -> Logical_Bit_Operator7:data1
signal logical_bit_operator7_result_wire : std_logic; -- Logical_Bit_Operator7:result -> Counter1:sload
signal if_statement5_true_wire : std_logic; -- If_Statement5:true -> Logical_Bit_Operator8:data1
signal logical_bit_operator8_result_wire : std_logic; -- Logical_Bit_Operator8:result -> Counter1:cnt_ena
signal constant6_output_wire : std_logic_vector(23 downto 0); -- Constant6:output -> Multiplier:datab
signal constant13_output_wire : std_logic_vector(23 downto 0); -- Constant13:output -> Pipelined_Adder3:datab
signal pipelined_adder3_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder3:result -> If_Statement2:c
signal single_pulse1_result_wire : std_logic; -- Single_Pulse1:result -> State_Machine_Editor1:reset
signal state_machine_editor1_data_wire : std_logic_vector(23 downto 0); -- State_Machine_Editor1:data -> colorbar_0:input
signal col_0_output_wire : std_logic_vector(31 downto 0); -- col_0:output -> [cast0:input, cast1:input, cast2:input, cast6:input]
signal cast0_output_wire : std_logic_vector(23 downto 0); -- cast0:output -> Divider:numer
signal cast1_output_wire : std_logic_vector(23 downto 0); -- cast1:output -> If_Statement:c
signal cast2_output_wire : std_logic_vector(23 downto 0); -- cast2:output -> If_Statement3:b
signal constant11_output_wire : std_logic_vector(15 downto 0); -- Constant11:output -> cast3:input
signal cast3_output_wire : std_logic_vector(23 downto 0); -- cast3:output -> If_Statement5:b
signal multiplier_result_wire : std_logic_vector(47 downto 0); -- Multiplier:result -> [cast4:input, cast5:input]
signal cast4_output_wire : std_logic_vector(23 downto 0); -- cast4:output -> If_Statement1:c
signal cast5_output_wire : std_logic_vector(23 downto 0); -- cast5:output -> If_Statement2:b
signal cast6_output_wire : std_logic_vector(23 downto 0); -- cast6:output -> Pipelined_Adder3:dataa
signal bus_builder_output_wire : std_logic_vector(2 downto 0); -- Bus_Builder:output -> cast7:input
signal cast7_output_wire : std_logic_vector(2 downto 0); -- cast7:output -> State_Machine_Editor1:col_select
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Counter1:aclr, Divider:aclr, Multiplier:aclr, Pipelined_Adder3:aclr, Single_Pulse1:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Counter1:clock, Divider:clock, Multiplier:clock, Pipelined_Adder3:clock, Single_Pulse1:clock, State_Machine_Editor1:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
pipelined_adder3 : component alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map (
width => 24,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast6_output_wire, -- dataa.wire
datab => constant13_output_wire, -- datab.wire
result => pipelined_adder3_result_wire, -- result.wire
user_aclr => pipelined_adder3user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder3enavcc_output_wire -- ena.wire
);
pipelined_adder3user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder3user_aclrgnd_output_wire -- output.wire
);
pipelined_adder3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder3enavcc_output_wire -- output.wire
);
col_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => col, -- input.wire
output => col_0_output_wire -- output.wire
);
bus_builder : component alt_dspbuilder_bus_build_GNI6E4JZ66
generic map (
width => 3
)
port map (
output => bus_builder_output_wire, -- output.wire
in0 => if_statement_true_wire, -- in0.wire
in1 => if_statement1_true_wire, -- in1.wire
in2 => if_statement2_true_wire -- in2.wire
);
divider : component alt_dspbuilder_divider_GNKAPZN5MO
generic map (
Signed => 0,
width => 24,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
numer => cast0_output_wire, -- numer.wire
denom => constant8_output_wire, -- denom.wire
quotient => divider_quotient_wire, -- quotient.wire
remain => open, -- remain.wire
user_aclr => divideruser_aclrgnd_output_wire, -- user_aclr.wire
ena => dividerenavcc_output_wire -- ena.wire
);
divideruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => divideruser_aclrgnd_output_wire -- output.wire
);
dividerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => dividerenavcc_output_wire -- output.wire
);
colorbar_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => state_machine_editor1_data_wire, -- input.wire
output => colorbar -- output.wire
);
if_statement5 : component alt_dspbuilder_if_statement_GNJ7D74ANQ
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a>b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement5_true_wire, -- true.wire
a => counter_0_output_wire, -- a.wire
b => cast3_output_wire -- b.wire
);
counter_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter, -- input.wire
output => counter_0_output_wire -- output.wire
);
constant6 : component alt_dspbuilder_constant_GNKT7L5CDY
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000010",
width => 24
)
port map (
output => constant6_output_wire -- output.wire
);
if_statement3 : component alt_dspbuilder_if_statement_GNIV4UP6ZO
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a=b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement3_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => cast2_output_wire -- b.wire
);
logical_bit_operator12 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator12_result_wire, -- result.wire
data0 => if_statement3_true_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
if_statement2 : component alt_dspbuilder_if_statement_GNMQPB5LUF
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>b) or (a=b)) and ((a<c) or (a=c))",
number_inputs => 3,
width => 24
)
port map (
true => if_statement2_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => cast5_output_wire, -- b.wire
c => pipelined_adder3_result_wire -- c.wire
);
if_statement1 : component alt_dspbuilder_if_statement_GNZR777PB6
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>b) or (a=b)) and (a<c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement1_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => divider_quotient_wire, -- b.wire
c => cast4_output_wire -- c.wire
);
constant8 : component alt_dspbuilder_constant_GNUWBUDS4L
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000011",
width => 24
)
port map (
output => constant8_output_wire -- output.wire
);
constant9 : component alt_dspbuilder_constant_GNJ2DIDH6N
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000001",
width => 24
)
port map (
output => constant9_output_wire -- output.wire
);
logical_bit_operator7 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator7_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => logical_bit_operator12_result_wire -- data1.wire
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ctrl_en, -- input.wire
output => ctrl_en_0_output_wire -- output.wire
);
constant11 : component alt_dspbuilder_constant_GNNCFWNIJI
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000100",
width => 16
)
port map (
output => constant11_output_wire -- output.wire
);
if_statement : component alt_dspbuilder_if_statement_GNWHMBR6GA
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>zero) and (a<b)) or (a=c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => divider_quotient_wire, -- b.wire
c => cast1_output_wire -- c.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => data_en, -- input.wire
output => data_en_0_output_wire -- output.wire
);
constant13 : component alt_dspbuilder_constant_GNJ2DIDH6N
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000001",
width => 24
)
port map (
output => constant13_output_wire -- output.wire
);
logical_bit_operator8 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator8_result_wire, -- result.wire
data0 => data_en_0_output_wire, -- data0.wire
data1 => if_statement5_true_wire -- data1.wire
);
single_pulse1 : component alt_dspbuilder_single_pulse_GN2XGKTRR3
generic map (
delay => 1,
signal_type => "Step Down",
impulse_width => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
result => single_pulse1_result_wire, -- result.wire
sclr => single_pulse1sclrgnd_output_wire, -- sclr.wire
ena => single_pulse1enavcc_output_wire -- ena.wire
);
single_pulse1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => single_pulse1sclrgnd_output_wire -- output.wire
);
single_pulse1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => single_pulse1enavcc_output_wire -- output.wire
);
state_machine_editor1 : component StateMachineEditor1
port map (
clock => clock_0_clock_output_clk, -- clock.clk
reset => single_pulse1_result_wire, -- reset.wire
col_select => cast7_output_wire, -- col_select.wire
data_en => data_en_0_output_wire, -- data_en.wire
data => state_machine_editor1_data_wire -- data.wire
);
counter1 : component alt_dspbuilder_counter_GNZKRIGTBB
generic map (
use_usr_aclr => "false",
use_ena => "false",
use_cin => "false",
use_sset => "false",
ndirection => 1,
svalue => "1",
use_sload => "true",
use_sclr => "false",
use_cout => "false",
modulus => 65536,
use_cnt_ena => "true",
width => 24,
use_aset => "false",
use_aload => "false",
avalue => "0"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => constant9_output_wire, -- data.wire
cnt_ena => logical_bit_operator8_result_wire, -- cnt_ena.wire
sload => logical_bit_operator7_result_wire, -- sload.wire
q => counter1_q_wire, -- q.wire
cout => open -- cout.wire
);
multiplier : component alt_dspbuilder_multiplier_GNEIWYOKUR
generic map (
DEDICATED_MULTIPLIER_CIRCUITRY => "YES",
Signed => 0,
OutputMsb => 47,
aWidth => 24,
bWidth => 24,
OutputLsb => 0,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => divider_quotient_wire, -- dataa.wire
datab => constant6_output_wire, -- datab.wire
result => multiplier_result_wire, -- result.wire
user_aclr => multiplieruser_aclrgnd_output_wire, -- user_aclr.wire
ena => multiplierenavcc_output_wire -- ena.wire
);
multiplieruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplieruser_aclrgnd_output_wire -- output.wire
);
multiplierenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplierenavcc_output_wire -- output.wire
);
cast0 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast0_output_wire -- output.wire
);
cast1 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast1_output_wire -- output.wire
);
cast2 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast2_output_wire -- output.wire
);
cast3 : component alt_dspbuilder_cast_GNCPEUNC4M
generic map (
round => 0,
saturate => 0
)
port map (
input => constant11_output_wire, -- input.wire
output => cast3_output_wire -- output.wire
);
cast4 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplier_result_wire, -- input.wire
output => cast4_output_wire -- output.wire
);
cast5 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplier_result_wire, -- input.wire
output => cast5_output_wire -- output.wire
);
cast6 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast6_output_wire -- output.wire
);
cast7 : component alt_dspbuilder_cast_GNLHWQIRQK
generic map (
round => 0,
saturate => 0
)
port map (
input => bus_builder_output_wire, -- input.wire
output => cast7_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE
|
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.11.10:36:05
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE is
port (
data_en : in std_logic := '0'; -- data_en.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
col : in std_logic_vector(31 downto 0) := (others => '0'); -- col.wire
ctrl_en : in std_logic := '0'; -- ctrl_en.wire
colorbar : out std_logic_vector(23 downto 0); -- colorbar.wire
counter : in std_logic_vector(23 downto 0) := (others => '0') -- counter.wire
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_pipelined_adder_GNWEIMU3MK is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNWEIMU3MK;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_bus_build_GNI6E4JZ66 is
generic (
width : natural := 8
);
port (
output : out std_logic_vector(2 downto 0); -- wire
in0 : in std_logic := 'X'; -- wire
in1 : in std_logic := 'X'; -- wire
in2 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_bus_build_GNI6E4JZ66;
component alt_dspbuilder_divider_GNKAPZN5MO is
generic (
Signed : natural := 0;
width : natural := 8;
pipeline : natural := 0
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
denom : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
numer : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
quotient : out std_logic_vector(width-1 downto 0); -- wire
remain : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_divider_GNKAPZN5MO;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_if_statement_GNJ7D74ANQ is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNJ7D74ANQ;
component alt_dspbuilder_constant_GNKT7L5CDY is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNKT7L5CDY;
component alt_dspbuilder_if_statement_GNIV4UP6ZO is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNIV4UP6ZO;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_if_statement_GNMQPB5LUF is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNMQPB5LUF;
component alt_dspbuilder_if_statement_GNZR777PB6 is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNZR777PB6;
component alt_dspbuilder_constant_GNUWBUDS4L is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNUWBUDS4L;
component alt_dspbuilder_constant_GNJ2DIDH6N is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNJ2DIDH6N;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_constant_GNNCFWNIJI is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNCFWNIJI;
component alt_dspbuilder_if_statement_GNWHMBR6GA is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNWHMBR6GA;
component alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic (
delay : positive := 1;
signal_type : string := "Impulse";
impulse_width : positive := 1
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
result : out std_logic; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_single_pulse_GN2XGKTRR3;
component StateMachineEditor1 is
port (
clock : in std_logic := 'X'; -- clk
col_select : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
data : out std_logic_vector(23 downto 0); -- wire
data_en : in std_logic := 'X'; -- wire
reset : in std_logic := 'X' -- wire
);
end component StateMachineEditor1;
component alt_dspbuilder_counter_GNZKRIGTBB is
generic (
use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "0";
use_sload : string := "false";
use_sclr : string := "false";
use_cout : string := "false";
modulus : integer := 256;
use_cnt_ena : string := "false";
width : natural := 8;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0"
);
port (
aclr : in std_logic := 'X'; -- clk
aload : in std_logic := 'X'; -- wire
aset : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cnt_ena : in std_logic := 'X'; -- wire
cout : out std_logic; -- wire
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
direction : in std_logic := 'X'; -- wire
ena : in std_logic := 'X'; -- wire
q : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X'; -- wire
sload : in std_logic := 'X'; -- wire
sset : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_counter_GNZKRIGTBB;
component alt_dspbuilder_multiplier_GNEIWYOKUR is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "AUTO";
Signed : natural := 0;
OutputMsb : integer := 8;
aWidth : natural := 8;
bWidth : natural := 8;
OutputLsb : integer := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
dataa : in std_logic_vector(aWidth-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(bWidth-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(OutputMsb-OutputLsb+1-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_multiplier_GNEIWYOKUR;
component alt_dspbuilder_cast_GN7PRGDOVA is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN7PRGDOVA;
component alt_dspbuilder_cast_GNCPEUNC4M is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCPEUNC4M;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
component alt_dspbuilder_cast_GNLHWQIRQK is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNLHWQIRQK;
signal pipelined_adder3user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder3user_aclrGND:output -> Pipelined_Adder3:user_aclr
signal pipelined_adder3enavcc_output_wire : std_logic; -- Pipelined_Adder3enaVCC:output -> Pipelined_Adder3:ena
signal divideruser_aclrgnd_output_wire : std_logic; -- Divideruser_aclrGND:output -> Divider:user_aclr
signal dividerenavcc_output_wire : std_logic; -- DividerenaVCC:output -> Divider:ena
signal single_pulse1sclrgnd_output_wire : std_logic; -- Single_Pulse1sclrGND:output -> Single_Pulse1:sclr
signal single_pulse1enavcc_output_wire : std_logic; -- Single_Pulse1enaVCC:output -> Single_Pulse1:ena
signal multiplieruser_aclrgnd_output_wire : std_logic; -- Multiplieruser_aclrGND:output -> Multiplier:user_aclr
signal multiplierenavcc_output_wire : std_logic; -- MultiplierenaVCC:output -> Multiplier:ena
signal constant9_output_wire : std_logic_vector(23 downto 0); -- Constant9:output -> Counter1:data
signal constant8_output_wire : std_logic_vector(23 downto 0); -- Constant8:output -> Divider:denom
signal counter1_q_wire : std_logic_vector(23 downto 0); -- Counter1:q -> [If_Statement1:a, If_Statement2:a, If_Statement3:a, If_Statement:a]
signal divider_quotient_wire : std_logic_vector(23 downto 0); -- Divider:quotient -> [If_Statement1:b, If_Statement:b, Multiplier:dataa]
signal if_statement_true_wire : std_logic; -- If_Statement:true -> Bus_Builder:in0
signal if_statement1_true_wire : std_logic; -- If_Statement1:true -> Bus_Builder:in1
signal if_statement2_true_wire : std_logic; -- If_Statement2:true -> Bus_Builder:in2
signal counter_0_output_wire : std_logic_vector(23 downto 0); -- counter_0:output -> If_Statement5:a
signal if_statement3_true_wire : std_logic; -- If_Statement3:true -> Logical_Bit_Operator12:data0
signal data_en_0_output_wire : std_logic; -- data_en_0:output -> [Logical_Bit_Operator12:data1, Logical_Bit_Operator8:data0, State_Machine_Editor1:data_en]
signal ctrl_en_0_output_wire : std_logic; -- ctrl_en_0:output -> Logical_Bit_Operator7:data0
signal logical_bit_operator12_result_wire : std_logic; -- Logical_Bit_Operator12:result -> Logical_Bit_Operator7:data1
signal logical_bit_operator7_result_wire : std_logic; -- Logical_Bit_Operator7:result -> Counter1:sload
signal if_statement5_true_wire : std_logic; -- If_Statement5:true -> Logical_Bit_Operator8:data1
signal logical_bit_operator8_result_wire : std_logic; -- Logical_Bit_Operator8:result -> Counter1:cnt_ena
signal constant6_output_wire : std_logic_vector(23 downto 0); -- Constant6:output -> Multiplier:datab
signal constant13_output_wire : std_logic_vector(23 downto 0); -- Constant13:output -> Pipelined_Adder3:datab
signal pipelined_adder3_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder3:result -> If_Statement2:c
signal single_pulse1_result_wire : std_logic; -- Single_Pulse1:result -> State_Machine_Editor1:reset
signal state_machine_editor1_data_wire : std_logic_vector(23 downto 0); -- State_Machine_Editor1:data -> colorbar_0:input
signal col_0_output_wire : std_logic_vector(31 downto 0); -- col_0:output -> [cast0:input, cast1:input, cast2:input, cast6:input]
signal cast0_output_wire : std_logic_vector(23 downto 0); -- cast0:output -> Divider:numer
signal cast1_output_wire : std_logic_vector(23 downto 0); -- cast1:output -> If_Statement:c
signal cast2_output_wire : std_logic_vector(23 downto 0); -- cast2:output -> If_Statement3:b
signal constant11_output_wire : std_logic_vector(15 downto 0); -- Constant11:output -> cast3:input
signal cast3_output_wire : std_logic_vector(23 downto 0); -- cast3:output -> If_Statement5:b
signal multiplier_result_wire : std_logic_vector(47 downto 0); -- Multiplier:result -> [cast4:input, cast5:input]
signal cast4_output_wire : std_logic_vector(23 downto 0); -- cast4:output -> If_Statement1:c
signal cast5_output_wire : std_logic_vector(23 downto 0); -- cast5:output -> If_Statement2:b
signal cast6_output_wire : std_logic_vector(23 downto 0); -- cast6:output -> Pipelined_Adder3:dataa
signal bus_builder_output_wire : std_logic_vector(2 downto 0); -- Bus_Builder:output -> cast7:input
signal cast7_output_wire : std_logic_vector(2 downto 0); -- cast7:output -> State_Machine_Editor1:col_select
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Counter1:aclr, Divider:aclr, Multiplier:aclr, Pipelined_Adder3:aclr, Single_Pulse1:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Counter1:clock, Divider:clock, Multiplier:clock, Pipelined_Adder3:clock, Single_Pulse1:clock, State_Machine_Editor1:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
pipelined_adder3 : component alt_dspbuilder_pipelined_adder_GNWEIMU3MK
generic map (
width => 24,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast6_output_wire, -- dataa.wire
datab => constant13_output_wire, -- datab.wire
result => pipelined_adder3_result_wire, -- result.wire
user_aclr => pipelined_adder3user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder3enavcc_output_wire -- ena.wire
);
pipelined_adder3user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder3user_aclrgnd_output_wire -- output.wire
);
pipelined_adder3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder3enavcc_output_wire -- output.wire
);
col_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => col, -- input.wire
output => col_0_output_wire -- output.wire
);
bus_builder : component alt_dspbuilder_bus_build_GNI6E4JZ66
generic map (
width => 3
)
port map (
output => bus_builder_output_wire, -- output.wire
in0 => if_statement_true_wire, -- in0.wire
in1 => if_statement1_true_wire, -- in1.wire
in2 => if_statement2_true_wire -- in2.wire
);
divider : component alt_dspbuilder_divider_GNKAPZN5MO
generic map (
Signed => 0,
width => 24,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
numer => cast0_output_wire, -- numer.wire
denom => constant8_output_wire, -- denom.wire
quotient => divider_quotient_wire, -- quotient.wire
remain => open, -- remain.wire
user_aclr => divideruser_aclrgnd_output_wire, -- user_aclr.wire
ena => dividerenavcc_output_wire -- ena.wire
);
divideruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => divideruser_aclrgnd_output_wire -- output.wire
);
dividerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => dividerenavcc_output_wire -- output.wire
);
colorbar_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => state_machine_editor1_data_wire, -- input.wire
output => colorbar -- output.wire
);
if_statement5 : component alt_dspbuilder_if_statement_GNJ7D74ANQ
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a>b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement5_true_wire, -- true.wire
a => counter_0_output_wire, -- a.wire
b => cast3_output_wire -- b.wire
);
counter_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter, -- input.wire
output => counter_0_output_wire -- output.wire
);
constant6 : component alt_dspbuilder_constant_GNKT7L5CDY
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000010",
width => 24
)
port map (
output => constant6_output_wire -- output.wire
);
if_statement3 : component alt_dspbuilder_if_statement_GNIV4UP6ZO
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "a=b",
number_inputs => 2,
width => 24
)
port map (
true => if_statement3_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => cast2_output_wire -- b.wire
);
logical_bit_operator12 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator12_result_wire, -- result.wire
data0 => if_statement3_true_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
if_statement2 : component alt_dspbuilder_if_statement_GNMQPB5LUF
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>b) or (a=b)) and ((a<c) or (a=c))",
number_inputs => 3,
width => 24
)
port map (
true => if_statement2_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => cast5_output_wire, -- b.wire
c => pipelined_adder3_result_wire -- c.wire
);
if_statement1 : component alt_dspbuilder_if_statement_GNZR777PB6
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>b) or (a=b)) and (a<c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement1_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => divider_quotient_wire, -- b.wire
c => cast4_output_wire -- c.wire
);
constant8 : component alt_dspbuilder_constant_GNUWBUDS4L
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000011",
width => 24
)
port map (
output => constant8_output_wire -- output.wire
);
constant9 : component alt_dspbuilder_constant_GNJ2DIDH6N
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000001",
width => 24
)
port map (
output => constant9_output_wire -- output.wire
);
logical_bit_operator7 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator7_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => logical_bit_operator12_result_wire -- data1.wire
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ctrl_en, -- input.wire
output => ctrl_en_0_output_wire -- output.wire
);
constant11 : component alt_dspbuilder_constant_GNNCFWNIJI
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000100",
width => 16
)
port map (
output => constant11_output_wire -- output.wire
);
if_statement : component alt_dspbuilder_if_statement_GNWHMBR6GA
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "((a>zero) and (a<b)) or (a=c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement_true_wire, -- true.wire
a => counter1_q_wire, -- a.wire
b => divider_quotient_wire, -- b.wire
c => cast1_output_wire -- c.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => data_en, -- input.wire
output => data_en_0_output_wire -- output.wire
);
constant13 : component alt_dspbuilder_constant_GNJ2DIDH6N
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000001",
width => 24
)
port map (
output => constant13_output_wire -- output.wire
);
logical_bit_operator8 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator8_result_wire, -- result.wire
data0 => data_en_0_output_wire, -- data0.wire
data1 => if_statement5_true_wire -- data1.wire
);
single_pulse1 : component alt_dspbuilder_single_pulse_GN2XGKTRR3
generic map (
delay => 1,
signal_type => "Step Down",
impulse_width => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
result => single_pulse1_result_wire, -- result.wire
sclr => single_pulse1sclrgnd_output_wire, -- sclr.wire
ena => single_pulse1enavcc_output_wire -- ena.wire
);
single_pulse1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => single_pulse1sclrgnd_output_wire -- output.wire
);
single_pulse1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => single_pulse1enavcc_output_wire -- output.wire
);
state_machine_editor1 : component StateMachineEditor1
port map (
clock => clock_0_clock_output_clk, -- clock.clk
reset => single_pulse1_result_wire, -- reset.wire
col_select => cast7_output_wire, -- col_select.wire
data_en => data_en_0_output_wire, -- data_en.wire
data => state_machine_editor1_data_wire -- data.wire
);
counter1 : component alt_dspbuilder_counter_GNZKRIGTBB
generic map (
use_usr_aclr => "false",
use_ena => "false",
use_cin => "false",
use_sset => "false",
ndirection => 1,
svalue => "1",
use_sload => "true",
use_sclr => "false",
use_cout => "false",
modulus => 65536,
use_cnt_ena => "true",
width => 24,
use_aset => "false",
use_aload => "false",
avalue => "0"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => constant9_output_wire, -- data.wire
cnt_ena => logical_bit_operator8_result_wire, -- cnt_ena.wire
sload => logical_bit_operator7_result_wire, -- sload.wire
q => counter1_q_wire, -- q.wire
cout => open -- cout.wire
);
multiplier : component alt_dspbuilder_multiplier_GNEIWYOKUR
generic map (
DEDICATED_MULTIPLIER_CIRCUITRY => "YES",
Signed => 0,
OutputMsb => 47,
aWidth => 24,
bWidth => 24,
OutputLsb => 0,
pipeline => 0
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => divider_quotient_wire, -- dataa.wire
datab => constant6_output_wire, -- datab.wire
result => multiplier_result_wire, -- result.wire
user_aclr => multiplieruser_aclrgnd_output_wire, -- user_aclr.wire
ena => multiplierenavcc_output_wire -- ena.wire
);
multiplieruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplieruser_aclrgnd_output_wire -- output.wire
);
multiplierenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplierenavcc_output_wire -- output.wire
);
cast0 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast0_output_wire -- output.wire
);
cast1 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast1_output_wire -- output.wire
);
cast2 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast2_output_wire -- output.wire
);
cast3 : component alt_dspbuilder_cast_GNCPEUNC4M
generic map (
round => 0,
saturate => 0
)
port map (
input => constant11_output_wire, -- input.wire
output => cast3_output_wire -- output.wire
);
cast4 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplier_result_wire, -- input.wire
output => cast4_output_wire -- output.wire
);
cast5 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplier_result_wire, -- input.wire
output => cast5_output_wire -- output.wire
);
cast6 : component alt_dspbuilder_cast_GN7PRGDOVA
generic map (
round => 0,
saturate => 0
)
port map (
input => col_0_output_wire, -- input.wire
output => cast6_output_wire -- output.wire
);
cast7 : component alt_dspbuilder_cast_GNLHWQIRQK
generic map (
round => 0,
saturate => 0
)
port map (
input => bus_builder_output_wire, -- input.wire
output => cast7_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_DATA_GENERATE
|
package issue575 is
type rec is record
x : integer;
y : bit_vector(1 to 3);
end record;
procedure test (x : out rec; val : bit);
end package;
package body issue575 is
procedure test (x : out rec; val : bit) is
begin
x.y := (others => val);
end procedure;
end package body;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VComponents.all;
entity delay_line is
generic (
width : positive := 8
);
port (
clk : in std_logic;
rst : in std_logic;
input : IN std_logic;
output : OUT std_logic;
setting : IN std_logic_vector(width-1 downto 0)
);
end delay_line;
architecture Behavioral of delay_line is
signal chain : std_logic_vector(((2**width)-1) downto 0);
signal chain_t : std_logic_vector(((2**width)-1) downto 0);
signal select_t : std_logic_vector(((2**width)-1) downto 0);
signal input_t : std_logic_vector(((2**width)/4)-1 downto 0);
signal output_t : std_logic;
attribute KEEP : string;
attribute KEEP of chain_t : signal is "true";
attribute KEEP of input_t : signal is "true";
attribute RLOC : string;
attribute RLOC of first_mux : label is "X" & INTEGER'image(0) & "Y" & INTEGER'image(0);
constant delay_time: time := 300 ps;
begin
output <= input when (unsigned(setting) = 0) else output_t;
reg: process(clk, rst, input, setting)
begin
if (rst = '1') then
select_t <= (others => '0');
elsif rising_edge(clk) then
select_t <= (others => '0');
select_t <= std_logic_vector(to_unsigned(1, 2**width) sll 2**width-1-to_integer(unsigned(setting)));
end if;
end process reg;
first_mux: muxf6 port map (s => '0', i0 => input_t(0), i1 => '0', o => chain_t(0));
chain(0) <= chain_t(0) after delay_time;
delay_loop: for j in 1 to ((2**WIDTH)-1) generate
begin
even_cols: if ((j/32) rem 2) = 0 generate
-- four mux go into one slice
constant row : integer := (j/4) rem 8;
constant column : integer := j/32;
attribute RLOC of mux : label is "X" & INTEGER'image(column) & "Y" & INTEGER'image(row);
begin
mux: muxf6 port map (s => select_t(j), i0 => chain(j - 1), i1 => input_t(j/4), o => chain_t(j));
chain(j) <= chain_t(j) after delay_time;
end generate;
odd_cols: if ((j/32) rem 2) = 1 generate
-- four mux go into one slice
constant row : integer := 7-((j/4) rem 8);
constant column : integer := j/32;
attribute RLOC of mux : label is "X" & INTEGER'image(column) & "Y" & INTEGER'image(row);
begin
mux: muxf6 port map (s => select_t(j+(3-((j rem 4)*2))), i0 => chain(j+(3-((j rem 4)*2)) - 1), i1 => input_t(j/4), o => chain_t(j+(3-((j rem 4)*2))));
chain(j) <= chain_t(j) after delay_time;
end generate;
end generate;
reg_loop: for j in 0 to ((2**width)/4)-1 generate
begin
even_cols: if ((j/8) rem 2) = 0 generate
constant row : integer := (j) rem 8;
constant column : integer := j/8;
attribute RLOC of input_reg : label is "X" & INTEGER'image(column-1) & "Y" & INTEGER'image(row);
begin
input_reg : FDCE generic map (INIT => '0')port map (Q => input_t(j), C => clk,CE => '1', CLR => rst, D => input);
end generate;
odd_cols: if ((j/8) rem 2) = 1 generate
constant row : integer := 7-((j) rem 8);
constant column : integer := j/8;
attribute RLOC of input_reg : label is "X" & INTEGER'image(column-1) & "Y" & INTEGER'image(row);
begin
input_reg : FDCE generic map (INIT => '0')port map (Q => input_t(j), C => clk,CE => '1', CLR => rst, D => input);
end generate;
end generate;
output_t <= chain(2**width-1);
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VComponents.all;
entity delay_line is
generic (
width : positive := 8
);
port (
clk : in std_logic;
rst : in std_logic;
input : IN std_logic;
output : OUT std_logic;
setting : IN std_logic_vector(width-1 downto 0)
);
end delay_line;
architecture Behavioral of delay_line is
signal chain : std_logic_vector(((2**width)-1) downto 0);
signal chain_t : std_logic_vector(((2**width)-1) downto 0);
signal select_t : std_logic_vector(((2**width)-1) downto 0);
signal input_t : std_logic_vector(((2**width)/4)-1 downto 0);
signal output_t : std_logic;
attribute KEEP : string;
attribute KEEP of chain_t : signal is "true";
attribute KEEP of input_t : signal is "true";
attribute RLOC : string;
attribute RLOC of first_mux : label is "X" & INTEGER'image(0) & "Y" & INTEGER'image(0);
constant delay_time: time := 300 ps;
begin
output <= input when (unsigned(setting) = 0) else output_t;
reg: process(clk, rst, input, setting)
begin
if (rst = '1') then
select_t <= (others => '0');
elsif rising_edge(clk) then
select_t <= (others => '0');
select_t <= std_logic_vector(to_unsigned(1, 2**width) sll 2**width-1-to_integer(unsigned(setting)));
end if;
end process reg;
first_mux: muxf6 port map (s => '0', i0 => input_t(0), i1 => '0', o => chain_t(0));
chain(0) <= chain_t(0) after delay_time;
delay_loop: for j in 1 to ((2**WIDTH)-1) generate
begin
even_cols: if ((j/32) rem 2) = 0 generate
-- four mux go into one slice
constant row : integer := (j/4) rem 8;
constant column : integer := j/32;
attribute RLOC of mux : label is "X" & INTEGER'image(column) & "Y" & INTEGER'image(row);
begin
mux: muxf6 port map (s => select_t(j), i0 => chain(j - 1), i1 => input_t(j/4), o => chain_t(j));
chain(j) <= chain_t(j) after delay_time;
end generate;
odd_cols: if ((j/32) rem 2) = 1 generate
-- four mux go into one slice
constant row : integer := 7-((j/4) rem 8);
constant column : integer := j/32;
attribute RLOC of mux : label is "X" & INTEGER'image(column) & "Y" & INTEGER'image(row);
begin
mux: muxf6 port map (s => select_t(j+(3-((j rem 4)*2))), i0 => chain(j+(3-((j rem 4)*2)) - 1), i1 => input_t(j/4), o => chain_t(j+(3-((j rem 4)*2))));
chain(j) <= chain_t(j) after delay_time;
end generate;
end generate;
reg_loop: for j in 0 to ((2**width)/4)-1 generate
begin
even_cols: if ((j/8) rem 2) = 0 generate
constant row : integer := (j) rem 8;
constant column : integer := j/8;
attribute RLOC of input_reg : label is "X" & INTEGER'image(column-1) & "Y" & INTEGER'image(row);
begin
input_reg : FDCE generic map (INIT => '0')port map (Q => input_t(j), C => clk,CE => '1', CLR => rst, D => input);
end generate;
odd_cols: if ((j/8) rem 2) = 1 generate
constant row : integer := 7-((j) rem 8);
constant column : integer := j/8;
attribute RLOC of input_reg : label is "X" & INTEGER'image(column-1) & "Y" & INTEGER'image(row);
begin
input_reg : FDCE generic map (INIT => '0')port map (Q => input_t(j), C => clk,CE => '1', CLR => rst, D => input);
end generate;
end generate;
output_t <= chain(2**width-1);
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2330.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02330ent IS
END c07s02b07x00p02n02i02330ent;
ARCHITECTURE c07s02b07x00p02n02i02330arch OF c07s02b07x00p02n02i02330ent IS
BEGIN
TESTING: PROCESS
type NEW_INT is range INTEGER'LOW to INTEGER'HIGH;
variable k : NEW_INT := 2 ** 5;
BEGIN
assert NOT(k=32)
report "***PASSED TEST: c07s02b07x00p02n02i02330"
severity NOTE;
assert (k=32)
report "***FAILED TEST: c07s02b07x00p02n02i02330 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02330arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2330.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02330ent IS
END c07s02b07x00p02n02i02330ent;
ARCHITECTURE c07s02b07x00p02n02i02330arch OF c07s02b07x00p02n02i02330ent IS
BEGIN
TESTING: PROCESS
type NEW_INT is range INTEGER'LOW to INTEGER'HIGH;
variable k : NEW_INT := 2 ** 5;
BEGIN
assert NOT(k=32)
report "***PASSED TEST: c07s02b07x00p02n02i02330"
severity NOTE;
assert (k=32)
report "***FAILED TEST: c07s02b07x00p02n02i02330 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02330arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2330.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02330ent IS
END c07s02b07x00p02n02i02330ent;
ARCHITECTURE c07s02b07x00p02n02i02330arch OF c07s02b07x00p02n02i02330ent IS
BEGIN
TESTING: PROCESS
type NEW_INT is range INTEGER'LOW to INTEGER'HIGH;
variable k : NEW_INT := 2 ** 5;
BEGIN
assert NOT(k=32)
report "***PASSED TEST: c07s02b07x00p02n02i02330"
severity NOTE;
assert (k=32)
report "***FAILED TEST: c07s02b07x00p02n02i02330 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02330arch;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_io_regs is
generic (
g_8voices : boolean := false;
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_sid_control );
end sid_io_regs;
architecture registers of sid_io_regs is
signal control_i : t_sid_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_base_left =>
control_i.base_left <= unsigned(io_req.data);
when c_sid_base_right =>
control_i.base_right <= unsigned(io_req.data);
when c_sid_snoop_left =>
control_i.snoop_left <= io_req.data(0);
when c_sid_snoop_right =>
control_i.snoop_right <= io_req.data(0);
when c_sid_enable_left =>
control_i.enable_left <= io_req.data(0);
when c_sid_enable_right =>
control_i.enable_right <= io_req.data(0);
when c_sid_extend_left =>
if g_8voices then
control_i.extend_left <= io_req.data(0);
end if;
when c_sid_extend_right =>
if g_8voices then
control_i.extend_right <= io_req.data(0);
end if;
when c_sid_wavesel_left =>
control_i.comb_wave_left <= io_req.data(0);
when c_sid_wavesel_right =>
control_i.comb_wave_right <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_voices =>
io_resp.data <= std_logic_vector(to_unsigned(g_num_voices, 8));
when c_sid_base_left =>
io_resp.data <= std_logic_vector(control_i.base_left);
when c_sid_base_right =>
io_resp.data <= std_logic_vector(control_i.base_right);
when c_sid_snoop_left =>
io_resp.data(0) <= control_i.snoop_left;
when c_sid_snoop_right =>
io_resp.data(0) <= control_i.snoop_right;
when c_sid_enable_left =>
io_resp.data(0) <= control_i.enable_left;
when c_sid_enable_right =>
io_resp.data(0) <= control_i.enable_right;
when c_sid_extend_left =>
io_resp.data(0) <= control_i.extend_left;
when c_sid_extend_right =>
io_resp.data(0) <= control_i.extend_right;
when c_sid_wavesel_left =>
io_resp.data(0) <= control_i.comb_wave_left;
when c_sid_wavesel_right =>
io_resp.data(0) <= control_i.comb_wave_right;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_sid_control_init;
end if;
end if;
end process;
end architecture;
|
-- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_add_sub
-- ============================================================
-- File Name: lpm_add_sub0.vhd
-- Megafunction Name(s):
-- lpm_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_add_sub0 IS
PORT
(
add_sub : IN STD_LOGIC ;
cin : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
cout : OUT STD_LOGIC ;
overflow : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_add_sub0;
ARCHITECTURE SYN OF lpm_add_sub0 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
add_sub : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
overflow : OUT STD_LOGIC ;
cin : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
overflow <= sub_wire0;
cout <= sub_wire1;
result <= sub_wire2(3 DOWNTO 0);
lpm_add_sub_component : lpm_add_sub
GENERIC MAP (
lpm_direction => "UNUSED",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_ADD_SUB",
lpm_width => 4
)
PORT MAP (
dataa => dataa,
add_sub => add_sub,
datab => datab,
cin => cin,
overflow => sub_wire0,
cout => sub_wire1,
result => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CarryIn NUMERIC "1"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: ConstantA NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-- Retrieval info: PRIVATE: Function NUMERIC "2"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: Overflow NUMERIC "1"
-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
-- Retrieval info: PRIVATE: Representation NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
-- Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
-- Retrieval info: USED_PORT: cin 0 0 0 0 INPUT NODEFVAL cin
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: dataa 0 0 4 0 INPUT NODEFVAL dataa[3..0]
-- Retrieval info: USED_PORT: datab 0 0 4 0 INPUT NODEFVAL datab[3..0]
-- Retrieval info: USED_PORT: overflow 0 0 0 0 OUTPUT NODEFVAL overflow
-- Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL result[3..0]
-- Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0
-- Retrieval info: CONNECT: @dataa 0 0 4 0 dataa 0 0 4 0
-- Retrieval info: CONNECT: @datab 0 0 4 0 datab 0 0 4 0
-- Retrieval info: CONNECT: @cin 0 0 0 0 cin 0 0 0 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: CONNECT: overflow 0 0 0 0 @overflow 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
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