Module Expr Str Import alias identifier ImportFrom alias Assign NameStore ListLoad Str Assign NameStore Dict Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num Num ListLoad Num ListLoad Num ListLoad Num ListLoad Num ListLoad Num ListLoad Num ListLoad Num Num Num ListLoad Num ListLoad Num ListLoad Num ListLoad Num Num Num ListLoad Num Num Num ListLoad Num Num Num ListLoad Num ListLoad Num Num Num ListLoad Num ListLoad Num ListLoad Num Num Num ListLoad Num ListLoad Num ListLoad Num ListLoad Num ListLoad Num Num Num ListLoad Num ListLoad Num Num Num ListLoad Num Num Num ListLoad Num ListLoad Num ListLoad Num Num Num ListLoad Num ListLoad Num Num Num FunctionDef arguments args NameParam NameParam NameParam NameParam defaults NameLoad NameLoad NameLoad body Expr Str If CompareIs NameLoad NameLoad body If CompareNotIn NameLoad NameLoad body Assign NameStore Call AttributeLoad NameLoad attr Call NameLoad Call AttributeLoad NameLoad attr Raise Call NameLoad BinOpMod Str TupleLoad Call AttributeLoad NameLoad attr Call AttributeLoad NameLoad attr Assign NameStore Call AttributeLoad NameLoad attr SubscriptLoad NameLoad Index NameLoad AttributeLoad NameLoad attr orelse Assign NameStore SubscriptLoad Call AttributeLoad NameLoad attr Call AttributeLoad NameLoad attr NameLoad AttributeLoad NameLoad attr Slice Num If BoolOpOr Call AttributeLoad NameLoad attr CompareLt NameLoad Num Call AttributeLoad NameLoad attr CompareGt NameLoad NameLoad CompareLt AttributeLoad NameLoad attr Num body Raise Call NameLoad Str Assign NameStore Call AttributeLoad NameLoad attr NameLoad Assign NameStore BinOpSub BinOpPow Num NameLoad Num If CompareIs NameLoad NameLoad body Assign NameStore NameLoad orelse Assign NameStore Call NameLoad NameLoad If CompareLt NameLoad Num body Raise Call NameLoad Str If CompareIs NameLoad NameLoad body Assign NameStore Call AttributeLoad NameLoad attr NameLoad keyword AttributeLoad NameLoad attr keyword Str orelse Assign NameStore Call AttributeLoad Call AttributeLoad NameLoad attr NameLoad keyword NameLoad keyword Str attr AttributeLoad NameLoad attr If BoolOpOr CompareNotEq AttributeLoad NameLoad attr Num CompareNotEq AttributeLoad NameLoad attr NameLoad body Raise Call NameLoad Str If Call AttributeLoad NameLoad attr CompareEq NameLoad Num body Raise Call NameLoad Str Assign NameStore Call AttributeLoad NameLoad attr NameLoad keyword AttributeLoad NameLoad attr keyword Str Assign NameStore Call NameLoad NameLoad NameLoad NameLoad NameLoad NameLoad Return TupleLoad NameLoad NameLoad decorator_list
N/A N/A Tools for MLS generation N/A numpy np _max_len_seq_inner _max_len_seq_inner N/A __all__ N/A max_len_seq N/A _mls_taps N/A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 N/A 1 N/A 2 N/A 3 N/A 3 N/A 5 N/A 6 N/A 7 6 1 N/A 5 N/A 7 N/A 9 N/A 11 10 4 N/A 12 11 8 N/A 13 12 2 N/A 14 N/A 15 13 4 N/A 14 N/A 11 N/A 18 17 14 N/A 17 N/A 19 N/A 21 N/A 18 N/A 23 22 17 N/A 22 N/A 25 24 20 N/A 26 25 22 N/A 25 N/A 27 N/A 29 28 7 N/A 28 N/A 31 30 10 max_len_seq N/A N/A nbits state length taps N/A None None None N/A N/A 
    Maximum length sequence (MLS) generator.

    Parameters
    ----------
    nbits : int
        Number of bits to use. Length of the resulting sequence will
        be ``(2**nbits) - 1``. Note that generating long sequences
        (e.g., greater than ``nbits == 16``) can take a long time.
    state : array_like, optional
        If array, must be of length ``nbits``, and will be cast to binary
        (bool) representation. If None, a seed of ones will be used,
        producing a repeatable representation. If ``state`` is all
        zeros, an error is raised as this is invalid. Default: None.
    length : int | None, optional
        Number of samples to compute. If None, the entire length
        ``(2**nbits) - 1`` is computed.
    taps : array_like, optional
        Polynomial taps to use (e.g., ``[7, 6, 1]`` for an 8-bit sequence).
        If None, taps will be automatically selected (for up to
        ``nbits == 32``).

    Returns
    -------
    seq : array
        Resulting MLS sequence of 0's and 1's.
    state : array
        The final state of the shift register.

    Notes
    -----
    The algorithm for MLS generation is generically described in:

        https://en.wikipedia.org/wiki/Maximum_length_sequence

    The default values for taps are specifically taken from the first
    option listed for each value of ``nbits`` in:

        http://www.newwaveinstruments.com/resources/articles/
            m_sequence_linear_feedback_shift_register_lfsr.htm

    .. versionadded:: 0.15.0
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