Module ImportFrom alias ImportFrom alias Import alias Import alias Import alias Expr Call AttributeLoad AttributeLoad NameLoad attr attr Num Call AttributeLoad AttributeLoad NameLoad attr attr Call AttributeLoad AttributeLoad NameLoad attr attr Call AttributeLoad AttributeLoad NameLoad attr attr Call AttributeLoad AttributeLoad NameLoad attr attr Call AttributeLoad AttributeLoad NameLoad attr attr Call AttributeLoad AttributeLoad NameLoad attr attr NameLoad ImportFrom alias FunctionDef arguments args NameParam NameParam defaults Num Num body Assign NameStore Call NameLoad Str Assign NameStore Call AttributeLoad NameLoad attr Str Assign NameStore Call AttributeLoad NameLoad attr Str Assign NameStore ListComp Call AttributeLoad NameLoad attr BinOpAdd Str Call NameLoad NameLoad keyword Num comprehension NameStore Call NameLoad NameLoad Assign NameStore Call AttributeLoad NameLoad attr Str Assign NameStore Call AttributeLoad NameLoad attr Str Expr Call AttributeLoad NameLoad attr Call NameLoad Num Expr Call AttributeLoad NameLoad attr Call NameLoad Num Assign NameStore Call NameLoad NameLoad Str NameLoad NameLoad Assign NameStore Call AttributeLoad NameLoad attr Str Call AttributeLoad BinOpSub NameLoad Num attr keyword Num Expr Call AttributeLoad NameLoad attr Call AttributeLoad NameLoad attr For NameStore Call NameLoad NameLoad body Expr Call AttributeLoad NameLoad attr Call SubscriptLoad NameLoad Index NameLoad NameLoad keyword CompareEq NameLoad NameLoad keyword NameLoad Expr Call AttributeLoad NameLoad attr Call SubscriptLoad NameLoad Index NameLoad NameLoad keyword CompareEq NameLoad NameLoad keyword NameLoad keyword NameLoad If CompareGt NameLoad Num body Expr Call AttributeLoad NameLoad attr Call SubscriptLoad NameLoad Index NameLoad NameLoad keyword CompareEq NameLoad Num keyword NameLoad keyword NameLoad Expr Call AttributeLoad NameLoad attr Return NameLoad decorator_list FunctionDef arguments args defaults body Assign NameStore Call NameLoad Str Assign NameStore Call NameLoad Assign NameStore Call AttributeLoad NameLoad attr NameLoad Assign NameStore Call AttributeLoad NameLoad attr NameLoad Assign NameStore SubscriptLoad NameLoad Index Str Assign NameStore SubscriptLoad NameLoad Index Str Assign NameStore Call AttributeLoad NameLoad attr NameLoad Str keyword Call AttributeLoad NameLoad attr NameLoad keyword Call AttributeLoad NameLoad attr NameLoad Expr Call AttributeLoad NameLoad attr NameLoad NameLoad Expr Call AttributeLoad NameLoad attr NameLoad NameLoad keyword Num Assign NameStore Call AttributeLoad NameLoad attr NameLoad NameLoad keyword Num Assign NameStore AttributeLoad NameLoad attr Expr Call AttributeLoad NameLoad attr Call NameLoad Num Call NameLoad Str Return NameLoad decorator_list If CompareEq NameLoad Str body Assign NameStore Call NameLoad Assign NameStore Call AttributeLoad NameLoad attr Str Expr Call NameLoad NameLoad
N/A __future__ absolute_import __future__ print_function N/A sys N/A os N/A math N/A N/A N/A N/A sys path insert 0 N/A N/A N/A os path dirname N/A N/A N/A os path dirname N/A N/A N/A os path dirname N/A N/A N/A os path dirname N/A N/A N/A os path dirname N/A N/A N/A os path abspath __file__ veriloggen * mkLed N/A N/A numports delay_amount N/A 8 2 N/A N/A m N/A Module blinkled N/A clk N/A N/A m Input CLK N/A rst N/A N/A m Input RST N/A led N/A N/A N/A m OutputReg N/A led N/A str i initval 0 N/A i N/A range numports N/A up N/A N/A m Wire up N/A down N/A N/A m Wire down N/A N/A N/A m Assign N/A up 1 N/A N/A N/A m Assign N/A down 0 N/A seq N/A Seq m seq clk rst N/A count N/A N/A m Reg count N/A N/A N/A numports 1 bit_length initval 0 N/A N/A N/A seq add N/A N/A count inc N/A i N/A range numports N/A N/A N/A N/A seq add N/A N/A led N/A i up cond N/A count i eager_val True N/A N/A N/A seq add N/A N/A led N/A i down cond N/A count i delay delay_amount eager_val True N/A N/A i 1 N/A N/A N/A N/A seq add N/A N/A led N/A i up cond N/A count 0 delay delay_amount eager_val True N/A N/A N/A seq make_always N/A m N/A mkTest N/A N/A N/A N/A N/A m N/A Module test N/A led N/A mkLed N/A params N/A N/A m copy_params led N/A ports N/A N/A m copy_sim_ports led N/A clk N/A ports N/A CLK N/A rst N/A ports N/A RST N/A uut N/A N/A m Instance led uut params N/A N/A m connect_params led ports N/A N/A m connect_ports led N/A N/A N/A simulation setup_waveform m uut N/A N/A N/A simulation setup_clock m clk hperiod 5 N/A init N/A N/A simulation setup_reset m rst period 100 N/A nclk N/A simulation next_clock N/A N/A N/A init add N/A Delay 1000 N/A Systask finish N/A m N/A N/A N/A __name__ __main__ N/A N/A test N/A mkTest N/A verilog N/A N/A test to_verilog tmp.v N/A N/A print verilog