Module ImportFrom alias ImportFrom alias Import alias Import alias ImportFrom alias Assign NameStore BinOpAdd Call AttributeLoad AttributeLoad NameLoad attr attr Call AttributeLoad AttributeLoad NameLoad attr attr Call AttributeLoad AttributeLoad NameLoad attr attr Call AttributeLoad AttributeLoad NameLoad attr attr NameLoad Str Assign NameStore Str FunctionDef arguments args defaults body Assign NameStore ListLoad BinOpAdd NameLoad Str Assign NameStore Str Assign NameStore NameLoad Assign NameStore NameLoad Assign NameStore NameLoad Assign NameStore NameLoad Assign NameStore Call NameLoad NameLoad NameLoad keyword NameLoad keyword NameLoad keyword NameLoad keyword NameLoad Expr Call AttributeLoad NameLoad attr Assign NameStore Call AttributeLoad NameLoad attr Assign NameStore Call AttributeLoad NameLoad attr Assign NameStore Call AttributeLoad NameLoad attr Assign NameStore Call AttributeLoad NameLoad attr Assign NameStore ListLoad For TupleStore NameStore NameStore Call NameLoad Call AttributeLoad NameLoad attr keyword Lambda arguments args NameParam defaults Call NameLoad SubscriptLoad NameLoad Index Num body For NameStore NameLoad body Expr Call AttributeLoad NameLoad attr Call AttributeLoad NameLoad attr Expr Call AttributeLoad NameLoad attr Str Assign NameStore Call AttributeLoad Str attr NameLoad Expr Call NameLoad NameLoad Assert CompareEq NameLoad NameLoad decorator_list If CompareEq NameLoad Str body Expr Call NameLoad
N/A __future__ absolute_import __future__ print_function N/A os N/A sys pyverilog.dataflow.dataflow_analyzer VerilogDataflowAnalyzer N/A codedir N/A N/A N/A N/A os path dirname N/A N/A N/A os path dirname N/A N/A N/A os path dirname N/A N/A N/A os path abspath __file__ /verilogcode/ N/A expected (Bind dest:TOP.WD tree:(IntConst 4))
(Bind dest:TOP._rn0_j tree:(IntConst 0))
(Bind dest:TOP._rn1_j tree:(Operator Plus Next:'d0,(IntConst 1)))
(Bind dest:TOP._rn2_j tree:(Operator Plus Next:'d1,(IntConst 1)))
(Bind dest:TOP._rn3_j tree:(Operator Plus Next:'d2,(IntConst 1)))
(Bind dest:TOP._rn4_j tree:(Operator Plus Next:'d3,(IntConst 1)))
(Bind dest:TOP.j tree:(Terminal TOP._rn4_j))
(Bind dest:TOP.md_generate0.ge_for0[0].subloop.ge_if0._subt.tmp tree:(Branch Cond:(Operator Eq Next:'d0,(IntConst 0)) True:(Operator Unot Next:(Partselect Var:(Terminal TOP.subin) MSB:'d0 LSB:'d0))))
(Bind dest:TOP.subout msb:'d0 lsb:'d0 tree:(Branch Cond:(Operator Eq Next:'d0,(IntConst 0)) True:(Partselect Var:(Terminal TOP.subin) MSB:'d0 LSB:'d0)))
(Bind dest:TOP.subout msb:'d1 lsb:'d1 tree:(Branch Cond:(Operator Eq Next:'d1,(IntConst 0)) False:(Branch Cond:(Operator Eq Next:'d1,(IntConst 1)) True:(Operator Xor Next:(Terminal TOP.md_generate0.ge_for0[0].subloop.ge_if0._subt.tmp),(Partselect Var:(Terminal TOP.subin) MSB:'d1 LSB:'d1)))))
(Bind dest:TOP.subout msb:'d2 lsb:'d2 tree:(Branch Cond:(Operator Eq Next:'d2,(IntConst 0)) False:(Branch Cond:(Operator Eq Next:'d2,(IntConst 1)) False:(Operator Xor Next:(Terminal TOP.md_generate0.ge_for0[1].subloop.ge_if1_ELSE._subf.tmp),(Partselect Var:(Terminal TOP.subin) MSB:'d2 LSB:'d2)))))
(Bind dest:TOP.subout msb:'d3 lsb:'d3 tree:(Branch Cond:(Operator Eq Next:'d3,(IntConst 0)) False:(Branch Cond:(Operator Eq Next:'d3,(IntConst 1)) False:(Operator Xor Next:(Terminal TOP.md_generate0.ge_for0[2].subloop.ge_if3_ELSE._subf.tmp),(Partselect Var:(Terminal TOP.subin) MSB:'d3 LSB:'d3)))))
 test N/A N/A N/A N/A N/A filelist N/A N/A codedir generate.v N/A topmodule TOP N/A noreorder False N/A nobind False N/A include None N/A define None N/A analyzer N/A VerilogDataflowAnalyzer filelist topmodule noreorder noreorder nobind nobind preprocess_include include preprocess_define define N/A N/A N/A analyzer generate N/A directives N/A N/A analyzer get_directives N/A instances N/A N/A analyzer getInstances N/A terms N/A N/A analyzer getTerms N/A binddict N/A N/A analyzer getBinddict N/A output N/A N/A N/A bk bv N/A sorted N/A N/A binddict items key N/A N/A N/A x N/A N/A str N/A x N/A 0 N/A N/A bvi bv N/A N/A N/A N/A output append N/A N/A bvi tostr N/A N/A N/A output append N/A rslt N/A N/A join output N/A N/A print rslt N/A N/A expected rslt N/A N/A N/A __name__ __main__ N/A N/A N/A test