Datasets:

jgammack

/

MTL-abstracts

like 0

Hafnia-filled Photonic Crystal Emitters for Mesoscale Thermophotovoltaic Energy Converters

Thermophotovoltaic (TPV) systems are promising as small scale, portable generators for power sensors, small robotic platforms, and portable computational and communication equipment. In TPV systems, an emitter at high temperature emits radiation that is then converted to electricity by a low bandgap photovoltaic cell. Our group’s approach to increase both TPV power and efficiency is to use two-dimensional, hafnia-filled tantalum photonic crystals (PhCs) as emitters. These emitters consist of a 2D array of cylindrical cavities etched in tantalum and filled with hafnia (HfO2). They work by enabling efficient spectral tailoring of thermal radiation for a wide range of incidence angles; they can increase the fuel-to-electricity efficiency of our group’s propane-based TPV system from 4.3% to above 12%. However, fabricating these PhCs is difficult: while the deep cavities of the PhC must be filled as completely as possible, using atomic layer deposition to fill the cavities layer by layer leads to an uneven and thick top hafnia surface that adversely impacts the emittance. Because the PhC optical performance improves with a flatter top hafnia surface, we explore methods to planarize the top surface, in particular by depositing a sacrificial oxide layer and etching it back. With a single iteration, the average height difference between the hafnia crest and trough is reduced from about 200nm to 90nm in silicon PhC samples, suggesting a method to fabricate PhCs with improved geometry and emittance. Precise fabrication of PhC emitters can enable high TPV performance and pave the way toward portable micro-generators for off the grid applications.

Fabric Integration of Organic Photovoltaics

In recent years, wearable technologies have emerged as a platform beyond basic functionality, such as a watch or a headphone, into highly integrated tools capable of communications, biosensing, navigation guidance, and performing financial transactions. Yet these technologies remain localized on the body in a bulky form-factor such as a smartwatch, AR glasses, or earbuds. Seamless integration of electronics over large areas into the most indispensable wearable, clothing, remains a distant goal. Forgoing conventional discrete/bulky electronics in place of emerging thin-film alternatives promises to bridge this gap. In this project, we report integration of organic photovoltaics (OPV) into ultra-lightweight composite fabrics (Dyneema) as a first step towards realizing elec-tronically active fabrics. The devices are fabricated on CVD-deposited ultra-thin dielectric substrates, which lend themselves for use on fabrics through transfer lamination. Employing standard thermal evaporation and RF sputtering processes, we have demonstrat-ed fabric-integrated OPV devices with over 1% power conversion efficiencies. In an effort to realize photo-voltaics with higher efficiencies that can power larger electronic devices, we are currently exploring the use of electronic polymer inks, which can be coated/print-ed through scalable roll-to-roll processes. Techniques developed in this project can also enable integration of other devices including displays, sensors, speakers, and actuators.

Balancing Actuation and Computing Energy in Low-power Motion Planning

We study a novel class of motion planning problems, in-spired by emerging low-power robotic vehicles, such as insect-size flyers, high-endurance autonomous blimps, and chip-size satellites for which the energy consumed by computing hardware while planning a path can be as large as the energy consumed by actuation hard-ware during the execution of the same path. For these new applications, we must consider the total energy of executing and computing a candidate solution to eval-uate a motion plan. Figure 1 shows average actuation energy and computing energy curves for a selected robotic platform and computing platform. Here, min-imizing only the actuation energy does not minimize the total energy. Instead, stopping computing earlier and accepting a higher actuation energy cost for a low-er computing energy cost minimizes the total energy.We propose a new algorithm, called Computing Energy Included Motion Planning (CEIMP). CEIMP op-erates similarly to other anytime planning algorithms, except it stops when it estimates further computing will require more computing energy than potential savings in actuation energy. The algorithm relies on Bayesian inference to estimate future energy savings to evaluate the trade-off between the computing ener-gy required to continue sampling and the potential fu-ture actuation energy savings after such computation. CEIMP outperforms the average baseline of using max-imum computing resources in realistic computational experiments involving 10 MIT building floor plans. On the ARM Cortex-A15, for a simulated vehicle that uses 1 Watt to travel 1 m/s, CEIMP saves 2.1-8.9x the total ener-gy on average across floor plans compared to the base-line, translating to missions that can last 2.1-8.9x longer on the same battery. Figure 2 shows CEIMP in action; while the path returned by CEIMP is longer than the path returned by the baseline, CEIMP’s total energy is much closer to the true minimum of total energy than the baseline.

Enabling Low-cost Electrodes in PbS Solar Cells through a Nickel Oxide Buffer Layer

The versatile characteristics of lead sulfide quantum dots (PbS QD) make them an attractive material to de-velop high-efficiency, low-cost, and flexible photovol-taics (PVs). Hole transport layers (HTLs) and electron transport layers are essential building blocks in these solar cell architectures. PbS QDs with an EDT ligand are widely used as an HTL in high-efficiency QDPVs. However, the limited compatibility of the EDT with different electrode materials prevents the continued development of QDPVs into manufacturing capable de-vice architectures. Specifically, the dependence on gold electrodes is cost-prohibitive for depositing QDPVs on a large scale.While gold cannot be used on a commercial scale, less expensive but more chemically reactive materials can be used. Replacing gold with aluminum or copper would cut material costs by a factor of at least 1,200. Through the use of a nickel oxide (NiOx) buffer layer, these devices become compatible with lower-cost elec-trodes. As a p-type metal oxide, NiOx is a favorable HTL material with a high work function, large band gap, and film stability.In fact, through the use of a NiOx buffer layer, power conversion efficiencies for devices with low-er-cost electrodes are equivalent to their gold electrode counterparts. However, even though NiOx buffer layer devices show improved performance and stability com-pared to devices without NiOx buffer layers, the power conversion efficiency drops after a couple of months due to a new barrier within the device stack. Current research focuses on improving the stability of QDPVs with low cost electrodes through identifying and miti-gating the barrier formation.

Architecture-level Energy Estimation of Accelerator Designs

With Moore's law slowing down and Dennard scaling ending, energy-efficient domain-specific accelerators have become a promising direction for hardware de-signers to continue bringing energy efficiency improve-ments to data and computation intensive applications. To ensure fast exploration of accelerator design space, architecture-level energy estimators, which perform energy estimations without requiring complete hard-ware description of the designs, are critical to design-ers. However, it is hard to use existing architecture-lev-el energy estimators to obtain accurate estimates for accelerator designs, as accelerator designs are diverse and sensitive to data patterns.To solve this problem, we present Accelergy (Fig-ure 1), an architecture-level energy estimation method-ology. Accelergy allows the users to define their own components in their designs to allow descriptions of the diverse design space. At the same time, to reflect the energy differences brought by special data patterns, e.g., sparsity in data, Accelergy also allows the users to define special actions types related to the components. To enhance flexibility, Accelergy defines an interface to communicate with other estimators that focus on en-ergy estimations of specific types of components in the designs (e.g., memory storage components). To illustrate the usage of Accelergy methodology, we implemented an example framework for energy estimations of deep neural network (DNN) accelerator designs. We further integrate Accelergy with Timeloop, a DNN mapping space exploration tool, to enable accurate estimation of processing-in-memory (PIM) based DNN accelera-tor designs. We validated the Accelergy framework on a conventional digital design Eyeriss as well as a PIM-based design, both achieving a total energy estimation accuracy of 95% and accurate energy breakdowns of various components in the designs (Figure 2).

Low-frequency Buckled Beam MEMS Energy Harvester

Vibrational energy harvesting at the MEMS scale is a unique challenge for low-frequency sources which are ubiquitous but do not operate at resonant frequencies of structures on the micro scale. It is nature’s law that resonant frequency is inversely proportional to mass, which is a great challenge for micro-scale energy har-vesting devices operating at low frequencies (less than 100Hz). A bi-stable buckled beam design is presented that does not rely on resonance of a MEMS structure but rather operates by snapping between buckled states at low frequencies. A fully functional piezoelectric MEMS energy harvester is designed, monolithically fabricated, and tested. An electromechanical lumped parameter mod-el is developed to analyze the nonlinear dynamics and to guide the design of the nonlinear oscillator-based energy harvester. Multi-layer beam structure with re-sidual stress induced buckling is achieved through the progressive residual stress control of the deposition processes along the fabrication steps. Dynamic test-ing, however, demonstrated that optimizing the beam stiffness to proof mass ratio was challenging given the presence of undesired modes of vibration. A new iter-ation of the design was fabricated with changes to the proof mass geometry which stabilize the oscillations by reducing rotational inertia, a key variable in enhanc-ing dynamic performance of the device.

A CMOS-based Energy Harvesting Approach for Laterally-arrayed Multi-bandgap Concentrated Photovoltaic Systems

When high solar conversion efficiency is desired, peo-ple often adopt concentrated photovoltaic systems with multi-junction cells. However, traditional tandem structures widely used in such systems can suffer from current-mismatch effects with spectrum variations, whereas the Laterally-Arrayed Multi-Bandgap (LAMB) cell structure is a potentially higher-efficiency and lower-cost alternative.Here we show an energy harvesting approach de-signed to take full advantage of the LAMB cell struc-ture. Individual cells within a sub-module block are connected for approximate voltage-matching, and a Multi-Input Single-Output (MISO) buck converter combines the energy and performs Maximum Pow-er Point Tracking locally. A miniaturized MISO dc-dc converter prototype is developed in a 130nm CMOS process. For 45-160mW power levels, >95% peak effi-ciency is achieved in a small form factor designed to fit within available space in a LAMB cell block. The results demonstrate the potential of the LAMB CPV system for enhanced solar energy capture.

Engineering a 2D Hole Layer in Hydrogen-terminated Diamond Using Transition Metal Oxides

The quest for a suitable wide-bandgap semiconductor for high-power and high-frequency applications is well motivated; wide-bandgap semiconductors generally ex-hibit a high breakdown field and can therefore support a high voltage over short distances. Diamond (5.5 eV) in particular is an attractive prospect since its thermal conductivity and radiation hardness far surpass that of other wide-bandgap semiconductors. However, practi-cal transistors require the ability for the charge density to be engineered through substitutional doping, which has proven to be difficult considering the strong cova-lent bonds that make up bulk diamond.We use an alternative doping mechanism, surface transfer doping; it takes advantage of the unformed bonds at the diamond surface and generates a highly conductive 2D hole sheet at the surface with carrier densities up to 1014 cm-2. Surface transfer doping using stable high electron affinity transition-metal oxides (TMO) such as WO3 along and the novel contact-first process explored in this work shows great promise to advance process stability while maintaining the high current densities desired for future power diamond transistors. We are exploring various methods to reproducibly achieve high values of sheet hole concentration and hole mobility on the diamond surface that can be in-corporated into a transistor fabrication process. Our proposed design for characterizing mobility and sur-face conductivity combines a transmission line and Van der Pauw test structures simultaneously, as shown in Figure 1. We chose tungsten as the ohmic contact for its thermal stability and attractive process character-istics. We are examining different H-plasma processes for diamond surface bond passivation and the use of the hydrogen isotope deuterium. Preliminary results show increased carrier concentration and mobility with Al2O3 as the surface dopant, as in Figure 2. The methods explored in this work show promise towards the enhancement of diamond conductivity and repro-ducibility.

Dynamic Approach to Quantifying Strain Effects on Ionic and Electronic Defects in Functional Oxides

The search for novel electronic and magnetic properties in functional oxides has generated a growing interest in understanding the mobility and stability of ionic and electronic defects in these materials. Instead of altering material content, most research views mechanical strain as a lever for modulating defect concentration and mobility more finely and continuously in both semi-conductors and functional oxides. Previous studies also proposed that strain may increase ionic mobility by orders of magnitude, which is crucial for lowering the operation temperature of solid oxide fuel cells.However, experimental and computational results from research groups differ significantly due to the convoluted effect of mechanical strain and film/substrate interface on defect content and mobility. Such reliance on substrate selection to induce strain in the oxide thin film also limits the range of strain accessibility, with limited data available to dateWe have developed an experimental technique that facilitates application of in-plane strain to functional oxide thin films continuously on the same substrate. First, we combine photolithography and metal sputtering in MIT Nano to deposit an interdigitated Pt electrode down to a 2-micrometer finger distance on our sample (Figure 1). Next, we conduct 3- or 4-point bending and concurrent conductivity measurement of the thin film-on-substrate device (Figure 2). This approach is accessible to a wide temperature range and has precise gas control relevant to mixed ionic-electronic conducting oxides with extremely high reproducibility (error < 3%) over a long period of time. We can strain and measure the transport properties of the same functional oxide thin film at high temperature in situ, over a range of strains applied to a single system. Combining these experiments with our ab initio computational simulations and predictions of carrier dominance over a range of strains and temperatures, we also aim to measure the carrier mobility in Nb-doped SrTiO3 as a function of applied strain, to observe the sudden change of carrier mobility and temperature dependency. We believe this will also be a powerful technique for studying the strain effect on surface reactions like exsolution or catalytic reaction.

First Demonstration of GaN CMOS Logic on Si Substrate Operating at 300 Degrees C

The power density (and form-factor) of power electronic circuits is mostly dominated by the size of the passive energy storage components like inductors and capacitors, which depend on the switching frequency. Increasing the switching frequency of power electronic circuits can significantly reduce the energy storage requirement of these components to allow for smaller components. However, the maximum operating frequency of state-of-the-art GaN transistors, promising candidates for high-voltage compact switches, is usually limited by the gate inductance between the gate electrode and the driver circuit. Monolithically integrating the GaN-based driver circuit with that of the GaN power transistor on the same chip can significantly reduce this inductance.To increase the efficiency of such GaN-based integrated circuits, a CMOS-like circuit technology is needed. Major benefits of such a technology include zero/negligible static power dissipation, higher noise immunity, and linearity. However, the lack of high-performance GaN p-FETs and the challenges of their monolithic integration with E-mode n-FET devices are major roadblocks towards achieving such a technology. This work demonstrates a new GaN-based complementary circuit platform on 6-inch Si substrate. Figure 1(a) shows the voltage transfer characteristics (VTC) of the inverter for a VDD of 5 V along with output current. The inverter shows a record voltage gain of 27 V/V for a voltage switching of 0-to-5 V. Figure 1(b) shows the VTC of the same inverter for VDD=3 V, exhibiting excellent inverting behavior with Vswing=2.91 V and maximum gain of ~15 V/V. The dynamic switching of the inverter was characterized by connecting the inverter input to a pulse generator and the output to the high impedance port of an oscilloscope. The VDD was kept at 3 V because of the high gate leakage in the p-GaN gated n-FET above that voltage. The voltage of the input pulses varied from −0.2 V to 3 V with a ramp time of 100 ns. Figure 1(c)-(d) presents measured waveforms of the input and output signals. The output signal showed a voltage swing close to 0~3 V. The fall time was 1 µs; the rise time was 20 µs. It should be noted that these times represent an upper bound on the fall and rise times, as the very high input capacitance of the oscilloscope port (~ 350 pF) limits the measurements.High-temperature measurement of the inverter shows a reduction in the voltage gain, as shown in Figure 2. The maximum available voltage swing at the output is also reduced due to the rise of low-level Vout, which can be attributed to the reduction in ON-OFF current ratio of the p-FET at high temperature. At high temperature, because of the higher activation of Mg dopants, the threshold voltage of p-FET moves towards the positive zone, making it D-mode, which in turn reduces the ON-OFF current ratio. While room exists for significant performance improvement, this demonstration opens a number of application domains for GaN such as integrated CMOS driver circuits, CMOS logic, logic, and signal conditioning under harsh environment operation, among many others.

100-nm Channel Length E-mode GaN p-FET on Si Substrate

GaN-CMOS-technology could be instrumental towards realizing high-power-density, high-speed, low-form-factor, and highly-efficient power electronic circuits, which sparked many efforts to develop a high performance GaN p-FET. However, most of these demonstrations show normally-ON operation with ON-resistance over 1 kΩ∙mm. GaN/AlInGaN heterostructure-based p-FET shows low ON-resistance because of higher 2-DHG density and hole mobility but with D-mode operation. A GaN/AlN heterostructure based p-FET shows E-mode operation with RON of 640 Ω∙mm. However, n-FET integration with this p-FET requires regrowth. In this work, we demonstrate a self-aligned p-FET with a GaN/Al0.2Ga0.8N (20 nm)/GaN heterostructure grown by metal-organic-chemical vapor deposition (MOCVD) on Si substrate. The utilization of GaN-on-Si platform offers lower cost, availability of 200-mm-diameter substrates, and potential to integrate with high performance logic and analog functionality. While most of the GaN p-FET demonstrations so far in the literature mainly focused on recessed gate MISFET structure, we choose to develop a self-aligned structure (see Figure 1 for the device structure) as it offers the following advantages over a recessed gate MIS p-FET: (1) the shortest possible source to the drain distance, cutting down the access region; (2) low ON-resistance because of negligible access resistance: and (3) easier gate alignment.Our 100-nm channel length self-aligned device with recess depth of 70 nm exhibits a record ON-resistance of 400 Ω∙mm and ON-current over 5 mA/mm with ON-OFF ratio of 6×105 when compared with other p-FET demonstrations based on a GaN/AlGaN heterostructure (see Figure 2 for benchmarking of our device with other p-FET demonstrated in the literature). The device shows E-mode operation with a threshold voltage of −1 V, making it a promising candidate for a GaN-based complementary circuit that can be integrated on a Si platform. A monolithically integrated n-channel transistor with p-GaN gate is also demonstrated.

Characterizing and Optimizing Qubit Coherence Based on SQUID Geometry

Superconducting qubits are leading candidates to implement quantum hardware capable of performing certain computational tasks more efficiently than their classical counterparts. A prerequisite for scalable quantum computation is a sufficiently low noise level in the participating qubits. The dominant source of decoherence in frequency tunable superconducting qubits is 1/f flux noise, presumably originating from magnetic defects located at the interfaces of their SQUID loops. Here, we measure the flux noise amplitudes of more than 50 capacitively shunted flux qubits and study their dependence on geometric parameters of their SQUID loops. Each of six chips (Figure 1) holds ten capacitively shunted flux qubits, featuring two copies of five different SQUID loop geometries, respectively. Dispersive readout of each qubit is performed using a common transmission line and individual readout resonators. We perform a series of spin-echo measurements in the vicinity of the flux sweet spot of the qubits, showing that the pure dephasing rate is proportional to the slope of the qubit spectrum, which is in turn related to the flux noise amplitude for each qubit. Our data (Figure 2) show good agreement with a previously presented microscopic model for independent spin impurities, which has so far eluded experimental verification. Due to a limited applicability of the proposed model for superconducting films of finite thickness, we provide numerical simulations of the current distribution in our SQUIDs, which extend and refine the considered model. Our improved model is in excellent quantitative agreement with our data both in terms of absolute numbers and geometry dependence (Figure 2b). Our results demonstrate that flux noise is suppressed in SQUIDs with small perimeters, fat wires, and thick superconducting films therefore serve as a guide for minimizing the flux noise susceptibility in future circuits.

Control of Conducting Filaments Properties in TiO2 by Structural and Chemical Disorder for Neuromorphic Computing

Resistive switching (RS) random access memories are considered as possible artificial synapses in next-generation neuromorphic networks, mostly due to their predicted high memory density, energy efficiency and scalability. Integration of these devices in a neuromorphic computing system could allow solving intensive computing tasks actually only handled by the human brains such as speech and character recognition as well as grammar and noise modeling. Within their architecture, redox-based RS memory devices store binary code information using the electric field-induced resistance change of an oxide layer by conductive filament (CF) formation and rupture (Figure 1a). Nevertheless, a lack of control on the properties of CFs, which mainly forms at chemical and structural defects, causes detrimental cycle-to-cycle and device-to-device variations. We are therefore studying the effect of strain on the microstructure, chemistry and RS properties of TiO2 thin films to get insights into defects formation with the objective of selectively doping along these defects (Figure 1b). We found that the microstructural properties of pulsed laser deposited epitaxial TiO2 films depend on both the film thickness and the nature of the bottom electrode, suggesting a potential method to better control defects properties and improve consistency in RS.

Manipulation of Coupling and Magnon Transport in Magnetic Metal-insulator Hybrid Structures

Ferromagnetic metals and insulators are widely used for generation, control, and detection of magnon spin signals. Most magnonic structures are based primarily on either magnetic insulators or ferromagnetic metals, while heterostructures integrating both of them are less explored. Here, by introducing a Pt/yttrium iron garnet (YIG)/permalloy (Py) hybrid structure grown on Si substrate (Figure 1(a)), we studied the magnetic cou-pling and magnon transmission across the interface of the two magnetic layers. After the film growth by mag-netron sputtering, atomic force microscopy (AFM) mea-surements were performed (Figure 1(b)) to characterize the film quality, which indicates a surface roughness of approximately 1 nm. Moreover, we found that with-in this structure, Py and YIG exhibit an antiferromag-netic coupling field as strong as 150 mT, as evidenced by both the vibrating-sample magnetometry (VSM) (Figure 1(c)) and polarized neutron reflectometry mea-surements. By controlling individual layer thicknesses and external fields, we realize parallel and antiparallel magnetization configurations, which are further uti-lized to control the magnon current transmission. We show that a magnon spin-valve with an ON/OFF ratio of ~130% can be realized out of this multilayer structure at room temperature through both spin pumping and spin Seebeck effect experiments. Owing to the efficient control of magnon current and the compatibility with Si technology, the Pt/YIG/Py hybrid structure could po-tentially find applications in magnon-based logic and memory devices.

Nonvolatile Control of Long-distance Spin Transport in an Easy-plane Antiferromagnetic Insulator

How an antiferromagnet transmits spin angular momentum by the quanta of spin-wave excitations, viz. magnons is one of the core topics of antiferromagnetic magnon spintronics. It is generally believed that only easy-axis antiferromagnets can support spin transmis-sion, a natural inference of the fact that the circularly polarized magnons there have finite spin angular momentum. In contrast, easy-plane antiferromagnets would destroy spin transport due to the vanished angular momentum carried by their linearly polarized magnons.In this work we show that contrary to this traditional picture, spin transmission over micrometer distance indeed happens in an easy-plane insulating antiferromagnet, α-Fe2O3 thin film. A model involving superposition of linearly polarized propagating magnons is proposed to account for the observations. Enabled by this physical insight, our work opens up additional possibilities for nonvolatile, low magnetic field control of spin transmission, where a spin-current switch with a 100% on/off ratio is realized.

Gigahertz Frequency Antiferromagnetic Resonance and Strong Magnon-magnon Coupling in the Layered Crystal CrCl3

Antiferromagnetic spintronics is an emerging field with potential to realize high-speed memory devices. Compared to ferromagnetic materials, antiferromagnetic dynamics are less well understood, partly due to their high intrinsic frequencies that require terahertz techniques to probe. Here, we introduce the layered antiferromagnetic insulator CrCl3 as a tunable platform for studying antiferromagnetic dynamics. Because of weak interlayer coupling, the antiferromagnetic resonance (AFMR) frequencies are within the range of typical microwave electronics (<20 GHz). This allows us to excite different modes of AFMR and to induce a symmetry-protected mode crossing with an external magnetic field. We further show that a tunable coupling between the optical and acoustic magnon modes can be realized by breaking rotational symmetry. Recently, strong magnon-magnon coupling between two adjacent magnetic layers has been achieved, with potential applications in hybrid quantum systems. Our results demonstrate strong magnon-magnon coupling within a single material and therefore provide a versatile system for microwave control of antiferromagnetic dynamics. Furthermore, CrCl3 crystals can be exfoliated down to the monolayer limit, allowing device integration for antiferromagnetic spintronics. We transferred layered bulk CrCl3 onto a coplanar waveguide (CPW) and secured it with Kapton tape. The crystal c-axis is normal to the CPW plane. We measure microwave transmission in a cryostat by fixing the excitation frequency and sweeping the applied magnetic field. When the field is applied in-plane and parallel to the in-plane radio frequency field, both acoustic and optical modes of AFMR are observed. The mode frequency evolutions are well-described by theoretical formulas. When the field is canted out-of-plane, two magnon modes hybridize because of rotational symmetry breaking, and the coupling strength is tunable by rotation angle. Our results demonstrate that CrCl3 serves as a convenient platform for studying AFMRs in microwave frequencies and shows the possibility to realize magnon-magnon coupling utilizing van der Waals assembly.

High-density Microwave Packaging for Superconducting Quantum Information Processors

Quantum information processors hold the promise to solve specific computational problems much faster than classical computers. Superconducting qubits are among the leading candidates for realizing near-term quantum processors. Beyond lithographic scalability, superconducting qubits offer long computational operation windows–coherence times–relative to short operational gate times that have enabled the demonstration of the first practical quan-tum algorithms. Despite this progress, engineering challenges must be met to further scale these devices. In particular, qubits require a precisely engineered microwave environment to suppress energy decay and corresponding information loss. For instance, the corruption of information can occur due to lossy package modes interacting with the qubit electric field. As the number of qubits increases, qubit packages must be adapted to support an increasing number of input/output ports without adding additional loss channels.Our qubit package, shown in Figure 1 (a), provides a well-defined electromagnetic (EM) environment. It consists of an aluminum-coated copper cavity and a microwave interposer with 32 waveguides. We performed full-wave simulations of the signal launches, the package cavity, and superconducting wirebonds to establish principles needed to construct larger packages. We evaluated the presence and absence of lossy package modes using high-coherence qubits as sensors, illustrated in panel (b). A weakly driven package mode causes EM-field enhancement with increased microwave photon number fluctuations, which, when coupled to the qubit, shifts its energy levels. The resulting qubit energy fluctuations result in qubit dephasing inferable via Ramsey interferometry. Sweeping a probe tone in frequency while monitoring the coherence time reveals the presence of parasitic package modes. Panel (c) exhibits a mode-free operating environment up to 11 GHz. Our EM model can reproduce the observed package modes, shown in panel (d). Current work focuses on the design of packages to support more complex qubit chips and modular interconnects to facilitate fast chip exchange.

Scanning Transmission Electron Microscopy Imaging of Materials

Properties of materials are controlled by the arrangement and type of atoms in the structure. Many characterization techniques can provide information about the crystal structure and micro scale features, but atomic scale information is critical for fully understanding a material system. Through advanced scanning transmission electron microscopy (STEM) techniques, atomic column intensity and positions can be extracted to provide useful information about ordering, local distortions, and defects.Materials such as strontium titanate, SrTiO3, demonstrate the capabilities of this powerful imaging technique. Annular dark field (ADF) STEM imaging shows atom column contrast from Sr and Ti cations, as expected from the crystal structure, but no contrast from the oxygen anion atom columns due to the low atomic number of oxygen (Figure 1 a). Integrated differential phase contrast (iDPC) imaging in the STEM mode makes the lighter oxygen atoms visible (Figure 1 b). Additionally, the electric field vector map in projection can be found from the differential phase contrast data acquired from a four-segment detector (Figure 1 c). Projected charge density maps obtained from differential phase contrast imaging clearly show symmetrical charge contours revealing non-polar behavior in the SrTiO3 sample (Figure 1 d). Such a projected charge density imaging technique is useful in studying polar functional material.The positions and intensity of each atom column can be extracted from the STEM images using image analysis techniques. Detailed, quantitative analysis of bond lengths, bond angles, and atomic contrast can be used to find regions of order, local distortions, and defects. Structural nanoscale features such as ferroelectric/ferromagnetic domains or chemical/distortion-ordered regions can be correlated with the electrical, mechanical, ferroelectric, magnetic, and other properties of the material to elucidate the nanoscale origin of macroscale properties.

Degradation Under Forward Bias Stress of Normally-off GaN High Electron Mobility Transistors

Energy-efficient electronics have been gaining much attention as a necessary path to meet the growing demand for energy and sustainability. GaN field-effect transistors (FETs) show great promise as high-voltage power transistors due to their ability to withstand a large voltage and carry a high current with minimum losses. For best circuit reliability and performance, a normally-off transistor is highly desirable. An attractive design is the p-doped gate AlGaN/GaN high electron mobility transistor (p-GaN HEMT).Our research aims to better understand the reliability issues impeding widespread adoption of p-GaN power HEMTs for power management applications. One key issue is device degradation under electrical stress, where key device performance figures such as the threshold voltage and the gate leakage current change with electrical stress.Understanding reliability issues of p-GaN power HEMTs is obstructed by the complex gate stack of the devices. First, both holes and electrons are present in the gate stack: holes in the p-doped GaN region and electrons in the 2-dimensional electron gas at the AlGaN/GaN interface. Furthermore, holes and electrons encounter several barriers (shown in the energy band diagram of Figure 1), obfuscating understanding of the electrostatics and transport physics under forward-bias stress. Coupled with the often time-dependent nature of degradation, p-GaN power HEMT reliability remains difficult to fully understand. For instance, Figure 2 shows the time evolution of the gate leakage with different constant gate voltage stress. As can be easily seen, the gate leakage current decreases with time at lower biases and high biases but increases with time at intermediate biases, showing a complex multi-regime behavior. Nevertheless, an on-going reliability analysis such as breakdown voltage indicates that p-GaN HEMTs show great promise as robust and efficient next-generation power transistors.

Vertical Leakage Characteristics of GaN Power Transistor

The great promise of Gallium Nitride Metal-Insula-tor-Semiconductor High Electron Mobility Transistors (GaN MIS-HEMTs) in the growing power electronic market has rapidly positioned these devices at the forefront of a new technology wave. This has triggered a vast amount of worldwide research and yielded con-tinuous improvements in device performance and electrical reliability. Regarding reliability, a key consid-eration in any new device technology, the maximum breakdown voltage is ultimately limited by the vertical breakdown of the drain-body junction. This is particu-larly a concern for devices with conductive substrates. A way to mitigate premature drain-body break-down under high positive drain voltage consists of ap-plying a positive voltage to the body with respect to the source so that the drain-body voltage can be reduced. A potentially problematic consequence of this is exces-sive source-body leakage current under off conditions. This is undesirable. In this work, we study the source-body leakage in commercially prototype devices for negative voltage at the source with respect to the body. Figure 1 shows the body current as the source is swept negative and then positive at 26. The different paths that are followed and the “eye” that appears could be due to trapping or a floating-body effect. Figure 2 shows the temperature dependence of the negative sweep. The sharp corner in the characteristics that coincides with the maximum widening of the “eye” opening ap-pears to have a negative temperature coefficient of -0.13 eV. These and other interesting features are critical to understanding the origin of the reverse bias source-body current so that it can be suppressed.

Quantum Landscape Engineering of Superconducting Circuit Ground States for Higher-order Coupler Design

Superconducting circuits provide a versatile engi-neering platform for the study of quantum systems and their use as a computational resource. Their ap-plication ranges from studying fundamental princi-ples such as the physics of quantum entanglement to the demonstration of large-scale control of quantum bits simulating spin models in solid state physics. Many-body interactions of multiple spins simultane-ously are one aspect of spin models that has not been demonstrated to date.In this work, we exploit that the response of the quantum ground state energy of a superconducting cir-cuit to external magnetic flux can be shaped by design to engineer artificial spin couplers. We propose a meth-odology for adding higher-order polynomial terms into the ground state energy versus flux by strongly cou-pling a series of rf SQUIDs. The fundamental instance of two rf SQUIDs generating a ground state with 4th-or-der terms is implemented experimentally. Probing this circuit with a sensor flux qubit, the qubit’s transition frequency maps the derivative of the quartic ground state in accordance with simulation. Modest levels of qubit coherence are maintained despite the relatively strong inductive coupling. These results demonstrate the viability of this design for use as a 4-local coupler and show promise for extending it to higher polynomi-al order.

Vertical Gallium Nitride FinFETs for RF Applications

From wireless communication systems like the 4G and 5G cellular services that enable 4K video streaming, to the high-resolution radars that are vital to national defense, radio frequency (RF) systems have become a ubiquitous part of modern life. A fundamental building block within these systems is the RF power amplifier. As amplifier technology progresses, the relentless de-mand for improved performance necessitates develop-ment of new transistor technologies that can operate at higher power levels and over larger bandwidths. While traditional planar processing techniques have led to countless successful RF amplifiers, the fact that all conduction takes place very near the wafer’s surface fundamentally limits their performance. If instead we utilize a compact vertical transistor design, the bulk material can be used to withstand large voltages in the vertical direction as opposed to lateral designs, which need large device areas. Additionally, bulk conduction improves thermal spreading, thereby reducing cooling needs, and vertical gate patterning techniques trade ex-pensive high-resolution lithography for relatively easy control of etch depth. This work presents novel vertical GaN RF tran-sistors. As the cross-sectional diagram in Figure 1 shows, the vertical GaN RF finFET consists of narrow fins to confine the current and has sidewall gates to modulate the conductivity within the fins. To enable high-frequency system integration, these devices were fabricated on sapphire, a highly insulating substrate, with a top-side drain contact to remove the need for through-wafer vias. To reduce costs and allow easier integration with existing technology, the same devices can be fabricated on GaN on Si as well. Figure 2 shows a scanning electron microscope (SEM) cross section of a fabricated device. These devices achieve a current den-sity of over 7 kA-cm-2 and a power gain cut-off frequen-cy, fmax, of 5.9 GHz, demonstrating a promising first step toward vertical GaN transistors in RF applications.

Towards Sub-10-nm-Diameter Vertical Nanowire III-V Tunnel FETs

Recently, III-V compound semiconductors have emerged as a promising family of materials for future complementary metal-oxide semiconductor (CMOS) technology, thanks to their superior electron trans-port properties. To enable continued scaling, a high aspect-ratio vertical nanowire (VNW) transistor geom-etry with a gate-all-around (GAA) structure is highly fa-vorable due to effective charge control and robustness to short-channel effects. Another big advantage of the vertical nanowire geometry is that it allows engineer-ing of the energy band structure along the transport di-rection, enlarging the device design space. In particular, device structures that potentially break the thermal limit of the subthreshold behavior become possible. In our research, we are pursuing the demonstra-tion of broken-band GaSb/InAs vertical nanowire tun-nel field-effect-transistors (TFETs) with sub-10-nm di-ameter for ultra-low power logic applications. We aim to exploit the recent demonstration of high-quality III-V MOS interface characteristics using in-situ ther-mal atomic-layer etching in combination with atomic layer deposition of the gate stack.In our work, we have developed a top-down ap-proach for sub-10-nm VNW fabrication, as shown in Figure 1. Hydrogen silsesquioxane (HSQ) hardmask is patterned by electron beam lithography (EBL), fol-lowed by Cl-based reactive-ion-etching (RIE) and al-cohol-based digital etch (DE). Planarization is anoth-er critical step, in which insulating layers are formed around the VNWs with good vertical location control. We have developed a method to accurately control the thickness of an HSQ film using EBL with different elec-tron doses. Figure 2 shows the final height of HSQ as a function of e-beam dose. The insets in Figure 2 show an example of a 60- nm-thick planarized HSQ spacer formed around a 230-nm-high InAs VNW.

W Contacts to H-terminated Diamond

Diamond is considered a leading candidate for harsh environment high-power electronics due to their ex-traordinary thermal and electrical properties. One of the many challenges facing diamond electronics is creating reliable and stable ohmic contacts to hydro-gen-terminated diamond (D:H). In this work we ex-plored a novel approach for scalable and self-aligned ohmic contacts to D:H. Our results show that using this approach stable ohmic contacts can be obtain with state-of-art contact resistance. The diamond surface conductivity is governed by its surface termination. H-termination leads to a con-ductive surface, while O-termination (D:O) results in in-sulating diamond. The different terminations are typi-cally obtained by exposing the diamond surface to H or O plasma (fig. 1). Since in D:H all the dangling bonds are practically passivated, it is typically hydrophobic and suffers from poor adhesion to most materials which are only weakly attached by Van der Waals forces. D:O however, is hydrophilic and can provide good adhesion. This create a problem for ohmic contacts which usually need to be laid over a conductive surface. To overcome this issue in our approach we first pattern W contact on D:O providing good adhesion. After this, the dia-mond surface is exposed to the H plasma. We use W in this approach since it is one of the few metals that can withstand prolongued exposure to H plasma at elevat-ed temperature without being damaged or go through embrittlement.To test our approach, we fabricated four terminal TLM test structures with nano contacts. From the anal-ysis of the data (Fig. 2), we extract the contact resistance (black markers), as well as the D:H (blue markers) as a function of contact length Lc (Fig. 1 right). Since this is a ‘side contact’, it does not follow the classical transfer length behavior obtained when Ohmic contacts are overlapping a conductive surface (Fig. 2, full line). Rath-er, the contact resistance is insensitive to the contact length. Notably, the sheet and contact resistance are in par with other approaches to obtain ohmic contacts to D:H.

Cryogenic GaN HEMT Technology for Application in Quantum Computing Electronics

High performance and scalable cryogenic electronics is an essential component of future quantum informa-tion systems, which typically operate below 4K. Cur-rent electronics rely on technology like CMOS (Si), or heterojunction bipolar transistor (e.g. SiGe, InP). This work explores the use of wide band gap het-erostructure electronics, specifically the AlGaN/GaN high electron mobility transistor (HEMT), for cryo-genic low-noise applications. These structures take advantage of the polarization-induced two-dimen-sional electron gas to create a high mobility channel, hence eliminating the use of heavy doping as in the other semiconductor technologies. Epitaxially-grown GaN-on-Silicon wafers are available in large (8 inch / 200 mm) substrates, therefore making the technology an excellent candidate for scalable RF electronics in quantum computing systems.Furthermore, the use of electrodes using supercon-ducting materials is proposed to significantly reduce the parasitic components and therefore push the RF performance of cryogenic devices. Short-channel tran-sistors with NbN gates of length 100 nm have been demonstrated with promising performance.In the next step, the effect of the superconduct-ing gate on RF characteristics of the transistors will be studied, with the eventual goal of pushing the fre-quency performance of these transistors to new limits. These transistors will be integrated into low noise am-plifier circuits for applications in readout and control electronics at cryogenic temperature. Furthermore, the developed cryogenic GaN HEMT technology would bring us one step closer to an all-nitride integrated elec-tronics-quantum device platform.

Quantitative Study on Current-induced Effects in an Antiferromagnetic Insulator/Pt Bilayer Film

Electrical control and detection of magnetic ordering inside antiferromagnets have attracted considerable interests, for making next generation of magnetic random access memory with advantages in speed and density. However, a full understanding of the recent prototypical spin-orbit torque antiferromagnetic mem-ory devices requires more quantitative and systematic study. Here we study the current-induced switching in a canted antiferromagnetic insulator α-Fe2O3, similar to previous demonstrations of antiferromagnetic memo-ries, but make good use of its uniquely small spin flop field. We compare the current-induced Hall resistance to the field-induced one, and look into the nature of the switching. We raise the concern that the signal in these memory devices can be complicated by two neglected sources that are unrelated to spin-orbit torques, while the contributions from spin-orbit torques are much smaller than expected. This work provides a pathway towards the clear realization of a spin-orbit torque antiferromagnetic insulator memory device.We epitaxially grew the α-Fe2O3 (0001) film on α-Al2O3 substrate. In Pt/α-Fe2O3 bilayer, we found a typical antiferromagnetic spin Hall magnetoresistance (SMR). We performed the conventional current-in-duced switching in the Hall cross devices and obtained a sawtooth-like behavior. However, it remained almost unchanged under magnetic field, which means a purely resistive switching. To exclude that, we measured the angle-dependent SMR curve subject to an in-plane ro-tating field when applying different sensing currents. The current always tilts the Néel vector towards itself, which is quantified by two effective magnetic energy changes, with 180° and 360° angle period, respectively. Macrospin simulation based on the conventional damp-ing-like torque cannot reproduce the results, while a newly-proposed thermo-magnetoelastic effect well ex-plains the data. The 360° period energy change, instead, can be explained by a field-like spin-orbit torque.

High-performance 2D Material Devices for Large-scale Integrated Circuits and Power Electronic Applications

Among all the possible back-end-of-line (BEOL) solu-tions to improve the integration density and func-tionality of conventional silicon circuits, 2D material devices are believed to be very promising, due to their high mobility, relatively large band gaps, and atom-lev-el thickness. These devices are beneficial for both logic integrated circuits and power electronic applications. However, the large area growth of high quality 2D ma-terial thin films and 2D material devices and achieving low contact resistance have always been challenging and hinder the development of 2D material devices and circuits.Recently, by using Au contacts and MOCVD tech-nique, we have fabricated back-gated MoS2 transistors on 4-inch MoS2 wafer with 200-nm channel length and have obtained excellent device performance, i.e., high on-state current of around 220 µA/µm (Figure 1) and low contact resistance of around 9.9 kΩ·µm (Figure 2). In order to have larger scale 2D materials with better quality, we are currently building a MOCVD system in EML labs to grow 2D materials, e.g., MoS2 and WSe2, on 6-inch wafers. We are also using Li-induced phase tran-sition in the source/drain regions to further reduce the contact resistance of 2D material transistors. Moreover, top-gated MoS2 transistors with a multilayer hBN gate dielectric are also being investigated to improve the gate controllability and the mobility of the channel ma-terials. In the very near future, we hope to demonstrate 2D material circuits, such as multiplexers, and DC-DC converters with high performance 2D material devices.

Polarization Switching in Highly Scaled Ferroelectric MOS Capacitor

Ferroelectric FETs (FeFET) are promising candidates for low-power, scalable, and non-volatile memory-enabling applications such as in-memory computing, artificial intelligence (e.g., analog synapses, coupled oscillator networks, spiking neurons) and quantum computing (i.e., cryogenic memory). Ultra-thin doped HfO2 based thin-films have emerged as an attractive option for FeFETs due to precise thickness control through atom-ic layer deposition (ALD) and Complemnetary Metal Oxide Semiconductor(CMOS) compatibility. However, the design space of a FeFET-based memory that op-erates with a low supply voltage, a sufficient memory window, and high endurance is not well understood. In this work, we systematically investigate ferroelectric Hf0.5Zr0.5O2 MOS capacitors to study the electrostatics of the device, which solidifies the design criteria for low voltage FeFETs. In this study, MOS capacitors (Figure 1) are fabri-cated on p-Si wafers using standard CMOS processing with different ferroelectric thicknesses. The dielectric constant, k, of the annealed Hf0.5Zr0.5O2 film is higher than those of HfO2 and ZrO2(k = 25) for all thicknesses, as observed in the small signal capacitance-voltage (C-V) characteristics (Figure 2) due to the film’s orthorhom-bic phase. At low gate biases, the HZO film is hystere-sis-free (Figure 2 inset) and shows negligible frequency dispersion, indicating a high-quality interface. At high gate bias, the thinner films show rapid increase of the capacitance, resembling the peak of butterfly-like be-havior of standard ferroelectric capacitors as the net charge exceeds the critical charge required to achieve the coercive field. However, this behavior is absent in the thick HZO film, where the coercive field is higher than the breakdown field. The high dielectric constant and relatively low effective charge of the ferroelectric thin film, in combination with the ultrathin SiO2 inter-layer, enables the polarization switching of the thinner dielectrics. This is the first observation of polarization switching ferroelectric MOS capacitors using small-sig-nal measurement.These results indicate that our technology can enable FeFETs operating at 2.5 V with highly scaled dielectrics (tFE =5 nm) that are required for a future transistor topology. This is a significant improvement compared to state-of-the-art flash memory. However, to enable lower switching voltage FeFET, additional materials and device engineering would be required as the switching voltage weakly scales with ferroelectric thickness.

First Demonstration of GaN Vertical Power FinFETs on Engineered Substrates

GaN vertical power Fin Field Effect Transistors (Fin-FET) are promising high-voltage switches for the next generation of high-frequency power electronics ap-plications. Thanks to a vertical fin channel, the device offers excellent electrostatic and threshold voltage control, eliminating the need for epitaxial regrowth or p-type doping, unlike other vertical GaN power tran-sistors. Vertical GaN FinFETs with 1200 V breakdown voltage (BV), 5 A current rating and excellent switching figures of merit have been demonstrated recently on free-standing GaN substrates. Despite this promising performance, the commercialization of these devices has been limited by the high cost ($50-$100/cm2) and small (~ 2 inch) diameter of free-standing GaN sub-strates. The use of GaN-on-Si wafers could reduce the substrate cost by 1000; however, the growth of the thick (~10 μm or thicker) drift layers required for kV class applications is extremely challenging on Si. Alter-natively, GaN grown on engineered substrates (QST®) with a matched thermal expansion coefficient could enable low-cost vertical GaN FinFETs with thick (>10 μm) drift layers and large wafer diameters (8-12 inch). In this work, we have demonstrated a quasi-vertical GaN FinFET on engineered QST® substrates for the first time.A conformal oxide-based planarization and etch-back technology was used for gate etching and source-to-gate spacer etching. The device demonstrates a cur-rent density of JDS=3.8 kA/cm2 at VGS= 1.5 V and VDS= 4 V (Figure 2), and a maximum gm = 2 kS/cm2 at VDS= 4 V when normalized with respect to the total device area (fin width and spacing between fins), a record for vertical and quasi-vertical MOSFETs on non-GaN sub-strates. The current density in each fin is higher than 30 kA/cm2 at the same bias condition. The on-resis-tance is currently limited by non-ideal source contacts, as is evident in the Schottky-like behavior of the drain current at low VDS. The source contact resistance can be improved by either higher doping density or rapid thermal annealing of the metal stack after contact for-mation. The results are very promising for large wafer scale manufacturing and commercialization of vertical GaN power FinFETs.

Tuning Plant Cell Culture Parameters for Improved Model Physiologies

In vitro plant culture models provide valuable insights into factors governing plant growth and development. Improved understanding of genetic and biochemical pathways in plants has facilitated advancements in a variety of industries —from guiding the development of more robust crops, to enabling increased biofuel yields by tuning biomass genetics. Despite the utility of plant culture models, translation of cellular findings to the plant-scale is hindered in current culture systems. These limitations are, in part, because culture systems fail to recapitulate physical aspects of the natural cellular environment. This work investigates the role of extra-cellular mechanical and chemical influences such as scaffold stiffness, hormone concentrations, media pH, and cell density on cell development and growth patterns. Early results indicate that tuning of biomechanical and biochemical cues leads to cell growth which deviates from typical culture morphologies and better resembles natural plant tissue structures. New analytical methods and measurement metrics were developed to monitor cell enlargement, elongation, and differentiation in response to altered culture conditions. Through factorial design of experiments, optimal conditions for maintenance of long-term cell viability or elevated differentiation rates have been identified. Maps of cell response over a range of extracellular conditions allows for tuning of plant cell models to allow for the exhibition of de-sired physiological compositions. With the aid of these new data maps, plant tissues which are traditionally difficult to access or study in real-time can be better replicated for study in the laboratory setting.

Conformable Ultrasound Patch with Energy-efficient In-memory Computation for Bladder Volume Monitoring

Continuous monitoring of urinary bladder volume aids management of common conditions such as post-oper-ative urinary retention. Urinary retention is prevented by catheterization, an invasive procedure that greatly increases urinary tract infection. Ultrasound imaging has been used to estimate bladder volume as it is porta-ble, non-ionizing, and low-cost. Despite this, ultrasound technology faces fundamental challenges limiting its usability for next generation wearable technologies. (1) Current ultrasound probes cannot cover curved hu-man body parts or perform whole-organ imaging with high spatiotemporal resolution. (2) Current systems require skilled manual scanning with attendant mea-surement variability. (3) Current systems are insuffi-ciently energy-efficient to permit ubiquitous wearable device deployment.We are developing an energy-efficient body con-tour conformal ultrasound patch capable of real-time bladder volume monitoring. This system will incorpo-rate (1) deep neural network- (DNN) based segmenta-tion algorithms to generate spatiotemporally accurate bladder volume estimates and (2) energy-efficient stat-ic random-access memory (SRAM) with in-memory dot-product computation for low-power segmentation network implementation. We aim to develop platform technology embodiments deployable across a wide range of health-monitoring wearable device applica-tions requiring accurate, real-time, and autonomous tissue monitoring. We are training a low-precision (pruned and quan-tized weights) DNN for accurate bladder segmentation. DNNs are computation-intensive and require large amounts of storage due to high dimensionality data structures with millions of model parameters. This shifts the design emphasis towards data movement between memory and compute blocks. Matrix vector multiplications (MVM) are a dominant kernel in DNNs, and In-Memory computation can use the structural alignment of a 2D SRAM array and the data flow in ma-trix vector multiplications to reduce energy consump-tion and increase system throughput.

Arterial Blood Pressure Estimation Using Ultrasound Technology

Hypertension, or high blood pressure (BP), is a major risk factor for cardiovascular diseases. Doctors prefer monitoring BP waveforms of ICU patients as the mor-phology and absolute values of these signals help to assert the cardiovascular fitness of the patient. At pres-ent, doctors use invasive radial catheters to record these waveforms. Invasive transducers are inconvenient and can be painful and risky to the patient. Hence, we are developing an algorithm to estimate BP waveforms us-ing non-invasive ultrasound measurements at the bra-chial and carotid arteries. Ultrasound probes are a commonly used sensing modality for non-invasive cardiovascular imaging. For instance, doctors use a linear array transducer to image superficial blood vessels like the brachial or the carot-id artery. These multifunctional probes can record the lumen area waveform of these arteries and measure the velocity of the blood. In this project, we will record the aforementioned signals with a commercial ultra-sound probe and a custom-designed probe (see Figure 1) and use the physics of the arterial pulse wave trans-mission to estimate the shape and absolute values of the pressure waveform. The pressure waves originat-ing from the heart traverse the arterial wall with a velocity commonly referred to as pulse wave velocity (PWV). According to the physics of the arterial pulse wave transmission, we can calculate PWV from the ul-trasound signals. Compliance and pulse pressure of the pressure waves in the artery may be obtained using the Bramwell-Hill equation. Finally, absolute values of the pressure will be derived using a combination of a trans-mission line model of the artery and machine learning algorithms.

Superficial Blood Vessel Lumen Pressure Measurement with Force-coupled Ultrasound Image Segmentation and Finite-element Modeling

Blood pressures of arteries and veins are valuable indicators of cardiovascular health. Systolic and diastolic arterial pressure can be obtained in vivo noninvasively and accurately with a blood pressure cuff on one of the limbs. However, no noninvasive means to evaluate lumen pressure in veins exists other than visual assessment of the internal jugular vein, which often requires ample skill to execute despite its inaccuracy. What is more, venous pressure is constantly evaluated in the context of congestive heart failure in determining diuretic treatment. Heart failure cardiologists face the difficult decision between ordering an invasive test with plenty of inherent risk or noninvasively but inaccurately evaluating jugular venous pressure.Our group has developed a force-coupled ultrasound probe attachment, providing the ability to measure the force applied by an ultrasound probe for each image obtained. We can segment a superficial blood vessel of fewer than 5 cm of depth and without bone between it and the skin to track its deformation in response to external force applied by the ultrasound probe. Furthermore, we can create a forward finite-element model of a blood vessel cross section to predict vessel deformation in response to the known force applied. We can nest this forward model into a combined iterative inverse model with the observed force and vessel deformation to optimize over the lumen pressure by comparing predicted deformation to observed deformation. This method has the potential to noninvasively and accurately derive sampled arterial and venous pressure waves.

Development of Fully-automated and Field-deployable Sample Preparation Platform Using a Spiral Inertial Microfluidic Device

Sample separation is a key step in sample preparation to isolate target analytes from interferents in the biofluid sample for a particular analysis. As the current standard, centrifugation and affinity-based (labeling) methods or their combination are used for sample separation. Although those methods themselves are straightforward, they are labor-, energy-, and time-intensive and require large volumes of sample (on the order of 1 mL) and well-trained operators; expensive labeling reagents should be employed for the labeling methods. More importantly, the centrifugation process and cell labeling can cause damage of sample (e.g., ex vivo cell activation), which leads the challenges in assessing the host’s immune response or leukocyte functions correctly.To overcome these limitations, we propose a new type of spiral cell-sorting process using a multi-dimensional double spiral (MDDS) device, where particles are concentrated through a first smaller-dimensional spiral channel and subsequently separated through a second, larger-dimensional spiral channel (Figure 1a). Because of the initial focusing in the first spiral channel, particle dispersion can be significantly decreased, and smaller particles can be effectively extracted into the outer-wall side of the channel, resulting in increase of separation resolution (Figure 1b). To obtain a more purified and concentrated output, we also developed a new recirculation platform based on a check-valve that allows only one-way flow. In the platform, the separated output can be extracted back into the input syringe by the withdrawal motion of a syringe pump and processed again through the MDDS device by the infusion motion of a syringe pump, resulting in higher purity and concentration (Figure 1c). The developed platform can be operated in a fully-automated or even hand-powered manner with a great separation performance. Therefore, we expect that the developed platform could provide an innovative sample preparation solution for point-of-care analyses and diagnostics.

Nanofluidic Monitoring of the Quality of Protein Drugs During Biomanufacturing

Biologics are drugs produced from any biological source (e.g., mammalian cells, bacteria, yeast). Biologics include recombinant therapeutic proteins, vaccines, monoclonal antibodies, and other living cells. Because of their high ef-fectiveness and reduced complications, biologics can be used to treat many complex conditions, such as cancers and autoimmune disorders, and are transforming mod-ern medicine. Biologics are typically produced through a biomanufacturing process including large-scale bioreac-tor cultivation, purification, and quality checks. Quality checking is critical during this process; quality deviation can significantly compromise drug efficacy and safety.To ensure the quality of biologics, quality control laboratories at manufacturing sites routinely use con-ventional analytical technologies, such as liquid chro-matography and mass spectroscopy. Most analytical technologies require (1) labor intensive manual sample preparation, (2) large sample volume, and (3) technical expertise from scientists/technicians. In addition, these techniques have limited data throughput due to offline and discontinuous analysis. To overcome these limita-tions, micro/nanofluidics can be used to monitor critical quality attributes during biomanufacturing. With the ad-vantages of easy automation, continuous-flow, and small sample volume, micro/nanofluidic technologies can pro-duce a large amount of quality data for improved quality control and understanding of biologics. Previously, our group introduced a new nanofluidic device for contin-uous-flow multi-parameter quality analytics. Recently, this nanofluidic device was integrated with continuous biomanufacturing to monitor protein size in a fully auto-mated, continuous, online manner (Figure 1).We are expanding the capability of our nanofluidic device to monitor other critical quality attributes such as binding affinity and glycosylation of monoclonal an-tibodies during biomanufacturing. With optimization of the monitoring system, we aim to achieve “real-time” and “multi-modal” quality analytics. This nanofluidic an-alytics is expected to improve the safety and efficiency of biomanufacturing in the future.

Measuring Eye Movement Features Using Mobile Devices to Track Neurodegenerative Diseases

Current clinical assessment of neurodegenerative dis-eases (e.g., Alzheimer’s disease) requires trained special-ists, is mostly qualitative and is commonly done only intermittently. Therefore, these assessments are affect-ed by an individual physician’s clinical acumen and by a host of confounding factors, such a patient’s level of attention. Quantitative, objective and more frequent measurements are needed to mitigate the influence of these factors. A promising candidate for a quantitative and ac-cessible diseases progression monitor is eye movement. In the clinical literature, an eye movement is often mea-sured through a pro/anti-saccade task, where a subject is asked to look towards/away from a visual stimulus. Two features are observed to be significantly different between healthy subjects and patients: reaction time (time difference between a stimulus presentation and the initiation of the corresponding eye movement) and error rate (the proportion of eye movements towards the wrong direction). However, these features are com-monly measured with high-speed, IR-illuminated cam-eras, which limits the accessibility. Our goal is to devel-op a novel system that measures these features outside of the clinical environment.Previously, we showed we can accurately measure reaction time using iPhone cameras, by combining a deep convolutional neural network (CNN) for gaze es-timation with a model-based approach for saccade on-set determination. We showed that there is significant intra- and inter-subject variability in reaction time, which highlights the importance of individualized tracking. We have since developed an app to facilitate data collection and include error rate measurement. With a large amount of data, we can validate the effect of age on these features and identify confounding fac-tors, leading to a better understanding of relationship between eye movement features and disease progres-sion. By facilitating repeat measurements, our frame-work opens the possibility of quantifying patient state on a finer timescale in a broader population than pre-viously possible.

Noninvasive Monitoring of Single-cell Mechanics by Acoustic Scattering

The monitoring of mechanics in a single cell throughout the cell cycle has been hampered by the invasiveness of mechanical measurements. Here we quantify mechanical properties via acoustic scattering of waves from a cell inside a fluid-filled vibrating cantilever with a temporal resolution of < 1 min. Through simulations, experiments with hydrogels, and the use of chemically perturbed cells, we show that our readout, the size-normalized acoustic scattering (SNACS), measures stiffness. To demonstrate the noninvasiveness of SNACS over successive cell cycles, we used measurements that resulted in deformations of < 15 nm. The cells maintained constant SNACS throughout interphase but showed dynamic changes during mitosis. Our work provides a basis for understanding how growing cells maintain mechanical integrity and demonstrates that acoustic scattering can be used to noninvasively probe subtle and transient dynamics.

Modular Optoelectronic System for Wireless, Programmable Neuromodulation

Optogenetics is a technique that uses visible light stimulation to activate or inhibit neurons genetically modified to express light-sensitive proteins from the microbial rhodopsin family. It offers light-sensitive opsin proteins to the region of interest and provide advantages such as cell type specificity, millisecond temporal precision, and rapid reversibility. Furthermore, compared to the electrical stimulation, it causes negligible electrical perturbation to the environment, which enables simultaneous electrical recording while stimulating a region of interest. The stimulation of the targeted neurons can be achieved using lasers, light-emitting diode (LED)-coupled optical fibers, or wireless μLEDs. This work presents a modular, light-weight head-borne neuromodulation platform that achieves low-power wireless neuromodulation and allows real-time programmability of the stimulation parameters such as the frequency, duty cycle, and intensity. This platform is composed of two parts: the main device and the optional intensity module (Figure 1). The main device is functional independently; however, the intensity control module can be introduced on demand (Figure 2). The stimulation is achieved through the use of LEDs directly integrated in the custom-drawn fiber-based probes. Our platform can control up to 4 devices simultaneously, and each device can control multiple LEDs in a given subject. Our hardware uses off-the-shelf components and has a plug-and-play structure, which allows for fast turnover time and eliminates the need for complex surgeries. The rechargeable, battery-powered wireless platform uses Bluetooth Low Energy (BLE) and is capable of providing stable power and communication regardless of orientation. This platform presents a potential advantage over the battery-free, fully implantable systems that rely on wireless power transfer, which is typically direction-dependent, requires sophisticated implantation surgeries, and demands complex experimental apparatuses. Although the battery life is limited to several hours, this is sufficient to complete the majority of behavioral neuroscience experiments. Our platform consumes 0.5 mW and has a battery life of 12 hours.

Nanoparticle for Drug Delivery Using TERCOM

Targeted drug delivery has been an area of active investigation for many decades. Some approaches target cell-borne receptors; others use external stimuli such as heat or radio waves to drive spatially-localized release. In this work, particles estimate their own location within the body by correlating their sensed fluid environment (e.g. temp., press., salinity, sugar, pH, etc.) against an embodied map and release on the basis of this estimate; the approach is related to terrain contour matching (TERCOM), a technique used in air navigation. Preliminarily explored particle concepts have included liposomes and proteins (bottom-up fab) and thin films (top-down fab). As envisioned, a mixture of drug-laden and empty permeable vessels, each with a different environmental response, interconnect through a capacitive volume separated from the surroundings by a permeable film. In another envisioned approach, the monomer sequence of polypeptides or other polymers is selected to provide the greatest activity in preferred capillaries, the sequence of experienced environments affecting the conformation. In both, using item response theory, the mixture's or particle's composition is tailored to deliver a larger dose or greater activity to preferred capillaries. A chip concept that implements a microarray with a half-toned chemical library and material data drawn from conventional surgical analogs has also been considered as a means of screening candidate compositions for the desired spatial sensitivity. Overall, the work builds on a past effort by the PI and his group to develop nanoparticles which record their experience in DNA. Current efforts focus on the theory of estimating location within the body from vectors of sensed variables and on the development of concepts for particles and chips. The ultimate objective is to demonstrate a nanoparticle that implements TERCOM- or DSMAC-like navigation in the body and a chip that can evaluate its selectivity. The concept is outlined in Figure 1.

Multiplexed Graphene Sensors for Detection of Ions in Electrolyte

Nowadays wearable electronics such as sweat sensors targeting key biomarkers have been heavily investigated. However, these electronics typically contain only one sensor for each type of analyte and the performance is evaluated and optimized separately. When applied to real-world application with complex environment, the reproducibility and the reliability of such device is questionable. Here we present a platform technology for multiplexed, large-area sensing array for more reliable measurement. Graphene is used as signal transducer because of its high surface-to-volume ratio and excellent electrical properties. By utilizing a material jetting 3D printer, we can deposit different types of functionalization on specific regions of the array to achieve multiplexed sensing. Here we demonstrate a fully integrated sensing array with three types of ion-selective membranes (ISMs) to achieve detection of sodium, potassium and calcium(see Figure 1). Each types of functionalization covers over 70 working devices and in total more than 200 devices are functional in one array. The sensor array is first tested with various concentration of solutions contain pure K, Na or Ca ions. All three types of sensors show excellent Nernstian sensitivity towards their target ion and moderate level of sensitivity towards other two types of ions. Using Principle Component Analysis, we can cluster and identify the type of ion as shown in Figure 2. The sensor array is also tested with a set of mixture solutions that are prepared by fixing the concentration of interfering ions while varying concentration of a specific type of ions. Similar clusters are observed indicating the sensor array’s ability for identifying which type of ion concentration is changing within a complex mixture solution. This work demonstrates the possibility of achieving highly reliable multiplexed sensing array that can be deployed in complex environments. By collecting data from a statistically significant sample size, we would be able to apply more sophisticated statistical methods or machine learning models to further associate complex mixtures for real-world applications.

Analytical and Numerical Modeling of Microphones for Fully Implantable Assistive Hearing Devices

Fully implantable cochlear implants (CIs) could take advantage of the natural enhancement of pressure and binaural cues afforded by the outer ear. They would also allow for hearing 24/7 and mitigate the limitations and inconvenience of an external device. To enable a fully implantable CI, we are developing two piezoelectric implantable microphones to be embedded inside a cochlear implant electrode array or the middle ear cavity as shown in Figure 1. The first type senses pressure along the CI array and has a form factor similar to conventional CI arrays. It will not sense at the base of the cochlea where unwanted noise can originate and scarring and bony growth occurs. The latter sits adjacent to the eardrum and senses any umbo displacement. We have built prototypes of such piezoelectric microphones made with polyvinylidene fluoride (PVDF), a piezoelectric film. We have inserted these prototype microphones inside the scala tympani through the round window and in the middle ear cavity. Preliminary tests show promise for achieving good sensitivity, low noise, and wide bandwidth with this structure. Our approach combines analytical models for design guidance, numerical models for design verification, and bench-test experiments for validation. Analytical modeling is driven by the differential equations of solid mechanics and piezoelectricity. Numerical modeling is enabled by the COMSOL Multiphysics software where we have created simulations of the piezoelectric sensor and use ear mechanics measurements to choose the appropriate boundary conditions.Progress has been made to advance both prototypes into a practical implantable microphone. We have created a platform for system optimization and started the iterative design process. In the near future we will begin sensing circuit design which will modify the system’s overall sensitivity. We will verify numerical model parameters, conduct bench testing imitating cochlear conditions, develop surgical implantation methods, and generate device manufacturing processes

Spontaneous Relaxation towards Dislocation-free Heteroepitaxy

Epitaxy laid a foundation for conventional electronic systems as it produces high-quality single crystalline materials. To grow various materials through epitaxy, heteroepitaxy is required as a limited set of available substrates exists. However, a lattice-mismatched issue in heteroepitaxy leads to degradation in the materials’ quality by introducing dislocations to release accumulated strain energy due to the lattice-mismatch. Here, we report a unique approach to release the accumulated strain energy in heteroepitaxy by coating graphene on substrates. As graphene provides a slippery nature on substrates, deposited particles are easily moved around to have energetically favorable atomic lattice. Thus, inserted graphene allows us to grow strain-free single-crystalline materials, a process named spontaneous relaxation. We expect this spontaneous relaxation will be useful to realize the monolithic integration of various lattice-mismatched systems. Figure 1 shows a mechanism of strain relaxation in conventional epitaxy. GaP was grown on GaAs substrate that has 3.7 % misfit strain. Because of the lattice-mismatch, a substantial number of dislocations was introduced to release the accumulated strain energy above a critical strain level. This energy is known as a source to degrade the material’s properties. On the other hand, Figure 2 shows a scenario of strain relaxation through spontaneous relaxation. GaP was grown on a graphene-coated GaAs substrate. As graphene has lattice transparency and provides a slippery surface on top of the substrates, strain-released GaP was obtained. These results demonstrate the feasibility of another strain relaxation pathway on graphene-coated substrates, which will broaden the materials set available for heteroepitaxy.

Graphene-based Tunneling Nanoelectromechanical Switch

Nanoelectromechanical (NEM) switches are considered to be a promising complementary technology for conventional logic switches because of their zero static power consumption and potential for low-voltage operation. However, they can suffer from stiction caused by significant van der Waals forces acting on their nanoscale structures. Such stiction can easily lead to the permanent failure of a conventional NEM switch and generally prevents miniaturization, leading to a high actuation voltage. Therefore, for NEM switches to be competitive, it is necessary to develop a NEM switch with high switching reliability, low-voltage operation, and ultra-low power consumption. The fabrication of such a switch should also be scalable to enable its popularization within the digital integrated-circuit industry. This work advances the development of a novel squeezable NEM switch, called a squitch. To fabricate the squitch as shown in Figure 1, a pair of nanometer-smooth gold electrodes are fabricated via electron beam lithography and transferred to a glass substrate. A monolayer of polyethylene glycol (PEG)-thiol is then deposited on electrodes via a self-assembly process. Finally, a single layer of graphene is patterned and transferred onto the bottom part of the squitch. Varying the voltage applied between the gold electrodes can electrostatically modulate the thickness of the compressible PEG-thiol monolayer, enabling an exponential change of the current tunneling through it. At this point, as shown in Figure 2, an on/off current ratio of 100:1 with sub-1 V actuation has been achieved. The devices can also survive 10 to 100 cycles of operations, showing observable durability. The fabrication yield is up to ~ 40% and can be further improved by modifying the methods of transferring graphene and exploring new molecules with the appropriate mechanical properties. In the future, we plan to design a squitch based completely on graphene while keeping the current structure to avoid the potential effect of electromigration.

Low-temperature Ferroelectric Hf0.5Zr0.5O2 for InGaAs-channel Negative Capacitance Field-effect-transistors

Negative capacitance (NC) MOSFETs by integrating ferroelectric (FE) hafnium zirconium oxide (HZO) film in the MOS gate stack have generated enormous interest due to its performance-boosting and CMOS process compatibility. Stable ferroelectricity in the HZO film is usually obtained after a rapid thermal annealing (RTA) step at 500℃. This is because film crystallization under the right conditions is crucial for the formation of the FE orthorhombic phase. However, in order to achieve NC InGaAs-channel MOSFETs, as is our goal, a low-temperature process is essential to preserve the integrity of the gate oxide/InGaAs channel interface. This is also needed for precise capacitance matching. In our work, we have focused our attention towards enabling a low thermal budget process for FE formation of HZO film.After optimization of the HZO atomic layer deposition (ALD) process, Metal – FE – Metal (MFM) capacitors were fabricated to characterize the FE properties, as shown in Figure 1. To provide higher tensile stress and promote the formation of the orthorhombic phase in the HZO film during RTA, 100 nm-thick TiN as electrode was introduced. Figure 2 shows the polarization – voltage characteristics of MFM capacitors annealed at 500℃ and 400℃. The result demonstrates that the HZO film attains FE properties with a 400℃ thermal process. This is also confirmed by the strong FE switching current peaks observed in Figure 3.We are in addition exploring the further decrease of process temperature of HZO crystallization through the introduction of a ZrO2 seed layer under the HZO film (Figures 2 and 3). This has been shown to boost orthorhombic phase formation. Going beyond, we have observed that HZO film deposited by plasma-enhanced ALD (PE-ALD) yields ferroelectric behavior with a 350℃ thermal process. Our research will continue by integrating the optimized gate stack with our established InGaAs MOSFET platform for developing InGaAs NCFETs.

Artificial Heterostructuring of Single-crystalline Complex-oxide Membranes

Epitaxial heterostructures are the backbone of many important electrical and photonic devices used today. Although many dissimilar crystals can be utilized, epitaxy is limited by the choice of substrates. In other words, the epitaxial film must be similar to the crystal structure of the host wafer. Such limitations impede the advancement of heterostructure engineering and prevent many novel physical phenomena from being discovered because they prevent epitaxial growth of dissimilar materials on a single substrate.To overcome this limitation, we have developed a method to easily remove the epitaxial layer and transfer it onto any arbitrary substrate by using graphene as a release platform in a method called remote epitaxy. By extending this method to complex-oxide material systems, we have, for the first time, artificially created a complex-oxide membrane heterostructure by stacking piezoelectric PMN-PT and magnetostrictive CoFe2O4 (CFO) and hybridizing their properties. Both membranes were released from the substrates and were manually stacked by hand, with the PMN-PT membrane having a thickness of 500 nm and CFO having a thickness of 300 nm. The multiferroic heterostructure was fabricated into a device that allowed measurement of the voltage generated across the PMN-PT membrane (Figure 1).The device was measured by applying a magnetic field across the entire heterostructure and measuring the resulting voltage generation across the PMN-PT membrane. In this device, the magnetic field strains the CFO membrane, and that strain is transferred to the PMN-PT, generating voltage (i.e., magnetoelectric coupling). We noticed that completely freestanding devices generated higher voltages by several factors than devices still clamped to the substrate (Figure 2). These results demonstrate the feasibility of creating novel heterostructures that have never been possible before using remote epitaxy and show the advantages of utilizing freestanding membranes as opposed to those still stuck on their substrates.

Morphological Stability of Nanometer-scale Single-crystal Metallic Interconnects

Continued IC scaling requires interconnects with cross-sectional dimensions in the <10nm range. At these dimensions the resistance of interconnects increases dramatically due to surface and grain boundary electron scattering. The reliability of interconnects with nanoscale dimensions is also expected to be compromised by reduced morphological stability. As a part of a collaborative program focused on ballistic conduction and morphological stability of single-crystal nanometer-scale interconnects, we are investigating the crystallographic dependence of the morphological stability of Ru wires.Thin single-crystal films agglomerate into small particles via capillary driven surface diffusion in a process known as solid-state "dewetting." With decreasing film thickness, the temperature at which dewetting occurs is well below the constituent materials melting temperature. However, previous work on single-crystal (FCC) Ni films has demonstrated that crystalline anisotropy gives rise to special crystallographic orientations along which single-crystal wires are kinetically stable (Figure 1). Interconnects composed of such wires should have decreased vulnerability to morphological instabilities during processing and circuit operation. These wires will have strongly faceted surfaces which are predicted to reduce electron scattering and decrease interconnect resistance. Ru is a candidate material for future interconnects, and exploratory work with single-crystal (0001) films suggests that wires oriented along directions will be particularly stable (Figure 2). Work on patterning and testing of such wires is currently underway. In addition to this experimental work, we are working toward accurate simulations of anisotropic solid-state dewetting. These simulations reproduce the dramatic effect that stable surfaces can have on wire stability and provide an opportunity to systematically probe the effects of individual material properties. Combining the results of these experiments and simulations with those of past work on Ni will provide insights that will enable optimization of interconnect structural and crystallographic factors for design of morphologically stable nanowires with cross-sectional dimensions significantly below 10nm.

Modern Microprocessor Built from Complementary Carbon Nanotube Transistors

Electronics is approaching a major paradigm shift because silicon transistor scaling no longer yields historical energy-efficiency benefits, spurring research towards beyond-silicon nano-technologies. In particular, carbon nanotube field-effect transistor (CNFET)-based digital circuits promise substantial energy-efficiency benefits, but the inability to perfectly control intrinsic nanoscale defects and variability in carbon nanotubes has precluded the realization of very-large-scale integrated systems. Here we overcome these challenges to demonstrate a beyond-silicon microprocessor built entirely from CNFETs: RV16X-NANO. This 16-bit micro-processor is based on the RISC-V instruction set, runs standard 32-bit instructions on 16-bit data and addresses, comprises more than 14,000 complementary metal–oxide–semiconductor CNFETs and is designed and fabricated using industry-standard design flows and processes. We propose a manufacturing methodology (MMC) for carbon nanotubes, a set of combined processing and design techniques for overcoming nanoscale imperfections at macroscopic scales across full wafer substrates. The key elements of MMC are:(1) RINSE (removal of incubated nanotubes through selective exfoliation). We propose a method of removing CNT aggregate defects through a selective mechanical exfoliation process. RINSE reduces CNT aggregate defect density by >250× without affecting non-aggregated CNTs or degrading CNFET performance.(2) MIXED (metal interface engineering crossed with electrostatic doping). Our combined CNT doping process leverages both metal contact work function engineering as well as electrostatic doping to realize a robust wafer-scale CNFET CMOS process. We experimentally yield entire dies with >10,000 CNFET CMOS digital logic gates (2-input ‘not-or’ gates with functional yield 14,400/14,400, comprising 57,600 total CNFETs), and present a wafer-scale CNFET CMOS uni-formity characterization across 150-mm wafers.(3) DREAM (designing resiliency against metallic CNTs). This technique overcomes the presence of metallic CNTs entirely through circuit design. DREAM relaxes the requirement on metallic CNT purity by about 10,000× (relaxed from a semiconducting CNT purity requirement of 99.999999% to 99.99%),

Nanostructured, Additively Manufactured, Miniature Ionic Liquid Ion Sources

Electrospraying is a high-electric field physical phenomenon that transforms electrically conductive liquids into fine, uniform streams of micro/nanoparticles; the applications of electrospraying include mass spectrometry, nanosatellite propulsion, combustors, and agile manufacturing. Unfortunately, electrospray emitters have very low throughput; consequently, several research groups have investigated, for about two decades, greatly increasing the electrospray source’s throughput via emitter multiplexing, using micro- and nanotechnology to attain lower startup voltage and denser emitter arrays. Although successful, the reported implementations harness cleanroom microfabrication, which has an associated high cost that is incompatible with many applications of electrospraying. In this project, we explore the use of additive manufacturing to create, at a very low cost, monolithic arrays of electrospray emitters capable of ion emission. We have succeeded at demonstrating the first additively manufactured ionic liquid electrospray sources in the literature; our devices produce per-emitter current comparable to that produced by silicon microfabricated counterparts, at a small fraction of their fabrication cost. The devices are diodes composed of an emitting electrode and an extractor electrode: the emitting electrode is a monolithic array of digital light projection (DLP)-printed solid, conical, polymeric needles covered by a conformal layer of hydrothermally grown zinc oxide (ZnO) nanowires as a wicking material (Figure 1), while the extractor electrode is a laser-cut SS 316L plate with an array of apertures that matches the pattern of the array of needles. Characterization of the devices in vacuum using the ionic liquid EMI-BF4 demonstrates bipolar, uniform array emission of solvated ions—in agreement with the literature on ionic liquid ion sources. Current research efforts focus on increasing the number of emitters per unit of area and on exploring other materials and designs for implementing the devices.

Soldiers’ Hearing Health Protection and Auditory Augmentation Using Electrostatic NEMS

Our work on acoustic nanomembrane electromechan-ical transducers (NEMS) that can safely fit and operate inside an ear is motivated by the desire to improve U.S. soldiers’ auditory health. From the time soldiers set foot on training grounds to their deployment in war zones, they are consistently exposed to deleterious noise from rapid gunshots, friendly fire, explosions, jet engines, and armored personnel carriers. Noise levels from these sources often exceed safe hearing thresh-olds and can inflict irreversible ear trauma and hear-ing loss. Existing hearing protection solutions that at-tempt to mitigate tactical noise are often insufficient and compromise communication, combatant response time, and response accuracy. Indeed, it is recognized that hearing loss resulting from military service is a massive financial and clinical burden, which needs a technical solution that can protect soldiers and assist veteran civilians.To simultaneously provide hearing protection, ef-fective tactical communication, and situational aware-ness, an in-the-ear acoustic system is needed, one that can operate at low power with distortion-free acoustic output over the entire human auditory range. Scalable versions of such systems do not yet exist, which moti-vates us to suggest that the design of our electrostatic NEMS enables them to operate as ultra-low-power mi-crospeakers. The low weight, the material composition, and the geometry of our NEMS membranes ensure linear and near-uniform acoustic output in the human auditory range. Hence, if integrated with earmolds, our NEMS could be used as high-fidelity microspeakers for speech enhancement in communication and noise at-tenuation. The same transducers can also act as acous-tic dosimeters and as ambient-facing microphones for sensing acoustic signals. This composite reversible device is designed to attenuate harmful sounds while enhancing verbal communication and maintaining acoustic transparency with the surroundings. Leverag-ing our nanomembrane transducer technology, we aim to reach superior size, weight, and power consumption specifications, with no compromise in performance.

Proton-based Resistive Memory for Analog Computing Applications

The size of state-of-the-art deep neural networks (DNNs) and consequent computation load have been increasing ever since the beginning of their outbreak. Since bigger and deeper neural networks trained with larger data sets generally provide better performance, this trend is expected to accelerate in the future. However, this poses as a significant problem for conventional digital architectures as the energy and time consumption for training DNNs have become unmanageable. The idea of using analog resistive crossbars to do parallel vector-matrix multiplications based on Ohm's and Kirchhoff's Laws have been known since 1960s. It was recently discovered that rank-one outer product-based updates can also be performed in parallel using pulse-coincidence for multiplication and incremental conductance change of devices for accumulation. These advancements have fueled the investigation of various non-volatile analog resistive memory technologies to realize fast, energy-efficient and versatile platforms for deep learning. In this work we implement a three-terminal electrochemical (i.e. battery-like) resistive memory device, employing the smallest ion, the proton. The conductance of the device is determined by the proton concentration intercalated inside the channel material. Electrical pulses applied to the gate enable protons to drift between the reservoir and the channel through the solid electrolyte as electrons move through the external circuit in the same direction (Fig. 1). When the gate is electrically open, proton movement through the electrolyte is forbidden since electrons cannot flow through the outside circuit, enabling non-volatile memory. We have demonstrated this concept on devices composed of a WO3 channel, Nafion electrolyte and Pd as hydrogen reservoir (Fig. 2) Devices have very low energy consumption (18 aJ/(μm2 x nS), nearly symmetric modulation characteristics and long cycling lifetime. Future work will involve optimizing the material stack, scaling and integration of these devices ultimately realizing a full-scale DNN training accelerator

High-throughput Vapor Transport Deposition of Organic-inorganic Perovskite Films

Vapor transport deposition (VTD) is a promising technique for enabling high-throughput large-area deposition of next-generation perovskite solar cells. VTD uses a carrier gas to transfer sublimed salts from source to substrate, where they react to form perovskite films. Unlike vapor thermal evaporation, VTD decouples the material deposition rate from material temperature, allowing for high-throughput deposition. VTD allows independent control of chamber pressure and deposition rate, parameters which can be tuned to change the film crystallization kinetics. Like thermal evaporation, VTD permits precise control of thickness and eliminates hazardous solvents from device fabrication, allowing facile growth of complex multi-layer device structures such as tandem solar cells. The high throughput deposition coupled with low vacuum operation reduces the capex requirement for VTD deposition tools and has led to commercialization of the technique for CdTe and organic semiconductor materials manufacturing.Through the use of a custom home-built VTD setup, we study perovskite solar cell active-layer film formation via co-evaporation of lead iodide and methylammonium iodide (MAI). We determined parameters and deposition conditions necessary to form high-quality methylammonium lead iodide films. We found that control of MAI degradation and its deposition rate during VTD is a critical challenge that must be overcome. Last, we developed numerical simulations of material diffusion and gas flow necessary to narrow the VTD design parameter space. We are assembling the next-generation VTD reactor to study the impact of critical parameters such as substrate temperature, carrier gas flow rate, chamber pressure, and deposition rate on film formation kinetics by examining metrics such as photoluminescence, x-ray diffraction, morphology, and device efficiency. We aim to demonstrate VTD to be a viable new deposition method for large-area high-throughput manufacturing of perovskite solar cells.

Imaging Moiré Periodicities at the 2D/3D Interface Using 4D STEM

Structure and defects at the interface between 2D materials and their 3D bulk adjuncts greatly influence nanoscale device properties, such as contact resistance, photo-response, and high-frequency performance. Knowledge of fundamental charge transfer at this interface is critical for the continued and rapid development of devices that utilize 2D materials. Recent advances in scanning transmission electron microscopy (STEM), such as aberration correction and 4D STEM, allow analysis of interface growth, structure, and ordering. In this work, we use 4D STEM to directly image hidden moiré periodicities arising from epitaxial growth of nanoislands on 2D materials in ultra-high vacuum. Epitaxial growth creates moiré patterns arising from rotation and lattice mismatch between the nanoisland and underlying 2D material substrate. We use 4D STEM to directly image these periodic superlattices, which are not visible in conventional TEM or STEM and often can result in strong electron correlations. DFT calculations show that this moiré is directly responsible for a periodic modulation of electronic structure in the 2D material. Our work illustrates the essential role of emerging microscopy techniques to unveil the mechanisms of moiré superlattices, and we explore the implications of these on physical properties at the 2D/3D interface, such as enhanced charge transfer and moiré-modulated local interactions.

Templated Solid-state Dewetting of Single-crystal Thin Films

Solid-state dewetting of single-crystal thin films leads to an ordered array of particles that align along a few specific crystallographic orientations due to crystalline anisotropy. When single-crystal thin films are pre-patterned and then subjected to dewetting, which is known as templated dewetting, a regular array of complex features can be fabricated. The features that result from templated dewetting are affected by various instabilities that develop at the retracting edges of pre-patterns and the characteristics they produce. One instability that retracting edges can develop is pinch-off (see Figure 1a), which leads a wire parallel to the retracting edge; this process can occur repeatedly to form multiple wires . Alternatively, retracting edges can be subject to fingering instability (see Figure 1b), which leads to an array of wires aligned along the finger propagation direction. Understanding and controlling whether pinch-off or fingering occurs is important for controlled pattern formation. In the past year we have demonstrated that the initial roughness of a film edge determines whether pinch-off or fingering occurs, with rough edges leading to fingering (Figure 1). To further understand this phenomenon and to control it, we patterned large rectangular patches, with edges having controlled patterned roughness to template the fingering instability (Figure 2a). The edges of the patches were also aligned along various in-plane crystallographic orientations to study the effects of crystalline anisotropy on the templated fingering instability. We have found that templating of edge roughness can cause a fingering instability, with a very narrow distribution of the width and period of the fingers and wire, and that the wavelength of patterned roughness can control the steady-state finger period (Figure 2b). We further found that t the period of fingers affects the steady-state finger propagation velocity, so we developed a kinetic model that predicts steady-state finger propagation velocity as a function of the finger period. Strong effects of crystalline anisotropy on the templated fingering instability were observed. We found that edges that were aligned along a kinetically stable orientation resisted development of a fingering instability, even with the templating, and the patterned roughness disappeared as they retracted and became straight. Edges with orientations other than a kinetically stable orientation all developed fingering instabilities, but the finger propagation orientation was affected by the initial edge orientation; as a result, the steady-state finger period and propagation velocity were also affected. Furthermore, we studied effects of initial film thickness on the templated fingering instability using the same range of wavelengths of patterned roughness and the same range of in-plane orientations of the edge. During this study we found that the steady-state finger propagation velocity increases as film thickness decreases and that width of the wires that form due to propagation of the fingers decreases with film thickness, while the wavelength of patterned roughness still controls the finger period. Through these studies, we are developing techniques through which templated dewetting can be used as a patterning method.

Nucleation and Growth of Metal Thin Films and Nanocrystals on Two-dimensional Materials

The interface between metals and 2D materials (2DMs) influences device properties such as contact resistance, photoresponse, and high-frequency performance. In this project, we study the nucleation and growth of a variety of metals, including Ag, Au, Ti, Cr and Nb, on 2DMs (graphene, hexagonal boron nitride (hBN), WSe2, MoS2). We use transmission electron microscopy (TEM) to provide direct insight into crystal size, shape and orientation, epitaxy, and diffusivity. Besides the basic parameters that affect growth mode and epitaxy such as diffusivity, binding, and cohesive energies, we also explore the effects of 2DM thickness, temperature during deposition, and substrate (SiO2, hBN, or suspended). Combining the knowledge of deposition conditions, templating, and nucleation control greatly enhances routes towards tailored interface design for emerging 2DM device applications.Temperature during deposition greatly affects the diffusivity of metal atoms on the 2D surface. As expected from crystal growth models, temperature determines whether the crystal morphology is dendritic or compact and faceted on 2DMs (Figure 1). The effect of the substrate on the epitaxy and crystal morphology is relatively unexplored, and we find suspended 2DMs exhibit the largest epitaxial alignment (Figure 2). This is seen even for relative thick 2DMs, suggesting that substrate effects such as surface charges play little role in the crystal growth. Rather, 2DM roughness may be a determining parameter, which is decidedly lower for suspended 2DMs. In suspended layers, we also find that diffusion distance depends on 2DM thickness, with longest diffusion distances (>2 μm) on suspended Gr >8 monolayers thick. This project aims to contribute to the emerging field of 2D material devices through atomic scale characterization of metal nanocrystal growth on 2DMs, facilitating the design of contacts, heterostructures, and coupled materials for future 2DM dimensional devices.

An Energy-efficient Configurable Accelerator for Post-quantum Lattice-based Cryptography

Public key cryptography protocols, such as RSA and elliptic curve cryptography, will be rendered insecure by Shor’s algorithm when large-scale quantum computers are built. Cryptographers are working on quantum-resistant algorithms, and lattice-based cryptography has emerged as a prime candidate. However, the high computational complexity of these algorithms makes it challenging to implement lattice-based protocols on low-power embedded devices. To address this challenge, we present an energy-efficient lattice cryptography processor with configurable parameters. Efficient sampling, with a SHA-3-based PRNG, provides two orders-of-magnitude energy savings; a single-port RAM-based number theoretic transform memory architecture is proposed, which provides 124k-gate area savings, while a low-power modular arithmetic unit accelerates polynomial computations. This is the first ASIC implementation to demonstrate multiple lattice-based protocols proposed for post-quantum standardi-zation by NIST.Figure 1 shows the architecture of our lattice cryptography processor along with the chip micrograph. Our test chip was fabricated in TSMC 40-nm low-power CMOS process and supports voltage scaling from 1.1V down to 0.68V. The cryptographic core occupies 0.28 mm2 area consisting of 106k logic gates and 40.25 KB SRAM. It can be programmed with custom instructions for polynomial arithmetic and sampling and it coupled with a low-power RISC-V micro-processor to demonstrate NIST Round 2 lat-tice-based key encapsulation and digital signature protocols Frodo, NewHope, qTESLA, CRYSTALS-Kyber and CRYSTALS-Dilithium, achieving up to an order-of-magnitude improvement in performance and energy-efficiency compared to state-of-the-art hardware implementations. All key building blocks are constant-time and secure against timing and simple power analysis side-channel attacks. The cryptographic core can also be programmed to implement masking-based differential power analysis side-channel countermeasures, with additional computation cost, with no change to the hardware.

Conformable Ultrasound Patch with Energy-efficient In-memory Computation for Bladder Volume Monitoring

Continuous monitoring of urinary bladder volume aids management of common conditions such as post-oper-ative urinary retention. Urinary retention is prevented by catheterization, an invasive procedure that greatly increases urinary tract infection. Ultrasound imaging has been used to estimate bladder volume as it is porta-ble, non-ionizing, and low-cost. Despite this, ultrasound technology faces fundamental challenges limiting its usability for next generation wearable technologies. (1) Current ultrasound probes cannot cover curved hu-man body parts or perform whole-organ imaging with high spatiotemporal resolution. (2) Current systems require skilled manual scanning with attendant mea-surement variability. (3) Current systems are insuffi-ciently energy-efficient to permit ubiquitous wearable device deployment. We are developing an energy-efficient body con-tour conformal ultrasound patch capable of real-time bladder volume monitoring. This system will incorpo-rate (1) deep neural network (DNN) based segmenta-tion algorithms to generate spatiotemporally accurate bladder volume estimates and (2) energy-efficient stat-ic random-access memory (SRAM) with in-memory dot-product computation for low-power segmentation network implementation. We aim to develop platform technology embodiments deployable across a wide range of health-monitoring wearable device applica-tions requiring accurate, real-time, and autonomous tissue monitoring. We are training a low-precision (pruned and quan-tized weights) DNN for accurate bladder segmentation. DNNs are computation-intensive and require large amounts of storage due to high dimensionality data structures with millions of model parameters. This shifts the design emphasis towards data movement between memory and compute blocks. Matrix vector multiplications (MVM) are a dominant kernel in DNNs, and In-Memory computation can use the structural alignment of a 2D SRAM array and the data flow in ma-trix vector multiplications to reduce energy consump-tion and increase system throughput.

Bandwidth Scalable Current Sensing with Integrated Fluxgate Magnetometers

Contactless current sensing finds use in many industrial applications including power line monitoring, motor control, and electric vehicle battery management, as it provides inherent galvanic isolation over direct shunt-sensing. Magnetometers indirectly sense current through a wire by measuring the magnetic fields around it. For stray magnetic field rejection, magnetic sensors need to be placed in the air gap of a magnetic core around each wire. This solution is costly, bulky, and inconvenient to install. [1] proposes a plug-in solution with an array of integrated fluxgate (IFG) magnetometers for contactless current sensing in industrial internet of things applications. IFG offers a better alternative than Hall sensors in terms of dynamic range (~10^5), sensitivity (200 V/T), linearity (0.1%), and low temperature drift. IFG sensors work by driving magnetic cores in and out of saturation and sensing the resulting voltage difference. They achieve high linearity by balancing external magnetic fields within the core using compensation current, which can be quite power hungry, requiring up to 1W power for a three-phase measurement. Previous IFG sensors are designed for continuous operation at high sampling rates and cannot be duty cycled efficiently due to the long convergence time needed per measurement. The primary goal of this work is to reduce the energy needs of IFG sensors so they can be used in an array in energy constrained environments. Secondary goals are to increase the bandwidth to >100 kHz for fault detection and increase the measurement range to +/- 60 A at 0.5 cm away from the wire for a compact solution. We achieve these goals through a mixed signal front-end design to enable energy-efficient duty cycling in a bandwidth scalable fluxgate magnetic-to-digital converter. This work achieves higher measurement range, > 100 kHz bandwidth, and considerable energy savings with duty cycling from >100 kHz bandwidths for machine health monitoring to <1 kHz for power quality management.

SynCells - Electronic Microparticles for Sensing Applications

Autonomous electronic systems smaller than the diam-eter of a human hair (<100 µm) presents a great oppor-tunity for sensing applications because they allow us to interact with the environment at a much smaller scale. These microsystems could be used for example to de-tect chemicals in very confined spaces like the human body or microfluidic channels. Alternatively, they are small enough to be sprayed on surfaces to form distrib-uted sensor networks or even be incorporated into fi-bers to make smart clothing. However, fabricating and designing such microsystems is difficult due to integra-tion challenges and a limited power budget.In this work, we present a 60x60x2 µm3 electronic platform, called Synthetic Cell or SynCell, that over-comes these issues by leveraging the unique integra-tion capabilities of 2D material on an SU-8 substrate and the use of functional materials to reduce power consumption. We integrated several components on this platform including molybdenum disulfide-based transistors and chemical sensors, analog timers based on eroding germanium films, and magnetic iron pads (see Figure 1). These building blocks represent a broad set of capabilities and enable functions like computa-tion, sensing, time tracking and remote actuation, re-spectively. Over the past years, we have optimized the SynCell fabrication and lift-off process and recently demonstrated a yield close to a hundred percent of ful-ly working SynCells. To show the potential of SynCells in confined spaces, we magnetically positioned several SynCells in a microfluidic channel to detect putrescine in a proof-of-concept experiment, see Figure 2. After we extracted them from the channel, we successfully read out the timer and sensor signal, the latter of which was am-plified by an onboard transistor circuit. In the future, SynCells may be useful in a wide variety of fields, from clinical research to printable/sprayable sensor coatings.

Wideband Sub-THz Components for Ultra-efficient Meter-class Interconnect

With the growing interest in millimeter wave and terahertz (THz) electronics, there has been an associated interest in the various components that are required to realize these systems. In one such application, guided and modulated sub-THz (approximately 220-330 GHz) waves are used to transport high-rate data over backplane-scale distances. Such a scheme is attractive for a number of reasons, including broad available fractional bandwidth, compact system size (driven by smaller wavelengths compared to lower-frequency operations), relative robustness to misalignment during assembly versus optical systems, and lower transmission losses than those exhibited by copper lines for high-speed data transmission. One of the challenges associated with the development of the above link system is the realization of compact, low-loss channelizers over the wide operating bandwidth afforded by these types of lines. While waveguide-based channelizers have been demonstrated at lower bands and waveguide components are available at higher operating frequencies, they are relatively large and require more expensive packaging and interface schemes. This type of scheme would require a planar integration approach to be economically feasible.We have demonstrated the best-in-class channel-ization performance on a new Intel organic packaging process over 40% fractional bandwidth and occupying up to 200x less area than competing approaches. The de-sign makes use of a very fast circuit-EM co-design tech-nique to overcomes computational hurdles associated with large-scale, full-wave dimensional optimization to rapidly optimize the design. The work utilizes a ridged-SIW resonator design, enabled by the Intel packaging technology, provides superior performance, enables the wide operating band, and reduces the device size by 40%. This design methodology, the selected channel-izer topology, and the packaging technology provide a feasible path toward ubiquitous, highly-integrated, and low-cost THz-communication systems-in-package at the board/back-plane level.

A CMOS-based Dense 240-GHz Scalable Heterodyne Receiving Array with Globally-accessible Phase-locked Local Oscillation Signals

Driven by the thrust of sensor miniaturization, there is a growing interest in forming steerable beams on the chip scale, which calls for pushing the operation frequency of beam-steering systems towards the terahertz (THz) range. However, this requires disruptive changes to traditional THz receiver architectures, e.g. square-law direct detector arrays (low sensitivity and no phase information preserved) and small heterodyne mixer arrays (bulky and not scalable). The major issue that prevents the latter case from being scalable is the need of large-scale power distribution network for local oscillation signals (LO), which can be very lossy at such high frequency. Here, we report a highly scalable 240-GHz 4×8 heterodyne array achieved by replacing the LO power distributor with a network that couples LOs generated locally at each unit. Now the major challenge for this specific architecture is that each unit should fit into a tight λ/2×λ/2 area to suppress side lobes from beam forming - it makes integrating mixer, local oscillator, and antenna into a unit difficult. Our design addresses this challenge well: the highly compact units ultimately enable the integration of two interleaved 4×4 phase-locked sub-arrays in 1.2-mm2.The architecture of the entire array is shown in Figure 1(a). Its core component is a self-oscillating harmonic mixer (SOHM), which can simultaneously (1) generate high-power LO signal and (2) down-mix the radio frequency (RF) signal. Since coupling is designed to be global, LOs generated in all units are all locked to an external reference signal by phase-locking two units only. The die (Figure 1(b)) photo shows the placement of the array and the PLL. The measured sensitivity (required incident RF power to achieve SNR=1 at baseband) over 1-kHz detection bandwidth is 58fW, which is more than 4000× improvement over state-of-the-art large-scale square-law detector arrays. Figure 2 shows that this work has pushed the boundary of THz receiver arrays in terms of scale and sensitivity.

Method and Countermeasure for SAR ADC Power Side-channel Attack

Analog-to-digital converters (ADCs) are essential building blocks of most electronic systems as they convert analog signals into digital bits. Since the demand for digital signal processing keeps growing, researchers have focused on enhancing the ADC performance to keep up with the demand of digital processors. However, recent studies have raised a hardware security concern regarding the ADC-related security loophole, warning that private signal information can be leaked through power supply current waveforms of an ADC.Figure 1 illustrates an example ADC power side-channel attack (PSA) scenario in sensing hardware that is acquiring a private signal (e.g., healthcare, smart home devices, industrial monitoring). By employing an encryption engine equipped with a PSA-countermeasure, an attacker is prevented from performing eavesdropping and extracting the secret key of the encryption algorithm by tapping into the power supply of the encryption engine. Also, a tamper-proof package can be used to prevent an attacker from directly tapping into the sensor output signal. However, for practical reasons such as a provision for battery replacement and a limitation on physical dimensions, the tamper-proof package may not extend to the ADC power supplies, allowing an attacker to tap into the power supply waveforms of the ADC. Due to the strong correlation between the ADC power supply current waveforms and the ADC digital outputs, an at-tacker can perform an ADC PSA to obtain the private signal data of the sensing hardware.This work explores both aspects of ADC PSA: method and countermeasure with an emphasis on SAR ADCs. In this work, neural networks are used as a mapping function that converts a SAR ADC power supply current waveform into the corresponding ADC digital output. To protect a SAR ADC from the proposed PSA method, switched-capacitor circuits called current equalizers are used to decorrelate the on-chip ADC activity and the ADC power supply current waveforms. Figure 2 shows the experimental PSA results on a custom-designed SAR ADC (Figure 2c) that demonstrate the effectiveness of the proposed SAR ADC PSA method and countermeasure schemes.

Reconfigurable CNN Processor for Compressed Networks

Convolutional neural networks (CNNs) have become the standard for performing complex tasks such as image classification due to their high accuracy. However, they typically involve substantial computation (~109 multiplies and adds) to process a single image and require a large amount of storage (~10 to 100 MB) for the fixed weight parameters and intermediate output activations. This makes it challenging to process CNNs locally on edge devices with low power and low latency. To address this, we need custom hardware accelerators to exploit the high parallelism present in the computations. At the same time, they should be flexible enough to support various networks, especially as new and better networks are continuously being developed. Because of the memory constraints on edge devices, we focus on networks compressed by techniques such as Deep Compression and Trained Ternary Quantization, which quantize the weights to a small number of unique values (usually 16 or fewer).We propose a scalable architecture for efficiently processing compressed networks by reordering the multiplications and additions. Instead of performing each multiply-and-add separately, we accumulate all the activations multiplied by the same weight together and perform the multiplication at the end. With a small number of unique weights, the number of multiplications is greatly reduced, and consequently decreasing the average energy per operation. To enable the tradeoff between accuracy and efficiency, we added reconfigurability for different weight and activation bit widths. This allows us to use shorter bit widths in applications where energy must be minimized and a drop in accuracy can be tolerated. With added support for residual connections and depthwise convolutions, our accelerator can run modern networks such as ResNet and MobileNet, enabling CNN processing for a wide range of applications on energy-constrained devices including cell phones and IoT nodes.

Simulation and Analysis of GaN CMOS Logic

There is an increasing demand for electronics that can operate in high-temperature conditions, such as spacecraft and sensors for industrial environments. A promising solution exists in electronics based on wide-bandgap materials, among which gallium nitride (GaN) stands out as a strong candidate due to its excellent material properties and potential for monolithic integration. Most current demonstrations of GaN logic are based on nMOS technology, which has a high static power consumption. GaN CMOS technology, which has lower static power consumption, is desired.This work studies the effect of p-channel transistor performance and circuit parameters on the performance of CMOS digital logic circuits. The industry-standard MIT virtual source GaN-FET model (MVSG) was used to accurately model the behavior of the n-channel and p-channel transistors, which were fabricated on the developed GaN-complementary circuit platform. Furthermore, excellent matching was achieved between the experimental data of a fabricated CMOS logic inverter and the simulated compact models. Several building blocks of digital logic, namely, the logic inverter, multi-stage ring oscillator, and static random-access memory (SRAM) cell, were studied using the developed computer-aided design (CAD) framework. Device-circuit co-design was conducted to optimize circuit performance, using a variety of design parameters including transistor sizing and supply voltage scaling. The high temperature performance of the circuits, simulated based on experimentally observed trends of the devices, was projected. The results indicate that GaN CMOS technology based on our monolithically integrated platform has potential for a variety of use cases, including harsh-environment digital computation. This technique will be scaled up for more complex combinational and sequential logic building blocks, with the eventual goal of realizing a GaN CMOS microprocessor.

Energy-efficient SAR ADC with Background Calibration and Resolution Enhancement

Many signals, for example, medical signals, do not change much from sample to sample most of the time. Conventional switching schemes for SAR ADCs do not exploit this signal characteristic and test each bit start-ing with the MSB. Previous work called least-signifi-cant-bit (LSB)-first saves energy and bit-cycles by start-ing with a previous sample code and searching for the remainder by testing bits from the LSB end. However, certain code transitions consume unnecessary energy, even when the code change over the previous code is small.This work addresses this problem with a new algo-rithm called Recode then LSB-first (RLSB-first) that re-duces the switching energy and bit-cycles required for all cases of small code change across the full range of possible previous sample codes. RLSB-first uses split-DAC to systematically encode the previous code before LSB-first. RLSB-first lowers switching energy by up to 2.5 times and uses up to 3 times fewer bit-cycles than LSB-first. In addition to creating an energy-efficient SAR ADC, this work aims to use the savings for back-ground calibration and resolution enhancement.

Rethinking Empirical Evaluation of Adversarial Robustness Using First-order Attack Methods

Deep neural networks (DNNs) are known to be vulnerable to adversarial perturbations, which are often imperceptible to humans but can alter predictions of machine learning systems; robustness against those perturbations is becoming an important design factor. A practical approach to measuring adversarial robustness of DNNs is to use the accuracy of those models on examples generated by adversarial attack methods as a proxy for adversarial robustness. However, the failure of those attack methods to find adversarial perturbations cannot be equated with being robust. In our work, we identify three phenomena that inflate accuracy against popular bounded first-order attack methods: 1) a loss function numerically becoming zero when using standard floating point representation, resulting in non-useful gradients; 2) innate non-differentiable functions in DNNs, such as ReLU activation and Max Pooling, incurring “gradient masking”; and 3) certain regularization methods used during training to induce the models to be less amenable to first-order approximation. For each case, we propose compensation methods to improve the evaluation metric for adversarial robustness. The impact of these three sources of overestimated adversarial robustness can be significant when comparing different model capacities for adversarial robustness. For example, Figure 1 shows the adversarial robustness of deep models with the same architecture but different number of neurons per layer. Compensating for these three phenomena can change the relative benefit of using larger models in terms of adversarial accuracy. Similarly, Figure 2 shows adversarial robustness when we iteratively prune weights of an over-parameterized deep model. Adversarial accuracy against the baseline attack method significantly drops as we prune the model; however, actually there is little difference between the original dense model and the sparser models in their adversarial robustness when we properly compensate for these phenomena. Therefore, it is important to rethink the metric we use before we draw conclusions on model capacities or other design factors for their adversarial robustness.

Efficient Video Understanding with Temporal Shift Module

Hardware-efficient video understanding is an important step towards real-world deployment, both in the cloud and on the edge. For example, there are over 10^5 hours of videos uploaded to YouTube every day to be processed for recommendation and ad ranking; similarly, terabytes of sensitive videos in hospitals need to be processed locally on edge devices to protect privacy. All these industry applications require both accurate and efficient video understanding.Traditionally, a 2D convolutional neural network (CNN) is more efficient but cannot model temporal information; 3D CNN can perform spatial-temporal feature learning, but at the cost of high computation. In this paper, we propose a novel temporal shift module (TSM), which achieves 3D CNN performance at 2D cost. By shifting some of the channels bi-directionally along the temporal dimension, we can facilitate temporal reasoning in 2D CNN at the cost of zero FLOPs and zero parameters. We also propose a uni-directional TSM for online video understanding, supporting online classification and detection from a streaming video.TSM is efficient and accurate: on temporal related datasets, we can improve the performance by double digits at almost no overhead compared to a 2D network. TSM ranks first on Something-Something leaderboard upon submission. TSM is highly scalable: it can be scaled up to 1,536 GPUs and finish the training on Kinetics in 15 minutes; it can also be scaled down to edge deployment, achieving 77 FPS on Jetson Nano and 29 FPS on Galaxy Note 8.

Secure System for Implantable Drug Delivery

Recent advances in microelectronics and medical technology have enabled Internet-connected IMDs that the patients/users can control through external handheld or wearable devices. However, several proof-of-concept attacks have been demonstrated on such devices by exploiting weaknesses in authentication protocols or their implementations. While such connected implantable devices have the potential to enable many emerging medical applications such as on-command implantable drug delivery, security concerns pose a threat to their widespread deployment. To address this challenge, we present a secure low-power integrated circuit (IC) with sub-nW sleep-state power, energy-efficient cryptographic acceleration, and a novel dual-factor authentication mechanism that ensures that the ultimate security of the IMD lies in the hands of the user. As a solution, we propose a dual-factor authentication scheme in which cryptographic authentication is supplemented with a voluntary response from the user. The voluntary response serves as a guarded action from the user; that is, it represents consent from the user for executing the desired action without causing them much inconvenience. In our protocol, we have selected a touch-based voluntary response where the user taps on their skin near the IMD. Since most implants are subcutaneous, they can easily detect the tap-pattern and authenticate using this second-factor response. Clearly, for an adversary to provide correct second-factor response to the IMD without alerting the user is difficult, which provides higher security guarantees. In addition to second-factor authentication, the human voluntary factor (human touch) is also used for waking up the system. This provides dual benefits of achieving extremely low-power wake-up and protecting against energy-drainage attacks. Through circuit-level optimizations, energy-efficient architecture and a novel dual-factor authentication mechanism, this work demonstrates a low-power IC for securing connected biomedical devices of the near future.

A Sampling Jitter Tolerant Continuous-time Pipelined ADC in 16-nm FinFET

Almost all real-world signals are analog. Yet most data is stored and processed digitally due to advances in the integrated circuit technology. Therefore, analog-to-digital converters (ADCs) are an essential part of any electronic system. The advances in modern communication systems including 5G mobile networks and baseband processors require the ADCs to have large dynamic range and bandwidth. Although there have been steady improvements in the performance of ADCs, the improvements in conversion speed have been less significant because the sampling clock jitter limits the speed-resolution product (Figure 1). The effect of sampling clock jitter has been considered fundamental. However, it has been shown that continuous-time delta-sigma modulators may reduce the effect of sampling jitter. But since delta-sigma modulators rely on relatively high oversampling, they are unsuitable for high frequency applications. Therefore, ADCs with low oversampling ratio are desirable for high-speed data conversion. In conventional Nyuistrate ADCs, the input is sampled upfront (Figure 2). Any jitter in the sampling clock directly affects the sampled input and degrades the signal-to-noise ratio (SNR). It is well known that for a known rms sampling jitter σt the maximum achievable SNR is limited to 1/(2πfinσt,) where fin is the input signal frequency. In an SoC environment, it is difficult to reduce the rms jitter below 100 fs. This limits the maximum SNR to just 44 dB for a 10 GHz input signal. Therefore, unless the effect of sampling jitter is reduced, the performance of an ADC would be greatly limited for high frequency input signals.In this project, we propose a continuous-time pipelined ADC having reduced sensitivity to sampling jitter. We are designing this ADC in 16-nm FinFET technology to give a proof-of-concept for improved sensitivity to the sampling clock jitter.

Bandgap-less Temperature Sensors for High Untrimmed Accuracy

Temperature sensors are extensively used in measurement, instrumentation, and control systems. A sensor that integrates the sensing element, analog-to-digital converter, and other interface electronics on the same chip is referred to as a smart sensor. CMOS- based smart temperature sensors offer the benefits of low cost and direct digital outputs over conventional sensors. However, they are limited in their absolute ac-curacy due to the non-ideal behavior of the devices used to design them. Therefore, these sensors require either calibration or gain/offset adjustments in the analog domain to achieve desired accuracies (Figure 1). The latter process, also called trimming, needs additional expensive test equipment and valuable production time and is a major contributor to the cost of the sensors. To enable high volume production of CMOS- based temperature sensors at low cost, it is imperative to achieve high accuracies without trimming.This work proposes the design of a CMOS temperature sensor that uses fundamental physical quantities resilient to process variations, package stress, and manufacturing tolerances, in order to achieve high accuracies without trimming. Simulation results prove that 3σ inaccuracy of less than 1o C can be obtained with the proposed method.

Low Power Time-of-flight Imaging for Dynamic Scenes

Depth sensing is useful for many emerging applications, which include mobile augmented reality and robotics. Time-of-flight (ToF) cameras are appealing depth sensors that obtain dense depth measurements, or depth maps, with minimal latency. However, because these sensors obtain depth by emitting light, they can be power-hungry and limit the battery-life of mobile devices. To address this limitation, we present two approaches, shown in Figure 1, that reduce the power for depth sensing by leveraging the other available data: (1) when RGB images are concurrently collected, our technique reduces the usage of the ToF camera and estimates new depth maps using a previous depth map and the consecutive images; (2) when only the data from a ToF camera is available, we adaptively vary the amount of light that the ToF camera emits to infrequently obtain high-power depth maps and to use them to denoise subsequent low power ones. In the second scenario, the ToF camera is always on, but we reduce the overall amount of emitted light while still obtaining accurate depth maps.In contrast to our previous approaches that dealt with rigid environments, our techniques here can be used for applications that operate in dynamic environments, where the ToF camera and objects in the scenes can have independent, rigid, and non-rigid motions. For dynamic scenes, we show two benefits: (1) when RGB images are concurrently collected, our algorithm can reduce the usage of the ToF camera by over 90%, while still estimating new depth maps with a mean relative error (MRE) of 2.5% when compared to depth maps obtained using a ToF camera; and (2) when only the data from a ToF camera is available, our algorithm can reduce the overall amount of emitted light by up to 81% and the MRE of the low power depth maps by up to 64%. For these techniques, our algorithms use sparse operations and linear least squares to efficiently estimate or denoise depth maps at up to real-time (e.g., 30 fps) using the CPUs of a standard laptop computer and an embedded processor. Our work taken together enables energy-efficient, low latency, and accurate depth sensing for a variety of emerging applications.

CMOS Molecular Clock Using High-order Rotational Transition Probing and Slot-array Couplers

Recently, chip-scale molecular clock (CSMC) referenced to sub-THz transitions of carbonyl sulfide (OCS) gas has emerged as a low-cost solution to achieve high stability with a small size. However, the long-term stability of the first CSMC is limited by the non-flat transmission baseline, which is susceptible to environmental disturbance. In order to enhance the long-term stability, we presented a CSMC chip that enables high-order dispersion curve locking. Since Nth-order dispersion curve can be comprehended as Nth-order derivative of the OCS line profile, the baseline tilting becomes negligible with high-order dispersion curve. Also, our chip adopts a pair of slot array couplers (SAC) for low loss chip-to-waveguide connection. Figure 1 shows the clock architecture which consists of a spectroscopic transmitter (TX), referenced to a 60 MHz voltage-controlled crystal oscillator (VCXO), and a spectroscopic receiver (RX). In order to generate the TX probing signal which is wave-length-modulated at a rate of fm=100kHz, high-accuracy, differential sine signal at fm is generated by a pair of 8bit DACs and then fed to varactors in the 57.77 GHz VCO in TX PLL2. The harmonic-rejection lock-in detector (HRLKD) is referenced to fLKREF=3fm, since the 3rd-order dispersion curve is used in this work. Figure 2 shows the structure and simulated S parameter of the SAC. The simulated loss and 3dB fractional bandwidth of the SAC are 5.2dB and 22%, respectively. The chip was fabricated in a 65nm bulk CMOS process and its DC power consumption was 70mW. The measured Allan Deviation are 3.2×10-10@τ=1s and 4.3×10-11@τ=103s, respectively, and the measured magnetic sensitivity of the unshielded clock is ±2.9×10-12/Gauss. With an on-chip temperature sensor and a 2nd-order polynomial compensation, the frequency drift over temperature range of 27~65°C is ±3.0×10-9. This work based on very compact size and low cost demonstrates stability performance that is comparable with chip-scale atomic clocks. Its applications include 5G cellular basestations, portable navigation systems, communication and sensing under GPS-denied conditions.

FastDepth: Fast Monocular Depth Estimation on Embedded Systems

Depth sensing is a critical function for many robotic tasks such as localization, mapping and obstacle detection. There has been a significant and growing interest in performing depth estimation from a single RGB image, due to the relatively low cost and size of monocular cameras. However, state-of-the-art single-view depth estimation algorithms are based on fairly large deep neural networks that have high computational complexity and slow runtimes on embedded platforms. This poses a significant chal-lenge when performing real-time depth estimation on an embedded platform, for instance, mounted on a Micro Aerial Vehicle (MAV). Our work addresses this problem of fast depth estimation on embedded systems. We investigate efficient and lightweight encoder-decoder network architectures. To further improve their computational efficiency in terms of real metrics (e.g., latency), we apply resource-aware network adaptation (NetAdapt) to automatically simplify proposed architectures. In addition to reducing encoder complexity, our proposed optimizations significantly reduce the cost of the decoder network (Figure 1). We perform hardware-specific compilation targeting deployment on the NVIDIA Jetson TX2 platform. Our methodology demonstrates that it is possible to achieve similar accuracy as prior work on depth estimation, but at inference speeds that are an order of magnitude faster (Figure 2). Our network, FastDepth, runs at 178 fps on a TX2 GPU and at 27 fps when using only the TX2 CPU, with active power consumption under 10 W.

Design Considerations for Efficient Deep Neural Networks in Processing-in-memory Accelerators

Deep neural networks (DNNs) deliver state-of-the-art accuracy on a wide range of artificial intelligence tasks at the cost of high computational complexity. Since data movement tends to dominate energy consumption and can limit throughput for memory-bound workloads, processing in memory (PIM) has emerged as a promising way for processing DNNs. Unfortunately, the design of efficient DNNs specifically for PIM accelerators has not been widely explored. In this work, we highlight the key differences between PIM and digital accelerators and summarize how these differences need to be accounted for when designing DNNs for PIM accelerators. The key design considerations include (1) resilience to circuit and device non-idealities, which affect accuracy; (2) data movement of feature map activations, which affects energy consumption and latency; and (3) utilization of the memory array, which affects energy consumption and latency. We examine the use of PIM accelerators on 18 DNNs published since 2012 for image classification on the ImageNet dataset to highlight the importance of the various design considerations. Our experiment results show that the common principles used to design efficient DNNs for digital accelerators (e.g., making a DNN deeper with smaller layers) may not suit PIM accelerators. Therefore, we need to rethink how to design efficient DNNs for PIM accelerators.

A Terahertz FMCW Comb Radar in 65-nm CMOS with 100GHz Bandwidth

The increasing demands for low-cost, compact, and high-resolution radar systems have driven the op-eration frequency to terahertz due to the shorter wavelength and larger bandwidth. However, conven-tional single-transceiver frequency-modulated contin-uous-wave (FMCW) radar chips provide only limited signal bandwidth, especially when implemented using Complementary metal–oxide–semiconductor (CMOS) technologies with low fT and fmax. Therefore, prior THz integrated radars are based on compound semicon-ductors and have severely degraded performance near the band edges. That not only limits their applications in high-accuracy scenarios but also creates tradeoffs between bandwidth and detection range. To avoid such limitations, we adopt a frequency-comb-based scalable architecture using a paralleled transceiver array as shown in Figure 1. The concept of the FMCW comb radar is illustrated as a wideband chirp signal is divided into N identical segments that sweep simultaneously using an array of transceivers with equally-spaced carrier frequencies. Each transceiver has its own on-chip antenna, and the received echo sig-nal is mixed with the transmitted signal to generate an IF output. The presented high-parallelism scheme of-fers several advantages over single-transceiver radars. Firstly, it achieves scalable bandwidth extension and enables implementations in less advanced technologies as well as flatter frequency responses across the entire operation band. Secondly, the flat frequency response also leads to higher linearity of the equivalent chirp signal. Thirdly, the SNR of comb radar is improved by N for a given total detection time. Implemented in a 65-nm bulk CMOS process, a five-transceiver radar chip is prototyped with seamless coverage of the entire 220-to-320GHz band as shown in Figure 2. Across the total chirp bandwidth of 100GHz, 0.6dBm/20dBm (with/without lens) multi-channel-ag-gregated EIRP with 8.8dB output power fluctuation, and 22.8dB minimum RX noise figure are achieved. With all five channels stitched together, 2.5-mm separa-tion of two objects is clearly detected. This chip has an area of 5mm2 and consumes 840mW of power. This is the first demonstration of THz radar in CMOS process, and a record FMCW bandwidth is achieved.

GaN Electronics for High-temperature Applications

Gallium nitride is a promising candidate for high-tem-perature applications. However, despite the excellent performance shown by early high-temperature proto-types, several issues in traditional lateral AlGaN/GaN HEMTs could cause early degradation and failure un-der high-temperature operation (over 300°C). These in-clude ohmic degradation, gate leakage, buffer leakage, and poor passivation. Additionally, enhancement-mode HEMTs are preferred from the application point of view because they reduce the circuit complexity and cost. At the same time, the two-dimensional electron gas induced by AlGaN/GaN heterostructures makes HEMTs naturally depletion-mode devices. Devices capable of high-temperature operation were demonstrated by combing gate injections tran-sistors (GITs) with ion-implanted refractory metal con-tacts. A self-aligned gate-first process, together with an etch-stop process, was developed and optimized to improve fabrication efficiency and device uniformity for large-scale integration. Basic logic building blocks including inverters, a NAND gate, a NOR gate, SRAM, and a ring oscillator have been demonstrated and char-acterized at both room temperature and high tempera-ture (300°C).

Hybrid Intelligence in Design

One of the greatest challenges facing society is addressing the complexities of big picture, system-level, interdisciplinary problems in a holistic way. Human designers, architects, and engineers have come to rely on steadily improving computational tools to design, model, and analyze their systems of interest. At this stage one might ask several questions: “How could we teach junior engineers, architects, and scientists to design complex systems successfully without spending years on job training? Could we also assist human experts to minimize the probability of failure by leveraging recent developments in artificial intelligence (AI) and big data?” While the resurgence of AI and machine learning suggest ways to even more fully automate downstream tasks in the design process, we propose to go up-stream of design, where all the key concepts are determined. Could machine intelligence help this early stage of designing beyond routine design and the optimization of pre-specified goals toward the generation of good, novel designs? To capture the benefit of machine learning for design, the information and knowledge embodied in design must be represented in a method that machines can understand, memorize, and retrieve, with the goal of enhancing the practice of design. Preliminary investigation has shown how Natural Language Processing (NLP) models can be applied to accurately estimate design metrics such as functional independence based solely on descriptions of different design cases, as shown in Figure 1. With a framework for representing design knowledge, machines can effectively augment the work of human designers at the early stages of the design process.

Partition WaveNet for Deep Modeling of Automated Material Handling System Traffic

The throughput of a modern semiconductor fabrication plant depends greatly on the performance of its automated material handling system. Spatiotemporal modeling of the dynamics of a material handling system can lead to a multi-purpose model capable of generalizing to many tasks, including dynamic route optimization, traffic prediction, and anomaly detection. Graph-based deep learning methods have enjoyed considerable success in other traffic modeling domains, but semiconductor fabrication plants are out of reach because of their prohibitively large transport graphs. In this report, we consider a novel neural network architecture, Partition WaveNet, for spatiotemporal modeling on large graphs. Partition WaveNet uses a learned graph partition as an encoder to reduce the input size combined with a WaveNet-based stacked dilated 1D convolution component. The adjacency structure from the original graph is propagated to the induced partition graph. We discuss the motivation for framing our problem as a supervised learning task instead of a reinforcement learning task, as well as the benefits of Partition WaveNet over alternative neural network architectures. We evaluate Partition WaveNet on data from a simulated and a real semiconductor fabrication plant. We find that Partition WaveNet outperforms other spatiotemporal networks using network embeddings or graph partitions for dimensionality reduction.

Efficient AutoML with Once-for-all Network

We address the challenging problem of efficient inference across many devices and resource constraints, especially on edge devices. Conventional approaches either manually design or use neural architecture search (NAS) to find a specialized neural network and train it from scratch for each case, which is computationally prohibitive (causing CO2 emission as much as 5 cars' lifetime) and thus unscalable. In this work, we propose to train a once-for-all (OFA) net-work that supports diverse architectural settings by decoupling training and search, to reduce the cost. We can quickly get a specialized sub-network by selecting from the OFA network without additional training. To efficiently train OFA networks, we also propose a novel progressive shrinking algorithm, a generalized pruning method that reduces the model size across many more dimensions than pruning (depth, width, kernel size, and resolution). It can obtain a surprisingly large number of sub-networks that can fit different hardware platforms and latency constraints while maintaining the same level of accuracy as training independently. On diverse edge devices, OFA consistently outperforms state-of-the-art (SOTA) NAS methods (up to 4.0% ImageNet top1 accuracy improvement over MobileNetV3, or same accuracy but 1.5x faster than MobileNetV3, and 2.6x faster than EfficientNet w.r.t measured latency) while reducing GPU hours and CO2 emission by many orders of magnitude. In particular, OFA achieves a new SOTA 80.0% ImageNet top1 accuracy under the mobile setting (<600M MACs).OFA is the winning solution for the 3rd Low Power Computer Vision Challenge (LPCVC, classification DSP track) and the 4th LPCVC (both classification track and detection track).

Robustness Verification and Defense for Tree-based Machine Learning Models

Although adversarial examples and model robustness have been extensively studied in the context of linear models and neural networks, research on this issue in tree-based models is still limited, despite the prevalence of tree-based models in manufacturing and other domains. In this work, we develop a novel algorithm to learn robust trees, as well as an efficient algorithm to evaluate the robustness of a tree-based model. Our first algorithm aims to optimize the performance under the worst-case perturbation of input features, which leads to a max-min saddle point problem. Incorporating this saddle point objective into the decision tree building procedure is nontrivial due to the discrete nature of trees—a naive approach to finding the best split according to this saddle point objective will take exponential time. To make our approach practical and scalable, we approximate the inner minimizer in this saddle point problem and present implementations for classical information gain-based trees as well as state-of-the-art tree boosting models such as XGBoost. As demonstrated in Figure 1, experimental results on real world datasets demonstrate that the proposed algorithms can substantially improve the robustness of tree-based models against adversarial examples. Formal robustness verification of decision tree ensembles involves finding the exact minimal adversarial perturbation or a guaranteed lower bound, which is NP-complete in general. We show that for tree ensembles, the verification problem can be cast as a max-clique problem on a multipartite graph with bounded boxicity. For low dimensional problems when boxicity can be viewed as constant, this reformulation leads to a polynomial time algorithm. For general problems, by exploiting the boxicity of the graph, we develop an efficient multi-level verification algorithm that can give tight lower bounds on the robustness of decision tree ensembles while allowing iterative improvement and anytime termination. As in Figure 2, our algorithm is much faster than a previous approach that requires solving mixed integer linear programming (MILP) and can give tight robustness verification bounds on large models with one thousand deep trees.

An Efficient and Continuous Approach to Information-theoretic Exploration

Exploration of unknown environments is embedded in many robotics applications: search and rescue, crop survey, space exploration, etc. The central problem an exploring robot must answer is “where should I move next?” The answer should balance travel cost with the amount of information expected to be gained about the environment. Traditionally, this question has been an-swered by a variety of heuristics that provide no guar-antees on their exploration efficiency. Information-the-oretic methods can produce an optimal solution, but until now they were thought to be computationally intractable.In our recent work we describe the Fast Continu-ous Mutual Information (FCMI) algorithm, which com-putes the information-theoretic exploration metric ef-ficiently. FCMI takes as input an incomplete occupancy map like the one shown in Figure 1, where white pix-els indicate free space, black pixels indicate occupied space, and gray pixels indicate unknown space. It then returns an information surface as shown in Figure 2, where the brightness of each pixel indicates how much information is expected to be gained by exploring at that location. The algorithm also works on multi-reso-lution or 3-dimensional maps. FCMI has a lower asymp-totic complexity than existing methods and our exper-iments demonstrate that it is hundreds of times faster than the state-of-the-art for practical inputs.The key insight that enables FCMI is to consid-er the occupancy map as a continuous random field rather than a discrete collection of cells. This reveals a nested information structure that makes it possible to recursively reuse computation from one map location in adjacent locations. The continuous structure also provides more general insights that are relevant to any occupancy mapping system.For practical map sizes, FCMI runs in seconds on a single threaded laptop CPU which is well within the timing constraints for most robotic applications. It provides considerable savings to energy constrained systems by reducing both the exploration travel cost and the computation cost. FCMI is also highly paral-lelizable and suited for a rapid, low energy, embedded implementation.

On the Use of Deep Learning for Retrieving Phase from Noisy Inputs in the Coherent Modulation Imaging Scheme

Low-dose light imaging is of significance in many cases when minimal radiation exposure of samples is desired. In biological imaging, high-dose light may induce phototoxic effects at the cost of larger signal-to-noise ratio (SNR). In particle imaging, for instance, imaging integrated circuits (IC) with high-power beam leads to destructive side-effects, e.g., heat-induced deformation. However, quantum nature of photon detection influences and degrades the quality of intensity measurements, and on top of the Poisson statistics, other types of noise sources, e.g., thermal or readout noise, add up.Deep neural networks (DNNs) have been used for retrieving phase information from noisy intensity measurements. Nonetheless, the ill-posedness of the inversion problem, governed by a physical system design, could not be sufficiently addressed when the DNN alone was used. Due to the ill-posedness of the system, residual artifacts remained in reconstructions, thus a decrease in image fidelity. Therefore, we suggest the application of random phase modulation on an optical field, also known as a coherent modulation imaging (CMI) scheme, along with the DNNs as a method of reconstruction.In this work, we provide both quantitative and qualitative results that unwanted artifacts in reconstructions are largely removed in the coherent modulation imaging scheme under low-light conditions in conjunction with the DNNs. Here, phase extraction neural network (PhENN), which is an encoder-decoder DNN architecture based on ResNet specifically optimized for phase retrieval tasks, was used as a design of the DNN.

Rapid Uniformity Tuning in Ion Implantation Systems Using Bayesian Optimization

As the size of integrated circuits continue to shrink, variations in their fabrication processes become more significant, hindering their electrical performances and yields. One such wafer-scale variation occurs in ion implantation processes, where an ion beam implants charged particles into a substrate. As the beam is scanned across the wafer, its shape and intensity often change, resulting in a non-uniform implantation. This effect can be compensated for by adjusting the speed of the ion beam as it moves across the wafer; however, in order to do so, the dynamics of the ion beam shape must be known.Our work focuses on using Bayesian optimization, a form of reinforcement learning, to rapidly learn how the beam shape changes, and to optimize the beam speeds in order to reduce non-uniformities. Here, we capture our knowledge of the beam shapes by treating its intensities as multivariate, normally distributed, random variables. After observing new implantations, we then use this framework to update our belief of the beam shapes, then solve for a new set of scan speeds which result in our desired profile under this updated model. We then continue this process until we converge to our desired profile. After this initial tuning, the same tuning algorithm continues to run during normal operation. Implantation measurements are periodically made, the model is updated using these measurements, and any corrections to the scan speeds are made in order to maximize uniformity. This process allows us to both quickly tune a new implantation recipe, while also allowing us to learn and compensate for any changing conditions in the tool.

A Mutual Information Accelerator for Autonomous Robot Exploration

Robotic exploration problems arise in various contexts, ranging from search and rescue missions to underwater and space exploration. In these domains, exploration algorithms that allow the robot to rapidly create the map of the unknown environment can reduce the time and energy for the robot to complete its mission. Shannon mutual information (MI) at a given location is a measure of how much new information of the unknown environment the robot will obtain given what the robot already know from its incomplete understanding of the environment. In a typical exploration pipeline, robot starts with an incomplete map of the environment. At every step, the robot computes the MI across the entire map. Then, the robot can select the location with the highest mutual information for exploration in order to gain the most information about the unknown environment.However, on the CPUs and GPUs typically found on mobile robotic platforms, computing MI using the state-of-the-art Fast Shannon Mutual Information (FSMI) algorithm across the entire map takes more than one second, which is too slow for enabling fast autonomous exploration. As a result, the emerging literature considers approximation techniques, and many practitioners rely on heuristics that often fail to provide any theoretical guarantees. To eliminate the bottleneck associated with the computation of MI across the entire map, we propose a novel multicore hardware architecture (Figure 1) with a memory subsystem that efficiently organizes the storage of the occupancy grid map and an arbiter that effectively resolves memory access conflicts among MI cores so that the entire system achieves high throughput. In addition, we provide rigorous analysis of memory subsystem and arbiter in order to justify our design decisions and provide provable performance guarantees. Finally, we thoroughly validated the entire hardware architecture by implementing it using a commercial 65nm ASIC technology (Figure 2).

Ionic Analog Synapses for Deep Learning Accelerators

The recent progress in novel hardware/software co-optimizations for machine learning has led to tremendous improvement of the efficiency of neural networks. Nevertheless, the energy efficiency is still orders of magnitude lower than biological counterpart – the brain. Digital CMOS architecture has inherent limitations for deep learning applications due to their volatile memory, spatially separated memory and computation, and the lack of connectivity between nodes. Crossbar arrays of non-volatile memory devices, able to perform simple operations (e.g. bit multiplication), can potentially achieve a 30000× improvement in energy efficiency. State-of-the-art analog “synaptic” devices based on resistive memories suffer from stochastic, asymmetric, and non-linear weight updates, detrimental to training accuracy. Electrochemical ionic devices have been shown to be fast, energy efficient, and exhibit symmetric, linear weight updates. However, electrolytes used for the electrochemical reaction are often CMOS incompatible and suffers from scalability. Here we propose a new transistor-based analog synapse, consisting of a proton-doped SiO2 gate oxide which electrostatically modifies the threshold voltage of the semiconductor channel, tuning the channel conductance (Figure 1). Non-volatility is maintained by trapping of protons in the oxide. Due to electrostatics, we expect to observe a symmetric and linear shift in threshold voltage, leading to linear weight updates. We study the proton diffusion and electrostatic effects through device simulation via Silvaco Atlas and analytical modeling. Simulations show a threshold voltage shift of the MOS gate stack due to the presence of ions in the gate oxide (Figure 2). We fabricate n-Si/ALD SiO2/Al MOS capacitor and to demonstrate the feasibility of our ionic device. We observe that the MOS gate stack exhibits hysteretic behavior below 2V, indicating non-volatility and low-voltage operation. The results of this work will shed light on the feasibility of simple CMOS-compatible ionic devices for the next generation of neural network hardware accelerators.

Efficient 3D Deep Learning with Point-voxel CNN

3D deep learning has received increased attention thanks to its wide applications: e.g., AR/VR and autonomous driving. These applications need to interact with people in real time and therefore require low latency. However, edge devices (such as AR/VR headsets and self-driving cars) are tightly constrained by hardware resources and battery. Previous work processes 3D data using either voxel-based or point-based NN models. However, both approaches are computationally inefficient. The computation cost and memory footprints of the voxel-based models grow cubically with the input resolution, making it memory-prohibitive to scale up the resolution. As for point-based networks, up to 80% of the time is wasted on structuring the sparse data which have rather poor memory locality, not on the actual feature extraction.To this end, we propose Point-Voxel CNN (PVCNN) that represents the 3D input data as point clouds to take advantage of the sparsity to reduce the memory footprint, and leverages the voxel-based convolution to obtain the contiguous memory access pattern (Figure 1). Evaluated on semantic and part segmentation datasets, it achieves a much higher accuracy than the voxel-based baseline with 10× GPU memory reduction; it also outperforms the state-of-the-art point-based models with 7× measured speedup on average (Figure 2). We validate its general effectiveness on 3D object detection: Frustrum PVCNN outperforms Frustrum PointNet++ by up to 2.4% mAP with 1.8× measured speedup and 1.4× GPU memory reduction.

Learning Human-environment Interactions Using Scalable Functional Textiles

Living organisms extract information and learn from the surroundings through constant physical interactions. For example, humans are particularly receptive to tactile cues (on hands, limbs, and torso), which enable the performing of complex tasks like dexterous grasp and locomotion. Observing and modeling interactions between humans and the physical world are fundamental for the study of human behavior, healthcare, robotics, and human-computer interactions. However, many studies of human-environment interactions rely on more easily observable visual or audible datasets because it is challenging to obtain tactile data in a scalable manner. Recently, Sundaram et al. coupled tactile-sensing gloves and machine learning to uncover signatures of the human grasp. However, the recording and analysis of whole-body interactions remain elusive, as this would require large-scale wearable sensors with low cost, dense coverage, conformal fit, and minimal presence to permit natural human activities. We present a textile-based tactile learning platform that enables researchers to record, monitor, and learn human activities and the associated interactions. Realized with inexpensive piezoresistive fibers (0.2 USD/m) and automated machine knitting, our functional textiles offer dense coverage (> 1000 sensors) over large complex surfaces (> 2000 cm2). Further, we leverage machine learning for sensing correction, ensuring that our system is robust against potential variations from individual receptors. To validate the capability of our sensor, we capture diverse human-environment interactions (> 1,000,000 tactile frames) and demonstrate that machine learning techniques can be used with our data to classify human activities, predict whole-body poses, and discover novel motion signatures. This work opens new possibilities in wearable electronics, healthcare, manufacturing, and robotics.

Automated Fault Detection in Manufacturing Equipment Using Semi-supervised Deep Learning

Our project investigates the use of semi-supervised deep learning systems for automated fault detection and predictive maintenance of manufacturing equipment. Unexpected equipment faults can be highly costly to manufacturing lines, but data-driven fault detection systems often require a high level of domain-specific expertise to implement as well as continued human oversight. To this end, we are developing and testing general-purpose fault detection systems that require minimal labeled data. Our system trains deep autoencoders to function as a non-linear compression algorithm for sensor readings from manufacturing equipment. The compressed sensor signals are used as a proxy for the equipment’s hidden state, and the reconstruction error is used to detect unexpected behavior. The compressed representation and reconstruction error are combined to provide a robust anomaly score. Instances in time with the highest anomaly score are then flagged to be labeled by a human operator as faulty or nominal. With sparsely labeled faults, the system then uses Gaussian mixture models to classify different types of errors and predicts future faults by monitoring parameter drift towards known fault states. Our system is currently being trained to detect failed runs on a plasma etcher (used for integrated circuit fabrication) using internal sensors that take voltage, current, pressure, and temperature readings. In preliminary tests, the system was able to correctly detect 88% of failed etching runs and identify specific markers in different signals indicative of faults. For example, a failure mode of the plasma etcher involves an abnormally high temperature (Figure 1). Without any labeled errors, the system flagged the higher temperatures as possibly indicative of faults (Figure 2).We are currently testing the system on a wider range of applications, including estimating wear of milling machine cutting tools and predicting the risk of breakage. We are also developing prototypes of contactless voltage/current sensors that can easily be retrofitted onto older machinery to test the efficacy of fault detection systems using only external power draw.

Control of Conductive Filaments in Resistive Switching Oxides

There is a growing interest in using specialized neuro-morphic hardware for artificial neural network appli-cations such as image and speech processing, which require significant computational resources. These neuromorphic devices show promise for reducing the demands of such applications by increasing speed and decreasing power consumption compared to current software-based methods. One approach to achieving this goal is through oxide thin film resistive switching devices arranged in a crossbar array configuration. Re-sistive switching can mimic several aspects of neural networks, such as short- and long-term plasticity, via the dynamics of switching between multiple analog conductance states-dominated by the creation, annihi-lation, and movement of defects within the film (such as oxygen vacancies). These processes can be stochas-tic in nature and contribute significantly to device vari-ability, both within and between individual devices. Our research focuses on reducing the variability of the set/reset voltages and enhancing control of the con-ductance state with voltage pulsing using model sys-tems of HfO2 grown on Nb:SrTiO3 substrates through the control of film growth and processing parameters. We show that depending on the growth temperature, substrate orientation, and substrate surface treatment, devices can exhibit forming-free switching or forming voltages ranging from 4 to 7 V. Forming-free devices show lower variability in the high and low conduc-tance states but have a lower on/off conductance ratio. We rationalize these results using film microstructure information obtained from 2D X-ray diffraction and cross-sectional transmission electron microscopy. This work provides a significant step towards controlling the mechanisms behind device variability and achiev-ing devices that meet the strict requirements of neuro-morphic computing.

Variational Inference for Model-free Simulation of Dynamic Systems with Unknown Parameters

Complex physical, biological, and engineering processes can be modelled using dynamic systems with few parameters. However, in real-world applications including manufacturing, it is possible to encounter systems for which the dynamics are not well understood and identifying the parameters is challenging.“Model-free” approaches aim to learn the dynamics of the system from data. Classical statistical models assume the dynamics are linear to make the inference analytically tractable. Extension to nonlinearity usually requires partial knowledge about the system. Our goal is to achieve modeling of nonlinear dynamic systems purely by using data with the strength of deep learning.In this work, we formulate the learning task as variational inference by considering the unknown parameters as random variables. Then, we use two recurrent neural networks and a feedforward network as the variational autoencoder to learn an approximate posterior distribution. The first recurrent neural network is a pre-trained encoder that encodes the input into a dense representation. Then, the feedforward network transforms the representation into the posterior distribution. Finally, the second recurrent neural network receives samples from the posterior distribution to predict the mean and variance of the output. Loss functions include pretraining loss, reconstruction loss, and KL divergence loss with regard to the prior. Figure 1 gives an overview of our model.The numerical experiments show that the proposed model produces a more accurate simulation than the standard recurrent neural networks, especially when the Monte Carlo method is applied to perform multiple-step simulations. In addition, by analyzing the learned posterior distribution, we show that our approach can correctly identify the number of underlying parameters.

SpArch: Efficient Architecture for Sparse Matrix Multiplication

Generalized sparse matrix-matrix multiplication (SpGEMM) is the key computing kernel for many algorithms such as compressed deep neural networks. However, the performance of SpGEMM is memory-bounded on the traditional general-purpose computing platforms (CPU, GPU) because of the irregular memory access pattern and poor locality brought by the ex-tremely sparse matrices. For instance, the density of Twitter's adjacency matrix is as low as 0.000214%. Previous accelerator OuterSPACE proposed an outer product method that has perfect input reuse but poor output reuse due to enormous partial matrices, thus achieving only 10.4% of the theoretical peak.Therefore, we propose SpArch (HPCA'2020) to jointly optimize input and output data reuse. We obtain input reuse by using the outer product and output reuse by on-chip partial matrix merging (Figure 1).We first design a highly parallelized merger to pipeline the two computing stages, Multiply and Merge. However, the number of partial matrices can easily exceed the on-chip merger's parallelism and incurs even larger DRAM access. We thus propose a condensed matrix representation for the left input matrix, where all non-zero elements are pushed to the left, forming much denser columns and fewer partial matrices. Unfortunately, the condensed rep-resentation can still produce more partial matrices than the merger's parallelism. Since the merge order impacts DRAM access, we should merge matrices with fewer non-zeros first. To this end, we design a Huffman tree scheduler to decide the near-optimal merge order of the partial matrices. Finally, we propose a row prefetcher to prefetch rows of the right matrix and store to a row buffer, thus improving the input reuse.We evaluate SpArch on real-world datasets from SuiteSparse, SNAP, and rMAT, achieving 4×, 19×, 18×, 17×, and 1285× speedup and 6×, 164×, 435×, 307×, and 62× energy saving over OuterSPACE, MKL, cuSPARSE, CUSP and ARM Armadillo, respectively. Figure 2 shows the speedup breakdown of SpArch over OuterSPACE.

Efficient Natural Language Processing with Hardware-aware Transformers (HAT)

Transformers have been widely used in Natural Language Processing (NLP) tasks, providing a significant performance improvement over previous convolutional and recurrent models. Nevertheless, transformers cannot be easily deployed in mobile/edge devices due to their extremely high cost of computation. For instance, to translate a sentence with only 30 words, a Transformer-Big model executes 13G Mult-Adds and takes 20 seconds on Raspberry Pi 4, making real-time NLP impossible.We found two critical phenomena that impact the transformer’s efficiency: (1) FLOPs cannot reflect real latency and (2) efficient model architecture varies for different hardware. The reason is that for different hardware, the latency influencing factors differ a lot. For example, the embedding size has a large impact on Raspberry Pi but can hardly influence GPU latency.Inspired by the success of neural architecture search (NAS), we propose to search for hardware-aware transformers (HAT, ACL'2020) by directly involving hardware latency feedback in the design loop (Figure 1). Hence, we do not need FLOPs as a latency proxy and can search hardware-specific models. We first construct a large search space with two features: (1) arbitrary encoder-decoder attention to allow all decoder layers to attend to multiple and different encoder layers and (2) heterogeneous layers to let different layers have different architectures. To conduct a low-cost search, we first train a SuperTransformer, which contains many Sub-Transformers with weight-sharing. Then we perform an evolutionary search in the Super-Transformer to find the best SubTransformers under hardware latency constraints.We evaluate our HAT with three translation tasks on Raspberry pi ARM CPU, Intel CPU, and Nvidia GPU. HAT achieves up to 3× speedup and 3.7× smaller size over the conventional Transformer-Big model (Figure 2). With 10000× less search cost, HAT outperforms the Evolved Transformer with 2.7× speedup and 3.6× smaller size. Therefore, HAT enables efficient NLP on mobile devices.

Flexible Low Power CNN Accelerator for Edge Computing with Weight Tuning

Smart edge devices that support efficient neural network (NN) processing have recently gained public attention. With algorithm development, previous work has proposed small-footprint NNs achieving high performance in various medium complexity tasks, e.g. speech keyword spotting (KWS), human activity recognition (HAR), etc. Among them, convolutional NNs (CNNs) perform well, which gives rise to the deployment of CNNs on edge devices. A hardware platform for edge devices should be (1) flexible to support various NN structures optimized for different applications; (2) energy efficient to operate within the power budget; (3) achieving high accuracy to minimize spurious triggering of power-hungry downstream processing, since it is often part of a large system. This work proposes a weight tuning algorithm to improve the energy efficiency by lowering the switching activity of weight-related components, e.g. weight buses and multipliers. To achieve that, the algorithm reduces the Hamming distance between successive weights as shown in Figure 1. A flexible and runtime-reconfigurable CNN accelerator is co-designed with the algorithm. The system is fully self-contained for small CNNs. Speech keyword spotting is shown as an example with an integrated feature extraction frontend. As shown in Figure 2, a fully integrated custom ASIC is fabricated for this system. Based on post place-and-route simulation of the ASIC, the weight tuning algorithm reduces the energy consumption of weight delivery and computation by 1.70x and 1.20x respectively with little loss in accuracy.

Protonic Solid-state Electrochemical Synapse for Physical Neural Networks

Physical neural networks made of analog resistive switching processors are promising platforms for analog computing and for emulating biological synapses. State-of-the-art resistive switches rely on either conductive filament formation or phase change, processes that suffer from poor reproducibility or high energy consumption, respectively. To avoid such shortcomings, we establish an alternative synapse design (Figure 1a) that relies on a deterministic charge-controlled mechanism, modulated electrochemically in solid state, that consists of shuffling the smallest cation, the proton. This proof-of-concept, protonic solid-state electrochemical synapse is a three-terminal configuration and has a channel of active material (A), here taken as WO3. By protonation/deprotonation, we modulate the electronic conductivity of the channel over seven orders of magnitude, obtaining a continuum of resistance states (Figure 1b). A solid proton reservoir layer (R), PdHx, serves as the gate terminal. A proton conducting solid electrolyte (E), Nafion, separates the channel and the reservoir. By probing the atomic, electronic, and crystal structures (Figure 1c-d) involved during proton intercalating, we reveal an increase in the electronic conductivity of WO3 resulting from the increase of both the carrier density and the mobility. This switching mechanism has several key advantages over other switching mechanisms, in-cluding low energy dissipation and good reversibility and symmetry in programming.We are also working to improve device properties and integrability of this protonic synapse by exploring alternative materials for both the active channel and the solid-state electrolyte. On one hand, promising host materials for the intercalation of protons and multivalent ions, such as vanadium pentaoxide, graphene oxide, and tantalum pentaoxide, are being investigated as potential active materials. On the other hand, nanocrystalline yttrium-doped barium zirconate and gadolinium-doped cerium oxide are being studied as possible room-temperature fast proton conductor ceramics.

WSe2 Thin Film Solar Cells

Our group is interested in exploring the ultimate limits of microsystem scaling and functionality. The amount of energy available to the system is one of the key constraints, and solar cells based on transition metal dichalcogenides (TMDs) could be a key component of future highly-integrated microsystems.Single atomic layer TMDs have been explored extensively for ultrathin optoelectronic applications due to their direct bandgap and strong light-matter interactions. However, optoelectronic applications of multi-layer TMD thin-films have not been as extensively studied despite their strong absorption characteristics and wide absorption frequency. Nevertheless, published work has shown that a p-n junction made with chemically doped multilayer MoS2 can achieve an efficiency of 2.8%, and a vertical Schottky junction WSe2 solar cell can achieve efficiencies as high as 6.7%. Most intriguingly, it has been shown that with careful design, a 15nm WSe2 solar cell can absorb 90% of 633nm incident light, demonstrating that TMDs can push the limit of thin film photovoltaics.In this work, we study the electronic transport and photovoltaic characteristics of multilayer (~100 nm) WSe2 devices that can later be integrated as the energy harvester in a micro-scale sensing system. We have demonstrated a Schottky junction WSe2 solar cell using dissimilar metal contacts. The proof-of-concept dual-metal device showed an open-circuit voltage of ~ 0.2 V, short circuit current density ~ 4 mA/cm2 and power conversion efficiency ~ 2% under white light illumination with input power of 300 W/m2. This study is extended to explore methods to better optimize the WSe2 based solar cell using experimental and modeling techniques. We are currently developing hole and electron transport layers to improve the device efficiency.

Critical Design Parameters for Omnidirectional 2-D Filled Photonic Crystal Selective Emitter for Thermophotovoltaics

Thermophotovoltaic (TPV) systems are promising as small-scale, portable generators to power sensors, small robotic platforms, and portable computational and communication equipment. In TPV systems, an emitter at high-temperature emits radiation that is then converted to electricity by a low bandgap pho-tovoltaic cell. One approach to improve the efficiency is to use hafnia-filled two-dimensional (2-D) tantalum (Ta) photonic crystals (PhCs). These emitters enable ef-ficient spectral tailoring of thermal radiation for a wide range of incidence angles. However, fabricating these PhCs is difficult. We use focused ion beam (FIB) imaging and simulations to investigate the effects of fabrication imperfections on the emit-tance of a fabricated hafnia-filled PhC and to iden-tify design parameters critical to the overall PhC performance. We demonstrate that, more so than uniform cavity filling, the PhC performance relies on the precise cavity period and radius values and thickness of the top hafnia layer.

Low-power Management IC for Vibrational Energy Harvesting Applications

Vibration-based machine health monitoring provides an efficient real-time method for tracking the health of industrial motors, thereby achieving predictive main-tenance and avoiding machine downtime. Vibration sensors are attached to the vibrating motors, and peri-odically transmit data indicative of machine health. To power such monitors, we demonstrate a vibration-based energy harvesting system whose schematic is shown in Figure 1. It extracts power from 50Hz industrial motors and comprises a co-designed MEMS-based transducer and associated low-power management circuit.The MEMS-based energy harvester shown in Figure 1 can generate about 1 mW output power under matched load at resonance. However, its high quality-factor results in significant reduction in output power and voltage at off-resonance conditions. The system is made resilient to manufacturing variations which cause a mismatch between the harvester’s natural resonance and the motor frequency by using the interface power electronics. A Meissner oscillator circuit shown in Figure 2 is used to achieve battery-less cold-start from low harvester-voltages at off-resonance. A regular operation circuit is designed to operate once the cold-start circuit generates above-1V output voltage (Vout). This circuit employs an H-bridge to interface the harvester whose FETs are switched based on current-feedback. The load-storage element is toggled between the two ports of the harvester to synthesize the desired load-current at any frequency. The circuit thus accomplishes conjugate-impedance matching for efficient power extraction from the harvester. Further, it can tune the harvester’s source reactance to electrically shift its resonance to achieve increased bandwidth of operation.The IC implemented in the Taiwan Semiconductor Manufacturing Company (TSMC) 180nm process (shown in Figure 1) is co-designed with the harvester achieves cold-start from 150mV-peak AC-voltage from the harvester at 5% off-resonance (10x state-of-the-art). The H-bridge circuit is able to deliver 800 μW to the load at 71% efficiency at resonance as shown in Figure 2. It is also able to perform frequency tuning to account for manufacturing tolerances (A first low-power IC demonstration for this application).

Electromagnetic MEMS Harvester for Vibrational Energy Harvesting Applications

Powering machine health monitoring sensors with the motions from the machinery allows install-and-forget implementation of the machine health monitoring net-work. Electromagnetic MEMS based-transducer provides an efficient interface between industrial machines and the rest of the vibration-based energy harvesting system. Implementing the mechanical harvester’s spring system on silicon, allows the mechanical system and the circuit to be manufactured through the same process, cutting down on both assembly time and complexity.The transducer design uses a modified version of the classic 4 bar linkage spring design. The long beams are tapered such that the end connecting to the guide rod is wider than the connecting region to the shuttle, which houses the magnet (see Figure 1). This alleviates the stress experienced at the joints of the beam, which is the typical weak point of the structure. With the tapered beam, the current design achieves a full stroke of 1.6mm and is more robust with regard to handling during the assembly process. The design also offers good modal separation, with the modal frequency of the first undesirable mode several hundred Hz above the desired, horizontal translational mode. The coils are manually wound using 42 AWG enamel coated copper wires with two coils placed at 150mm above and below the magnet’s plane of motion. The coils and the spring system are each fixed in a plastic package. When attached to the source of vibration, the harvester’s magnet vibrates in between the coils, inducing an EMF in the coils in accordance with Lenz’s Law. The coils are connected in series, and the induced voltages add to produce an output voltage, which is interfaced with custom designed circuitry for energy harvesting. The assembled mechanical harvester can deliver 1mW of output power at resonance with a matched load.

Micro-buckled Beam Based Ultra-low Frequency Vibration Energy Harvester

MEMS energy harvesting has been keenly pursued to provide perpetual power for many wireless applica-tions including distributed sensor networks and up-coming IoT systems. However, scavenging a sufficient amount of power for wireless communication from environmentally available vibrations, typically at low frequency (<70Hz) and low acceleration (0.5g), has nei-ther been successful nor reported at the MEMS scale. Here we present a bi-stable buckled beam MEMS en-ergy harvester which could meet those requirements in terms of low operating frequency, wide bandwidth, and power, all packaged in the size of a coin. This new design does not rely on conventional linear or non-lin-ear resonance of the MEMS structure, but instead oper-ates with large snapping motions of buckled beams at very low frequencies. A fully functional piezoelectric device has been designed, monolithically fabricated, and tested to induce bi-stable buckling of ~200µm. The first batch device generated peak power of 85 nW with 50% half-power bandwidth under 70Hz at 0.5g.Our bi-stable nonlinear oscillator-based MEMS energy harvester has a clamped-clamped beam structure with a stack of thin-films having 28 pairs of beams 0.4mm wide in a silicon frame of 15mm×12mm. Each beam has approximately 500 interdigitated Au fingers over 0.2 µm thick PZT. A proof mass is located in the middle, connecting the beams to synchronize their out-of-plane motion and minimize undesirable torsion. Thin-film layers of various stresses have an effective total compression and balanced stress with respect to the neutral axis to achieve bi-stable buckling. The residual stress and the thickness of the thin films are monitored for each deposition step, and progressive feedback control of subsequent deposition is employed to minimize deviation from the design target. The final released device (Figure 1) shows desired bi-stable buckling of about 200µm Figure 2) which is within 5% of the designed value. The dynamic testing with a laser vibrometer validates the design concept that the buckled beam device could have large-amplitude oscillations with low-frequency and low-amplitude inputs (<70Hz and 0.5g).

RuO2 as Cathode Material of Thin Film Lithium-ion Batteries (LIB)

Technologies for the Internet of Things (IoT) are be-ing developed for a vast number of networking appli-cations. Thin film batteries are important for IoT sys-tems as they are better integrated within an integrated circuit (IC) and can store energy that is harvested by green generators (e.g., solar cells) and provide it to sen-sors. RuO2 had been found to have a larger specific ca-pacity compared to other cathode materials of lithium ion batteries (LIB), and thus, is a good candidate as a cathode material of thin film LIB. We are currently studying the reaction mechanism of RuO2 and lithium in parallel with the fabrication of full battery devices. To analyze the mechanism of lithium storage in thin film RuO2, we performed cyclic voltammetry (CV) tests with varying lower limits, as shown in Figure 1. Sur-prisingly, the lithiation process consists of 3 peaks while the delithiation process consists of 4 peaks. Moreover, the 3rd delithiation peak does not appear in sequential order relative to the other delithiation peaks. To reveal the correspondence between the peaks and specific re-actions, ex situ cross-sectional TEM, electron diffraction, Raman spectroscopy, and XPS are currently being used. In addition to characterizing the lithiation of RuO2, we have also built full battery devices that include a lithiated Si anode, a lithium phosphorous oxynitride (LiPON) electrolyte, and RuO2 cathode. Figure 2 shows the cycle performance of the microbattery at a rate of C/10. It could deliver a highly reversible capacity of approximately 150 µAh cm-2 µm-1 after 100 cycles, which is still 2.5 times higher than commercial CYMBET microbatteries. Ongoing work is focused on improving the cyclability of the RuO2 and silicon anodes through stress engineering, as well as improving the volumetric capacity through process improvements. These initial results suggest a promising route towards IC integratable batteries for on-chip power delivery.

Kinetic Study of the Reversible Lithiation in Si Thin Film Anodes

Among all the known anode materials for Li-ion batter-ies, Si is a promising candidate for applications in CMOS- compatible microbatteries. It has extraordinarily high capacities (8375 Ah/cm3, 3579 Ah/kg), which is a result of the unique alloying mechanism during lithiation that involves bond breakage and a series of formation of new short-range structures. The reversible lithiation of Si anodes (Figure 1, highlighted) has not been exten-sively studied, and there have also been debates over whether it is a diffusion process or a phase-transition process. Here we adopt the potentiostatic technique to study the reversible phase transitions that occur in the second and subsequent lithiation cycles.It was found that there is always a peak in the current vs. time curve under desirable potentiostatic test conditions in the reversible lithiation regime (Figure 2). The existence of the peak suggests there is phase transition in the reversible lithiation, rather than pure diffusion where current should decrease monotonically with time. The time at which the peak occurs (tpeak) increases with the applied potential, which indicates slower kinetics for the phase transition. Kinetic parameters could be extrapolated from the current vs. time curves upon modeling and fitting.