topic Re: How to ged rid of the Negative Slack in Timing Analysishttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/985821#M17052
<P>Hi&nbsp;<LI-USER uid="96042"></LI-USER>&nbsp;</P><P>This is the report</P><P>&nbsp;</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="LUT.JPG" style="width: 425px;"><img src="https://xlnx.i.lithium.com/t5/image/serverpage/image-id/57988iA488145FC030B8F2/image-size/large?v=1.0&amp;px=999" title="LUT.JPG" alt="LUT.JPG" /></span></P><P>&nbsp;</P><P>thank you.</P>Thu, 20 Jun 2019 05:22:39 GMTjose096212019-06-20T05:22:39ZHow to ged rid of the Negative Slackhttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/981627#M16997
<P>Hi, I'm Jose and I'm a bit new in the area of Timing Analysis.<BR />I have the next situation.  I am with a design but I have a problem of timing (Negative Slack) in the circuit I've tried to solve the problem adding D-flip-flop between the modules which the problem was reported with in the Timing Summary.  The thing is that I added the registers but the negative slack doesn´t dissapear completely (though it was reduced considerately) instead remain in other places.</P><P>&nbsp;</P><P>The remaining&nbsp; endpoints with problems are 4, as show the Fig.1 and Fig.2</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="T2.JPG" style="width: 999px;"><img src="https://xlnx.i.lithium.com/t5/image/serverpage/image-id/57360i13BC11445F2E004A/image-size/large?v=1.0&amp;px=999" title="T2.JPG" alt="T2.JPG" /></span></P><P>Fig.1.  Number of failing endpoints:4.</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="T1.JPG" style="width: 999px;"><img src="https://xlnx.i.lithium.com/t5/image/serverpage/image-id/57361iCB4DD1B8247C97F7/image-size/large?v=1.0&amp;px=999" title="T1.JPG" alt="T1.JPG" /></span></P><P>Fig.2.  Paths with timing.</P><P>The thing is that when I select the schematic of the first failed endpoint as shown in Fig.3 I notice something strange.  First, it is supposed that the module register5 (a D-FlipFlop) and the module intCounterAndConcatADC share a data bus of 4 bits, and I don´t know why appears 30:0.  Second, the dataToFIFO[92] and count_reg[4] appear within register5 but really belong to the module intCounterAndConcatADC, why?</P><P>last, How can I get rid of that negative slack?  I probed to add another register after register5 but the timing negative slack got increased.</P><P>&nbsp;</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="T3.JPG" style="width: 999px;"><img src="https://xlnx.i.lithium.com/t5/image/serverpage/image-id/57362i0CB3451A29B30254/image-size/large?v=1.0&amp;px=999" title="T3.JPG" alt="T3.JPG" /></span></P><P>Fig.3.  Path with timing,eschematic</P><P>&nbsp;</P><P>&nbsp;</P><P>Thank you</P>Sat, 08 Jun 2019 05:52:58 GMThttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/981627#M16997jose096212019-06-08T05:52:58ZRe: How to ged rid of the Negative Slackhttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/981632#M16998
<P>Hi&nbsp;<LI-USER uid="177286"></LI-USER>&nbsp;,</P><P>Please follow the below steps and check whether it helps:</P><P>route_design -unroute</P><P>place_design -unplace</P><P>place_design -directive Explore</P><P>physopt_design -directive Explore</P><P>route_design -directive Explore</P><P>And then report_timing_summary.</P><P>Thanks,</P><P>Raj</P>Sat, 08 Jun 2019 07:13:12 GMThttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/981632#M16998rshekhaw2019-06-08T07:13:12ZRe: How to ged rid of the Negative Slackhttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/981669#M17000
<P>Hi ,&nbsp;<LI-USER uid="177286"></LI-USER>&nbsp;,</P>
<P>The WNS and TNS is not large in this design and trying some different place_design directives can achieve timing with high probability.</P>
<P>For the D[30:0] bus, please check what the other logic connected on it.&nbsp;</P>Sat, 08 Jun 2019 12:26:55 GMThttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/981669#M17000hongh2019-06-08T12:26:55ZRe: How to ged rid of the Negative Slackhttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/981712#M17001
<P>thank you&nbsp;<LI-USER uid="18270"></LI-USER>&nbsp; and&nbsp;<LI-USER uid="103580"></LI-USER>&nbsp; for answer.</P><P>&nbsp;</P><P><LI-USER uid="103580"></LI-USER>&nbsp;rshekhaw&nbsp;, the method you say implies that I have to do it every time I implement that project?  for example if I join it to another bigger project I need to do the same?  is there a permanent solution?</P><P><LI-USER uid="18270"></LI-USER>&nbsp;&nbsp;, what are the directives you are saying?  in the same way, does it implies that I have to do it every time I implement that project?</P><P>thanks</P>Sat, 08 Jun 2019 23:30:16 GMThttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/981712#M17001jose096212019-06-08T23:30:16ZRe: How to ged rid of the Negative Slackhttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/981717#M17002
<P>Hi,&nbsp;<LI-USER uid="177286"></LI-USER>&nbsp;,</P>
<P>For Example, the place_design directives you can try:&nbsp;&nbsp;Explore/ExtraNetDelay_high/ExtraNetDelay_low...</P>
<P>phys_opt_design can also be added after place_design and route_design.</P>
<P>For the detailed information, you can refer to UG904.</P>
<P>It's just the effort to archive timing closure with tool's options, and you can continue to optimize your design, Ex: reduce the logic level of the critical path...&nbsp;</P>
<P>With the further optimization of the design, maybe you don't need to try so many directives next time.</P>
<P>&nbsp;</P>Sun, 09 Jun 2019 01:58:11 GMThttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/981717#M17002hongh2019-06-09T01:58:11ZRe: How to ged rid of the Negative Slackhttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/982561#M17014
<P>The negative slack is pretty small and normally the tool can resolve them.  Logic level is resonable but fanout is a little high.  Register replication may help.</P><P>What is the clock frequency?  and CLB utilization?</P>Tue, 11 Jun 2019 15:39:03 GMThttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/982561#M17014peterk2019-06-11T15:39:03ZRe: How to ged rid of the Negative Slackhttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/983773#M17036
<P><LI-USER uid="18270"></LI-USER>&nbsp; &nbsp;thank you for tell me what the common directives are and to specify the User Guide that is related with these about.</P><P><LI-USER uid="103580"></LI-USER>&nbsp;, your commands worked deleting the timing problem.  what more do you recommend to make the solution permanent?</P><P><BR /><LI-USER uid="96042"></LI-USER>&nbsp; the frequency is 500 MHz.  What is a Register application?  to segment the circuit?  I don´t know where to see the CLB utilization you are talking about.  I searched but I didn't find some ilustrating proccess to do it.  How do I see it?</P><P>&nbsp;</P><P>thank you for the help</P>Thu, 13 Jun 2019 21:43:40 GMThttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/983773#M17036jose096212019-06-13T21:43:40ZRe: How to ged rid of the Negative Slackhttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/984156#M17040
<P>500 MHz is pretty fast.  Since using explore directive works, I would just keep using that.</P><P>Register replication is duplicating registers when fanout is greater than the set amount (the default maybe 10,000).  You can do this manually in your code or set it in the synthesis options.  Becareful setting the option since this applies to the whole design.  I think the latest Vivado allows synthesis strategy apply to block level.</P><P>report_utilization will show CLB (LUTs) used in your design.</P>Fri, 14 Jun 2019 20:58:50 GMThttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/984156#M17040peterk2019-06-14T20:58:50ZRe: How to ged rid of the Negative Slackhttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/985821#M17052
<P>Hi&nbsp;<LI-USER uid="96042"></LI-USER>&nbsp;</P><P>This is the report</P><P>&nbsp;</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="LUT.JPG" style="width: 425px;"><img src="https://xlnx.i.lithium.com/t5/image/serverpage/image-id/57988iA488145FC030B8F2/image-size/large?v=1.0&amp;px=999" title="LUT.JPG" alt="LUT.JPG" /></span></P><P>&nbsp;</P><P>thank you.</P>Thu, 20 Jun 2019 05:22:39 GMThttps://forums.xilinx.com/t5/Timing-Analysis/How-to-ged-rid-of-the-Negative-Slack/m-p/985821#M17052jose096212019-06-20T05:22:39Z