Field effect transistors are common devices utilized in integrated circuitry, for example in logic circuitry, memory circuitry and control circuitry for memory circuitry.  Such devices typically comprise a pair of source/drain regions having a channel region received therebetween.  A conductive gate is provided operably proximate the channel region, and is spaced therefrom by a gate dielectric region.  Application of a suitable voltage to the conductive gate causes current flow between the source/drain regions through the channel region. 
By way of example only, the conductive material of the gate might be formed above or over semiconductive material or within openings formed in the semiconductive material, and for example whether within bulk monocrystalline substrate material or within semiconductor-on-insulator material.  When formed within trenches or other openings in semiconductive material, some of such are referred to as recessed access devices.  Here, masking material is provided over the semiconductive material of the substrate and patterned to form gate line trenches within the substrate.  With the trenches so formed, the masking material is removed, and then a gate dielectric is formed within the trench openings, for example by thermal oxidation of exposed semiconductive material within the trench.  Gate material is then deposited to overfill the trenches.  The gate material received outwardly of the trenches is then patterned, typically using photolithography and etch, to form desired gate outlines over the trenches within which the gate material is also received. 
Typically, the gate material patterning forms the gate lines over the trenches to be very close to or of the same width as the underlying trenches.  Photomask misalignment can undesirably place an edge of the desired gate line pattern within the lateral confines of the previously etched trench.  This is highly undesirable, as the gate pattern etch can etch gate material within the trench, ultimately leading to circuitry failure or at least unacceptable device configuration and performance. 
While the invention was motivated in addressing the above identified issues, it is in no way so limited.  The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents.