The present disclosure relates to cache memory, and more particularly, to cache memory and an operation method thereof. 
Cache memory is high-speed memory disposed between a processor and system memory in order to compensate an operating speed between the processor and the system memory (for example, SDRAM).  The cache memory may temporarily store instructions or data requested from the processor. 
In general, cache memory may include level-1 cache memory and level-2 cache memory.  The level-1 cache memory may be directly connected to a processor and provide fast access.  The level-2 cache memory may be positioned in a lower level of the level-1 cache memory and transmit/receive data to/from the level-1 cache memory. 
In a multi-processor system, each of a plurality of processors may be connected to a different level-1 cache memory and share one level-2 cache memory.  In this case, an issue may occur from the coherence on data stored in different level-1 cache memories.  Recently, various techniques for maintaining such data coherence are under development.