To turn off a known form of FET switching circuit of the type shown as prior art in FIG.  1 it is necessary to pull the gate down to a negative voltage, i.e., one equal to the most negative signal on the source or the analog rail on the input IN plus the pinch off voltage, -- (V + Vp).  One of the FETs is shown as a combination FET F1 + F2 to show the relationship of the known prior art switching circuit to the present invention. 
One fundamental problem with this known form of switching circuit comprising FET F3 across the analog input rail 1N and the output terminal OUT, FET F4 and FET F1 + FET F2 is that when the current is pulled down, i.e., when the switch is turned off and the gate pulled down to a negative voltage, the sum of F1 and F2 draws current and takes amounts of power.  This results from the fact that it is necessary to create a voltage drop equal to or greater than the pinch off voltage across F1 and F2.  It would be desirable to reduce the power consumption when F3 is in the off state. 
In addition, the normal manner of turning off such a FET switching circuit is with a bipolar transistor T1 coupled to the negative supply.  However, in driving current into the base of such a transistor, it stores charge in the base which results in a delay time in the turn off of the switching circuit. 
In order to turn the switch FET F3 on, i.e., to get the gate to come from a negative voltage up to the analog signal voltage on the analog signal rail IN very rapidly, it is necessary to draw large values of current through the sum of FETs F1, F2 and F4. 
With such a circuit, it is a problem to get from the off to the one state very rapidly and yet not dissipate power in the off state of the switching circuit.  Therefore, it is necessary to have a high transient current through the leg of the circuit F1, F2 and F4 and a need to discharge the capacitance on the gate of FET F3 very rapidly.