1.  Field of the Invention
The present invention relates to a thin film magnetic memory device, and particularly to a thin film magnetic memory device provided with memory cells having MTJs (Magnetic Tunnel Junctions). 
2.  Description of the Background Art
In recent years, attention has been given to a MRAM (Magnetic Random Access Memory) as a storage device, which can nonvolatilely store data with low power consumption.  The MRAM device uses a plurality of thin film magnetic elements formed in a semiconductor integrated circuit for nonvolatilely storing data, and can perform random access to the thin film magnetic elements and others. 
FIG.  15 conceptually shows a data storing principle of a memory cell having a magnetic tunnel junction, which will be merely referred to as an xe2x80x9cMTJ memory cellxe2x80x9d hereinafter. 
Referring to FIG.  15, the MTJ memory cell includes a tunneling magneto-resistance element TMR having a MR (Magneto-Resistive) effect, in which an electric resistance of a material changes depending on a direction of magnetization of a magnetic material.  As a distinctive feature, tunneling magneto-resistance element TMR can achieve a remarkable MR effect and a high MR ratio (electric resistance ratio depending on the magnetization direction) even at a room temperature. 
Tunneling magneto-resistance element TMR includes ferromagnetic material films 201 and 202 as well as an insulating film (tunneling film) 203.  In tunneling magneto-resistance element TMR, a magnitude of a tunneling current flowing through insulating film 203, which is located between ferromagnetic material films 201 and 202, changes in accordance with a direction of spin of electrons, which depends on the magnetization directions of ferromagnetic material films 201 and 202.  The number of states, which spin electrons in ferromagnetic material films 201 and 202 can enter, depends on the magnetization direction.  Therefore, the tunneling current increases when ferromagnetic material films 201 and 202 are magnetized in the same direction.  When these are magnetized in the opposite directions, respectively, the tunneling current decreases. 
This phenomenon is utilized as follows.  The magnetization direction of ferromagnetic material film 202 is switched in accordance with storage data while fixing the magnetization direction of ferromagnetic material film 201, and the magnitude of the tunneling current flowing through tunneling film 203 and thus the electric resistance of tunneling magneto-resistance element TMR are detected.  Thereby, the tunneling magneto-resistance element TMR can be used as a memory cell for storing data of one bit.  The magnetization direction of ferromagnetic material film 201 is fixed by an antiferromagnetic material or the like, and is generally referred to as a xe2x80x9cspin valvexe2x80x9d. 
In the following description, ferromagnetic material film 201 having a fixed magnetization direction may also referred to as a xe2x80x9cfixed magnetic film 201xe2x80x9d, and ferromagnetic material film 202 having a magnetization direction corresponding to the storage data may also be referred to as a xe2x80x9cfree magnetic film 202xe2x80x9d. 
For achieving a memory device having a high density, it is desired that MTJ memory cells formed of such tunneling magneto-resistance element TMRs are arranged in a two-dimensional array form.  In general, the ferromagnetic material has a direction, which allows easy magnetization owing to crystal structures, forms and others (and thus requires a low energy for magnetization), and this direction is generally referred to as an easy axis.  The magnetization direction of free magnetic film 202 corresponding to the storage data is set along this easy axis.  Conversely, the direction, in which the ferromagnetic material cannot be magnetized easily (and a high energy is required for magnetization), is referred to as a hard axis. 
FIG.  16 conceptually shows data write magnetic fields applied to the MTJ memory cell in a data write operation. 
In FIG.  16, an abscissa gives a data write magnetic field H(EA) in the direction of the easy axis, and an ordinate gives a data write magnetic field H(HA) in the direction of the hard axis.  When a vector sum of data write magnetic fields H(EA) and H(HA) reaches a region exceeding an asteroid curve 205, the magnetization direction of tunneling magneto-resistance element TMR (magnetization direction of free magnetic film 202) is rewritten into the direction of the easy axis. 
Conversely, when the data write magnetic field within the region surrounded by asteroid curve 205 is applied, the magnetization direction of tunneling magneto-resistance element TMR is not renewed, and the stored contents are nonvolatilely held. 
As shown in FIG.  16, data write magnetic field H(EA) required for the data writing is reduced by simultaneously applying data write magnetic field H(HA).  Thus, operation points 206 and 207 during the data writing are represented by vector sums of data write magnetic field H(HA) in the uniform direction not affected by the write data and data write magnetic field H(EA) in the direction corresponding to the write data.  Further, each of the data write magnetic fields H(HA) and H(EA) at operation points 206 and 207 is designed not to reach the region exceeding asteroid curve 205. 
FIG.  17 conceptually shows an arrangement of data write interconnections in the memory cell array formed of the MTJ memory cells. 
Referring to FIG.  17, the memory cell array, in which tunneling magneto-resistance elements TMR each forming the MTJ memory cell are arranged in rows and columns, is provided with data write lines 210 and 215 arranged in a grid-like form.  Each of data write lines 210 and 215 is supplied with a data write current for generating or the other of data write magnetic fields H(EA) and H(HA). 
For example, data write line 210 generates data write magnetic field H(HA), and data write line 215 generates data write magnetic field H(EA).  For this, data write line 210 is selectively supplied with the data write current in the uniform direction, and data write line 215 is selectively supplied with the data write current in the direction corresponding to the write data.  For the MTJ memory cell, which is designated as a target of data writing, corresponding data write interconnections 210 and 215 are both supplied with the data write currents. 
Therefore, the data can be selectively written into the plurality of tunneling magneto-resistance elements TMR arranged in a two-dimensional fashion by controlling supply of the data write currents to data write interconnections 210 and 215 in accordance with the address selection. 
FIG.  18 conceptually shows a structure for reading data from the MTJ memory cell. 
Structures similar to that in FIG.  18 are disclosed in technical references such as xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cellxe2x80x9d, ISSCC Digest of Technical Papers, TA7.2, February 2000, xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elementsxe2x80x9d, ISSCC Digest of Technical Papers, TA7.3, February 2000, and xe2x80x9cA 256 kb 3.0V 1T1MTJ Nonvolatile Magneto-resistive RAMxe2x80x9d, ISSCC Digest of Technical Papers, TA7.6, February 2001. 
Referring to FIG.  18, the writing of data into the MTJ memory cell, i.e., into tunneling magneto-resistance element TMR is executed, as already described, by the magnetic fields, which are generated by the data write currents flowing through a digit line DL and a bit line BL, respectively.  For example, digit line DL corresponds to data write line 210 shown in FIG.  17, and bit line BL corresponds to data write line 215. 
As an access element for reading data from tunneling magneto-resistance element TMR, the structure is provided with an access transistor ATR, which is turned on and off in accordance with a voltage on a word line WL.  Access transistor ATR is typically formed of a MOS (Metal Oxide Silicon) transistor.  One of source/drain regions of access transistor ATR is electrically coupled to tunneling magneto-resistance element TMR, and the other is coupled to a fixed voltage such as a ground voltage. 
In the data read operation, bit line BL is set to a voltage other than the above fixed voltage, and word line WL is activated to turn on access transistor ATR.  Thereby, a current corresponding to the magnetization direction of tunneling magneto-resistance element TMR, i.e., a current corresponding to the storage data can be supplied to a current path including bit line BL and tunneling magneto-resistance element TMR via access transistor ATR.  Therefore, by comparing the bit line current in this operation with a reference current, it is possible to determine whether the storage data in the MTJ memory cell formed of tunneling magneto-resistance element TMR is at an H-level or an L-level.  Since the bit line current in the data read operation is much smaller than the data write current, the current flowing in the data read operation does not change the magnetization direction of tunneling magneto-resistance element TMR.  Thus, the data reading can be performed in a nondestructive manner. 
FIG.  19 conceptually shows a conventional layout of the MTJ memory cell formed of one tunneling magneto-resistance element TMR and one access transistor. 
Referring to FIG.  19, an MTJ memory cell 10 according to a conventional layout has tunneling magneto-resistance element TMR, which is arranged at a crossing between bit BL arranged in the X direction and digit line DL arranged in the Y direction.  As will be described below, tunneling magneto-resistance element TMR is coupled to access transistor ATR, which is turned on and off in response to the voltage on word line WL arranged in the Y direction, via a contact portion 15. 
FIG.  20 is a cross section showing a structure taken along line P-Pxe2x80x2 in FIG.  19. 
Referring to FIG.  20, digit line DL is formed at a first metal interconnection layer M1.  Bit line BL is formed at a higher metal interconnection layer M2, and is coupled to tunneling magneto-resistance element TMR. 
Access transistor ATR formed on a semiconductor main substrate SUB has source/drain regions 20 and 25 as well as a substrate region 27, which is formed between source/drain regions 20 and 25, and is located immediately under a gate (word line WL).  In substrate region 27, a channel is formed corresponding to a voltage on word line WL coupled to the gate. 
Source/drain region 25 is electrically coupled to the fixed voltage, and source/drain region 20 is electrically coupled to tunneling magneto-resistance element TMR via contact portion 15.  In the following description, source/drain region 25 coupled to the fixed voltage may be merely referred to as xe2x80x9csource region 25xe2x80x9d, and source/drain region 20 coupled to tunneling magneto-resistance element TMR may be merely referred to as xe2x80x9cdrain region 20xe2x80x9d.  Access transistor ATR is isolated from the neighboring access transistor by an insulating and isolating film 30. 
FIG.  21 conceptually shows a part of the memory array, in which the MTJ memory cells shown in FIG.  19 are arranged in rows and columns. 
Referring to FIG.  21, MTJ memory cells 10 shown in FIG.  19 are arranged in rows and columns, and neighbor to each other in the X- and Y-directions.  Memory cells neighboring to each other in the X direction form groups, each of which corresponds to the memory cell row.  Memory cells neighboring to each other in the Y direction form groups, each of which corresponds to the memory cell column. 
Bit line BL is arranged in the X direction, and is coupled to each of tunneling magneto-resistance elements TMR in the memory cells belonging to the corresponding memory cell row.  Word line WL is arranged in the Y direction, and is coupled to the gate of each of access transistors in the memory cells belonging to the corresponding memory cell column.  Digit lines DL extend in the Y direction, and are arranged corresponding to the memory cell columns, respectively. 
Tunneling magneto-resistance element TMR is arranged with its longer side located in the Y direction.  Therefore, the data write current flowing through digit line DL generates a magnetic field in the direction of hard axis (HA), and the data write current flowing through bit line BL applies the data write magnetic field in the direction of easy axis (EA). 
FIG.  22 is a cross section showing structures taken along lines P-Pxe2x80x2 and Q-Qxe2x80x2 in FIG.  21.  Sections taken along lines P-Pxe2x80x2 and Q-Qxe2x80x2 are present in neighboring two memory cell rows, respectively. 
In the layout arrangement according to the prior art, MTJ memory cells 10 in each memory cell row have substantially the same structure (layout).  Thus, a coupling layout between tunneling magneto-resistance element TMR and access transistor ATR in each MTJ memory cell 10 is substantially the same as those in the other MTJ memory cells. 
As shown in FIG.  22, therefore, the P-Pxe2x80x2 section and the Qxe2x80x94Q section have substantially the same structures, and tunneling magneto-resistance elements TMR in each memory cell row are electrically coupled to access transistors ATR, which are electrically isolated from each other by insulating films 30, respectively.  The coupling relationship between tunneling magneto-resistance element TMR and access transistor ATR in each MTJ memory cell 10 is substantially the same as that shown in FIG.  20, and therefore, description thereof is not repeated. 
Word line WL for controlling on/off of access transistor ATR corresponds to a transistor gate interconnection, which extends in the Y direction through a gate layer for electrically coupling the gates of the access transistors belonging to the same memory cell column together.  Thus, each word line WL is shared by all the MTJ memory cells, which belong to the same memory cell column, and therefore neighbor to each other in the Y direction. 
In the layout arrangement according to the prior art, if the capacity of memory array increases, and the MTJ memory cells corresponding to each word line WL increase in number, a parasitic capacitance of word line WL remarkably increases.  This results in lowering of the data read speed because the voltage on word line WL cannot be changed rapidly for turning on access transistor ATR. 
A reference cell provided for generating a reference current to be compared with a passing current of the MTJ memory cell, which is designated as an access target and may also be referred to as a xe2x80x9cselected memory cellxe2x80x9d hereinafter, may be arranged in a region other than the memory array provided with the MTJ memory cells arranged in rows and columns.  In this structure, a read margin may be impaired due to influences of noises and others in the data read operation. 
An object of the invention is to provide a thin film magnetic memory device having a layout arrangement for achieving fast and accurate data reading. 
In summary, a thin film magnetic memory device according to the invention includes a plurality of memory cells, a plurality of data lines, and first and second gate interconnections.  The plurality of memory cells are arranged in rows and columns along first and second directions.  The memory cells neighboring to each other in the first direction form first groups, and the memory cells neighboring to each other in the second direction form second groups. 
The plurality of data lines are arranged in the first direction, and correspond to the first groups, respectively.  The first and second gate interconnections are arranged in the second direction, and correspond to the second groups, respectively.  Each memory cell includes a magneto-resistance element having an electric resistance variable in accordance with magnetically written storage data, and an access transistor for electrically coupling the magneto-resistance element between a fixed voltage and corresponding one among the plurality of data lines in a data read operation.  Each access transistor is turned on and off in accordance with a voltage on the one gate interconnection selected from the corresponding one first gate interconnection and the corresponding one second gate interconnection of the plurality of first and second gate interconnections and predetermined for the first group. 
Preferably, each of the memory cells has a layout inverted in the second direction with respect to that of the memory cell neighboring in the first direction. 
Accordingly, the invention can achieve such as a major advantage that interconnection capacitances of the first and second gate interconnections can be lower than those of a structure, in which one gate interconnection is shared by the memory cells neighboring to each other in the second direction.  Consequently, the access transistor in the memory cell selected as an access target can be rapidly turned on so that a data read operation can be performed fast. 
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.