The preferred embodiment of the present provides a low cost method of producing chromium masks (used in the manufacture of integrated circuits) using a methodology herein called "quantum lithography," a term coined by the inventors of the present invention.  It should be understood, however, that the methodology of quantum lithography is applicable to any masking or patterning task requiring feature edges that are positioned with high accuracy. 
As integrated circuit fabrication techniques become more sophisticated, feature sizes become ever smaller.  Manufacturing integrated circuits requires the use of several overlapping layers of masks which must be precisely positioned relative to each other to form the structure.  The positional accuracy of placement of the features on each integrated circuit mask is also extremely important. 
To make masks acceptable for use in manufacture of integrated circuits which meet the state of the art standards, especially the positional accuracy requirements, prior art system use scanning electron beam pattern generators.  These state of the art machines use interferometers to precisely position the workpiece supporting the mask blank and scan the workpiece with an electron beam in raster fashion.  The electron beam is turned on and off to expose an electron sensitive resist layer over a layer of chromium so as to define the size, shape and position of the features to be fabricated. 
Such electron beam pattern generators are very expensive.  Further, they must be employed in precisely controlled environments where temperature and humidity are controlled to very tight tolerances.  Typically temperature must be controlled to plus or minus 0.1.degree.  C. Particulates in the air must also be eliminated or substantially reduced.  Such operational environments are very expensive to build and maintain. 
Integrated circuits (hereinafter sometimes also referred to as chips or dies) are designed for many different purposes.  The number of such circuits built depends upon the application for which the circuit is designed.  For example, for a memory chip, millions may be built whereas an exotic microwave integrated circuit may have only a few hundred built.  The microwave chip will however require the same or greater precision in feature size and positional accuracy as the memory chip.  Since the cost to make a chip is related to the number made, it is apparent that making chips which require state of the art feature sizes and positional accuracy becomes impractical when a low volume of chips are to be made. 
More generally, there is a large market for low volume, application specific integrated circuits (ASICs), many of which require state of the art circuit feature sizes and positional accuracy. 
Most prior art integrate circuit processing systems use 5.times.  reticles (the terms reticles and masks are used interchangeably herein).  This means that the feature sizes on the mask will be reduced in size by a factor of five during projection of the mask image on the die.  As feature sizes become smaller and approach 0.25 microns, aberrations in the optics of the stepper machines used to project the image of the mask onto the die will prevent 5.times.  reduction from being used.  In such processes 1.times.  reticles or masks will have to be fabricated.  1.times.  reticles have feature sizes and positional accuracy identical to that which will be in the final product because no magnification or demagnification is used projecting the mask image onto the wafer.  Thus, while prior art 5.times.  masks could be defined using pattern generators with minimum feature sizes five times larger than the minimum feature sizes on the corresponding integrated circuits, in the near future 1.times.  masks will be required with minimum feature sizes equal to the minimum feature sizes on the corresponding integrated circuits.  Thus there will be a need for pattern generation equipment and methods which generate masks with dramatically smaller minimum features and which require dramatically better positional accuracy than has been required heretofore. 
Accordingly, a need has arisen for a process of making integrated circuit masks whereby state of the art feature sizes and positional accuracy may be achieved, but which is also practical for use in making masks for low production volume chips.