Digital light processing (DLP)® technology from Texas Instruments Inc. has been proven to be a viable and reliable technology for use in data and multimedia image projection systems.  The basis of the DLP technology is the Digital Micro-mirror Device (DMD) from Texas Instruments as described in U.S. Pat.  No.  5,061,049 by Hornbeck issued on Oct. 29, 1991 and incorporated herein by reference.  The DMD chip is a micro electromechanical system (MEMS) consisting of an array of bistable mirrors fabricated over a CMOS memory substrate.  Projection systems based on this technology vary in configuration and include one-chip, two-chip, and three-chip DMD designs.  Special properties of the DMD chip and the method by which light is modulated by the mirrors afford the possibility of developing a 3D stereoscopic projection system based on the DMD technology.  A 3D stereoscopic projection system has the ability to deliver left and right eye views of an image to multiple people thus creating the illusion of depth for groups of people.  The DLP based 3D stereoscopic projection system described here provides many benefits including low crosstalk between left-eye right-eye information, high brightness, low flicker, and compactness. 
Single Chip DMD Projection Systems
Single-chip projector systems utilize a single DMD (digital micro-mirror device) chip and a color wheel to display full color images.  The DMD chip reflects light passing through the color wheel either through the projection lens system onto a projection screen or back through the color wheel into the light source.  Since the DMD chip consists of thousands of tiny micro-electromechanical mirrors, the chip itself does not regulate color.  For this reason a color wheel that consists of at least three primary colors (e.g., red, green, and blue) is used to modulate the light source color.  The color is modulated at a rate faster than is discernable by the human eye, thereby causing a full color effect.  The intensity of the light that is reflected by each pixel (micro-mirror) of the DMD chip is control by a pulse-width modulation scheme.  This scheme is more fully described in “Pulse Width Modulation Control in DLP Projectors,” 115–121 TI Technical Journal, July–September 1998, by Don Doherty and Greg Hewlett and hereby incorporated by reference.  The DMD chip consists of a complicated micro-mechanical mirror system constructed over a CMOS memory substrate.  The DMD chip is described in “Digital light Processing for High Brightness, High Resolution Applications”, pg.  4 by Larry J. Hornbeck from Texas Instrument website, www.ti.com/dlp white paper section and hereby incorporated by reference.  To display a single image frame from a video or computer source on the DMD chip, mirror state information is written to the CMOS substrate of the DMD chip in blocks or groups.  Once a block of memory is written, each mirror above the block is updated to its new state.  This process continues block by block until each mirror in the chip is updated.  At the end of the frame, all mirrors on the chip are reset to the “OFF ” position at the same time.  That is, each mirror is directed to reflect light back into the optical source.  The fact that all mirrors on the DMD chip are reset to “OFF” at the end of a chip update makes the DMD chip eminently suitable as a light valve for 3D stereoscopic projection systems as explained below. 
The Mirror as a Switch
The DMD light switch 100 as illustrated in FIG.  1) is a member of a class of devices known as microelectromechanical systems (MEMS).  Other MEMS devices include pressure sensors, accelerometers, and micoractuators.  The DMD is monolithically fabricated by CMOS-like processes over a CMOS memory.  Each light switch has an aluminum mirror, 16 μm square 102 that can reflect light in one of two directions, depending on the state of the underlying memory cell.  Rotation of the mirror is accomplished through electrostatic attraction produced by voltage differences developed between the mirror and the underlying memory cell.  With the memory cell in the on (1) state, the mirror rotates to +10 degrees.  With the memory cell in the off (0) state, the mirror rotates to −10 degrees. 
By combining the DMD 202 with a suitable light source (not shown) and projection optics 204 (FIG.  2), the mirror reflects incident light either into or out of the pupil of the projection lens by a simple beam-steering technique.  Thus, the (1) state of the mirror appears bright and the (0) state of the mirror appears dark.  Compared to diffraction-based light switches, the beam-steering action of the DMD light switch provides a superior tradeoff between contrast ratio and the overall brightness efficiency of the system. 
Grayscale and Color Operation
Grayscale is achieved by binary pulse width modulation of the incident light.  Color is achieved by using color filters; either stationary or rotating, in combination with one, two, or three DMD chips
The DMD light switch is able to turn light on and off rapidly by the beam-steering action of the mirror.  As the mirror rotates, it either reflects light into or out of the pupil of the projection lens, to create a burst of digital light pulses that the eye interprets as an analog image.  The optical switching time for the DMD light switch is ˜2 microseconds.  The mechanical switching time, including the time for the mirror to settle and latch, is ˜15 μs. 
The technique for producing the sensation of grayscale to the observer's eye is called binary pulse width modulation.  The DMD accepts electrical words representing gray levels of brightness at its input and outputs optical words, which are interpreted by the eye of the observer as analog brightness levels. 
The details of the binary pulse width modulation (PWM) technique are illustrated in FIG.  3.  For simplicity, the PWM technique is illustrated for a 4-bit word (24 or 16 gray levels) 300.  Each bit in the word represents time duration for light to be on or off (1 or 0).  The time durations have relative values of 20, 21, 22, 23 or 1, 2, 4, 8.  The shortest interval (1) is called the least significant bit (LSB).  The longest interval (8) is called the most significant bit (MSB).  The video field time is divided into four time durations of 1/15, 2/15, 4/15, and 8/15 of the video field time.  The possible gray levels produced by all combinations of bits in the 4-bit word are 24 or 16 equally spaced gray levels (0, 1/15, 2/15 . . .  15/15).  Current DLP systems are either 24-bit color (8 bits or 256 gray levels per primary color) or 30-bit color (10 bits or 1024 gray levels per primary color). 
In the simple example shown in FIG.  3, spatial and temporal artifacts can be produced because of imperfect integration of the pulsed light by the viewer's eye.  These artifacts can be reduced to negligible levels by a “bit-splitting” technique.  In this technique, the longer duration bits are subdivided into shorter durations, and these split bits are distributed throughout the video field time.  SLP displays combine pulse width modulation and bit-splitting to produce a “true-analog” sensation, but with greater accuracy and stability than can be achieved by analog projection systems. 
DMD Cell Architecture and Fabrication
The DMD pixel 400 is a monolithically integrated MEMS super-structure cell fabricated over a CMOS SRAM 402 cell as illustrated in FIG.  4.  An organic sacrificial layer is removed by plasma etching to produce air gaps between the metal layers 404 of the superstructure.  The air gaps free the structure to rotate about two compliant torsion hinges 406.  The mirror 408 is rigidly connected to an underlying yoke 410.  Two thin, mechanically compliant torsion hinges to support posts that are attached to the underlying substrate, in turn, connect the yoke. 
The address electrodes 412 for the mirror and yoke are connected to the complementary sides of the underlying SRAM cell.  The yoke and mirror are connected to a bias bus fabricated at the metal-3 layer.  The bias bus 414 interconnects the yoke and mirrors of each pixel to a bond pad at the chip perimeter.  An off-chip driver supplies the bias waveform necessary for proper digital operation (Section 2.4).  The DMD mirrors are 16 μm square and made of aluminum for maximum reflectivity.  They are arrayed on 17 μm centers to form a matrix having a high fill factor (˜90%).  The high fill factor produces high efficiency for light use at the pixel level and a seamless (pixelation-free) projected image. 
Electrostatic fields are developed between the mirror and its address electrode and the yoke and its address electrode, creating an efficient electrostatic torque.  This torque works against the restoring torque of the hinges to produce mirror and yoke rotation in the positive or negative direction.  The mirror and yoke rotate until the yoke comes to rest (or lands) against mechanical stops that are at the same potential as the yoke.  Because geometry determines the rotation angle, as opposed to a balance of electrostatic torques employed in earlier analog devices, the rotation angle is precisely determined. 
The fabrication of the DMD superstructure begins with a completed CMOS memory circuit.  A thick oxide is deposited over metal-2 of the CMOS and then planarized using a chemical mechanical polish (CMP) technique.  The CMP step provides a completely flat substrate for DMD superstructure fabrication, ensuring that the projector's brightness uniformity and contrast ratio are not degraded. 
Through the use of six photo mask layers, the superstructure is formed with layers of aluminum for the address electrode (metal-3), hinge, yoke and mirror layers and hardened photoresist for the sacrificial layers (spacer-1 and spacer-2) that form the two air gaps.  The aluminum is sputter-deposited and plasma-etched using plasma-deposited SiO2 as the etch mask.  Later in the packaging flow, the sacrificial layers are plasma-ashed to form the air gaps. 
The packaging flow begins with the wafers partially sawed along the chip scribe lines to a depth that will allow the chips to be easily broken apart later.  The partially sawed and cleaned wafers then proceed to a plasma etcher that is used to selectively strip the organic sacrificial layers from under the DMD mirror, yoke, and hinges.  Following this process, a thin lubrication layer is deposited to prevent the landing tips of the yoke from adhering to the landing pads during operation.  Before separating the chips from one another, each chip is tested for full electrical and optical functionality by a high-speed automated wafer tester.  Finally, the chips are separated from the wafer, plasma-cleaned, relubricated, and hermetically sealed in a package. 
The DMD chips are packaged in two array sizes, SVGA (800×600) and SXGA (1280×1024).  The diagonals of the active area are 0.7 in. ( SVGA) and 1.1 in. ( SXGA). 
Electronic Operation
The DMD pixel is inherently a digital device because of the way it is electronically driven.  It is operated in an electrostatically bistable mode by the application of a bias voltage to the mirror to minimize the address voltage requirements.  Thus, large rotation angles can be achieved with a conventional 5-volt CMOS address circuit. 
The organization of the DMD chip is illustrated in FIG.  5.  Underlying each DMD mirror and mechanical superstructure cell is a six-transistor SRAM.  Multiple data inputs and demultiplexers (1:16) are provided to match the frequency capability of the on-chip CMOS with the required video data rates.  The pulse width modulation scheme for the DMD requires that the video field time be divided into binary time intervals or bit times.  During each bit time, while the mirrors of the array are modulating light, the underlying memory array is refreshed or updated for the next bit time.  Once the memory array has been updated, all the mirrors in the array are released simultaneously and allowed to move to their new address states. 
This simultaneous update of all mirrors, when coupled with the PWM bit-splitting algorithm described above, produces an inherently low-flicker display.  Flicker is the visual artifact that can be produced in CRTs as a result of brightness decay with time of the phosphor. 
Because CRTs are refreshed in an interlaced scan-line format, there is both a line-to-line temporal phase shift in brightness as well as an overall decay in brightness.  DLP-based displays have inherently low flicker because all pixels are updated at the same time (there is no line-to-line temporal phase shift) and because the PWM bit-splitting algorithm produces short-duration light pulses that are uniformly distributed throughout the video field time (no temporal decay in brightness). 
Proper operation of the DMD is achieved by using the bias and address sequence illustrated in FIG.  6 and detailed in Table 1. 
The bias voltage has three functions.  First, it produces a bistable condition to minimize the address voltage requirement, as previously mentioned.  In this manner, large rotation angles can be achieved with conventional 5-volt CMOS.  Second, it electromechanically latches the mirrors so that they cannot respond to changes in the address voltage until the mirrors are reset.  The third function of the bias is to reset the pixels so that they can reliably break free of surface adhesive forces and begin to rotate to their new address states. 
Although the metal surfaces of the superstructure are coated with a passivation layer or lubrication layers, the remaining van der Waal or surface forces between molecules require more than the hinge-restoring force to reliably reset the mirrors.  A reset voltage pulse applied to the mirror and yoke causes the spring tips of the yoke to flex.  As the spring tips unflex, they produce a reaction force that causes the yoke landing tips to accelerate away from the landing pads, producing a reliable release from the surface
1 Table 1.  DMD Address and Reset Sequence
                1.  Memory ready 602—All memory cells under the DMD have been loaded with the new address states for the mirrors.         2.  Reset 604—All mirrors are reset in parallel (voltage pulse applied to bias bus).         3.  Unlatch 606—The bias is turned off to unlatch mirrors and allow them to release and begin to rotate to flat state.         4.  Differentiate 608—Retarding fields are applied to the yoke and mirrors in order to rotationally separate the mirrors that remain in the same state from those that are to cross over to a new state.         5.  Land and latch 610—The bias is turned on to capture the rotationally separated mirrors and enable them to rotate to the addressed states, then settle and latch.         6.  Update memory array 612 (one line at a time)—The bias remains turned on to keep the mirrors latched so as to prevent them from responding to changes in the memory, while the memory is written with new video data.         7.  Repeat sequence beginning at step 1.DMD Structure        
As discussed above each DMD consists of thousands of tilting, microscopic, aluminum alloy mirrors.  These mirrors are mounted on a hidden yoke.  A torsion-hinge structure connects the yoke to support posts.  The torsion hinges permit mirror rotation of +10 degrees.  The support posts are connected to an underlying bias/reset bus.  The bias/reset bus is connected so that both the bias and reset voltage can be supplied to each mirror.  The mirror, hinge structure, and support posts are all formed over an underlying complementary metal oxide semiconductor (CMOS) address circuit and a pair of address electrodes
Applying voltage to one of the address electrodes in conjunction with a bias/reset voltage to the mirror structure creates an electrostatic attraction between the mirror and the addressed side.  The mirror tilts until it touches the landing electrode that is held at the same potential.  At this point, the mirror is electromechanically latched in place.  Placing a binary one in the memory cell causes the mirror to tilt +10 degrees, while a zero causes the mirror to tilt −10 degrees. 
DMDs have been built in arrays as large as 2048×1152, yielding roughly 2.3 million mirrors per device.  These devices have the capability of showing true high-definition television.  The first mass-produced DMD will be an 848×600 device.  This DMD will be capable of projecting NTSC, phase alternating line (PAL), VGA, and super video graphics adapter (SVGA) graphics, and it will also be capable of displaying 16:9 aspect ratio sources.  The video processing for a micromirror display system is more fully described in a “White Paper” entitled “Video processing for DLP™ Display System” by Vishal Markandey, Todd Clatnoff and Greg Pettitt available on the Texas Instruments web page (http://www.dlp.com/dlp/resources/whitepapers/pdf/vproc.pdf), hereby incorporated in full by reference. 
Single-Chip DMD Projection System—Example 1
FIG.  7 illustrates a typical single chip DMD projector optical design 700 by Texas Instruments as described in “From Cathode Rays To Digital Micromirrors: A History of Electronic Projection Display Technology”, Larry J. Hornbeck, pg.  40, TI Technical Journal, July–September 1998 and hereby incorporated by reference.  In this design an elliptic mirror and condenser lens 702 projects light through the color wheel 604 and into an integrator rod 706.  A second condensing lens system 108 gathers light exiting from the integrator rod 706.  Two reflecting prisms 710 and 712 are used to reflect this light onto the DMD chip 714 that, in turn, reflects light out through the projection optics 716 and onto a view screen (not shown). 
Single-Chip DMD Projection System—Example 2
FIG.  8 illustrates an alternative DMD projector configuration 200 used by Plus Corporation.  This design is simpler in that it does not utilize reflecting prisms.  In this design light passes from an elliptic mirror through a color wheel 204 and is collected by a condensing lens system.  The light is then reflected from a fixed mirror 208 up to the DMD chip 210, from whence it is reflected out through the projection optics 212 as dictated by the image being displayed. 
The designs represented by FIG.  8 and FIG.  9 are not the only possible ways in which a single chip DLP projection system can be configured.  These figures are included for illustrative purposes only and do not in any way limit the applicability of this invention to other single chip DLP configurations using a single DMD chip and a color wheel. 
Three-Segment Color Wheel for Single Chip DMD Projection Systems
FIG.  9 illustrates a three-segment color wheel configuration 900 for a single chip DLP projection system.  This wheel design consists of a wheel hub 902 and a translucent region consisting of three separate color filters, red 904, green 906, and blue 908.  DLP projection systems utilizing the three-color color wheel split each image into three separate color components that are displayed sequentially in time and that correspond to the color filters on the wheel.  In the case of a 60 Hz video source input to the projector, the image is split into its red, green, and blue components and displayed at a rate of 180 Hz. 
Four-Segment Color Wheel for Single Chip DMD Projection Systems
FIG.  10 illustrates a four-segment color wheel configuration 1000 for single chip DLP projection systems.  This wheel design enables the projector to display brighter white images by adding a clear filter 1002 to the color wheel 1004 in addition to the red 1006, green 1008, and blue 1010 color filters.  In this configuration, each primary color (red, green, and blue) subtends the same angle while the white section subtends a slightly smaller angle than the color filters. 
DMD Projector Video Processing Block Diagram for Single-Chip DLP Projector
FIG.  11 is an illustrative block diagram of the video processing system for a DLP projector as more fully described in “Video Processing for DLP® Display Systems” by Clantanoff T. Markandy and G. Pettitt from Texas Instruments website, www.ti.com/dlp, white paper section and hereby incorporated by reference.  Information flow in this diagram is from left to right.  In this illustrative system a video source input is supplied on the extreme left.  The video source 1102 can be component, composite, NTSC, Y/C, PAL, or any other video format for which the projector has been designed to receive.  The Font-End Video Processing block 1104 handles the initial conditioning and interpretation of the incoming video signal.  The most important step in this block is the conversion of the analog video signal to digital data.  Since the DMD chip is an inherently digital device, typically all video processing inside the projector is done digitally.  Another important step is the conversion of the video signal to Y/C or chrominance/luminance format. 
The second block in the video process is the Interpolation Processing block 1106.  Since DMD chip devices have a higher pixel resolution than the incoming video data (e.g., 800×600, or 1024×768 pixels wide by pixels high) the video signal must be re-sampled at the higher resolution.  Further, since many video formats are “interlaced”, that is all odd lines are displayed and then all even lines are displayed, the signal must be converted from interlaced to progressive scan.  Progressive scan means that data is displayed in the order that it comes from the top to the bottom (or vice versa) in a single scan or sweep.  Since the DMD chip is a progressive scan device a progressive scan conversion must be performed on the video signal.  Because of the way in which 3D stereoscopic images are transmitted in video signals it is possible for the Interpolation Processing block to degrade or scramble the left-eye and right-eye information carried in the video signal, depending on the algorithm implemented for the progressive scan conversion step.  This will be discussed in greater detail below. 
The final step, Back-End Processing 1108, splits the video input image or computer input image into the proper color space representation.  That is, for the wheel shown in FIG.  8, the image is split into red, green, and blue components.  For the wheel of FIG.  9 the image is split into red, green, blue, and white components.  The output of this step is color space image information acceptable by the DMD chip driver circuitry 1110. 
Dual Chip DMD Projection Systems
Dual-chip DMD projection systems are rare or non-existent in the market place.  The idea was to use two DMD display chips and a two-color color wheel to display a full color image.  The disadvantages of this system include added complexity due to the management of two DMD displays and retention of a mechanical color wheel filter system, among others. 
Three Chip DMD Projection Systems
Three-chip DMD projection systems are gaining popularity in the large projector venue market.  They consist of a complex optical prism system used to illuminate the three separate DMD display chips.  The disadvantage of these systems is the higher cost of the multiple display devices and the more complicated optics.  Advantages include the capacity for greater brightness and a reduction in complexity due to the absence of a mechanical color wheel filter. 
Existing Stereoscopic Projection Systems
Existing 3D projection systems include micropolarizer (μPol) based projection systems; dual projectors and CRT based projection systems with a Z-Screen.  Many of these are the subject of one or more patents or patent applications by the assignee of this application VRex, Inc. or its parent Reveo, Inc.
Christie and Barco Digital Three Chip Stereoscopic DLP® Projection System
Shortcomings of other projection systems and of the Christie and Barco 3D DLP projection system include the fact that the projector output is synchronized to the input.  This means that the rate at which the projector displays the sequence of left and right images is the same is the input vertical synchronization signal.  The result is that in order to reduce or eliminate flicker in the projected image, the input image source must be driven at a very high frame rate.  An advantage of the present invention over prior art systems is that the input frame rate and the output frame rate can be completely decoupled, eliminating the need for expensive high-end computer equipment required to generate the high frame-rate images. 
Off-the-Shelf Micro-Mirror Projection Systems
There are several brands of off-the-shelf DLP projection systems that have been found to support a form of “page-flipped” 3D output without any modifications.  To view stereoscopic 3D images with such projectors, a pair of liquid crystal shutter glasses may be synchronized to the video input source or to the RGB computer input source.  The major shortcoming of this solution is that the maximum input frame rate for the RGB computer input is typically 85 Hz (42.5 Hz per eye) and is not high enough to avoid noticeable flicker.  This fact is also true for the video input that is fixed at around 60 Hz (30 Hz per eye).  Another shortcoming is the fact that the flicker rate of the output is dependent on the input data frame rate. 
The Problem
The fundamental problem of stereoscopic imaging is the display of two perspective images in such a way that they appear simultaneous to an observer and in such a way that the each eye sees only the corresponding perspective image.  There are many systems in existence that provided this capability for stereo viewing by various different methods.  The problem solved by this invention is the display of high-quality 3D stereoscopic images using a digital micro-mirror based optical system.  Further, the present invention provides a means and apparatus to interpolate 3D image data from any input signal resolution to the display resolution without corruption due to the mixing of left-right perspective image data.  All major stereoscopic data formats are supported.  Further the present invention provides a system whereby 3D image decoding may be accomplished through one of three different decoding methods including passive linearly polarized eyewear, passive circularly polarized eyewear, active shutter glass eyewear or color filter based glasses.  In the preferred embodiment the user may switch between any of the 3D optical encoding methods by simply changing an external filter assembly. 
Micro-mirror display technology (such as that developed by Texas Instruments) as discussed above is well suited to stereoscopic display because of its fast switching times and extremely low persistence compared to liquid crystal based display technologies such as polysilicon, DILA™ (digital image light amplifier), and LCOS (liquid crystal on silicon).  These properties that are inherent to DMD technology help to reduce stereoscopic crosstalk (the observed light leakage between left and right perspective views) in ways that are not possible by other 3D methods.  Further, unlike some other 3D methods this invention permits the operation of the 3D projector in both stereoscopic and non-stereoscopic modes without any physical hardware or software changes required in switching between the two viewing methods.  In addition to the 3D enhancements to DMD projectors, one aspect of the invention also has the capability of enhancing the brightness of 3D projection systems.  This benefit is derived from the cholesteric liquid crystal reflective coatings used on certain color wheels variations and used as a stand-alone polarization plate.