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abstract: 'Neuromorphic systems typically use the to transmit signals among nodes, cores, and chips.  Communication of between neuromorphic cores/chips typically requires two parallel digital signal buses for operations.  This requirement can become very expensive for large-scale systems in terms of both dedicated pins and power consumption.  In this paper we present a compact fully asynchronous event-driven transmitter/receiver block that is both power efficient and efficient.  This block implements high-throughput low-latency bi-directional communication through a parallel bus.  We show that by placing the proposed transceiver block in two separate chips and linking them by a single bus, we can drive the communication and switch the transmission direction of the shared bus on a single event basis, from either side with low-latency.  We present experimental results that validate the circuits proposed and demonstrate reliable bi-directional event transmission with high-throughput.  The proposed block, integrated in a neuromorphic chip fabricated using a 28nm FDSOI process, occupies a silicon die area of 140$\mu$m $\times$ 70$\mu$m.  The experimental measurements show that the event-driven block combined with standard digital has a direction switch latency of 5ns and can achieve a worst-case bi-directional event transmission throughput of 28.6M$\cdot$Events/second while consuming 11pJ per event (26-bit) delivery.' 
author:
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title: 'A bi-directional Address-Event transceiver block for low-latency inter-chip communication in neuromorphic systems'
---

Introduction {#sec:introduction}
============

The has been widely used in brain-inspired neuromorphic systems as a communication protocol for transmitting and receiving spikes encoded as among spiking silicon neurons and synapses.  For example dynamic vision sensors [@Delbruck_etal10a] and silicon cochleas [@Liu_etal14a] use the to transmit their sensory processing outputs to neuromorphic processors and transceivers [@Park_etal14; @Merolla_etal14a; @Furber_etal14; @Qiao_etal15; @Moradi_etal17].  As these types of neuromorphic VLSI systems typically require to be transmitted with high throughput and low latency, the strategy employed to implement the communication protocol makes use of asynchronous bit-parallel channels.  This strategy however is not scalable, as the width of the parallel bus and the power required to transmit these parallel events scales with the size of the network.  In addition, the pin count and power requirements become even larger if one desires to build modular systems with north/south, east/west links necessary to tile multiple cores or chips in 2D arrays [@Merolla_etal14a; @Moradi_etal17].  Instead of simple pure parallel protocol, some approaches use a “word-serial” protocol to transmit multiple row addresses for every column address serviced (or vice-versa) to reduce pin numbers [@Boahen04; @Brandli_etal14].  Furthermore, bit-serial has been proposed as a potential solution to transmit events in a fully bit-serial format to further reduce pin numbers [@Zamarreno-Ramos_etal13a].  However, these approaches lead to significant increment in latency and overhead for the complexity of the circuit implementation.  Moreover, the design proposed in [@Zamarreno-Ramos_etal13a] needs additional clock generation and synchronization circuits which is expensive for fully asynchronous neuromorphic system. 

In this paper, we present a compact fully-asynchronous event-driven transceiver block which can be easily combined with standard digital to realize bi-directional inter-chip communication through a single parallel bus with high-throughput and low-latency.  In the next Section, we introduce architecture of the proposed transceiver block.  In Section \[sec:circuits\], we describe the circuits that implement the proposed bi-directional block.  In Section \[sec:experimental-results\] we present experimental results obtained from the measurements of a test chip fabricated in 28nm FDSOI process.  We present concluding remarks and discussion in Section \[sec:conclusions\]. 

Architecture {#sec:architecture}
============

![ Architecture of proposed bi-directional transceiver block.  SW\_Control block checks states of two linked chip and generates control signal $TX/RX\_EN$ to allow TX\_Buffer to push events on signal AER bus or allow RX\_Buffer to take events from the single AER bus.  Bi-directional tri-state buffers are switched by $TX/RX\_EN$ for bus direction.  TX/RX\_FIFOs are added to increase throughput of proposed AE transmission block.[]{data-label="fig:arch"}](arch){width="47.00000%"}

   SW\_reqL (SW\_ackR)   SW\_ackL (SW\_reqR)   Left Mode   Right Mode
  --------------------- --------------------- ----------- ------------
            0                     1               TX           RX
       $\Uparrow$                 1               TX           RX
            1               $\Downarrow$       TX$\to$RX   RX$\to$TX
            1                $\Uparrow$           RX           TX
      $\Downarrow$                1            RX$\to$TX   TX$\to$RX

  : SW\_req/ack states for mode switching []{data-label="table:code"}

![ Mode switch scheme of proposed AER in/out block for bi-directional events transmission.[]{data-label="fig:scheme"}](handshaking){width="48.00000%"}

Figure \[fig:arch\] shows the architecture of the proposed transceiver block.  Bi-directional chip communication can be implemented by connecting two transceiver blocks directly with a single shared bit-parallel AER bus.  As is shown in Fig.  \[fig:arch\], $SW\_ack$ and $SW\_req$ from two linked AE blocks are swapped and connected to announce state of each other.  The SW\_Control block in each transceiver block then checks the states of two connected chip which are indicated by $SW\_ack$ and $SW\_req$, and generates control signals $TX/RX\_EN$ to allow TX\_Buffer to push events on the shared AER bus or allow RX\_Buffer to take events from the bus.  Each AE block use $SW\_ack$ to identify its own states (i.e., logic “1” if this AE block need to switch to transmitter mode “TX” for transmitting events, and logic “0” if currently this AE block has no event to transmit and can be switched to receiver mode “RX”), and use $SW\_req$ to get states of it’s linked AE block.  SW\_Control block on both sides will generate control signals $TX\_EN$ and $RX\_EN$ to switch on/off TX\_Buffer and RX\_Buffer and alternatively map terminals of TX\_Buffer or RX\_Buffer to the shared bus for a mode switching.  Table \[table:code\] shows how modes are switched in different cases, with $\Uparrow$ representing logic “0” to “1” and $\Downarrow$ representing logic “1” to “0”. 

Moreover, conditions need to be met for a safe mode switching.  An AE transceiver block will only request a mode switching RX$\to$TX by asserting its SW\_ack $\Uparrow$ when: 1) The block is currently in a “RX” mode; 2)The block has received at least one event in “RX” mode (except that this block is initially reset to “RX” mode for a chip-level global reset); And 3) one or more events need to be transmitted.  An transceiver block will only acknowledge a mode switching request from its lined block by de-asserting its SW\_ack $\Downarrow$ when: 1) The block is currently in a “TX” mode, and 2) it received a mode switching request. 

Figure \[fig:scheme\] shows an example how bi-directional transmission is implemented with proposed AE transceiver block following 4-phase handshaking.  Assume that two AE transceiver blocks are linked by a signal AER bus, and initially we set $SW\_ackL$ of left block to logic “1” and $SW\_ackR$ of right block to logic “0”.  So that initially the left AE block is in “TX” mode and the right AE block is in “RX” mode, to allow event transmission from left to right.  Once there is an event need to be transmitted on right side, $SW\_ackR$ will be assert to “1” to request a mode switching.  After requested by $SW\_ackR$, as soon as there is no more event need to be transmitted by the left AE block, $SW\_ackL$ will be deassert to “0” to acknowledge the mode switching request.  Correspondingly, $TX/RX\_EN$ in both blocks will be flipped to complete the mode switching. 

Bi-directional tri-state buffers as shown in Fig.  \[fig:arch\] are then switched by $TX/RX\_EN$ for mapping signals of TX/RX\_Buffer blocks to shared AER bus.  We should notice that the tri-state buffers can be directly replaced with standard digital with $TX/RX\_EN$ as a configure signal for Input/Output switching.  Input and output FIFOs are added to increase throughput of proposed AE transceiver block. 

Circuits Implementation {#sec:circuits}
=======================

The proposed transceiver block is implemented following 4-phase handshaking protocol based on .  Figure \[fig:SW\_Control\] shows circuit implementation of SW\_Control block for controlling mode switching.  RX\_Probe is employed to probe whether the belonging AE block has received at least one event as a receiver ($PX\_P$ = “1”) in “RX” mode ($SW\_req$ = “1”).  TX\_Probe is used to probe whether currently the belonging AE transceiver block has no event to be transmitted ($TX\_P$ = “0”) as a transmitter in “TX” mode ($TX\_EN$ = “1”) when its linked AE transceiver block requests to switch the mode ($SW\_req \Uparrow$).  Switch Controller sub-block requests a mode switching RX$\to$TX (by asserting $SW\_ack$ to “1”) when a coming event needs to be transmitted ($TX\_in\_req$ = “1”) if its belonging AE transceiver block is currently in “RX” mode ($RX\_EN$ = “1”) and it has successfully received at least one event ($PX\_P$ = “1”) in “RX” mode.  Three NFETs in Switch Controller sub-block gated by $TX\_in\_req$, $RX\_EN$ and $PX\_P$ implement these guards.  Switch Controller block also acknowledges a mode switching request from its linked AE transceiver block for a mode switching TX$\to$RX ($SW\_req$ = “1”) if currently no event needs to be transmitted ($TX\_P$ = “0”).  Two p-FETs in Switch Controller sub-block gated by $SW\_reqB$ and $TX\_P$ implement these guards. 

As described in previous section, If the AE transceiver block requested a mode switching RX$\to$TX and its linked AE block has acknowledged this request ($SW\_ack$ = “1” $\cap$ $SW\_req$ = “0”) , this AE block will be switched to “TX” mode ($TX\_EN$ = “1”).  Otherwise, if this AE transmission block has acknowledged a mode switching TX$\to$RX requested by its linked AE block ($SW\_req$ = “1” $\cap$ $SW\_ack$ = “0”), this AE block will be switched to “RX” mode ($RX\_EN$= “1”).  In these figures, signal ends with “B” represent reversed signal.  Logic gates gated by $SRst$, $PRst$ are global reset signals used to reset TX and RX Probes to an initial state, for example, $RX\_P$ is reset to “0” for “TX” mode or “1” for “RX” mode. 

Figure \[fig:output\] shows transistor level circuit implementation of TX\_Buffer based on , following 4-phase bundled-data handshaking protocol.  The process stage includes Handshaking and Data function blocks.  Block guarantees that the process stage only deal with coming events while the linked AE transceiver block is free ($SW\_req$ = “0”).  Block checks whether the processing progress is completed to generate handshaking signal for previous process stage.  Block generates internal enable signal $en$ to enable functional processing.  Matched delay element is added to provide the worst case latency of buffer operation from valid input event data to output event.  Block implements an event buffer function. 

RX\_Buffer following 4-phase rail-rail handshaking protocol based on is shown in Fig.  \[fig:input\].  Block checks whether the processing progress is completed and generates acknowledge signal $RX\_in\_ack$ to acknowledge previous process stage for a valid input and completed valid output.  Block generates internal enable signal $en$ to enable functional processing.  Dual-rail protocol (block and ) is utilized in this RX\_Buffer and following RX\_FIFO stage for processes.  Validity check block is employed to indicate output data from this process stage is valid. 

![ Circuit implementation of SW\_Control block.  RX\_Probe and TX\_Probe are used to probe its state once it is in “RX” mode or “TX” mode.  TX/RX Switch Control generates SW\_ack signal and further generate TX/RX\_EN for its mode switch.[]{data-label="fig:SW_Control"}](SW_Control.pdf){width="48.00000%"}

![ Circuit implementation of 4-phase bundled-data TX\_Buffer based on PCHB.  The TX\_Buffer includes handshaking and data blocks. []{ data-label="fig:output"}](Controlled_Output.pdf){width="48.00000%"}

![ Circuit implementation of 4-phase dual-rail RX\_Buffer based on PCHB.  The RX\_Buffer includes handshaking, data and validity check blocks.[]{data-label="fig:input"}](Controlled_Input.pdf){width="48.00000%"}

Experimental Results {#sec:experimental-results}
====================

The proposed AE transceiver block is implemented and placed at all chip boarders of a neuromorphic chip in 28nm FDSOI process [@Qiao_Indiveri16] for implementing 2D chip-array bi-directional 26-bit communication.  Standard digital s with driven ability of 2mA are adopted and internally configured by $TX\_EN$ and $RX\_EN$ for switching event transmission direction.  As is shown in Fig.  \[fig:die\_photo\], each AE block occupies a silicon area of 140$\mu$m $\times$ 70$\mu$m.  By easily utilizing proposed AE blocks, we saved 100 s which is a significant reducing for a prototype chip with totally 180 s.

In order to judge the performance, we first measured single direction events transmission performance by continuously sending address events from single direction.  As is shown in Fig.  \[fig:experiment2\], AE transceivers from two linked chips are first reset to transmission direction from right to left.  For continuously events communing from left, AE blocks first need to switch transmission direction with a switching latency $t_{sw}$ of around 5ns.  Latency from a successfully mode switching to asserting the first request $t_{sw2req}$ is around 5ns.  For continuously single direction events transmission, latency between two requests $t_{req2req}$ is around 31ns, with a throughput of 32.3M$\cdot$Events/second. 

For bi-directional transmission, we transmitted events from both directions of two linked blocks.  As is shown in Fig.  \[fig:experiment1\], request latency of two events from two directions is around 35ns, with an achieved worst case bi-directional throughput of 28.6M$\cdot$Events/second.  Energy for delivering one 26-bit event is 11pJ at 1V power supply, excluding power consumption from digital IOs. 

A summary of the key figures of the proposed AE transceiver block is shown in Table \[table:AE\]. 

![ Neuromorphic chip implemented in 28nm FDSOI with proposed AE transceiver block combined with standard digital IOs for bi-directional inter-chip AER communication.  Each AE block occupies a silicon area of 140$\mu$m $\times$ 70$\mu$m.[]{data-label="fig:die_photo"}](die_photo_no_layout){width="47.00000%"}

![ Signal waves for continuously one-direction events transmission with a throughput of 32.3M$\cdot$Events/second.[]{data-label="fig:experiment2"}](experiment2){width="45.00000%"}

![ Signal waves for bi-directional events transmission with a throughput of 28.6M$\cdot$Events/second.[]{data-label="fig:experiment1"}](experiment1){width="45.00000%"}

  --------------------------- ------------------------------------------------
  Process Technology          28nm FDSOI
  Silicon Area                140$\mu$m $\times$ 70$\mu$m
  Throughput (with IO)        32.3MEvents/s / 28.6MEvents/s (bi-directional)
  Latency                     5ns
  Energy per Event (26-bit)   11pJ@1V
  --------------------------- ------------------------------------------------

  :  bi-directional transmission block circuit key figures.[]{data-label="table:AE"}

Conclusions {#sec:conclusions}
===========

We presented a compact low-power event-driven bi-directional transceiver block for high-throughput and low-latency bi-directional inter-chip communication.  The proposed fully asynchronous block is compatible with standard digital s for easily implementing bi-directional inter-chip communication while saving half s, comparing with normal bit-parallel protocol.  Furthermore, it is possible to combine proposed scheme with “sub-words” to further reduce numbers and power consumption.  We designed and fabricated the proposed transmission block in 28nm FDSOI process with an area of 140$\mu$m $\times$ 70$\mu$m.  Combined with standard digital s, we implemented 2D spiking neural network bi-directional chip-array communication.  Chip measurements show that the proposed transceiver block can achieve a worst case bi-directional event throughput of 28.6M$\cdot$Events/s with energy per event 11pJ at 1V supply voltage.  The latency for switching transmission direction between two AE transmission blocks is around 5ns. 

Acknowledgment {#acknowledgment .unnumbered}
==============

This work is supported by the EU ERC grant “NeuroP” (257219) and by the EU ICT grant “NeuRAM$^3$” (687299). 

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