1.  Field of the Invention
The present invention relates to a method and apparatus for handling bus data transfers.  More particularly, the invention relates to a method and apparatus for combining multiple individual data segments destined for certain types memory addresses into a group which is then transferred over a bus using a single arbitration phase. 
2.  The Background Art
Computers of all types typically comprise a motherboard and two or more circuit cards connected together through one or more sets of common lines called buses.  Common types of bus arrangements include Peripheral Component Interconnect (PCI).,  Industry Standard Architecture (ISA), VESA Local Bus (VLB) and Small Computer Systems Interface (SCSI). 
FIG.  1 depicts a prior art arrangement of computer devices which communicate using one or more buses. 
Referring to FIG.  1, CPU 10 interfaces with memory 12 and bus 14 through bridge 16.  Also coupled to bus 14 are graphics device 18, audio device 20, other device 22, and bus bridge 24.  Bus bridge 24 is coupled to a second bus 26 which may itself couple to several other devices such as bus master 28 and device 30. 
Bus 14 and bus 26 each separately comprise a common set of interconnect lines which connect their coupled devices to each other so those devices may communicate with each other.  Persons of ordinary skill in the art readily recognize that devices coupled to bus 14 may only communicate with devices coupled to bus 26 through bus bridge 24.  If two or more of devices on either bus attempt to simultaneously transfer data over the bus, a data collision results, and neither set of data being transferred arrives intact at its destination.  Thus, coupled to each bus is an arbitrator which determines which device has access to the bus at any given time. 
For the purposes of this disclosure, bus 14 represents a PCI bus, and arbitration on bus 14 is provided by circuitry within bridge 16.  Bus 26 is a second bus, and arbitration mechanism 28 may provide arbitration services for devices coupled to bus 26. 
A producer device is defined for this disclosure to be a device having data to be transferred over a bus.  Correspondingly, a consumer device shall be a device that recieves data over a bus or which is the destmation for a pending bus data transfer. 
When a producer device on either bus 14 or bus 26 requires access to the bus for a data transfer, the producer device signals the requirement for bus access to the proper arbitrator.  The arbitrator then acts on the request either by granting access to the bus, or by queuing the request so it will be acted on according to a fairness algorithm.  Details of how this arbitration actually takes place over a PCI compliant bus may be found in PCI Specification Rev. 2.1 (hereafter called "PCI specification") available from the PCI Special Interest Group, Hillsboro, Oreg. 
Computer designs which are compliant with the PCI specification have a PCI bus which allows devices to send data over the bus using a burst transfer.  A burst transfer is allowed when successive data packets to be transferred over the bus are addressed to consecutive memory addresses.  A burst transfer, after a device is granted permission by the arbitrator to transfer data, consists of a single address phase, followed by multiple data phases. 
Although many devices exist which are capable of burst transmission over a given bus, such as the PCI compliant bus discussed herein, many devices exist such as CPU 10, graphics device 18, audio device 20, other device 22, and bus bridge 24 which lack the capability to perform burst data transmissions.  These devices are able to transfer data over the bus to other devices, but must have an address phase for each data segment needing to be transferred.  In some cases, additional arbitration phases are also required. 
Any unnecessary arbitration sequences and address phases which result from single address-data phases being required use valuable time which would be better used for other operations.  In a burst transmission, only one arbitration phase is typically required, since successive data phases transfer data to consecutive memory addresses.  It would therefore be beneficial to provide a method and apparatus which collects data from devices which are not burst-capable, organizes the data destined for consecutive and increasing memory addresses so that the data may be efficently transferred, and then transferring that data across the bus using burst transmission. 
Since a burst transmission allows for higher data throughput, data awaiting transmission while stored in a memory such as a first-in, first-out (FIFO) memory remains stored for less time than if single address-data phases were required.  Thus, the cost and physical size of the apparatus may be minimized due to less storage location being required when burst transmissions are employed.