Q:

What is the wrong with my verilog code? 

i wanna write register file in verilog that is write and read data registers. 
this is my code:
module registerfile(writeaddr1,writedata1,readaddr2,readdata2,readaddr3,readdata3,write,clock);
input [4:0] writeaddr1, readaddr2, readaddr3;
input [31:0] writedata1;
output[31:0]readdata2,readdata3;
reg [31:0]readdata2,readdata3;
input write,clock;
reg [31:0] cells [0:31];
always @(posedge clock) 
begin
if (write == 1) cells[writeaddr1] =writedata1;
   readdata2 = cells[readaddr2];
    readdata3 = cells[readaddr3];
end
endmodule

and this is my test bench. 
module testreg;
  reg [3:0]addr1,addr2,addr3;
  reg [31:0]data1;
  reg write;
    wire [31:0]data2,data3;
reg clock ; //Rising edge every 10 timesteps
registerfile regf(addr1,data1,addr2,data2,addr3,data3,write,clock);
initial begin
  addr1=1;
  addr2=2;
  addr3=3;
  write=0;
  data1=32'bx;
  clock=0;
  #10
  addr1=1;
  addr2=1;
  addr3=3;
  write=1;
  data1=30;
  clock=1;
  #10
  $finish;
end
endmodule

but i don't know why data2 between 10 and 20 is xxx?  I am write 30 in that location:( 

A:

If the period of clk is 20ns, Between 0ns and 20ns first write is applied, but data2 is not the same data1, because read and write is simultaneous and when you write a value on memory, at the next clk rising edge you can read the same value from memory.  Then between 20ns and 40ns (on clk rising edge) data2 is equal to data1. 

In the module testreg size of addr1 should be [4:0] :
 reg [4:0] addr1,addr2,addr3;

As Greg said in the module registerfile it's better to use non-blocking assignments (<=) such as the following code :
always @(posedge clock) 
    if (write) begin
        cells[writeaddr1] <= writedata1;
        readdata2 <= cells[readaddr2];
        readdata3 <= cells[readaddr3];
    end

Just use the following code and continue to run simulation until 40ns :
initial begin
    addr1=1;
    data1=30;
    addr2=1;
    write=1;
end

initial begin
    clock = 0;
    forever #10 clock = ~clock;
end

I simulated your code with the above changes and could get the correct result.