This invention relates in general to voltage generation circuits and in particular, to a charge pump circuit for receiving a voltage, generating an output voltage greater than the received voltage, and providing the generated output voltage, in addition to an output current, to other circuitry in a system. 
Charge pump circuits are used in various applications such as, for example, in an electrically programmable and erasable, read-only-memory ("EEPROM").  In an EEPROM, high voltages are required to program and erase the memory cells, while a lower, logic level voltage is only required to read their programmed states.  To eliminate a high voltage input to the EEPROM, an on-chip, charge pump circuit can be included that generates the required high programing and erasing voltages from the lower, logic level voltage. 
FIG.  1 illustrates one prior art version of a charge pump circuit, wherein an output voltage generated from such a circuit can be shown to be: EQU Vout=[Vdd+n(Vclk-VT)]-VT (1)
where "VT" is the voltage drop across each diode transistor; "Vdd" is an input voltage typically supplied from an external power supply; "n" is the number of diode-capacitor stages; and "Vclk" is the voltage amplitude of the clock signals, CLK and CLKB, which is typically the same as Vdd. 
Although simple to implement, the charge pump circuit of FIG.  1 is deficient in at least three respects.  First, each stage of the circuit contributes a diode voltage drop VT, so that for n stages the cumulative voltage drop acting to reduce the output voltage adds up to n*VT.  Second, the circuit only supplies output current during one phase of the clock since the capacitors are recharged during the other phase.  Third, the isolation diode at the output of the circuit reduces the output voltage by still another diode voltage drop VT. 
FIG.  2 illustrates another prior art version of a charge pump circuit.  Although this version avoids the cumulative voltage drop, n,VT, experienced by the charge pump circuit of FIG.  1, it is still deficient in at least two respects.  First, like the charge pump circuit of FIG.  1, it only supplies output current during one phase of the clock.  Second, an isolation diode at the output of the circuit reduces the output voltage by a voltage drop VT.  The output voltage generated from this circuit can be shown to be: EQU Vout=[Vdd+n (Vdd)]-VT (2)
U.S. Pat.  No.  4,888,738, incorporated herein by reference, and co-invented by the inventor of the present invention, discloses another prior art version of a charge pump circuit which supplies current on both halves of a clock signal and eliminates the diode voltage drop VT in a first stage of the charge pump circuit, but does not disclose how to eliminate voltage drops VT contributed by subsequent stages of a charge pump circuit, nor how to eliminate a final voltage drop due to an isolation diode at the output of a charge pump circuit.