The present invention pertains to a pulse generator, and more specifically, the invention relates, particularly but not exclusively, to a pulse generator that is independent of supply voltage and useful with non-volatile semiconductor memories, the description which follows covering this field of application for convenience of explanation only. 
As is well known, a timing signal is input to non-volatile semiconductor memories in order to control the operation of a sense amplifier therein. 
In particular, the length of the timing pulse should correspond ideally to the rise time duration of the memory wordlines or rows WL, or that of the memory bitlines BL.  Thus, the sensing phases can be started in a correctly biased condition of the memory cell. 
In most memories, the rise time of the rows WL is primarily dependent on internal resistances of the memory structure, and is only marginally affected by variations in the value of the supply voltage Vdd.  This because the row driver is controlled by a fixed voltage that is generated internally and independently of the supply voltage Vdd. 
Known are circuits for generating timing signals of a pulse type whose length is jointly or separately dependent on the operating temperature T and the supply voltage Vdd. 
Shown schematically in FIG.  1 is an asymmetric delay chain 1 which is controlled by an input signal START-OF-READ1 of a pulse type.  This signal, shown in FIG.  1B, generates an output signal OUT1 which is at one time dependent on the operating temperature T and the supply voltage Vdd, as shown in FIG.  1C.
In particular, the asymmetric delay chain 1 comprises a cascade of inverters 2a, 2b, . . . ,  2n connected between a first supply voltage reference Vdd and a second voltage reference, specifically a ground GND.  The asymmetric delay chain 1 further includes a centroid node NB1 connected to the ground GND through a discharge capacitor CS1. 
The asymmetric delay chain 1 additionally includes at least a pair of resistive inverters 2kxe2x88x921 and 2k connected to said centroid node NB1. 
This prior circuit has essentially two disadvantages:
The output signal OUT1 is dependent on the value of the supply voltage Vdd; and
the dependency of the circuit operation on the operating temperature T does not correspond to the dependency on temperature of the rows WL. 
Likewise, shown respectively in FIGS.  2A, 2B and 2C are an upgraded asymmetric delay chain 3, its input signal START-OF-READ2, and its output signal OUT2. 
In particular, the upgraded asymmetric delay chain 3 comprises a cascade of inverters 4a, 4b, . . . ,  4n connected between the supply voltage reference Vdd and the ground GND, and has been produced by modifying the asymmetric delay chain 1 by the addition of an internal regulated supply voltage reference 5 effective to power a pair of resistive inverters 4kxe2x88x921 and 4k connected to a centroid node NB2, itself connected to the ground GND through a discharge capacitor CS2. 
It should be noted that this regulated voltage 5 is the same as used by the row driver. 
The output signal OUT2 provided by the upgraded asymmetric delay chain 3 is independent of the supply voltage Vdd, but is dependent on the operating temperature T.
Although achieving its objective, this solution also has drawbacks, namely:
The dependency of the circuit operation on the operating temperature T does not correspond to the dependency on temperature of the rows WL; and
the internal regulated voltage reference 5 involves increased current consumption with respect to a charge pump generating it. 
Particularly in the presence of a high supply voltage Vdd and a low temperature, the prior circuits discussed above show to be too fast, and release the sense amplifier before the row WL can be correctly biased.  By contrast, in the presence of a low supply voltage Vdd and a high temperature, they are excessively slow and detain the sense amplifier release. 
Also known are circuits that employ dummy lines to simulate the performance of the memory rows to be driven. 
The underlying technical problem of this invention is to provide a pulse generator that is independent of temperature and has such structural and finctional features as to overcome the limitations and drawbacks that beset prior art generators. 
The disclosed embodiments of the invention are directed to generating a pulse whose length is independent of the supply voltage, and whose temperature coefficient can follow the wordline rise time, the pulse being synchronized to the trailing edge of an initiating signal. 
Based on this principle, the technical problem is solved by a pulse generator that includes at least one current mirror connected between first and second voltage references and to at least one initiation terminal receiving a pulsive-type initiating signal, connected to a load terminal receiving a load signal, and connected to an output terminal providing an output signal.  The pulse generator further includes at least one logic gate having one input terminal connected to an internal control circuit node of the current mirror, having another input terminal connected to receive the initiating signal, and having an output terminal connected to the output terminal of the pulse generator; at least one regulator circuit connected between the current mirror and the second voltage reference, and connected in feedback to the output terminal; and at least one conductive-type transistor connected between the current mirror and the regulator circuit, the output terminal of the pulse generator delivering a retarded pulsive-type output signal that is independent of the supply voltage and exhibits the same dependency on temperature as the regulator circuit. 
In accordance with another aspect of the invention, a circuit is provided that comprises a pulse generator configured to generate a pulse signal, the length of which is independent of a supply voltage, and having a temperature coefficient that can follow the rise time of a memory word line, the pulse signal synchronized to a trailing edge of an initiating signal.