The prior art is replete with different versions of electronic circuits that perform specific functions, and their sizes and complexities vary widely.  One general design principle for simple circuits is minimizing the total number of constituent parts (i.e., components) utilized to form the circuit.  As most, if not all, electronic circuits are eventually implemented in tangible form as, e.g., solid-state integrated circuit chips, costs ordinarily diminish as the number of components decreases, as the chip area decreases concomitantly.  However, with individual transistor gate lengths being reduced to 0.1 μm and below, reducing the total number of process steps required to fabricate the chip can be more important than reducing the absolute number of components thereon.  Moreover, regardless of the number of devices in a circuit, the number of process steps necessary to fabricate the circuit may be minimized by limiting the number of different types of devices therein. 
FIGS.  1A and 1B depict different designs for a simple inverter circuit.  FIG.  1A depicts an inverter designed in a typical n-type metal-oxide-semiconductor (NMOS) transistor technology, i.e., utilizing only NMOS field-effect transistors (FETs).  Transistor Q1 is in a pull-up configuration and operates in a manner similar to that of a simple pull-up resistor.  When input A is in a low logic state, transistor Q2 is turned off, the output Ā is dominated by the signal voltage (depicted as +) through pull-up transistor Q1, and the output Ā is placed in a high logic state.  Conversely, when the input A is in a high logic state, transistor Q2 is turned on, the output Ā is dominated by the signal voltage through transistor Q2 to ground, and the output Ā is placed in a low logic state.  An important shortcoming of this NMOS-only inverter circuit is its significant steady-state power dissipation through pull-up transistor Q1 when the input A is high and the output Ā is low.  The power consumption (and associated heat dissipation) of more complex circuits incorporating NMOS-only inverters may be prohibitive. 
Complementary metal-oxide-semiconductor (CMOS) technology, utilizing both NMOS and p-type metal-oxide-semiconductor (PMOS) transistors, has been used to combat the above-described power dissipation issue.  FIG.  1B depicts an inverter designed in a typical CMOS technology.  PMOS transistor Q1 is in a pull-up configuration and operates in a “complementary” fashion to NMOS transistor Q2.  When the input A is in a low logic state, transistor Q1 is turned on, transistor Q2 is turned off, and the output Ā is pulled high through transistor Q1.  Conversely, when input A is in a high logic state, transistor Q1 is turned off, transistor Q2 is turned on, and the output Ā is pulled low through transistor Q2 to ground.  Since PMOS transistor Q1 and NMOS transistor Q2 are never both turned on at the same time, a steady current is never drawn through transistors Q1 and Q2, and power dissipation is minimized.  However, this advantage comes with a price.  Since fabrication of NMOS and PMOS transistors must be performed separately (as they include, e.g., different source, drain, and well doping, as well as the associated photolithography steps), the processing cost of CMOS circuits is generally much higher. 
As described above, typical low-complexity circuit designs (where the term “low-complexity” is utilized herein to refer to designs utilizing a minimum number of different types of constituent components) suffer from, e.g., high power dissipation.  Unfortunately, strategies for reducing power dissipation typically involve the introduction of higher complexity, thus increasing the processing and overall costs of integrated-circuit chips.  Accordingly, there exists a need for electronic circuit designs that both minimize power consumption and utilize a minimal number of different component types.