1.  Field of the Invention
This invention pertains broadly to the field of event sequencing devices such as those used to cause a succession of events to occur at preselected times in the future.  More particularly, the invention pertains to an event sequencer whose clock time is given by a counter chain of fast and slow speed counters.  In still greater particularity, the invention relates to an event sequencer whose clock time is provided by uninterrupted fast and slow speed counters. 
2.  Description of the Related Art
To determine the time at which an event is to be initiated, the state of a real-time, clock-driven, counter must be compared against a stored value corresponding to the time at which the scheduled event is to begin. 
If, for example, the event is to be initiated at a time resolution of four nanoseconds over an interval of 16.8 milliseconds, the counter would need at least a 22-bit counting capacity (16.8 msec.div.4 nanoseconds=2.sup.22).  For a counter of this capacity, a significant time period can be required for the counter to increment by just one count, that is, one clock pulse. 
For example, in transitioning to the next count from a count corresponding to the 21 lowest order bits set high and the remaining (most significant) bit set low, all 22 bits of the binary counter must change state.  If the time (count) of the counter is read-out before all bit changes have propagated and have switched state (jointly known as counter settling time), significant counting inaccuracy will result.  This, in turn, will result in erroneous initiation times for planned events. 
Prior art exist for reading time-on-the-fly and avoiding errors in time comparisons and event initialization.  In one technique, a suspension of counting occurs until all counter bits have settled.  This results in a "dead time" that creates a loss of count perpetuity, i.e. a loss of maintenance of absolute time, and therefore cannot be used to initiate events requiring high timing precision. 
Another technique uses a fully synchronized counter chain in which all bits change state within one clock period.  Although the read-out of this device will be relatively accurate, this approach requires that each counter module (typically of four-bits) be capable of operation at the full clock rate even though counter transitions will be occurring less and less often for higher order bits (by a factor of 2 from one bit to the next higher bit).  Utilizing this high-speed synchronized counter chain to record higher order bits results in greater dollar costs, increased power consumption, enhanced heat dissipation, higher peripheral circuit complexity and greater circuit board area.  Further, in such a chain, there are module-to-module delays which result in progressively increasing bit settling times as counter chain lengths are increased.  This results in a decreasing of the maximum event frequency at which events can be initiated. 
Another approach uses a combination of a fast synchronous counter to count low order bits and a slower and therefore less expensive and less power-consuming ripple-through or slow-counter to count high order bits.  In this design, read-out of the high order bits is delayed whenever there is a carry bit out of the fast counter stage.  This delay depends upon the maximum propagation and switching times within the slow counter stages and undesirably prevents event times from being compared during the delay.  If the capacity of the slow-speed counter is increased, the delay must be prolonged.  In either case, the delay will slow the speed at which events may be sequenced. 
There is thus a need for an event sequencer that does not experience the drawbacks of count suspension or delay while at the same time provides for rapid event sequencing, is economical, of low power, simple in design and that occupies little circuit board area.  Such features are provided by the invention disclosed herein.