1.  Technical Field
Example embodiments of the inventive concept may relate to methods of fabricating fan-out wafer level packages and/or packages formed by the methods. 
2.  Description of the Related Art
A packaging process manufacturing a semiconductor package means a series of processes that connect a semiconductor chip to external connection terminals and seal the semiconductor chip for protecting the semiconductor chip from an external impact. 
The semiconductor packages have been variously developed for purposes of small size, light weight, and low fabrication cost with the development of an electronic industry.  Additionally, as widely used in various application fields such as a digital display device, a MP3 player, a mobile phone, and a mass storage device, various kinds of semiconductor packages are proposed.  For example, the various kinds of semiconductor packages may include a ball grid array (BGA) package and a wafer level package (WLP), etc. 
The semiconductor chip may be mounted on a printed circuit board and a molding process may be performed.  And then solder balls may be bonded on a bottom surface of the printed circuit board, thereby forming the BGA package.  The BGA package positively needs the mold process.  Additionally, since the BGA package uses the printed circuit board, it is limited that a thickness of the BGA package is reduced. 
For solving the problems of the BGA package, the WLPs have been proposed.  The WLP does not need the molding process.  A redistribution line pattern may be formed on a bottom surface of the semiconductor chip and solder balls may be directly on the redistribution line pattern, thereby forming the WLP.  Thus, since the WLP does not need the molding process and the printed circuit board, a structure of the WLP may be simple and a thickness of the WLP may be reduced. 
Meanwhile, as the semiconductor chip becomes more and more integrated, a size of the semiconductor chip may become more and more reduced.  However, the intervals between the solder balls may be fixed by an international semiconductor standard.  Thus, it is difficult to bond a desired number of the solder balls to the WLP.  Additionally, as the size of the semiconductor chip becomes reduced, it is difficult to handle and test the WLP.  Furthermore, as the size of the semiconductor chip becomes reduced, it may be required to variously change a board on which the WLP is mounted. 
For solving the above problems, a fan-out WLP have been proposed.  In the fan-out WLP, a mold layer may be disposed around the semiconductor chip, the redistribution line pattern may also be formed on a bottom surface of the mold layer, and some of the solder balls may be bonded to the redistribution line pattern under the mold layer.