An NMOS transistor is a field effect transistor having N-type conductivity source and drain regions at opposite sides of a channel region of P-type conductivity.  A conductive gate is over the channel region and is insulated therefrom by a layer of an insulating material, such as silicon dioxide.  Electrostatic discharge (ESD) damage to NMOS output devices is a common occurrence in the use of integrated circuits (ICs) which include NMOS transistors.  In larger geometry devices (NMOS transistors having gate lengths of at least 1.5 micrometers) with thick gate oxides (at least 2500 nanometers in thickness), the damage is usually due to source-drain snap-back and secondary breakdown across the channel region, resulting in a short between the source and drain.  It is possible to design an NMOS output transistor to withstand a reasonable level of ESD by making use of the bipolar snap-back mechanism of the transistor.  However, failure eventually occurs because of the secondary breakdown.  As IC geometries, and gate oxide thickness shrink, the drain to gate becomes more vulnerable and can be the major weak point with regard to ESD damage.  In NMOS transistors having a gate oxide thicknesses below 1000 nanometers, the drain to gate oxide breakdown is the major failure mechanism.  This results from the necessity of designing the NMOS transistor to minimize hot carrier effects and often results in NMOS source-drain breakdown and snap-back voltage that are above the gate oxide breakdown voltage. 
A lateral NPN bipolar transistor is similar in structure to an NMOS transistor in that it comprises a pair of N-type regions spaced apart by a P-type region.  Such NPN bipolar transistors have similar problems with regard to ESD as the NMOS transistor, particularly when the width of the P-type region is very small.