This invention relates to a semiconductor memory system using a non-volatile memory capable of being electrically reprogrammed, and more specifically, to a control method for an alternative memory in a case of a failure or degradation of a memory by using a flash memory as a non-volatile memory. 
In general, a flash memory is a semiconductor memory including at most several percent of originally abnormal memory blocks which cannot be reprogrammed.  It is necessary to handle the memory so as not to use the abnormal memory blocks.  Therefore, before using the memory for reading/writing data, a format process is required.  Specifically, in the format process, characteristic data which indicates whether the memory block is normal or abnormal is read from a specific address in the block.  When the memory block is normal block which can be used, management information indicating that the memory block is normal is written in the block.  Further, when the memory block is reprogrammed 100000 times or more, the flash memory may change into an abnormal memory afterwards due to degradation.  As a result, the reprogramming for the block becomes impossible (but it is possible to read from the block).  In this case, in order to preserve the semiconductor memory system, reassignment for the block is performed.  Specifically, data stored in the abnormal block is moved to a normal block and a logical address is reassigned.  It should be noted that the normal block to be reassigned may be included in the same memory chip or another memory chip. 
JP 05-216775 A discloses a semiconductor memory system including a main flash memory, an alternative flash memory, and a write cache memory mounted thereon.  When a block which has reached the end of its life or in which a failure has occurred is detected, a storage destination is switched from the abnormal block to a block in the alternative flash memory.  The write cache memory is a RAM which functions as a write data cache for improving a write latency in the semiconductor memory system.  JP 2000-181805 A discloses a memory system including a flash memory, a processor, and a display lamp.  The processor includes means for controlling the display lamp when the remaining capacity of a reserved storage area reaches a set capacity, and notifying an operator etc.  performing maintenance of a fact that the reprogramming for the flash memory may become impossible in the near future.