Synchronizers are used to interface two digital components that are operating from unrelated clock signals.  Because the clock signals are unrelated, data transferred from one component to the other is asynchronous.  An asynchronous input introduces the potential for metastability failures.  In contrast to asynchronous inputs, synchronous inputs to a system obey strict timing relations governed by a reference such as a system clock.  For example, a synchronous input to a flip-flop changes only within a predetermined part of the system clock period.  The predetermined timing window for the change in the input is defined to ensure that the setup and hold time requirements of the flip-flop are satisfied.  The setup time defines the amount of time that a data input must be available and stable before an active clock edge.  The hold time describes the length of time that the data to be clocked into the flip-flop must remain available and stable after an active clock edge.  Because there is no fixed relationship between an asynchronous input and the clock signal the asynchronous input may violate either a set-up or hold time requirement.  When these timing requirements are violated it can put the circuit into a metastable state which is where the circuit may linger or oscillate indefinitely between two stable states.  Failures resulting from metastable behavior are particularly troublesome and mysterious because they are intermittent, random, and virtually untraceable. 
A well known approach to transferring data between two asynchronous components is to use an interface that converts the asynchronous inputs to synchronous inputs by sampling the inputs using the system clock.  This sampling process is called synchronization and the interface is known as a synchronizer.  The inherent unpredictability of the timing relationship between an asynchronous input and a clock signal has made metastability a significant recurrent problem in digital systems. 
A conventional synchronizer is illustrated in FIG.  1.  Clock domain A 110 and clock domain B 116 have independent clocks.  Data transferred from clock domain A is therefore an asynchronous input to clock domain B. Flip-flop 112 and flip-flop 114 form a synchronizer 118.  Both of the flip-flops are driven by a clock signal from the clock B domain.  The flip-flops provide a one clock period delay during which a marginal input value has the opportunity to resolve to either valid logic value as it is shifted through the synchronizer flip-flops.  However, a primary problem of the conventional synchronizer is that there remains a significant probability that the input at flip-flop 112 will violate the flip-flop 112 set-up time placing flip-flop 112 into an indeterminate state that can cause the signal to fail to be passed on to flip-flop 114. 
In a test environment, the clock domain A 110 clock signal and the clock domain B 116 signal may be derived from a single clock in the test system.  A conventional approach to transferring data across an asynchronous boundary in a test environment is to skew the clocks to minimize the likelihood of a data input violating the set-up time of a receiving device.  In a high frequency test environment the uncertainty in the timing relationship between the two clock signals may approach the clock period of the faster clock signal.  When this occurs skewing the clocks is no longer sufficient to deterministically transfer data across the asynchronous boundary.  Other synchronizers have attempted to use clock enable signals to avoid metastable states. 
Computer systems can be designed to tolerate certain types of uncertainty in asynchronous interfaces.  For example, data transfer between a CPU and a system bus may be asynchronous.  The transfer of data between the CPU and the bus may be delayed by one or more cycles due to the asynchronous interface.  The system can be designed to tolerate such variations in order to maximize the overall system operating speed.  However, in a test environment, a test machine provides an input pattern to a device and checks to see if a specific output pattern is provided.  If data is delayed non-deterministically at an asynchronous interface, the test system interprets the delay as a malfunction in the part because the output does not match the predefined output pattern at a specific point in time.  Therefore, systems that may tolerate asynchronous variations in actual operation still must conform to deterministic operation in the test environment.  In conventional systems, devices often fail high frequency testing because of a delay introduced in an asynchronous data transfer, when in fact the devices would be completely functional when run in the application system because the system is designed to accommodate non-deterministic delays in data transfer.  As a result perfectly functional devices are discarded or are sold for application at a lower frequency than they actually could be operated at. 
In view of these and other problems of conventional synchronizers, a synchronizer that provides deterministic data transfer across an asynchronous boundary in a test environment and allows for high speed performance in an application environment would be highly desirable.