It is common in current commercial products for each storage element of a flash EEPROM array to store a single bit of data by operating in a binary mode, where two ranges of threshold levels of the storage element transistors are defined as storage levels.  The threshold levels of transistors correspond to ranges of charge levels stored on their storage elements.  In addition to shrinking the size of the memory arrays, the trend is to further increase the density of data storage of such memory arrays by storing more than one bit of data in each storage element transistor.  This is accomplished by defining more than two threshold levels as storage states for each storage element transistor, four such states (2 bits of data per storage element) now being included in commercial products.  More storage states, such as 16 states per storage element, are contemplated.  Each storage element memory transistor has a certain total range (window) of threshold voltages in which it may practically be operated, and that range is divided into the number of states defined for it plus margins between the states to allow for them to be clearly differentiated from one another. 
As the number of states stored in each memory cell increases, the tolerance of any shifts in the programmed charge level on the storage elements decreases.  Since the ranges of charge designated for each storage state must necessarily be made narrower and placed closer together as the number of states stored on each memory cell storage element increases, the programming must be performed with an increased degree of precision and the extent of any post-programming shifts in the stored charge levels that can be tolerated, either actual or apparent shifts, is reduced.  Actual disturbs to the charge stored in one cell can be created when programming and reading that cell, and when reading, programming and erasing other cells that have some degree of electrical coupling with the that cell, such as those in the same column or row, and those sharing a line or node. 
Apparent shifts in the stored charge levels occur because of field coupling between storage elements.  The degree of this coupling is necessarily increasing as the sizes of memory cell arrays are being decreased, which is occurring as the result of improvements of integrated circuit manufacturing techniques.  The problem occurs most pronouncedly between two groups of adjacent cells that have been programmed at different times.  One group of cells is programmed to add a level of charge to their storage elements that corresponds to one set of data.  After the second group of cells is programmed with a second set of data, the charge levels read from the storage elements of the first group of cells often appear to be different than programmed because of the effect of the charge on the second group of storage elements being capacitively coupled with the first.  This is known as the Yupin effect, and is described in U.S. Pat.  No.  5,867,429, which patent is incorporated herein in their entirety by this reference.  This patent describes either physically isolating the two groups of storage elements from each other, or taking into account the effect of the charge on the second group of storage elements when reading that of the first group. 
In the types of memory systems described herein, as well as in others, including magnetic disc storage systems, the integrity of the data being stored is maintained by use of an error correction technique.  Most commonly, an error correction code (ECC) is calculated for each sector or other unit of data that is being stored at one time, and that ECC is stored along with the data.  The ECC is most commonly stored together with the sector of user data from which the ECC has been calculated.  When this data is read from the memory, the ECC is used to determine the integrity of the user data being read.  One or a few erroneous bits of data within a sector of data can often be corrected by use of the ECC but the existence of more errors renders the attempted data read to fail.  Thus, the existence of bits that are read incorrectly because of close field coupling with adjacent memory cells can cause an attempted data read to fail.