This application claims priority from Korean Patent Application No.  2003-74660, filed on Oct. 24, 2003, the disclosure of which is incorporated herein by reference in its entirety. 
1.  Field of the Invention
This disclosure relates to a method of fabricating a semiconductor package, and more particularly, to a method of fabricating an ultra thin flip-chip package. 
2.  Description of the Related Art
To mount a semiconductor chip on a printed circuit board (PCB), flip-chip packaging can be used.  Flip-chip packaging is a method of directly bonding a bond pad of a semiconductor chip to a PCB, and has advantages of occupying a small area and a fast operating speed. 
FIGS.  1 through 8 are sectional views illustrating a conventional method of fabricating a flip-chip package. 
Referring to FIG.  1, a semiconductor chip 17 including a bond pad 13 formed on a semiconductor substrate 11 and a passivation film pattern 15 partially exposing the bond pad 13 is prepared.  A polyimide film pattern 19 exposing an upper surface of the bond pad 13 is formed on the passivation film pattern 15.  The polyimide film pattern 19 protects the surface of the semiconductor chip 17. 
A first under barrier metal film 21 is formed on the semiconductor chip 17 and the polyimide film pattern 19.  Accordingly, a portion of the first under barrier metal film 21 is formed on the bond pad 13.  The first under barrier metal film 21 is a composite film including a titanium film and a nickel film stacked sequentially. 
Referring to FIG.  2, by forming a photoresist film on the first under barrier metal film 21 and patterning the photoresist film, a photoresist pattern 23 having a hole 22 exposing a region above the bond pad 13 is formed.  The first under barrier metal film 21 on the bond pad 13 is exposed by the photoresist pattern 23. 
Next, referring to FIG.  3, a second under barrier metal film 25 is then formed on the exposed portion of the first under barrier metal film 21.  The second under barrier metal film 25 is formed by an electroplating method in which the photoresist pattern 23 is used as an electroplating-preventing film.  The second under barrier metal film 25 is a nickel film. 
Referring to FIG.  4, a solder bump 27 is formed on the second under barrier metal film 25 so as to fill the hole 22 of the photoresist pattern 23.  The solder bump 27 is formed by an electroplating method in which the photoresist pattern 23 is used as a film for preventing an electroplating.  The solder bump 27 is formed of an alloy film composed of lead and tin. 
Referring to FIG.  5, the photoresist pattern 23 is removed.  Then, referring to FIG.  6, the first under barrier metal film 21 is etched by using the solder bump as an etch mask.  Accordingly, the first under barrier metal film 21 is disposed only below the second under barrier metal film 25. 
Referring to FIGS.  7 and 8, a water-soluble flux 29 is coated on the resultant structure to cover the solder bump 27.  Thereafter, the solder bump 27 is reflowed by a thermal process using the water-soluble flux 29, and is made in a rounded form.  Then, although not shown in the drawings, the semiconductor chip 17 on which the solder bump 27 is formed is directly bonded to a PCB (not shown), thereby completing the fabrication of the flip-chip package. 
The method of fabricating the flip-chip package in FIGS.  1 through 8 has the following drawbacks. 
First, in the conventional method, the height of the solder bump 27 should be limited to a height of 100 μm so as to permit the packaging of the semiconductor chip.  Due to this limitation, it is difficult to realize an ultra thin flip-chip package.  Also, when the solder bump is made to the height of 100 μm, the height of the photoresist pattern used as the electroplating-preventing film should be at least 70 μm, which results in an increase in the fabrication costs. 
Secondly, in the conventional method, since the increase in the integrity of a semiconductor chip requires the size of the bond pad and the height of the solder bump to be decreased, the structural reliability of the flip-chip package is lowered. 
Thirdly, in the conventional method, since a joint crack generated in the solder layer is propagated after the bonding of the solder bump and the PCB, the structural reliability of the flip-chip package is lowered. 
Fourthly, since the conventional method requires the complicated processes as illustrated in FIGS.  1 through 8, especially the reflow process of the solder bump, the flip-chip package is subject to thermal stress.