In memory systems, including those utilizing dynamic random access memory (DRAM) arrays, a precharge overhead is incurred before a target wordline is accessed.  During the precharge period, each wordline in the DRAM array is preconditioned in order to insure that only the target wordline is accessed.  However, the precharge period increases the access latency which in turn reduces the bandwidth associated with accessing data from the DRAM.  This problem is addressed in further detail below with reference to FIGS.  1 and 2. 
FIG.  1 illustrates a typical asynchronous DRAM 100 including a memory array 110, a column address buffer 112, a row address buffer 114, a refresh controller and counter 116, a column access strobe bar (CASB) clock generator 122, a row access strobe bar (RASB) clock generator 124, a data in buffer 126, a data out buffer 125, sense amplifiers and I/O gating circuits 130, a write driver 128, an I/O sense amplifier 127, a row decoder 132, and a column decoder 134.  The memory 100 operates in response to external signals provided by a controlling device 136, such as a microprocessor.  The memory 100 also provides connections for external power supply (V.sub.cc) and ground (GND) signals. 
The principle of operation of DRAMs, such as the memory 100, is well known and therefore is only briefly described herein.  The controller 136 initiates a memory operation by supplying address signals A.sub.0 -A.sub.n designating the address of a memory location where the operation is to be performed.  The addresses are clocked into the DRAM by two external strobe signals, row access strobe bar (RASB) and column access strobe bar (CASB). 
In asynchronous DRAM operation, when the RASB signal is in a low state, the memory array 110 is in an active period.  When the RASB signal is in a high state, the memory array is in a precharge period.  During the active period, the address signals are transmitted to the row decoder 132 to select a row and to activate a target word line (WL).  All the cells associated with the target word line are accessed. 
When the CASB signal is in a low state, the address signals are transmitted to the column decoder 134 in order to select the bit lines (BL) associated with a target column.  If the memory operation is a read, the bit lines are coupled to I/O sense amplifiers 127 that sense out the data stored in the corresponding cells of the row and column that are active.  If the memory operation is a write, the bit lines are coupled to write drivers 128 that write in the data which is used to program the corresponding cells of the row and column that are active.  During the precharge period, before the selected word line is deactivated, the memory cells are restored and then the bit lines are preset to the precharge state. 
Regardless of whether the memory operation is a write or a read, the row decoder 132 decodes the address signals A.sub.0 -A.sub.n and activates the word line of the row that includes the memory word that is the target of the current memory operation.  Prior to activating the word line, all word lines are precharged or reset to ground.  Then the target word line is activated.  The precharge period is used to deactivate any activated word lines before the target word line is activated thereby ensuring that only the target word line is activated.  It should be noted that in this application, the term "precharge" means resetting all the word lines to ground. 
FIG.  2 illustrates the precharge period that is incurred each time a word line is activated.  A first memory operation is performed which reads data stored in row one, columns one through three, and a second memory operation is performed which reads data stored in row two, columns four and five.  When RASB is high, each word line in the DRAM array 110 is precharged.  When RASB is low, a target word line is activated for read or write access. 
Before row one is activated, a first precharge period 140 is incurred in order to deactivate all the word lines in the DRAM array 110.  Then row one is activated in order to read out the data residing in the cells corresponding to row one, columns one through three.  Next, a second precharge period 142 is incurred in order to deactivate all the word lines, especially the word line corresponding to row one. 
The precharge overhead incurred in accessing each word line reduces the bandwidth associated with accessing data from the DRAM.  A prior art multibank DRAM memory from MoSys shows one approach to alleviate this precharge overhead.  In the MoSys DRAM, each memory bank is of a fixed size and is connected to a common bus internal to the multibank DRAM.  The address for a target bank is broadcast on the bus.  Each bank "listens" to the bus for its own address and accepts the signals intended for it. 
Each memory bank acts as an independent memory array having its own column and row decoder, control circuitry and bus interface.  The independence of each bank allows for the precharge period for one bank to be overlapped with the access of another bank.  Although this memory design is effective at reducing the overhead associated with the precharge period, it does so by requiring each memory bank to have its own control circuitry and circuitry to interface with the bus.  This increases the cost and complexity of the DRAM.