1.  Field of the Invention
The present invention relates to a semiconductor read only memory, particularly to a mask ROM (read only memory) into which information can be written at a fabrication stage. 
2.  Description of the Related Art
In recent years, semiconductor read only memories such as mask ROMs (Read Only Memories) have much finer device elements and larger memory capacity, and thus improvement in the production yield thereof becomes a prima issue.  In order to improve the production yield, various structures of mask ROMs have been proposed so far. 
One example is a mask ROM provided with an error-correcting circuit, which has already been put into practical use.  A second example is a mask R0M provided with redundant memory cells, such as conventionally employed in a RAM (Random Access Memory), etc.,  for a memory cell column (row) arranged along a bit line (a word line).  According to the second example, in cases where a defective memory cell is found in a memory cell array, the redundant memory cells are substituted for the memory cell column or row including the defective memory cell. 
The mask ROM provided with the error-correcting circuit has an advantage that the time for dealing with and repairing the defective memory cell can be shorten, but has a disadvantage that the chip area is increased by 20% or more due to additional inclusion of the error-correcting circuit and memory cells for correcting any errors. 
Moreover, such a mask ROM provided with the redundant memory cells cannot readily be put to practical use unlike a case of the RAM, etc, because not only address information but much more data information should be written into the mask ROM.  In cases where several bits of memory cells show some defect, not only information of the defective memory cell but also that of normal memory cells connected to the same line to which the defective memory cell is connected should be written into each fuse element of the mask ROM. 
Hereinafter, an exemplary structure of such a mask ROM will be described referring to FIG.  8, assuming that 1024 or more memory cells are connected to a common word line or bit line.  As is shown in FIG.  8, the mask ROM comprises a sense amplifier 40, a row decoder 60, bit lines 90, a word line i, a selection circuit 50, a substitute address storage section 20, and a substitute data storage section 21.  In cases where a defective memory cell is connected to the word line i, address information to specify the word line i is written into the substitute address storage section 20 provided with a plurality of fuse elements (not shown) by disconnecting prescribed fuse elements with radiation from laser light.  Furthermore, information from all the memory cells (1024 or more memory cells) including the defective memory cell, connected to the word line i, is written into the substitute data storage section 21 provided with a plurality of fuse elements (not shown) by disconnecting prescribed fuse elements with radiation from laser light.  As a result, if the memory cell connected to the word line i is accessed, a signal output from the substitute address storage section 20 is activated.  Accordingly, the information stored in the substitute data storage section 21 is output via the selection circuit 50. 
According to such a mask ROM, many fuse elements are inevitably disconnected with radiation from laser light, thereby substantially increasing the time needed for dealing with the laser light.  Furthermore, the production yield cannot practically be improved because the percentage of success of the disconnection by laser light is decreased or the like.  In cases where the source or drain of a transistor included in the memory cell array shows a defect, it often occurs that the other memory cells connected to the bit line to which the transistor is connected cannot be read out correctly.