Fast growth of the pervasive computing and handheld/communication industry generates exploding demand for high capacity nonvolatile solid-state data storage devices.  It is believed that nonvolatile memories, especially flash memory, will replace DRAM to occupy the biggest share of memory market.  However, flash memory has several drawbacks such as slow access speed (˜ms write and ˜50-100 ns read), limited endurance (˜103-104 programming cycles), and the integration difficulty in system-on-chip (SoC).  Flash memory (NAND or NOR) also faces significant scaling problems at 32 nm node and beyond. 
Magneto-resistive Random Access Memory (MRAM) is another promising candidate for future nonvolatile and universal memory.  MRAM features non-volatility, fast writing/reading speed (<10 ns), almost unlimited programming endurance (>1015 cycles) and zero standby power.  The basic component of MRAM is a magnetic tunneling junction (MTJ).  Data storage is realized by switching the resistance of MTJ between a high-resistance state and a low-resistance state.  MRAM switches the MTJ resistance by using a current induced magnetic field to switch the magnetization of MTJ.  As the MTJ size shrinks, the switching magnetic field amplitude increases and the switching variation becomes severer.  Hence, the incurred high power consumption limits the scaling of conventional MRAM. 
Recently, a new write mechanism, which is based upon spin polarization current induced magnetization switching, was introduced to the MRAM design.  This new MRAM design, called Spin-Transfer Torque RAM (STRAM), uses a (bidirectional) current through the MTJ to realize the resistance switching.  Therefore, the switching mechanism of STRAM is constrained locally and STRAM is believed to have a better scaling property than the conventional MRAM. 
However, a number of yield-limiting factors must be overcome before STRAM enters the production stage.  One concern in traditional STRAM design is the thickness tradeoff between of the free layer of the STRAM cell.  A thicker free layer improves the thermal stability and data retention but also increases the switching current requirement since it is proportional to the thickness of the free layer.  Thus, the amount of current required to switch the STRAM cell between resistance data states is large.