1.  Field of Invention
This invention relates to the architecture of a crossbar switch which minimizes the area required for the cross-point array and as a result also maximizes the frequency of operation and minimizes the power dissipation. 
2.  Prior Art
Prior art for crossbar switches utilizes an architecture that co-locates all of the data lines that comprise an input port or an output port together so that all data lines comprising a given port are adjacent to one of the other data lines that comprise that same input or output port.  In most semiconductor technologies including current process nodes with minimum features sizes of 45 nanometers or less, this results in sub-optimization of the area, performance and power.  This results from the fact that the interconnect spacings for the data lines often require a larger area than the area required for the cross-point array that controls the switching of all data lines associated with an input port into a particular output port.  This is not true for all crossbar switch configurations, but tends to be true for switches with wide data paths.  The area required for routing of the data lines increases as the square of the number of data lines that comprise each port.  The required number of cross points to control the connections between input and output ports increases linearly with the number of data lines that comprise each port.  Thus for any crossbar switch there will always be a data-path width for which the area required for the routing of the data-path signals exceeds the area required for the transistors used to implement the cross-points.  Furthermore if the length of the data-path signal lines can be reduced the transistors used for implementing the cross points can be made smaller, which further reduces the area required for the cross points.