Clock skew occurs when a clock signal from the same source arrives at different components at different times.  If the clock skew is too large, timing constraints such as setup and/or hold times of the circuit design may be violated. 
In an effort to avoid timing violations, some circuit design tools create balanced clock trees.  A clock tree generally distributes the same clock signal from a clock source to synchronous circuit elements (“clock loads”) of the circuit design, and in some integrated circuits (ICs), clock routing resources are configurable to establish multiple clock trees that route clocks signals from multiple clock sources.  A clock tree includes a portion of a vertical track, which may be referred to as a “spine,” and a portion(s) of a horizontal track(s) that intersects the spine.  The portion of the horizontal track may be referred to as a “branch.”  Each of the branches includes a programmable delay circuit that can be programmed with a delay value for introducing a specified amount of delay in the clock signal. 
Some circuit design tools initially create a balanced clock tree in an initial placement and configuration of clock resources for a circuit design.  A balanced clock tree has clock routing resources configured in a manner that attempts to minimize clock skew on the clock tree.  In many instances a balanced clock tree alleviates clock skew for parts of a circuit design.  However, in some instances, clock skew timing violations occur in spite of the balanced clock tree.