Modern integrated circuits incorporate a variety of design-for-test (DFT) structures to enhance their inherent testability.  The most popular DFT structure is based on scan design where a plurality of externally accessible scan chains, each comprising one or more scan cells coupled in series, are embedded into the integrated circuit.  The scan cell is a storage element comprising either a scan flip-flop or a scan latch.  Typically, scan design is used in conjunction with fault simulation and combinational ATPG (automatic test pattern generation) to generate manufacturing and diagnostic test patterns for production test, prototype debug, and yield improvement. 
It is not uncommon for many functionally fault-free manufactured devices to fail the Scan/ATPG test due to errors in scan design implementation.  A typical example is when one or more scan chains are incorrectly designed, causing hold time violations to exist between adjacent scan cells during a shift operation.  In this case, a significantly large percentage of manufactured devices are likely to fail the flush-test portion of the Scan/ATPG test.  Another example is when a scan design implementation introduces a hold time violation at the data input of a scan cell that does not exist in normal operation mode, and that is exercised during a capture operation.  This causes the scan cell to fail the deterministic-test portion of the Scan/ATPG test for a significantly large percentage of the manufactured devices due to an undesirable state, which causes test failures, being captured into the scan cell.  These scan design implementation mishaps often further result in a degradation of manufacturing yield. 
Since scan design implementation errors are often only uncovered after the devices are manufactured, it is desirable to be able to recover from such scan design implementation errors at a stage when physical design changes are no longer possible.  In a conventional Scan/ATPG approach, manufacturing yield is recovered by instructing an automatic test equipment (ATE) either to ignore comparison errors of all undesirable states in failing scan cells which are determined to be due to incorrect scan design implementation, or to completely ignore comparing all failing scan chains that are determined to be incorrectly designed. 
With the emerging popularity of design-for-test (DFT) methodologies, such as Logic BIST (built-in self-test) and Compressed Scan/ATPG, scan chains are no longer externally accessible during the test process.  In these schemes, a large number of scan chains are implemented in a design such that their scan chain inputs are controlled by a pattern generator, such as a pseudorandom pattern generator (PRPG), a random pattern generator (RPG), a broadcaster, or a decompressor, and such that their scan chain outputs are connected to a pattern compactor, such as a multiple-input signature-register (MISR) or a linear compactor.  Utilizing these pattern generators and pattern compactors during test limits the amount of scan chain debug and diagnosis that is possible, and reduces or eliminates the ability to improve yield by selectively masking off failing scan cells on an ATE.  This makes it extremely difficult to recover from any inadvertent scan design implementation errors.  This can have a dramatic effect on manufacturing yield and can force a designer to abandon the selected DFT methodology. 
Prior-art solutions to this problem tend to focus on the debug and diagnosis aspects rather than on yield improvement.  These solutions manage the interactions between scan chains and scan cell locations to be masked off using a combinational logic network that is built out of a network of AND gates.  This forces the interaction between scan chain masking and scan cell location masking to be cumulative, meaning that the masking off is the union of the two.  Three prior-art solutions are summarized below:
Prior-art #1, FIG.  2A, is described in a paper co-authored by Ghosh-Dastidar and Touba (2000).  This solution adds an output-mask network 206a, built out of a network of AND gates, between the scan core (scan chain) outputs and the inputs of the pattern compactor 207a, called MISR.  A combinational output controller is used in conjunction with a shift register 202a and a range comparator 201a to control which scan chains and scan cell locations across all scan chains should be prevented from reaching the MISR.  A scan cell location across all scan chains includes all scan cells, one from each scan chain, that appear at the scan outputs during the same cycle of the shift-out operation and are compacted in parallel into the pattern compactor.  This solution suffers from two major limitations.  The first limitation is due to the fact that a range comparator 201a is used to specify the range of scan cell locations to be masked off.  This limits the amount of flexibility this solution can offer in masking off multiple scan cell locations, forcing the user to mask off all fault-free scan cell locations in between.  The second limitation is due to the fact that it is necessary to mask off a complete scan chain or a complete scan cell location across all scan chains in order to improve yield for a single bit failure.  This dramatically reduces the circuit's fault coverage.  The limitation becomes extremely severe, further reducing the circuit's fault coverage, when multiple bit failures are spread across multiple scan chains in various scan cell locations. 
Prior-art #2, FIG.  2B, is described in U.S. Patent Application Publication US 2002/0188903 A1 by Chu et al. ( 2002).  This solution replaces the range comparator with a ring counter 201b shifting alongside the regular scan chains, allowing individual scan cell locations across all scan chains to be masked off.  However, this solution does not adequately solve the problem of being able to improve yield with minimum fault coverage loss, since it is still required to mask off a complete scan chain or a complete scan cell location across all scan chains in order to mask off a single bit failure.  Similar limitations as prior-art solution #1 also exist for multiple bit failures. 
Prior-art #3, FIG.  2C, is described in U.S. Patent Application Publication US 2003/0115521 A1 by Rajski et al. ( 2003).  This solution utilizes a selector circuit 204c similar to the output-mask network in prior-art solution #1, and a controller circuit 203c broadly defined to include any circuit capable of preventing failing scan cells from reaching the pattern compactor (MISR).  Its purpose is mainly to mask off unknown states and multiple faults from reaching the MISR during test, debug, or diagnosis, and not for yield improvement.  In all the embodiments specified by this invention, the circuitry used for masking off interactions between scan chains and scan cell locations is always implemented using a network of AND gates, similar to the combinational output controller of the previous two prior-art solutions.  Thus, this solution still suffers from the problem of having to mask off a complete scan chain or a complete scan cell location across all scan chains in order to be able to mask off multiple bit failures. 
Therefore, there is a need to extend the debug and diagnosis capabilities of current prior-art solutions to cover yield improvement.  There is a further need to extend the debug and diagnosis of the deterministic-test portion of current prior-art solutions to cover the flush-test portion as well.  Finally, there is a further need to improve upon current prior-art solutions to allow designers to recover from inadvertent scan design implementation errors, producing a manufacturing test with minimum fault coverage loss.