1.  Field of the Invention
The present invention is related to electronic circuits and more specifically to phase locked loop circuits that can be used to generate high resolution derivative frequency reference outputs. 
2.  Description of the Prior Art
A fundamental problem of phase noise exists in voltage controlled oscillators (VCO's).  Typical VCO solutions usually select on-chip ring oscillators to eliminate the need for off-chip components, but ring oscillators have higher phase noise than LC-tank type oscillators.  There are many synthesizer design tradeoffs required for high-integration receivers.  New architectures and approaches for improving phase noise and spurious tone performance in local oscillators are being investigated.  Innovations in this work have been made at several levels, including the PLL architectural level, PLL system level, and the radio architecture level. 
Frequency synthesizer design has traditionally had to tradeoff between the loop bandwidth of the PLL and the frequency spacing of the oscillator output.  A high bandwidth PLL can be used to reject ring-oscillator phase noise within the bandwidth of the PLL, but a higher bandwidth will also result in larger spurious tones.  New architectures are being explored that attempt to work around this bottleneck, e.g., doing channel selection with the second local oscillator, and allowing the first local oscillator to be fixed-frequency.  This allows the first synthesizer to use a higher loop bandwidth and maintain a locked PLL. 
Some prior art fractional synthesis techniques use phase-interpolation blocks that interpolate between phases in ring oscillators to provide a fractional divide-by ratio in the PLL feedback loop.  The result is a higher PLL loop bandwidth for a given channel spacing, and spurious tone level. 
Digitally controlled phase locked loops (PLL's) have a granularity to their frequency outputs because the steps that occur in one output frequency to the next is a function of the least significant digital divider control bit.  Vernier control to achieve a fractional part of a frequency step has not been available in PLL implementations.