1.  Field of the Invention
The present invention is related to a method of manufacturing a semiconductor device, and the device.  More specifically, the present invention relates to a technique for planarizing a film on a semiconductor substrate having a trench type element isolation structure. 
2.  Background of the Invention
A semiconductor integrated circuit needs to avoid electrical interference between elements to control them independently in operation.  For this reason, the semiconductor integrated circuit has adopted the element isolation structure having an element isolation region.  One of well-known methods for forming such a structure is a trench isolation method, to which various improvements have been proposed. 
The trench isolation method is a method for providing electrical isolation between elements by forming a trench in a substrate from the surface and filling the trench with a dielectric.  This method causes little bird's beak that is found in a structure formed by a LOCOS method, thereby reducing the area of the element isolation structure on the substrate surface as compared with the LOCOS method.  Thus, the trench isolation method is suitable for promoting downsizing of a semiconductor integrated circuit.  That is, it can be said that the method is an indispensable element isolation method for a semiconductor device which will be more downsized. 
In a manufacturing process of a downsized, multi-layer integrated circuit, with a reduction in focus margin in the photolithography process or a reduction in overetching in the etching process, it becomes important to ensure flatness of each layer formed on the substrate.  For this reason, a CMP method has been widely performed to planarize the top surface of the substrate after the trench type element isolation structure is formed. 
Before planarization by the CMP method, for the purpose of reducing polishing time and avoiding over-polishing (dishing) in a large element isolation region, dry etching is often applied to a large protrusion on the surface previous to the polishing by the CMP method.  Such preliminary planarization is hereinafter referred to as "first planarization", while the planarization by the CMP method as "second planarization".  A planarization technique which combines the first and the second planarization, can be said a simple and effective technique for high-precision planarization. 
To achieve element isolation by the trench isolation method, it is necessary to fill a narrow-opened trench with a dielectric without "key-hole" shaped cross-sectional void (seam).  One of outstanding methods to meet this requirement is a film formation method, such as an HDP-CVD (High Density Plasma-Chemical Vapor Deposition), that performs etching and deposition at the same time.  In the following description, we take the HDP-CVD method as an example. 
A film formed by the HDP-CVD method has a characteristic section shape as described later.  Thus, it is impossible to employ first planarization according to a conventional technique, as it is, that is given for planarizing a film formed by a film formation method such as a low-pressure CVD method (disclosed, for example, in Japanese Patent Laid-Open No.  9-102539).  To resolve this problem, various propositions have been made.  We will now described such propositions, referring to the drawings. 
FIGS.  21 to 28 are longitudinal cross-sectional views of a semiconductor device, showing successive stages of a method for manufacturing the device according to a first conventional technique. 
As shown in FIG.  21, a silicon substrate 101, on which (on a surface 101S) a silicon oxide film (or underlying oxide film) 102 and a silicon nitride film 103 are sequentially formed, is etched to form trenches 121A and 121C (each referred to also as a trench 121) that form element isolation regions 120A and 120C (each referred to also as an element isolation region 120), respectively.  More specifically, with a photolithography pattern used as a mask, the silicon nitride film 103 and the silicon oxide film 102 are anisotropically etched to form the trenches 121 in the silicon substrate 101 from the surface 101S to a predetermined depth.  In the drawing, regions except the element isolation regions 120 are active regions 130B and 130D (each referred to also as an active region 130).  The concept of the element isolation regions 120 and the active regions 130 includes not only a two-dimensional region on the surface 101S of the silicon substrate 101 but also a three-dimensional region in a direction perpendicular to the surface 101S of the silicon substrate 101. 
In the following drawings, when there is a necessity to distinguish between each of the element isolation regions 120 or between each of the active regions 130, an additional English alphabet is attached to the reference numeral of each region, for example, the element isolation regions 120A, 120C or the active regions 130B, 130D as shown in FIG.  21.  Similarly, the same component in each element isolation region 120 or in each active region 130 is distinguished by attaching the alphabet of each region to the reference numeral thereof. 
Next, as shown in FIG.  22, silicon oxides 111 are formed on the overall surface by the HDP-CVD method, by which the trenches 121A and 121C are filled with silicon oxides 111A and 111C, respectively.  Each of the silicon oxides 11A and 111C buried in the trenches 121A and 121C is referred to also as a "buried oxide 111", while each of silicon oxides 111B and 111D formed on the silicon nitride films 103B and 103D, respectively, is referred to also as a "silicon oxide film 111".  The silicon oxide films 111B and 111D have characteristic shapes due to the properties of film formation by the HDP-CVD method.  That is, the silicon oxide films 111 are formed to be protrusions having triangular or trapezoidal section shapes, depending on the width of the active regions 130.  The slope of such protrusions from the edges of the active regions 130 has a gradient of about 45.degree.  to the substrate surface 101S. Thus, a trapezoidal silicon oxide film 111D is formed on the silicon nitride film 103D in the active region 130D which has a width of twice the thickness of the silicon oxide film 111D.
Next, a resist is formed on the overall surface of the silicon oxides 111.  The resist is then patterned by photolithography to form a resist 141 having a pattern shown in FIG.  23.  More specifically, as shown in FIG.  23, the resist 141 is formed to cover the silicon oxides (buried oxides) 111 in all the element isolation regions 120, and the silicon oxide films 111 in the active regions 130 that range from each edge of the element isolation regions 120 to a distance equivalent to the maximum film thickness of the silicon oxide films 111 (or film thickness of the buried oxides 111).  Further, if the opening width of the resist 141 in the active region 130 is smaller than the minimum design size of the semiconductor device (e.g., the active region 130B in FIG.  23), the resist 141 is further formed on the silicon oxide film 111 in that active region. 
Then, the silicon oxide film 111 that is not covered with the resist 141 is dry etched, with the silicon nitride film 103 used as a stopper film.  That is, the silicon oxide film 111D of the maximum film thickness h on the silicon nitride film 103D is etched back.  This completes the first planarization of the silicon oxide film 111 (see FIG.  24). 
After that, the resist 141 is removed to expose the silicon oxide films 111 covered with the resist (see FIG.  25). 
Next, the exposed silicon oxide films 111 (including the remainder of the silicon oxide film 111D), shown in FIG.  25, are polished and removed by the CMP method (second planarization).  In planarization by the CMP method, a stopper film is generally provided at the end of polishing.  When a silicon oxide film is a film to be polished, a silicon nitride film having sufficiently lower polishing rate than that of the silicon oxide film is, in most cases, used as a stopper film.  That is, the silicon nitride film 103 acts as a stopper film in the second planarization.  After this planarization, there remain only the silicon oxides (buried oxides) 111 in the trenches 121 as shown in FIG.  26. 
Then, the silicon nitride films 103 are removed by thermal phosphoric acid. 
Next, a silicon oxide film is formed on the surfaces of the underlying oxide films 102 and the buried oxides 111.  The silicon oxide film is then anisotropically etched to form sidewalls 131BA, 131BC, and 131DC (each referred to also as a sidewall 131), as shown in FIG.  27, at the side walls of the buried oxides 111 that protrude above the surface of the underlying oxide films 102.  The sidewalls 131 protect the edge portions of the buried oxides 111 in the trenches 121 during hydrofluoric-acid treatment which will be described later. 
The silicon oxide films 102 and the sidewalls 131 are then removed by wet etching using hydrofluoric acid.  This forms, as shown in FIG.  28, trench or wedge type element isolations 111 comprising the silicon oxides (buried oxides) 111 buried in the trenches 121. 
The aforementioned first conventional technique has several problems as follows:
(1) First, since the maximum film thickness of the silicon oxide film 111 that remains on the silicon nitride film 103 after the first planarization, is equivalent to the height h of the buried oxides 111 or the depth h of the trenches 121, the total amount of the residual silicon oxide films 111 is extremely high.  This increases the amount to be polished by the CMP method, thereby considerably increasing the polishing time.  PA1 (2) Especially when it takes a considerable time to polish a relatively large element isolation region 111A (FIG.  25) by the CMP method, a further problem will arise.  For example, when the polishing by the CMP method is performed by the amount that depends on the residual silicon oxide film 111D of the maximum film thickness on the silicon nitride film 103D (c.f.,  FIG.  25), in regions except the active region 130D, not only the silicon oxide films 111 but also the silicon nitride films 103 which are to act as stopper films will be polished as shown in FIG.  26.  This is more likely to occur in the silicon nitride film 103 adjacent to a relatively large element isolation region 120 than in the silicon nitride film 103 in a region clustered with the active regions 130.  In this case, as shown in FIG.  27, the height of the side walls of the buried oxide 111 that protrude above the surface of the underlying oxide film 102 is reduced, so that only a low sidewall such as the sidewall 131BA is formed thereat.  Since the low sidewall 131BA fails to adequately protect the edge portion of the buried oxide 111A during the hydrofluoric-acid treatment at the ninth process, a depression 132AB is generated, as shown in FIG.  28, at the edge portion of the buried oxide 111A. PA1 (3) When an element that constitutes a semiconductor device, such as an MOSFET, is formed in the active region 130B adjacent to the depression 132AB, gate electric field will be easily concentrated at the edge portion of the active region 130B. This causes imperfections in the device characteristics: inverse narrow channel effect or hump in sub-threshold characteristics of the MOSFET.  The inverse narrow channel effect is described in detail in IEEE ELECTRON DEVICE LETTERS, VOL EDL-7, NO.  Jul. 7, 1986, pp.  419-421. 
With respect to the sub-threshold characteristics, a normal MOSFET has drain-current (Id) characteristics (sub-threshold characteristics) to a gate voltage Vd as shown in FIG.  29.  When an element isolation 111 includes the depression 132AB, however, gate electric field is concentrated at the edge portion of the active region 130B which is adjacent to the depression 132AB.  This causes hump in the sub-threshold characteristics of the MOSFET as shown in FIG.  30.  That is, the hump occurs because the threshold voltage of a parasitic MOSFET which is formed due to the depression 132AB of the buried oxide (element isolation) 111, is smaller than that of a real MOSFET. 
Next, referring to FIGS.  31 to 33, we will describe a method of manufacturing a semiconductor device according to a second conventional technique that can prevent the generation of the aforementioned depression 132AB.  FIGS.  31 to 33 are longitudinal cross-sectional views of the semiconductor device, showing successive stages of the method. 
First, as in the method of the first conventional technique, trenches 221 (221A, 221C, and 221E) forming element isolation regions 220 (220A, 220C, and 220E) are formed, as shown in FIG.  31, in a silicon substrate 201 on which (on the surface 201S) an underlying oxide film 202 and a silicon nitride film 203 are formed. 
Then, as shown in FIG.  32, silicon oxides 211 are formed inside the trenches 221 and on the silicon nitride film 203 by the HDP-CVD method as in the method of the first conventional technique. 
Further, as shown in FIG.  33, a resist 241 is formed in a predetermined region on the surface of the silicon oxides 211 as in the method of the first conventional technique.  In this manufacturing method, however, the resist 241 that extends from each edge of the element isolation regions 220 toward the adjacent active regions 230 (corresponding to a second resist portion 242 in FIG.  33) is formed within a range of a distance equivalent to an alignment margin a.
Next, as shown in FIG.  33, the silicon oxide film 211 that is not covered with the resist 241 is dry etched, with the silicon nitride film 203 used as a stopper film.  That is, the silicon oxide film 211 of the maximum film thickness h on the silicon nitride film 203 (cf.  FIG.  32) is etched back.  This completes the first planarization of the silicon oxide film 211. 
After that, as in the method of the first conventional technique, the resist 241 is removed to perform the second planarization by the CMP method.  Then, the silicon nitride films 203 is removed, and after sidewalls are formed, the silicon oxide films 202 and the sidewalls are etched to be removed.  This form trench or wedge type element isolations 211 inside the trenches 221 (see FIG.  28). 
We will now summarize the aforementioned problems (1) to (3) of the first conventional technique. 
First, since there exists a large amount of the silicon oxide film 111 to be polished as shown in FIG.  23, the second planarization requires a long processing time.  Second, since the surface shape after polishing by the CMP method depends on the asperity of the surface before polishing, the depression 132AB will be generated at the edge portion of the large element isolation region 120A as shown in FIG.  28.  Third, because of the depression 132AB, gate electric field is easily concentrated at the edge portion of the MOSFET that is formed in the active region 130B adjacent to the large element isolation region 120A. This causes inverse narrow channel effect or hump in the sub-threshold characteristics (cf.  FIG.  30), thereby causing imperfections in the device characteristics. 
These problems (1) to (3) can be solved by the second conventional technique to some extent.  That is, according to the second conventional technique, the range of the resist 241 (cf.  FIG.  33) is smaller than that of the resist 141 formed according to the first conventional technique (cf.  FIG.  24), so that more silicon oxide film 211 can be removed in the first planarization than in the first conventional technique.  This shortens the processing time of polishing by the CMP method (second planarization), resolving the problem (1).  Accordingly, the problem (2) (generation of the depression 132AB (cf.  FIG.  28)) and the problem (3) due to the depression 132AB can be suppressed. 
According to the second conventional technique, however, if etch selectivity is inappropriately set between the silicon oxide film 211 and the silicon nitride film 203 in the first planarization, not only the silicon oxide film 202 and the silicon nitride film 203 that acts as a stopper film in dry etching, but also part of the silicon substrate 201 will be etched as shown in FIG.  33 (problem (4)).  Such excessively etched portions 251D and 251F (hereinafter referred to as overetching 251D and 251F) can be often found in a region where the silicon oxide film 211 has a film thickness of less than the maximum film thickness h, and especially in the vicinity of the second resist portions 242. 
To avoid such overetching 251D and 251F, it is considered to increase the thickness of the silicon nitride films 203.  This, however, increases an aspect ratio of the trenches 221, thereby easily causing defects such as seam (cf.  FIG.  34) when the silicon oxides 211 are buried in the trenches 221.  We will describe this problem in detail, referring to FIGS.  34 and 35.  FIG.  34 is a sectional view of the semiconductor device, and FIG.  35 is a top view thereof.  FIG.  34 corresponds to a section taken along a line I--I in FIG.  35.  As shown in FIG.  34, each buried oxide 311 has a seam 380, which will be filled with a conductive material in the subsequent process.  If the conductive material remains in the seam 380, a plurality of wires 381 formed above the silicon substrate 301 will short via that conductive material as shown in FIG.  35.  Because of this, although the overetching 251D and 251F may be prevented to some extent, it has to be admitted that this technique is not appropriate for the method of manufacturing the trench type element isolation.