A typical example of the latching circuit is illustrated in FIG.  1 and largely comprises two NAND gates, two level shifters and a controller for preventing the complementary output signals from excessing a predetermined voltage level.  In detail, Q31 to Q39 and Q3a to Q3c stand for respective depletion type field effect transistors, and D31 to D32 are indicative of diodes, respectively.  C31 and C32 designate respective capacitances, and N31 to N36 are indicative of respective nodes provided in the latching circuit.  The latching circuit is accompanied with two negative voltage sources Vss1 and Vss2, and the two negative voltage sources Vss1 and Vss2 produce negative voltage levels of -1.5 volt and -3.3 volts, respectively.  These two negative voltage levels of -1.5 volt and -3.3 volts are hereinunder referred to as negative voltage levels Vss1 and Vss2, respectively.  Input signals Din1 and Din2 complementarily shifted between the high and low voltage levels are supplied to the respective first input nodes IN1 and IN2 of the two NAND gates, and a clock signal CLK is shared by the two NAND gates.  With the input signals Din1 and Din2 and the clock signal CLK.  the latching circuit produces output signals Dout1 and Dout2 complementarily shifted between the high and low voltage levels. 
For better understanding of the prior-art latching circuit, description is hereinunder made for the latching operation with reference to FIG.  2 of the drawings.  Prior to starting the latching operation ( or at time t40 ), the input signal Din1, the clock signal CLK and the output signal Dout1 remain in the low voltage levels ( or the negative voltage levels Vss1 and Vss2 ), and, accordingly, the complementary input signal Din2 and the complementary output signal Dout2 are shifted to the high voltage level ( or the ground voltage level and the negative voltage level Vss1 ).  The nodes N31 and N34 are in the low voltage level ( or the negative voltage level Vss1 ) and the high voltage level ( or the ground voltage level ), respectively. 
If the input signal Din1 goes up to the high voltage level and, accordingly, the complementary input signal is recovered to the low voltage level at time t41, no latching operation is achieved in this stage, because the clock signal CLK is not altered in the voltage level.  With the complementary input signal Din2 of the low voltage level and the clock signal CLK of the low voltage level, both of the depletion type field effect transistors Q32 and Q33 are turned off to cut off a conduction path between the negative voltage source Vss1 and the node N31.  However, the depletion type field effect transistor Q34 is turned on to provide a conduction path between the negative voltage level Vss1 and the node N31, because the complementary output signal of the high voltage level is supplied to the gate electrode thereof, thereby allowing the depletion type field effect transistor Q35 to be turned off.  Then, the depletion type field effect transistor Q35 remains in the off-state, and, accordingly, the output signal Dout1 of the low voltage level continues to be produced on the basis of the negative voltage level Vss2.  On the other hand, the node N34 is kept in the high voltage level due to the depletion type field effect transistors Q38 and Q3a in the respective off states, and, for this reason, the depletion type field effect transistor Q3b is turned on to produce the output signal of the high voltage level. 
At time t42, the clock signal CLK is shifted from the low voltage level to the high voltage level, then both of the depletion type field effect transistors Q32 and Q38 turn on, thereby allowing the node N34 to go down toward the low voltage level.  The node N34 reaches the low voltage level at time t43 to cause the depletion type field effect transistor Q3b to turn off, however, the complementary output signal Dout2 reaches the low voltage level at time t45 due to the accumulation of the negative charges to the capacitor C32. 
When the complementary output signal Dout2 is lowered under the threshold level of the depletion type field effect transistor Q34 ( or at time t44 ), the node N31 goes up to the high voltage level, and, for this reason, the depletion type field effect transistor turns on to allow the capacitor C31 to discharge the accumulated negative charges.  As a result, the output signal Dout1 reaches the high voltage level at time t46.  After the output signals Dout1 and Dout2 are respectively shifted in the voltage level, the clock signal CLK is recovered to the low voltage level at time t47, and the latching operation is completed. 
A problem is encountered in the prior-art latching circuit in prompt response to the alternation of the input signals Din1 and Din2.  THis is because of the fact the depletion type field effect transistors Q34 and Q3a are incorporated in the prior-art latching circuit for preventing the output signal Dout1 or Dout2 from the insufficient negative voltage level.  The depletion type field effect transistors Q34 and Q3a are shifted in series due to accumulation of the negative charges to one of the capacitors followed by discharging the other capacitor, and, as a result, a prolonged time period is consumed from alternation of the clock signal ( or time t42 ) to the completion of the shifting operation ( or time t46 ). 
If the depletion type field effect transistors Q35, Q36, Q3b and Q3c are selected to be larger in channel conductance, the consumed time period may be decreased, however, a considerable amount of current is consumed in the level shifters of the latching circuit.  In a practical application, development efforts are made for reduction in the current consumption.  Then, the above solution is not feasible.  On the other hand, the depletion type field effect transistors Q35, Q36, Q3b and Q3c tend to be decreased in channel conductance for reduction in the amount of current consumed.  In fact, if the level shifters formed by those depletion type field effect transistors are decreased in current driving capability to a third, the time interval of 5t measuring from time t42 to time t46 is prolonged to be as long as about 4.2 times of the time interval.  The prolonged time interval TL is calculated as follows: EQU TL=4t .times.3+4t.times.(3/4).times.3=21t