The present invention relates to the field of electronic filters, and more particularly to high order SINC filters that shape signals to follow the trigonometric function SINC defined as SINC(f)=sin(f)/f, where f is the frequency of the input signal. 
Electronic filters are widely used today in communications systems.  For example, circuits that perform interpolation and decimation functions use filters that spectrally shape a signal in such a way that the filter""s output is a function of some desired mathematical function.  Certain interpolator and decimator circuits use SINC filters that shape signals to follow the trigonometric function SINC.  Such filters can be implemented as first, second, third or higher order filters depending on the requirements of system in which they are used. 
Low order SINC filters, such as first and second order filters, which can be implemented using relatively simple circuits, have poor attenuation at high frequencies compared to high order SINC filters, such as third and higher order filters.  The impulse response of an Mth order filter is the impulse response of a first order SINC filter convolved with itself M times.  An Mth order filter is realized by cascading M first-order filters together. 
High order SINC filters suffer from a significant drawback.  Specifically, they require additional circuitry, such as multipliers, adders and memory because their impulse responses are spread over three or more periods of a sub-sampled clock, rather than just one or two periods as in lower order SINC filters.  For example, the memory requirements of such filters increase proportionately with N, the ratio of the sub-sampling frequency to the main clock frequency.  Adding additional circuitry adds to the complexity, cost and power consumption of the circuit. 
We have developed in accordance with the principles of the invention an interpolator circuit and a decimator circuit which are each fabricated using high order SINC filters.  The interpolator circuit includes a plurality of cascades of three integrators, wherein the output of each of the cascades of integrators is coupled to a plurality of adders to generate a single integrator output.  The decimator circuit includes a plurality of cascades of three integrators and an output, wherein one or more of the integrators in each cascade are coupled to an output of the cascades of three integrators and the output of each integrator in a cascade is coupled to the decimator output through an adder circuit.  Advantageously, unlike conventional high order SINC filters, increasing the sub-sampling ratio of either the high order SINC interpolator or decimator fabricated according to the present invention does not result in a corresponding increase in circuit complexity.