1.  Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor integrated circuit having a three-dimensional (3D) stack package structure. 
2.  Description of the Related Art
Packaging technology for semiconductor integrated circuits are being further advanced for miniaturization and mounting reliability.  In accommodating the high performance of electrical and electronic products while pursuing the miniaturization of electrical and electronic products, a stack package technology is used. 
Here, “stack” means vertically stacking at least two or more semiconductor chips or packages.  When a stack package is used for a semiconductor memory device, a product having a memory capacity two or more times larger than a memory capacity may be obtained.  Furthermore, the stack package increases not only the memory capacity but also the packaging density and the efficiency in use of mounting area.  Therefore, the stack package technology is useful. 
Here, a stack package may be fabricated according to the following methods.  According to a first method, individual semiconductor chips may be stacked, and then packaged at once.  According to a second method, packaged individual semiconductor chips may be stacked.  The individual semiconductor chips of the stacked semiconductor package are electrically coupled through metallic wires or through silicon vias (TSV).  The stack package using TSVs has a structure where the physical and electrical coupling between the semiconductor chips is vertically achieved by TSVs formed in the respective semiconductor chips. 
FIG.  1 is a side cross-sectional view of a conventional semiconductor integrated circuit.  FIG.  2 is a plan view of a fourth semiconductor chip illustrated in FIG.  1. 
Referring to FIGS.  1 and 2, the semiconductor integrated circuit 100 includes first to fourth semiconductor chips 110 to 140, a plurality of first through-chip vias 150A to 150C, a plurality of second through-chip vias 160A to 160C, a plurality of third through-chip vias 170A to 170E, and a plurality of coupling pads BP11 to BP13.  The first to fourth semiconductor chips 110 to 140 are stacked vertically.  The plurality of first through-chip vias 150A to 150C are vertically formed through the first to fourth semiconductor chips 110 to 140 at a plurality of first positions corresponding to the respective first through-chip vias and configured to operate as an interface for a first power supply Power 1.  The plurality of second through-chip vias 160A to 160C are vertically formed through the first to fourth semiconductor chips 110 to 140 at a plurality of second positions corresponding to the respective second through-chip vias and configured to operate as an interface for a second power supply Power 2.  The plurality of third through-chip vias 170A to 170E are vertically formed through the first to fourth semiconductor chips 110 to 140 at a plurality of third positions corresponding to the respective third through-chip vias and configured to operate as an interface for a variety of signals.  The plurality of coupling pads BP11 to BP13 are provided between the respective through-chip vias 150A to 150C, 160A to 160C, and 170A to 170C and configured to electrically couple is corresponding through-chip vias. 
The first to fourth semiconductor chips 110 to 140 may be fabricated by the same process.  In this case, the first master chip 110 positioned at the lowermost position serves as a master chip, and the other semiconductor chips 120 to 140 serve as slave chips. 
Since the plurality of first to third through-chip vias 150A to 150C, 160A to 160C, and 170A to 170E are configured to operate as an interface for power supplies or signals, they may be formed of a metal having an excellent conductivity.  For example, copper (Cu) may be used.  The plurality of first to third through-chip vias 150A to 150C, 160A to 160C, and 170A to 170E include TSVs. 
Furthermore, the plurality of coupling pads BP11 to BP13 refer to bump pads. 
In accordance with the semiconductor integrated circuit 100 configured in the above-described manner, a variety of signals or power supplies are transferred through the plurality of first to third through-chip vias 150A to 150C, 160A to 160C, and 170A to 170E. Therefore, current consumption and signal delay may be minimized, and operation performance may be enhanced with an improved bandwidth. 
However, the conventional semiconductor integrated circuit 100 has the following features. 
Each of the first to fourth semiconductor chips 110 to 140 includes an active layer formed on the upper surface thereof, and a variety of circuits are provided in the active layer.  However, according to the trend for high integration, only a minimum number of circuits are left, and unnecessary circuits are removed, in order to reduce the size of the first to fourth semiconductor chips 110 to 140.  The circuits which are usually removed may include circuits for stabilizing a power supply (for example, a reservoir capacitor).  Furthermore, the first and second through-chip vias 150A to 150C and 160A to 160C for interfacing power supplies have a vertical structure in which they are vertically coupled, where the vertical structure is vulnerable to an ohmic drop.  Here, as the number of stacked semiconductor chips increases, the number of through-chip vias to be coupled to the semiconductor chips also increases.  As to through-chip vias stacked at the upper positions, they have access to lower power supplies due to an ohmic drop that inevitably occurs.  In this case, a malfunction may occur due to an unstable signal transmission, and high-speed operations may not be performed properly due to unstable asynchronous characteristics. 
Furthermore, the conventional semiconductor integrated circuit 100 may not properly analyze errors in transferring signals through the plurality of third through-chip vias 170A to 170E in a package state.