1.  Field of the Invention
The present invention relates to a memory module and a memory system having the memory module. 
2.  Description of the Related Art
FIG.  1 is a view of a prior art memory module.  Referring to FIG.  1, a memory module 10 includes a plurality of semiconductor memory devices 11_i (where i is 1 through 9) and a first connector 13 having a plurality of connection terminals connected via a bus (not shown) with the memory devices 11_i. 
FIG.  2 is a view of a prior art memory system including memory module of FIG.  1.  Referring to FIG.  2, a memory system 20 includes a motherboard 21, a chip set (or a controller) 23 mounted on a printed circuit board (PCB) of the motherboard 21, and two memory modules 10_1 and 10_2.  The memory modules 10_1 and 10_2 are inserted into slots 25_1 and 25_2, respectively. 
Data and command signals output from the chip set 23 are input to the plurality of semiconductor memory devices 11 via a bus on the PCB of the motherboard 21, the respective slot 25, the respective connector 13 and the bus of the respective memory module 10. 
Data output from the plurality of semiconductor memory devices 11 of each of the memory modules 10_1 and 10_2 is output to the chip set 23 via the bus of each of the memory modules 10_1 and 10_2, the respective first connector 13, the respective slot 25 and the bus on the motherboard 21. 
In a case where command signals, power supplies, and high-speed data are transmitted via the buses of the motherboard 21, the attenuation of data transmitted via the buses and crosstalk among the buses increase with an increase in the operational speed of the memory system 20.  Due to this, the number of memory modules, which may be used in the memory system 20, is reduced. 
Also, the difference (1) in the distance between the chip set 23 and the slot 25_1 and (2) the distance between the chip set 23 and the slot 25_2 causes skews of signals input/output between the chip set 23 and the memory module 10_1 and between the chip set 23 and the memory module 10_2.