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Fuel cell design with an integrated heat exchanger and gas humidification unit

A fuel cell assembly having a flow distribution subassembly that comprises four sets of flow channels, the first set facing an anode for distribution of a fuel reactant to said anode, the second set facing a cathode for distribution of an oxidant to said cathode, the third set in flow communication with said second set and in heat transfer relation with at least one of said anode and said cathode, and the fourth set receiving a coolant different from said oxidant.

1. A fuel cell assembly having a flow distribution subassembly, the subassembly comprising: a first set of flow channels facing an anode for distribution of a fuel reactant to said anode; a second set of flow channels facing a cathode for distribution of an oxidant to said cathode; a third set of flow channels in flow communication with said second set of flow channels, said third set of flow channels in heat transfer relation with at least one of said anode and said cathode and receiving said oxidant upstream of said second set of flow channels; and a fourth set of flow channels receiving a coolant fluid that is different from said oxidant. 2. The fuel cell assembly according to claim 1, wherein said flow distribution subassembly comprises a unitized bipolar plate, said plate defining said first and second sets of flow channels and at least one of said third and fourth sets of flow channels. 3. The fuel cell assembly according to claim 1, further comprising a cooling device disposed downstream of said third set of flow channels for cooling said oxidant upstream of said second set of flow channels. 4. The fuel cell assembly according to claim 1, wherein a first conductive substrate is patterned to define said first set of flow channels, a second conductive substrate is patterned to define said second set of flow channels, and wherein said first and second substrates are joined together. 5. The fuel cell assembly according to claim 4, further comprising a separator sheet interposed between said first and second conductive substrates. 6. The fuel cell assembly according to claim 5, wherein said third set of flow channels is on one side of said separator sheet and said fourth set of flow channels is on an opposite side of said separator sheet. 7. The fuel cell assembly according to claim 6, wherein said separator sheet comprises a water transport media. 8. The fuel cell assembly according to claim 7, wherein said coolant of said fourth set of channels comprises water which permeates through said water transport media to said third set of channels to humidify said oxidant. 9. The fuel cell assembly according to claim 5, wherein said separator sheet comprises a non-porous electrically conductive material. 10. The fuel cell assembly according to claim 5, further comprising at least one support member disposed adjacent said separator sheet. 11. The fuel cell assembly according to claim 1, wherein respective channels of said first and said second-set of channels are aligned opposing one another. 12. The fuel cell assembly according to claim 1, wherein respective channels of said first and said second set of channels are offset from one another. 13. The fuel cell assembly according to claim 1, wherein respective cross-sectional areas of said first, second, third, and fourth sets of channels are not all the same. 14. The fuel cell assembly of claim 1, wherein a cross-sectional area of a channel of said third set is greater than a cross-sectional area of the next adjacent channel of said second set. 15. The fuel cell assembly of claim 1, wherein said oxidant stream comprises nebulized water. 16. A cooled bipolar plate assembly for separating adjacent first and second fuel cells of a proton exchange membrane (PEM) fuel cell stack and for conducting electric current between said cells, said assembly comprising: a first substrate comprising an anode-confronting face having a plurality of first lands formed therein to define a plurality of first grooves for distributing fuel reactant to the first cell, and a first heat exchange face opposite said anode-confronting face; a second substrate comprising a cathode-confronting face having a plurality of second lands formed therein to define a plurality of second grooves for distributing oxidant to the second cell, and a second heat exchange face opposite said cathode-confronting face, wherein said first and second heat exchange faces: (a) confront each other so as to define therebetween a plurality of passages, at least a portion of said passages receiving said oxidant flowing therethrough to cool an adjacent cell and directing said oxidant to said plurality of second grooves; and (b) are electrically coupled to each other at a plurality of sites. 17. The bipolar plate assembly of claim 16, wherein another portion of said passages receives a substantially dielectric liquid coolant. 18. The bipolar plate assembly of claim 16, further comprising a cooling device disposed downstream of said at least a portion of said passages for cooling said oxidant upstream of said plurality of second grooves. 19. A fuel cell assembly comprising: (i) a first bipolar plate assembly including; (a) a first plate member having a plurality of lands and grooves defining a first flow field for distributing fuel to a first MEA; and (b) a second plate member having a plurality of lands and grooves defining a second flow field distributing oxidant to a second MEA, wherein said lands of said first plate member are joined to respective said lands of said second plate member at a plurality of sites so as to define a first plurality of passages for a first coolant, and wherein said first plurality of passages is in flow communication with said second flow field; and (ii) a second bipolar plate assembly including: (a) a third plate member having a plurality of lands and grooves defining a third flow field for distributing oxidant to said first MEA; (b) a fourth plate member having a plurality of lands and grooves defining a fourth flow field distributing fuel to a third MEA, wherein said lands of said third plate member are joined to respective said lands of said fourth plate member at a plurality of sites so as to define a second plurality passages for a second coolant. 20. A method for cooling an electrochemical fuel cell, the method comprising: conducting an electrochemical reaction in the fuel cell by oxidizing a fuel reactant with an oxidant reactant at a membrane electrode assembly (MEA), thereby generating electrical energy and heat; and cooling said MEA by transferring heat from said MEA to one of said reactants in a first flow path, thereby cooling said MEA and heating said reactant, and directing said heated reactant to a second flow path for reaction at said MEA. 21. The method according to claim 20, wherein said cooling further comprises transporting a coolant through a plurality of coolant flow channels in thermal communication with said membrane electrode assembly. 22. The method according to claim 20, further comprising humidifying said oxidant reactant. 23. The method according to claim 20, wherein said directing includes flowing said reactant from said first flow path to a manifold and then to said second flow path. 24. A fuel cell assembly comprising: an electrode; a plurality of reactant flow channels distributing reactant to said electrode; a first set of coolant flow channels receiving said reactant upstream of said reactant flow channels and directing said reactant to said reactant flow channels; and a second set of coolant flow channels separate from said first set, in heat transfer relationship with said electrode, and containing a coolant, wherein said coolant and said reactant are different. 25. The assembly of claim 24, wherein said first set of coolant channels contains oxidant. 26. The assembly of claim 24, wherein said second set of coolant channels contains dielectric liquid coolant. 27. The assembly of claim 24, wherein said electrode forms a part of a MEA and said first and second sets of coolant channels are on opposite sides of said MEA. 28. The assembly of claim 24, wherein at least one channel of said reactant flow channels is surrounded on three sides by said coolant flow channels. 29. The assembly of claim 28, wherein two sides of said reactant flow channel face respective channels of said first set. 30. The assembly of claim 28, wherein two sides of said reactant flow channel face respective channels of said second set. 31. The assembly of claim 24, wherein at least one said reactant channel has a height of about one-half the height of an adjacent said coolant channel of said first set.

<SOH> BACKGROUND OF THE INVENTION <EOH>Fuel cell power systems convert a fuel and an oxidant into electricity. One such fuel cell power system has a proton exchange membrane (hereinafter also referred to as “PEM”) to catalytically facilitate the reaction of fuels (such as hydrogen) and oxidants (such as oxygen or air) into electricity. The PEM is a solid polymer electrolyte that facilitates transfer of protons from the anode to the cathode in each individual fuel cell of the stack of fuel cells present in a fuel cell power system. In a typical fuel cell assembly, or stack, each fuel cell has flow fields in flow communication with manifolds that provide channels for the various reactant gases to flow into each cell. Gas diffusion assemblies then distribute the reactants from the flow fields to the reactive anode and cathode of a membrane electrode assembly (hereinafter also referred to “MEA”). Effective operation of a PEM fuel cell requires proper humidification of the PEM to maintain its proton conductivity. At the same time, the flow field channels and gas diffusion assemblies must be maintained in non-flooded operational states. In operation, the oxidant is supplied to the cathode where it reacts with hydrogen cations that have crossed the PEM and electrons from an external circuit. The fuel cell generates both electricity and water through the electrochemical reaction. The water is typically removed with the cathode effluent, which may dehydrate the PEM unless the water is otherwise replaced. It should be noted that the rate of evaporation to the cathode is generally greater than the rate of water generation. When hydrated, the polymeric PEM possesses “acidic” properties that provide a medium for conducting protons from the anode to the cathode of the fuel cell. However, if the PEM is not sufficiently hydrated, the “acidic” character diminishes, and may impede the desired electrochemical reaction of the cell. Hydration of the PEM also assists in temperature control within the fuel cell, insofar as the heat capacity of water provides a heat sink. In addition to issues of water balance and cell hydration, another issue in fuel cell design is the efficient use of space. For example, space in a vehicle is precious and designs that minimize the ongoing use of space in the vehicle clearly benefit the utility of the vehicle; this leads toward integration of the humidifying system into each of the fuel cells. The need for efficiency in operation and greater integration of cooling and humidification to achieve efficient space utilization in fuel cell systems continues to be strongly felt. What is needed is a fuel cell power system which provides integrated humidification of the feed gases (especially the oxidant) and cooling of the MEA.

<SOH> SUMMARY OF THE INVENTION <EOH>The present invention is directed to a fuel cell having a membrane electrode assembly in reactive interface with (1) a plurality of oxidant reactant flow channels receiving and carrying an oxidant reactant, and (2) a plurality of fuel reactant flow channels receiving and carrying a fuel reactant. The fuel cell includes a plurality of oxidant coolant channels, each in thermal interface with an MEA, preferably for the length of the reactive interface. Preferably each oxidant coolant channel is also in flow communication with a respective cathode reactant flow channel. Two-phase air feed, which may include nebulized water and air, is provided to each oxidant coolant channel. The nebulized water humidifies the air using heat from the fuel cell. Humidified air is discharged from the oxidant coolant channel outlet to provide humidified oxidant to the cathode reactant channel. In a further aspect, the present invention provides a plurality of coolant flow channels adjacent to the reactant flow channels and the MEA. The coolant flow channels are positioned providing a thermal interface surface adjacent the MEA. Preferably, each coolant flow channel has an elongated axis in parallel alignment with the elongated axis of the adjacent reactant flow channel for the length of the reactive interface of the fuel cell. In one embodiment, the plurality of coolant flow channels transports a dielectric liquid coolant. In another variation, the oxidant coolant and the liquid dielectric coolant are used together in separate coolant channels. In yet another aspect of the present invention, an oxidant cooling channel cools the fuel cell while receiving water from the liquid coolant channel via a water transport media. The water humidifies the oxidant prior to entering the cathode reactant channel. In still another aspect of the present invention, the fuel cell system includes a fuel processor making a reformate gas for the fuel cell from a hydrocarbon fuel feed, a reformer water feed, and a reformer air feed. The fuel processor and fuel cell are controlled by a computer which balances water flows to hydrate the fuel cell. A further aspect of the present invention discloses a method for cooling an electrochemical fuel cell. The method includes conducting an electrochemical reaction by oxidizing a fuel reactant with an oxidant reactant at an MEA. In addition to water, the reaction produces electricity and thermal energy. The MEA is cooled by transferring heat to at least one of the reactants in a first flow path, thereby heating the reactant. The heated reactant is subsequently directed to a second flow path leading to the MEA in a reactant capacity. Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiments of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.

DC/DC-less coupling of matched batteries to fuel cells

A fuel cell system that employs a matched battery that matches the battery voltage to a fuel cell power bus voltage so as to eliminate the need for a DC/DC converter. The internal characteristics and parameters of the matched battery allow it to operate over the large load dependent voltage swing of the fuel cell, and prevent the battery state of charge from going below a damaging value. The battery type, number of battery cells and the battery internal impedance are selected to provide the desired matching. In one embodiment, the battery is a lithium ion battery. The system also includes a diode electrically coupled to the power bus line and a by-pass switch electrically coupled to the power bus line in parallel with the diode. The by-pass switch is selectively opened or closed to allow the fuel cell stack to recharge the battery and prevent the battery from being overcharged.

1. A fuel cell system comprising: an electrical power bus line; a fuel cell stack electrically coupled to the power bus line; and a matched battery electrically coupled to the power bus line, said battery being matched by the number of battery cells and state of charge (SOC) depending parameters of the battery that prevent it from discharging below a damaging SOC. 2. The system according to claim 1 further comprising a blocking diode electrically coupled to the power bus line and a by-pass switch electrically coupled to the power bus line in parallel with the diode, said by-pass switch being selectively opened or closed to allow the fuel cell stack to recharge the battery and prevent the battery from being overcharged. 3. The system according to claim 1 wherein the SOC parameters of the battery include the voltage and the internal impedance of the battery. 4. The system according to claim 1 wherein the battery is matched to protect against battery over-discharge, battery over-current and battery over-charge. 5. The system according to claim 1 wherein the battery is selected from the group consisting of lithium ion batteries and nickel-metal-hydride batteries. 6. The system according to claim 1 wherein the battery is a nickel-metal-hydride battery having 240 cells and an output power of 30 kW. 7. The system according to claim 1 further comprising an AC or DC traction motor system electrically coupled to the power bus line, said motor system providing a voltage on the power bus line during regenerative braking for recharging the battery. 8. The system according to claim 1 wherein the fuel cell system is on a vehicle. 9. A fuel cell system comprising: an electrical power bus line; a fuel cell stack electrically coupled to the power bus line; and a lithium ion battery electrically coupled to the power bus line, said battery including a predetermined number of battery cells and a certain internal impedance that allow the battery to be matched by its state of charge (SOC) characteristics to the voltage on the power bus line provided by the fuel cell stack. 10. The system according to claim 9 wherein the number of cells of the battery prevent it from discharging below a damaging state of charge. 11. The system according to claim 9 wherein the battery is matched to protect against battery over-discharge, battery over-current and battery over-charge. 12. The system according to claim 9 further comprising a blocking diode electrically coupled to the power bus line and a by-pass switch electrically coupled to the power bus line in parallel with the diode, said by-pass switch being selectively opened and closed to allow the fuel cell stack to recharge the battery and prevent the battery from being overcharged. 13. The system according to claim 9 further comprising an AC or DC traction motor system electrically coupled to the power bus line, said motor system providing a voltage on the bus line during regenerative braking for recharging the battery. 14. The system according to claim 9 wherein the fuel cell system is on a vehicle. 15. A fuel cell system for a vehicle, said system comprising: an electrical power bus line; a fuel cell stack electrically coupled to the power bus line; a lithium ion battery electrically coupled to the power bus line, said battery including a predetermined number of battery cells and a certain internal impedance that allow the battery to be matched by its discharge characteristics to the voltage on the power bus line provided by the fuel cell stack and prevent it from discharging below a damaging state of charge; and a blocking diode electrically coupled to the power bus line and a by-pass switch electrically coupled to the power bus line in parallel with the diode, said by-pass switch being selectively opened or closed to allow the fuel cell stack to recharge the battery or prevent the battery from being overcharged. 16. The system according to claim 15 wherein the battery is matched to protect against battery over-discharge, battery over-current and battery over-charge. 17. The system according to claim 15 further comprising an AC or DC traction motor system electrically coupled to the power bus line, said motor system providing a voltage on the bus line during regenerative braking for recharging the battery.

<SOH> BACKGROUND OF THE INVENTION <EOH>1. Field of the Invention This invention relates generally to a fuel cell system and, more particularly, to a fuel cell system that employs a matched battery that eliminates the need for a DC/DC converter. 2. Discussion of the Related Art Hydrogen is a very attractive fuel because it is clean and can be used to efficiently produce electricity in a fuel cell. The automotive industry expends significant resources in the development of hydrogen fuel cells as a source of power for vehicles. Such vehicles would be more efficient and generate fewer emissions than today's vehicles employing internal combustion engines. A hydrogen fuel cell is an electrochemical device that includes an anode and a cathode with an electrolyte therebetween. The anode receives hydrogen gas and the cathode receives oxygen or air. The hydrogen gas is dissociated in the anode to generate free hydrogen protons and electrons. The hydrogen protons pass through the electrolyte to the cathode. The hydrogen protons react with the oxygen and the electrons in the cathode to generate water. The electrons from the anode cannot pass through the electrolyte, and thus are directed through a load to perform work before being sent to the cathode. The work acts to operate the vehicle. Proton exchange membrane fuel cells (PEMFC) are a popular fuel cell for vehicles. The PEMFC generally includes a solid polymer electrolyte proton conducting membrane, such as a perfluorosulfonic acid membrane. The anode and cathode typically include finely divided catalytic particles, usually platinum (Pt), supported on carbon particles and mixed with an ionomer. The catalytic mixture is deposited on opposing sides of the membrane. The combination of the anode catalytic mixture, the cathode catalytic mixture and the membrane define a membrane electrode assembly (MEA). MEAs are relatively expensive to manufacture and require certain conditions for effective operation. These conditions include proper water management and humidification, and control of catalyst poisoning constituents, such as carbon monoxide (CO). Several fuel cells are typically combined in a fuel cell stack to generate the desired power. The fuel cell stack receives a cathode input gas, typically a flow of air forced through the stack by a compressor. Not all of the oxygen is consumed by the stack and some of the air is output as a cathode exhaust gas that may include water as a stack by-product. The fuel cell stack also receives an anode hydrogen input gas that flows into the anode side of the stack. Most fuel cell vehicles are hybrid vehicles that employ a supplemental power source in addition to the fuel cell stack, such as a DC battery or super capacitor. The power source provides supplemental power for the various vehicle auxiliary loads, for system start-up and during high power demands when the fuel cell stack is unable to provide the desired power. The fuel cell stack provides power to a traction motor through a DC voltage bus line for vehicle operation. The battery provides supplemental power to the voltage bus line during those times when additional power is needed beyond what the stack can provide, such as during heavy acceleration. For example, the fuel cell stack may provide 70 kW of power. However, vehicle acceleration may require 100 kW of power. The fuel cell stack is used to recharge the battery at those times when the fuel cell stack is able to provide the system power demand. The generator power available from the traction motor during regenerative braking is also used to recharge the battery. In the hybrid vehicle discussed above, a bi-directional DC/DC converter is typically necessary to step up the DC voltage from the battery to match the battery voltage to the bus line voltage dictated by the voltage output of the fuel cell stack and step down the stack voltage during battery recharging. However, DC/DC converters are relatively large, costly and heavy, providing obvious disadvantages. It is desirable to eliminate the DC/DC converter from a fuel cell vehicle including a supplemental power source. There have been various attempts in the industry to eliminate the DC/DC converter in fuel cell powered vehicles by providing a power source that is able to handle the large voltage swing coming from the fuel cell stack with its V/I characteristic (polarization curve) over the operating conditions of the vehicle. FIG. 2 is a graph with current density on the horizontal axis and fuel cell stack voltage on the vertical axis showing a typical fuel cell stack V/I characteristic or polarization curve of a stack including 400 cells in series. In one known system, a super-capacitor is used as the supplemental power source. However, the super-capacitor is limited by how much it can be discharged because of its low energy content. Also, the super-capacitor requires a power device to ramp up the super-capacitor voltage at system start-up. Certain types of batteries have also been used to eliminate the DC/DC converter in vehicle fuel cell systems. However, these systems were limited by the ability to discharge the battery beyond a certain level. In other words, these types of batteries would be damaged as a result of large voltage swings on the DC bus line during the operation of the system.

<SOH> SUMMARY OF THE INVENTION <EOH>In accordance with the teachings of the present invention, a fuel cell system is disclosed that employs a matched battery that matches the battery voltage to a power bus line voltage so as to eliminate the need for a DC/DC converter. The internal characteristics and parameters of the matched battery allow it to operate over a large voltage discharge swing as dictated by the fuel cell V/I characteristic, and prevent the battery from being over-discharged. The battery type, number of battery cells and the battery internal impedance are designed to provide the desired matching. In one embodiment, the battery is a lithium ion battery. The system also includes a diode electrically coupled to the power bus line and a by-pass switch electrically coupled to the bus line in parallel with the diode. The by-pass switch is selectively opened and closed to allow the fuel cell stack to recharge the battery and prevent the battery from being overcharged. Additional advantages and features of the present invention will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings.

Polishing pads and planarizing machines for mechanical or chemical-mechanical planarization of microelectronic-device substrate assemblies, and methods for making and using such pads and machines

Polishing pads used in the manufacturing of microelectronic devices, and apparatuses and methods for making and using such polishing pads. In one aspect of the invention, a polishing pad for planarizing microelectronic-device substrate assemblies has a backing member including a first surface and a second surface, a plurality of pattern elements distributed over the first surface of the backing member, and a hard cover layer over the pattern elements. The pattern elements define a plurality of contour surfaces projecting away from the first surface of the backing member. The cover layer at least substantially conforms to the contour surfaces of the pattern elements to form a plurality of hard nodules projecting away from the first surface of the backing member. The hard nodules define abrasive elements to contact and abrade material from a microelectronic-device substrate assembly. As such, the cover layer defines at least a portion of a planarizing surface of the polishing pad.

1. A polishing pad for planarizing microelectronic-device substrate assemblies, comprising: a backing member having a first surface and a second surface; a plurality of pattern elements distributed over the first surface of the backing member, the pattern elements defining a plurality of contour surfaces projecting away from the first surface of the backing member; and a hard cover layer over the pattern elements and over portions of the first surface of the backing member exposed between pattern elements, the cover layer at least substantially conforming to the contour surfaces of the pattern elements to form a plurality of hard nodules projecting away from the first surface of the backing member, the nodules defining at least a portion of a planarizing surface of the polishing pad for engaging a microelectronic-device substrate assembly. 2-83. (canceled)

<SOH> BACKGROUND OF THE INVENTION <EOH>Mechanical and chemical-mechanical planarizing processes (collectively “CMP”) are used in the manufacturing of electronic devices for forming a flat surface on semiconductor wafers, field emission displays and many other microelectronic-device substrate assemblies. CMP processes generally remove material from a substrate assembly to create a highly planar surface at a precise elevation in the layers of material on the substrate assembly. FIG. 1 schematically illustrates an existing web-format planarizing machine 10 for planarizing a substrate assembly 12 . The planarizing machine 10 has a support table 14 with a top panel 16 at a workstation where an operative portion (A) of a polishing pad 40 is positioned. The top panel 16 is generally a rigid plate to provide a flat, solid surface to which a particular section of the polishing pad 40 may be secured during planarization. The planarizing machine 10 also has a plurality of rollers to guide, position and hold the polishing pad 40 over the top panel 16 . The rollers include a supply roller 20 , first and second idler rollers 21 a and 21 b , first and second guide rollers 22 a and 22 b , and a take-up roller 23 . The supply roller 20 carries an unused or preoperative portion of the polishing pad 40 , and the take-up roller 23 carries a used or postoperative portion of the polishing pad 40 . Additionally, the first idler roller 21 a and the first guide roller 22 a stretch the polishing pad 40 over the top panel 16 to hold the polishing pad 40 stationary during operation. A motor (not shown) drives at least one of the supply roller 20 and the take-up roller 23 to sequentially advance the polishing pad 40 across the top panel 16 . As such, clean preoperative sections of the polishing pad 40 may be quickly substituted for used sections to provide a consistent surface for planarizing and/or cleaning the substrate assembly 12 . The web-format planarizing machine 10 also has a carrier assembly 30 that controls and protects the substrate assembly 12 during planarization. The carrier assembly 30 generally has a substrate holder 32 to pick up, hold and release the substrate assembly 12 at appropriate stages of the planarizing cycle. A plurality of nozzles 33 attached to the substrate holder 32 dispense a planarizing solution 44 onto a planarizing surface 42 of the polishing pad 40 . The carrier assembly 30 also generally has a support gantry 34 carrying a drive assembly 35 that translates along the gantry 34 . The drive assembly 35 generally has an actuator 36 , a drive shaft 37 coupled to the actuator 36 , and an arm 38 projecting from the drive shaft 37 . The arm 38 carries the substrate holder 32 via another shaft 39 such that the drive assembly 35 orbits the substrate holder 32 about an axis B-B offset from a center point C-C the substrate assembly 12 . The polishing pad 40 and the planarizing solution 44 define a planarizing medium that mechanically and/or chemically-mechanically removes material from the surface of the substrate assembly 12 . The web-format planarizing machine 10 typically uses a fixed-abrasive polishing pad in which abrasive particles are fixedly bonded to a suspension material. In fixed-abrasive applications, the planarizing solution is generally a “clean solution” without abrasive particles because the abrasive particles are fixedly distributed across the planarizing surface 42 of the polishing pad 40 . In other applications, the polishing pad 40 may be a nonabrasive pad composed of a polymeric material (e.g., polyurethane), a resin, or other suitable materials without abrasive particles. The planarizing solutions 44 used with nonabrasive polishing pads are typically CMP slurries with abrasive particles and chemicals to remove material from a substrate. To planarize the substrate assembly 12 with the planarizing machine 10 , the carrier assembly 30 presses the substrate assembly 12 against the planarizing surface 42 of the polishing pad 40 in the presence of the planarizing solution 44 . The drive assembly 35 then orbits the substrate holder 32 about the offset axis B-B to translate the substrate assembly 12 across the planarizing surface 42 . As a result, the abrasive particles and/or the chemicals in the planarizing medium remove material from the surface of the substrate assembly 12 . CMP processes should consistently and accurately produce a uniformly planar surface on the substrate assembly 12 to enable precise fabrication of circuits and photo-patterns. During the fabrication of transistors, contacts, interconnects and other components, many substrate assemblies develop large “step heights” that create a highly topographic surface across the substrate assembly 12 . To enable the fabrication of integrated circuits with high densities of components, it is necessary to produce a highly planar substrate surface at several stages of processing the substrate assembly 12 because nonplanar substrate surfaces significantly increase the difficulty of forming submicron features. For example, it is difficult to accurately focus photo-patterns to within tolerances approaching 0.1 μm on nonplanar substrate surfaces because submicron photolithographic equipment generally has a very limited depth of field. Thus, CMP processes are often used to transform a topographical substrate surface into a highly uniform, planar substrate surface. In the competitive semiconductor industry, it is also highly desirable to have a high yield in CMP processes by quickly producing a uniformly planar surface at a desired endpoint on a substrate assembly 12 . For example, when a conductive layer on a substrate assembly 12 is under-planarized in the formation of contacts or interconnects, many of these components may not be electrically isolated from one another because undesirable portions of the conductive layer may remain on the substrate assembly 12 over a dielectric layer. Additionally, when a substrate assembly 12 is over planarized, components below the desired endpoint may be damaged or completely destroyed. Thus, to provide a high yield of operable microelectronic devices, CMP processing should quickly remove material until the desired endpoint is reached. One technique to improve the performance of CMP processing is to use fixed-abrasive pads (FAPs) with a clean planarizing solution instead of nonabrasive pads with abrasive slurries. One problem with abrasive slurries is that the slurry may not uniformly contact the face of a substrate assembly 12 because the leading edge of the substrate assembly 12 wipes the slurry off of the pad 40 . As a result, more abrasive particles generally contact the edge of the substrate 12 assembly than the center, causing a center-to-edge planarizing profile. FAPs seek to resolve this problem by fixedly attaching the abrasive particles to the pad in a desired distribution. By fixing the abrasive particles to the pad instead of suspending the abrasive particles in the slurry, the center of the substrate assembly 12 contacts a large number of abrasive particles irrespective of the distribution of planarizing solution between the pad and the substrate assembly 12 . Using FAPs, however, presents some drawbacks in CMP processing. One drawback of existing FAPs is that the abrasive particles in the FAPs may not adequately planarize substrate assemblies with very small components (e.g., components with a dimension of 0.25 μM or less). Existing FAPs are typically fabricated by covering a Mylar® or polyurethane backing film with a layer of resin and abrasive particles. The resin is then cured, and the layer of cured resin and abrasive particles may be textured. The particle size distribution of the abrasive particles in FAPs should: (1) be consistent from one pad to another to provide consistent planarizing results; and (2) have small particle sizes that are generally less than the critical dimension of the smallest components to avoid producing defects and to form a very smooth surface on the substrate assembly. The particle size distribution in FAPs, however, may not be small enough to planarize very small components because individual abrasive particles may agglomerate into larger abrasive elements that have a plurality of individual particles. For example, FAPs may have abrasive particles with individual particle sizes of approximately 10-250 μm, but the individual particles may agglomerate together to form relatively large abrasive elements in the resin having a size distribution from 0.2-1.5 μm. The formation of such large abrasive elements alters the consistency of the FAPs because the extent that the particles agglomerate varies from one pad to another, or even within a single pad. Additionally, large abrasive elements may scratch the substrate assembly and produce defects, or they may damage very small components of the integrated circuitry on a substrate assembly. Thus, the agglomeration of abrasive particles into larger abrasive elements is a serious problem for fabricating very small electronic components with FAPs. Another drawback of FAPs is that it is difficult to obtain the desired distribution of abrasive particles in the resin even when the individual abrasive particles do not form a significant number of larger abrasive elements. For example, it is generally difficult to control the distribution of the abrasive particles in the resin because the resin typically has a relatively high viscosity that inhibits uniform mixing of the abrasive particles. One particularly difficult application is producing FAPs with ceria abrasive particles because it is difficult to manufacture small ceria particles and it is difficult to uniformly mix ceria particles in a liquid. Thus, even if the abrasive particles do not agglomerate extensively, it is still difficult to obtain a desired distribution of abrasive particles at the planarizing surface of an FAP. Still another concern of using FAPs is that these pads are relatively expensive and may wear out rather quickly. FAPs are relatively expensive because of the difficulties in obtaining sufficiently small particle sizes and a desired distribution of the abrasive particles, as explained above. Moreover, FAPs are subject to wear because the substrate assembly rubs against the resin at the planarizing surface causing the resin to wear down. As a result, some of the abrasive particles may detach from the resin and cause defects, or the abrasiveness of the pad may be sufficiently altered to produce inconsistent planarizing results. Therefore, using FAPs may increase the costs of planarizing microelectronic-device substrate assemblies.

<SOH> SUMMARY OF THE INVENTION <EOH>The present invention is directed toward polishing pads used in the manufacturing of microelectronic devices, and apparatuses and methods for making and using such polishing pads. In one aspect of the invention, a polishing pad for planarizing microelectronic-device substrate assemblies has a backing member including a first surface and a second surface, a plurality of pattern elements distributed over the first surface of the backing member, and a hard cover layer over the pattern elements. The pattern elements define a plurality of contour surfaces projecting away from the first surface of the backing member. The backing member and the pattern elements can accordingly define a base section having a first surface, a plurality of contour surfaces above the first surface, and a second surface configured to be placed on a planarizing machine. The cover layer at least substantially conforms to the contour surfaces of the pattern elements to form a plurality of hard nodules projecting away from the first surface of the backing member. The hard nodules define abrasive elements to contact and abrade material from a microelectronic-device substrate assembly. As such, the cover layer defines at least a portion of a planarizing surface of the polishing pad. The pattern elements are preferably colloidal silica particles that can be manufactured in precise sizes and shapes. The pattern elements preferably have particle sizes from approximately 5-500 nm, and more preferably from approximately 10-120 nm. The cover layer preferably is composed of an abrasive layer of material deposited over the pattern elements. For example, the abrasive layer can be composed of silica nitride, ceria, silica, alumina, titania, titanium, zirconium or nitride. In another aspect of the invention, a polishing pad is manufactured by depositing a plurality of pattern elements over the first surface of the backing member, and then depositing the hard cover layer over the pattern elements. For example, the pattern elements can be deposited onto the first surface of the backing member by pulling the backing member through a bath having a liquid and a plurality of the pattern elements suspended in the liquid. The pattern elements are preferably colloidal in the liquid. The backing member is then removed from the bath to evaporate the liquid from the backing member and leave a plurality of the pattern elements distributed over the first surface of the backing member. The hard cover layer can then be deposited over the pattern elements using chemical vapor deposition, plasma vapor deposition or other suitable deposition processes for forming thin films on a surface. In still another aspect of the invention, a microelectronic-device substrate assembly may be planarized using such a polishing pad by depositing a planarizing solution onto the polishing pad and pressing the substrate assembly against the hard nodules at the planarizing surface. The method continues by moving at least one of the substrate assembly and the polishing pad with respect to the other to rub the face of the substrate assembly across the nodules in the presence of the planarizing solution. The hard nodules accordingly abrade material from the face of the substrate assembly in a manner similar to abrasive particles in a fixed-abrasive pad.

Immersion lithography process, and structure used for the same and patterning process

An immersion lithography process is described. First, a photoresist layer on a material layer is formed. Then, an acid compensation layer is formed on the photoresist layer. An immersion exposure step is performed on the acid compensation layer and the photoresist layer. The acid compensation layer contains a photo-acid generator with a concentration of the photo-acid higher than that produced by a photo-acid generator in the photoresist layer after the immersion exposure step. Then, a development step is performed to pattern the acid compensation layer and the photoresist layer.

1. An immersion lithography process, comprising: forming a photoresist layer on a material layer; forming an acid compensation layer on the photoresist layer; performing an immersion exposure step on the acid compensation layer and the photoresist layer; and performing a development step to pattern the acid compensation layer and the photoresist layer. 2. The immersion lithography process of claim 1, wherein the acid compensation layer contains a photo-acid generator with a concentration of the photo-acid higher than that produced by a photo-acid generator in the photoresist layer after the immersion exposure step. 3. The immersion lithography process of claim 1, wherein the material of the acid compensation layer is the same as that of the photoresist layer. 4. The immersion lithography process of claim 3, wherein the acid compensation layer contains a photo-acid generator with a concentration higher than that in the photoresist layer. 5. The immersion lithography process of claim 1, wherein the material of the acid compensation layer is different from that of the photoresist layer. 6. The immersion lithography process of claim 5, wherein the acid compensation layer contains a photo-acid generator that has a dissolving rate lower than that contained in the photoresist layer. 7. The immersion lithography process of claim 1, wherein the acid compensation layer has a thickness of 10-30 nm. 8. A patterning process, comprising: forming a photoresist layer on a material layer; forming an acid compensation layer on the photoresist layer; performing an immersion exposure step on the acid compensation layer and the photoresist layer; performing a development step to form a patterned acid compensation layer and a patterned photoresist layer; and etching the material layer by using the patterned acid compensation layer and the patterned photoresist layer as etching masks. 9. The patterning process of claim 8, wherein the acid compensation layer contains a photo-acid generator with a concentration of the photo-acid higher than that produced by a photo-acid generator in the photoresist layer after the immersion exposure step. 10. The patterning process of claim 8, wherein the material of the acid compensation layer is the same as that of the photoresist layer. 11. The patterning process of claim 10, wherein the acid compensation layer contains a photo-acid generator with a concentration higher than that in the photoresist layer. 12. The patterning process of claim 8, wherein the material of the acid compensation layer is different from that of the photoresist layer. 13. The patterning process of claim 12, wherein the acid compensation layer contains a photo-acid generator that has a dissolving rate lower than that contained in the photoresist layer. 14. The patterning process of claim 8, wherein the acid compensation layer has a thickness of 10-30 nm. 15. A structure used in an immersion lithography process, the structure comprising: a photoresist layer disposing on a material layer; and an acid compensation layer disposing on the photoresist layer. 16. The structure of claim 15, wherein the material of the acid compensation layer is the same as that of the photoresist layer. 17. The structure of claim 16, wherein the acid compensation layer contains a photo-acid generator with a concentration higher than that in the photoresist layer. 18. The structure of claim 15, wherein the material of the acid compensation layer is different from that of the photoresist layer. 19. The structure of claim 18, wherein the acid compensation layer contains a photo-acid generator that has a dissolving rate lower than that contained in the photoresist layer. 20. The structure of claim 15, wherein the acid compensation layer has a thickness of 10-30 nm.

<SOH> BACKGROUND OF THE IVENTION <EOH>1. Field of the Invention This invention relates to a semiconductor process, and particularly to an immersion lithography process and a patterning process. 2. Brief Description of Related Art Photolithography is one of the most important technologies in semiconductor production. All patterns or doping areas regarding to metal oxide semiconductor device are defined by photolithography. In general, photolithography process includes photoresist coating, light exposure and development. In the exposure step, exposure light beams travel through a mask to reach a photoresist layer or directly reach the photoresist layer to generate photochemical reaction at exposed sections of the photoresist layer. After baking and developing steps, mask patterns are transferred to the photoresist layer to form a patterned photoresist layer. As the integration of integral circuits increases, the device size of the integral circuits decreases. In order to meet the requirement in reduction of device size, an immersion lithography process has been developed. Currently, this immersion lithography process is conducted in liquid phase. By taking the advantage that the refractive index of liquid is higher than that of air, the wavelength will be shortened while light travels through liquid. The resolution of exposure is thereby increased to achieve the reduction in device size. However, the immersion lithography process has several critical concerns to be overcome, such as interaction between the immersion liquid and the photoresist layer and the control of micro-bubbles in the liquid. Specifically when the exposure step is conducted, part of chemicals enters the liquid from the photoresist layer due to the contact with the liquid, which deteriorates the photoresist layer. Particularly, when photo-acid generator (PAG) contained in the photoresist layer diffuses into the immersion liquid during the exposure step, the PAG concentration will be lowered. As a result, the developed photoresist patterns have T-top problem. As such, the process resolution, the process window, and the critical size and uniformity of the photoresist patterns are adversely affected. One approach has been proposed to solve the T-top problem in the art by forming a barrier layer over the photoresist layer. The barrier layer does not contain photo-acid generator, and is used to stop the photo-acid generator from diffusing into the immersion liquid. The formation of the barrier layer is complicated as the property of the barrier layer must be unsolvable in the immersion liquid during the exposure step while solvable in tetra-methyl-ammonium hydroxide (TMAH) developing agent. Furthermore, forming the barrier layer on the photoresist layer adds cost to the total production.

<SOH> SUMMARY OF THE INVENTION <EOH>Therefore, it is an object of the invention to provide an immersion lithography process that solves the T-top problem in the art caused by the diffusion of chemicals into the immersion liquid from the photoresist layer so as to improve the process resolution. It is another object of the invention to provide a patterning process that precisely controls the critical size and increases the uniformity of the critical size. It is another object of the invention to provide a structure used in the immersion lithography process to prevent the formation of T-top photoresist patterns and thus increases the process window. In one aspect of the invention, an immersion lithography process is provided. The immersion lithography process comprises forming a photoresist layer on a material layer; forming an acid compensation layer on the photoresist layer; performing an immersion exposure step on the acid compensation layer and the photoresist layer; and performing a development step to pattern the acid compensation layer and the photoresist layer. According to one preferred embodiment of the invention, the acid compensation layer contains a photo-acid generator with a concentration of the photo-acid higher than that produced by a photo-acid generator in the photoresist layer after the immersion exposure step. According to one preferred embodiment of the invention, the material of the acid compensation layer is the same as that of the photoresist layer, and the acid compensation layer contains a photo-acid generator with a concentration higher than that in the photoresist layer. According to one preferred embodiment of the invention, the material of the acid compensation layer is different from that of the photoresist layer, and the acid compensation layer contains a photo-acid generator that has a dissolving rate lower than that contained in the photoresist layer. According to one preferred embodiment of the invention, the acid compensation layer has a thickness of about 10-30 nm. In another aspect of the invention, a patterning process is provided. The patterning process comprises forming a photoresist layer on a material layer; forming an acid compensation layer on the photoresist layer; performing an immersion exposure step on the acid compensation layer and the photoresist layer; performing a development step to form a patterned acid compensation layer and a patterned photoresist layer; and etching the material layer by using the patterned acid compensation layer and the patterned photoresist layer as etching masks. According to one preferred embodiment of the invention, the aforementioned acid compensation layer contains a photo-acid generator with a concentration of the photo-acid higher than that produced by a photo-acid generator in the photoresist layer after the immersion exposure step. According to one preferred embodiment of the invention, the material of the acid compensation layer is the same as that of the photoresist layer, and the acid compensation layer contains a photo-acid generator with a concentration higher than that in the photoresist layer. According to one preferred embodiment of the invention, the material of the acid compensation layer is different from that of the photoresist layer, and the acid compensation layer contains a photo-acid generator that has a dissolving rate lower than that contained in the photoresist layer. According to one preferred embodiment of the invention, the acid compensation layer has a thickness of about 10-30 nm. The present invention further provides a structure used in an immersion lithography process. The structure comprises a photoresist layer on a material layer; and an acid compensation layer on the photoresist layer. According to one preferred embodiment of the invention, the material of the acid compensation layer is the same as that of the photoresist layer, and the acid compensation layer contains a photo-acid generator with a concentration higher than that in the photoresist layer. According to one preferred embodiment of the invention, the material of the acid compensation layer is different from that for the photoresist layer, and the acid compensation layer contains a photo-acid generator that has a dissolving rate lower than that contained in the photoresist layer. According to one preferred embodiment of the invention, the acid compensation layer has a thickness of about 10-30 nm. In the invention, the acid compensation layer formed over the photoresist layer is used as a photo-acid generator diffusion layer to replace the photoresist layer. After the immersion exposure step, the concentration of the photo-acid generator contained in the acid compensation layer is higher than that in the photoresist layer. There are no T-top concerns in the subsequent processing steps so that the critical size of the patterns can be precisely controlled and thus the process resolution can be improved.

Semiconductor package free of substrate and fabrication method thereof

A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

1. A semiconductor package, comprising: a dielectric material layer formed with a plurality of openings penetrating the same; a conductive material applied in the openings of the dielectric material layer; a conductive layer formed on the dielectric material layer and the conductive material, wherein the conductive layer comprises a plurality of conductive traces and a chip attach portion, and each of the conductive traces has a terminal; at least one chip mounted on the chip attach portion of the conductive layer, and electrically connected to the chip attach portion and the terminals; and an encapsulant for encapsulating the chip and the conductive layer, with the dielectric material layer and the conductive material being partly exposed from the encapsulant. 2. The semiconductor package of claim 1, further comprising a metal layer applied on the terminals of the conductive traces. 3. The semiconductor package of claim 2, wherein the metal layer is made of silver or a nickel/gold alloy. 4. The semiconductor package of claim 1, further comprising an insulating layer applied on the conductive traces, with the terminals of the conductive traces being exposed from the insulating layer. 5. The semiconductor package of claim 4, wherein the insulating layer is made of solder mask or polyimide. 6. The semiconductor package of claim 1, wherein the conductive material comprises a solder material. 7. The semiconductor package of claim 6, wherein the solder material comprises a tin/lead alloy. 8. The semiconductor package of claim 1, wherein the conductive layer comprises a first copper layer formed on the dielectric material layer and the conductive material, and a second copper layer formed on the first copper layer and comprising the plurality of conductive traces. 9. The semiconductor package of claim 8, wherein the first copper layer is smaller in thickness than the second copper layer. 10. The semiconductor package of claim 1, wherein the dielectric material layer is made of a material selected from the group consisting of epoxy resin, polyimide and polytetrafluoroethylene (PTFE). 11. The semiconductor package of claim 1, wherein the chip is electrically connected to the chip attach portion and the terminals by a plurality of bonding wires. 12. The semiconductor package of claim 11, wherein the bonding wires for electrically connecting the chip to the chip attach portion are ground wires. 13. The semiconductor package of claim 1, further comprising a plurality of solder balls implanted on the exposed part of the conductive material. 14. A method for fabricating a semiconductor package, comprising the steps of: preparing a metal carrier; applying a dielectric material layer over a surface of the metal carrier, and forming a plurality of openings through the dielectric material layer; applying a conductive material in the openings of the dielectric material layer; forming a conductive layer on the dielectric material layer and the conductive material, wherein the conductive layer comprises a plurality of conductive traces and a chip attach portion, and each of the conductive traces has a terminal; mounting at least one chip on the chip attach portion of the conductive layer, and electrically connecting the chip to the chip attach portion and the terminals; forming an encapsulant for encapsulating the chip and the conductive layer; and removing the metal carrier to partly expose the dielectric material layer and the conductive material. 15. The method of claim 14, further comprising a step of applying a metal layer on the terminals of the conductive traces. 16. The method of claim 15, wherein the metal layer is made of silver or a nickel/gold alloy. 17. The method of claim 14, further comprising a step of applying an insulating layer on the conductive traces, with the terminals of the conductive traces being exposed from the insulating layer. 18. The method of claim 17, wherein the insulating layer is made of solder mask or polyimide. 19. The method of claim 14, wherein the metal carrier is made of copper. 20. The method of claim 14, wherein the metal carrier is removed by an etching process. 21. The method of claim 14, wherein the conductive material comprises a solder material. 22. The method of claim 21, wherein the solder material comprises a tin/lead alloy. 23. The method of claim 14, wherein the conductive layer comprises a first copper layer formed on the dielectric material layer and the conductive material, and a second copper layer formed on the first copper layer and comprising the plurality of conductive traces. 24. The method of claim 23, wherein the first copper layer is smaller in thickness than the second copper layer. 25. The method of claim 14, wherein the dielectric material layer is made of a material selected from the group consisting of epoxy resin, polyimide and polytetrafluoroethylene (PTFE). 26. The method of claim 14, wherein the chip is electrically connected to the chip attach portion and the terminals by a plurality of bonding wires. 27. The method of claim 26, wherein the bonding wires for electrically connecting the chip to the chip attach portion are ground wires. 28. The method of claim 14, further comprising a step of implanting a plurality of solder balls on the exposed part of the conductive material.