Datasets:

davide221

/

hdl-raw-35k

like 0

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fslt_2CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

5a7e0f51841799c99d83349bd23973ef

preusser/q27

src/vhdl/queens/msg_funnel.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.utils.all; entity msg_funnel is generic ( N : positive -- Number of Funnel Inputs ); port ( -- Global Control clk : in std_logic; rst : in std_logic; -- Funnel Inputs ivld : in std_logic_vector(0 to N-1); idat : in byte_vector(0 to N-1); ieof : in std_logic_vector(0 to N-1); igot : out std_logic_vector(0 to N-1); -- Funnel Output oful : in std_logic; odat : out byte; oeof : out std_logic; oput : out std_logic ); end msg_funnel; library IEEE; use IEEE.numeric_std.all; architecture rtl of msg_funnel is component arbit_forward generic ( N : positive -- Length of Token Chain ); port ( tin : in std_logic; -- Fed Token have : in std_logic_vector(0 to N-1); -- Token Owner pass : in std_logic_vector(0 to N-1); -- Token Passers grnt : out std_logic_vector(0 to N-1); -- Token Output tout : out std_logic -- Unused Token ); end component; signal Active : std_logic := '0'; signal SelBin : unsigned(log2ceil(N)-1 downto 0) := (others => '-'); signal grnt : std_logic_vector(0 to N-1); signal tout : std_logic; begin process(clk) begin if rising_edge(clk) then if rst = '1' then Active <= '0'; SelBin <= (others => '-'); else if oful = '0' then if Active = '0' then if tout = '0' then for i in 0 to N-1 loop if grnt(i) = '1' then SelBin <= to_unsigned(i, SelBin'length); end if; end loop; Active <= '1'; end if; else if ivld(to_integer(SelBin)) = '1' and ieof(to_integer(SelBin)) = '1' then SelBin <= (others => '-'); Active <= '0'; end if; end if; end if; end if; end if; end process; odat <= (others => 'X') when Is_X(std_logic_vector(SelBin)) else idat(to_integer(SelBin)); oeof <= 'X' when Is_X(std_logic_vector(SelBin)) else ieof(to_integer(SelBin)); genGots: for i in 0 to N-1 generate igot(i) <= '0' when Active = '0' else '0' when oful = '1' else 'X' when Is_X(std_logic_vector(SelBin)) else '0' when SelBin /= to_unsigned(i, SelBin'length) else ivld(i); end generate genGots; oput <= Active and ivld(to_integer(SelBin)) and not oful; -- Arbitration blkArbit: block is signal pass : std_logic_vector(0 to N-1); begin pass <= not ivld; arbit : arbit_forward generic map ( N => N ) port map ( tin => '1', have => (others => '0'), pass => pass, grnt => grnt, tout => tout ); end block; end rtl;

agpl-3.0

0cc0625fe5fbf56bc108f6be8db51760

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_consumption.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_consumption | -- | --------------------------------------------------------------------------------------------------- -- File wf_consumption.vhd | -- | -- Description The unit groups the main actions that regard data consumption. | -- It instantiates the units: | -- | -- o wf_cons_bytes_processor: for the handling of consumed RP_DAT data bytes (var_1, | -- var_2, var_rst, var_4) as they arrive from the | -- wf_fd_receiver (registration to the RAM or outputting | -- to the DAT_O). | -- | -- | -- o wf_cons_outcome : for the validation of the consumed frame at the end of | -- its arrival (in terms of FSS, CTRL, PDU_TYPE, Lgth & | -- CRC bytes). | -- | -- ___________________________________________________________ | -- | wf_consumption | | -- | | | -- | _____________________________________________ | | -- | | | | | -- | | wf_cons_outcome | | | -- | | | | | -- | |_____________________________________________| | | -- | | | -- | _____________________________________________ | | -- | | | | | -- | | wf_cons_bytes_processor | | | -- | | | | | -- | |_____________________________________________| | | -- |___________________________________________________________| | -- /\ | -- ___________________________________________________________ | -- | | | -- | wf_fd_receiver | | -- |___________________________________________________________| | -- /\ | -- ___________________________________________________________________ | -- O____________________________FIELDBUS______________________________O | -- | -- | -- Note: In the entity declaration of this unit, below each input signal, we mark | -- for which of the instantiated units it is essential. | -- | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 11/01/2011 | -- Version v0.01 | -- Depends on wf_reset_unit | -- wf_fd_receiver | -- wf_engine_control | ---------------- | -- Last changes | -- 01/2011 EG v0.01 first version | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_consumption --================================================================================================= entity wf_consumption is port( -- INPUTS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- used by: all the units slone_i : in std_logic; -- used by: wf_cons_bytes_processor for selecting the data storage (RAM or DAT_O bus) -- used by: wf_cons_outcome for the VAR2_RDY signal (stand-alone mode does not treat var_2) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- nanoFIP WorldFIP Settings subs_i : in std_logic_vector (7 downto 0); -- used by: wf_cons_outcome for checking if the 2 bytes of a var_rst match the station's addr -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- used by: all the units -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Signals from the wf_fd_receiver rx_byte_i : in std_logic_vector (7 downto 0); rx_byte_ready_p_i : in std_logic; -- used by: wf_cons_bytes_processor rx_fss_crc_fes_ok_p_i : in std_logic; rx_crc_wrong_p_i : in std_logic; -- used by: wf_cons_outcome -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- nanoFIP User Interface, WISHBONE Slave wb_clk_i : in std_logic; wb_adr_i : in std_logic_vector (8 downto 0); -- used by: wf_cons_bytes_processor for the managment of the Consumption RAM -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Signals from the wf_engine_control unit cons_bytes_excess_i : in std_logic; -- used by: wf_cons_outcome var_i : in t_var; -- used by: wf_cons_bytes_processor and wf_cons_outcome byte_index_i : in std_logic_vector (7 downto 0); -- used by: wf_cons_bytes_processor for the reception coordination -- used by: wf_cons_outcome for the validation of the LGTH byte -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Signal from the wf_jtag_controller unit jc_mem_adr_rd_i : in std_logic_vector (8 downto 0); -- used by: wf_cons_bytes_processor for the readings from the JC_cons memory ------------------------------------------------------------------------------------------------- -- OUTPUTS -- nanoFIP User Interface, NON-WISHBONE outputs var1_rdy_o : out std_logic; var2_rdy_o : out std_logic; -- nanoFIP User Interface, WISHBONE Slave outputs -- MODIFIED was (15 downto 0) data_o : out std_logic_vector (7 downto 0); -- Signals to the wf_production nfip_status_r_tler_p_o : out std_logic; -- Signals to the wf_reset_unit assert_rston_p_o : out std_logic; rst_nfip_and_fd_p_o : out std_logic; -- Signals to the wf_jtag_controller unit jc_start_p_o : out std_logic; jc_mem_data_o : out std_logic_vector (7 downto 0)); end entity wf_consumption; --================================================================================================= -- architecture declaration --================================================================================================= architecture struc of wf_consumption is signal s_cons_ctrl_byte, s_cons_pdu_byte, s_cons_lgth_byte : std_logic_vector (7 downto 0); signal s_cons_var_rst_byte_1, s_cons_var_rst_byte_2 : std_logic_vector (7 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Consumed Bytes Processing -- --------------------------------------------------------------------------------------------------- Consumption_Bytes_Processor : wf_cons_bytes_processor port map( uclk_i => uclk_i, nfip_rst_i => nfip_rst_i, slone_i => slone_i, byte_ready_p_i => rx_byte_ready_p_i, var_i => var_i, byte_index_i => byte_index_i, byte_i => rx_byte_i, wb_clk_i => wb_clk_i, wb_adr_i => wb_adr_i, jc_mem_adr_rd_i => jc_mem_adr_rd_i, -------------------------------------------------------- data_o => data_o, jc_mem_data_o => jc_mem_data_o, cons_ctrl_byte_o => s_cons_ctrl_byte, cons_pdu_byte_o => s_cons_pdu_byte, cons_lgth_byte_o => s_cons_lgth_byte, cons_var_rst_byte_1_o => s_cons_var_rst_byte_1, cons_var_rst_byte_2_o => s_cons_var_rst_byte_2); -------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- Consumption Outcome -- --------------------------------------------------------------------------------------------------- Consumption_Outcome : wf_cons_outcome port map( uclk_i => uclk_i, slone_i => slone_i, subs_i => subs_i, nfip_rst_i => nfip_rst_i, rx_fss_crc_fes_ok_p_i => rx_fss_crc_fes_ok_p_i, rx_crc_wrong_p_i => rx_crc_wrong_p_i, cons_bytes_excess_i => cons_bytes_excess_i, var_i => var_i, byte_index_i => byte_index_i, cons_ctrl_byte_i => s_cons_ctrl_byte, cons_pdu_byte_i => s_cons_pdu_byte, cons_lgth_byte_i => s_cons_lgth_byte, cons_var_rst_byte_1_i => s_cons_var_rst_byte_1, cons_var_rst_byte_2_i => s_cons_var_rst_byte_2, -------------------------------------------------------- var1_rdy_o => var1_rdy_o, var2_rdy_o => var2_rdy_o, jc_start_p_o => jc_start_p_o, nfip_status_r_tler_p_o => nfip_status_r_tler_p_o, assert_rston_p_o => assert_rston_p_o, rst_nfip_and_fd_p_o => rst_nfip_and_fd_p_o); -------------------------------------------------------- end architecture struc; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

0e69193c0ac8bafa0d8950d25eebe6c4

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fslt_4CACHE_W.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 2; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

0a6cee6f1e4dcfd1b230fcf676d1570d

malkadi/FGPU

bitstreams/settings_and_utilization/V2_2CUs_float_2AXI_2TAGM.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 1; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data por0s constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FSQRT_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

5aa3a36ecb5067802d37b7837eabf13a

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_no_fadd_area_estimation.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

e9fce07638289424dfbfba221bd247e3

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_float_max_mem.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

5ed2e06f8daedad12916d11f3d84aa0e

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_production.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_production | -- | --------------------------------------------------------------------------------------------------- -- File wf_production.vhd | -- | -- Description The unit groups the main actions that regard data production. | -- It instantiates the units: | -- | -- o wf_prod_bytes_retriever: that retrieves | -- o user-data bytes from : | -- - the Produced RAM or | -- - or the"nanoFIP User Interface,NON-WISHBONE"bus DAT_I -- - or the wf_jtag_controller unit | -- o PDU,CTRL bytes : from the WF_PACKAGE | -- o MPS,nFIP status: from the wf_status_bytes_gen | -- o LGTH byte : from the wf_prod_data_lgth_calc | -- and following the signals from the external unit, | -- wf_engine_control,forwards them to the wf_fd_transmitter| -- | -- o wf_status_bytes_gen : that receives information from the wf_consumption unit,| -- the "FIELDRIVE" & "User Interface,NON-WISHBONE" inputs | -- and outputs, and generates the nanoFIP and the MPS | -- status bytes | -- | -- o wf_prod_permit : that signals the user that user-data bytes can safely | -- be written to the memory or the DAT_I bus | -- | -- ___________________________________________________________ | -- | wf_production | | -- | | | -- | _________________________________ | | -- | | | | | -- | | wf_prod_permit | | | -- | |_________________________________| | | -- | | | -- | _________________________________ ________________ | | -- | | | | | | | -- | | wf_prod_bytes_retriever | < | wf_status_bytes| | | -- | | | | _gen | | | -- | |_________________________________| |________________| | | -- |___________________________________________________________| | -- \/ | -- ___________________________________________________________ | -- | | | -- | wf_fd_transmitter | | -- |___________________________________________________________| | -- \/ | -- ___________________________________________________________________ | -- 0_____________________________FIELDBUS______________________________O | -- | -- Note: In the entity declaration of this unit, below each input signal, we mark | -- which of the instantiated units needs it. | -- | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 6/2011 | -- Version v0.03 | -- Depends on wf_reset_unit | -- wf_consumption | -- wf_engine_control | -- wf_wb_controller | -- wf_model_constr_decoder | -- wf_jtag_controller | ---------------- | -- Last changes | -- 2/2011 v0.02 EG wf_serializer removed from this unit | -- 6/2011 v0.03 EG added wf_jtag_controller+handling | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_production --================================================================================================= entity wf_production is port( -- INPUTS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- used by: all the units slone_i : in std_logic; -- used by: wf_prod_bytes_retriever for the selection of data bytes from the RAM or the DAT_I -- used by: wf_status_bytes_gen because the MPS status is different in memory & stand-alone nostat_i : in std_logic; -- used by: wf_prod_bytes_retriever for the delivery or not of the nanoFIP status byte -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Signal from the wf_reset_unit unit nfip_rst_i : in std_logic; -- used by: all the units -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- nanoFIP User Interface, WISHBONE Slave wb_clk_i : in std_logic; wb_adr_i : in std_logic_vector (8 downto 0); wb_data_i : in std_logic_vector (7 downto 0); -- used by: wf_prod_bytes_retriever for the managment of the Production RAM -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Signal from the wf_wb_controller wb_ack_prod_p_i : in std_logic; -- used by: wf_prod_bytes_retriever for the latching of the wb_data_i -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- nanoFIP User Interface, NON-WISHBONE slone_data_i : in std_logic_vector (15 downto 0); -- used by: wf_prod_bytes_retriever for the bytes retrieval in stand-alone mode var1_acc_a_i : in std_logic; var2_acc_a_i : in std_logic; var3_acc_a_i : in std_logic; -- used by: wf_status_bytes_gen for the nanoFIP status byte, bits 2, 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- nanoFIP FIELDRIVE fd_txer_a_i : in std_logic; fd_wdgn_a_i : in std_logic; -- used by: wf_status_bytes_gen for the nanoFIP status byte, bits 6, 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Signals from the wf_jtag_controller unit jc_tdo_byte_i : in std_logic_vector (7 downto 0); -- used by: wf_prod_bytes_retriever for the bytes retrieval of a var_5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Signals from the wf_engine_control byte_index_i : in std_logic_vector (7 downto 0); data_lgth_i : in std_logic_vector (7 downto 0); byte_request_accept_p_i : in std_logic; var_i : in t_var; -- also used by: wf_prod_permit for the VAR3_RDY generation -- used by: wf_prod_bytes_retriever for the definition of the bytes to be delivered -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Signals from the wf_consumption var1_rdy_i : in std_logic; var2_rdy_i : in std_logic; nfip_status_r_fcser_p_i : in std_logic; nfip_status_r_tler_p_i : in std_logic; -- used by: wf_status_bytes_gen for the generation of the nanoFIP status byte, bits 2, 4, 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Signals from the wf_model_constr_decoder unit constr_id_dec_i : in std_logic_vector (7 downto 0); model_id_dec_i : in std_logic_vector (7 downto 0); -- used by: wf_prod_bytes_retriever for the production of a var_identif ------------------------------------------------------------------------------------------------- -- OUTPUTS -- Signal to the wf_FD_transmitter byte_o : out std_logic_vector (7 downto 0); -- nanoFIP User Interface, NON-WISHBONE outputs u_cacer_o : out std_logic; r_fcser_o : out std_logic; u_pacer_o : out std_logic; r_tler_o : out std_logic; var3_rdy_o : out std_logic); end entity wf_production; --================================================================================================= -- architecture declaration --================================================================================================= architecture struc of wf_production is signal s_var3_rdy : std_logic; signal s_rst_status_bytes_p : std_logic; signal s_nfip_stat, s_mps : std_logic_vector (7 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Production Permit -- --------------------------------------------------------------------------------------------------- -- Instantiation of the wf_prod_permit unit production_VAR3_RDY_generation: wf_prod_permit port map( uclk_i => uclk_i, nfip_rst_i => nfip_rst_i, var_i => var_i, ----------------------------------------------- var3_rdy_o => s_var3_rdy); ----------------------------------------------- --------------------------------------------------------------------------------------------------- -- Bytes retrieval -- --------------------------------------------------------------------------------------------------- -- Instantiation of the wf_prod_bytes_retriever unit production_bytes_retriever : wf_prod_bytes_retriever port map( uclk_i => uclk_i, model_id_dec_i => model_id_dec_i, constr_id_dec_i => constr_id_dec_i, slone_i => slone_i, nostat_i => nostat_i, nfip_rst_i => nfip_rst_i, wb_clk_i => wb_clk_i, wb_adr_i => wb_adr_i, wb_ack_prod_p_i => wb_ack_prod_p_i, nFIP_status_byte_i => s_nfip_stat, mps_status_byte_i => s_mps, var_i => var_i, byte_index_i => byte_index_i, byte_being_sent_p_i => byte_request_accept_p_i, data_lgth_i => data_lgth_i, wb_data_i => wb_data_i, slone_data_i => slone_data_i, var3_rdy_i => s_var3_rdy, jc_tdo_byte_i => jc_tdo_byte_i, ----------------------------------------------- rst_status_bytes_p_o => s_rst_status_bytes_p, byte_o => byte_o); ----------------------------------------------- --------------------------------------------------------------------------------------------------- -- Status Byte Generation -- --------------------------------------------------------------------------------------------------- -- Instantiation of the wf_status_bytes_gen unit production_status_bytes_generator : wf_status_bytes_gen port map( uclk_i => uclk_i, nfip_rst_i => nfip_rst_i, slone_i => slone_i, fd_wdgn_a_i => fd_wdgn_a_i, fd_txer_a_i => fd_txer_a_i, nfip_status_r_fcser_p_i => nfip_status_r_fcser_p_i, var1_rdy_i => var1_rdy_i, var2_rdy_i => var2_rdy_i, var3_rdy_i => s_var3_rdy, var1_acc_a_i => var1_acc_a_i, var2_acc_a_i => var2_acc_a_i, var3_acc_a_i => var3_acc_a_i, nfip_status_r_tler_p_i => nfip_status_r_tler_p_i, rst_status_bytes_p_i => s_rst_status_bytes_p, var_i => var_i, ----------------------------------------------- u_cacer_o => u_cacer_o, u_pacer_o => u_pacer_o, r_tler_o => r_tler_o, r_fcser_o => r_fcser_o, nFIP_status_byte_o => s_nfip_stat, mps_status_byte_o => s_mps); ----------------------------------------------- var3_rdy_o <= s_var3_rdy; end architecture struc; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

aca8e09c1329fc1f32612aa3d6a5cd3d

kennethlyn/fpga-image-example

hdl_nodes/subtractor/subtractor.srcs/sources_1/dyplo_fifo.vhd

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gpl-2.0

2f9a1edb686998dd827e47ad6b8223a9

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_SubInteger_2AXI_2TAGM.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 1; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

3ecf309c071f6dea0543e1292c5db3cc

preusser/q27

src/vhdl/PoC/io/io_FanControl.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Patrick Lehmann -- -- Module: Generic Fan Controller -- -- Description: -- ------------------------------------ -- This module generates a PWM signal for a 3-pin (transistor controlled) or -- 4-pin fan header. The FPGAs temperature is read from device specific system -- monitors (normal, user temperature, over temperature). -- -- For example the Xilinx System Monitors are configured as follows: -- -- | /-----\ -- Temp_ov on=80 | - - - - - - /-------/ \ -- | / | \ -- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ -- | / | \ -- | / | | \ -- Temp_us on=35 | - /---/ | | \ -- Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\ -- | / | | | \ -- ----------------|--------|------------|--------------|----------|--------- -- pwm = | min | medium | max | medium | min -- -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.STD_LOGIC_1164.all; library PoC; use PoC.config.all; use PoC.utils.all; use PoC.vectors.all; use PoC.physical.all; use PoC.components.all; use PoC.xil.all; entity io_FanControl is generic ( CLOCK_FREQ : FREQ; ADD_INPUT_SYNCHRONIZERS : BOOLEAN := TRUE; ENABLE_TACHO : BOOLEAN := FALSE ); port ( -- Global Control Clock : in STD_LOGIC; Reset : in STD_LOGIC; -- Fan Control derived from internal System Health Monitor Fan_PWM : out STD_LOGIC; -- Decoding of Speed Sensor (Requires ENABLE_TACHO) Fan_Tacho : in std_logic := 'X'; TachoFrequency : out std_logic_vector(15 downto 0) ); end; architecture rtl of io_FanControl is -- constant TIME_STARTUP : TIME := 500 ms; -- StartUp time -- Use frequencies only to make Vivado work. constant TIME_STARTUP_INVERSE : FREQ := 2 Hz; -- StartUp time constant PWM_RESOLUTION : POSITIVE := 4; -- 4 Bit resolution => 0 to 15 steps constant PWM_FREQ : FREQ := 10 Hz; -- constant TACHO_RESOLUTION : POSITIVE := 8; signal PWM_PWMIn : STD_LOGIC_VECTOR(PWM_RESOLUTION - 1 downto 0); signal PWM_PWMOut : STD_LOGIC := '0'; begin -- System Monitor and temperature to PWM ratio calculation for Virtex6 -- ========================================================================================================================================================== genXilinx : if (VENDOR = VENDOR_XILINX) generate signal OverTemperature_async : STD_LOGIC; signal OverTemperature_sync : STD_LOGIC; signal UserTemperature_async : STD_LOGIC; signal UserTemperature_sync : STD_LOGIC; signal TC_Timeout : STD_LOGIC; signal StartUp : STD_LOGIC; begin genML605 : if (BOARD = BOARD_ML605) generate SystemMonitor : xil_SystemMonitor_Virtex6 port map ( Reset => Reset, -- Reset signal for the System Monitor control logic Alarm_UserTemp => UserTemperature_async, -- Temperature-sensor alarm output Alarm_OverTemp => OverTemperature_async, -- Over-Temperature alarm output Alarm => open, -- OR'ed output of all the Alarms VP => '0', -- Dedicated Analog Input Pair VN => '0' ); end generate; genSeries7Board : if ((BOARD = BOARD_KC705) or (BOARD = BOARD_VC707)) generate SystemMonitor : xil_SystemMonitor_Series7 port map ( Reset => Reset, -- Reset signal for the System Monitor control logic Alarm_UserTemp => UserTemperature_async, -- Temperature-sensor alarm output Alarm_OverTemp => OverTemperature_async, -- Over-Temperature alarm output Alarm => open, -- OR'ed output of all the Alarms VP => '0', -- Dedicated Analog Input Pair VN => '0' ); end generate; sync : entity PoC.sync_Bits generic map ( BITS => 2 ) port map ( Clock => Clock, Input(0) => OverTemperature_async, Input(1) => UserTemperature_async, Output(0) => OverTemperature_sync, Output(1) => UserTemperature_sync ); -- timer for warm-up control -- ========================================================================================================================================================== TC : entity PoC.io_TimingCounter generic map ( TIMING_TABLE => (0 => CLOCK_FREQ/TIME_STARTUP_INVERSE) -- timing table ) port map ( Clock => Clock, -- clock Enable => StartUp, -- enable counter Load => '0', -- load Timing Value from TIMING_TABLE selected by slot Slot => 0, -- Timeout => TC_Timeout -- timing reached ); StartUp <= not TC_Timeout; process(StartUp, UserTemperature_sync, OverTemperature_sync) begin if (StartUp = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%; start up elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100% elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50% else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13% end if; end process; end generate; genAltera : if (VENDOR = VENDOR_ALTERA) generate -- signal OverTemperature_async : STD_LOGIC; signal OverTemperature_sync : STD_LOGIC; -- signal UserTemperature_async : STD_LOGIC; signal UserTemperature_sync : STD_LOGIC; signal TC_Timeout : STD_LOGIC; signal StartUp : STD_LOGIC; begin genDE4 : if (BOARD = BOARD_DE4) generate OverTemperature_sync <= '0'; UserTemperature_sync <= '1'; end generate; -- timer for warm-up control -- ========================================================================================================================================================== TC : entity PoC.io_TimingCounter generic map ( TIMING_TABLE => (0 => CLOCK_FREQ/TIME_STARTUP_INVERSE) -- timing table ) port map ( Clock => Clock, -- clock Enable => StartUp, -- enable counter Load => '0', -- load Timing Value from TIMING_TABLE selected by slot Slot => 0, -- Timeout => TC_Timeout -- timing reached ); StartUp <= not TC_Timeout; process(StartUp, UserTemperature_sync, OverTemperature_sync) begin if (StartUp = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%; start up elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100% elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50% else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13% end if; end process; end generate; -- PWM signal modulator -- ========================================================================================================================================================== PWM : entity PoC.io_PulseWidthModulation generic map ( CLOCK_FREQ => CLOCK_FREQ, -- PWM_FREQ => PWM_FREQ, -- PWM_RESOLUTION => PWM_RESOLUTION -- ) port map ( Clock => Clock, Reset => Reset, PWMIn => PWM_PWMIn, PWMOut => PWM_PWMOut ); -- registered output Fan_PWM <= PWM_PWMOut when rising_edge(Clock); -- tacho signal interpretation -> convert to RPM -- ========================================================================================================================================================== genNoTacho : if (ENABLE_TACHO = FALSE) generate TachoFrequency <= (TachoFrequency'range => 'X'); end generate; genTacho : if (ENABLE_TACHO = TRUE) generate signal Tacho_sync : STD_LOGIC; signal Tacho_Freq : STD_LOGIC_VECTOR(TACHO_RESOLUTION - 1 downto 0); begin -- Input Synchronization genNoSync : if (ADD_INPUT_SYNCHRONIZERS = FALSE) generate Tacho_sync <= Fan_Tacho; end generate; genSync : if (ADD_INPUT_SYNCHRONIZERS = TRUE) generate sync_i : entity PoC.sync_Bits port map ( Clock => Clock, -- Clock to be synchronized to Input(0) => Fan_Tacho, -- Data to be synchronized Output(0) => Tacho_sync -- synchronised data ); end generate; Tacho : entity PoC.io_FrequencyCounter generic map ( CLOCK_FREQ => CLOCK_FREQ, -- TIMEBASE => (60 sec / 64), -- ca. 1 second RESOLUTION => 8 -- max. ca. 256 RPS -> max. ca. 16k RPM ) port map ( Clock => Clock, Reset => Reset, FreqIn => Tacho_sync, FreqOut => Tacho_Freq ); -- multiply by 64; divide by 2 for RPMs (2 impulses per revolution) => append 5x '0' TachoFrequency <= resize(Tacho_Freq & "00000", TachoFrequency'length); -- resizing to 16 bit end generate; end;

agpl-3.0

d37c426e8f76de604598a6b32e4cb1bf

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_fdiv_max.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

b6835f6abf369be1377ebb5827de4b65

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_2AXI_2TAGM.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

effd6a398cf82b085cfa3be5724889e1

alvieboy/iotpanel

cpld/iotpanel.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity iotpanel is port ( clk: in std_logic; cs: inout std_logic; --di: in std_logic; rgb: out std_logic_vector(5 downto 0); col: out std_logic_vector(3 downto 0); stb: out std_logic; clko: out std_logic; --idtr: in std_logic; gpio13: in std_logic; gpio14: in std_logic; espreset: out std_logic; espen: inout std_logic; esptx: in std_logic; esprx: out std_logic; gpio2: inout std_logic; gpio0: inout std_logic; gpio5: inout std_logic; gpio4: inout std_logic; --espchpd: out std_logic; gpio16: inout std_logic; gpio12: inout std_logic; oe: inout std_logic; panelen: inout std_logic; usr: inout std_logic_vector(6 downto 3); iusr: in std_logic ); end iotpanel; architecture Behavioral of iotpanel is signal shifter: std_logic_vector(9 downto 0); alias irx: std_logic is usr(5); alias idtr:std_logic is usr(4); signal internal_reset_q: std_logic; signal hclock: std_logic; signal data_queued: std_logic; signal internalcs: std_logic; alias di: std_logic is gpio13; begin -- CH_PD Pull-up -- GPIO16/RST Pull-up -- GPIO15 Pull-down -- GPIO2 Pull-up -- GPIO0 Pull-up for normal or pull-down for bootloader mode. gpio2 <= 'Z'; -- External pullup --gpio0 <= not irx; -- RX from external programmer. gpio0 <= usr(3); gpio16 <= 'Z'; -- External pullup gpio12 <= 'Z'; gpio5 <= 'Z'; cs <= '0' when gpio16='1' else 'Z'; -- Startup/Working CS mode. -- CS is now gpio4 internalcs <= gpio4 when gpio16='0' else '1'; -- Ignore commands when SW not running. --usr(3) <= gpio4;--'Z'; esprx <= usr(5); usr(6) <= esptx; oe <= gpio5 when gpio16='0' else '1'; panelen <= 'Z'; -- not used yet espen <= 'Z'; -- not used yet espreset<='0' when idtr='1' else '1'; --espen<='0' when idtr='0' and irx='1' else '1'; stb <= gpio12; --stb <= clk; --clko <= gpio14; process(clk,internalcs) begin if internalcs='1' then shifter <= (others => '0'); elsif rising_edge(clk) then if internal_reset_q='1' then shifter(8 downto 2) <= (others => '0'); shifter(1) <= shifter(0); shifter(0) <= di; else shifter <= shifter(shifter'HIGH-1 downto 0) & di; end if; end if; end process; --clko <= shifter(8); clko <= hclock; process(clk,internalcs) begin if internalcs='1' then internal_reset_q<='0'; data_queued<='0'; elsif rising_edge(clk) then if internal_reset_q='1' then internal_reset_q<='0'; else internal_reset_q <= shifter(8); if shifter(8)='1' then data_queued<='1'; end if; end if; if hclock='1' then data_queued<='0'; end if; end if; end process; process(clk,internalcs) begin if internalcs='1' then hclock<='0'; elsif rising_edge(clk) then if shifter(8 downto 6)="001" then hclock<='0'; else --if internal_reset_q='1' then if data_queued='1' and shifter(3)='1' and internal_reset_q='0' then hclock <= '1'; end if; end if; end if; end process; process(clk) begin if rising_edge(clk) then if shifter(8 downto 6)="001" then rgb <= shifter(4 downto 0) & di; end if; end if; end process; process(gpio4) begin if rising_edge(gpio4) then if shifter(8)='0' then col <= shifter(3 downto 0); end if; end if; end process; end Behavioral;

lgpl-3.0

8c8c4bf8f3915b5cfdb1762ece425955

wltr/cern-fgclite

critical_fpga/src/rtl/cf/sefi_detector.vhd

------------------------------------------------------------------------------- --! @file sefi_detector.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-11-19 --! @brief Detect SEFI on external inputs. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.lfsr_pkg.all; --! @brief Entity declaration of sefi_detector --! @details --! Detect a Single Event Functional Interrupt (SEFI) on an external input. entity sefi_detector is generic ( --! Number of stages to check num_g : positive := 10); port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name SEFI signals --! @{ --! Enable en_i : in std_ulogic; --! Input sig_i : in std_ulogic; --! Output sefi_o : out std_ulogic); --! @} end entity sefi_detector; --! RTL implementation of sefi_detector architecture rtl of sefi_detector is --------------------------------------------------------------------------- -- Types and Constants --------------------------------------------------------------------------- -- LFSR counter bit length constant len_c : natural := lfsr_length(num_g); -- LFSR counter initial value constant seed_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_seed(len_c); -- LFSR counter max value constant max_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_shift(seed_c, num_g - 1); --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal count : std_ulogic_vector(len_c - 1 downto 0); signal sig : std_ulogic; signal sefi : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- sefi_o <= sefi; --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin count <= seed_c; sig <= '0'; sefi <= '0'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else if en_i = '1' then sig <= sig_i; if sig_i = sig then count <= lfsr_shift(count); else count <= seed_c; end if; end if; if count = max_c then sefi <= '1'; count <= seed_c; end if; end if; end if; end process regs; end architecture rtl;

mit

14cf8aade39e94f41b5e798db34064fb

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_fadd_fmul_fdiv_fsqrt_6_2_1_2.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 6; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

fd9079998654f6ed6c90171e409dc849

joalcava/sparcv8-monocicle

alu.vhd

library IEEE; use IEEE.NUMERIC_STD.ALL; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity alu is Port( carry: in STD_LOGIC; aluop : in STD_LOGIC_VECTOR (5 downto 0); crs1 : in STD_LOGIC_VECTOR (31 downto 0); crs2 : in STD_LOGIC_VECTOR (31 downto 0); r : out STD_LOGIC_VECTOR (31 downto 0) ); end alu; architecture ArqAlu of alu is begin process(aluop, crs1, crs2,carry) begin if (aluop="000000") or (aluop="001000") then --Add Operations r <= crs1 + crs2; elsif (aluop="001010") or (aluop="001011") then --AddX Operations r<=crs1 +crs2 + carry; elsif (aluop="000001") or (aluop="001001") then --Sub Operations r <= crs1 - crs2 ; elsif (aluop="001100") or (aluop="001101") then --SubX Operations r<=crs1 - crs2 - carry; elsif (aluop="000010") or (aluop="001110") then --Or Operations r <= crs1 or crs2; elsif (aluop="000011") or (aluop="001111") then --And Operations r <= crs1 and crs2; elsif (aluop="000101") or (aluop="010010") then --OrN Operations r <= crs1 or not(crs2); elsif (aluop="000100") or (aluop="010000") then --Xor Operations r <= crs1 xor crs2; elsif (aluop="000110") or (aluop="010001") then --AndN Operations r <= crs1 and not(crs2); elsif (aluop="000111") or (aluop="010011") then --Xnor Operations r <= crs1 xnor crs2; elsif (aluop="010100")then --SLL r<= to_stdlogicvector(to_bitvector(crs1) SLL conv_integer(crs2)); elsif (aluop="010101")then --SRL r<= to_stdlogicvector(to_bitvector(crs1) SRL conv_integer(crs2)); else r<=x"00000000"; end if; end process; end ArqAlu;

gpl-3.0

9b28cd128297fc03cbdb6e6aa1fac4aa

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_Atomic_SubInteger.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant SUB_INTEGER_IMPLEMENT : natural := 1; -- implement sub-integer store operations constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant ATOMIC_IMPLEMENT : natural := 1; constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

9c6d3b57ce34f54ad593156e82b0f7f9

jpidancet/mips

rtl/cpu_decode.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; library work; use work.mips_defs.ALL; entity cpu_decode is port (instr : in std_logic_vector(31 downto 0); pcplus4 : in std_logic_vector(31 downto 0); rs_n : out std_logic_vector(4 downto 0); rt_n : out std_logic_vector(4 downto 0); rd_n : out std_logic_vector(4 downto 0); shamt_n : out std_logic_vector(4 downto 0); imm_n : out std_logic_vector(31 downto 0); alusrc_n : out std_logic; regdst_n : out std_logic; alucontrol_n : out alucontrol_type; ovf_en_n : out std_logic; regwrite_n : out std_logic; memtoreg_n : out std_logic; memread_n : out std_logic; memwrite_n : out std_logic; rd1_n : out std_logic_vector(31 downto 0); rd2_n : out std_logic_vector(31 downto 0); pcsrc_n : out std_logic; branch_n : out std_logic; pcbranch_n : out std_logic_vector(31 downto 0); -- Forward forward_a : in std_logic; forward_b : in std_logic; aluout_fwd : in std_logic_vector(31 downto 0); -- Register file reg_a1 : out std_logic_vector(4 downto 0); reg_a2 : out std_logic_vector(4 downto 0); reg_rd1 : in std_logic_vector(31 downto 0); reg_rd2 : in std_logic_vector(31 downto 0)); end entity cpu_decode; architecture rtl of cpu_decode is component decoder is port (op : in std_logic_vector(5 downto 0); func : in std_logic_vector(5 downto 0); reg_write : out std_logic; mem_to_reg : out std_logic; mem_read : out std_logic; mem_write : out std_logic; branch : out branch_type; alucontrol : out alucontrol_type; ovf_en : out std_logic; cmp : out compare_type; alu_src : out std_logic; reg_dst : out std_logic; imm_extend : out extend_type; link : out std_logic; rd31 : out std_logic); end component decoder; signal imm : std_Logic_vector(31 downto 0); signal branch : branch_type; signal imm_extend : extend_type; signal cmp_res : std_logic; signal cmp_op : compare_type; signal cmpval_a, cmpval_b : std_logic_vector(31 downto 0); signal link : std_logic; signal rd31 : std_logic; -- force rd=31 begin process (instr, imm_extend) begin case imm_extend is when ZERO_EXTEND => imm <= std_logic_vector(resize(unsigned(instr(15 downto 0)), 32)); when SIGN_EXTEND => imm <= std_logic_vector(resize(signed(instr(15 downto 0)), 32)); when SHIFT16_EXTEND => imm <= instr(15 downto 0) & "0000000000000000"; end case; end process; rs_n <= instr(25 downto 21); rt_n <= instr(20 downto 16); rd_n <= "11111" when rd31 = '1' else instr(15 downto 11); shamt_n <= instr(10 downto 6); rd1_n <= reg_rd1; rd2_n <= pcplus4 when link = '1' else reg_rd2; reg_a1 <= instr(25 downto 21); reg_a2 <= instr(20 downto 16); imm_n <= imm; cmpval_a <= aluout_fwd when forward_a = '1' else reg_rd1; cmpval_b <= aluout_fwd when forward_b = '1' else reg_rd2; decoder0: decoder port map (op => instr(31 downto 26), func => instr(5 downto 0), reg_write => regwrite_n, mem_to_reg => memtoreg_n, mem_read => memread_n, mem_write => memwrite_n, branch => branch, alucontrol => alucontrol_n, ovf_en => ovf_en_n, cmp => cmp_op, alu_src => alusrc_n, reg_dst => regdst_n, imm_extend => imm_extend, link => link, rd31 => rd31); process (cmp_op, cmpval_a, cmpval_b) variable res : boolean := false; begin case cmp_op is when CMP_EQUAL => res := cmpval_a = cmpval_b; when CMP_NOT_EQUAL => res := cmpval_a /= cmpval_b; when CMP_GREATER => res := cmpval_a > cmpval_b; when CMP_GREATER_OR_EQUAL => res := cmpval_a >= cmpval_b; when CMP_LESS => res := cmpval_a < cmpval_b; when CMP_LESS_OR_EQUAL => res := cmpval_a <= cmpval_b; when others => end case; if res then cmp_res <= '1'; else cmp_res <= '0'; end if; end process; process (pcplus4, instr, branch, imm, cmpval_a, cmp_res) begin case branch is when NO_BRANCH => pcbranch_n <= (others => '0'); branch_n <= '0'; pcsrc_n <= '0'; when BRANCH_COND => pcbranch_n <= std_logic_vector(unsigned(pcplus4) + unsigned(imm(29 downto 0) & "00")); branch_n <= '1'; pcsrc_n <= cmp_res; when JUMP_IMM => pcbranch_n <= pcplus4(31 downto 28) & instr(25 downto 0) & "00"; branch_n <= '0'; pcsrc_n <= '1'; when JUMP_REG => pcbranch_n <= cmpval_a; -- Use forwarded value when possible branch_n <= '1'; pcsrc_n <= '1'; end case; end process; end architecture rtl;

isc

30b07611f2918fbfd474383ab381650a

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_6Stations_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 6; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

353ce29e65cf9053714810bb1f5e925f

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_2AXI_4CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 2; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

2b9516078ccdb51e3b3d456a5cd0278d

kennethlyn/fpga-image-example

hdl_nodes/subtractor/subtractor.srcs/sources_1/dyplo_hdl_node.vhd

-- File: dyplo_hdl_node.vhd -- -- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED. -- -- This file contains confidential and proprietary information of -- Topic Embedded Products B.V. and is protected under Dutch and -- International copyright and other international intellectual property laws. -- -- Disclaimer -- -- This disclaimer is not a license and does not grant any rights to the -- materials distributed herewith. Except as otherwise provided in a valid -- license issued to you by Topic Embedded Products B.V., and to the maximum -- extend permitted by applicable law: -- -- 1. Dyplo is furnished on an "as is", as available basis. Topic makes no -- warranty, express or implied, with respect to the capability of Dyplo. All -- warranties of any type, express or implied, including the warranties of -- merchantability, fitness for a particular purpose and non-infringement of -- third party rights are expressly disclaimed. -- -- 2. Topic's maximum total liability shall be limited to general money -- damages in an amount not to exceed the total amount paid for in the year -- in which the damages have occurred. Under no circumstances including -- negligence shall Topic be liable for direct, indirect, incidental, special, -- consequential or punitive damages, or for loss of profits, revenue, or data, -- that are directly or indirectly related to the use of, or the inability to -- access and use Dyplo and related services, whether in an action in contract, -- tort, product liability, strict liability, statute or otherwise even if -- Topic has been advised of the possibility of those damages. -- -- This copyright notice and disclaimer must be retained as part of this file at all times. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; library dyplo_hdl_node_lib; use dyplo_hdl_node_lib.hdl_node_package.all; use dyplo_hdl_node_lib.hdl_node_user_params.all; library user_logic; use user_logic.all; entity dyplo_hdl_node is port( -- Miscellaneous node_id : in std_logic_vector(c_hdl_node_id_width - 1 downto 0); -- DAB interface dab_clk : in std_logic; dab_rst : in std_logic; dab_addr : in std_logic_vector(c_hdl_dab_awidth - 1 downto 0); dab_sel : in std_logic; dab_wvalid : in std_logic; dab_rvalid : in std_logic; dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); -- Receive data from backplane to FIFO b2f_tdata : in std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0); b2f_tstream_id : in std_logic_vector(c_hdl_stream_id_width - 1 downto 0); b2f_tvalid : in std_logic; b2f_tready : out std_logic; -- Send data from FIFO to backplane f2b_tdata : out std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0); f2b_tstream_id : out std_logic_vector(c_hdl_stream_id_width - 1 downto 0); f2b_tvalid : out std_logic; f2b_tready : in std_logic; -- Serial fifo status info fifo_status_sync : in std_logic; fifo_status_flag : out std_logic; -- fifo statuses of destination fifo's dest_fifo_status : in std_logic_vector(3 downto 0); -- Clock signals user_clocks : in std_logic_vector(3 downto 0) ); attribute secure_config : string; attribute secure_config of dyplo_hdl_node : entity is "PROTECT"; attribute secure_netlist : string; attribute secure_netlist of dyplo_hdl_node : entity is "ENCRYPT"; attribute secure_net_editing : string; attribute secure_net_editing of dyplo_hdl_node : entity is "PROHIBIT"; attribute secure_net_probing : string; attribute secure_net_probing of dyplo_hdl_node : entity is "PROHIBIT"; end dyplo_hdl_node; architecture rtl of dyplo_hdl_node is component dyplo_user_logic_subtractor is generic( INPUT_STREAMS : integer := 4; OUTPUT_STREAMS : integer := 4 ); port( -- Processor bus interface dab_clk : in std_logic; dab_rst : in std_logic; dab_addr : in std_logic_vector(15 downto 0); dab_sel : in std_logic; dab_wvalid : in std_logic; dab_rvalid : in std_logic; dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); -- Streaming input interfaces cin_tdata : in cin_tdata_ul_type; cin_tvalid : in std_logic_vector(INPUT_STREAMS - 1 downto 0); cin_tready : out std_logic_vector(INPUT_STREAMS - 1 downto 0); cin_tlevel : in cin_tlevel_ul_type; -- Streaming output interfaces cout_tdata : out cout_tdata_ul_type; cout_tvalid : out std_logic_vector(OUTPUT_STREAMS - 1 downto 0); cout_tready : in std_logic_vector(OUTPUT_STREAMS - 1 downto 0); -- Clock signals user_clocks : in std_logic_vector(3 downto 0) ); end component dyplo_user_logic_subtractor; signal dab_sel_ul : std_logic; signal dab_wvalid_ul : std_logic; signal dab_rvalid_ul : std_logic; signal dab_rdata_ul : std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); signal cin_tdata_i : cin_tdata_ul_type; signal cin_tvalid_i : std_logic_vector(c_input_streams - 1 downto 0); signal cin_tready_i : std_logic_vector(c_input_streams - 1 downto 0); signal cin_tlevel_i : cin_tlevel_ul_type; signal cout_tdata_i : cout_tdata_ul_type; signal cout_tvalid_i : std_logic_vector(c_output_streams - 1 downto 0); signal cout_tready_i : std_logic_vector(c_output_streams - 1 downto 0); begin ----------------------------------------------------------------------------- -- CONTROL MEMORY MAP FOR CPU FIFO INTERFACE -- ----------------------------------------------------------------------------- -- The available memory range for the CPU fifo control is limited to -- -- 64Kbyte/32 = 2Kbytes or 512 words. The maximum burst transfer of the -- -- AXI bus is 256 words. The actual FIFO data memory range is also limited -- -- to 64Kbytes or 16Kwords. Also, the space is divided between reading and -- -- writing. This leaves 8Kwords per direction and with a burst length of -- -- 256 words, maximum 32 input streams and 32 output streams can be -- -- supported. -- ----------------------------------------------------------------------------- -- Each fifo has the following metrics: -- -- - FIFO full and FIFO empty flag -- -- - FIFO fill level compare register and compare flag -- -- - Actual FIFO fill level indicator -- -- - Under/overflow detection flag when operating FIFO out of range -- -- -- -- Per input FIFO (from FPGA fabric to the CPU) it is required to specify -- -- the stream source. Also, a maskable interrupt should be issued per -- -- input FIFO to signal the need to empty the FIFO by the CPU. -- ----------------------------------------------------------------------------- dyplo_hdl_node_logic_i : dyplo_hdl_node_logic generic map ( INPUT_STREAMS => c_input_streams, OUTPUT_STREAMS => c_output_streams ) port map( -- Miscellaneous node_id => node_id, -- DAB interface dab_clk => dab_clk, dab_rst => dab_rst, dab_addr => dab_addr, dab_sel => dab_sel, dab_wvalid => dab_wvalid, dab_rvalid => dab_rvalid, dab_wdata => dab_wdata, dab_rdata => dab_rdata, -- Receive data from backplane to FIFO b2f_tdata => b2f_tdata, b2f_tstream_id => b2f_tstream_id, b2f_tvalid => b2f_tvalid, b2f_tready => b2f_tready, -- Send data from FIFO to backplane f2b_tdata => f2b_tdata, f2b_tstream_id => f2b_tstream_id, f2b_tvalid => f2b_tvalid, f2b_tready => f2b_tready, -- Serial fifo status info fifo_status_sync => fifo_status_sync, fifo_status_flag => fifo_status_flag, -- fifo statuses of destination fifo's dest_fifo_status => dest_fifo_status(c_output_streams - 1 downto 0), -- DAB interface to user logic dab_sel_ul => dab_sel_ul, dab_wvalid_ul => dab_wvalid_ul, dab_rvalid_ul => dab_rvalid_ul, dab_rdata_ul => dab_rdata_ul, -- In streams to user logic cin_tdata_ul => cin_tdata_i, cin_tvalid_ul => cin_tvalid_i, cin_tready_ul => cin_tready_i, cin_tlevel_ul => cin_tlevel_i, -- Out streams from user logic cout_tdata_ul => cout_tdata_i, cout_tvalid_ul => cout_tvalid_i, cout_tready_ul => cout_tready_i ); dyplo_user_logic_i : dyplo_user_logic_subtractor generic map( INPUT_STREAMS => c_input_streams, OUTPUT_STREAMS => c_output_streams ) port map( -- Processor bus interface dab_clk => dab_clk, dab_rst => dab_rst, dab_addr => dab_addr(15 downto 0), dab_sel => dab_sel_ul, dab_wvalid => dab_wvalid_ul, dab_rvalid => dab_rvalid_ul, dab_wdata => dab_wdata, dab_rdata => dab_rdata_ul, -- Streaming input interfaces cin_tdata => cin_tdata_i, cin_tvalid => cin_tvalid_i, cin_tready => cin_tready_i, cin_tlevel => cin_tlevel_i, -- Streaming output interfaces cout_tdata => cout_tdata_i, cout_tvalid => cout_tvalid_i, cout_tready => cout_tready_i, -- Clock signals user_clocks => user_clocks ); end rtl;

gpl-2.0

d04599306139ab8e87fb8c4988e862bb

Kinxil/VHDL_Projects

Mandelbrot/Shared.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; package CONSTANTS is -- Param -- constant PARAM_DELAY : integer := 50000000; --~500ms -- Fixed format -- constant FIXED : INTEGER := 28; --Number of bits for , part -- Data size -- constant XY_RANGE : INTEGER := 32; --Number of bits for x and y data constant ITER_MAX : INTEGER := 4095; --Max number of iteration constant ITER_RANGE : INTEGER := 12; constant QUATRE : SIGNED (XY_RANGE-1 downto 0) := to_signed(4,32) sll FIXED ; constant bit_per_pixel : integer := 12; constant COLOR_MAX : integer := 2047; end CONSTANTS; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; package FUNCTIONS is function mult(A : STD_LOGIC_VECTOR; B : STD_LOGIC_VECTOR; QF : integer) return STD_LOGIC_VECTOR; function mult(A : SIGNED; B : SIGNED; QF : integer) return SIGNED; end FUNCTIONS; package body FUNCTIONS is --Maths functions function mult(A : SIGNED; B : SIGNED; QF : integer) return SIGNED is CONSTANT DMAX_R : integer := A'LENGTH + B'LENGTH; CONSTANT PHI : integer := A'LENGTH - QF; VARIABLE r : SIGNED(DMAX_R-1 DOWNTO 0); begin r := A*B; return r(DMAX_R - PHI - 1 downto QF); end mult; function mult(A : STD_LOGIC_VECTOR; B : STD_LOGIC_VECTOR; QF : integer) return STD_LOGIC_VECTOR is begin return STD_LOGIC_VECTOR(mult(SIGNED(A),SIGNED(B),QF)); end mult; end FUNCTIONS;

gpl-3.0

2015cce14f13ce5e7addd0bff55fb513

wltr/cern-fgclite

critical_fpga/src/rtl/cf/nf.vhd

------------------------------------------------------------------------------- --! @file nf.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-07-08 --! @brief NanoFIP communication and synchronization. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.nf_pkg.all; --! @brief Entity declaration of nf --! @details --! This component handles the NanoFIP communication and provides a --! synchronization mechanism with the field-bus cycle. entity nf is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Control signals --! @{ --! Start transmission tx_start_i : in std_ulogic; --! Received command number cmd_num_o : out std_ulogic_vector(1 downto 0); --! Received command number enable cmd_num_en_o : out std_ulogic; --! NanoFIP FPGA version nf_version_o : out std_ulogic_vector(3 downto 0); --! NanoFIP FPGA version enable nf_version_en_o : out std_ulogic; --! @} --! @name Debugging --! @{ --! Data output nf_debug_o : out std_ulogic_vector(7 downto 0); --! Data output enable nf_debug_en_o : out std_ulogic; --! @} --! @name NanoFIP interface --! @{ --! Inputs nf_i : in nf_in_t; --! Outputs nf_o : out nf_out_t; --! @} --! @name Registers --! @{ --! Gateway commands command_o : out nf_command_t; --! FGClite status status_i : in nf_status_t; --! @} --! @name Page --! @{ --! Address page_addr_i : in std_ulogic_vector(5 downto 0); --! Write enable page_wr_en_i : in std_ulogic; --! Data input page_data_i : in std_ulogic_vector(7 downto 0); --! Done flag page_done_o : out std_ulogic); --! @} end entity nf; --! RTL implementation of nf architecture rtl of nf is --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal rx_data : std_ulogic_vector(43 downto 0); signal rx_data_en : std_ulogic; signal tx_data : std_ulogic_vector(14 downto 0); signal tx_data_en : std_ulogic; signal tx_busy : std_ulogic; signal tx_done : std_ulogic; signal tx_reg_rd_en : std_ulogic; signal tx_reg_addr : std_ulogic_vector(5 downto 0); signal tx_reg_data : std_ulogic_vector(7 downto 0); signal tx_reg_data_en : std_ulogic; signal tx_mem_rd_en : std_ulogic; signal tx_mem_addr : std_ulogic_vector(5 downto 0); signal tx_mem_data : std_ulogic_vector(7 downto 0); signal tx_mem_data_en : std_ulogic; signal mem_rd_en : std_ulogic; signal mem_addr : std_ulogic_vector(6 downto 0); signal mem_data : std_ulogic_vector(7 downto 0); signal mem_data_en : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- cmd_num_o <= rx_data(33 downto 32); cmd_num_en_o <= rx_data_en; nf_debug_o <= tx_data(7 downto 0); nf_debug_en_o <= tx_data_en; nf_version_o <= rx_data(43 downto 40); nf_version_en_o <= rx_data_en; --------------------------------------------------------------------------- -- Signal Assignments --------------------------------------------------------------------------- tx_reg_rd_en <= mem_rd_en and mem_addr(6); tx_reg_addr <= mem_addr(5 downto 0); tx_mem_rd_en <= mem_rd_en and not mem_addr(6); tx_mem_addr <= mem_addr(5 downto 0); mem_data <= tx_reg_data when mem_addr(6) = '1' else tx_mem_data; mem_data_en <= tx_reg_data_en when mem_addr(6) = '1' else tx_mem_data_en; --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- --! 3-wire serial receiver from NF nf_rx_inst : entity work.serial_3wire_rx generic map ( data_width_g => 44) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, rx_frame_i => nf_i.rx_frame, rx_bit_en_i => nf_i.rx_bit_en, rx_i => nf_i.rx, data_o => rx_data, data_en_o => rx_data_en, error_o => open); --! 3-wire serial transmitter to NF nf_tx_inst : entity work.serial_3wire_tx generic map ( data_width_g => 15, num_ticks_g => 8) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, data_i => tx_data, data_en_i => tx_data_en, busy_o => tx_busy, done_o => tx_done, tx_frame_o => nf_o.tx_frame, tx_bit_en_o => nf_o.tx_bit_en, tx_o => nf_o.tx); --! NF receiver registers nf_rx_registers_inst : entity work.nf_rx_registers port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => '0', wr_en_i => rx_data_en, addr_i => rx_data(33 downto 32), data_i => rx_data(31 downto 0), command_o => command_o); --! NF transmitter registers nf_tx_registers_inst : entity work.nf_tx_registers port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, rd_en_i => tx_reg_rd_en, addr_i => tx_reg_addr, data_o => tx_reg_data, data_en_o => tx_reg_data_en, status_i => status_i); --! NF transmitter page nf_tx_page_inst : entity work.two_port_ram_tmr generic map ( depth_g => 64, width_g => 8) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, wr_addr_i => page_addr_i, wr_en_i => page_wr_en_i, wr_data_i => page_data_i, wr_done_o => page_done_o, wr_busy_o => open, rd_addr_i => tx_mem_addr, rd_en_i => tx_mem_rd_en, rd_data_o => tx_mem_data, rd_data_en_o => tx_mem_data_en, rd_busy_o => open); --! NF transmitter nf_transmitter_inst : entity work.nf_transmitter port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, start_i => tx_start_i, tx_addr_o => tx_data(14 downto 8), tx_data_o => tx_data(7 downto 0), tx_data_en_o => tx_data_en, tx_busy_i => tx_busy, tx_done_i => tx_done, mem_rd_en_o => mem_rd_en, mem_addr_o => mem_addr, mem_data_i => mem_data, mem_data_en_i => mem_data_en); end architecture rtl;

mit

f96613cc5f409fa7f9a79ed29f999611

wltr/cern-fgclite

critical_fpga/src/rtl/cf.vhd

------------------------------------------------------------------------------- --! @file cf.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-07-06 --! @brief Critical FPGA core component. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.ab_pkg.all; use work.nf_pkg.all; use work.xf_pkg.all; use work.cf_pkg.all; use work.sram_pkg.all; --! @brief Entity declaration of cf --! @details --! The core component for the Critical FPGA implementation. entity cf is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name LEDs --! @{ --! Red LEDs leds_red_n_o : out std_ulogic_vector(5 downto 0); --! Green LEDs leds_green_n_o : out std_ulogic_vector(5 downto 0); --! Test LEDs leds_test_n_i : in std_ulogic; --! @} --! @name Power converter interface --! @{ --! Power converter commands conv_cmd_o : out std_ulogic_vector(7 downto 0); --! Power converter status conv_stat_i : in std_ulogic_vector(15 downto 0); --! @} --! @name External SRAM interface --! @{ --! Inputs sram_i : in sram_in_t; --! Outputs sram_o : out sram_out_t; --! @} --! @name Optical interface --! @{ --! Optical input optical_i : in std_ulogic_vector(1 downto 0); --! @} --! @name Analogue board interface --! @{ --! Inputs ab_i : in ab_in_t; --! Outputs ab_o : out ab_out_t; --! @} --! @name Interlocks --! @{ --! Interlock inputs interlock_i : in std_ulogic_vector(1 downto 0); --! Interlock outputs interlock_o : out std_ulogic_vector(1 downto 0); --! @} --! @name PF interface --! @{ --! Send power cycle request to PF pf_req_n_o : out std_ulogic; --! Enable power down on PF pf_pwr_dwn_en_o : out std_ulogic; --! Failure flag from PF pf_pwr_flr_i : in std_ulogic; --! Power down signal from PF pf_pwr_dwn_i : in std_ulogic; --! @} --! @name NanoFIP interface --! @{ --! Inputs nf_i : in nf_in_t; --! Outputs nf_o : out nf_out_t; --! @} --! @name Auxiliary FPGA interface --! @{ --! Inputs xf_i : in xf_in_t; --! Outputs xf_o : out xf_out_t; --! @} --! @name Auxiliary interface (UART to diagnostics connector) --! @{ --! Input aux_i : in std_ulogic; --! Output aux_o : out std_ulogic; --! @} --! @name Debugging --! @{ --! Serial receiver debug_rx_i : in std_ulogic; --! Serial transmitter debug_tx_o : out std_ulogic; --! Debugging probe debug_probe_o : out std_ulogic); --! @} end entity cf; --! RTL implementation of cf architecture rtl of cf is --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal acc_sel_vs : std_ulogic; signal acc_sel_ia : std_ulogic; signal acc_sel_ib : std_ulogic; signal command_received : std_ulogic_vector(3 downto 0); signal command_received_dlyd : std_ulogic_vector(3 downto 0); signal conv_cmd : std_ulogic_vector(7 downto 0); signal powering_failure : std_ulogic; signal sequence_num : unsigned(1 downto 0); signal adc_log_freeze : std_ulogic; signal dim_log_freeze : std_ulogic; signal comm_ok : std_ulogic; signal dim_trig_latched : std_ulogic_vector(15 downto 0); signal dim_trig_unlatched : std_ulogic_vector(15 downto 0); signal nanofip_version : std_ulogic_vector(3 downto 0); --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal leds_red : std_ulogic_vector(5 downto 0); signal leds_green : std_ulogic_vector(5 downto 0); signal command : nf_command_t; signal status : nf_status_t; signal ms_strobe : std_ulogic; signal ms_number : std_ulogic_vector(0 to 19); signal ms_0_dlyd : std_ulogic; signal adc_sefi : std_ulogic_vector(5 downto 0); signal adc_vs : std_ulogic_vector(23 downto 0); signal adc_vs_en : std_ulogic; signal adc_ia : std_ulogic_vector(23 downto 0); signal adc_ia_en : std_ulogic; signal adc_ib : std_ulogic_vector(23 downto 0); signal adc_ib_en : std_ulogic; signal acc_vs : std_ulogic_vector(31 downto 0); signal acc_vs_en : std_ulogic; signal acc_ia : std_ulogic_vector(31 downto 0); signal acc_ia_en : std_ulogic; signal acc_ib : std_ulogic_vector(31 downto 0); signal acc_ib_en : std_ulogic; signal ow_scan_busy : std_ulogic; signal cmd_num : std_ulogic_vector(1 downto 0); signal cmd_num_en : std_ulogic; signal page_addr : std_ulogic_vector(5 downto 0); signal page_data : std_ulogic_vector(7 downto 0); signal page_wr_en : std_ulogic; signal page_done : std_ulogic; signal page_ready : std_ulogic; signal dim : std_ulogic_vector(19 downto 0); signal dim_en : std_ulogic; signal sram_adc_addr : std_ulogic_vector(4 downto 0); signal sram_adc_rd_en : std_ulogic; signal sram_adc_data : std_ulogic_vector(23 downto 0); signal sram_adc_data_en : std_ulogic; signal sram_adc_done : std_ulogic; signal sram_dim_addr : std_ulogic_vector(4 downto 0); signal sram_dim_rd_en : std_ulogic; signal sram_dim_data : std_ulogic_vector(15 downto 0); signal sram_dim_data_en : std_ulogic; signal sram_dim_done : std_ulogic; signal dim_addr : std_ulogic_vector(6 downto 0); signal dim_rd_en : std_ulogic; signal dim_data : std_ulogic_vector(15 downto 0); signal dim_data_en : std_ulogic; signal ow_addr : std_ulogic_vector(5 downto 0); signal ow_rd_en : std_ulogic; signal ow_data : std_ulogic_vector(79 downto 0); signal ow_data_en : std_ulogic; signal pf_vref : std_ulogic_vector(15 downto 0); signal pf_vref_en : std_ulogic; signal pf_vref_ovr : std_ulogic; signal nf_debug : std_ulogic_vector(7 downto 0); signal nf_debug_en : std_ulogic; signal dim_trig_num : std_ulogic_vector(3 downto 0); signal dim_trig_lat : std_ulogic; signal dim_trig_unl : std_ulogic; signal nf_version : std_ulogic_vector(3 downto 0); signal nf_version_en : std_ulogic; signal cycle_period : std_ulogic_vector(19 downto 0); --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- conv_cmd_o <= conv_cmd; interlock_o(0) <= powering_failure; interlock_o(1) <= conv_cmd(6); debug_probe_o <= adc_log_freeze; -- ms_number(0); -- Test LEDs leds_red_n_o <= (others => '0') when leds_test_n_i = '0' else (not leds_red); leds_green_n_o <= (others => '0') when leds_test_n_i = '0' else (not leds_green); --------------------------------------------------------------------------- -- Signal Assignments --------------------------------------------------------------------------- -- NanoFIP status leds_green(0) <= comm_ok; -- FGC status leds_green(1) <= not (adc_sefi(0) or adc_sefi(1) or adc_sefi(2) or adc_sefi(3) or adc_sefi(4) or adc_sefi(5)); -- PSU status (?) leds_green(2) <= '1'; -- Voltage source status leds_green(3) <= not conv_stat_i(2); -- not VS_FAULT -- DCCT status leds_green(4) <= conv_stat_i(8) and conv_stat_i(9); -- DCCTA_OK and DCCTB_OK -- Power Interlock Controller status leds_green(5) <= not powering_failure; leds_red <= not leds_green; status.fgc_status_en <= ms_0_dlyd; status.fgc_status(15) <= conv_cmd(6); status.fgc_status(14) <= powering_failure; status.fgc_status(13) <= interlock_i(1); status.fgc_status(12) <= interlock_i(0); status.fgc_status(11) <= ow_scan_busy; status.fgc_status(10) <= not command_received_dlyd(3); status.fgc_status(9) <= not command_received_dlyd(2); status.fgc_status(8) <= not command_received_dlyd(0); status.fgc_status(7) <= adc_sefi(0); status.fgc_status(6) <= adc_sefi(1); status.fgc_status(5) <= adc_sefi(2); status.fgc_status(4) <= adc_sefi(3); status.fgc_status(3) <= adc_sefi(4); status.fgc_status(2) <= adc_sefi(5); status.fgc_status(1 downto 0) <= std_ulogic_vector(sequence_num); status.adc_acc_vs_0 <= acc_vs; status.adc_acc_vs_1 <= acc_vs; status.adc_acc_ia_0 <= acc_ia; status.adc_acc_ia_1 <= acc_ia; status.adc_acc_ib_0 <= acc_ib; status.adc_acc_ib_1 <= acc_ib; status.adc_acc_vs_0_en <= acc_vs_en and acc_sel_vs; status.adc_acc_vs_1_en <= acc_vs_en and not acc_sel_vs; status.adc_acc_ia_0_en <= acc_ia_en and acc_sel_ia; status.adc_acc_ia_1_en <= acc_ia_en and not acc_sel_ia; status.adc_acc_ib_0_en <= acc_ib_en and acc_sel_ib; status.adc_acc_ib_1_en <= acc_ib_en and not acc_sel_ib; status.vs_dig_out <= conv_cmd; status.vs_dig_out_en <= ms_0_dlyd; status.vs_dig_in <= conv_stat_i; status.vs_dig_in_en <= ms_number(0); status.adc_log_idx_en <= ms_number(0); status.dim_log_idx_en <= ms_number(0); status.dim_a_trig_lat <= dim_trig_latched; status.dim_a_trig_lat_en <= ms_number(0); status.dim_a_trig_unl <= dim_trig_unlatched; status.dim_a_trig_unl_en <= ms_number(0); status.dim_a1_ana_0 <= dim(15 downto 0); status.dim_a1_ana_0_en <= dim_en when (dim(19 downto 16) = "0001" and dim(13 downto 12) = "00") else '0'; status.dim_a1_ana_1 <= dim(15 downto 0); status.dim_a1_ana_1_en <= dim_en when (dim(19 downto 16) = "0001" and dim(13 downto 12) = "01") else '0'; status.dim_a1_ana_2 <= dim(15 downto 0); status.dim_a1_ana_2_en <= dim_en when (dim(19 downto 16) = "0001" and dim(13 downto 12) = "10") else '0'; status.dim_a1_ana_3 <= dim(15 downto 0); status.dim_a1_ana_3_en <= dim_en when (dim(19 downto 16) = "0001" and dim(13 downto 12) = "11") else '0'; status.version_cfnf(3 downto 0) <= CF_VERSION_c; status.version_cfnf(7 downto 4) <= nanofip_version; status.version_cfnf_en <= '1'; status.cycle_period(19 downto 0) <= cycle_period; status.cycle_period(31 downto 20) <= (others => '0'); status.cycle_period_en <= ms_number(0); --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- --! Field-bus timing synchronization timing_inst : entity work.field_bus_timing port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, cmd_0_i => nf_i.cmd_0, ms_strobe_o => ms_strobe, ms_period_i => command.ms_period, ms_number_o => ms_number, cycle_period_o => cycle_period); --! NanoFIP communication and synchronization nf_inst : entity work.nf port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => ms_number(2), tx_start_i => page_ready, cmd_num_o => cmd_num, cmd_num_en_o => cmd_num_en, nf_version_o => nf_version, nf_version_en_o => nf_version_en, nf_debug_o => nf_debug, nf_debug_en_o => nf_debug_en, nf_i => nf_i, nf_o => nf_o, command_o => command, status_i => status, page_addr_i => page_addr, page_wr_en_i => page_wr_en, page_data_i => page_data, page_done_o => page_done); --! Analogue board filtering and control ab_inst : entity work.ab port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, ab_i => ab_i, ab_o => ab_o, ms_strobe_i => ms_strobe, ms_0_strobe_i => ms_0_dlyd, command_i => command, sefi_o => adc_sefi, pf_vref_i => pf_vref, pf_vref_en_i => pf_vref_en, pf_vref_ovr_i => pf_vref_ovr, adc_vs_o => adc_vs, adc_vs_en_o => adc_vs_en, adc_ia_o => adc_ia, adc_ia_en_o => adc_ia_en, adc_ib_o => adc_ib, adc_ib_en_o => adc_ib_en, acc_vs_o => acc_vs, acc_vs_en_o => acc_vs_en, acc_ia_o => acc_ia, acc_ia_en_o => acc_ia_en, acc_ib_o => acc_ib, acc_ib_en_o => acc_ib_en); --! Auxiliary FPGA communication xf_inst : entity work.xf port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, xf_i => xf_i, xf_o => xf_o, ms_0_strobe_i => ms_number(0), ms_1_strobe_i => ms_number(1), command_i => command, dim_o => dim, dim_en_o => dim_en, dim_trig_num_o => dim_trig_num, dim_trig_lat_o => dim_trig_lat, dim_trig_unl_o => dim_trig_unl, backplane_type_o => status.backplane, backplane_type_en_o => status.backplane_en, version_xfpf_o => status.version_xfpf, version_xfpf_en_o => status.version_xfpf_en, seu_count_o => status.seu_count, seu_count_en_o => status.seu_count_en, ow_scan_busy_o => ow_scan_busy, dim_addr_i => dim_addr, dim_rd_en_i => dim_rd_en, dim_data_o => dim_data, dim_data_en_o => dim_data_en, ow_addr_i => ow_addr, ow_rd_en_i => ow_rd_en, ow_data_o => ow_data, ow_data_en_o => ow_data_en); --! Power FPGA communication pf_inst : entity work.pf port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, pf_req_n_o => pf_req_n_o, pf_pwr_dwn_en_o => pf_pwr_dwn_en_o, pf_pwr_dwn_i => pf_pwr_dwn_i, ms_0_strobe_i => ms_number(0), ms_9_strobe_i => ms_number(9), ms_11_strobe_i => ms_number(11), v_ref_i => command.v_ref, v_ref_o => pf_vref, v_ref_en_o => pf_vref_en, v_ref_override_o => pf_vref_ovr, backplane_i => status.backplane, command_received_i => command_received_dlyd); --! Serial field-bus communication serial_inst : entity work.field_bus_serial port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, start_i => ms_number(0), command_i => command, data_o => status.serial_data, data_num_o => status.serial_num, data_en_o => status.serial_data_en, rx_i => aux_i, tx_o => aux_o); --! External SRAM access arbitration sram_inst : entity work.sram port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, adc_log_idx_o => status.adc_log_idx, dim_log_idx_o => status.dim_log_idx, adc_freeze_i => adc_log_freeze, dim_freeze_i => dim_log_freeze, ms_0_strobe_i => ms_0_dlyd, adc_vs_i => adc_vs, adc_vs_en_i => adc_vs_en, adc_ia_i => adc_ia, adc_ia_en_i => adc_ia_en, adc_ib_i => adc_ib, adc_ib_en_i => adc_ib_en, dim_i => dim, dim_en_i => dim_en, idx_i => command.index, idx_type_i => command.index_type, adc_addr_i => sram_adc_addr, adc_rd_en_i => sram_adc_rd_en, adc_data_o => sram_adc_data, adc_data_en_o => sram_adc_data_en, adc_done_i => sram_adc_done, dim_addr_i => sram_dim_addr, dim_rd_en_i => sram_dim_rd_en, dim_data_o => sram_dim_data, dim_data_en_o => sram_dim_data_en, dim_done_i => sram_dim_done, sram_i => sram_i, sram_o => sram_o); --! Prepare page to be sent via NanoFIP fetch_page_inst : entity work.fetch_page port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => ms_number(0), start_i => ms_0_dlyd, done_o => page_ready, idx_i => command.index, idx_type_i => command.index_type, page_addr_o => page_addr, page_wr_en_o => page_wr_en, page_data_o => page_data, page_done_i => page_done, sram_adc_addr_o => sram_adc_addr, sram_adc_rd_en_o => sram_adc_rd_en, sram_adc_data_i => sram_adc_data, sram_adc_data_en_i => sram_adc_data_en, sram_adc_done_o => sram_adc_done, sram_dim_addr_o => sram_dim_addr, sram_dim_rd_en_o => sram_dim_rd_en, sram_dim_data_i => sram_dim_data, sram_dim_data_en_i => sram_dim_data_en, sram_dim_done_o => sram_dim_done, dim_addr_o => dim_addr, dim_rd_en_o => dim_rd_en, dim_data_i => dim_data, dim_data_en_i => dim_data_en, ow_addr_o => ow_addr, ow_rd_en_o => ow_rd_en, ow_data_i => ow_data, ow_data_en_i => ow_data_en); debug_inst : entity work.debug_serial port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, start_i => ms_number(1), debug_i => nf_debug, debug_en_i => nf_debug_en, debug_o => open, debug_en_o => open, rx_i => debug_rx_i, tx_o => debug_tx_o); --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin acc_sel_vs <= '1'; acc_sel_ia <= '1'; acc_sel_ib <= '1'; ms_0_dlyd <= '0'; sequence_num <= to_unsigned(0, sequence_num'length); command_received <= (others => '0'); command_received_dlyd <= (others => '0'); conv_cmd <= (others => '0'); powering_failure <= '0'; adc_log_freeze <= '0'; dim_log_freeze <= '0'; comm_ok <= '0'; dim_trig_latched <= (others => '0'); dim_trig_unlatched <= (others => '0'); nanofip_version <= (others => '0'); end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else ms_0_dlyd <= ms_number(0); command_received_dlyd <= command_received; if ms_number(4) = '1' then acc_sel_vs <= '1'; elsif acc_vs_en = '1' then acc_sel_vs <= '0'; end if; if ms_number(4) = '1' then acc_sel_ia <= '1'; elsif acc_ia_en = '1' then acc_sel_ia <= '0'; end if; if ms_number(4) = '1' then acc_sel_ib <= '1'; elsif acc_ib_en = '1' then acc_sel_ib <= '0'; end if; if dim_trig_lat = '1' then dim_trig_latched(to_integer(unsigned(dim_trig_num))) <= '1'; end if; if dim_trig_unl = '1' then dim_trig_unlatched(to_integer(unsigned(dim_trig_num))) <= '1'; end if; if nf_version_en = '1' then nanofip_version <= nf_version; end if; if ms_number(0) = '1' then sequence_num <= sequence_num + 1; conv_cmd <= command.vs_cmd; powering_failure <= command.vs_cmd(7) or pf_pwr_flr_i; adc_log_freeze <= command.adc_log_freeze; dim_log_freeze <= command.dim_log_freeze; -- Stop VS_RUN when VS_FAULT if conv_stat_i(2) = '1' then conv_cmd(0) <= '0'; end if; if command_received = "1111" then comm_ok <= '1'; else comm_ok <= '0'; end if; end if; if ms_number(0) = '1' then command_received <= (others => '0'); elsif cmd_num_en = '1' then command_received(to_integer(unsigned(cmd_num))) <= '1'; end if; if ms_0_dlyd = '1' then dim_trig_latched <= (others => '0'); dim_trig_unlatched <= (others => '0'); end if; end if; end if; end process regs; end architecture rtl;

mit

3e40f4f01d406fc4e9c6bb7bae634341

joalcava/sparcv8-monocicle

TBSP8.vhd

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 22:40:11 11/09/2016 -- Design Name: -- Module Name: C:/Users/Personal/Downloads/sparcv8-monocicle-master/TBSP8.vhd -- Project Name: monocicle-sparcv8 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: Sparcv8Monocicle -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY TBSP8 IS END TBSP8; ARCHITECTURE behavior OF TBSP8 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Sparcv8Monocicle PORT( CLK : IN std_logic; RST : IN std_logic; R : OUT std_logic_vector(31 downto 0) ); END COMPONENT; --Inputs signal CLK : std_logic := '0'; signal RST : std_logic := '0'; --Outputs signal R : std_logic_vector(31 downto 0); -- Clock period definitions constant CLK_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Sparcv8Monocicle PORT MAP ( CLK => CLK, RST => RST, R => R ); -- Clock process definitions CLK_process :process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process; -- Stimulus process stim_proc: process begin RST <= '1'; wait for CLK_period; RST <= '0'; wait ; wait; end process; END;

gpl-3.0

1ecb73082db1ada93f37ddaafb7f8d7b

Kinxil/VHDL_Projects

Mandelbrot/ClockManager.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; library WORK; use WORK.CONSTANTS.ALL; entity ClockManager is Port ( clock : in std_logic; reset : in std_logic; ce_param : out std_logic); end ClockManager; architecture Behavioral of ClockManager is signal cpt : integer := 0; begin process (clock, reset) begin if (reset = '1') then cpt<=0; elsif (rising_edge(clock)) then if (cpt< PARAM_DELAY) then cpt<= cpt + 1; ce_param<='0'; else cpt<=0; ce_param<='1'; end if; end if; end process; end Behavioral;

gpl-3.0

d4a0f4de03501e7c8bf1091f7fc39568

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_8Stations_2TAGM.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

39532113f6f06f85e21e1f84534f638e

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

19632f534927dcfcd1dc6130938e4103

jpidancet/mips

rtl/decoder.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; library work; use work.mips_defs.ALL; entity decoder is port (op : in std_logic_vector(5 downto 0); func : in std_logic_vector(5 downto 0); reg_write : out std_logic; mem_to_reg : out std_logic; mem_read : out std_logic; mem_write : out std_logic; branch : out branch_type; alucontrol : out alucontrol_type; ovf_en : out std_logic; cmp : out compare_type; alu_src : out std_logic; reg_dst : out std_logic; imm_extend : out extend_type; link : out std_logic; rd31 : out std_logic); end entity decoder; architecture rtl of decoder is begin process (op, func) begin case op is when OP_SPECIAL => reg_write <= '1'; mem_to_reg <= '0'; mem_read <= '0'; mem_write <= '0'; case func is when FUNC_SLL => ovf_en <= '0'; alucontrol <= ALU_SLL; branch <= NO_BRANCH; link <= '0'; when FUNC_SRL => ovf_en <= '0'; alucontrol <= ALU_SRL; branch <= NO_BRANCH; link <= '0'; when FUNC_JR => ovf_en <= '0'; alucontrol <= ALU_SLL; branch <= JUMP_REG; link <= '0'; when FUNC_JALR => ovf_en <= '0'; alucontrol <= ALU_BPLUS4; branch <= JUMP_REG; link <= '1'; when FUNC_ADD => ovf_en <= '1'; alucontrol <= ALU_ADD; branch <= NO_BRANCH; link <= '0'; when FUNC_ADDU => ovf_en <= '0'; alucontrol <= ALU_ADD; branch <= NO_BRANCH; link <= '0'; when FUNC_SUB => ovf_en <= '1'; alucontrol <= ALU_SUB; branch <= NO_BRANCH; link <= '0'; when FUNC_SUBU => ovf_en <= '0'; alucontrol <= ALU_SUB; branch <= NO_BRANCH; link <= '0'; when FUNC_AND => ovf_en <= '0'; alucontrol <= ALU_AND; branch <= NO_BRANCH; link <= '0'; when FUNC_OR => ovf_en <= '0'; alucontrol <= ALU_OR; branch <= NO_BRANCH; link <= '0'; when FUNC_XOR => ovf_en <= '0'; alucontrol <= ALU_XOR; branch <= NO_BRANCH; link <= '0'; when FUNC_NOR => ovf_en <= '0'; alucontrol <= ALU_NOR; branch <= NO_BRANCH; link <= '0'; when FUNC_SLT => ovf_en <= '0'; alucontrol <= ALU_SLT; branch <= NO_BRANCH; link <= '0'; when FUNC_SLTU => ovf_en <= '0'; alucontrol <= ALU_SLTU; branch <= NO_BRANCH; link <= '0'; when others => ovf_en <= '0'; alucontrol <= ALU_SLL; branch <= NO_BRANCH; link <= '0'; end case; alu_src <= '0'; reg_dst <= '1'; cmp <= CMP_EQUAL; imm_extend <= ZERO_EXTEND; rd31 <= '0'; when OP_LW => reg_write <= '1'; mem_to_reg <= '1'; mem_read <= '1'; mem_write <= '0'; branch <= NO_BRANCH; alu_src <= '1'; reg_dst <= '0'; alucontrol <= ALU_ADD; ovf_en <= '0'; cmp <= CMP_EQUAL; imm_extend <= SIGN_EXTEND; link <= '0'; rd31 <= '0'; when OP_SW => reg_write <= '0'; mem_to_reg <= '-'; mem_read <= '0'; mem_write <= '1'; branch <= NO_BRANCH; alu_src <= '1'; reg_dst <= '-'; alucontrol <= ALU_ADD; ovf_en <= '0'; cmp <= CMP_EQUAL; imm_extend <= SIGN_EXTEND; link <= '0'; rd31 <= '0'; when OP_BEQ => reg_write <= '0'; mem_to_reg <= '-'; mem_read <= '0'; mem_write <= '0'; branch <= BRANCH_COND; alu_src <= '0'; reg_dst <= '-'; alucontrol <= ALU_SUB; ovf_en <= '0'; cmp <= CMP_EQUAL; imm_extend <= SIGN_EXTEND; link <= '0'; rd31 <= '0'; when OP_BNE => reg_write <= '0'; mem_to_reg <= '-'; mem_read <= '0'; mem_write <= '0'; branch <= BRANCH_COND; alu_src <= '0'; reg_dst <= '-'; alucontrol <= ALU_SUB; ovf_en <= '0'; cmp <= CMP_NOT_EQUAL; imm_extend <= SIGN_EXTEND; link <= '0'; rd31 <= '0'; when OP_ADDI => reg_write <= '1'; mem_to_reg <= '0'; mem_read <= '0'; mem_write <= '0'; branch <= NO_BRANCH; alu_src <= '1'; reg_dst <= '0'; alucontrol <= ALU_ADD; ovf_en <= '1'; cmp <= CMP_EQUAL; imm_extend <= SIGN_EXTEND; link <= '0'; rd31 <= '0'; when OP_ANDI => reg_write <= '1'; mem_to_reg <= '0'; mem_read <= '0'; mem_write <= '0'; branch <= NO_BRANCH; alu_src <= '1'; reg_dst <= '0'; alucontrol <= ALU_AND; ovf_en <= '0'; cmp <= CMP_EQUAL; imm_extend <= ZERO_EXTEND; link <= '0'; rd31 <= '0'; when OP_ORI => reg_write <= '1'; mem_to_reg <= '0'; mem_read <= '0'; mem_write <= '0'; branch <= NO_BRANCH; alu_src <= '1'; reg_dst <= '0'; alucontrol <= ALU_OR; ovf_en <= '0'; cmp <= CMP_EQUAL; imm_extend <= ZERO_EXTEND; link <= '0'; rd31 <= '0'; when OP_LUI => reg_write <= '1'; mem_to_reg <= '0'; mem_read <= '0'; mem_write <= '0'; branch <= NO_BRANCH; alu_src <= '1'; reg_dst <= '0'; alucontrol <= ALU_OR; ovf_en <= '0'; cmp <= CMP_EQUAL; imm_extend <= SHIFT16_EXTEND; link <= '0'; rd31 <= '0'; when OP_ADDIU => reg_write <= '1'; mem_to_reg <= '0'; mem_read <= '0'; mem_write <= '0'; branch <= NO_BRANCH; alu_src <= '1'; reg_dst <= '0'; alucontrol <= ALU_ADD; ovf_en <= '0'; cmp <= CMP_EQUAL; imm_extend <= SIGN_EXTEND; link <= '0'; rd31 <= '0'; when OP_J => reg_write <= '0'; mem_to_reg <= '-'; mem_read <= '0'; mem_write <= '0'; branch <= JUMP_IMM; alu_src <= '-'; reg_dst <= '-'; alucontrol <= ALU_SLL; ovf_en <= '-'; cmp <= CMP_EQUAL; imm_extend <= ZERO_EXTEND; link <= '0'; rd31 <= '0'; when OP_JAL => reg_write <= '1'; mem_to_reg <= '0'; mem_read <= '0'; mem_write <= '0'; branch <= JUMP_IMM; alu_src <= '0'; reg_dst <= '1'; alucontrol <= ALU_BPLUS4; ovf_en <= '0'; cmp <= CMP_EQUAL; imm_extend <= ZERO_EXTEND; link <= '1'; rd31 <= '1'; when others => reg_write <= '-'; mem_to_reg <= '-'; mem_read <= '-'; mem_write <= '-'; branch <= NO_BRANCH; alu_src <= '-'; reg_dst <= '-'; alucontrol <= ALU_SLL; ovf_en <= '-'; cmp <= CMP_EQUAL; imm_extend <= ZERO_EXTEND; link <= '0'; rd31 <= '0'; end case; end process; end architecture rtl;

isc

397ed832dff2c5c3899769b82c9e65d4

preusser/q27

src/vhdl/queens/arbit_forward.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity arbit_forward is generic ( N : positive -- Length of Token Chain ); port ( tin : in std_logic; -- Fed Token have : in std_logic_vector(0 to N-1); -- Token Owner pass : in std_logic_vector(0 to N-1); -- Token Passers grnt : out std_logic_vector(0 to N-1); -- Token Output tout : out std_logic -- Unused Token ); end arbit_forward; library IEEE; use IEEE.numeric_std.all; architecture rtl of arbit_forward is -- Pseudo Addends and Sum signal a, b : unsigned(N-1 downto 0); signal s : unsigned(N downto 0); begin genAddends: for i in 0 to N-1 generate a(i) <= have(i) xor pass(i); b(i) <= have(i); end generate genAddends; s <= ('0' & a) + b + (0 to 0 => tin); genGrant: for i in 0 to N-1 generate grnt(i) <= s(i) and not pass(i); end generate genGrant; tout <= s(N); end rtl;

agpl-3.0

d9d05d1e0e5f97e6605412aab33216eb

preusser/q27

src/vhdl/top/xilinx/ml505_queens_uart.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity ml505_queens_uart is generic ( N : positive := 27; L : positive := 2; SOLVERS : positive := 22; COUNT_CYCLES : boolean := false; CLK_FREQ : positive := 100000000; CLK_MUL : positive := 16; CLK_DIV : positive := 9; BAUDRATE : positive := 115200; SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte ); port ( clkx : in std_logic; rstx : in std_logic; rx : in std_logic; tx : out std_logic; leds : out std_logic_vector(0 to 7) ); end ml505_queens_uart; library IEEE; use IEEE.numeric_std.all; library UNISIM; use UNISIM.vcomponents.all; architecture rtl of ml505_queens_uart is -- Global Control signal clk : std_logic; signal rst : std_logic; -- Solver Status signal avail : std_logic; begin ----------------------------------------------------------------------------- -- Generate Global Controls blkGlobal: block is signal clk_u : std_logic; -- Unbuffered Synthesized Clock signal rst_s : std_logic_vector(1 downto 0) := (others => '0'); begin DCM0 : DCM_BASE generic map ( CLKIN_PERIOD => 1000000000.0/real(CLK_FREQ), CLKIN_DIVIDE_BY_2 => FALSE, PHASE_SHIFT => 0, CLKFX_MULTIPLY => CLK_MUL, CLKFX_DIVIDE => CLK_DIV, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "NONE", -- only using clkfx DLL_FREQUENCY_MODE => "HIGH", DFS_FREQUENCY_MODE => "HIGH", DUTY_CYCLE_CORRECTION => TRUE, STARTUP_WAIT => TRUE -- Delay until DCM LOCK ) port map ( CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => clk_u, CLKFX180 => open, LOCKED => open, CLKFB => '0', CLKIN => clkx, RST => '0' ); clk_buf : BUFG port map ( I => clk_u, O => clk ); -- Reset Synchronization process(clk) begin if rising_edge(clk) then rst_s <= (not rstx) & rst_s(rst_s'left downto 1); end if; end process; rst <= rst_s(0); end block blkGlobal; ---------------------------------------------------------------------------- -- Solver Chain chain: entity work.queens_uart generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES, CLK_FREQ => integer((real(CLK_MUL)*real(CLK_FREQ))/real(CLK_DIV)), BAUDRATE => BAUDRATE, SENTINEL => SENTINEL ) port map ( clk => clk, rst => rst, rx => rx, tx => tx, avail => avail ); ---------------------------------------------------------------------------- -- Basic Status Output leds <= std_logic_vector(to_unsigned((SOLVERS mod (2**(leds'length-1)-1))+1, leds'length-1)) & avail; end rtl;

agpl-3.0

1e06fc464c1b7ef113a9a6934954b22b

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_min_area_pkg.vhd

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mit

3b66d30c2d7d679bc66ef4fb5eab7e6f

jcowgill/cs-dacs-robot

Common/AsyncRxStateDecoder.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY AsyncRxStateDecoder is PORT ( State : in STD_LOGIC_VECTOR (6 downto 0); Idle : out STD_LOGIC; -- 00 ChkStart : out STD_LOGIC; -- 07 DoShift : out STD_LOGIC; -- 17, 27, ... 67, 77 ChkStop : out STD_LOGIC; -- 77 CountReset : out STD_LOGIC -- 78 ); END AsyncRxStateDecoder; ARCHITECTURE Behavioral of AsyncRxStateDecoder is BEGIN -- Produce output signals Idle <= '1' WHEN (State = "0000000") ELSE '0'; ChkStart <= '1' WHEN (State = "0000111") ELSE '0'; DoShift <= '1' WHEN ((State(3 downto 0) = "0111") AND (State(6 downto 4) /= "000")) ELSE '0'; ChkStop <= '1' WHEN (State = "1110111") ELSE '0'; CountReset <= '1' WHEN (State = "1111000") ELSE '0'; END Behavioral;

apache-2.0

b86e215b1ccc7257480a30ee12b24a16

alpenwasser/pitaya

firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/xilinx.com/cic_compiler_v4_0/hdl/cic_compiler_v4_0_vh_rfs.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block mgBHxdGDKdFcNwl/Xx2WnyYZ7ba1BCdJcMSppx8JqLmJP1U5rviV9jaAKYu+vvTpty8wG5ySKIoS ICgIgO6V5w== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block igue1BkOrge2VpVQVRwbQ8pn3AwvEDZEEPivjx8QGiAj++94vrpWbiOuxNNKjjH1ls8/BaEytlI0 k+G45Qzlo4hEXwfSuLSzM8KYt7g93jXYIYktHgYGGNu3aOJWIi2cXvloY+pGimCQfcOaVGolYyH9 IhhuNsGI+eWWVc+rY1A= `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 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mit

88c39a14aad73407c8ccfecc09a289d4

blytkerchan/BrainF

BrainF_top.vhdl

-- BrainF* interpreter -- Version: 20141018 -- Author: Ronald Landheer-Cieslak -- Copyright (c) 2014 Vlinder Software -- License: LGPL-3.0 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity BrainF_top is port( resetN : in std_logic ; clock : in std_logic ; spi_miso : out std_logic ; spi_mosi : in std_logic ; spi_clock : in std_logic ; spi_slave_selectN : in std_logic ); end entity; architecture behavior of BrainF_top is component BrainF is generic( MAX_INSTRUCTION_COUNT : positive ; MEMORY_SIZE : positive ); port( resetN : in std_logic ; clock : in std_logic ; load_instructions : in std_logic ; instruction_octet : in std_logic_vector(7 downto 0) ; ack_instruction : out std_logic ; program_full : out std_logic ; read_memory : in std_logic ; memory_byte : out std_logic_vector(7 downto 0) ; memory_byte_ready : out std_logic ; memory_byte_read_ack : in std_logic ; done : out std_logic ); end component; signal load_instructions : std_logic := '0'; signal instruction_octet : std_logic_vector(7 downto 0) := (others => '0'); begin interpreter : BrainF generic map( MAX_INSTRUCTION_COUNT => 65535 , MEMORY_SIZE => 65535 ) port map( resetN => resetN , clock => clock , load_instructions => load_instructions , instruction_octet => instruction_octet , ack_instruction => open , program_full => open , read_memory => '0' , memory_byte => open , memory_byte_ready => open , memory_byte_read_ack => '0' , done => open ); end behavior;

lgpl-3.0

e631e48252ef677de932284872a570d5

David-Estevez/spaceinvaders

src/screenFormat.vhd

---------------------------------------------------------------------------------- -- -- Lab session #4: screenFormat -- -- Send the screen elements to the VGA controller -- -- Authors: -- David Estévez Fernández -- Sergio Vilches Expósito -- ---------------------------------------------------------------------------------- library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity screenFormat is port ( VGAx : in std_logic_vector (9 downto 0); VGAy : in std_logic_vector (9 downto 0); test : in std_logic; invArray: in std_logic_vector (39 downto 0); invLine : in std_logic_vector (3 downto 0); shipX1 : in std_logic_vector (4 downto 0); bullX1 : in std_logic_vector (4 downto 0); bullY1 : in std_logic_vector (3 downto 0); bulletFlying1: in std_logic; player2shown : in std_logic; shipX2 : in std_logic_vector (4 downto 0); bullX2 : in std_logic_vector (4 downto 0); bullY2 : in std_logic_vector (3 downto 0); bulletFlying2: in std_logic; specialScreen: in std_logic_vector( 2 downto 0); p1Score: in std_logic_vector(7 downto 0); p2Score: in std_logic_vector(7 downto 0); rgb : out std_logic_vector(2 downto 0) ); end screenFormat; architecture behavioral of screenFormat is -- macropixels signal x : std_logic_vector (4 downto 0); -- 0 to 19 signal y : std_logic_vector (3 downto 0); -- 0 to 14 -- game sprites: type sprite is array( 0 to 31, 0 to 31) of std_logic; CONSTANT alien1: sprite := ( "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000011000000000011000000000", "00000000011000000000011000000000", "00000000000110000001100000000000", "00000000000110000001100000000000", "00000000011111111111111000000000", "00000000011111111111111000000000", "00000001111001111110011110000000", "00000001111001111110011110000000", "00000111111111111111111111100000", "00000111111111111111111111100000", "00000110011111111111111001100000", "00000110011111111111111001100000", "00000110011000000000011001100000", "00000110011000000000011001100000", "00000000000111100111100000000000", "00000000000111100111100000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000" ); CONSTANT ship_sprite: sprite := ( "00000000000000011000000000000000", "00000000000000011000000000000000", "00000000000000011000000000000000", "00000000000000011000000000000000", "00000000000001111110000000000000", "00000000000001111110000000000000", "00000000000001111110000000000000", "00000000000001111110000000000000", "00000001100001111110000110000000", "00000001100001111110000110000000", "00000001100001111110000110000000", "00000001100001111110000110000000", "00000001100111111111100110000000", "00000001100111111111100110000000", "00000001111111100111111110000000", "00000001111111100111111110000000", "01100001111110000001111110000110", "01100001111110000001111110000110", "01100001111110011001111110000110", "01100001111110011001111110000110", "01100001111111111111111110000110", "01100001111111111111111110000110", "01100111111111111111111111100110", "01100111111111111111111111100110", "01111111111111111111111111111110", "01111111111111111111111111111110", "01111110011111111111111001111110", "01111110011111111111111001111110", "01111000011110011001111000011110", "01111000011110011001111000011110", "01100000000000011000000000000110", "01100000000000011000000000000110" ); CONSTANT funny_bullet: sprite := ( "00000000000000111100000000000000", "00000000000001011110000000000000", "00000000000010101111000000000000", "00000000000110001111100000000000", "00000000001111111111110000000000", "00000000001111110011110000000000", "00000000011111110001111000000000", "00000000011111100001111000000000", "00000000011111110001111000000000", "00000000011111100001111000000000", "00000000011111100011111000000000", "00000000011111110011111000000000", "00000000011111111111111000000000", "00000000000000000000000000000000", "00000000010111111111111000000000", "00000000010111111111111000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000", "00000000000000000000000000000000" ); -- Define colors as constants: CONSTANT BLACK : STD_LOGIC_VECTOR( 2 DOWNTO 0) := "000"; CONSTANT BLUE : STD_LOGIC_VECTOR( 2 DOWNTO 0) := "001"; CONSTANT GREEN : STD_LOGIC_VECTOR( 2 DOWNTO 0) := "010"; CONSTANT CYAN : STD_LOGIC_VECTOR( 2 DOWNTO 0) := "011"; CONSTANT RED : STD_LOGIC_VECTOR( 2 DOWNTO 0) := "100"; CONSTANT MAGENTA : STD_LOGIC_VECTOR( 2 DOWNTO 0) := "101"; CONSTANT YELLOW : STD_LOGIC_VECTOR( 2 DOWNTO 0) := "110"; CONSTANT WHITE : STD_LOGIC_VECTOR( 2 DOWNTO 0) := "111"; begin -- Conversion to macropixels (32x32 blocks) x <= VGAx(9 downto 5); y <= VGAy(8 downto 5); -- Process to draw the screen process (x,y,test,specialScreen,invArray,bulletFlying1,bullX1,bullY1,player2shown,bulletFlying2,bullX2,bullY2,shipX1,shipX2,invLine) variable currentPixel: std_logic; -- Stores temporarily the current pixel of the sprite variable currentInvader: std_logic_vector( 1 downto 0); -- Stores the type of the current invader variable indX, indY: integer range 0 to 31; -- Indices inside the 32x32 block variable indInv: integer range 0 to 39; -- Index inside the invaders array begin if test = '1' then -- Show test checkerboard pattern ---------------------------------------- if (x(0) xor y(0)) = '1' then rgb <= BLACK; else rgb <= WHITE; end if; else -- Select screen case specialScreen is when "000" => -- No special screen (show game) ------------------------------------ -- Get coordinates inside de 32x32 macropixel indX := to_integer(unsigned(VGAx(4 downto 0))); indY := to_integer(unsigned(VGAy(4 downto 0))); -- Convert the 'macropixel' x coordinate to the invArray coordinates (2*x+1, 2*x) indInv := to_integer(unsigned(x)) * 2; currentInvader := invArray( indInv+1 downto indInv); -- Show player 1 bullet in red if bulletFlying1 = '1' and (x = bullX1) and (y = bullY1) then if funny_bullet( indY, indX) = '1' then rgb <= CYAN; else rgb <= BLACK; end if; -- Show player 2 bullet in magenta elsif player2shown = '1' and bulletFlying2 = '1' and (x = bullX2) and (y = bullY2) then if funny_bullet( indY, indX) = '1' then rgb <= MAGENTA; else rgb <= BLACK; end if; -- Show ship 1 in blue elsif (x = shipX1) and (y = std_logic_vector(to_unsigned(14,4))) then if ship_sprite( indY, indX) = '1' then rgb <= BLUE; else rgb <= BLACK; end if; -- Show ship 2 in cyan elsif player2shown = '1' and (x = shipX2) and (y = std_logic_vector(to_unsigned(14,4))) then if ship_sprite( indY, indX) = '1' then rgb <= RED; else rgb <= BLACK; end if; -- Show invaders in green elsif ( currentInvader /= "00") and (y = invLine) then currentPixel := alien1( indY, indX); if currentPixel = '1' then case currentInvader is when "01" => -- Easy alien rgb <= GREEN; when "10" => -- Medium alien rgb <= YELLOW; when "11" => -- Hard alien rgb <= WHITE; when others => rgb <= "XXX"; end case; else rgb <= BLACK; end if; else -- Pixel is black otherwise: rgb <= BLACK; end if ; when "001" => -- You win screen ------------------------------------- -- Get coordinates inside de 32x32 macropixel indX := to_integer(unsigned(VGAx(4 downto 0))); indY := to_integer(unsigned(VGAy(4 downto 0))); -- Convert the 'macropixel' x coordinate to the invArray coordinates (2*x+1, 2*x) indInv := to_integer(unsigned(x)) * 2; currentInvader := invArray( indInv+1 downto indInv); if (y = std_logic_vector(to_unsigned(5,4))) then -- We are in the correct line if ((x > std_logic_vector(to_unsigned(0,5))) and (x < std_logic_vector(to_unsigned(9,5)))) then -- We are in the correct box if (p1Score(7-to_integer(unsigned(x))) = '1') then -- Show an alien currentPixel := alien1( indY, indX); if currentPixel = '1' then rgb <= BLACK; else rgb <= BLUE; end if; else rgb <= BLUE; end if; else rgb <= BLACK; end if; elsif (y = std_logic_vector(to_unsigned(7,4))) then -- We are in the correct line if ((x > std_logic_vector(to_unsigned(0,5))) and (x < std_logic_vector(to_unsigned(9,5)))) then -- We are in the correct box if (p2Score(7-to_integer(unsigned(x))) = '1') then -- Show an alien currentPixel := alien1( indY, indX); if currentPixel = '1' then rgb <= BLACK; else rgb <= RED; end if; else rgb <= RED; end if; else rgb <= BLACK; end if; else rgb <= BLACK; end if; when "010" => -- You lose screen ------------------------------------- if (x(0) xor y(0)) = '1' then rgb <= BLACK; else rgb <= BLUE; end if; -- Temporarily blue checkerboard pattern when "011" => -- Game won screen ------------------------------------- if (x(0) xor y(0)) = '1' then rgb <= BLACK; else rgb <= YELLOW; end if; -- Temporarily blue checkerboard pattern when others => rgb <= "XXX"; -- Indicate error end case; end if ; end process; end behavioral;

gpl-3.0

22a8629c96a9c436a0482119c660bd4a

marcoep/MusicBoxNano

ip/ClocksPLL.vhd

-- megafunction wizard: %ALTPLL% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altpll -- ============================================================ -- File Name: ClocksPLL.vhd -- Megafunction Name(s): -- altpll -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 16.0.0 Build 211 04/27/2016 SJ Lite Edition -- ************************************************************ --Copyright (C) 1991-2016 Altera Corporation. All rights reserved. --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, the Altera Quartus Prime License Agreement, --the Altera MegaCore Function License Agreement, or other --applicable license agreement, including, without limitation, --that your use is for the sole purpose of programming logic --devices manufactured by Altera and sold by Altera or its --authorized distributors. Please refer to the applicable --agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY ClocksPLL IS PORT ( areset : IN STD_LOGIC := '0'; inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ; c2 : OUT STD_LOGIC ; locked : OUT STD_LOGIC ); END ClocksPLL; ARCHITECTURE SYN OF clockspll IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0); SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0); SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC ; SIGNAL sub_wire5 : STD_LOGIC ; SIGNAL sub_wire6 : STD_LOGIC ; SIGNAL sub_wire7 : STD_LOGIC ; COMPONENT altpll GENERIC ( bandwidth_type : STRING; clk0_divide_by : NATURAL; clk0_duty_cycle : NATURAL; clk0_multiply_by : NATURAL; clk0_phase_shift : STRING; clk1_divide_by : NATURAL; clk1_duty_cycle : NATURAL; clk1_multiply_by : NATURAL; clk1_phase_shift : STRING; clk2_divide_by : NATURAL; clk2_duty_cycle : NATURAL; clk2_multiply_by : NATURAL; clk2_phase_shift : STRING; compensate_clock : STRING; inclk0_input_frequency : NATURAL; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; operation_mode : STRING; pll_type : STRING; port_activeclock : STRING; port_areset : STRING; port_clkbad0 : STRING; port_clkbad1 : STRING; port_clkloss : STRING; port_clkswitch : STRING; port_configupdate : STRING; port_fbin : STRING; port_inclk0 : STRING; port_inclk1 : STRING; port_locked : STRING; port_pfdena : STRING; port_phasecounterselect : STRING; port_phasedone : STRING; port_phasestep : STRING; port_phaseupdown : STRING; port_pllena : STRING; port_scanaclr : STRING; port_scanclk : STRING; port_scanclkena : STRING; port_scandata : STRING; port_scandataout : STRING; port_scandone : STRING; port_scanread : STRING; port_scanwrite : STRING; port_clk0 : STRING; port_clk1 : STRING; port_clk2 : STRING; port_clk3 : STRING; port_clk4 : STRING; port_clk5 : STRING; port_clkena0 : STRING; port_clkena1 : STRING; port_clkena2 : STRING; port_clkena3 : STRING; port_clkena4 : STRING; port_clkena5 : STRING; port_extclk0 : STRING; port_extclk1 : STRING; port_extclk2 : STRING; port_extclk3 : STRING; self_reset_on_loss_lock : STRING; width_clock : NATURAL ); PORT ( areset : IN STD_LOGIC ; inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); locked : OUT STD_LOGIC ); END COMPONENT; BEGIN sub_wire2_bv(0 DOWNTO 0) <= "0"; sub_wire2 <= To_stdlogicvector(sub_wire2_bv); sub_wire0 <= inclk0; sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0; sub_wire6 <= sub_wire3(2); sub_wire5 <= sub_wire3(1); sub_wire4 <= sub_wire3(0); c0 <= sub_wire4; c1 <= sub_wire5; c2 <= sub_wire6; locked <= sub_wire7; altpll_component : altpll GENERIC MAP ( bandwidth_type => "AUTO", clk0_divide_by => 10, clk0_duty_cycle => 50, clk0_multiply_by => 1, clk0_phase_shift => "0", clk1_divide_by => 1, clk1_duty_cycle => 50, clk1_multiply_by => 6, clk1_phase_shift => "0", clk2_divide_by => 3125, clk2_duty_cycle => 50, clk2_multiply_by => 8, clk2_phase_shift => "1953125", compensate_clock => "CLK0", inclk0_input_frequency => 20000, intended_device_family => "Cyclone IV E", lpm_hint => "CBX_MODULE_PREFIX=ClocksPLL", lpm_type => "altpll", operation_mode => "NORMAL", pll_type => "AUTO", port_activeclock => "PORT_UNUSED", port_areset => "PORT_USED", port_clkbad0 => "PORT_UNUSED", port_clkbad1 => "PORT_UNUSED", port_clkloss => "PORT_UNUSED", port_clkswitch => "PORT_UNUSED", port_configupdate => "PORT_UNUSED", port_fbin => "PORT_UNUSED", port_inclk0 => "PORT_USED", port_inclk1 => "PORT_UNUSED", port_locked => "PORT_USED", port_pfdena => "PORT_UNUSED", port_phasecounterselect => "PORT_UNUSED", port_phasedone => "PORT_UNUSED", port_phasestep => "PORT_UNUSED", port_phaseupdown => "PORT_UNUSED", port_pllena => "PORT_UNUSED", port_scanaclr => "PORT_UNUSED", port_scanclk => "PORT_UNUSED", port_scanclkena => "PORT_UNUSED", port_scandata => "PORT_UNUSED", port_scandataout => "PORT_UNUSED", port_scandone => "PORT_UNUSED", port_scanread => "PORT_UNUSED", port_scanwrite => "PORT_UNUSED", port_clk0 => "PORT_USED", port_clk1 => "PORT_USED", port_clk2 => "PORT_USED", port_clk3 => "PORT_UNUSED", port_clk4 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED", port_clkena1 => "PORT_UNUSED", port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED", port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED", port_extclk0 => "PORT_UNUSED", port_extclk1 => "PORT_UNUSED", port_extclk2 => "PORT_UNUSED", port_extclk3 => "PORT_UNUSED", self_reset_on_loss_lock => "ON", width_clock => 5 ) PORT MAP ( areset => areset, inclk => sub_wire1, clk => sub_wire3, locked => sub_wire7 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "50000" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "5.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "300.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.128000" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" -- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "23" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "5.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "300.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.12800000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "90.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -- Retrieval info: PRIVATE: RECONFIG_FILE STRING "ClocksPLL.mif" -- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" -- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -- Retrieval info: PRIVATE: SPREAD_USE STRING "0" -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_CLK0 STRING "1" -- Retrieval info: PRIVATE: USE_CLK1 STRING "1" -- Retrieval info: PRIVATE: USE_CLK2 STRING "1" -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "6" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "3125" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "8" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "1953125" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" -- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" -- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" -- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL ClocksPLL.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ClocksPLL.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL ClocksPLL.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ClocksPLL.cmp FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ClocksPLL.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL ClocksPLL_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf -- Retrieval info: CBX_MODULE_PREFIX: ON

gpl-3.0

ed11968ef8f2ed88028bd2e0a0ddc953

open-power/snap

actions/hdl_example/hw/action_axi_slave.vhd

---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- -- Copyright 2016,2017 International Business Machines -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions AND -- limitations under the License. -- ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity action_axi_slave is generic ( -- Users to add parameters here -- User parameters ends -- Do not modify the parameters beyond this line -- Width of S_AXI data bus C_S_AXI_DATA_WIDTH : integer := 32; -- Width of S_AXI address bus C_S_AXI_ADDR_WIDTH : integer := 6 ); port ( -- Users to add ports here reg_0x10_i : in std_logic_vector(31 downto 0); reg_0x14_i : in std_logic_vector(31 downto 0); reg_0x20_o : out std_logic_vector(31 downto 0); reg_0x30_o : out std_logic_vector(31 downto 0); reg_0x34_o : out std_logic_vector(31 downto 0); reg_0x38_o : out std_logic_vector(31 downto 0); reg_0x3c_o : out std_logic_vector(31 downto 0); reg_0x40_o : out std_logic_vector(31 downto 0); reg_0x44_o : out std_logic_vector(31 downto 0); int_enable_o : out std_logic; app_start_o : out std_logic; app_done_i : in std_logic; app_ready_i : in std_logic; app_idle_i : in std_logic; -- User ports ends -- Do not modify the ports beyond this line -- Global Clock Signal S_AXI_ACLK : in std_logic; -- Global Reset Signal. This Signal is Active LOW S_AXI_ARESETN : in std_logic; -- Write address (issued by master, acceped by Slave) S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); -- -- Write channel Protection type. This signal indicates the -- -- privilege and security level of the transaction, and whether -- -- the transaction is a data access or an instruction access. -- S_AXI_AWPROT : in std_logic_vector(2 downto 0); -- Write address valid. This signal indicates that the master signaling -- valid write address and control information. S_AXI_AWVALID : in std_logic; -- Write address ready. This signal indicates that the slave is ready -- to accept an address and associated control signals. S_AXI_AWREADY : out std_logic; -- Write data (issued by master, acceped by Slave) S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); -- Write strobes. This signal indicates which byte lanes hold -- valid data. There is one write strobe bit for each eight -- bits of the write data bus. S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); -- Write valid. This signal indicates that valid write -- data and strobes are available. S_AXI_WVALID : in std_logic; -- Write ready. This signal indicates that the slave -- can accept the write data. S_AXI_WREADY : out std_logic; -- Write response. This signal indicates the status -- of the write transaction. S_AXI_BRESP : out std_logic_vector(1 downto 0); -- Write response valid. This signal indicates that the channel -- is signaling a valid write response. S_AXI_BVALID : out std_logic; -- Response ready. This signal indicates that the master -- can accept a write response. S_AXI_BREADY : in std_logic; -- Read address (issued by master, acceped by Slave) S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); -- -- Protection type. This signal indicates the privilege -- -- and security level of the transaction, and whether the -- -- transaction is a data access or an instruction access. -- S_AXI_ARPROT : in std_logic_vector(2 downto 0); -- Read address valid. This signal indicates that the channel -- is signaling valid read address and control information. S_AXI_ARVALID : in std_logic; -- Read address ready. This signal indicates that the slave is -- ready to accept an address and associated control signals. S_AXI_ARREADY : out std_logic; -- Read data (issued by slave) S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); -- Read response. This signal indicates the status of the -- read transfer. S_AXI_RRESP : out std_logic_vector(1 downto 0); -- Read valid. This signal indicates that the channel is -- signaling the required read data. S_AXI_RVALID : out std_logic; -- Read ready. This signal indicates that the master can -- accept the read data and response information. S_AXI_RREADY : in std_logic ); end action_axi_slave; architecture action_axi_slave of action_axi_slave is -- AXI4LITE signals signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); signal axi_awready : std_logic; signal axi_wready : std_logic; signal axi_bresp : std_logic_vector(1 downto 0); signal axi_bvalid : std_logic; signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); signal axi_arready : std_logic; signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal axi_rresp : std_logic_vector(1 downto 0); signal axi_rvalid : std_logic; -- Example-specific design signals -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH -- ADDR_LSB is used for addressing 32/64 bit registers/memories -- ADDR_LSB = 2 for 32 bits (n downto 2) -- ADDR_LSB = 3 for 64 bits (n downto 3) constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1; constant OPT_MEM_ADDR_BITS : integer := 5; ------------------------------------------------ ---- Signals for user logic register space example -------------------------------------------------- ---- Number of Slave Registers 16 signal slv_reg0 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal slv_reg0_new : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal slv_reg1 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal slv_reg2 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal slv_reg3 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal slv_reg8 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal slv_reg12 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal slv_reg13 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal slv_reg14 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal slv_reg15 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal slv_reg16 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal slv_reg17 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal slv_reg18 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal slv_reg19 : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal slv_reg_rden : std_logic; signal slv_reg_wren : std_logic; signal reg_data_out : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); signal byte_index : integer; signal idle_q : std_logic; signal app_start_q : std_logic; signal app_done_q : std_logic; signal slv_reg0_bit0_q : std_logic; begin -- I/O Connections assignments int_enable_o <= slv_reg1(0); S_AXI_AWREADY <= axi_awready; S_AXI_WREADY <= axi_wready; S_AXI_BRESP <= axi_bresp; S_AXI_BVALID <= axi_bvalid; S_AXI_ARREADY <= axi_arready; S_AXI_RDATA <= axi_rdata; S_AXI_RRESP <= axi_rresp; S_AXI_RVALID <= axi_rvalid; -- Implement axi_awready generation -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is -- de-asserted when reset is low. process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then axi_awready <= '0'; else if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then -- slave is ready to accept write address when -- there is a valid write address and write data -- on the write address and data bus. This design -- expects no outstanding transactions. axi_awready <= '1'; else axi_awready <= '0'; end if; end if; end if; end process; -- Implement axi_awaddr latching -- This process is used to latch the address when both -- S_AXI_AWVALID and S_AXI_WVALID are valid. process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then axi_awaddr <= (others => '0'); else if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then -- Write Address latching axi_awaddr <= S_AXI_AWADDR; end if; end if; end if; end process; -- Implement axi_wready generation -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is -- de-asserted when reset is low. process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then axi_wready <= '0'; else if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then -- slave is ready to accept write data when -- there is a valid write address and write data -- on the write address and data bus. This design -- expects no outstanding transactions. axi_wready <= '1'; else axi_wready <= '0'; end if; end if; end if; end process; -- Implement memory mapped register select and write logic generation -- The write data is accepted and written to memory mapped registers when -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to -- select byte enables of slave registers while writing. -- These registers are cleared when reset (active low) is applied. -- Slave register write enable is asserted when valid address and data are available -- and the slave is ready to accept the write address and write data. slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ; process (S_AXI_ACLK) variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS-1 downto 0); begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0'); slv_reg2 <= (others => '0'); slv_reg3 <= (others => '0'); slv_reg8 <= (others => '0'); slv_reg12 <= (others => '0'); slv_reg13 <= (others => '0'); slv_reg14 <= (others => '0'); slv_reg15 <= (others => '0'); slv_reg16 <= (others => '0'); slv_reg17 <= (others => '0'); slv_reg18 <= (others => '0'); slv_reg19 <= (others => '0'); else loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS-1 downto ADDR_LSB); if (slv_reg_wren = '1') then case loc_addr is when b"00000" => for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop if ( S_AXI_WSTRB(byte_index) = '1' ) then -- Respective byte enables are asserted as per write strobes -- slave registor 0 slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); end if; end loop; when b"00001" => for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop if ( S_AXI_WSTRB(byte_index) = '1' ) then -- Respective byte enables are asserted as per write strobes -- slave registor 1 slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); end if; end loop; when b"00010" => for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop if ( S_AXI_WSTRB(byte_index) = '1' ) then -- Respective byte enables are asserted as per write strobes -- slave registor 2 slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); end if; end loop; when b"00011" => for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop if ( S_AXI_WSTRB(byte_index) = '1' ) then -- Respective byte enables are asserted as per write strobes -- slave registor 3 slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); end if; end loop; when b"01000" => for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop if ( S_AXI_WSTRB(byte_index) = '1' ) then -- Respective byte enables are asserted as per write strobes -- slave registor 8 slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); end if; end loop; when b"01100" => for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop if ( S_AXI_WSTRB(byte_index) = '1' ) then -- Respective byte enables are asserted as per write strobes -- slave registor 12 slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); end if; end loop; when b"01101" => for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop if ( S_AXI_WSTRB(byte_index) = '1' ) then -- Respective byte enables are asserted as per write strobes -- slave registor 13 slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); end if; end loop; when b"01110" => for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop if ( S_AXI_WSTRB(byte_index) = '1' ) then -- Respective byte enables are asserted as per write strobes -- slave registor 14 slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); end if; end loop; when b"01111" => for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop if ( S_AXI_WSTRB(byte_index) = '1' ) then -- Respective byte enables are asserted as per write strobes -- slave registor 15 slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); end if; end loop; when b"10000" => for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop if ( S_AXI_WSTRB(byte_index) = '1' ) then -- Respective byte enables are asserted as per write strobes -- slave registor 16 slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); end if; end loop; when b"10001" => for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop if ( S_AXI_WSTRB(byte_index) = '1' ) then -- Respective byte enables are asserted as per write strobes -- slave registor 17 slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); end if; end loop; when b"10010" => for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop if ( S_AXI_WSTRB(byte_index) = '1' ) then -- Respective byte enables are asserted as per write strobes -- slave registor 18 slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); end if; end loop; when b"10011" => for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop if ( S_AXI_WSTRB(byte_index) = '1' ) then -- Respective byte enables are asserted as per write strobes -- slave registor 19 slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); end if; end loop; when others => slv_reg0 <= slv_reg0; slv_reg1 <= slv_reg1; slv_reg2 <= slv_reg2; slv_reg3 <= slv_reg3; slv_reg8 <= slv_reg8; slv_reg12 <= slv_reg12; slv_reg13 <= slv_reg13; slv_reg14 <= slv_reg14; slv_reg15 <= slv_reg15; slv_reg16 <= slv_reg16; slv_reg17 <= slv_reg17; slv_reg18 <= slv_reg18; slv_reg19 <= slv_reg19; end case; end if; if app_start_q = '1' then slv_reg0(0) <= '0'; end if; end if; end if; end process; -- Implement write response logic generation -- The write response and response valid signals are asserted by the slave -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. -- This marks the acceptance of address and indicates the status of -- write transaction. process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then axi_bvalid <= '0'; axi_bresp <= "00"; --need to work more on the responses else if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then axi_bvalid <= '1'; axi_bresp <= "00"; elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) end if; end if; end if; end process; -- Implement axi_arready generation -- axi_arready is asserted for one S_AXI_ACLK clock cycle when -- S_AXI_ARVALID is asserted. axi_awready is -- de-asserted when reset (active low) is asserted. -- The read address is also latched when S_AXI_ARVALID is -- asserted. axi_araddr is reset to zero on reset assertion. process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then axi_arready <= '0'; axi_araddr <= (others => '1'); else if (axi_arready = '0' and S_AXI_ARVALID = '1') then -- indicates that the slave has acceped the valid read address axi_arready <= '1'; -- Read Address latching axi_araddr <= S_AXI_ARADDR; else axi_arready <= '0'; end if; end if; end if; end process; -- Implement axi_arvalid generation -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both -- S_AXI_ARVALID and axi_arready are asserted. The slave registers -- data are available on the axi_rdata bus at this instance. The -- assertion of axi_rvalid marks the validity of read data on the -- bus and axi_rresp indicates the status of read transaction.axi_rvalid -- is deasserted on reset (active low). axi_rresp and axi_rdata are -- cleared to zero on reset (active low). process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then axi_rvalid <= '0'; axi_rresp <= "00"; else if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then -- Valid read data is available at the read data bus axi_rvalid <= '1'; axi_rresp <= "00"; -- 'OKAY' response elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then -- Read data is accepted by the master axi_rvalid <= '0'; end if; end if; end if; end process; -- Implement memory mapped register select and read logic generation -- Slave register read enable is asserted when valid address is available -- and the slave is ready to accept the read address. slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ; process (slv_reg0_new, slv_reg1, slv_reg2, slv_reg3, reg_0x10_i, reg_0x14_i, slv_reg8, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, axi_araddr) variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS-1 downto 0); begin -- Address decoding for reading registers loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS-1 downto ADDR_LSB); case loc_addr is when b"00000" => reg_data_out <= slv_reg0_new; -- 0x00 when b"00001" => reg_data_out <= slv_reg1; -- 0x04 when b"00010" => reg_data_out <= slv_reg2; -- 0x08 when b"00011" => reg_data_out <= slv_reg3; -- 0x0c when b"00100" => reg_data_out <= reg_0x10_i; -- 0x10 when b"00101" => reg_data_out <= reg_0x14_i; -- 0x14 when b"01000" => reg_data_out <= slv_reg8; -- 0x20 when b"01100" => reg_data_out <= slv_reg12; -- 0x30 when b"01101" => reg_data_out <= slv_reg13; -- 0x34 when b"01110" => reg_data_out <= slv_reg14; -- 0x38 when b"01111" => reg_data_out <= slv_reg15; -- 0x3c when b"10000" => reg_data_out <= slv_reg16; -- 0x40 when b"10001" => reg_data_out <= slv_reg17; -- 0x44 when b"10010" => reg_data_out <= slv_reg18; -- 0x48 when b"10011" => reg_data_out <= slv_reg19; -- 0x4c when others => reg_data_out <= (others => '0'); end case; end process; -- Output register or memory read data process( S_AXI_ACLK ) is begin if (rising_edge (S_AXI_ACLK)) then if ( S_AXI_ARESETN = '0' ) then axi_rdata <= (others => '0'); else if (slv_reg_rden = '1') then -- When there is a valid read address (S_AXI_ARVALID) with -- acceptance of read address by the slave (axi_arready), -- output the read dada -- Read address mux axi_rdata <= reg_data_out; -- register read data end if; end if; end if; end process; -- Add user logic here -- Reiner app_start_o <= app_start_q; reg_0x20_o <= slv_reg8; reg_0x30_o <= slv_reg12; reg_0x34_o <= slv_reg13; reg_0x38_o <= slv_reg14; reg_0x3c_o <= slv_reg15; reg_0x40_o <= slv_reg16; reg_0x44_o <= slv_reg17; process( S_AXI_ACLK ) is variable app_done_i_q : std_logic; variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS-1 downto 0); begin if (rising_edge (S_AXI_ACLK)) then if ( S_AXI_ARESETN = '0' ) then app_start_q <= '0'; app_done_q <= '0'; app_done_i_q := '0'; slv_reg0_bit0_q <= '0'; idle_q <= '0'; else idle_q <= app_idle_i; slv_reg0_bit0_q <= slv_reg0(0); app_done_i_q := app_done_i; loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS-1 downto ADDR_LSB); -- clear ap_done bit when register is read if slv_reg_rden = '1'and loc_addr = "00000" then app_done_q <= '0'; end if; if (app_done_i_q = '0' and app_done_i = '1') then app_done_q <= '1'; end if; if slv_reg0_bit0_q = '0' and slv_reg0(0) = '1' then app_start_q <= '1'; end if; if idle_q = '1' and app_idle_i = '0' then app_start_q <= '0'; end if; end if; end if; end process; slv_reg0_new <= slv_reg0 (31 downto 4) & app_ready_i & idle_q & app_done_q & app_start_q ; -- User logic ends end action_axi_slave;

apache-2.0

bed543bdb5ae37a64b533e14213b8e75

MiddleMan5/233

Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_FlagReg_0_1/synth/RAT_FlagReg_0_1.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:module_ref:FlagReg:1.0 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY RAT_FlagReg_0_1 IS PORT ( IN_FLAG : IN STD_LOGIC; LD : IN STD_LOGIC; SET : IN STD_LOGIC; CLR : IN STD_LOGIC; CLK : IN STD_LOGIC; OUT_FLAG : OUT STD_LOGIC ); END RAT_FlagReg_0_1; ARCHITECTURE RAT_FlagReg_0_1_arch OF RAT_FlagReg_0_1 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_FlagReg_0_1_arch: ARCHITECTURE IS "yes"; COMPONENT FlagReg IS PORT ( IN_FLAG : IN STD_LOGIC; LD : IN STD_LOGIC; SET : IN STD_LOGIC; CLR : IN STD_LOGIC; CLK : IN STD_LOGIC; OUT_FLAG : OUT STD_LOGIC ); END COMPONENT FlagReg; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF RAT_FlagReg_0_1_arch: ARCHITECTURE IS "FlagReg,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_FlagReg_0_1_arch : ARCHITECTURE IS "RAT_FlagReg_0_1,FlagReg,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF RAT_FlagReg_0_1_arch: ARCHITECTURE IS "RAT_FlagReg_0_1,FlagReg,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=FlagReg,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK"; BEGIN U0 : FlagReg PORT MAP ( IN_FLAG => IN_FLAG, LD => LD, SET => SET, CLR => CLR, CLK => CLK, OUT_FLAG => OUT_FLAG ); END RAT_FlagReg_0_1_arch;

mit

2c4a4c3856c915b19fba2cddfb5ddc06

BBN-Q/VHDL-Components

src/PolyphaseSSB.vhd

-- Modulates a complex 4 sample wide waveform stream for SSB modulation -- -- Uses 16 DSP slices: 4 * (2 per ComplexMultiplier and 2 per DDS) -- -- Original authors Diego Riste and Colm Ryan -- Copyright 2015, Raytheon BBN Technologies library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.and_reduce; --just use and in vhdl-2008 entity PolyphaseSSB is generic ( IN_DATA_WIDTH : natural := 16; OUT_DATA_WIDTH : natural := 16; ACCUMULATOR_WIDTH : natural := 24 ); port ( clk : in std_logic; rst : in std_logic; phase_increment : in std_logic_vector(ACCUMULATOR_WIDTH-1 downto 0); --signed N-bit integer (portion of circle) phase_offset : in std_logic_vector(ACCUMULATOR_WIDTH-1 downto 0); --signed N-bit integer (portion of circle) waveform_in_re : in std_logic_vector(4*IN_DATA_WIDTH-1 downto 0); waveform_in_im : in std_logic_vector(4*IN_DATA_WIDTH-1 downto 0); waveform_out_re : out std_logic_vector(4*OUT_DATA_WIDTH-1 downto 0); waveform_out_im : out std_logic_vector(4*OUT_DATA_WIDTH-1 downto 0); out_vld : out std_logic ) ; end entity ; -- PolyphaseSSB architecture arch of PolyphaseSSB is signal dds_vld : std_logic_vector(3 downto 0) := (others => '0'); signal prod_vld : std_logic_vector(3 downto 0) := (others => '0'); type SINCOS_ARRAY_t is array(0 to 3) of std_logic_vector(OUT_DATA_WIDTH+1 downto 0); type PHASE_ARRAY_t is array(0 to 3) of signed(ACCUMULATOR_WIDTH-1 downto 0); signal cos_array, sin_array : SINCOS_ARRAY_t := (others => (others => '0')); signal phase_offsets : PHASE_ARRAY_t := (others => (others => '0')); signal base_phase : signed(ACCUMULATOR_WIDTH-1 downto 0) := (others => '0'); signal phases : PHASE_ARRAY_t := (others => (others => '0')); begin --Base phase accumulator at 1/4 rate base_phase_accum : process(clk) begin if rising_edge(clk) then if rst = '1' then base_phase <= (others => '0'); else base_phase <= base_phase + signed(phase_increment); end if; end if; end process; --skew the offset for each of the four samples to interpolate --skew by 0,1/4,1/2,3/4 of phase_increment phase_offset_skew : process(clk) begin if rising_edge(clk) then phase_offsets(0) <= signed(phase_offset); phase_offsets(1) <= signed(phase_offset) + shift_right(signed(phase_increment),2); phase_offsets(2) <= signed(phase_offset) + shift_right(signed(phase_increment),1); phase_offsets(3) <= signed(phase_offset) + shift_right(signed(phase_increment),1) + shift_right(signed(phase_increment),2); end if; end process; --output all 4 phases phase_outputs : process(clk) begin if rising_edge(clk) then for ct in 0 to 3 loop phases(ct) <= base_phase + phase_offsets(ct); end loop; end if; end process; --generate the sin/cos LUTs sincos_lut_gen : for ct in 0 to 3 generate sincos_lut_inst : entity work.SinCosLUT generic map ( PHASE_WIDTH => OUT_DATA_WIDTH, OUTPUT_WIDTH => OUT_DATA_WIDTH+2 ) port map ( clk => clk, rst => rst, phase_tdata => std_logic_vector(phases(ct)(phases(ct)'high downto phases(ct)'high-OUT_DATA_WIDTH+1)), phase_tvalid => '1', sin_tdata => sin_array(ct), cos_tdata => cos_array(ct), sincos_tvalid => dds_vld(ct) ); end generate; ComplexMultipliergen : for ct in 0 to 3 generate myComplexMultiplier : entity work.ComplexMultiplier generic map ( A_WIDTH => IN_DATA_WIDTH, B_WIDTH => OUT_DATA_WIDTH+2, PROD_WIDTH => OUT_DATA_WIDTH, BIT_SHIFT => 1 ) port map ( clk => clk, rst => rst, a_data_re => waveform_in_re((ct+1)*IN_DATA_WIDTH-1 downto ct*IN_DATA_WIDTH), a_data_im => waveform_in_im((ct+1)*IN_DATA_WIDTH-1 downto ct*IN_DATA_WIDTH), a_vld => '1', a_last => '0', b_data_re => cos_array(ct), b_data_im => sin_array(ct), b_vld => dds_vld(ct), b_last => '0', prod_data_re => waveform_out_re((ct+1)*OUT_DATA_WIDTH-1 downto ct*OUT_DATA_WIDTH), prod_data_im => waveform_out_im((ct+1)*OUT_DATA_WIDTH-1 downto ct*OUT_DATA_WIDTH), prod_vld => prod_vld(ct) ); end generate ; -- ComplexMultipliergen out_vld <= and_reduce(prod_vld); -- just and in VHDL-2008 end architecture ; -- arch

mpl-2.0

2cec166a24f5c53d5c0835887a5430e2

alpenwasser/pitaya

firmware/fpga/p_FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ip/design_1_dec_to_fir_mux_1_0/sim/design_1_dec_to_fir_mux_1_0.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: noah-huesser:user:dec_to_fir_mux:1.0 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY design_1_dec_to_fir_mux_1_0 IS PORT ( DecRate : IN STD_LOGIC_VECTOR(31 DOWNTO 0); Mux3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); Mux2 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); Mux1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); Mux0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ); END design_1_dec_to_fir_mux_1_0; ARCHITECTURE design_1_dec_to_fir_mux_1_0_arch OF design_1_dec_to_fir_mux_1_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dec_to_fir_mux_1_0_arch: ARCHITECTURE IS "yes"; COMPONENT dec_to_fir_mux IS PORT ( DecRate : IN STD_LOGIC_VECTOR(31 DOWNTO 0); Mux3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); Mux2 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); Mux1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); Mux0 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ); END COMPONENT dec_to_fir_mux; BEGIN U0 : dec_to_fir_mux PORT MAP ( DecRate => DecRate, Mux3 => Mux3, Mux2 => Mux2, Mux1 => Mux1, Mux0 => Mux0 ); END design_1_dec_to_fir_mux_1_0_arch;

mit

49d13768d1e3478ddc751664ce5d6a0d

stefanct/aua

hw/io/sc_de2_digits/src/sc_de2_digits.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.aua_types.all; entity sc_de2_digits is port ( clk : in std_logic; reset : in std_logic; -- SimpCon slave interface to IO ctrl address : in sc_addr_t; wr_data : in sc_data_t; rd : in std_logic; wr : in std_logic; rd_data : out sc_data_t; rdy_cnt : out sc_rdy_cnt_t; -- pins digit0_pins : out std_logic_vector(6 downto 0); digit1_pins : out std_logic_vector(6 downto 0); digit2_pins : out std_logic_vector(6 downto 0); digit3_pins : out std_logic_vector(6 downto 0); digit4_pins : out std_logic_vector(6 downto 0); digit5_pins : out std_logic_vector(6 downto 0) ); end sc_de2_digits; architecture rtl of sc_de2_digits is signal digit0_nxt : std_logic_vector(6 downto 0); signal digit1_nxt : std_logic_vector(6 downto 0); signal digit2_nxt : std_logic_vector(6 downto 0); signal digit3_nxt : std_logic_vector(6 downto 0); signal digit4_nxt : std_logic_vector(6 downto 0); signal digit5_nxt : std_logic_vector(6 downto 0); signal digit0 : std_logic_vector(6 downto 0); signal digit1 : std_logic_vector(6 downto 0); signal digit2 : std_logic_vector(6 downto 0); signal digit3 : std_logic_vector(6 downto 0); signal digit4 : std_logic_vector(6 downto 0); signal digit5 : std_logic_vector(6 downto 0); begin rd_data <= (others => '0'); rdy_cnt <= (others => '0'); -- no wait states digit0_pins <= digit0; digit1_pins <= digit1; digit2_pins <= digit2; digit3_pins <= digit3; digit4_pins <= digit4; digit5_pins <= digit5; process(address, wr_data, wr, digit0, digit1, digit2, digit3, digit4, digit5) begin digit0_nxt <= digit0; digit1_nxt <= digit1; digit2_nxt <= digit2; digit3_nxt <= digit3; digit4_nxt <= digit4; digit5_nxt <= digit5; if wr = '1' then case address(3 downto 0) is when x"0" => digit0_nxt <= wr_data(6 downto 0); when x"1" => digit1_nxt <= wr_data(6 downto 0); when x"2" => digit2_nxt <= wr_data(6 downto 0); when x"3" => digit3_nxt <= wr_data(6 downto 0); when x"4" => digit4_nxt <= wr_data(6 downto 0); when x"5" => digit5_nxt <= wr_data(6 downto 0); when others => null; end case; end if; end process; process(clk, reset) begin if (reset='1') then digit0 <= (others => '1'); digit1 <= (others => '1'); digit2 <= (others => '1'); digit3 <= (others => '1'); digit4 <= (others => '1'); digit5 <= (others => '1'); elsif rising_edge(clk) then digit0 <= digit0_nxt; digit1 <= digit1_nxt; digit2 <= digit2_nxt; digit3 <= digit3_nxt; digit4 <= digit4_nxt; digit5 <= digit5_nxt; end if; end process; end rtl;

gpl-3.0

a271827eaf3b9dc52b91ae4837fa0c51

alpenwasser/pitaya

firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd

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mit

85d426f9fad89ca0518c06d50fec2be7

alpenwasser/pitaya

firmware/fpga/p_FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ip/design_1_MUX1_0/sim/design_1_MUX1_0.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: raphael-frey:user:axis_multiplexer:1.0 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY design_1_MUX1_0 IS PORT ( ClkxCI : IN STD_LOGIC; RstxRBI : IN STD_LOGIC; SelectxDI : IN STD_LOGIC_VECTOR(1 DOWNTO 0); Data0xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0); Data1xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0); Valid0xSI : IN STD_LOGIC; Valid1xSI : IN STD_LOGIC; Ready0xSO : OUT STD_LOGIC; Ready1xSO : OUT STD_LOGIC; DataxDO : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); ValidxSO : OUT STD_LOGIC; ReadyxSI : IN STD_LOGIC ); END design_1_MUX1_0; ARCHITECTURE design_1_MUX1_0_arch OF design_1_MUX1_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_MUX1_0_arch: ARCHITECTURE IS "yes"; COMPONENT multiplexer IS GENERIC ( C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_NUM_SI_SLOTS : INTEGER ); PORT ( ClkxCI : IN STD_LOGIC; RstxRBI : IN STD_LOGIC; SelectxDI : IN STD_LOGIC_VECTOR(1 DOWNTO 0); Data0xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0); Data1xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0); Data2xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0); Data3xDI : IN STD_LOGIC_VECTOR(23 DOWNTO 0); Valid0xSI : IN STD_LOGIC; Valid1xSI : IN STD_LOGIC; Valid2xSI : IN STD_LOGIC; Valid3xSI : IN STD_LOGIC; Ready0xSO : OUT STD_LOGIC; Ready1xSO : OUT STD_LOGIC; Ready2xSO : OUT STD_LOGIC; Ready3xSO : OUT STD_LOGIC; DataxDO : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); ValidxSO : OUT STD_LOGIC; ReadyxSI : IN STD_LOGIC ); END COMPONENT multiplexer; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF ClkxCI: SIGNAL IS "xilinx.com:signal:clock:1.0 SI_clk CLK"; ATTRIBUTE X_INTERFACE_INFO OF RstxRBI: SIGNAL IS "xilinx.com:signal:reset:1.0 SI_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF Data0xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TDATA"; ATTRIBUTE X_INTERFACE_INFO OF Data1xDI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TDATA"; ATTRIBUTE X_INTERFACE_INFO OF Valid0xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TVALID"; ATTRIBUTE X_INTERFACE_INFO OF Valid1xSI: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TVALID"; ATTRIBUTE X_INTERFACE_INFO OF Ready0xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI0 TREADY"; ATTRIBUTE X_INTERFACE_INFO OF Ready1xSO: SIGNAL IS "xilinx.com:interface:axis:1.0 SI1 TREADY"; ATTRIBUTE X_INTERFACE_INFO OF DataxDO: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TDATA"; ATTRIBUTE X_INTERFACE_INFO OF ValidxSO: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TVALID"; ATTRIBUTE X_INTERFACE_INFO OF ReadyxSI: SIGNAL IS "xilinx.com:interface:axis:1.0 MO TREADY"; BEGIN U0 : multiplexer GENERIC MAP ( C_AXIS_TDATA_WIDTH => 24, C_AXIS_NUM_SI_SLOTS => 2 ) PORT MAP ( ClkxCI => ClkxCI, RstxRBI => RstxRBI, SelectxDI => SelectxDI, Data0xDI => Data0xDI, Data1xDI => Data1xDI, Data2xDI => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)), Data3xDI => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)), Valid0xSI => Valid0xSI, Valid1xSI => Valid1xSI, Valid2xSI => '0', Valid3xSI => '0', Ready0xSO => Ready0xSO, Ready1xSO => Ready1xSO, DataxDO => DataxDO, ValidxSO => ValidxSO, ReadyxSI => ReadyxSI ); END design_1_MUX1_0_arch;

mit

d0bb9c3fd4f9ab5610467744e3dce711

viniciussmello/SistemasDigitais

Trabalho 1/ULA/Multiplicador.vhd

---------------------------------------------------------------------------------- -- Create Date: 15:41:26 04/11/2017 -- Module Name: Multiplicador - Behavioral -- x3y0 x2y0 x1y0 x0y0 -- x3y1 x2y1 x1y1 x0y1 -- x3y2 x2Y2 x1Y2 x0y2 -- x3y3 x2y3 x1y3 x0y3 -- Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 ---------------------------------------------------------------------------------- -- Z0 = x0y0 -- Z1 = x1y0 + x0y1 -- Z2 = x2y0 + x1y1 + x0y2 + Cin(Z1) -- Z3 = x3y0 + x2y1 + x1y2 + x0y3 -- Z4 = ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Multiplicador is port( A : in std_logic_vector (3 downto 0); B : in std_logic_vector (3 downto 0); Z : out std_logic_vector (7 downto 0) ); end Multiplicador; architecture Behavioral of Multiplicador is component Somador1bit Port ( x : in STD_LOGIC; y : in STD_LOGIC; cin : in STD_LOGIC; cout : out STD_LOGIC; z : out STD_LOGIC; p : out STD_LOGIC; g : out STD_LOGIC); end component; signal p: STD_LOGIC; signal g: STD_LOGIC; signal CoutVector: STD_LOGIC_VECTOR(7 downto 0); begin Z(0) <= A(0) and B(0); -- S0 S1: Somador1bit port map((A(1) and B(0)), (A(0) and B(1)), '0', CoutVector(0), Z(1), p, g); S2: Somador1bit port map((A(1) and B(0)), (A(0) and B(1)), CoutVector(0), CoutVector(1), Z(1), p, g); end Behavioral;

gpl-3.0

ffc3232fcd895d5129011ac355d2ef30

David-Estevez/spaceinvaders

src/edgeDetectorRiseFall.vhd

---------------------------------------------------------------------------------- -- -- Lab session #2: edge detector -- -- Detects raising edges and ouputs a one-period pulse. -- -- Authors: -- David Estévez Fernández -- Sergio Vilches Expósito -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity edgeDetectorRiseFall is port( clk: in STD_LOGIC; reset: in STD_LOGIC; enable: in STD_LOGIC; input: in STD_LOGIC; detected: out STD_LOGIC ); end edgeDetectorRiseFall; architecture Behavioral of edgeDetectorRiseFall is begin process( clk, reset) variable currentState: STD_LOGIC; variable previousState: STD_LOGIC; begin -- Reset if reset = '1' then currentState := '0'; previousState := '0'; detected <= '0'; -- Synchronous behaviour elsif clk'Event and clk = '1' then if enable = '1' then -- Update states previousState := currentState; currentState := input; -- If the current state is different from the previous one, -- an edge has arrived: detected <= currentState xor previousState; end if; end if; end process; end Behavioral;

gpl-3.0

cf059eae224e475d02e7517b73b65cf9

MiddleMan5/233

Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_FlagReg_0_0/synth/RAT_FlagReg_0_0.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:module_ref:FlagReg:1.0 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY RAT_FlagReg_0_0 IS PORT ( IN_FLAG : IN STD_LOGIC; LD : IN STD_LOGIC; SET : IN STD_LOGIC; CLR : IN STD_LOGIC; CLK : IN STD_LOGIC; OUT_FLAG : OUT STD_LOGIC ); END RAT_FlagReg_0_0; ARCHITECTURE RAT_FlagReg_0_0_arch OF RAT_FlagReg_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_FlagReg_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT FlagReg IS PORT ( IN_FLAG : IN STD_LOGIC; LD : IN STD_LOGIC; SET : IN STD_LOGIC; CLR : IN STD_LOGIC; CLK : IN STD_LOGIC; OUT_FLAG : OUT STD_LOGIC ); END COMPONENT FlagReg; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF RAT_FlagReg_0_0_arch: ARCHITECTURE IS "FlagReg,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_FlagReg_0_0_arch : ARCHITECTURE IS "RAT_FlagReg_0_0,FlagReg,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF RAT_FlagReg_0_0_arch: ARCHITECTURE IS "RAT_FlagReg_0_0,FlagReg,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=FlagReg,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK"; BEGIN U0 : FlagReg PORT MAP ( IN_FLAG => IN_FLAG, LD => LD, SET => SET, CLR => CLR, CLK => CLK, OUT_FLAG => OUT_FLAG ); END RAT_FlagReg_0_0_arch;

mit

2a058e1356697894b28378aa8427e266

VLSI-EDA/PoC-Examples

src/mem/ddr3/memtest_KC705_Vivado.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================= -- Authors: Martin Zabel -- -- Module: Memory tester for KC705 board using Xilinx MIG with one -- 512-bit port. -- -- Description: -- ------------------------------------ -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; library poc; use poc.utils.all; entity memtest_KC705 is port ( KC705_SystemClock_200MHz_p : in std_logic; KC705_SystemClock_200MHz_n : in std_logic; KC705_GPIO_LED : out std_logic_vector(7 downto 0); ddr3_dq : inout std_logic_vector(64-1 downto 0); ddr3_dqs_p : inout std_logic_vector(8-1 downto 0); ddr3_dqs_n : inout std_logic_vector(8-1 downto 0); ddr3_addr : out std_logic_vector(14-1 downto 0); ddr3_ba : out std_logic_vector(3-1 downto 0); ddr3_ras_n : out std_logic; ddr3_cas_n : out std_logic; ddr3_we_n : out std_logic; ddr3_reset_n : out std_logic; ddr3_ck_p : out std_logic_vector(1-1 downto 0); ddr3_ck_n : out std_logic_vector(1-1 downto 0); ddr3_cke : out std_logic_vector(1-1 downto 0); ddr3_cs_n : out std_logic_vector(1*1-1 downto 0); ddr3_dm : out std_logic_vector(8-1 downto 0); ddr3_odt : out std_logic_vector(1-1 downto 0)); end entity memtest_KC705; architecture rtl of memtest_KC705 is signal sysclk_unbuf : std_logic; signal refclk : std_logic; signal memtest_status : std_logic_vector(2 downto 0); -- Inputs / Outputs of MIG core signal sys_rst : std_logic; signal app_addr : std_logic_vector(28-1 downto 0); signal app_cmd : std_logic_vector(2 downto 0); signal app_en : std_logic; signal app_wdf_data : std_logic_vector((4*2*64)-1 downto 0); signal app_wdf_end : std_logic; signal app_wdf_mask : std_logic_vector((4*2*64)/8-1 downto 0); signal app_wdf_wren : std_logic; signal app_rd_data : std_logic_vector((4*2*64)-1 downto 0); signal app_rd_data_end : std_logic; signal app_rd_data_valid : std_logic; signal app_rdy : std_logic; signal app_wdf_rdy : std_logic; signal ui_clk : std_logic; signal ui_clk_sync_rst : std_logic; signal init_calib_complete : std_logic; -- component declaration required for Xilinx Vivado component mig_KC705_MT8JTF12864HZ_1G6 port ( ddr3_dq : inout std_logic_vector(63 downto 0); ddr3_dqs_p : inout std_logic_vector(7 downto 0); ddr3_dqs_n : inout std_logic_vector(7 downto 0); ddr3_addr : out std_logic_vector(13 downto 0); ddr3_ba : out std_logic_vector(2 downto 0); ddr3_ras_n : out std_logic; ddr3_cas_n : out std_logic; ddr3_we_n : out std_logic; ddr3_reset_n : out std_logic; ddr3_ck_p : out std_logic_vector(0 downto 0); ddr3_ck_n : out std_logic_vector(0 downto 0); ddr3_cke : out std_logic_vector(0 downto 0); ddr3_cs_n : out std_logic_vector(0 downto 0); ddr3_dm : out std_logic_vector(7 downto 0); ddr3_odt : out std_logic_vector(0 downto 0); app_addr : in std_logic_vector(27 downto 0); app_cmd : in std_logic_vector(2 downto 0); app_en : in std_logic; app_wdf_data : in std_logic_vector(511 downto 0); app_wdf_end : in std_logic; app_wdf_mask : in std_logic_vector(63 downto 0); app_wdf_wren : in std_logic; app_rd_data : out std_logic_vector(511 downto 0); app_rd_data_end : out std_logic; app_rd_data_valid : out std_logic; app_rdy : out std_logic; app_wdf_rdy : out std_logic; app_sr_req : in std_logic; app_ref_req : in std_logic; app_zq_req : in std_logic; app_sr_active : out std_logic; app_ref_ack : out std_logic; app_zq_ack : out std_logic; ui_clk : out std_logic; ui_clk_sync_rst : out std_logic; init_calib_complete : out std_logic; -- System Clock Ports sys_clk_i : in std_logic; -- Reference Clock Ports clk_ref_i : in std_logic; sys_rst : in std_logic ); end component mig_KC705_MT8JTF12864HZ_1G6; begin -- architecture rtl ----------------------------------------------------------------------------- -- Clock Buffer ----------------------------------------------------------------------------- -- This system clock is used two-fold: -- -- 1) It is used as the reference / system clock for the memory controllers -- (MIG). There it feeds only PLLs, so that, dedicated routing can be -- used and no BUFG is required. -- -- 2) It is also used for the IDELAYCTRL and temperature monitor logic. -- This requires a BUFG, but could also be driven by another 200 MHz -- clock source. If this other clock is not free-runnning, then -- IDELAYCTRL and the temperature monitor must be hold in reset until -- this other clock is stable. sysclk_ibuf : ibufds port map ( I => KC705_SystemClock_200MHz_p, IB => KC705_SystemClock_200MHz_n, O => sysclk_unbuf); -- sufficient for memory controllers only. refclk_bufg : bufg port map ( I => sysclk_unbuf, O => refclk); -- buffered 200 MHz reference clock ----------------------------------------------------------------------------- -- MemoryTester ----------------------------------------------------------------------------- MemoryTester : block -- The smallest addressable unit of the "app" interface has DQ_BITS bits. -- The smallest addressable unit of the "mem" interface has D_BITS bits. -- The burst length is then D_BITS / DQ_BITS. constant D_BITS : positive := 512; constant DQ_BITS : positive := 64; constant BL_BITS : natural := log2ceil(D_BITS / DQ_BITS); constant MEM_A_BITS : natural := ite(SIMULATION, 17-3, -- 128 KByte / 8 = 16 KByte per chip (on SoDIMM) 30-3) -- 1 GB / 8 = 128 MB per chip (on SoDIMM) -BL_BITS; signal mem_rdy : std_logic; signal mem_rstb : std_logic; signal mem_req : std_logic; signal mem_write : std_logic; signal mem_addr : unsigned(MEM_A_BITS-1 downto 0); signal mem_wdata : std_logic_vector(D_BITS-1 downto 0); signal mem_rdata : std_logic_vector(D_BITS-1 downto 0); begin -- block MemoryTester fsm : entity work.memtest_fsm generic map ( A_BITS => MEM_A_BITS, D_BITS => 128) -- check only 128 bits port map ( clk => ui_clk, rst => ui_clk_sync_rst, mem_rdy => mem_rdy, mem_rstb => mem_rstb, mem_rdata => mem_rdata(127 downto 0), -- check only lower 128 mem_req => mem_req, mem_write => mem_write, mem_addr => mem_addr, mem_wdata => mem_wdata(127 downto 0), status => memtest_status(2 downto 0)); mem_wdata(D_BITS-1 downto 128) <= (others => '0'); -- TODO adapter : entity poc.ddr3_mem2mig_adapter_Series7 generic map ( D_BITS => D_BITS, DQ_BITS => DQ_BITS, MEM_A_BITS => MEM_A_BITS, APP_A_BITS => app_addr'length) port map ( mem_req => mem_req, mem_write => mem_write, mem_addr => mem_addr, mem_wdata => mem_wdata, mem_rdy => mem_rdy, mem_rstb => mem_rstb, mem_rdata => mem_rdata, init_calib_complete => init_calib_complete, app_rd_data => app_rd_data, app_rd_data_end => app_rd_data_end, app_rd_data_valid => app_rd_data_valid, app_rdy => app_rdy, app_wdf_rdy => app_wdf_rdy, app_addr => app_addr, app_cmd => app_cmd, app_en => app_en, app_wdf_data => app_wdf_data, app_wdf_end => app_wdf_end, app_wdf_mask => app_wdf_mask, app_wdf_wren => app_wdf_wren); end block MemoryTester; ----------------------------------------------------------------------------- -- Memory Controller Instantiation ----------------------------------------------------------------------------- -- Apply an initial reset pulse. Required for IDELAYCTRL. sys_rst_pulse : FD generic map ( INIT => '1') port map ( D => '0', C => refclk, Q => sys_rst); mig : mig_KC705_MT8JTF12864HZ_1G6 port map ( ddr3_dq => ddr3_dq, ddr3_dqs_p => ddr3_dqs_p, ddr3_dqs_n => ddr3_dqs_n, ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_ras_n => ddr3_ras_n, ddr3_cas_n => ddr3_cas_n, ddr3_we_n => ddr3_we_n, ddr3_reset_n => ddr3_reset_n, ddr3_ck_p => ddr3_ck_p, ddr3_ck_n => ddr3_ck_n, ddr3_cke => ddr3_cke, ddr3_cs_n => ddr3_cs_n, ddr3_dm => ddr3_dm, ddr3_odt => ddr3_odt, sys_clk_i => sysclk_unbuf, clk_ref_i => refclk, app_addr => app_addr, app_cmd => app_cmd, app_en => app_en, app_wdf_data => app_wdf_data, app_wdf_end => app_wdf_end, app_wdf_mask => app_wdf_mask, app_wdf_wren => app_wdf_wren, app_rd_data => app_rd_data, app_rd_data_end => app_rd_data_end, app_rd_data_valid => app_rd_data_valid, app_rdy => app_rdy, app_wdf_rdy => app_wdf_rdy, app_sr_req => '0', -- reserved app_sr_active => open, app_ref_req => '0', -- unused app_ref_ack => open, app_zq_req => '0', -- unused app_zq_ack => open, ui_clk => ui_clk, ui_clk_sync_rst => ui_clk_sync_rst, init_calib_complete => init_calib_complete, sys_rst => sys_rst); -- active high ----------------------------------------------------------------------------- -- Status Output ----------------------------------------------------------------------------- KC705_GPIO_LED(7) <= ui_clk_sync_rst; KC705_GPIO_LED(6) <= '0'; KC705_GPIO_LED(5) <= '0'; KC705_GPIO_LED(4) <= '0'; KC705_GPIO_LED(3) <= init_calib_complete; KC705_GPIO_LED(2 downto 0) <= memtest_status; end architecture rtl;

apache-2.0

af0e7074ea6a6b5631aa7c3d17471fb6

VLSI-EDA/PoC-Examples

src/common/my_config_DE0.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann -- -- Package: Project specific configuration. -- -- Description: -- ------------------------------------ -- Configuration file for a Altera DE0 board. -- -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= -- -- package my_config is -- Change these lines to setup configuration. constant MY_BOARD : string := "DE0"; -- Altera DE0 Board (Cyclone III) constant MY_DEVICE : string := "None"; -- infer from MY_BOARD -- For internal use only constant MY_VERBOSE : boolean := FALSE; end package;

apache-2.0

bf330141ef18cc4bdd3f6d0f7ec9d712

VLSI-EDA/PoC-Examples

src/comm/remote/remote_terminal_control_top.vhdl

-- EMACS settings: -*- tab-width:2 -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ------------------------------------------------------------------------------- -- Description: Hardware Testbench for remote_terminal_control. -- See DUT description for details. -- Authors: Thomas B. Preußer <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- Copyright 2007-2014 Technische Universität Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity remote_terminal_control_top is generic ( CLK_FREQ : positive := 50000000; -- 50 MHz BAUD : positive := 115200 ); port ( clk : in std_logic; rxd : in std_logic; txd : out std_logic; sw : in std_logic_vector(7 downto 0); led : out std_logic_vector(7 downto 0) ); end remote_terminal_control_top; library IEEE; use IEEE.numeric_std.all; library poc; use poc.functions.all; use poc.uart.all; architecture rtl of remote_terminal_control_top is -- Control component remote_terminal_control is generic ( RESET_COUNT : natural; PULSE_COUNT : natural; SWITCH_COUNT : natural; LIGHT_COUNT : natural; DIGIT_COUNT : natural ); port ( -- Global Control clk : in std_logic; rst : in std_logic; -- UART Connectivity idat : in std_logic_vector(6 downto 0); istb : in std_logic; odat : out std_logic_vector(6 downto 0); ordy : in std_logic; oput : out std_logic; -- Control Outputs resets : out std_logic_vector(imax(RESET_COUNT -1, 0) downto 0); pulses : out std_logic_vector(imax(PULSE_COUNT -1, 0) downto 0); switches : out std_logic_vector(imax(SWITCH_COUNT-1, 0) downto 0); -- Monitor Inputs lights : in std_logic_vector(imax( LIGHT_COUNT-1, 0) downto 0); digits : in std_logic_vector(imax(4*DIGIT_COUNT-1, 0) downto 0) ); end component; signal rst : std_logic; signal idat : std_logic_vector(7 downto 0); signal istb : std_logic; signal odat : std_logic_vector(7 downto 0); signal oput : std_logic; signal ordy : std_logic; begin -- rtl rst <= '0'; blkUART: block signal bclk : std_logic; signal bclk_x8 : std_logic; begin rx: uart_rx generic map ( OUT_REGS => true ) port map ( clk => clk, rst => rst, bclk_x8_r => bclk_x8, rxd => rxd, dos => istb, dout => idat ); tx: uart_tx port map ( clk => clk, rst => rst, bclk_r => bclk, stb => oput, din => odat, rdy => ordy, txd => txd ); bclk_gen: uart_bclk generic map ( CLK_FREQ => CLK_FREQ, BAUD => BAUD ) port map ( clk => clk, rst => rst, bclk_r => bclk, bclk_x8_r => bclk_x8 ); end block blkUART; term_ctrl: remote_terminal_control generic map ( RESET_COUNT => 0, PULSE_COUNT => 0, SWITCH_COUNT => 8, LIGHT_COUNT => 8, DIGIT_COUNT => 2 ) port map ( clk => clk, rst => rst, idat => idat(6 downto 0), istb => istb, odat => odat(6 downto 0), ordy => ordy, oput => oput, resets => open, pulses => open, switches => led, lights => sw, digits => sw ); odat(7) <= '0'; end rtl;

apache-2.0

33077e4ce891a6745b5ebf2baeaa258c

VLSI-EDA/PoC-Examples

src/common/my_config_ML505.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann -- -- Package: Project specific configuration. -- -- Description: -- ------------------------------------ -- Configuration file for a Xilinx ML505 board. -- -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= -- -- package my_config is -- Change these lines to setup configuration. constant MY_BOARD : string := "ML505"; -- ML505 - Xilinx Virtex 5 reference design board: XC5VLX50T constant MY_DEVICE : string := "None"; -- infer from MY_BOARD -- constant MY_VERBOSE : boolean := FALSE; -- activate detailed report statements in functions and procedures end package;

apache-2.0

56e8388bae723879f2036f9d922f6a4a

MiddleMan5/233

Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_FlagReg_1_0/RAT_FlagReg_1_0_sim_netlist.vhdl

-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -- Date : Fri Oct 27 00:02:33 2017 -- Host : Juice-Laptop running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- C:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_FlagReg_1_0/RAT_FlagReg_1_0_sim_netlist.vhdl -- Design : RAT_FlagReg_1_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7a35tcpg236-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity RAT_FlagReg_1_0_FlagReg is port ( OUT_FLAG : out STD_LOGIC; IN_FLAG : in STD_LOGIC; SET : in STD_LOGIC; LD : in STD_LOGIC; CLR : in STD_LOGIC; CLK : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of RAT_FlagReg_1_0_FlagReg : entity is "FlagReg"; end RAT_FlagReg_1_0_FlagReg; architecture STRUCTURE of RAT_FlagReg_1_0_FlagReg is signal \^out_flag\ : STD_LOGIC; signal OUT_FLAG_i_1_n_0 : STD_LOGIC; begin OUT_FLAG <= \^out_flag\; OUT_FLAG_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"ACAFACAC" ) port map ( I0 => IN_FLAG, I1 => SET, I2 => LD, I3 => CLR, I4 => \^out_flag\, O => OUT_FLAG_i_1_n_0 ); OUT_FLAG_reg: unisim.vcomponents.FDRE port map ( C => CLK, CE => '1', D => OUT_FLAG_i_1_n_0, Q => \^out_flag\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity RAT_FlagReg_1_0 is port ( IN_FLAG : in STD_LOGIC; LD : in STD_LOGIC; SET : in STD_LOGIC; CLR : in STD_LOGIC; CLK : in STD_LOGIC; OUT_FLAG : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of RAT_FlagReg_1_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of RAT_FlagReg_1_0 : entity is "RAT_FlagReg_1_0,FlagReg,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of RAT_FlagReg_1_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of RAT_FlagReg_1_0 : entity is "FlagReg,Vivado 2016.4"; end RAT_FlagReg_1_0; architecture STRUCTURE of RAT_FlagReg_1_0 is begin U0: entity work.RAT_FlagReg_1_0_FlagReg port map ( CLK => CLK, CLR => CLR, IN_FLAG => IN_FLAG, LD => LD, OUT_FLAG => OUT_FLAG, SET => SET ); end STRUCTURE;

mit

20614965ed1385a8fc5dd4b47408c015

stefanct/aua

hw/sim/tb_gate.vhd

library ieee; use ieee.std_logic_1164.all; use work.aua_types.all; entity aua_tb is end aua_tb; architecture aua_test of aua_tb is component aua port ( clk_in : in std_logic; reset_pin : in std_logic; switch_pins : in std_logic_vector(15 downto 0); led_pins : out std_logic_vector(15 downto 0); digit0_pins : out std_logic_vector(6 downto 0); digit1_pins : out std_logic_vector(6 downto 0); digit2_pins : out std_logic_vector(6 downto 0); digit3_pins : out std_logic_vector(6 downto 0); digit4_pins : out std_logic_vector(6 downto 0); digit5_pins : out std_logic_vector(6 downto 0); sram_addr : out std_logic_vector(RAM_ADDR_SIZE-1 downto 0); sram_dq : inout word_t; sram_we : out std_logic; -- sram_oe : out std_logic; sram_ub : out std_logic; sram_lb : out std_logic; -- sram_ce : out std_logic txd : out std_logic; rxd : in std_ulogic --~ ncts : in std_logic; --~ nrts : out std_logic ); end component; signal clk : std_logic; signal reset_pin : std_logic; signal switch_pins : std_logic_vector(15 downto 0); signal led_pins : std_logic_vector(15 downto 0); signal digit0_pins : std_logic_vector(6 downto 0); signal digit1_pins : std_logic_vector(6 downto 0); signal digit2_pins : std_logic_vector(6 downto 0); signal digit3_pins : std_logic_vector(6 downto 0); signal digit4_pins : std_logic_vector(6 downto 0); signal digit5_pins : std_logic_vector(6 downto 0); signal sram_addr : std_logic_vector(RAM_ADDR_SIZE-1 downto 0); signal sram_dq : word_t; signal sram_we : std_logic; signal sram_ub : std_logic; signal sram_lb : std_logic; signal txd : std_logic; signal rxd : std_logic; constant freq: natural := 70000000; constant clk_tick: natural := 1000000000/freq; constant uart_baud: natural := 115200; constant uart_clks: natural := freq/uart_baud; begin uart: process procedure icwait(cycles : natural) is begin for i in 1 to cycles loop wait until clk = '0' and clk'event; end loop; end; begin rxd <= '0'; icwait(uart_clks*2); rxd <= '1'; icwait(uart_clks); rxd <= '0'; icwait(uart_clks*2); rxd <= '1'; icwait(uart_clks*2); rxd <= '0'; icwait(uart_clks*2); rxd <= '1'; icwait(uart_clks*2); end process; --~ aua1: configuration work.aua_cache aua1: aua port map ( clk_in => clk, reset_pin => reset_pin, switch_pins => switch_pins, led_pins => led_pins, digit0_pins => digit0_pins, digit1_pins => digit1_pins, digit2_pins => digit2_pins, digit3_pins => digit3_pins, digit4_pins => digit4_pins, digit5_pins => digit5_pins, sram_addr => sram_addr, sram_dq => sram_dq, sram_we => sram_we, sram_ub => sram_ub, sram_lb => sram_lb, txd => txd, rxd => rxd ); CLKGEN: process begin clk <= '1'; wait for 10 ns; clk <= '0'; wait for 10 ns; end process CLKGEN; TEST: process procedure icwait(cycles : natural) is begin for i in 1 to cycles loop wait until clk = '0' and clk'event; end loop; end; begin reset_pin <= '0'; switch_pins <= x"ffff"; sram_dq <= (others => '0'); --~ rxd <= '0'; icwait(2); reset_pin <= '1'; icwait(9000); assert false report "sim finish" SEVERITY failure; end process TEST; end aua_test;

gpl-3.0

717050705faddd4a19da5cac568d7f1e

ErikAndren/SG90-PWM

Clk1Hz.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.Types.all; use ieee.std_logic_unsigned.all; entity clk1Hz is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; clk_out: out STD_LOGIC ); end; architecture Behavioral of clk1Hz is signal temporal: STD_LOGIC; constant HalfPeriod : positive := 25000000; signal counter : word(bits(HalfPeriod)-1 downto 0); begin freq_divider: process (reset, clk) begin if (reset = '0') then temporal <= '0'; counter <= (others => '0'); elsif rising_edge(clk) then if (counter = HalfPeriod) then temporal <= not temporal; counter <= (others => '0'); else counter <= counter + 1; end if; end if; end process; clk_out <= temporal; end Behavioral;

gpl-2.0

836cb88ecae9b66a0910d8dcd3a97400

alpenwasser/pitaya

firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/xilinx.com/fir_compiler_v7_2/hdl/fir_compiler_v7_2.vhd

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mit

b440279b9b4fd536982c4a8fc3313b6b

alpenwasser/pitaya

firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_bram18k_v3_0/hdl/xbip_bram18k_v3_0_vh_rfs.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block cQDd3XIPPlgRDhqULvYHvwCty2ZrVwzfefmANvx1dZIylIMC/SlAcj88wfYJOEUSOPC1U3p3rRJH cF/G+RPdfg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hcwXqOGXIKp1yMXglvtwKNDD2csTguI/218BbAfP1Qe5YaY7t7J14bh3PN4/sY8v5SUfs5PPhYYF AVoQ7+Y8KyIAkFOjVjl8Q3cizlaMAyaX6UCc4wmflvCCOjy7mkT0VJKPELyiFH5OE1gTiKu4NfqY cLpas2QiSAVn/xZw83g= `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block JJiSVarYWytdLFzHp3wkrD5+jxEb6zxCxwIxMuHES7X4vO/81ppoMZmSB67P59pBX5Chyu0EswKT bCRha6XDZljqkcBWrrqj3cLRE57UCaEr1RVpDNBMw7hjNrwCb9eTELEwb3X0mZPKBqVrRNroBMN5 Mb9o7SPJ2GKhIDEDF5Q= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block x9rjekK3vn0E248BFQkRU8rm2REs1XV6NiMfscimCVnt3moe1QOgVJzTLPCcPYvThLcZJXwVyFUX J1k2lVxuHKaC3FNNToKLX7girUcVANbS6jS2AjaAfdpYmQXF6epSjXy+KOWM7AfrGv2r7XNIcV6T P4He3ZDDIABlWanBaDiVD6NYtB9SspFXaifjJ2faT9Et8gWmYJogYQ4BjXl960BUcxWS5faBudWm MidcfsfVFpzH5bJ9L+thBkdIh/P3Rjr9ssCSzEagp+1l0DsZGX583KqMaKiaZiIsR+KyQ8Hrld0H vh5k+kh3k9z7ewkJNwM0LCpa2Y0qGSJOxIauzg== `protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block bMGW+/GNxe7XIGxZQsPwYg9NhBUySelE4d3DawPwcsMkcAefxMJ1JdlslSvSp+VjxIobQhkauqfs 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mit

be9a61457bba303124ecafc7eec0a6bb

David-Estevez/spaceinvaders

src/invaders.vhd

---------------------------------------------------------------------------------- -- -- Lab session #4: Invaders -- -- Block controlling the space invaders -- -- Each invader has its power encoded in 2 bits: -- 00 -> no invader -- 01 -> easy invader (1 shot) -- 10 -> medium invader (2 shots) -- 11 -> hard invader (3 shots) -- -- Authors: -- David Estévez Fernández -- Sergio Vilches Expósito -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity invaders is port ( clk : in std_logic; reset : in std_logic; clear : in std_logic; start : in std_logic; bullX1 : in std_logic_vector(4 downto 0); bullY1 : in std_logic_vector(3 downto 0); hit1 : out std_logic; bullX2 : in std_logic_vector(4 downto 0); bullY2 : in std_logic_vector(3 downto 0); hit2 : out std_logic; invArray : inout std_logic_vector(39 downto 0); invLine : inout std_logic_vector(3 downto 0); level : in std_logic_vector( 2 downto 0 ) ); end invaders; architecture behavioral of invaders is signal right : std_logic := '0'; -- movement of invaders: 1 = right; signal tick, tick1, tick2 : std_logic; -- Signal from timer signal moving : std_logic; signal sighit1, sighit2: std_logic; type INVADERMATRIX is array( 0 to 7) of std_logic_vector( 39 downto 0); constant initArray : INVADERMATRIX := ( "0000000000000000000001010101010101010101", -- level 1 "0000000000000000000001010101101001010101", -- level 2 "0000000000000000000001010110101010010101", -- level 3 "0000000000000000000001011010101010100101", -- level 4 "0000000000000000000010101010101010101010", -- level 5 "0000000000000000000001011010111110100101", -- level 6 "0000000000000000000001011011111111100101", -- level 7 "0000000000000000000011111111111111111111" -- level 8 ); --signal internalInvLine: std_logic_vector( 3 downto 0); component timer generic (t: integer); port( clk : in std_logic; reset : in std_logic; clear : in std_logic; en : in std_logic; q : out std_logic ); end component; signal enableTim1, enableTim2: std_logic; begin -- Instantiate a timer for invaders movement timing speedTimer1: timer generic map (400) -- Set this to a value around 10 for a faster simulation port map ( clk => clk, reset => reset, clear => clear, en => enableTim1, q => tick1 ); speedTimer2: timer generic map (200) -- Set this to a value around 10 for a faster simulation port map ( clk => clk, reset => reset, clear => clear, en => enableTim2, q => tick2 ); -- Timers control tick <= tick1 or tick2; enableTim1 <= '1' when level(2) = '0' else '0'; enableTim2 <= not enableTim1; -- Main process process (reset, clk, sighit1, sighit2) variable intBulletX1: integer range 0 to 39; -- Temporarily storage for bullet 1 X position translated into 2-bit-per-alien coordinates variable intBulletX2: integer range 0 to 39; -- Temporarily storage for bullet 2 X position translated into 2-bit-per-alien coordinates variable intLevel: integer range 0 to 7; -- Temporarily storage for level variable currentInvader: std_logic_vector(1 downto 0); begin if reset = '1' then --Default values: moving <= '0'; right <= '0'; sighit1 <= '0'; sighit2 <= '0'; -- Choose this value for simulating 'you win' state: --invArray <= "0000000000000000000000000000000000000000" ; -- Otherwise, this is the correct value (for first level): intLevel := to_integer( unsigned( level)); invArray <= initArray( intLevel ); -- Choose this value for simulating 'you lose' state: invLine <= "1101"; -- Otherwise, this is the correct value: --invLine <= "0000"; elsif clk'event and clk = '1' then if Clear = '1' then --Default values: moving <= '0'; right <= '0'; sighit1 <= '0'; sighit2 <= '0'; -- Choose this value for simulating 'you win' state: --invArray <= "0000000000000000000000000000000000000000" ; -- Otherwise, this is the correct value (for first level): intLevel := to_integer( unsigned( level)); invArray <= initArray( intLevel ); -- Choose this value for simulating 'you lose' state: -- invLine <= "1101"; -- Otherwise, this is the correct value: invLine <= "0000"; else -- Sequential behaviors: if (start = '1') then moving <= '1'; -- Set this to '0' to stop the invaders when testing the bullet end if; if (tick = '1') and (moving = '1') then -- Moving to the right if right = '0' then -- Condition for reaching the end of the line: there is at least a '1' in either of the 2 final values if invArray(39 downto 38) /= "00" then right <= '1'; -- Prevent further movement if the end has been reached if invLine /= "1110" then invLine <= std_logic_vector(unsigned(invLine) + to_unsigned(1,4)); -- Invaders Line ++ else moving <= '0'; end if; else invArray <= invArray(37 downto 0) & "00"; end if; -- Moving to the left else -- Condition for reaching the beginning of the line: there is at least a '1' in either of the 2 first positions if invArray(1 downto 0) /= "00" then right <= '0'; -- Prevent further movement if the end has been reached if invLine /= "1110" then invLine <= std_logic_vector(unsigned(invLine) + to_unsigned(1,4)); -- Invaders Line ++ else moving <= '0'; end if; else invArray <= "00" & invArray(39 downto 2); end if; end if; end if; -- Checking for bullet 1 -- [ There is an alien if there is a '1' in either the position bullX*2 or bullX*2+1 ] intBulletX1 := to_integer(unsigned(bullX1))*2; if (sighit1 = '0' ) and (bullY1 = invLine) and invArray( intBulletX1 + 1 downto intBulletX1 ) /= "00" then sighit1 <= '1'; -- Substract 1 to the alien power -- currentInvader := invArray( intBulletX1+1 downto intBulletX1 ) ; -- case currentInvader is -- when "01" => invArray( intBulletX1+1 downto intBulletX1 ) <= "00"; -- when "10" => invArray( intBulletX1+1 downto intBulletX1 ) <= "01"; -- when "11" => invArray( intBulletX1+1 downto intBulletX1 ) <= "10"; -- when others => invArray( intBulletX1+1 downto intBulletX1 ) <= "00"; -- end case; invArray( intBulletX1+1 downto intBulletX1 ) <= std_logic_vector(unsigned( invArray( intBulletX1+1 downto intBulletX1 )) - 1 ); else sighit1 <= '0'; end if ; -- Checking for bullet2 -- [ There is an alien if there is a '1' in either the position bullX*2 or bullX*2+1 ] intBulletX2 := to_integer(unsigned(bullX2))*2; if ( sighit2 = '0' ) and (bullY2 = invLine) and invArray( intBulletX2 + 1 downto intBulletX2 ) /= "00" then sighit2 <= '1'; -- Substract 1 to the alien power -- currentInvader := invArray( intBulletX2+1 downto intBulletX2 ) ; -- case currentInvader is -- when "01" => invArray( intBulletX2+1 downto intBulletX2 ) <= "00"; -- when "10" => invArray( intBulletX2+1 downto intBulletX2 ) <= "01"; -- when "11" => invArray( intBulletX2+1 downto intBulletX2 ) <= "10"; -- when others => invArray( intBulletX1+1 downto intBulletX1 ) <= "00"; -- end case; invArray( intBulletX2+1 downto intBulletX2 ) <= std_logic_vector(unsigned( invArray( intBulletX2+1 downto intBulletX2 )) - 1 ); else sighit2 <= '0'; end if ; end if; end if; -- Set hit outputs hit1 <= sighit1; hit2 <= sighit2; end process; end behavioral;

gpl-3.0

e8037ab2efbc362c0053f4f56cf59266

MiddleMan5/233

Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux2x1_10_0_0/synth/RAT_Mux2x1_10_0_0.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:module_ref:Mux2x1_10:1.0 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY RAT_Mux2x1_10_0_0 IS PORT ( A : IN STD_LOGIC_VECTOR(9 DOWNTO 0); B : IN STD_LOGIC_VECTOR(9 DOWNTO 0); SEL : IN STD_LOGIC; X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END RAT_Mux2x1_10_0_0; ARCHITECTURE RAT_Mux2x1_10_0_0_arch OF RAT_Mux2x1_10_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_Mux2x1_10_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT Mux2x1_10 IS PORT ( A : IN STD_LOGIC_VECTOR(9 DOWNTO 0); B : IN STD_LOGIC_VECTOR(9 DOWNTO 0); SEL : IN STD_LOGIC; X : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT Mux2x1_10; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF RAT_Mux2x1_10_0_0_arch: ARCHITECTURE IS "Mux2x1_10,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_Mux2x1_10_0_0_arch : ARCHITECTURE IS "RAT_Mux2x1_10_0_0,Mux2x1_10,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF RAT_Mux2x1_10_0_0_arch: ARCHITECTURE IS "RAT_Mux2x1_10_0_0,Mux2x1_10,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=Mux2x1_10,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; BEGIN U0 : Mux2x1_10 PORT MAP ( A => A, B => B, SEL => SEL, X => X ); END RAT_Mux2x1_10_0_0_arch;

mit

940d2a5b363484e76a08ec656501ffe0

viniciussmello/SistemasDigitais

Trabalho 2/Principal/ps2_keyboard_to_ascii.vhd

--traduzindo-- -------------------------------------------------------------------------------- -- -- FileName: ps2_keyboard_to_ascii.vhd -- Dependencies: ps2_keyboard.vhd, debounce.vhd -- Design Software: Quartus II 32-bit Version 12.1 Build 177 SJ Full Version -- -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. -- -- Version History -- Version 1.0 11/29/2013 Scott Larson -- Initial Public Release -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ps2_keyboard_to_ascii IS GENERIC( clk_freq : INTEGER := 50_000_000; --system clock frequency in Hz ps2_debounce_counter_size : INTEGER := 8); --set such that 2^size/clk_freq = 5us (size = 8 for 50MHz) PORT( clk : IN STD_LOGIC; --system clock input ps2_clk : IN STD_LOGIC; --clock signal from PS2 keyboard ps2_data : IN STD_LOGIC; --data signal from PS2 keyboard ascii_new : OUT STD_LOGIC; --output flag indicating new ASCII value ascii_code : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); --ASCII value END ps2_keyboard_to_ascii; ARCHITECTURE behavior OF ps2_keyboard_to_ascii IS TYPE machine IS(ready, new_code, translate, output); --needed states SIGNAL state : machine; --state machine SIGNAL ps2_code_new : STD_LOGIC; --new PS2 code flag from ps2_keyboard component SIGNAL ps2_code : STD_LOGIC_VECTOR(7 DOWNTO 0); --PS2 code input form ps2_keyboard component SIGNAL prev_ps2_code_new : STD_LOGIC := '1'; --value of ps2_code_new flag on previous clock SIGNAL break : STD_LOGIC := '0'; --'1' for break code, '0' for make code SIGNAL e0_code : STD_LOGIC := '0'; --'1' for multi-code commands, '0' for single code commands SIGNAL caps_lock : STD_LOGIC := '0'; --'1' if caps lock is active, '0' if caps lock is inactive SIGNAL control_r : STD_LOGIC := '0'; --'1' if right control key is held down, else '0' SIGNAL control_l : STD_LOGIC := '0'; --'1' if left control key is held down, else '0' SIGNAL shift_r : STD_LOGIC := '0'; --'1' if right shift is held down, else '0' SIGNAL shift_l : STD_LOGIC := '0'; --'1' if left shift is held down, else '0' SIGNAL ascii : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"FF"; --internal value of ASCII translation --declare PS2 keyboard interface component COMPONENT ps2_keyboard IS GENERIC( clk_freq : INTEGER; --system clock frequency in Hz debounce_counter_size : INTEGER); --set such that 2^size/clk_freq = 5us (size = 8 for 50MHz) PORT( clk : IN STD_LOGIC; --system clock ps2_clk : IN STD_LOGIC; --clock signal from PS2 keyboard ps2_data : IN STD_LOGIC; --data signal from PS2 keyboard ps2_code_new : OUT STD_LOGIC; --flag that new PS/2 code is available on ps2_code bus ps2_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --code received from PS/2 END COMPONENT; BEGIN --instantiate PS2 keyboard interface logic ps2_keyboard_0: ps2_keyboard GENERIC MAP(clk_freq => clk_freq, debounce_counter_size => ps2_debounce_counter_size) PORT MAP(clk => clk, ps2_clk => ps2_clk, ps2_data => ps2_data, ps2_code_new => ps2_code_new, ps2_code => ps2_code); PROCESS(clk) BEGIN IF(clk'EVENT AND clk = '1') THEN prev_ps2_code_new <= ps2_code_new; --keep track of previous ps2_code_new values to determine low-to-high transitions CASE state IS --ready state: wait for a new PS2 code to be received WHEN ready => IF(prev_ps2_code_new = '0' AND ps2_code_new = '1') THEN --new PS2 code received ascii_new <= '0'; --reset new ASCII code indicator state <= new_code; --proceed to new_code state ELSE --no new PS2 code received yet state <= ready; --remain in ready state END IF; --new_code state: determine what to do with the new PS2 code WHEN new_code => IF(ps2_code = x"F0") THEN --code indicates that next command is break break <= '1'; --set break flag state <= ready; --return to ready state to await next PS2 code ELSIF(ps2_code = x"E0") THEN --code indicates multi-key command e0_code <= '1'; --set multi-code command flag state <= ready; --return to ready state to await next PS2 code ELSE --code is the last PS2 code in the make/break code ascii(7) <= '1'; --set internal ascii value to unsupported code (for verification) state <= translate; --proceed to translate state END IF; --translate state: translate PS2 code to ASCII value WHEN translate => break <= '0'; --reset break flag e0_code <= '0'; --reset multi-code command flag --handle codes for control, shift, and caps lock CASE ps2_code IS WHEN x"58" => --caps lock code IF(break = '0') THEN --if make command caps_lock <= NOT caps_lock; --toggle caps lock END IF; WHEN x"14" => --code for the control keys IF(e0_code = '1') THEN --code for right control control_r <= NOT break; --update right control flag ELSE --code for left control control_l <= NOT break; --update left control flag END IF; WHEN x"12" => --left shift code shift_l <= NOT break; --update left shift flag WHEN x"59" => --right shift code shift_r <= NOT break; --update right shift flag WHEN OTHERS => NULL; END CASE; --translate control codes (these do not depend on shift or caps lock) IF(control_l = '1' OR control_r = '1') THEN CASE ps2_code IS WHEN x"1E" => ascii <= x"00"; --^@ NUL WHEN x"1C" => ascii <= x"01"; --^A SOH WHEN x"32" => ascii <= x"02"; --^B STX WHEN x"21" => ascii <= x"03"; --^C ETX WHEN x"23" => ascii <= x"04"; --^D EOT WHEN x"24" => ascii <= x"05"; --^E ENQ WHEN x"2B" => ascii <= x"06"; --^F ACK WHEN x"34" => ascii <= x"07"; --^G BEL WHEN x"33" => ascii <= x"08"; --^H BS WHEN x"43" => ascii <= x"09"; --^I HT WHEN x"3B" => ascii <= x"0A"; --^J LF WHEN x"42" => ascii <= x"0B"; --^K VT WHEN x"4B" => ascii <= x"0C"; --^L FF WHEN x"3A" => ascii <= x"0D"; --^M CR WHEN x"31" => ascii <= x"0E"; --^N SO WHEN x"44" => ascii <= x"0F"; --^O SI WHEN x"4D" => ascii <= x"10"; --^P DLE WHEN x"15" => ascii <= x"11"; --^Q DC1 WHEN x"2D" => ascii <= x"12"; --^R DC2 WHEN x"1B" => ascii <= x"13"; --^S DC3 WHEN x"2C" => ascii <= x"14"; --^T DC4 WHEN x"3C" => ascii <= x"15"; --^U NAK WHEN x"2A" => ascii <= x"16"; --^V SYN WHEN x"1D" => ascii <= x"17"; --^W ETB WHEN x"22" => ascii <= x"18"; --^X CAN WHEN x"35" => ascii <= x"19"; --^Y EM WHEN x"1A" => ascii <= x"1A"; --^Z SUB WHEN x"54" => ascii <= x"1B"; --^[ ESC WHEN x"5D" => ascii <= x"1C"; --^\ FS WHEN x"5B" => ascii <= x"1D"; --^] GS WHEN x"36" => ascii <= x"1E"; --^^ RS WHEN x"4E" => ascii <= x"1F"; --^_ US WHEN x"4A" => ascii <= x"7F"; --^? DEL WHEN OTHERS => NULL; END CASE; ELSE --if control keys are not pressed --translate characters that do not depend on shift, or caps lock CASE ps2_code IS WHEN x"29" => ascii <= x"20"; --space WHEN x"66" => ascii <= x"08"; --backspace (BS control code) WHEN x"0D" => ascii <= x"09"; --tab (HT control code) WHEN x"5A" => ascii <= x"0D"; --enter (CR control code) WHEN x"76" => ascii <= x"1B"; --escape (ESC control code) WHEN x"71" => IF(e0_code = '1') THEN --ps2 code for delete is a multi-key code ascii <= x"7F"; --delete END IF; WHEN OTHERS => NULL; END CASE; --translate letters (these depend on both shift and caps lock) IF((shift_r = '0' AND shift_l = '0' AND caps_lock = '0') OR ((shift_r = '1' OR shift_l = '1') AND caps_lock = '1')) THEN --letter is lowercase CASE ps2_code IS WHEN x"1C" => ascii <= x"61"; --a WHEN x"32" => ascii <= x"62"; --b WHEN x"21" => ascii <= x"63"; --c WHEN x"23" => ascii <= x"64"; --d WHEN x"24" => ascii <= x"65"; --e WHEN x"2B" => ascii <= x"66"; --f WHEN x"34" => ascii <= x"67"; --g WHEN x"33" => ascii <= x"68"; --h WHEN x"43" => ascii <= x"69"; --i WHEN x"3B" => ascii <= x"6A"; --j WHEN x"42" => ascii <= x"6B"; --k WHEN x"4B" => ascii <= x"6C"; --l WHEN x"3A" => ascii <= x"6D"; --m WHEN x"31" => ascii <= x"6E"; --n WHEN x"44" => ascii <= x"6F"; --o WHEN x"4D" => ascii <= x"70"; --p WHEN x"15" => ascii <= x"71"; --q WHEN x"2D" => ascii <= x"72"; --r WHEN x"1B" => ascii <= x"73"; --s WHEN x"2C" => ascii <= x"74"; --t WHEN x"3C" => ascii <= x"75"; --u WHEN x"2A" => ascii <= x"76"; --v WHEN x"1D" => ascii <= x"77"; --w WHEN x"22" => ascii <= x"78"; --x WHEN x"35" => ascii <= x"79"; --y WHEN x"1A" => ascii <= x"7A"; --z WHEN OTHERS => NULL; END CASE; ELSE --letter is uppercase CASE ps2_code IS WHEN x"1C" => ascii <= x"41"; --A WHEN x"32" => ascii <= x"42"; --B WHEN x"21" => ascii <= x"43"; --C WHEN x"23" => ascii <= x"44"; --D WHEN x"24" => ascii <= x"45"; --E WHEN x"2B" => ascii <= x"46"; --F WHEN x"34" => ascii <= x"47"; --G WHEN x"33" => ascii <= x"48"; --H WHEN x"43" => ascii <= x"49"; --I WHEN x"3B" => ascii <= x"4A"; --J WHEN x"42" => ascii <= x"4B"; --K WHEN x"4B" => ascii <= x"4C"; --L WHEN x"3A" => ascii <= x"4D"; --M WHEN x"31" => ascii <= x"4E"; --N WHEN x"44" => ascii <= x"4F"; --O WHEN x"4D" => ascii <= x"50"; --P WHEN x"15" => ascii <= x"51"; --Q WHEN x"2D" => ascii <= x"52"; --R WHEN x"1B" => ascii <= x"53"; --S WHEN x"2C" => ascii <= x"54"; --T WHEN x"3C" => ascii <= x"55"; --U WHEN x"2A" => ascii <= x"56"; --V WHEN x"1D" => ascii <= x"57"; --W WHEN x"22" => ascii <= x"58"; --X WHEN x"35" => ascii <= x"59"; --Y WHEN x"1A" => ascii <= x"5A"; --Z WHEN OTHERS => NULL; END CASE; END IF; --translate numbers and symbols (these depend on shift but not caps lock) IF(shift_l = '1' OR shift_r = '1') THEN --key's secondary character is desired CASE ps2_code IS WHEN x"16" => ascii <= x"21"; --! WHEN x"52" => ascii <= x"22"; --" WHEN x"26" => ascii <= x"23"; --# WHEN x"25" => ascii <= x"24"; --$ WHEN x"2E" => ascii <= x"25"; --% WHEN x"3D" => ascii <= x"26"; --& WHEN x"46" => ascii <= x"28"; --( WHEN x"45" => ascii <= x"29"; --) WHEN x"3E" => ascii <= x"2A"; --* WHEN x"55" => ascii <= x"2B"; --+ WHEN x"4C" => ascii <= x"3A"; --: WHEN x"41" => ascii <= x"3C"; --< WHEN x"49" => ascii <= x"3E"; --> WHEN x"4A" => ascii <= x"3F"; --? WHEN x"1E" => ascii <= x"40"; --@ WHEN x"36" => ascii <= x"5E"; --^ WHEN x"4E" => ascii <= x"5F"; --_ WHEN x"54" => ascii <= x"7B"; --{ WHEN x"5D" => ascii <= x"7C"; --| WHEN x"5B" => ascii <= x"7D"; --} WHEN x"0E" => ascii <= x"7E"; --~ WHEN OTHERS => NULL; END CASE; ELSE --key's primary character is desired CASE ps2_code IS WHEN x"45" => ascii <= x"30"; --0 WHEN x"16" => ascii <= x"31"; --1 WHEN x"1E" => ascii <= x"32"; --2 WHEN x"26" => ascii <= x"33"; --3 WHEN x"25" => ascii <= x"34"; --4 WHEN x"2E" => ascii <= x"35"; --5 WHEN x"36" => ascii <= x"36"; --6 WHEN x"3D" => ascii <= x"37"; --7 WHEN x"3E" => ascii <= x"38"; --8 WHEN x"46" => ascii <= x"39"; --9 WHEN x"52" => ascii <= x"27"; --' WHEN x"41" => ascii <= x"2C"; --, WHEN x"4E" => ascii <= x"2D"; --- WHEN x"49" => ascii <= x"2E"; --. WHEN x"4A" => ascii <= x"2F"; --/ WHEN x"4C" => ascii <= x"3B"; --; WHEN x"55" => ascii <= x"3D"; --= WHEN x"54" => ascii <= x"5B"; --[ WHEN x"5D" => ascii <= x"5C"; --\ WHEN x"5B" => ascii <= x"5D"; --] WHEN x"0E" => ascii <= x"60"; --` WHEN OTHERS => NULL; END CASE; END IF; END IF; IF(break = '0') THEN --the code is a make state <= output; --proceed to output state ELSE --code is a break state <= ready; --return to ready state to await next PS2 code END IF; --output state: verify the code is valid and output the ASCII value WHEN output => IF(ascii(7) = '0') THEN --the PS2 code has an ASCII output ascii_new <= '1'; --set flag indicating new ASCII output ascii_code <= ascii(6 DOWNTO 0); --output the ASCII value END IF; state <= ready; --return to ready state to await next PS2 code END CASE; END IF; END PROCESS; END behavior;

gpl-3.0

e8b43485f5b8631e5ea839e7fb8c396d

open-power/snap

actions/hdl_nvme_example/hw/action_axi_slave.vhd

---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- -- Copyright 2017 International Business Machines -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions AND -- limitations under the License. -- ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY action_axi_slave IS GENERIC ( -- Width of S_AXI data bus C_S_AXI_DATA_WIDTH : integer := 32; -- Width of S_AXI address bus C_S_AXI_ADDR_WIDTH : integer := 6 ); PORT ( reg_0x10_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); reg_0x14_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); reg_0x20_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); reg_0x30_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); reg_0x34_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); reg_0x38_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); reg_0x3c_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); reg_0x40_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); reg_0x44_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); reg_0x48_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); reg_0x4c_req_error_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0); reg_0x4c_nvme_error_i : IN STD_LOGIC_VECTOR( 2 DOWNTO 0); reg_0x4c_completion_i : IN STD_LOGIC_VECTOR( 4 DOWNTO 0); reg_0x4c_rd_strobe_o : OUT STD_LOGIC; reg_0x50_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); reg_0x54_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); int_enable_o : OUT STD_LOGIC; app_start_o : OUT STD_LOGIC; app_done_i : IN STD_LOGIC; app_ready_i : IN STD_LOGIC; app_idle_i : IN STD_LOGIC; -- AXI Slave interface -- Global Clock Signal S_AXI_ACLK : IN STD_LOGIC; -- Global Reset Signal. This Signal is Active LOW S_AXI_ARESETN : IN STD_LOGIC; -- Write address (issued by master, acceped by Slave) S_AXI_AWADDR : IN STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0); -- Write address valid. This signal indicates that the master signaling -- valid write address and control information. S_AXI_AWVALID : IN STD_LOGIC; -- Write address ready. This signal indicates that the slave is ready -- to accept an address and associated control signals. S_AXI_AWREADY : OUT STD_LOGIC; -- Write data (issued by master, acceped by Slave) S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); -- Write strobes. This signal indicates which byte lanes hold -- valid data. There is one write strobe bit for each eight -- bits of the write data bus. S_AXI_WSTRB : IN STD_LOGIC_VECTOR((C_S_AXI_DATA_WIDTH/8)-1 DOWNTO 0); -- Write valid. This signal indicates that valid write -- data and strobes are available. S_AXI_WVALID : IN STD_LOGIC; -- Write ready. This signal indicates that the slave -- can accept the write data. S_AXI_WREADY : OUT STD_LOGIC; -- Write response. This signal indicates the status -- of the write transaction. S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- Write response valid. This signal indicates that the channel -- is signaling a valid write response. S_AXI_BVALID : OUT STD_LOGIC; -- Response ready. This signal indicates that the master -- can accept a write response. S_AXI_BREADY : IN STD_LOGIC; -- Read address (issued by master, acceped by Slave) S_AXI_ARADDR : IN STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0); -- Read address valid. This signal indicates that the channel -- is signaling valid read address and control information. S_AXI_ARVALID : IN STD_LOGIC; -- Read address ready. This signal indicates that the slave is -- ready to accept an address and associated control signals. S_AXI_ARREADY : OUT STD_LOGIC; -- Read data (issued by slave) S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); -- Read response. This signal indicates the status of the -- read transfer. S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- Read valid. This signal indicates that the channel is -- signaling the required read data. S_AXI_RVALID : OUT STD_LOGIC; -- Read ready. This signal indicates that the master can -- accept the read data and response information. S_AXI_RREADY : IN STD_LOGIC ); END action_axi_slave; ARCHITECTURE action_axi_slave OF action_axi_slave IS -- AXI4LITE signals SIGNAL axi_awaddr : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0); SIGNAL axi_awready : STD_LOGIC; SIGNAL axi_wready : STD_LOGIC; SIGNAL axi_bresp : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL axi_bvalid : STD_LOGIC; SIGNAL axi_araddr : STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 DOWNTO 0); SIGNAL axi_arready : STD_LOGIC; SIGNAL axi_rdata : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); SIGNAL axi_rresp : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL axi_rvalid : STD_LOGIC; -- Example-specific design signals -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH -- ADDR_LSB is used for addressing 32/64 bit registers/memories -- ADDR_LSB = 2 for 32 bits (n downto 2) -- ADDR_LSB = 3 for 64 bits (n downto 3) CONSTANT ADDR_LSB : INTEGER := (C_S_AXI_DATA_WIDTH/32)+ 1; CONSTANT OPT_MEM_ADDR_BITS : INTEGER := 6; ------------------------------------------------ ---- Signals for user logic register space example -------------------------------------------------- ---- Number of Slave Registers 16 SIGNAL slv_reg0 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); SIGNAL slv_reg0_new : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); SIGNAL slv_reg1 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); SIGNAL slv_reg2 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); SIGNAL slv_reg3 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); SIGNAL slv_reg8 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); SIGNAL slv_reg12 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); SIGNAL slv_reg13 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); SIGNAL slv_reg14 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); SIGNAL slv_reg15 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); SIGNAL slv_reg16 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); SIGNAL slv_reg17 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); SIGNAL slv_reg18 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); SIGNAL slv_reg19 : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); SIGNAL slv_reg_rden : STD_LOGIC; SIGNAL slv_reg_wren : STD_LOGIC; SIGNAL reg_data_out : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 DOWNTO 0); SIGNAL byte_index : INTEGER; SIGNAL idle_q : STD_LOGIC; SIGNAL app_start_q : STD_LOGIC; SIGNAL app_done_q : STD_LOGIC; BEGIN -- I/O Connections assignments int_enable_o <= slv_reg1(0); S_AXI_AWREADY <= axi_awready; S_AXI_WREADY <= axi_wready; S_AXI_BRESP <= axi_bresp; S_AXI_BVALID <= axi_bvalid; S_AXI_ARREADY <= axi_arready; S_AXI_RDATA <= axi_rdata; S_AXI_RRESP <= axi_rresp; S_AXI_RVALID <= axi_rvalid; -- Implement axi_awready generation -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is -- de-asserted when reset is low. PROCESS (S_AXI_ACLK) BEGIN IF rising_edge(S_AXI_ACLK) THEN IF (axi_awready = '0' AND S_AXI_AWVALID = '1' AND S_AXI_WVALID = '1') THEN -- slave is ready to accept write address when -- there is a valid write address and write data -- on the write address and data bus. This design -- expects no outstanding transactions. axi_awready <= '1'; ELSE axi_awready <= '0'; END IF; IF S_AXI_ARESETN = '0' THEN axi_awready <= '0'; END IF; END IF; END PROCESS; -- Implement axi_awaddr latching -- This process is used to latch the address when both -- S_AXI_AWVALID and S_AXI_WVALID are valid. PROCESS (S_AXI_ACLK) BEGIN IF rising_edge(S_AXI_ACLK) THEN IF (axi_awready = '0' AND S_AXI_AWVALID = '1' AND S_AXI_WVALID = '1') THEN -- Write Address latching axi_awaddr <= S_AXI_AWADDR; END IF; IF S_AXI_ARESETN = '0' THEN axi_awaddr <= (OTHERS => '0'); END IF; END IF; END PROCESS; -- Implement axi_wready generation -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is -- de-asserted when reset is low. PROCESS (S_AXI_ACLK) BEGIN IF rising_edge(S_AXI_ACLK) THEN IF (axi_wready = '0' AND S_AXI_WVALID = '1' AND S_AXI_AWVALID = '1') THEN -- slave is ready to accept write data when -- there is a valid write address and write data -- on the write address and data bus. This design -- expects no outstanding transactions. axi_wready <= '1'; ELSE axi_wready <= '0'; END IF; IF S_AXI_ARESETN = '0' THEN axi_wready <= '0'; END IF; END IF; END PROCESS; -- Implement memory mapped register select and write logic generation -- The write data is accepted and written to memory mapped registers when -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to -- select byte enables of slave registers while writing. -- These registers are cleared when reset (active low) is applied. -- Slave register write enable is asserted when valid address and data are available -- and the slave is ready to accept the write address and write data. slv_reg_wren <= axi_wready AND S_AXI_WVALID AND axi_awready AND S_AXI_AWVALID ; PROCESS (S_AXI_ACLK) VARIABLE loc_addr : std_logic_vector(OPT_MEM_ADDR_BITS-1 DOWNTO 0); BEGIN IF rising_edge(S_AXI_ACLK) THEN loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS-1 DOWNTO ADDR_LSB); IF (slv_reg_wren = '1') THEN CASE loc_addr IS WHEN b"000000" => FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN -- Respective byte enables are asserted as per write strobes -- slave register 0 slv_reg0(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8); END IF; END LOOP; WHEN b"000001" => FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN -- Respective byte enables are asserted as per write strobes -- slave register 1 slv_reg1(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8); END IF; END LOOP; WHEN b"000010" => FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN -- Respective byte enables are asserted as per write strobes -- slave register 2 slv_reg2(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8); END IF; END LOOP; WHEN b"000011" => FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN -- Respective byte enables are asserted as per write strobes -- slave register 3 slv_reg3(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8); END IF; END LOOP; WHEN b"001000" => FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN -- Respective byte enables are asserted as per write strobes -- slave register 8 slv_reg8(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8); END IF; END LOOP; WHEN b"001100" => FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN -- Respective byte enables are asserted as per write strobes -- slave register 12 slv_reg12(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8); END IF; END LOOP; WHEN b"001101" => FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN -- Respective byte enables are asserted as per write strobes -- slave register 13 slv_reg13(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8); END IF; END LOOP; WHEN b"001110" => FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN -- Respective byte enables are asserted as per write strobes -- slave register 14 slv_reg14(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8); END IF; END LOOP; WHEN b"001111" => FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN -- Respective byte enables are asserted as per write strobes -- slave register 15 slv_reg15(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8); END IF; END LOOP; WHEN b"010000" => FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN -- Respective byte enables are asserted as per write strobes -- slave register 16 slv_reg16(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8); END IF; END LOOP; WHEN b"010001" => FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN -- Respective byte enables are asserted as per write strobes -- slave register 17 slv_reg17(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8); END IF; END LOOP; WHEN b"010010" => FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN -- Respective byte enables are asserted as per write strobes -- slave register 18 slv_reg18(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8); END IF; END LOOP; WHEN b"010011" => FOR byte_index IN 0 TO (C_S_AXI_DATA_WIDTH/8-1) LOOP IF ( S_AXI_WSTRB(byte_index) = '1' ) THEN -- Respective byte enables are asserted as per write strobes -- slave register 19 slv_reg19(byte_index*8+7 DOWNTO byte_index*8) <= S_AXI_WDATA(byte_index*8+7 DOWNTO byte_index*8); END IF; END LOOP; WHEN OTHERS => slv_reg0 <= slv_reg0; slv_reg1 <= slv_reg1; slv_reg2 <= slv_reg2; slv_reg3 <= slv_reg3; slv_reg8 <= slv_reg8; slv_reg12 <= slv_reg12; slv_reg13 <= slv_reg13; slv_reg14 <= slv_reg14; slv_reg15 <= slv_reg15; slv_reg16 <= slv_reg16; slv_reg17 <= slv_reg17; slv_reg18 <= slv_reg18; slv_reg19 <= slv_reg19; END CASE; END IF; IF app_start_q = '1' THEN slv_reg0(0) <= '0'; END IF; IF S_AXI_ARESETN = '0' THEN slv_reg0 <= (OTHERS => '0'); slv_reg1 <= (OTHERS => '0'); slv_reg2 <= (OTHERS => '0'); slv_reg3 <= (OTHERS => '0'); slv_reg8 <= (OTHERS => '0'); slv_reg12 <= (OTHERS => '0'); slv_reg13 <= (OTHERS => '0'); slv_reg14 <= (OTHERS => '0'); slv_reg15 <= (OTHERS => '0'); slv_reg16 <= (OTHERS => '0'); slv_reg17 <= (OTHERS => '0'); slv_reg18 <= (OTHERS => '0'); slv_reg19 <= (OTHERS => '0'); END IF; END IF; END PROCESS; -- Implement write response logic generation -- The write response and response valid signals are asserted by the slave -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. -- This marks the acceptance of address and indicates the status of -- write transaction. PROCESS (S_AXI_ACLK) BEGIN IF rising_edge(S_AXI_ACLK) THEN IF (axi_awready = '1' AND S_AXI_AWVALID = '1' AND axi_wready = '1' AND S_AXI_WVALID = '1' AND axi_bvalid = '0' ) THEN axi_bvalid <= '1'; axi_bresp <= "00"; ELSIF (S_AXI_BREADY = '1' AND axi_bvalid = '1') THEN --check if bready is asserted while bvalid is high) axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) END IF; IF S_AXI_ARESETN = '0' THEN axi_bvalid <= '0'; axi_bresp <= "00"; --need to work more on the responses END IF; END IF; END PROCESS; -- Implement axi_arready generation -- axi_arready is asserted for one S_AXI_ACLK clock cycle when -- S_AXI_ARVALID is asserted. axi_awready is -- de-asserted when reset (active low) is asserted. -- The read address is also latched when S_AXI_ARVALID is -- asserted. axi_araddr is reset to zero on reset assertion. PROCESS (S_AXI_ACLK) BEGIN IF rising_edge(S_AXI_ACLK) THEN IF (axi_arready = '0' AND S_AXI_ARVALID = '1') THEN -- indicates that the slave has acceped the valid read address axi_arready <= '1'; -- Read Address latching axi_araddr <= S_AXI_ARADDR; ELSE axi_arready <= '0'; END IF; IF S_AXI_ARESETN = '0' THEN axi_arready <= '0'; axi_araddr <= (OTHERS => '1'); END IF; END IF; END PROCESS; -- Implement axi_arvalid generation -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both -- S_AXI_ARVALID and axi_arready are asserted. The slave registers -- data are available on the axi_rdata bus at this instance. The -- assertion of axi_rvalid marks the validity of read data on the -- bus and axi_rresp indicates the status of read transaction.axi_rvalid -- is deasserted on reset (active low). axi_rresp and axi_rdata are -- cleared to zero on reset (active low). PROCESS (S_AXI_ACLK) BEGIN IF rising_edge(S_AXI_ACLK) THEN IF (axi_arready = '1' AND S_AXI_ARVALID = '1' AND axi_rvalid = '0') THEN -- Valid read data is available at the read data bus axi_rvalid <= '1'; axi_rresp <= "00"; -- 'OKAY' response ELSIF (axi_rvalid = '1' AND S_AXI_RREADY = '1') THEN -- Read data is accepted by the master axi_rvalid <= '0'; END IF; IF S_AXI_ARESETN = '0' THEN axi_rvalid <= '0'; axi_rresp <= "00"; END IF; END IF; END PROCESS; -- Implement memory mapped register select and read logic generation -- Slave register read enable is asserted when valid address is available -- and the slave is ready to accept the read address. slv_reg_rden <= axi_arready AND S_AXI_ARVALID AND (NOT axi_rvalid) ; PROCESS (slv_reg0_new, slv_reg1, slv_reg2, slv_reg3, reg_0x10_i, reg_0x14_i, slv_reg8, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, reg_0x48_i, slv_reg19, axi_araddr, reg_0x4c_completion_i, reg_0x4c_req_error_i, reg_0x4c_nvme_error_i, reg_0x50_i, reg_0x54_i) VARIABLE loc_addr : std_logic_vector(OPT_MEM_ADDR_BITS-1 DOWNTO 0); VARIABLE loc_idx : integer RANGE 0 TO 511; BEGIN -- Address decoding for reading registers loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS-1 DOWNTO ADDR_LSB); loc_idx := to_integer(unsigned(axi_araddr(5 DOWNTO 2))) * 32; CASE loc_addr IS WHEN b"000000" => reg_data_out <= slv_reg0_new; -- 0x00 WHEN b"000001" => reg_data_out <= slv_reg1; -- 0x04 WHEN b"000010" => reg_data_out <= slv_reg2; -- 0x08 WHEN b"000011" => reg_data_out <= slv_reg3; -- 0x0c WHEN b"000100" => reg_data_out <= reg_0x10_i; -- 0x10 WHEN b"000101" => reg_data_out <= reg_0x14_i; -- 0x14 WHEN b"001000" => reg_data_out <= slv_reg8; -- 0x20 WHEN b"001100" => reg_data_out <= slv_reg12; -- 0x30 WHEN b"001101" => reg_data_out <= slv_reg13; -- 0x34 WHEN b"001110" => reg_data_out <= slv_reg14; -- 0x38 WHEN b"001111" => reg_data_out <= slv_reg15; -- 0x3c WHEN b"010000" => reg_data_out <= slv_reg16; -- 0x40 WHEN b"010001" => reg_data_out <= slv_reg17; -- 0x44 WHEN b"010010" => reg_data_out <= reg_0x48_i; -- 0x48 : Tracking slots with NVMe read error (bits 31:16) / NVMe write error (bits 15:0) WHEN b"010011" => reg_data_out <= reg_0x4c_req_error_i & slv_reg19(15 DOWNTO 11) & reg_0x4c_nvme_error_i & slv_reg19(7 DOWNTO 5) & reg_0x4c_completion_i; -- 0x4c WHEN b"010100" => reg_data_out <= reg_0x50_i; -- 0x50 : Request tracking register -- for slot in {0,...,15}: -- bit slot+32 = '1' means: request from application for slot got initiated -- bit is reset when the applications request is completed -- bit slot = '1' means: request is an NVMe read request (NVMe writer request, otherwise) WHEN b"010101" => reg_data_out <= reg_0x54_i; -- 0x54 : NVMe request / response register -- for slot in {0,...,15}: -- bit slot+32 = '1' means: request to Nvme host controller for slot initiated -- bit is reset when the applications request is completed -- bit slot = '1' means: response from Nvme host controler for slot arrived -- bit is reset when the applications request is completed -- WHEN b"010111" => -- reg_data_out <= reg_0x5c_i; -- 0x5c : NVMe host controller debug register 0x4c (snd tracking info) -- -- for slot in {0,...,15}: -- -- bit slot+32 = '1' means: request to Nvme drive for slot initiated (=>WRITE_SQ) -- -- bit is reset when the drive signals receive of request -- -- bit slot = '1' means: request to Nvme drive for slot completed (=>WRITE_SQ_DOORBELL) -- -- bit is reset when the drive signals receive of request WHEN OTHERS => reg_data_out <= (OTHERS => '0'); END CASE; END PROCESS; reg_0x4c_rd_strobe_o <= '1' WHEN slv_reg_rden = '1' AND axi_araddr(7 DOWNTO 0) = x"4c" ELSE '0'; -- Output register or memory read data PROCESS( S_AXI_ACLK ) IS BEGIN IF (rising_edge (S_AXI_ACLK)) THEN IF (slv_reg_rden = '1') THEN -- When there is a valid read address (S_AXI_ARVALID) with -- acceptance of read address by the slave (axi_arready), -- output the read dada -- Read address mux axi_rdata <= reg_data_out; -- register read data END IF; IF ( S_AXI_ARESETN = '0' ) THEN axi_rdata <= (OTHERS => '0'); END IF; END IF; END PROCESS; app_start_o <= app_start_q; reg_0x20_o <= slv_reg8; reg_0x30_o <= slv_reg12; reg_0x34_o <= slv_reg13; reg_0x38_o <= slv_reg14; reg_0x3c_o <= slv_reg15; reg_0x40_o <= slv_reg16; reg_0x44_o <= slv_reg17; PROCESS( S_AXI_ACLK ) IS VARIABLE app_done_i_q : std_logic; VARIABLE loc_addr : std_logic_vector(OPT_MEM_ADDR_BITS-1 DOWNTO 0); BEGIN IF (rising_edge (S_AXI_ACLK)) THEN app_start_q <= app_start_q; idle_q <= app_idle_i; app_done_i_q := app_done_i; loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS-1 DOWNTO ADDR_LSB); -- clear app_done bit when register is read IF slv_reg_rden = '1' AND loc_addr = "00000" THEN app_done_q <= '0'; END IF; IF (app_done_i_q = '0' AND app_done_i = '1') THEN app_done_q <= '1'; END IF; IF slv_reg0(0) = '1' THEN app_start_q <= '1'; END IF; IF idle_q = '1' AND app_idle_i = '0' THEN app_start_q <= '0'; END IF; IF ( S_AXI_ARESETN = '0' ) THEN app_start_q <= '0'; app_done_q <= '0'; app_done_i_q := '0'; idle_q <= '0'; END IF; END IF; END PROCESS; slv_reg0_new <= slv_reg0 (31 DOWNTO 4) & app_ready_i & idle_q & app_done_q & app_start_q ; END action_axi_slave;

apache-2.0

1b1763b53626c7e8691494e7b1c1c240

VLSI-EDA/PoC-Examples

src/mem/sdram/memtest_s3esk_clockgen.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Martin Zabel -- -- Module: Clock Generator for Memory Test on Spartan-3E Starter Kit -- -- Description: -- ------------------------------------ -- DCM configuration for module 'memtest_s3esk'. -- -- The DCMs dcm_mem* have either unstable input clocks upon configuration and/or -- external feedback, and thus must be reset accordingly. So we do not use -- the STARTUP_WAIT feature at all. -- -- After startup the clocks are unstable. Thus, the logic -- clocked by clk_* must be hold in reset until rst_* is deasserted. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ ------------------------------------------------------------------------------- -- Naming Conventions: -- (Based on: Keating and Bricaud: "Reuse Methodology Manual") -- -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: all UPPERCASE -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- output of a register: "*_r" -- asynchronous signal: "*_a" -- pipelined or register delay signals: "*_p#" -- data before being registered into register with the same name: "*_nxt" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- tristate internal signal "*_z" ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.ALL; entity memtest_s3esk_clockgen is port ( clk_in : in std_logic; sd_ck_fb : in std_logic; user_rst : in std_logic; clk_sys : out std_logic; clk_mem : out std_logic; clk_mem_n : out std_logic; clk_mem90 : out std_logic; clk_mem90_n : out std_logic; clk_memfb90 : out std_logic; clk_memfb90_n : out std_logic; rst_sys : out std_logic; rst_mem : out std_logic; rst_mem90 : out std_logic; rst_mem180 : out std_logic; rst_mem270 : out std_logic; rst_memfb90 : out std_logic; rst_memfb270 : out std_logic; locked : out std_logic); end memtest_s3esk_clockgen; library unisim; use unisim.VComponents.all; architecture rtl of memtest_s3esk_clockgen is -- input buffer signal clk_in_bufo : std_logic; signal sd_ck_fb_bufo : std_logic; -- clock buffer inputs signal clk_sys_bufi : std_logic; signal clk_dv_bufi : std_logic; signal clk_mem_bufi : std_logic; signal clk_mem90_bufi : std_logic; signal clk_memfb90_bufi : std_logic; signal clk_memfb90_n_bufi : std_logic; -- global clocks (internal signals) signal clk_sys_i : std_logic; signal clk_mem_i : std_logic; signal clk_mem_n_i : std_logic; signal clk_mem90_i : std_logic; signal clk_mem90_n_i : std_logic; signal clk_memfb90_i : std_logic; signal clk_memfb90_n_i : std_logic; -- dcm reset signal dcm_mem_rst : std_logic; signal dcm_memfb_rst : std_logic; -- locked signals signal dcm_sys_locked : std_logic; signal dcm_mem_locked : std_logic; signal dcm_mem90_locked : std_logic; signal dcm_memfb_locked : std_logic; -- reset synchronizers for clk_sys, clk_mem* and clk_memfb* signal rst_sys_r : std_logic_vector(1 downto 0); signal rst_mem_r : std_logic_vector(1 downto 0); signal rst_mem90_r : std_logic_vector(1 downto 0); signal rst_mem180_r : std_logic_vector(1 downto 0); signal rst_mem270_r : std_logic_vector(1 downto 0); signal rst_memfb90_r : std_logic_vector(1 downto 0); signal rst_memfb270_r : std_logic_vector(1 downto 0); -- internal version of output signals signal locked_i : std_logic; -- do reset signal do_rst : std_logic; begin ----------------------------------------------------------------------------- -- 0. Input Clock buffer and system clock. ----------------------------------------------------------------------------- clk_in_buf : IBUFG port map ( I => clk_in, O => clk_in_bufo); ----------------------------------------------------------------------------- -- 1. System clock. ----------------------------------------------------------------------------- dcm_sys : DCM_SP generic map ( CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 20.0, -- period of input clock (50 Mhz) DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, CLK_FEEDBACK => "1X", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", CLKOUT_PHASE_SHIFT => "NONE", PHASE_SHIFT => 0, CLKDV_DIVIDE => 2.0, FACTORY_JF => X"C080") -- ? port map ( CLK0 => clk_sys_bufi, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLKDV => clk_dv_bufi, CLKFX => open, CLKFX180 => open, LOCKED => dcm_sys_locked, PSDONE => open, STATUS => open, CLKFB => clk_sys_i, CLKIN => clk_in_bufo, PSCLK => '0', PSEN => '0', PSINCDEC => '0', RST => '0'); clk_sys_buf : BUFG port map ( I => clk_sys_bufi, O => clk_sys_i); clk_sys <= clk_sys_i; -- clk_sys is stable as soon as GWE (Global Write Enable) is asserted. -- See documentation in file header. ----------------------------------------------------------------------------- -- 2. Generate memory clocks. -- -- The reset logic for this DCM has to wait until clk_sys gets stable. -- The reset must be asserted for three valid CLKIN cycles or longer. -- -- IMPORTANT NOTE: -- Yes dcm_mem and dcm_mem90 might be merged, if doubled input clock is -- generated by dcm_sys and then clk0 and clk90 DCM outputs are used. But -- these requires a DCM input clock of 100 MHz, which is out of specification -- for Spartan-3E stepping 0. ----------------------------------------------------------------------------- dcm_mem_rst_gen : SRLC16E generic map ( INIT => x"FFFF") -- hold reset for 16 clock cycles port map ( clk => clk_sys_i, ce => dcm_sys_locked, -- wait until clk_sys is stable d => '0', -- finished a0 => '1', a1 => '1', a2 => '1', a3 => '1', q => open, q15 => dcm_mem_rst); dcm_mem : DCM_SP generic map ( CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 20.0, -- 50 MHz DLL_FREQUENCY_MODE => "LOW", -- no specification found in manual DUTY_CYCLE_CORRECTION => FALSE, -- already 50 % CLK_FEEDBACK => "2X", DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", CLKOUT_PHASE_SHIFT => "NONE", PHASE_SHIFT => 0, FACTORY_JF => X"C080") -- ? port map ( CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => clk_mem_bufi, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => open, CLKFX180 => open, LOCKED => dcm_mem_locked, PSDONE => open, STATUS => open, CLKFB => clk_mem_i, CLKIN => clk_sys_i, PSCLK => '0', PSEN => '0', PSINCDEC => '0', RST => dcm_mem_rst); dcm_mem90 : DCM_SP generic map ( CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 20.0, -- 50 MHz DLL_FREQUENCY_MODE => "LOW", -- no specification found in manual DUTY_CYCLE_CORRECTION => FALSE, -- already 50 % CLK_FEEDBACK => "2X", DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => 32, -- 90° @ CLK2x FACTORY_JF => X"C080") -- ? port map ( CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => clk_mem90_bufi, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => open, CLKFX180 => open, LOCKED => dcm_mem90_locked, PSDONE => open, STATUS => open, CLKFB => clk_mem90_i, CLKIN => clk_sys_i, PSCLK => '0', PSEN => '0', PSINCDEC => '0', RST => dcm_mem_rst); clk_mem_buf : BUFG port map ( I => clk_mem_bufi, O => clk_mem_i); clk_mem_n_i <= not clk_mem_i; clk_mem90_buf : BUFG port map ( I => clk_mem90_bufi, O => clk_mem90_i); clk_mem90_n_i <= not clk_mem90_i; clk_mem <= clk_mem_i; clk_mem_n <= clk_mem_n_i; clk_mem90 <= clk_mem90_i; clk_mem90_n <= clk_mem90_n_i; ----------------------------------------------------------------------------- -- 3. Synchronized read clock for DDR-SDRAM controller. -- -- The reset logic for this DCM has to wait until clk_mem gets stable. -- The reset must be asserted for three valid CLKIN cycles or longer. -- Due to the external feedback, the number of cycles should be greater. ----------------------------------------------------------------------------- dcm_memfb_rst_gen : SRLC16E generic map ( INIT => x"FFFF") -- hold reset for 16 clock cycles port map ( clk => clk_mem_i, ce => dcm_mem_locked, -- wait until clk_mem is stable d => '0', -- finished a0 => '1', a1 => '1', a2 => '1', a3 => '1', q => open, q15 => dcm_memfb_rst); sd_ck_fb_buf : IBUFG port map ( I => sd_ck_fb, O => sd_ck_fb_bufo); dcm_memfb : DCM_SP generic map ( CLKIN_DIVIDE_BY_2 => TRUE, CLKIN_PERIOD => 10.0, -- period of input clock (100 Mhz) DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => FALSE, -- already 50 % CLK_FEEDBACK => "2X", DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- no deskew CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => 32+5, -- 90° +/- x @ CLK2X FACTORY_JF => X"C080") port map ( CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => clk_memfb90_bufi, CLK2X180 => clk_memfb90_n_bufi, CLK90 => open, CLKDV => open, CLKFX => open, CLKFX180 => open, LOCKED => dcm_memfb_locked, PSDONE => open, STATUS => open, CLKFB => clk_memfb90_i, CLKIN => sd_ck_fb_bufo, PSCLK => '0', PSEN => '0', PSINCDEC => '0', RST => dcm_memfb_rst); clk_memfb90_buf : BUFG port map ( I => clk_memfb90_bufi, O => clk_memfb90_i); clk_memfb90_n_buf : BUFG port map ( I => clk_memfb90_n_bufi, O => clk_memfb90_n_i); clk_memfb90 <= clk_memfb90_i; clk_memfb90_n <= clk_memfb90_n_i; ----------------------------------------------------------------------------- -- 4. Locked & Resets -- -- Coordinated Reset removal: -- - First, remove reset of clk_mem*, because it always waits for commands -- before it writes anything to the read FIFO. -- - Second, remove reset from clk_sys because it writes to the command FIFO -- as soon as possible. But at this time, the rst_rd from that FIFO must -- not be asserted, so that the write_addr is correctly transfered between -- the clock domains (gray-encoding is kept). ----------------------------------------------------------------------------- locked_i <= dcm_sys_locked and dcm_mem_locked and dcm_mem90_locked and dcm_memfb_locked; locked <= locked_i; do_rst <= (not locked_i) or user_rst; -- synchronize locked_i with clock domain clk_sys process (do_rst, clk_sys_i) begin -- process if do_rst = '1' then rst_sys_r <= (others => '1'); elsif rising_edge(clk_sys_i) then rst_sys_r(0) <= rst_mem_r(rst_mem_r'left); -- release as second rst_sys_r(rst_sys_r'left downto 1) <= rst_sys_r(rst_sys_r'left-1 downto 0); end if; end process; rst_sys <= rst_sys_r(rst_sys_r'left); -- synchronize locked_i with clock domain clk_mem process (do_rst, clk_mem_i) begin -- process if do_rst = '1' then rst_mem_r <= (others => '1'); elsif rising_edge(clk_mem_i) then rst_mem_r(0) <= '0'; rst_mem_r(rst_mem_r'left downto 1) <= rst_mem_r(rst_mem_r'left-1 downto 0); end if; end process; rst_mem <= rst_mem_r(rst_mem_r'left); -- synchronize locked_i with clock domain clk_mem90 process (do_rst, clk_mem90_i) begin -- process if do_rst = '1' then rst_mem90_r <= (others => '1'); elsif rising_edge(clk_mem90_i) then rst_mem90_r(0) <= '0'; rst_mem90_r(rst_mem90_r'left downto 1) <= rst_mem90_r(rst_mem90_r'left-1 downto 0); end if; end process; rst_mem90 <= rst_mem90_r(rst_mem90_r'left); -- synchronize locked_i with clock domain clk_mem_n process (do_rst, clk_mem_n_i) begin -- process if do_rst = '1' then rst_mem180_r <= (others => '1'); elsif falling_edge(clk_mem_n_i) then rst_mem180_r(0) <= '0'; rst_mem180_r(rst_mem180_r'left downto 1) <= rst_mem180_r(rst_mem180_r'left-1 downto 0); end if; end process; rst_mem180 <= rst_mem180_r(rst_mem180_r'left); -- synchronize locked_i with clock domain clk_mem90_n process (do_rst, clk_mem90_n_i) begin -- process if do_rst = '1' then rst_mem270_r <= (others => '1'); elsif falling_edge(clk_mem90_n_i) then rst_mem270_r(0) <= '0'; rst_mem270_r(rst_mem270_r'left downto 1) <= rst_mem270_r(rst_mem270_r'left-1 downto 0); end if; end process; rst_mem270 <= rst_mem270_r(rst_mem270_r'left); -- synchronize locked_i with clock domain clk_memfb90 process (do_rst, clk_memfb90_i) begin -- process if do_rst = '1' then rst_memfb90_r <= (others => '1'); elsif rising_edge(clk_memfb90_i) then rst_memfb90_r(0) <= '0'; rst_memfb90_r(rst_memfb90_r'left downto 1) <= rst_memfb90_r(rst_memfb90_r'left-1 downto 0); end if; end process; rst_memfb90 <= rst_memfb90_r(rst_memfb90_r'left); -- synchronize locked_i with clock domain clk_memfb90_n process (do_rst, clk_memfb90_n_i) begin -- process if do_rst = '1' then rst_memfb270_r <= (others => '1'); elsif rising_edge(clk_memfb90_n_i) then rst_memfb270_r(0) <= '0'; rst_memfb270_r(rst_memfb270_r'left downto 1) <= rst_memfb270_r(rst_memfb270_r'left-1 downto 0); end if; end process; rst_memfb270 <= rst_memfb270_r(rst_memfb270_r'left); end rtl;

apache-2.0

32322fe05d68ef4b9b1d2e973c98a93e

witchard/sock.sv

demo/adder.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity adder is generic ( width : positive := 1); port ( clk : in std_ulogic; reset : in std_ulogic; a : in std_ulogic_vector(width-1 downto 0); b : in std_ulogic_vector(width-1 downto 0); c : out std_ulogic_vector(width downto 0)); end adder; architecture rtl of adder is begin -- rtl -- purpose: Add the values -- type : sequential -- inputs : clk, reset, a, b -- outputs: c add: process (clk, reset) begin -- process add if reset = '1' then -- asynchronous reset (active high) c <= (others => '0'); elsif clk'event and clk = '1' then -- rising clock edge c <= std_ulogic_vector( unsigned('0' & a) + unsigned('0' & b) ); end if; end process add; end rtl;

mit

70f613b9fa1097a5cf1fed74e675993a

viniciussmello/SistemasDigitais

Trabalho 2/ConversorBCD/bcd_converter_teste.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY bcd_converter_teste IS END bcd_converter_teste; ARCHITECTURE behavior OF bcd_converter_teste IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT bcd_converter PORT( in_binary : IN std_logic_vector(31 downto 0); digit_0 : OUT std_logic_vector(3 downto 0); digit_1 : OUT std_logic_vector(3 downto 0); digit_2 : OUT std_logic_vector(3 downto 0); digit_3 : OUT std_logic_vector(3 downto 0); digit_4 : OUT std_logic_vector(3 downto 0); digit_5 : OUT std_logic_vector(3 downto 0); digit_6 : OUT std_logic_vector(3 downto 0); digit_7 : OUT std_logic_vector(3 downto 0); digit_8 : OUT std_logic_vector(3 downto 0); digit_9 : OUT std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs signal in_binary : std_logic_vector(31 downto 0) := (others => '0'); --Outputs signal digit_0 : std_logic_vector(3 downto 0); signal digit_1 : std_logic_vector(3 downto 0); signal digit_2 : std_logic_vector(3 downto 0); signal digit_3 : std_logic_vector(3 downto 0); signal digit_4 : std_logic_vector(3 downto 0); signal digit_5 : std_logic_vector(3 downto 0); signal digit_6 : std_logic_vector(3 downto 0); signal digit_7 : std_logic_vector(3 downto 0); signal digit_8 : std_logic_vector(3 downto 0); signal digit_9 : std_logic_vector(3 downto 0); constant period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: bcd_converter PORT MAP ( in_binary => in_binary, digit_0 => digit_0, digit_1 => digit_1, digit_2 => digit_2, digit_3 => digit_3, digit_4 => digit_4, digit_5 => digit_5, digit_6 => digit_6, digit_7 => digit_7, digit_8 => digit_8, digit_9 => digit_9 ); -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for period*10; in_binary(7 downto 0) <= "01100011"; -- insert stimulus here wait; end process; END;

gpl-3.0

8fea566d0f6d5c83eda3f2b49c7d545e

MiddleMan5/233

Experiments/RTL_Components/CPE233-master/StackPointer.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity StackPointer is port ( D_IN_BUS : in STD_LOGIC_VECTOR (7 downto 0); SEL : in STD_LOGIC_VECTOR (1 downto 0); LD : in STD_LOGIC; RST : in STD_LOGIC; CLK : in STD_LOGIC; D_OUT : out STD_LOGIC_VECTOR (7 downto 0); D_OUT_DEC : out STD_LOGIC_VECTOR (7 downto 0) ); end StackPointer; architecture Stack of StackPointer is signal SP : STD_LOGIC_VECTOR (7 downto 0) := x"00"; begin -- Load new value if needed LOAD : process (CLK, LD, SP, RST) begin if (rising_edge(CLK)) then if (LD = '1') then if (SEL = "00") then SP <= D_IN_BUS; elsif (SEL = "10") then SP <= SP - 1; elsif (SEL = "11") then SP <= SP + 1; end if; end if; end if; if (RST = '1') then SP <= (others => '0'); end if; end process LOAD; -- Output resulting stack pointers D_OUT <= SP; D_OUT_DEC <= SP - 1; end Stack;

mit

e89ab55c3b37d904c840cf71c2631bd9

blytkerchan/BrainF

BrainF.vhdl

-- BrainF* interpreter -- Version: 20141018 -- Author: Ronald Landheer-Cieslak -- Copyright (c) 2014 Vlinder Software -- License: LGPL-3.0 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity BrainF is generic( MAX_INSTRUCTION_COUNT : positive := 65536 ; MEMORY_SIZE : positive := 65536 ); port( resetN : in std_logic ; clock : in std_logic ; load_instructions : in std_logic ; instruction_octet : in std_logic_vector(7 downto 0) ; ack_instruction : out std_logic := '0' ; program_full : out std_logic := '0' ; read_memory : in std_logic ; memory_byte : out std_logic_vector(7 downto 0) := (others => '0') ; memory_byte_ready : out std_logic := '0' ; memory_byte_read_ack : in std_logic ; done : out std_logic := '0' ); end entity; architecture behavior of BrainF is type Instruction is (nop, halt, dot, plus, minus, advance, back_up, begin_loop, end_loop, zero); type Instructions is array(0 to (MAX_INSTRUCTION_COUNT - 1)) of Instruction; type Pipeline is array(0 to 1) of Instruction; subtype IPointer is integer range 0 to MAX_INSTRUCTION_COUNT; type InterpreterState is (execute_instruction, fetch_instruction); subtype NestCount is integer range 0 to MAX_INSTRUCTION_COUNT - 1; type Memory is array(0 to (MEMORY_SIZE - 1)) of std_logic_vector(7 downto 0); subtype Pointer is integer range 0 to (MEMORY_SIZE - 1); function toInstruction(i : std_logic_vector(7 downto 0)) return Instruction is begin case i is when x"23" => return halt; when x"2B" => return plus; when x"2D" => return minus; when x"2E" => return dot; when x"30" => return zero; when x"3E" => return advance; when x"3C" => return back_up; when x"5B" => return begin_loop; when x"5D" => return end_loop; when others => return nop; end case; end toInstruction; function increment(b : std_logic_vector(7 downto 0)) return std_logic_vector is begin if b = x"FF" then return x"00"; else return std_logic_vector(unsigned(b) + 1); end if; end increment; function decrement(b : std_logic_vector(7 downto 0)) return std_logic_vector is begin if b = x"00" then return x"FF"; else return std_logic_vector(unsigned(b) - 1); end if; end decrement; -- produced by p_interpret signal ptr : Pointer := 0; signal mem : Memory := (others => (others => '0')); signal stalled : std_logic := '0'; -- signals it's going forward in a loop. The p_fetch process will continue -- fetching until it finds the corresponding end-of-loop and puts that in pipe(0) at that time. -- produced by p_fetch signal pipe : Pipeline := (others => nop); signal iptr : IPointer := 0; signal nest_count : NestCount := 0; signal expect_stall : std_logic := '0'; signal should_back_up_on_stall : std_logic := '0'; -- set if we expect a stall on an end_loop instruction -- produced by p_loadInstructions signal program : Instructions := (others => halt); signal prev_load_instructions : std_logic := '0'; signal instruction_step : std_logic := '0'; signal iwptr : IPointer := 0; signal internal_program_full : std_logic := '0'; -- produced by p_readMemory signal prev_memory_byte_read_ack : std_logic := '0'; signal prev_read_memory : std_logic := '0'; begin p_interpret : process(resetN, clock, load_instructions, read_memory) begin if resetN = '0' or load_instructions = '1' then ptr <= 0; mem <= (others => (others => '0')); stalled <= '0'; elsif load_instructions = '0' and read_memory = '0' then if rising_edge(clock) then case pipe(0) is when dot => null; when plus => mem(ptr) <= increment(mem(ptr)); when minus => mem(ptr) <= decrement(mem(ptr)); when zero => mem(ptr) <= x"00"; when advance => if ptr = MEMORY_SIZE - 1 then ptr <= 0; else ptr <= ptr + 1; end if; when back_up => if ptr = 0 then ptr <= MEMORY_SIZE - 1; else ptr <= ptr - 1; end if; when begin_loop => if mem(ptr) = x"00" then stalled <= '1'; else stalled <= '0'; end if; when end_loop => if mem(ptr) /= x"00" then stalled <= '1'; else stalled <= '0'; end if; when halt => stalled <= '1'; when nop => null; end case; end if; end if; end process; p_fetch : process(resetN, clock, load_instructions, read_memory) variable done_skipping : boolean := False; begin if resetN = '0' or load_instructions = '1' then pipe <= (others => nop); iptr <= 0; nest_count <= 0; done <= '0'; expect_stall <= '0'; should_back_up_on_stall <= '0'; done_skipping := False; elsif load_instructions ='0' and read_memory = '0' then if rising_edge(clock) then -- if pipe(1) contains a begin_loop instruction, the p_interpret process may start stalling as soon as -- it sees it, which we will only know one (extra) clock cycle afterwards. In that case, we don't want -- to give it the next instruction unless we know it has had time to take a decision. Hence, if there's -- a begin_loop instruction in pipe(1) we set the expect_stall flag. If there's a begin_loop in pipe(0) -- and the expect_stall flag is set, we clear the flag and do nothing else. If the flag is not set, we -- check whether the stalled signal is raised and, if so, start searching for the end of the loop. If -- it's not set, we continue as normal. -- if pipe(1) contains an end_loop instruction, p_interpret may also stall but if it does, we need to -- start backing up. When pipe(1) contains an instruction, the instruction pointer (iptr) already -- points one past the instruction, because we're getting ready to read the next instruction into -- pipe(1). Hence, while we can anticipate our not stalling (and therefore load the next instruction -- into pipe(1) regardless) we have to make sure that if we do stall, we start by backing up the -- instruction pointer twice (or not count the end_loop instruction as nesting). if (pipe(1) = begin_loop or pipe(1) = end_loop or pipe(1) = halt) and stalled /= '1' and expect_stall = '0' then expect_stall <= '1'; done_skipping := False; if pipe(1) = end_loop then should_back_up_on_stall <= '1'; else should_back_up_on_stall <= '0'; end if; end if; if (pipe(0) = begin_loop or pipe(0) = end_loop) and expect_stall = '1' then expect_stall <= '0'; else if stalled = '0' then pipe(0) <= pipe(1); elsif stalled = '1' and nest_count = 0 and pipe(0) = begin_loop and pipe(1) = end_loop then -- we're done skipping over the loop! pipe(0) <= pipe(1); elsif stalled = '1' and nest_count = 0 and pipe(0) = end_loop and pipe(1) = begin_loop and should_back_up_on_stall = '0' then -- we are done backing up! pipe(0) <= pipe(1); iptr <= iptr + 2; done_skipping := True; elsif stalled = '1' and pipe(0) = halt then done <= '1'; elsif stalled = '1' and pipe(0) = pipe(1) and not done_skipping then nest_count <= nest_count + 1; elsif stalled = '1' and nest_count /= 0 and ((pipe(0) = begin_loop and pipe(1) = end_loop) or (pipe(0) = end_loop and pipe(1) = begin_loop)) then nest_count <= nest_count - 1; end if; if stalled = '0' or (stalled = '1' and pipe(0) = begin_loop) then if iptr = MAX_INSTRUCTION_COUNT then pipe(1) <= dot; done <= '1'; else if iptr + 2 < MAX_INSTRUCTION_COUNT and program(iptr) = begin_loop and program(iptr + 1) = minus and program(iptr + 2) = end_loop then pipe(1) <= zero; done <= '0'; iptr <= iptr + 3; else pipe(1) <= program(iptr); done <= '0'; iptr <= iptr + 1; end if; end if; elsif stalled = '1' and pipe(0) = halt then null; elsif not done_skipping then assert stalled = '1' and pipe(0) = end_loop report "Unexpected stall!" severity failure; if should_back_up_on_stall = '1' then assert iptr >= 3 report "Stalled with an invalid instruction pointer!" severity failure; pipe(1) <= program(iptr - 3); iptr <= iptr - 3; should_back_up_on_stall <= '0'; else -- this is where we start backing up pipe(1) <= program(iptr); done <= '0'; if iptr /= 0 then iptr <= iptr - 1; end if; end if; end if; end if; end if; end if; end process; p_loadInstructions : process(clock, resetN) begin if resetN = '0' then program <= (others => halt); prev_load_instructions <= '0'; instruction_step <= '0'; iwptr <= 0; internal_program_full <= '0'; else if rising_edge(clock) then if prev_load_instructions = '0' and load_instructions ='1' then program <= (others => halt); iwptr <= 0; instruction_step <= '0'; internal_program_full <= '0'; elsif prev_load_instructions = '1' and load_instructions ='1' then if instruction_step = '0' then if iwptr < MAX_INSTRUCTION_COUNT then program(iwptr) <= toInstruction(instruction_octet); iwptr <= iwptr + 1; else internal_program_full <= '1'; end if; end if; instruction_step <= not instruction_step and not internal_program_full; else iwptr <= 0; instruction_step <= '0'; end if; prev_load_instructions <= load_instructions; end if; end if; end process; ack_instruction <= instruction_step; program_full <= internal_program_full; p_readMemory : process(clock, resetN, read_memory) variable rptr : integer range 0 to MEMORY_SIZE := 0; begin if resetN = '0' or read_memory = '0' then rptr := 0; memory_byte <= (others => '0'); memory_byte_ready <= '0'; else if rising_edge(clock) then if read_memory = '1' then if prev_read_memory = '0' then memory_byte <= mem(0); memory_byte_ready <= '1'; rptr := 1; else if prev_memory_byte_read_ack = '0' and memory_byte_read_ack = '1' then if rptr /= MEMORY_SIZE then memory_byte <= mem(rptr); rptr := rptr + 1; else memory_byte_ready <= '0'; end if; end if; end if; prev_memory_byte_read_ack <= memory_byte_read_ack; end if; prev_read_memory <= read_memory; end if; end if; end process; end behavior;

lgpl-3.0

664ecde9999d34c5ee728d75cc5285c5

stefanct/aua

hw/id/src/id.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.aua_types.all; entity id is port ( clk : in std_logic; reset : in std_logic; -- pipeline register inputs opcode_in : in opcode_t; dest_in : in reg_t; pc_in : in pc_t; pcnxt_in : in pc_t; rega_in : in reg_t; regb_in : in reg_t; imm_in : in std_logic_vector(7 downto 0); -- asynchron register inputs async_rega : in reg_t; async_regb : in reg_t; -- results from wb to reg file regr : in reg_t; valr : in word_t; -- pipeline register outputs opcode_out : out opcode_t; dest_out : out reg_t; opa_out : out word_t; opb_out : out word_t; -- needed for EX forwarding rega_out : out reg_t; regb_out : out reg_t; opb_isfrom_regb : out boolean; -- branch decision pc_out : out pc_t; branch_out : out std_logic; -- interlock lock : in std_logic; id_locks : out std_logic ); end id; architecture sat1 of id is component reg is port ( clk : in std_logic; reset : in std_logic; async_rega : in reg_t; async_regb : in reg_t; rega : in reg_t; regb : in reg_t; async_regr : in reg_t; async_valr : in word_t; vala : out word_t; valb : out word_t ); end component; signal opcode_nxt : opcode_t; signal dest_nxt : reg_t; signal opa_nxt : word_t; signal opb_nxt : word_t; signal dest : reg_t; signal opa : word_t; signal opb : word_t; signal vala : word_t; signal valb : word_t; signal rega_nxt : reg_t; signal regb_nxt : reg_t; signal opb_isfrom_regb_nxt : boolean; signal jmpl_op : std_logic; -- set if instr is jmpl. used to propagate $ra to EX signal opa_to_nop : std_logic; -- set if we need opa to be all 0s for idle EX signal br_data_hz_nxt : std_logic; signal br_data_hz : std_logic; begin cmp_reg : reg port map(clk, reset, async_rega, async_regb, rega_in, regb_in, regr, valr, vala, valb); dest_out <= dest; rega_nxt <= rega_in; regb_nxt <= regb_in; id_locks <= br_data_hz_nxt; branch: process (opcode_in, pc_in, vala, valb, dest_in, dest, opb_nxt, rega_in, regb_in, br_data_hz) variable inv : std_logic; -- set if op is a "not branch" variable brinstr : std_logic; -- set if op changes PC begin inv := '0'; brinstr := '0'; br_data_hz_nxt <= '0'; opa_to_nop <= '0'; jmpl_op <= '0'; pc_out <= resize(unsigned(to_integer(pc_in) + signed(resize(unsigned(opb_nxt(ADDR_SIZE-1 downto 1)&'0'), ADDR_SIZE+1))), ADDR_SIZE); --~ pc_out <= unsigned(resize(unsigned(opb_nxt(ADDR_SIZE-1 downto 1)&'0'), ADDR_SIZE+1)); -- numeric_std warnings in modelsim opcode_nxt <= opcode_in; if opcode_in(5 downto 3)="010" then -- branch imm inv := opcode_in(2); brinstr := '1'; -- schedule nop opcode_nxt <= (others => '0'); opa_to_nop <= '1'; dest_nxt <= (others => '0'); elsif opcode_in(5 downto 1) ="00111" then inv := opcode_in(0); brinstr := '1'; pc_out <= pc_t(opb_nxt); -- absolute branch -- schedule nop opcode_nxt <= (others => '0'); opa_to_nop <= '1'; dest_nxt <= (others => '0'); elsif opcode_in = "001101" then inv := '0'; brinstr := '1'; -- jmpl, schedule mov r31, pc! opcode_nxt <= "111011"; dest_nxt <= "11111"; jmpl_op <= '1'; pc_out <= pc_t(valb); -- jump is absolute, and we need to take the reg value directly! elsif opcode_in(5 downto 2) = "1101" or opcode_in(5 downto 1) = "11100" then dest_nxt <= "11011"; else dest_nxt <= dest_in; end if; branch_out <= '0'; if brinstr='1' then if (dest=rega_in or dest=regb_in) and br_data_hz='0' then br_data_hz_nxt <= '1'; elsif (x"0000"=vala xor inv='1') then branch_out <= '1'; end if; end if; end process; -- inserts a nop (for branches etc.) insert_nop: process (vala, opa_to_nop) begin if opa_to_nop = '1' then opa_nxt <= (others => '0'); else opa_nxt <= vala; end if; end process; -- sign extend, expand and mux with regb extend_n_mux: process (opcode_in, imm_in, valb, jmpl_op, pcnxt_in) begin opb_isfrom_regb_nxt <= false; if opcode_in(5 downto 3)="000" then opb_nxt <= (15 downto 8 => '0') & imm_in(7 downto 0); elsif opcode_in(5 downto 2) ="1100" or opcode_in(5 downto 0) ="111010" then --expand whole imm (alu has to take care if thats "too much") opb_nxt <= (15 downto 7 => '0') & imm_in(6 downto 0); elsif opcode_in(5 downto 4)="01" then --sign extend imm(6 downto 0) if opcode_in(3) = '0' then -- imm branch; word addressing -> shift opb_nxt <= (15 downto 8 => imm_in(6)) & imm_in(6 downto 0) & '0'; else opb_nxt <= (15 downto 7 => imm_in(6)) & imm_in(6 downto 0); end if; elsif jmpl_op='1' then opb_nxt <= word_t(pcnxt_in); -- EX needs the return address --~ opb_nxt <= valb; else opb_isfrom_regb_nxt <= true; opb_nxt <= valb; end if; end process; sync: process (clk, reset) begin if reset = '1' then opcode_out <= (others => '0'); --~ dest_out <= (others => '0'); dest <= (others => '0'); opa_out <= (others => '0'); opb_out <= (others => '0'); rega_out <= (others => '0'); regb_out <= (others => '0'); br_data_hz <= '0'; opb_isfrom_regb <= false; elsif rising_edge(clk) then if lock/='1' then opcode_out <= opcode_nxt; --~ dest_out <= dest_nxt; dest <= dest_nxt; opa_out <= opa_nxt; opb_out <= opb_nxt; --~ else --~ opcode <= opcode; --~ dest <= dest; --~ opa <= opa; --~ opb <= opb; rega_out <= rega_nxt; regb_out <= regb_nxt; opb_isfrom_regb <= opb_isfrom_regb_nxt; br_data_hz <= br_data_hz_nxt; end if; end if; end process; end sat1;

gpl-3.0

ce03a76fa15eef65de4de16dfa4a71cb

MiddleMan5/233

Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlslice_0_0/sim/RAT_xlslice_0_0.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:xlslice:1.0 -- IP Revision: 0 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY work; USE work.xlslice; ENTITY RAT_xlslice_0_0 IS PORT ( Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); Dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END RAT_xlslice_0_0; ARCHITECTURE RAT_xlslice_0_0_arch OF RAT_xlslice_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_xlslice_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT xlslice IS GENERIC ( DIN_WIDTH : INTEGER; DIN_FROM : INTEGER; DIN_TO : INTEGER ); PORT ( Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); Dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT xlslice; BEGIN U0 : xlslice GENERIC MAP ( DIN_WIDTH => 18, DIN_FROM => 12, DIN_TO => 3 ) PORT MAP ( Din => Din, Dout => Dout ); END RAT_xlslice_0_0_arch;

mit

2b2afb8f964b5d7d78727ee9ca8d339f

David-Estevez/spaceinvaders

src/timer_tb.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY timer_tb IS END timer_tb; ARCHITECTURE behavior OF timer_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT timer generic (t: time); PORT( clk : IN std_logic; reset : IN std_logic; en : IN std_logic; q : OUT std_logic ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal reset : std_logic := '0'; signal en : std_logic := '0'; --Outputs signal q : std_logic; -- Clock period definitions constant clk_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: timer generic map (200 ns) PORT MAP ( clk => clk, reset => reset, en => en, q => q ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. reset <= '1'; wait for 100 ns; reset <= '0'; en <= '1'; wait; end process; END;

gpl-3.0

b79c5da4c9c8f53739b501d39019b609

David-Estevez/spaceinvaders

src/vga_tb.vhd

---------------------------------------------------------------------------------- -- -- Lab session #1: vga controller testbench -- ---------------------------------------------------------------------------------- -- Testing of the vga controller entity -- -- Author: David Estévez Fernández -- David Estévez Fernández ---------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY std; USE std.textio.ALL; ENTITY vga_tb IS END vga_tb; ARCHITECTURE behavior OF vga_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT vga PORT( clk : IN std_logic; reset : IN std_logic; RGB : IN std_logic_vector(2 downto 0); HSync : OUT std_logic; VSync : OUT std_logic; R : OUT std_logic; G : OUT std_logic; B : OUT std_logic; X : OUT std_logic_vector(9 downto 0); Y : OUT std_logic_vector(9 downto 0) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal reset : std_logic := '0'; signal RGB : std_logic_vector(2 downto 0) := (others => '0'); --Outputs signal HSync : std_logic; signal VSync : std_logic; signal R : std_logic; signal G : std_logic; signal B : std_logic; signal X : std_logic_vector(9 downto 0); signal Y : std_logic_vector(9 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: vga PORT MAP ( clk => clk, reset => reset, RGB => RGB, HSync => HSync, VSync => VSync, R => R, G => G, B => B, X => X, Y => Y ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process variable i: integer := 0; FILE output_file: TEXT is out "output.dat"; variable write_line: LINE; variable caca: std_logic; variable previousX, previousY: integer := -1; begin -- hold reset state for 100 ns. if i = 0 then wait for 40 ns; reset <= '1'; end if; -- record image: if reset = '1' then if VSync = '1' then if to_integer( unsigned(X) ) /= previousX and to_integer( unsigned(Y) /= previousY then write (write_line, 0); previousX := to_integer( unsigned(X) ); previousY := to_integer( unsigned(Y) ); end if; if HSync = '0' then writeline (output_file, write_line); end if; else wait; end if; end if; wait for clk_period; end process; END;

gpl-3.0

286b4b7820ef1650fa3e1c2f62d19137

VLSI-EDA/PoC-Examples

src/mem/ddr3/memtest_KC705.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================= -- Authors: Martin Zabel -- -- Module: Memory tester for KC705 board using Xilinx MIG with one -- 512-bit port. -- -- Description: -- ------------------------------------ -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; library poc; use poc.utils.all; entity memtest_KC705 is port ( KC705_SystemClock_200MHz_p : in std_logic; KC705_SystemClock_200MHz_n : in std_logic; KC705_GPIO_LED : out std_logic_vector(7 downto 0); ddr3_dq : inout std_logic_vector(64-1 downto 0); ddr3_dqs_p : inout std_logic_vector(8-1 downto 0); ddr3_dqs_n : inout std_logic_vector(8-1 downto 0); ddr3_addr : out std_logic_vector(14-1 downto 0); ddr3_ba : out std_logic_vector(3-1 downto 0); ddr3_ras_n : out std_logic; ddr3_cas_n : out std_logic; ddr3_we_n : out std_logic; ddr3_reset_n : out std_logic; ddr3_ck_p : out std_logic_vector(1-1 downto 0); ddr3_ck_n : out std_logic_vector(1-1 downto 0); ddr3_cke : out std_logic_vector(1-1 downto 0); ddr3_cs_n : out std_logic_vector(1*1-1 downto 0); ddr3_dm : out std_logic_vector(8-1 downto 0); ddr3_odt : out std_logic_vector(1-1 downto 0)); end entity memtest_KC705; architecture rtl of memtest_KC705 is signal sysclk_unbuf : std_logic; signal refclk : std_logic; signal memtest_status : std_logic_vector(2 downto 0); -- Inputs / Outputs of MIG core signal sys_rst : std_logic; signal app_addr : std_logic_vector(28-1 downto 0); signal app_cmd : std_logic_vector(2 downto 0); signal app_en : std_logic; signal app_wdf_data : std_logic_vector((4*2*64)-1 downto 0); signal app_wdf_end : std_logic; signal app_wdf_mask : std_logic_vector((4*2*64)/8-1 downto 0); signal app_wdf_wren : std_logic; signal app_rd_data : std_logic_vector((4*2*64)-1 downto 0); signal app_rd_data_end : std_logic; signal app_rd_data_valid : std_logic; signal app_rdy : std_logic; signal app_wdf_rdy : std_logic; signal ui_clk : std_logic; signal ui_clk_sync_rst : std_logic; signal init_calib_complete : std_logic; begin -- architecture rtl ----------------------------------------------------------------------------- -- Clock Buffer ----------------------------------------------------------------------------- -- This system clock is used two-fold: -- -- 1) It is used as the reference / system clock for the memory controllers -- (MIG). There it feeds only PLLs, so that, dedicated routing can be -- used and no BUFG is required. -- -- 2) It is also used for the IDELAYCTRL and temperature monitor logic. -- This requires a BUFG, but could also be driven by another 200 MHz -- clock source. If this other clock is not free-runnning, then -- IDELAYCTRL and the temperature monitor must be hold in reset until -- this other clock is stable. sysclk_ibuf : ibufds port map ( I => KC705_SystemClock_200MHz_p, IB => KC705_SystemClock_200MHz_n, O => sysclk_unbuf); -- sufficient for memory controllers only. refclk_bufg : bufg port map ( I => sysclk_unbuf, O => refclk); -- buffered 200 MHz reference clock ----------------------------------------------------------------------------- -- MemoryTester ----------------------------------------------------------------------------- MemoryTester : block -- The smallest addressable unit of the "app" interface has DQ_BITS bits. -- The smallest addressable unit of the "mem" interface has D_BITS bits. -- The burst length is then D_BITS / DQ_BITS. constant D_BITS : positive := 512; constant DQ_BITS : positive := 64; constant BL_BITS : natural := log2ceil(D_BITS / DQ_BITS); constant MEM_A_BITS : natural := ite(SIMULATION, 17-3, -- 128 KByte / 8 = 16 KByte per chip (on SoDIMM) 30-3) -- 1 GB / 8 = 128 MB per chip (on SoDIMM) -BL_BITS; signal mem_rdy : std_logic; signal mem_rstb : std_logic; signal mem_req : std_logic; signal mem_write : std_logic; signal mem_addr : unsigned(MEM_A_BITS-1 downto 0); signal mem_wdata : std_logic_vector(D_BITS-1 downto 0); signal mem_rdata : std_logic_vector(D_BITS-1 downto 0); begin -- block MemoryTester fsm : entity work.memtest_fsm generic map ( A_BITS => MEM_A_BITS, D_BITS => 128) -- check only 128 bits port map ( clk => ui_clk, rst => ui_clk_sync_rst, mem_rdy => mem_rdy, mem_rstb => mem_rstb, mem_rdata => mem_rdata(127 downto 0), -- check only lower 128 mem_req => mem_req, mem_write => mem_write, mem_addr => mem_addr, mem_wdata => mem_wdata(127 downto 0), status => memtest_status(2 downto 0)); mem_wdata(D_BITS-1 downto 128) <= (others => '0'); -- TODO adapter : entity poc.ddr3_mem2mig_adapter_Series7 generic map ( D_BITS => D_BITS, DQ_BITS => DQ_BITS, MEM_A_BITS => MEM_A_BITS, APP_A_BITS => app_addr'length) port map ( mem_req => mem_req, mem_write => mem_write, mem_addr => mem_addr, mem_wdata => mem_wdata, mem_rdy => mem_rdy, mem_rstb => mem_rstb, mem_rdata => mem_rdata, init_calib_complete => init_calib_complete, app_rd_data => app_rd_data, app_rd_data_end => app_rd_data_end, app_rd_data_valid => app_rd_data_valid, app_rdy => app_rdy, app_wdf_rdy => app_wdf_rdy, app_addr => app_addr, app_cmd => app_cmd, app_en => app_en, app_wdf_data => app_wdf_data, app_wdf_end => app_wdf_end, app_wdf_mask => app_wdf_mask, app_wdf_wren => app_wdf_wren); end block MemoryTester; ----------------------------------------------------------------------------- -- Memory Controller Instantiation ----------------------------------------------------------------------------- -- Apply an initial reset pulse. Required for IDELAYCTRL. sys_rst_pulse : FD generic map ( INIT => '1') port map ( D => '0', C => refclk, Q => sys_rst); mig : entity poc.mig_KC705_MT8JTF12864HZ_1G6 port map ( ddr3_dq => ddr3_dq, ddr3_dqs_p => ddr3_dqs_p, ddr3_dqs_n => ddr3_dqs_n, ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_ras_n => ddr3_ras_n, ddr3_cas_n => ddr3_cas_n, ddr3_we_n => ddr3_we_n, ddr3_reset_n => ddr3_reset_n, ddr3_ck_p => ddr3_ck_p, ddr3_ck_n => ddr3_ck_n, ddr3_cke => ddr3_cke, ddr3_cs_n => ddr3_cs_n, ddr3_dm => ddr3_dm, ddr3_odt => ddr3_odt, sys_clk_i => sysclk_unbuf, clk_ref_i => refclk, app_addr => app_addr, app_cmd => app_cmd, app_en => app_en, app_wdf_data => app_wdf_data, app_wdf_end => app_wdf_end, app_wdf_mask => app_wdf_mask, app_wdf_wren => app_wdf_wren, app_rd_data => app_rd_data, app_rd_data_end => app_rd_data_end, app_rd_data_valid => app_rd_data_valid, app_rdy => app_rdy, app_wdf_rdy => app_wdf_rdy, app_sr_req => '0', -- reserved app_sr_active => open, app_ref_req => '0', -- unused app_ref_ack => open, app_zq_req => '0', -- unused app_zq_ack => open, ui_clk => ui_clk, ui_clk_sync_rst => ui_clk_sync_rst, init_calib_complete => init_calib_complete, device_temp_i => (others => '0'), -- doesn't care if TEMP_MON_CONTROL is set -- to "INTERNAL" during netlist generation sys_rst => sys_rst); -- active high ----------------------------------------------------------------------------- -- Status Output ----------------------------------------------------------------------------- KC705_GPIO_LED(7) <= ui_clk_sync_rst; KC705_GPIO_LED(6) <= '0'; KC705_GPIO_LED(5) <= '0'; KC705_GPIO_LED(4) <= '0'; KC705_GPIO_LED(3) <= init_calib_complete; KC705_GPIO_LED(2 downto 0) <= memtest_status; end architecture rtl;

apache-2.0

0fef19dcbb4615a3dc0ebd674503acb4

MiddleMan5/233

Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_ControlUnit_0_0/sim/RAT_ControlUnit_0_0.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:module_ref:ControlUnit:1.0 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY RAT_ControlUnit_0_0 IS PORT ( CLK : IN STD_LOGIC; C : IN STD_LOGIC; Z : IN STD_LOGIC; INT : IN STD_LOGIC; RST : IN STD_LOGIC; OPCODE_HI_5 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); OPCODE_LO_2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); PC_LD : OUT STD_LOGIC; PC_INC : OUT STD_LOGIC; PC_RESET : OUT STD_LOGIC; PC_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); SP_LD : OUT STD_LOGIC; SP_RESET : OUT STD_LOGIC; SP_INCR : OUT STD_LOGIC; SP_DECR : OUT STD_LOGIC; RF_WR : OUT STD_LOGIC; RF_WR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); ALU_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); ALU_OPY_SEL : OUT STD_LOGIC; SCR_WR : OUT STD_LOGIC; SCR_ADDR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); SCR_DATA_SEL : OUT STD_LOGIC; C_FLAG_SEL : OUT STD_LOGIC; C_FLAG_LD : OUT STD_LOGIC; C_FLAG_SET : OUT STD_LOGIC; C_FLAG_CLR : OUT STD_LOGIC; SHAD_C_LD : OUT STD_LOGIC; Z_FLAG_SEL : OUT STD_LOGIC; Z_FLAG_LD : OUT STD_LOGIC; Z_FLAG_SET : OUT STD_LOGIC; Z_FLAG_CLR : OUT STD_LOGIC; SHAD_Z_LD : OUT STD_LOGIC; I_FLAG_SET : OUT STD_LOGIC; I_FLAG_CLR : OUT STD_LOGIC; IO_OE : OUT STD_LOGIC ); END RAT_ControlUnit_0_0; ARCHITECTURE RAT_ControlUnit_0_0_arch OF RAT_ControlUnit_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_ControlUnit_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT ControlUnit IS PORT ( CLK : IN STD_LOGIC; C : IN STD_LOGIC; Z : IN STD_LOGIC; INT : IN STD_LOGIC; RST : IN STD_LOGIC; OPCODE_HI_5 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); OPCODE_LO_2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); PC_LD : OUT STD_LOGIC; PC_INC : OUT STD_LOGIC; PC_RESET : OUT STD_LOGIC; PC_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); SP_LD : OUT STD_LOGIC; SP_RESET : OUT STD_LOGIC; SP_INCR : OUT STD_LOGIC; SP_DECR : OUT STD_LOGIC; RF_WR : OUT STD_LOGIC; RF_WR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); ALU_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); ALU_OPY_SEL : OUT STD_LOGIC; SCR_WR : OUT STD_LOGIC; SCR_ADDR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); SCR_DATA_SEL : OUT STD_LOGIC; C_FLAG_SEL : OUT STD_LOGIC; C_FLAG_LD : OUT STD_LOGIC; C_FLAG_SET : OUT STD_LOGIC; C_FLAG_CLR : OUT STD_LOGIC; SHAD_C_LD : OUT STD_LOGIC; Z_FLAG_SEL : OUT STD_LOGIC; Z_FLAG_LD : OUT STD_LOGIC; Z_FLAG_SET : OUT STD_LOGIC; Z_FLAG_CLR : OUT STD_LOGIC; SHAD_Z_LD : OUT STD_LOGIC; I_FLAG_SET : OUT STD_LOGIC; I_FLAG_CLR : OUT STD_LOGIC; IO_OE : OUT STD_LOGIC ); END COMPONENT ControlUnit; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF RST: SIGNAL IS "xilinx.com:signal:reset:1.0 RST RST"; ATTRIBUTE X_INTERFACE_INFO OF PC_RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 PC_RESET RST"; ATTRIBUTE X_INTERFACE_INFO OF SP_RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 SP_RESET RST"; BEGIN U0 : ControlUnit PORT MAP ( CLK => CLK, C => C, Z => Z, INT => INT, RST => RST, OPCODE_HI_5 => OPCODE_HI_5, OPCODE_LO_2 => OPCODE_LO_2, PC_LD => PC_LD, PC_INC => PC_INC, PC_RESET => PC_RESET, PC_MUX_SEL => PC_MUX_SEL, SP_LD => SP_LD, SP_RESET => SP_RESET, SP_INCR => SP_INCR, SP_DECR => SP_DECR, RF_WR => RF_WR, RF_WR_SEL => RF_WR_SEL, ALU_SEL => ALU_SEL, ALU_OPY_SEL => ALU_OPY_SEL, SCR_WR => SCR_WR, SCR_ADDR_SEL => SCR_ADDR_SEL, SCR_DATA_SEL => SCR_DATA_SEL, C_FLAG_SEL => C_FLAG_SEL, C_FLAG_LD => C_FLAG_LD, C_FLAG_SET => C_FLAG_SET, C_FLAG_CLR => C_FLAG_CLR, SHAD_C_LD => SHAD_C_LD, Z_FLAG_SEL => Z_FLAG_SEL, Z_FLAG_LD => Z_FLAG_LD, Z_FLAG_SET => Z_FLAG_SET, Z_FLAG_CLR => Z_FLAG_CLR, SHAD_Z_LD => SHAD_Z_LD, I_FLAG_SET => I_FLAG_SET, I_FLAG_CLR => I_FLAG_CLR, IO_OE => IO_OE ); END RAT_ControlUnit_0_0_arch;

mit

532eff5a7a1453cb10cee23020513955

open-power/snap

hardware/hdl/core/action_types.vhd

---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- -- Copyright 2016,2017 International Business Machines -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions AND -- limitations under the License. -- ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_misc.all; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.all; USE work.psl_accel_types.ALL; PACKAGE action_types IS CONSTANT C_M_AXI_CARD_MEM0_ID_WIDTH : integer := C_DDR_AXI_ID_WIDTH; CONSTANT C_M_AXI_CARD_MEM0_ADDR_WIDTH : integer := C_DDR_AXI_ADDR_WIDTH; CONSTANT C_M_AXI_CARD_MEM0_DATA_WIDTH : integer := C_DDR_AXI_DATA_WIDTH; CONSTANT C_M_AXI_CARD_MEM0_AWUSER_WIDTH : integer := C_DDR_AXI_AWUSER_WIDTH; CONSTANT C_M_AXI_CARD_MEM0_ARUSER_WIDTH : integer := C_DDR_AXI_ARUSER_WIDTH; CONSTANT C_M_AXI_CARD_MEM0_WUSER_WIDTH : integer := C_DDR_AXI_WUSER_WIDTH; CONSTANT C_M_AXI_CARD_MEM0_RUSER_WIDTH : integer := C_DDR_AXI_RUSER_WIDTH; CONSTANT C_M_AXI_CARD_MEM0_BUSER_WIDTH : integer := C_DDR_AXI_BUSER_WIDTH; -- Parameters for HBM ports CONSTANT C_M_AXI_CARD_HBM_ID_WIDTH : integer := C_AXI_CARD_HBM_ID_WIDTH; CONSTANT C_M_AXI_CARD_HBM_ADDR_WIDTH : integer := C_AXI_CARD_HBM_ADDR_WIDTH; CONSTANT C_M_AXI_CARD_HBM_SIM_ADDR_WIDTH : integer := C_AXI_CARD_HBM_SIM_ADDR_WIDTH; CONSTANT C_M_AXI_CARD_HBM_DATA_WIDTH : integer := C_AXI_CARD_HBM_DATA_WIDTH; CONSTANT C_M_AXI_CARD_HBM_AWUSER_WIDTH : integer := C_AXI_CARD_HBM_AWUSER_WIDTH; CONSTANT C_M_AXI_CARD_HBM_ARUSER_WIDTH : integer := C_AXI_CARD_HBM_ARUSER_WIDTH; CONSTANT C_M_AXI_CARD_HBM_WUSER_WIDTH : integer := C_AXI_CARD_HBM_WUSER_WIDTH; CONSTANT C_M_AXI_CARD_HBM_RUSER_WIDTH : integer := C_AXI_CARD_HBM_RUSER_WIDTH; CONSTANT C_M_AXI_CARD_HBM_BUSER_WIDTH : integer := C_AXI_CARD_HBM_BUSER_WIDTH; -- Parameters for Axi Slave Bus Interface AXI_CTRL_REG CONSTANT C_S_AXI_CTRL_REG_DATA_WIDTH : integer := C_REG_DATA_WIDTH; CONSTANT C_S_AXI_CTRL_REG_ADDR_WIDTH : integer := C_REG_ADDR_WIDTH; -- Parameters for Axi Master Bus Interface AXI_HOST_MEM : to Host memory CONSTANT C_M_AXI_HOST_MEM_ID_WIDTH : integer := C_HOST_AXI_ID_WIDTH; CONSTANT C_M_AXI_HOST_MEM_ADDR_WIDTH : integer := C_HOST_AXI_ADDR_WIDTH; CONSTANT C_M_AXI_HOST_MEM_DATA_WIDTH : integer := C_HOST_AXI_DATA_WIDTH; CONSTANT C_M_AXI_HOST_MEM_AWUSER_WIDTH : integer := CONTEXT_BITS; CONSTANT C_M_AXI_HOST_MEM_ARUSER_WIDTH : integer := CONTEXT_BITS; CONSTANT C_M_AXI_HOST_MEM_WUSER_WIDTH : integer := C_HOST_AXI_WUSER_WIDTH; CONSTANT C_M_AXI_HOST_MEM_RUSER_WIDTH : integer := C_HOST_AXI_RUSER_WIDTH; CONSTANT C_M_AXI_HOST_MEM_BUSER_WIDTH : integer := C_HOST_AXI_BUSER_WIDTH; -- Parameters for Axi Master Bus Interface AXI_NVME : to NVMe controller CONSTANT C_M_AXI_NVME_ID_WIDTH : integer := C_NVME_AXI_ID_WIDTH; CONSTANT C_M_AXI_NVME_ADDR_WIDTH : integer := C_NVME_AXI_ADDR_WIDTH; CONSTANT C_M_AXI_NVME_DATA_WIDTH : integer := C_NVME_AXI_DATA_WIDTH; CONSTANT C_M_AXI_NVME_AWUSER_WIDTH : integer := C_NVME_AXI_AWUSER_WIDTH; CONSTANT C_M_AXI_NVME_ARUSER_WIDTH : integer := C_NVME_AXI_ARUSER_WIDTH; CONSTANT C_M_AXI_NVME_WUSER_WIDTH : integer := C_NVME_AXI_WUSER_WIDTH; CONSTANT C_M_AXI_NVME_RUSER_WIDTH : integer := C_NVME_AXI_RUSER_WIDTH; CONSTANT C_M_AXI_NVME_BUSER_WIDTH : integer := C_NVME_AXI_BUSER_WIDTH; END action_types; PACKAGE BODY action_types IS END action_types;

apache-2.0

e7d218eac60f38bf7dd00d0b410e00b8

MiddleMan5/233

Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlconcat_0_0/sim/RAT_xlconcat_0_0.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:xlconcat:2.1 -- IP Revision: 2 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY work; USE work.xlconcat; ENTITY RAT_xlconcat_0_0 IS PORT ( In0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); In1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END RAT_xlconcat_0_0; ARCHITECTURE RAT_xlconcat_0_0_arch OF RAT_xlconcat_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_xlconcat_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT xlconcat IS GENERIC ( IN0_WIDTH : INTEGER; IN1_WIDTH : INTEGER; IN2_WIDTH : INTEGER; IN3_WIDTH : INTEGER; IN4_WIDTH : INTEGER; IN5_WIDTH : INTEGER; IN6_WIDTH : INTEGER; IN7_WIDTH : INTEGER; IN8_WIDTH : INTEGER; IN9_WIDTH : INTEGER; IN10_WIDTH : INTEGER; IN11_WIDTH : INTEGER; IN12_WIDTH : INTEGER; IN13_WIDTH : INTEGER; IN14_WIDTH : INTEGER; IN15_WIDTH : INTEGER; IN16_WIDTH : INTEGER; IN17_WIDTH : INTEGER; IN18_WIDTH : INTEGER; IN19_WIDTH : INTEGER; IN20_WIDTH : INTEGER; IN21_WIDTH : INTEGER; IN22_WIDTH : INTEGER; IN23_WIDTH : INTEGER; IN24_WIDTH : INTEGER; IN25_WIDTH : INTEGER; IN26_WIDTH : INTEGER; IN27_WIDTH : INTEGER; IN28_WIDTH : INTEGER; IN29_WIDTH : INTEGER; IN30_WIDTH : INTEGER; IN31_WIDTH : INTEGER; dout_width : INTEGER; NUM_PORTS : INTEGER ); PORT ( In0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); In1 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT xlconcat; BEGIN U0 : xlconcat GENERIC MAP ( IN0_WIDTH => 8, IN1_WIDTH => 2, IN2_WIDTH => 1, IN3_WIDTH => 1, IN4_WIDTH => 1, IN5_WIDTH => 1, IN6_WIDTH => 1, IN7_WIDTH => 1, IN8_WIDTH => 1, IN9_WIDTH => 1, IN10_WIDTH => 1, IN11_WIDTH => 1, IN12_WIDTH => 1, IN13_WIDTH => 1, IN14_WIDTH => 1, IN15_WIDTH => 1, IN16_WIDTH => 1, IN17_WIDTH => 1, IN18_WIDTH => 1, IN19_WIDTH => 1, IN20_WIDTH => 1, IN21_WIDTH => 1, IN22_WIDTH => 1, IN23_WIDTH => 1, IN24_WIDTH => 1, IN25_WIDTH => 1, IN26_WIDTH => 1, IN27_WIDTH => 1, IN28_WIDTH => 1, IN29_WIDTH => 1, IN30_WIDTH => 1, IN31_WIDTH => 1, dout_width => 10, NUM_PORTS => 2 ) PORT MAP ( In0 => In0, In1 => In1, In2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), In31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), dout => dout ); END RAT_xlconcat_0_0_arch;

mit

23f6b7fdcd7023fdf2f9befb6214e994

MiddleMan5/233

Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_util_vector_logic_0_0/synth/RAT_util_vector_logic_0_0.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:util_vector_logic:2.0 -- IP Revision: 2 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY util_vector_logic_v2_0; USE util_vector_logic_v2_0.util_vector_logic; ENTITY RAT_util_vector_logic_0_0 IS PORT ( Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END RAT_util_vector_logic_0_0; ARCHITECTURE RAT_util_vector_logic_0_0_arch OF RAT_util_vector_logic_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_util_vector_logic_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT util_vector_logic IS GENERIC ( C_OPERATION : STRING; C_SIZE : INTEGER ); PORT ( Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT util_vector_logic; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF RAT_util_vector_logic_0_0_arch: ARCHITECTURE IS "util_vector_logic,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_util_vector_logic_0_0_arch : ARCHITECTURE IS "RAT_util_vector_logic_0_0,util_vector_logic,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF RAT_util_vector_logic_0_0_arch: ARCHITECTURE IS "RAT_util_vector_logic_0_0,util_vector_logic,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_OPERATION=and,C_SIZE=1}"; BEGIN U0 : util_vector_logic GENERIC MAP ( C_OPERATION => "and", C_SIZE => 1 ) PORT MAP ( Op1 => Op1, Op2 => Op2, Res => Res ); END RAT_util_vector_logic_0_0_arch;

mit

e46d02ade27a0f788f7029ed68973b01

MiddleMan5/233

Experiments/Experiment8-GeterDone/RTL/prog_rom.vhd

----------------------------------------------------------------------------- -- Definition of a single port ROM for RATASM defined by prog_rom.psm -- -- Generated by RATASM Assembler -- -- Standard IEEE libraries -- ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use unisim.vcomponents.all; ----------------------------------------------------------------------------- entity prog_rom is port ( ADDRESS : in std_logic_vector(9 downto 0); INSTRUCTION : out std_logic_vector(17 downto 0); CLK : in std_logic); end prog_rom; architecture low_level_definition of prog_rom is ----------------------------------------------------------------------------- -- Attributes to define ROM contents during implementation synthesis. -- The information is repeated in the generic map for functional simulation. ----------------------------------------------------------------------------- attribute INIT_00 : string; attribute INIT_01 : string; attribute INIT_02 : string; attribute INIT_03 : string; attribute INIT_04 : string; attribute INIT_05 : string; attribute INIT_06 : string; attribute INIT_07 : string; attribute INIT_08 : string; attribute INIT_09 : string; attribute INIT_0A : string; attribute INIT_0B : string; attribute INIT_0C : string; attribute INIT_0D : string; attribute INIT_0E : string; attribute INIT_0F : string; attribute INIT_10 : string; attribute INIT_11 : string; attribute INIT_12 : string; attribute INIT_13 : string; attribute INIT_14 : string; attribute INIT_15 : string; attribute INIT_16 : string; attribute INIT_17 : string; attribute INIT_18 : string; attribute INIT_19 : string; attribute INIT_1A : string; attribute INIT_1B : string; attribute INIT_1C : string; attribute INIT_1D : string; attribute INIT_1E : string; attribute INIT_1F : string; attribute INIT_20 : string; attribute INIT_21 : string; attribute INIT_22 : string; attribute INIT_23 : string; attribute INIT_24 : string; attribute INIT_25 : string; attribute INIT_26 : string; attribute INIT_27 : string; attribute INIT_28 : string; attribute INIT_29 : string; attribute INIT_2A : string; attribute INIT_2B : string; attribute INIT_2C : string; attribute INIT_2D : string; attribute INIT_2E : string; attribute INIT_2F : string; attribute INIT_30 : string; attribute INIT_31 : string; attribute INIT_32 : string; attribute INIT_33 : string; attribute INIT_34 : string; attribute INIT_35 : string; attribute INIT_36 : string; attribute INIT_37 : string; attribute INIT_38 : string; attribute INIT_39 : string; attribute INIT_3A : string; attribute INIT_3B : string; attribute INIT_3C : string; attribute INIT_3D : string; attribute INIT_3E : string; attribute INIT_3F : string; attribute INITP_00 : string; attribute INITP_01 : string; attribute INITP_02 : string; attribute INITP_03 : string; attribute INITP_04 : string; attribute INITP_05 : string; attribute INITP_06 : string; attribute INITP_07 : string; ---------------------------------------------------------------------- -- Attributes to define ROM contents during implementation synthesis. ---------------------------------------------------------------------- attribute INIT_00 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_01 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000080804A400A5A6BFF2A20"; attribute INIT_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_08 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_09 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_3F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_00 of ram_1024_x_18 : label is "000000000000000000000000000000000000000000000000000000CF00000000"; attribute INITP_01 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INITP_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000"; begin ---------------------------------------------------------------------- --Instantiate the Xilinx primitive for a block RAM --INIT values repeated to define contents for functional simulation ---------------------------------------------------------------------- ram_1024_x_18: RAMB16_S18 --synthesitranslate_off --INIT values repeated to define contents for functional simulation generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000080804A400A5A6BFF2A20", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_00 => X"000000000000000000000000000000000000000000000000000000CF00000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000") --synthesis translate_on port map( DI => "0000000000000000", DIP => "00", EN => '1', WE => '0', SSR => '0', CLK => clk, ADDR => address, DO => INSTRUCTION(15 downto 0), DOP => INSTRUCTION(17 downto 16)); -- end low_level_definition; -- ---------------------------------------------------------------------- -- END OF FILE prog_rom.vhd ----------------------------------------------------------------------

mit

0703fe65ff20b5443a9291bf73ad2b63

David-Estevez/spaceinvaders

src/invaders_tb.vhd

---------------------------------------------------------------------------------- -- -- Lab session #4: Invaders testbech -- -- Testing the block controlling the space invaders -- -- Each invader has its power encoded in 2 bits: -- 00 -> no invader -- 01 -> easy invader (1 shot) [green] -- 10 -> medium invader (2 shots) [?] -- 11 -> hard invader (3 shots) [white] -- -- Authors: -- David Estévez Fernández -- Sergio Vilches Expósito -- ---------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY invaders_tb IS END invaders_tb; ARCHITECTURE behavior OF invaders_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT invaders PORT( clk : IN std_logic; reset : IN std_logic; start : in std_logic; bullX : IN std_logic_vector(4 downto 0); bullY : IN std_logic_vector(3 downto 0); hit : OUT std_logic; invArray : INOUT std_logic_vector(39 downto 0); invLine : INOUT std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal reset : std_logic := '0'; signal start: std_logic := '0'; signal bullX : std_logic_vector(4 downto 0) := std_logic_vector(to_unsigned(10,5)); signal bullY : std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(10,4)); --BiDirs signal invArray : std_logic_vector(39 downto 0); signal invLine : std_logic_vector(3 downto 0); --Outputs signal hit : std_logic; -- Clock period definitions constant clk_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: invaders PORT MAP ( clk => clk, reset => reset, start => start, bullX => bullX, bullY => bullY, hit => hit, invArray => invArray, invLine => invLine ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. reset <= '1'; wait for 100 ns; reset <= '0'; start <= '1'; wait for 1200 ms; -- Simulate a bullet: bullX <= std_logic_vector(to_unsigned(5,5)); bullY <= invLine; wait until hit = '1'; -- Reset the bullet bullX <= std_logic_vector(to_unsigned(0,5)) after clk_period; bullY <= std_logic_vector(to_unsigned(0,4)) after clk_period; wait; end process; END;

gpl-3.0

b6244eeb53094387b6ec30d4d0bb78db

odeke-em/hdl-class

learning/generics.vhd

entity And2 is generic (delay: DELAY_LENGTH) -- DELAY_LENGTH is a subtype: time range 0 fs to highest_time in the system port (x, y: in BIT; z: out BIT); end entity And2; architecture arch2 of And2 is begin z <= x and y after delay; end architecture arch2; -- When gate is used in a netlist, a value is passed to the model using a generic map g2: entity WORK.And2(arch2) generic map(5 ns) port map(p, b, q); -- Or the non-positional form can be used g2: entity WORK.And2(arch2) generic map(delay => 5ns) port map (z=>q, x=>p, y=>b); -- Omit generic map if default value is used generic(delay: DELAY_LENGTH := 5 ns); -- Using defaults g2: entity WORK.And2(arch2) port map(p, b, q); -- 5ns is passed to delay -- Or like this g2: entity WORK.And2(arch2) generic map(3 ns) port map(p, b, q); -- the default value will be used if reserved word "open" is used: g2: entity WORK.And2(arch2) generic map(open) port map(p, b, q);

mit

72a59cdf63d2f52b2b46e86ba1bde449

MiddleMan5/233

Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_slice_12_8_0/sim/RAT_slice_12_8_0.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:xlslice:1.0 -- IP Revision: 0 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY work; USE work.xlslice; ENTITY RAT_slice_12_8_0 IS PORT ( Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); Dout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END RAT_slice_12_8_0; ARCHITECTURE RAT_slice_12_8_0_arch OF RAT_slice_12_8_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_12_8_0_arch: ARCHITECTURE IS "yes"; COMPONENT xlslice IS GENERIC ( DIN_WIDTH : INTEGER; DIN_FROM : INTEGER; DIN_TO : INTEGER ); PORT ( Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); Dout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END COMPONENT xlslice; BEGIN U0 : xlslice GENERIC MAP ( DIN_WIDTH => 18, DIN_FROM => 7, DIN_TO => 3 ) PORT MAP ( Din => Din, Dout => Dout ); END RAT_slice_12_8_0_arch;

mit

22ca9002614fe5b6947553250a017a22

MiddleMan5/233

Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_StackPointer_0_0/sim/RAT_StackPointer_0_0.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:module_ref:StackPointer:1.0 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY RAT_StackPointer_0_0 IS PORT ( DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); RST : IN STD_LOGIC; LD : IN STD_LOGIC; INCR : IN STD_LOGIC; DECR : IN STD_LOGIC; CLK : IN STD_LOGIC; DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END RAT_StackPointer_0_0; ARCHITECTURE RAT_StackPointer_0_0_arch OF RAT_StackPointer_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_StackPointer_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT StackPointer IS PORT ( DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); RST : IN STD_LOGIC; LD : IN STD_LOGIC; INCR : IN STD_LOGIC; DECR : IN STD_LOGIC; CLK : IN STD_LOGIC; DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT StackPointer; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF RST: SIGNAL IS "xilinx.com:signal:reset:1.0 RST RST"; ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK"; BEGIN U0 : StackPointer PORT MAP ( DATA => DATA, RST => RST, LD => LD, INCR => INCR, DECR => DECR, CLK => CLK, DOUT => DOUT ); END RAT_StackPointer_0_0_arch;

mit

a08b9ec44164816515ca0539dc1487cc

MiddleMan5/233

Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlslice_0_0/synth/RAT_xlslice_0_0.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:xlslice:1.0 -- IP Revision: 0 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY work; USE work.xlslice; ENTITY RAT_xlslice_0_0 IS PORT ( Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); Dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END RAT_xlslice_0_0; ARCHITECTURE RAT_xlslice_0_0_arch OF RAT_xlslice_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_xlslice_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT xlslice IS GENERIC ( DIN_WIDTH : INTEGER; DIN_FROM : INTEGER; DIN_TO : INTEGER ); PORT ( Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); Dout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT xlslice; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF RAT_xlslice_0_0_arch: ARCHITECTURE IS "xlslice,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_xlslice_0_0_arch : ARCHITECTURE IS "RAT_xlslice_0_0,xlslice,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF RAT_xlslice_0_0_arch: ARCHITECTURE IS "RAT_xlslice_0_0,xlslice,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=18,DIN_FROM=12,DIN_TO=3}"; BEGIN U0 : xlslice GENERIC MAP ( DIN_WIDTH => 18, DIN_FROM => 12, DIN_TO => 3 ) PORT MAP ( Din => Din, Dout => Dout ); END RAT_xlslice_0_0_arch;

mit

28a43613701d0a3b321e255a674970a3

stefanct/aua

hw/reg/src/ram_inst.vhd

ram_inst : ram PORT MAP ( clock => clock_sig, data => data_sig, rdaddress => rdaddress_sig, wraddress => wraddress_sig, wren => wren_sig, q => q_sig );

gpl-3.0

7d32554e1bb38cdc20e1f8b6c3e3c6dd

MiddleMan5/233

Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Decrementer_0_0/RAT_Decrementer_0_0_sim_netlist.vhdl

-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -- Date : Fri Oct 27 10:20:39 2017 -- Host : Juice-Laptop running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Decrementer_0_0/RAT_Decrementer_0_0_sim_netlist.vhdl -- Design : RAT_Decrementer_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7a35tcpg236-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity RAT_Decrementer_0_0_Decrementer is port ( O : out STD_LOGIC_VECTOR ( 2 downto 0 ); I : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of RAT_Decrementer_0_0_Decrementer : entity is "Decrementer"; end RAT_Decrementer_0_0_Decrementer; architecture STRUCTURE of RAT_Decrementer_0_0_Decrementer is signal \O[7]_INST_0_i_1_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \O[6]_INST_0\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \O[7]_INST_0\ : label is "soft_lutpair0"; begin \O[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I(0), O => O(0) ); \O[6]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \O[7]_INST_0_i_1_n_0\, I1 => I(6), O => O(1) ); \O[7]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"E1" ) port map ( I0 => I(6), I1 => \O[7]_INST_0_i_1_n_0\, I2 => I(7), O => O(2) ); \O[7]_INST_0_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => I(4), I1 => I(2), I2 => I(0), I3 => I(1), I4 => I(3), I5 => I(5), O => \O[7]_INST_0_i_1_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity RAT_Decrementer_0_0 is port ( I : in STD_LOGIC_VECTOR ( 7 downto 0 ); O : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of RAT_Decrementer_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of RAT_Decrementer_0_0 : entity is "RAT_Decrementer_0_0,Decrementer,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of RAT_Decrementer_0_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of RAT_Decrementer_0_0 : entity is "Decrementer,Vivado 2016.4"; end RAT_Decrementer_0_0; architecture STRUCTURE of RAT_Decrementer_0_0 is begin \O[1]_INST_0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => I(0), I1 => I(1), O => O(1) ); \O[2]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"E1" ) port map ( I0 => I(1), I1 => I(0), I2 => I(2), O => O(2) ); \O[3]_INST_0\: unisim.vcomponents.LUT4 generic map( INIT => X"FE01" ) port map ( I0 => I(2), I1 => I(0), I2 => I(1), I3 => I(3), O => O(3) ); \O[4]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0001" ) port map ( I0 => I(3), I1 => I(1), I2 => I(0), I3 => I(2), I4 => I(4), O => O(4) ); \O[5]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFE00000001" ) port map ( I0 => I(4), I1 => I(2), I2 => I(0), I3 => I(1), I4 => I(3), I5 => I(5), O => O(5) ); U0: entity work.RAT_Decrementer_0_0_Decrementer port map ( I(7 downto 0) => I(7 downto 0), O(2 downto 1) => O(7 downto 6), O(0) => O(0) ); end STRUCTURE;

mit

dcfdf12cac787cebc7edb8a4ba1fffcb

MiddleMan5/233

Experiments/Experiment8-GeterDone/RTL/RAT_Basys3_Interface.vhd

---------------------------------------------------------------------------------- -- Company: RAT Technologies (a subdivision of Cal Poly CENG) -- Engineer: Various RAT rats -- -- Create Date: 02/03/2017 -- Module Name: RAT_wrapper - Behavioral -- Target Devices: Basys3 -- Description: Wrapper for RAT CPU. This model provides a template to interfaces -- the RAT CPU to the Basys3 development board. -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity RAT_Basys3_wrapper is Port ( LEDS : out STD_LOGIC_VECTOR (7 downto 0); SWITCHES : in STD_LOGIC_VECTOR (7 downto 0); RST : in STD_LOGIC; CLK : in STD_LOGIC); end RAT_Basys3_wrapper; architecture Behavioral of RAT_Basys3_wrapper is -- INPUT PORT IDS ------------------------------------------------------------- -- Right now, the only possible inputs are the switches -- In future labs you can add more port IDs, and you'll have -- to add constants here for the mux below CONSTANT SWITCHES_ID : STD_LOGIC_VECTOR (7 downto 0) := X"20"; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- OUTPUT PORT IDS ------------------------------------------------------------ -- In future labs you can add more port IDs CONSTANT LEDS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"40"; ------------------------------------------------------------------------------- -- Declare RAT_CPU ------------------------------------------------------------ component RAT_wrapper Port ( IN_PORT : in STD_LOGIC_VECTOR (7 downto 0); OUT_PORT : out STD_LOGIC_VECTOR (7 downto 0); PORT_ID : out STD_LOGIC_VECTOR (7 downto 0); INT_IN : in STD_LOGIC_VECTOR (0 downto 0); CLK : in STD_LOGIC; RST : in STD_LOGIC); end component RAT_wrapper; ------------------------------------------------------------------------------- -- Declare Clock Divider ------------------------------------------------------ component clk_div_fs is Port ( CLK : in std_logic; FCLK,SCLK : out std_logic); end component clk_div_fs; ------------------------------------------------------------------------------- -- Signals for connecting RAT_CPU to RAT_wrapper ------------------------------- signal s_input_port : std_logic_vector (7 downto 0); signal s_output_port : std_logic_vector (7 downto 0); signal s_port_id : std_logic_vector (7 downto 0); signal s_sloclk : std_logic; --signal s_interrupt : std_logic; -- not yet used -- Register definitions for output devices ------------------------------------ -- add signals for any added outputs signal r_LEDS : std_logic_vector (7 downto 0); ------------------------------------------------------------------------------- begin s_sloclk <= CLK; -- CLK_DIVIDER: clk_div_fs -- port map( CLK => CLK, -- SCLK => s_sloclk, -- FCLK => open); -- Instantiate RAT_CPU -------------------------------------------------------- CPU: RAT_wrapper port map( IN_PORT => s_input_port, OUT_PORT => s_output_port, PORT_ID => s_port_id, INT_IN => "0", -- s_interrupt CLK => s_sloclk, RST => RST); ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- MUX for selecting what input to read --------------------------------------- -- add conditions and connections for any added PORT IDs ------------------------------------------------------------------------------- inputs: process(s_port_id, SWITCHES) begin if (s_port_id = SWITCHES_ID) then s_input_port <= SWITCHES; else s_input_port <= x"00"; end if; end process inputs; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- MUX for updating output registers ------------------------------------------ -- Register updates depend on rising clock edge and asserted load signal -- add conditions and connections for any added PORT IDs ------------------------------------------------------------------------------- outputs: process(s_sloclk) begin if (rising_edge(s_sloclk)) then -- the register definition for the LEDS if (s_port_id = LEDS_ID) then r_LEDS <= s_output_port; end if; end if; end process outputs; ------------------------------------------------------------------------------- -- Register Interface Assignments --------------------------------------------- -- add all outputs that you added to this design LEDS <= r_LEDS; end Behavioral;

mit

62964ee4bb48ac1afce9b566bf402512

marcoep/MusicBoxNano

hdl/PWMGenerator.vhd

------------------------------------------------------------------------------- -- Title : PWM Generator -- Project : ------------------------------------------------------------------------------- -- File : PWMGenerator.vhd -- Author : <Marco@JUDI-WIN10> -- Company : -- Created : 2016-08-01 -- Last update: 2016-08-01 -- Platform : Mentor Graphics ModelSim, Altera Quartus -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Generate PWM with given pulse width. ------------------------------------------------------------------------------- -- Copyright (c) 2016 Marco Eppenberger ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-08-01 1.0 Marco Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity PWMGenerator is port ( Clk_CI : in std_logic; Reset_SI : in std_logic; DutyCycle_DI : in std_logic_vector(9 downto 0); PulseOut_DO : out std_logic); end entity PWMGenerator; architecture RTL of PWMGenerator is signal DutyCycle_D : unsigned(9 downto 0) := (others => '0'); signal PWMCounter_D : unsigned(9 downto 0) := (others => '0'); begin outreg : process (Clk_CI) is begin -- process outreg if Clk_CI'event and Clk_CI = '1' then -- rising clock edge if Reset_SI = '1' then -- synchronous reset (active high) DutyCycle_D <= (others => '0'); PWMCounter_D <= (others => '0'); PulseOut_DO <= '0'; else DutyCycle_D <= unsigned(DutyCycle_DI); PWMCounter_D <= PWMCounter_D + 1; if PWMCounter_D < DutyCycle_D then PulseOut_DO <= '1'; else PulseOut_DO <= '0'; end if; end if; end if; end process outreg; end architecture RTL;

gpl-3.0

398031b792bf2ab3e4fe89ef810fcf2a

MiddleMan5/233

Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_ScratchRam_0_0/synth/RAT_ScratchRam_0_0.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:module_ref:ScratchRam:1.0 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY RAT_ScratchRam_0_0 IS PORT ( DATA_IN : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DATA_OUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); ADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); WE : IN STD_LOGIC; CLK : IN STD_LOGIC ); END RAT_ScratchRam_0_0; ARCHITECTURE RAT_ScratchRam_0_0_arch OF RAT_ScratchRam_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_ScratchRam_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT ScratchRam IS PORT ( DATA_IN : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DATA_OUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); ADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); WE : IN STD_LOGIC; CLK : IN STD_LOGIC ); END COMPONENT ScratchRam; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF RAT_ScratchRam_0_0_arch: ARCHITECTURE IS "ScratchRam,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_ScratchRam_0_0_arch : ARCHITECTURE IS "RAT_ScratchRam_0_0,ScratchRam,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF RAT_ScratchRam_0_0_arch: ARCHITECTURE IS "RAT_ScratchRam_0_0,ScratchRam,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=ScratchRam,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK"; BEGIN U0 : ScratchRam PORT MAP ( DATA_IN => DATA_IN, DATA_OUT => DATA_OUT, ADDR => ADDR, WE => WE, CLK => CLK ); END RAT_ScratchRam_0_0_arch;

mit

bdd149fc35452eed4adc4e8909d5eadf

MiddleMan5/233

Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux2x1_10_0_0/RAT_Mux2x1_10_0_0_sim_netlist.vhdl

-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -- Date : Fri Oct 27 10:19:56 2017 -- Host : Juice-Laptop running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux2x1_10_0_0/RAT_Mux2x1_10_0_0_sim_netlist.vhdl -- Design : RAT_Mux2x1_10_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7a35tcpg236-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity RAT_Mux2x1_10_0_0_Mux2x1_10 is port ( X : out STD_LOGIC_VECTOR ( 9 downto 0 ); B : in STD_LOGIC_VECTOR ( 9 downto 0 ); A : in STD_LOGIC_VECTOR ( 9 downto 0 ); SEL : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of RAT_Mux2x1_10_0_0_Mux2x1_10 : entity is "Mux2x1_10"; end RAT_Mux2x1_10_0_0_Mux2x1_10; architecture STRUCTURE of RAT_Mux2x1_10_0_0_Mux2x1_10 is attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \X[0]_INST_0\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \X[1]_INST_0\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \X[2]_INST_0\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \X[3]_INST_0\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \X[4]_INST_0\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \X[5]_INST_0\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \X[6]_INST_0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \X[7]_INST_0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \X[8]_INST_0\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \X[9]_INST_0\ : label is "soft_lutpair4"; begin \X[0]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => B(0), I1 => A(0), I2 => SEL, O => X(0) ); \X[1]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => B(1), I1 => A(1), I2 => SEL, O => X(1) ); \X[2]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => B(2), I1 => A(2), I2 => SEL, O => X(2) ); \X[3]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => B(3), I1 => A(3), I2 => SEL, O => X(3) ); \X[4]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => B(4), I1 => A(4), I2 => SEL, O => X(4) ); \X[5]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => B(5), I1 => A(5), I2 => SEL, O => X(5) ); \X[6]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => B(6), I1 => A(6), I2 => SEL, O => X(6) ); \X[7]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => B(7), I1 => A(7), I2 => SEL, O => X(7) ); \X[8]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => B(8), I1 => A(8), I2 => SEL, O => X(8) ); \X[9]_INST_0\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => B(9), I1 => A(9), I2 => SEL, O => X(9) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity RAT_Mux2x1_10_0_0 is port ( A : in STD_LOGIC_VECTOR ( 9 downto 0 ); B : in STD_LOGIC_VECTOR ( 9 downto 0 ); SEL : in STD_LOGIC; X : out STD_LOGIC_VECTOR ( 9 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of RAT_Mux2x1_10_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of RAT_Mux2x1_10_0_0 : entity is "RAT_Mux2x1_10_0_0,Mux2x1_10,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of RAT_Mux2x1_10_0_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of RAT_Mux2x1_10_0_0 : entity is "Mux2x1_10,Vivado 2016.4"; end RAT_Mux2x1_10_0_0; architecture STRUCTURE of RAT_Mux2x1_10_0_0 is begin U0: entity work.RAT_Mux2x1_10_0_0_Mux2x1_10 port map ( A(9 downto 0) => A(9 downto 0), B(9 downto 0) => B(9 downto 0), SEL => SEL, X(9 downto 0) => X(9 downto 0) ); end STRUCTURE;

mit

78b405b35554d125c09f606e2e1d0282

MiddleMan5/233

Experiments/Experiment7-Its_Alive/RTL/RAT_Wrapper_W2017.vhd

---------------------------------------------------------------------------------- -- Company: RAT Technologies (a subdivision of Cal Poly CENG) -- Engineer: Various RAT rats -- -- Create Date: 02/03/2017 -- Module Name: RAT_wrapper - Behavioral -- Target Devices: Basys3 -- Description: Wrapper for RAT CPU. This model provides a template to interfaces -- the RAT CPU to the Basys3 development board. -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity RAT_Basys3_wrapper is Port ( LEDS : out STD_LOGIC_VECTOR (7 downto 0); SWITCHES : in STD_LOGIC_VECTOR (7 downto 0); RST : in STD_LOGIC; CLK : in STD_LOGIC); end RAT_Basys3_wrapper; architecture Behavioral of RAT_Basys3_wrapper is -- INPUT PORT IDS ------------------------------------------------------------- -- Right now, the only possible inputs are the switches -- In future labs you can add more port IDs, and you'll have -- to add constants here for the mux below CONSTANT SWITCHES_ID : STD_LOGIC_VECTOR (7 downto 0) := X"20"; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- OUTPUT PORT IDS ------------------------------------------------------------ -- In future labs you can add more port IDs CONSTANT LEDS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"40"; ------------------------------------------------------------------------------- -- Declare RAT_CPU ------------------------------------------------------------ component RAT_wrapper Port ( IN_PORT : in STD_LOGIC_VECTOR (7 downto 0); OUT_PORT : out STD_LOGIC_VECTOR (7 downto 0); PORT_ID : out STD_LOGIC_VECTOR (7 downto 0); INT_IN : in STD_LOGIC_VECTOR (0 downto 0); CLK : in STD_LOGIC; RST : in STD_LOGIC); end component RAT_wrapper; ------------------------------------------------------------------------------- -- Signals for connecting RAT_CPU to RAT_wrapper ------------------------------- signal s_input_port : std_logic_vector (7 downto 0); signal s_output_port : std_logic_vector (7 downto 0); signal s_port_id : std_logic_vector (7 downto 0); --signal s_interrupt : std_logic; -- not yet used -- Register definitions for output devices ------------------------------------ -- add signals for any added outputs signal r_LEDS : std_logic_vector (7 downto 0); ------------------------------------------------------------------------------- begin -- Instantiate RAT_CPU -------------------------------------------------------- CPU: RAT_wrapper port map( IN_PORT => s_input_port, OUT_PORT => s_output_port, PORT_ID => s_port_id, INT_IN => "0", -- s_interrupt CLK => CLK, RST => '0'); ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- MUX for selecting what input to read --------------------------------------- -- add conditions and connections for any added PORT IDs ------------------------------------------------------------------------------- inputs: process(s_port_id, SWITCHES) begin if (s_port_id = SWITCHES_ID) then s_input_port <= SWITCHES; else s_input_port <= x"00"; end if; end process inputs; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- MUX for updating output registers ------------------------------------------ -- Register updates depend on rising clock edge and asserted load signal -- add conditions and connections for any added PORT IDs ------------------------------------------------------------------------------- outputs: process(CLK) begin if (rising_edge(CLK)) then -- the register definition for the LEDS if (s_port_id = LEDS_ID) then r_LEDS <= s_output_port; end if; end if; end process outputs; ------------------------------------------------------------------------------- -- Register Interface Assignments --------------------------------------------- -- add all outputs that you added to this design LEDS <= r_LEDS; end Behavioral;

mit

3746fb028341434a66407ae1801e449d

MiddleMan5/233

Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_slice_1_0_0/sim/RAT_slice_1_0_0.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:xlslice:1.0 -- IP Revision: 0 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY work; USE work.xlslice; ENTITY RAT_slice_1_0_0 IS PORT ( Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); Dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END RAT_slice_1_0_0; ARCHITECTURE RAT_slice_1_0_0_arch OF RAT_slice_1_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_1_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT xlslice IS GENERIC ( DIN_WIDTH : INTEGER; DIN_FROM : INTEGER; DIN_TO : INTEGER ); PORT ( Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); Dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT xlslice; BEGIN U0 : xlslice GENERIC MAP ( DIN_WIDTH => 18, DIN_FROM => 7, DIN_TO => 0 ) PORT MAP ( Din => Din, Dout => Dout ); END RAT_slice_1_0_0_arch;

mit

ec6883a80568c7c27ff77985efa5a79f

alpenwasser/pitaya

firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ipshared/xilinx.com/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd

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mit

ebf1512b4ea59c40a1fc73b2366761af

open-power/snap

hardware/hdl/core/axi_dma_shim.vhd

---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- -- Copyright 2016,2017 International Business Machines -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions AND -- limitations under the License. -- ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- change log: -- 12/20/2016 R. Rieke removed fix for DMA overrun issue -- 03/15/2017 R. Rieke added support for interrupts and context id library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; use ieee.STD_LOGIC_UNSIGNED.all; use ieee.numeric_std.all; USE work.psl_accel_types.ALL; USE work.snap_core_types.all; entity axi_dma_shim is port ( -- Users to add ports here -- User ports ends -- Do not modify the ports beyond this line -- Global Clock Signal ha_pclock : in std_logic; -- Global Reset Signal. This Signal is Active LOW afu_reset : in std_logic; sd_c_o : out SD_C_T; sd_d_o : out SD_D_T; ds_c_i : in DS_C_T; ds_d_i : in DS_D_T; sj_c_o : out SJ_C_T; js_c_i : in JS_C_T; sk_d_o : out SK_D_T; ks_d_i : in KS_D_T ); end axi_dma_shim; architecture arch_imp of axi_dma_shim is type wr_fsm_t is (IDLE, DMA_WR_REQ, DMA_WR_DATA); type rd_fsm_t is (IDLE, DMA_RD_REQ); type fifo_buffer_t is array (0 to 31) of std_logic_vector(19 downto 0); type int_req_vec_t is array (0 to NUM_OF_ACTIONS) of std_logic; type int_src_vec_t is array (0 to NUM_OF_ACTIONS) of std_logic_vector(INT_BITS -2 downto 0 ); type int_ctx_vec_t is array (0 to NUM_OF_ACTIONS) of std_logic_vector(CONTEXT_BITS - 1 downto 0 ); signal fsm_read_q : rd_fsm_t; signal fsm_write_q : wr_fsm_t; signal fifo_buffer_q : fifo_buffer_t; -- AXI4FULL signals signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); signal axi_awready_q : std_logic; signal axi_wready_q : std_logic; signal axi_arready_q : std_logic; signal axi_rvalid : std_logic; signal axi_awlen : std_logic_vector(8-1 downto 0); signal id_fifo_wr_id_q : std_logic_vector(C_S_AXI_ID_WIDTH - 1 downto 0); signal id_fifo_data : std_logic_vector(C_S_AXI_ID_WIDTH - 1 downto 0); signal id_fifo_read : std_logic; signal id_fifo_empty_q : std_logic; signal id_fifo_wr_q : std_logic; signal force_fifo_empty_q : std_logic; signal fifo_wr_addr_q : std_logic_vector(4 downto 0); signal fifo_rd_addr_q : std_logic_vector(4 downto 0); signal int_req_vec : int_req_vec_t; signal int_src_vec : int_src_vec_t; signal int_ctx_vec : int_ctx_vec_t; signal int_ack_pending : std_logic; signal int_src_sel : integer range 0 to 16; -------------------------------------------------- begin -- I/O Connections assignments sk_d_o.S_AXI_AWREADY <= axi_awready_q; sk_d_o.S_AXI_WREADY <= axi_wready_q; sk_d_o.S_AXI_ARREADY <= axi_arready_q; fifo_logic: process(ha_pclock) begin if rising_edge(ha_pclock) then if afu_reset = '1' then fifo_wr_addr_q <= (others => '0'); fifo_rd_addr_q <= (others => '0'); id_fifo_empty_q <= '1'; force_fifo_empty_q <= '1'; else force_fifo_empty_q <= '0'; if id_fifo_wr_q = '1' then fifo_wr_addr_q <= fifo_wr_addr_q + '1'; end if; if id_fifo_read = '1' then force_fifo_empty_q <= '1'; fifo_rd_addr_q <= fifo_rd_addr_q + "00001"; end if; if fifo_wr_addr_q = fifo_rd_addr_q or id_fifo_read = '1' then id_fifo_empty_q <= '1'; else id_fifo_empty_q <= force_fifo_empty_q; end if; end if; -- else reset if id_fifo_wr_q = '1' then fifo_buffer_q(to_integer(unsigned(fifo_wr_addr_q))) <= id_fifo_wr_id_q; end if; end if; -- rising_edge end process; id_fifo_data <= fifo_buffer_q(to_integer(unsigned(fifo_rd_addr_q))); sk_d_o.S_AXI_BID <= id_fifo_data; sk_d_o.S_AXI_BRESP <= "00"; bvalid: process(id_fifo_empty_q, ks_d_i.S_AXI_BREADY ) begin sk_d_o.S_AXI_BVALID <= '0'; id_fifo_read <= '0'; if id_fifo_empty_q = '0' and ks_d_i.S_AXI_BREADY = '1' then sk_d_o.S_AXI_BVALID <= '1'; id_fifo_read <= '1'; end if; end process; axi_wr: process(ha_pclock) -- receive data from axi and send it to DMA begin if rising_edge(ha_pclock) then sd_d_o.wr_strobe <= (others => '0'); sd_d_o.wr_last <= '0'; -- reverse the byte order for i in 1 to C_S_AXI_DATA_WIDTH / 8 loop sd_d_o.wr_data(i * 8 - 1 downto (i-1) *8) <= ks_d_i.S_AXI_WDATA((C_S_AXI_DATA_WIDTH + 7)- i*8 downto C_S_AXI_DATA_WIDTH - i*8); end loop; -- i -- sd_d_o.wr_data <= ks_d_i.S_AXI_WDATA; case fsm_write_q is when IDLE => axi_awready_q <= '1'; sd_c_o.wr_req <= '0'; sd_d_o.wr_strobe <= (others => '0'); if axi_awready_q = '1' and ks_d_i.S_AXI_AWVALID = '1' then fsm_write_q <= DMA_WR_REQ; axi_awready_q <= '0'; sd_c_o.wr_addr <= ks_d_i.S_AXI_AWADDR; sd_c_o.wr_len <= ks_d_i.S_AXI_AWLEN; sd_c_o.wr_id <= ks_d_i.S_AXI_AWID; sd_c_o.wr_ctx <= ks_d_i.S_AXI_AWUSER; sd_c_o.wr_req <= '1'; end if; when DMA_WR_REQ => if ds_c_i.wr_req_ack = '1' then sd_c_o.wr_req <= '0'; -- axi_wready_q <= '1'; axi_wready_q <= ds_d_i.wr_data_ready; fsm_write_q <= DMA_WR_DATA; end if; when DMA_WR_DATA => axi_wready_q <= ds_d_i.wr_data_ready; if ks_d_i.S_AXI_WVALID = '1' then for i in 0 to (C_S_AXI_DATA_WIDTH / 8) -1 LOOP sd_d_o.wr_strobe(((C_S_AXI_DATA_WIDTH / 8) -1) - i) <= ks_d_i.S_AXI_WSTRB(i); end loop; -- i if (ks_d_i.S_AXI_WLAST = '1' AND axi_wready_q = '1') then sd_d_o.wr_last <= '1'; axi_wready_q <= '0'; fsm_write_q <= IDLE; end if; end if; when others => null; end case; -- handle wr completion id_fifo_wr_q <= '0'; if ds_c_i.wr_id_valid = '1' then id_fifo_wr_q <= '1'; id_fifo_wr_id_q <= std_logic_vector(ds_c_i.wr_id); end if; if afu_reset = '1' then fsm_write_q <= IDLE; axi_awready_q <= '0'; axi_wready_q <= '0'; sd_c_o.wr_req <= '0'; id_fifo_wr_q <= '0'; end if; end if; end process; axi_rd: process(ha_pclock) -- receive read request from axi and forward to DMA begin if rising_edge(ha_pclock) then case fsm_read_q is when IDLE => axi_arready_q <= '1'; if axi_arready_q = '1' and ks_d_i.S_AXI_ARVALID = '1' then fsm_read_q <= DMA_RD_REQ; axi_arready_q <= '0'; sd_c_o.rd_addr <= ks_d_i.S_AXI_ARADDR; sd_c_o.rd_len <= ks_d_i.S_AXI_ARLEN; sd_c_o.rd_id <= ks_d_i.S_AXI_ARID; sd_c_o.rd_ctx <= ks_d_i.S_AXI_ARUSER; sd_c_o.rd_req <= '1'; end if; when DMA_RD_REQ => if ds_c_i.rd_req_ack = '1' then sd_c_o.rd_req <= '0'; fsm_read_q <= IDLE; end if; when others => end case; if afu_reset = '1' then fsm_read_q <= IDLE; axi_arready_q <= '0'; sd_c_o.rd_req <= '0'; end if; -- end reset end if; -- end clock end process; sk_d_o.S_AXI_RLAST <= ds_d_i.rd_last; axi_rd2: process(ds_d_i.rd_data, ds_d_i.rd_id, ds_d_i.rd_data_strobe,ks_d_i.S_AXI_RREADY) begin -- reverse the byte order for i in 1 to C_S_AXI_DATA_WIDTH / 8 loop sk_d_o.S_AXI_RDATA(i * 8 - 1 downto (i-1) *8) <= std_logic_vector(ds_d_i.rd_data((C_S_AXI_DATA_WIDTH + 7) - i*8 downto C_S_AXI_DATA_WIDTH - i*8)); end loop; -- i sk_d_o.S_AXI_RID <= std_logic_vector(ds_d_i.rd_id); sk_d_o.S_AXI_RRESP <= "00"; sk_d_o.S_AXI_RVALID <= '0'; sd_d_o.rd_data_ack <= '0'; sk_d_o.S_AXI_RVALID <= ds_d_i.rd_data_strobe; if ds_d_i.rd_data_strobe = '1' and ks_d_i.S_AXI_RREADY = '1' then sd_d_o.rd_data_ack <= '1'; end if; end process; -------------------------------Interrupt Logic------------------------------------- int_process: process(ha_pclock) -- receive read request from axi and forward to DMA begin if rising_edge(ha_pclock) then sd_c_o.int_req <= '0'; sj_c_o.int_ack <= '0'; sk_d_o.int_req_ack <= '0'; if js_c_i.int_req = '1' then int_req_vec(0) <= '1'; int_src_vec(0) <= js_c_i.int_src; int_ctx_vec(0) <= js_c_i.int_ctx; end if; if ks_d_i.int_req = '1' then int_req_vec(1) <= '1'; int_src_vec(1) <= ks_d_i.int_src; int_ctx_vec(1) <= ks_d_i.int_ctx; end if; -- if we don't wait for an ack, then check for pending interrupts if int_ack_pending = '0' then -- has job manager sent an int if int_req_vec(0) = '1' then int_src_sel <= 0; int_ack_pending <= '1'; int_req_vec(0) <= '0'; sd_c_o.int_req <= '1'; sd_c_o.int_src <= '0' & int_src_vec(0); sd_c_o.int_ctx <= int_ctx_vec(0); else if int_req_vec(1) = '1' then int_src_sel <= 1; int_req_vec(1) <= '0'; int_ack_pending <= '1'; sd_c_o.int_req <= '1'; sd_c_o.int_src <= '1' & int_src_vec(1); sd_c_o.int_ctx <= int_ctx_vec(1); end if; end if; end if; -- handle int ack from DMA if ds_c_i.int_req_ack = '1' then int_ack_pending <= '0'; case int_src_sel is when 0 => sj_c_o.int_ack <= '1'; when others => sk_d_o.int_req_ack <= '1'; end case; end if; if afu_reset = '1' then sd_c_o.int_req <= '0'; sj_c_o.int_ack <= '0'; sk_d_o.int_req_ack <= '0'; int_ack_pending <= '0'; int_req_vec(0) <= '0'; int_req_vec(1) <= '0'; end if; end if; end process; end arch_imp;

apache-2.0

fe8e7a8d86709864725506d24018afd2

ayueha/infomatic-pj

src/ALU/alu-interpriter.vhd

library ieee; use ieee.std_logic_1164.all; --'U' --未初期化 (Uninitialized) --'X' --不定 (Forcing Unknown) --'0' --0 (Forcing 0) --'1' --1 (Forcing 1) --'Z' --ハイインピーダンス状態 (High Impedance) --'W' --弱い信号の不定 (Weak Unknown) --'L' --弱い信号の0 (Weak 0) --'H' --弱い信号の1 (Weak 1) --'-' --don't care entity alu is ---情報の定義 port (　　　　　　　　　　　　　　　　　　　　　　　　　-- n : in std_logic_vector (3 downto 0); --variable "n" input std_logic_vector :0 to 3(0,1,2,3) m : in std_logic_vector (3 downto 0); --variable "m" input std_logic_vector :0 to 3(0,1,2,3) opcode : in std_logic_vector (1 downto 0); --variable optcode input std_logic_vector :0 to 1(0,1) d : out std_logic_vector (3 downto 0); --variable "d" output std_logic_vector :0 to 3(0,1,2,3)　値再利用不可 cout : out std_logic --variable "cont" output std_logic 値再利用不可 ); end alu; architecture behavioral of alu is 　　　　　　　　　　---architecture name : behavioral Entitiy name :alu component carry_ripple_adder ---comportnent name :carry_ripple_adder port ( a : in std_logic_vector (3 downto 0); --variable "a" input std_logic_vector :0 to 3(0,1,2,3) b : in std_logic_vector (3 downto 0); --variable "b" input std_logic_vector :0 to 3(0,1,2,3) ci : in std_logic; --input s : out std_logic_vector (3 downto 0); ---output : 0,1,2,3 co : out std_logic ---output ); end component; signal m_inverted : std_logic_vector (3 downto 0); --signal m_inverted datatype:std_logic_vector signal nand_result : std_logic_vector (3 downto 0); --signal nand_result datatype:std_logic_vector signal nor_result : std_logic_vector (3 downto 0); --signal nor_result datatype:std_logic_vector signal adder_result : std_logic_vector (3 downto 0); --signal adder_result datatype:std_logic_vector signal adder_carry_out : std_logic; --signal adder_carry_out datatype:std_logic signal operation_type : std_logic; --signal operation_type datatype:std_logic signal sub : std_logic; --signal sub datatype:std_logic begin -- Make sense from control bits operation_type <= opcode(1); -- Are we doing addition/NAND or subtraction/NOR? sub <= opcode(0); -- Are we doing addition/NAND or subtraction/NOR? -- Here we calculate inverted bits for subtraction if necessary m_inverted(0) <= not m(0); m_inverted(1) <= not m(1); m_inverted(2) <= not m(2); m_inverted(3) <= not m(3); -- Addition ------------ some bugs ---------------------- adder_instance: carry_ripple_adder port map( a => n, --a : in std_logic_vector (3 downto 0); --variable "a" input std_logic_vector :0 to 3(0,1,2,3) --n : in std_logic_vector (3 downto 0); --variable "n" input std_logic_vector :0 to 3(0,1,2,3) if opcode="10" then b => m_inverted, --b: in std_logic_vector (3 downto 0); --variable "b" input std_logic_vector :0 to 3(0,1,2,3) elsif opcode="11" then --signal m_inverted : std_logic_vector (3 downto 0); --signal m_inverted datatype:std_logic_vector if opcode="10" then ci => '1'; ----input 1 elsif opcode="11" then ci =>'0'; ----input 0 end if; s => adder_result, --s : out std_logic_vector (3 downto 0); ---output : 0,1,2,3 --signal adder_result : std_logic_vector (3 downto 0); --signal adder_result datatype:std_logic_vector -- co => adder_carry_out ); -- Logical NAND operation ------------ some bugs------------------Operator procesure nand_result(0) <= not m(0) and n(0); nand_result(1) <= not m(1) and n(1); nand_result(2) <= not m(2) and n(2); nand_result(3) <= not m(3) and n(3); -- Logical NOR operation ------------some bugs ------------------ nor_result(0) <= not m(0) or n(0); nor_result(1) <= not m(1) or n(1); nor_result(2) <= not m(2) or n(2); nor_result(3) <= not m(3) or n(3); -- Select output based on which operation was requested d <= nand_result when opcode ="10" else nor_result when opcode ="11" else adder_result; -- Carry out bit cout <= (adder_carry_out xor sub) when operation_type = '0' else '0'; end;

mit

d50b6d3c2887c0a60eead0bb4dc51161

alpenwasser/pitaya

firmware/fpga/p_FIR_sim/FIR_sim/FIR_sim.srcs/sources_1/bd/design_1/ip/design_1_cic_compiler_0_1/synth/design_1_cic_compiler_0_1.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:cic_compiler:4.0 -- IP Revision: 10 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY cic_compiler_v4_0_10; USE cic_compiler_v4_0_10.cic_compiler_v4_0_10; ENTITY design_1_cic_compiler_0_1 IS PORT ( aclk : IN STD_LOGIC; s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s_axis_data_tvalid : IN STD_LOGIC; s_axis_data_tready : OUT STD_LOGIC; m_axis_data_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC ); END design_1_cic_compiler_0_1; ARCHITECTURE design_1_cic_compiler_0_1_arch OF design_1_cic_compiler_0_1 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_cic_compiler_0_1_arch: ARCHITECTURE IS "yes"; COMPONENT cic_compiler_v4_0_10 IS GENERIC ( C_COMPONENT_NAME : STRING; C_FILTER_TYPE : INTEGER; C_NUM_STAGES : INTEGER; C_DIFF_DELAY : INTEGER; C_RATE : INTEGER; C_INPUT_WIDTH : INTEGER; C_OUTPUT_WIDTH : INTEGER; C_USE_DSP : INTEGER; C_HAS_ROUNDING : INTEGER; C_NUM_CHANNELS : INTEGER; C_RATE_TYPE : INTEGER; C_MIN_RATE : INTEGER; C_MAX_RATE : INTEGER; C_SAMPLE_FREQ : INTEGER; C_CLK_FREQ : INTEGER; C_USE_STREAMING_INTERFACE : INTEGER; C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_C1 : INTEGER; C_C2 : INTEGER; C_C3 : INTEGER; C_C4 : INTEGER; C_C5 : INTEGER; C_C6 : INTEGER; C_I1 : INTEGER; C_I2 : INTEGER; C_I3 : INTEGER; C_I4 : INTEGER; C_I5 : INTEGER; C_I6 : INTEGER; C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER; C_S_AXIS_DATA_TDATA_WIDTH : INTEGER; C_M_AXIS_DATA_TDATA_WIDTH : INTEGER; C_M_AXIS_DATA_TUSER_WIDTH : INTEGER; C_HAS_DOUT_TREADY : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_config_tvalid : IN STD_LOGIC; s_axis_config_tready : OUT STD_LOGIC; s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s_axis_data_tvalid : IN STD_LOGIC; s_axis_data_tready : OUT STD_LOGIC; s_axis_data_tlast : IN STD_LOGIC; m_axis_data_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tready : IN STD_LOGIC; m_axis_data_tlast : OUT STD_LOGIC; event_tlast_unexpected : OUT STD_LOGIC; event_tlast_missing : OUT STD_LOGIC; event_halted : OUT STD_LOGIC ); END COMPONENT cic_compiler_v4_0_10; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF design_1_cic_compiler_0_1_arch: ARCHITECTURE IS "cic_compiler_v4_0_10,Vivado 2016.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_cic_compiler_0_1_arch : ARCHITECTURE IS "design_1_cic_compiler_0_1,cic_compiler_v4_0_10,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF design_1_cic_compiler_0_1_arch: ARCHITECTURE IS "design_1_cic_compiler_0_1,cic_compiler_v4_0_10,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=cic_compiler,x_ipVersion=4.0,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMPONENT_NAME=design_1_cic_compiler_0_1,C_FILTER_TYPE=1,C_NUM_STAGES=4,C_DIFF_DELAY=1,C_RATE=125,C_INPUT_WIDTH=16,C_OUTPUT_WIDTH=44,C_USE_DSP=1,C_HAS_ROUNDING=0,C_NUM_CHANNELS=1,C_RATE_TYPE=0,C_MIN_RATE=125,C_MAX_RATE=125,C_SAMPLE_FREQ=1,C_CLK_FREQ=1,C_USE_STREAMING_INTERFACE=1,C_FAMI" & "LY=zynq,C_XDEVICEFAMILY=zynq,C_C1=44,C_C2=44,C_C3=44,C_C4=44,C_C5=0,C_C6=0,C_I1=44,C_I2=44,C_I3=44,C_I4=44,C_I5=0,C_I6=0,C_S_AXIS_CONFIG_TDATA_WIDTH=1,C_S_AXIS_DATA_TDATA_WIDTH=16,C_M_AXIS_DATA_TDATA_WIDTH=48,C_M_AXIS_DATA_TUSER_WIDTH=1,C_HAS_DOUT_TREADY=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID"; BEGIN U0 : cic_compiler_v4_0_10 GENERIC MAP ( C_COMPONENT_NAME => "design_1_cic_compiler_0_1", C_FILTER_TYPE => 1, C_NUM_STAGES => 4, C_DIFF_DELAY => 1, C_RATE => 125, C_INPUT_WIDTH => 16, C_OUTPUT_WIDTH => 44, C_USE_DSP => 1, C_HAS_ROUNDING => 0, C_NUM_CHANNELS => 1, C_RATE_TYPE => 0, C_MIN_RATE => 125, C_MAX_RATE => 125, C_SAMPLE_FREQ => 1, C_CLK_FREQ => 1, C_USE_STREAMING_INTERFACE => 1, C_FAMILY => "zynq", C_XDEVICEFAMILY => "zynq", C_C1 => 44, C_C2 => 44, C_C3 => 44, C_C4 => 44, C_C5 => 0, C_C6 => 0, C_I1 => 44, C_I2 => 44, C_I3 => 44, C_I4 => 44, C_I5 => 0, C_I6 => 0, C_S_AXIS_CONFIG_TDATA_WIDTH => 1, C_S_AXIS_DATA_TDATA_WIDTH => 16, C_M_AXIS_DATA_TDATA_WIDTH => 48, C_M_AXIS_DATA_TUSER_WIDTH => 1, C_HAS_DOUT_TREADY => 0, C_HAS_ACLKEN => 0, C_HAS_ARESETN => 0 ) PORT MAP ( aclk => aclk, aclken => '1', aresetn => '1', s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_config_tvalid => '0', s_axis_data_tdata => s_axis_data_tdata, s_axis_data_tvalid => s_axis_data_tvalid, s_axis_data_tready => s_axis_data_tready, s_axis_data_tlast => '0', m_axis_data_tdata => m_axis_data_tdata, m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tready => '0' ); END design_1_cic_compiler_0_1_arch;

mit

e030cc3b3eacebbcabb73ba517fa8c2d

stefanct/aua

hw/io/sc_uart/src/sc_uart.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.aua_types.all; entity sc_uart is generic( clk_freq : integer; baud_rate : integer; txf_depth : integer; txf_thres : integer; rxf_depth : integer; rxf_thres : integer ); port ( clk : in std_logic; reset : in std_logic; -- SimpCon slave interface to IO ctrl address : in sc_addr_t; wr_data : in sc_data_t; rd : in std_logic; wr : in std_logic; rd_data : out sc_data_t; rdy_cnt : out sc_rdy_cnt_t; -- pins txd : out std_logic; rxd : in std_logic; ncts : in std_logic; nrts : out std_logic ); end sc_uart; architecture rtl of sc_uart is component fifo is generic (width : integer; depth : integer; thres : integer); port ( clk : in std_logic; reset : in std_logic; din : in std_logic_vector(width-1 downto 0); dout : out std_logic_vector(width-1 downto 0); rd : in std_logic; wr : in std_logic; empty : out std_logic; full : out std_logic; half : out std_logic ); end component; -- -- signals for uart connection -- signal ua_dout : std_logic_vector(7 downto 0); signal ua_wr, tdre : std_logic; signal ua_rd, rdrf : std_logic; type uart_tx_state_type is (s0, s1); signal uart_tx_state : uart_tx_state_type; signal tf_dout : std_logic_vector(7 downto 0); -- fifo out signal tf_rd : std_logic; signal tf_empty : std_logic; signal tf_full : std_logic; --~ signal tf_half : std_logic; signal ncts_buf : std_logic_vector(2 downto 0); -- sync in signal tsr : std_logic_vector(9 downto 0); -- tx shift register signal tx_clk : std_logic; type uart_rx_state_type is (s0, s1, s2); signal uart_rx_state : uart_rx_state_type; signal rf_wr : std_logic; signal rf_empty : std_logic; signal rf_full : std_logic; signal rf_half : std_logic; signal rxd_reg : std_logic_vector(2 downto 0); signal rx_buf : std_logic_vector(2 downto 0); -- sync in, filter signal rx_d : std_logic; -- rx serial data signal rsr : std_logic_vector(9 downto 0); -- rx shift register signal rx_clk : std_logic; signal rx_clk_ena : std_logic; constant clk16_cnt : integer := (clk_freq/baud_rate+8)/16-1; begin --rdy_cnt <= "00"; -- no wait states --rd_data(31 downto 8) <= std_logic_vector(to_unsigned(0, 24)); ---- ---- The registered MUX is all we need for a SimpCon read. ---- The read data is stored in registered rd_data. ---- --process(clk, reset) --begin --if (reset='1') then --rd_data(7 downto 0) <= (others => '0'); --elsif rising_edge(clk) then --ua_rd <= '0'; --rd_data(7 downto 0) <= (others => '0'); --if sc_base_addr(addr_bits-1 downto 1) = address(addr_bits-1 downto 1) then --if rd='1' then ---- that's our very simple address decoder --if address(0)='0' then --rd_data(7 downto 0) <= "000000" & rdrf & tdre; -- drf/e == rcv/transmit data reg full/empty --else --rd_data(7 downto 0) <= ua_dout; --ua_rd <= rd; --end if; --end if; --ua_wr <= wr and address(0); -- does this work in synced process? --end if; --end if; --end process; rdy_cnt <= "00"; -- no wait states rd_data(31 downto 8) <= std_logic_vector(to_unsigned(0, 24)); -- -- The registered MUX is all we need for a SimpCon read. -- The read data is stored in registered rd_data. -- sc: process(clk, reset) begin if (reset='1') then rd_data(7 downto 0) <= (others => '0'); elsif rising_edge(clk) then ua_rd <= '0'; if rd='1' then -- that's our very simple address decoder if address(0)='0' then rd_data(7 downto 0) <= "000000" & rdrf & tdre; else rd_data(7 downto 0) <= ua_dout; ua_rd <= rd; end if; end if; end if; end process; -- write is on address offest 1 ua_wr <= wr and address(0); -- serial clock -- process(clk, reset) variable clk16 : integer range 0 to clk16_cnt; variable clktx : unsigned(3 downto 0); variable clkrx : unsigned(3 downto 0); begin if (reset='1') then clk16 := 0; clktx := "0000"; clkrx := "0000"; tx_clk <= '0'; rx_clk <= '0'; rx_buf <= "111"; elsif rising_edge(clk) then rxd_reg(0) <= rxd; -- to avoid setup timing error in Quartus rxd_reg(1) <= rxd_reg(0); rxd_reg(2) <= rxd_reg(1); if (clk16=clk16_cnt) then -- 16 x serial clock clk16 := 0; -- -- tx clock -- clktx := clktx + 1; if (clktx="0000") then tx_clk <= '1'; else tx_clk <= '0'; end if; -- -- rx clock -- if (rx_clk_ena='1') then clkrx := clkrx + 1; if (clkrx="1000") then rx_clk <= '1'; else rx_clk <= '0'; end if; else clkrx := "0000"; end if; -- -- sync in filter buffer -- rx_buf(0) <= rxd_reg(2); rx_buf(2 downto 1) <= rx_buf(1 downto 0); else clk16 := clk16 + 1; tx_clk <= '0'; rx_clk <= '0'; end if; end if; end process; -- -- transmit fifo -- cmp_tf: fifo generic map (8, txf_depth, txf_thres) port map (clk, reset, wr_data(7 downto 0), tf_dout, tf_rd, ua_wr, tf_empty, tf_full, open);--tf_half); -- -- state machine for actual shift out -- process(clk, reset) variable i : integer range 0 to 11; begin if (reset='1') then uart_tx_state <= s0; tsr <= "1111111111"; tf_rd <= '0'; ncts_buf <= "111"; elsif rising_edge(clk) then ncts_buf(0) <= ncts; ncts_buf(2 downto 1) <= ncts_buf(1 downto 0); case uart_tx_state is when s0 => i := 0; if (tf_empty='0' and ncts_buf(2)='0') then uart_tx_state <= s1; tsr <= tf_dout & '0' & '1'; tf_rd <= '1'; end if; when s1 => tf_rd <= '0'; if (tx_clk='1') then tsr(9) <= '1'; tsr(8 downto 0) <= tsr(9 downto 1); i := i+1; if (i=11) then -- two stop bits uart_tx_state <= s0; end if; end if; end case; end if; end process; txd <= tsr(0); tdre <= not tf_full; -- -- receive fifo -- cmp_rf: fifo generic map (8, rxf_depth, rxf_thres) port map (clk, reset, rsr(8 downto 1), ua_dout, ua_rd, rf_wr, rf_empty, rf_full, rf_half); rdrf <= not rf_empty; nrts <= rf_half; -- glitches even on empty fifo! -- -- filter rxd -- with rx_buf select rx_d <= '0' when "000", '0' when "001", '0' when "010", '1' when "011", '0' when "100", '1' when "101", '1' when "110", '1' when "111", 'X' when others; -- -- state machine for actual shift in -- process(clk, reset) variable i : integer range 0 to 10; begin if (reset='1') then uart_rx_state <= s0; rsr <= "0000000000"; rf_wr <= '0'; rx_clk_ena <= '0'; elsif rising_edge(clk) then case uart_rx_state is when s0 => i := 0; rf_wr <= '0'; if (rx_d='0') then rx_clk_ena <= '1'; uart_rx_state <= s1; else rx_clk_ena <= '0'; end if; when s1 => if (rx_clk='1') then rsr(9) <= rx_d; rsr(8 downto 0) <= rsr(9 downto 1); i := i+1; if (i=10) then uart_rx_state <= s2; end if; end if; when s2 => rx_clk_ena <= '0'; if rsr(0)='0' and rsr(9)='1' then if rf_full='0' then -- if full just drop it rf_wr <= '1'; end if; end if; uart_rx_state <= s0; end case; end if; end process; end rtl;

gpl-3.0

0fe4500013e372d2d75100e3e0eca50e

MiddleMan5/233

Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_slice_12_3_0/sim/RAT_slice_12_3_0.vhd

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:xlslice:1.0 -- IP Revision: 0 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY work; USE work.xlslice; ENTITY RAT_slice_12_3_0 IS PORT ( Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); Dout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END RAT_slice_12_3_0; ARCHITECTURE RAT_slice_12_3_0_arch OF RAT_slice_12_3_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_12_3_0_arch: ARCHITECTURE IS "yes"; COMPONENT xlslice IS GENERIC ( DIN_WIDTH : INTEGER; DIN_FROM : INTEGER; DIN_TO : INTEGER ); PORT ( Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0); Dout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END COMPONENT xlslice; BEGIN U0 : xlslice GENERIC MAP ( DIN_WIDTH => 18, DIN_FROM => 17, DIN_TO => 13 ) PORT MAP ( Din => Din, Dout => Dout ); END RAT_slice_12_3_0_arch;

mit

be54487f4d09077cfc85bda36e9c15ca

MiddleMan5/233

Experiments/RTL_Components/CPE233-master/counter.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity counter is Port ( FROM_IMMED : in STD_LOGIC_VECTOR (9 downto 0); FROM_STACK : in STD_LOGIC_VECTOR (9 downto 0); INTERRUPT : in STD_LOGIC_VECTOR (9 downto 0); PC_MUX_SEL : in STD_LOGIC_VECTOR (1 downto 0); PC_OE : in STD_LOGIC; PC_LD : in STD_LOGIC; PC_INC : in STD_LOGIC; RST : in STD_LOGIC; CLK : in STD_LOGIC; PC_COUNT : out STD_LOGIC_VECTOR (9 downto 0); PC_TRI : out STD_LOGIC_VECTOR (9 downto 0)); end counter; architecture Behavioral of counter is component programCounter is Port ( D_IN : in STD_LOGIC_VECTOR (9 downto 0); PC_OE : in STD_LOGIC; PC_LD : in STD_LOGIC; PC_INC : in STD_LOGIC; RST : in STD_LOGIC; CLK : in STD_LOGIC; PC_COUNT : out STD_LOGIC_VECTOR (9 downto 0); PC_TRI : out STD_LOGIC_VECTOR (9 downto 0)); end component; signal D_IN : STD_LOGIC_VECTOR (9 downto 0) := "0000000000"; begin D_IN <= FROM_IMMED when PC_MUX_SEL = "00" else FROM_STACK when PC_MUX_SEL = "01" else INTERRUPT when PC_MUX_SEL = "10" else (others => '0'); counter : programCounter port map (D_IN, PC_OE, PC_LD, PC_INC, RST, CLK, PC_COUNT, PC_TRI); end Behavioral;

mit

3258b4b2f0124e795e66763383b89ff7

MiddleMan5/233

Experiments/Experiment8-GeterDone/RTL/FlagReg.vhd.vhd

-- -- A flip-flop to store the the zero, carry, and interrupt flags. -- To be used in the RAT CPU. -- -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FlagReg is Port ( IN_FLAG : in STD_LOGIC; --flag input LD : in STD_LOGIC; --load the out_flag with the in_flag value SET : in STD_LOGIC; --set the flag to '1' CLR : in STD_LOGIC; --clear the flag to '0' CLK : in STD_LOGIC; --system clock OUT_FLAG : out STD_LOGIC); --flag output end FlagReg; architecture Behavioral of FlagReg is begin process(CLK) begin if( rising_edge(CLK) ) then if( LD = '1' ) then OUT_FLAG <= IN_FLAG; elsif( SET = '1' ) then OUT_FLAG <= '1'; elsif( CLR = '1' ) then OUT_FLAG <= '0'; end if; end if; end process; end Behavioral;

mit

a2dd0a92b2e5f3046550f68b56241b41

VLSI-EDA/PoC-Examples

src/cache/cachetest_Atlys.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================= -- Authors: Martin Zabel -- -- Module: Test cache_mem on Digilent Atlys board. -- -- Description: -- ------------------------------------ -- Test cache_mem on Digilent Atlys board using the Xilinx Memory Controller -- (MIG). -- -- The user clock of the MIG core must be configured to 85 MHz by setting -- the parameter C3_CLKOUT2_DIVIDE to 7. At the moment, this can be achieved -- only by editing lib/PoC/py/config.entity.ini: -- -- 1. Go to section [XST.xil.mig.Atlys_1x128.nl] -- 2. Add the following line to the end of this section:: -- -- HDLParameters = C3_CLKOUT2_DIVIDE=7 -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library poc; use poc.utils.all; entity cachetest_Atlys is generic ( C3_SIMULATION : string := "FALSE"); port ( Atlys_SystemClock_100MHz : in std_logic; Atlys_GPIO_LED : out std_logic_vector(7 downto 0); -- Memory Controller Bank 3 mcb3_dram_dq : inout std_logic_vector(16-1 downto 0); mcb3_dram_a : out std_logic_vector(13-1 downto 0); mcb3_dram_ba : out std_logic_vector(3-1 downto 0); mcb3_dram_ras_n : out std_logic; mcb3_dram_cas_n : out std_logic; mcb3_dram_we_n : out std_logic; mcb3_dram_odt : out std_logic; mcb3_dram_cke : out std_logic; mcb3_dram_dm : out std_logic; mcb3_dram_udqs : inout std_logic; mcb3_dram_udqs_n : inout std_logic; mcb3_rzq : inout std_logic; mcb3_dram_udm : out std_logic; mcb3_dram_dqs : inout std_logic; mcb3_dram_dqs_n : inout std_logic; mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic); end entity cachetest_Atlys; architecture rtl of cachetest_Atlys is signal memtest0_status : std_logic_vector(2 downto 0); -- Memory Controller signals -- signal c3_sys_rst_i : std_logic; signal c3_calib_done : std_logic; signal c3_clk0 : std_logic; -- output from IP core signal c3_rst0 : std_logic; -- output from IP core, asynchronously asserted! -- signal c3_p0_cmd_clk : std_logic; signal c3_p0_cmd_en : std_logic; signal c3_p0_cmd_instr : std_logic_vector(2 downto 0); signal c3_p0_cmd_bl : std_logic_vector(5 downto 0); signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0); signal c3_p0_cmd_empty : std_logic; signal c3_p0_cmd_full : std_logic; -- signal c3_p0_wr_clk : std_logic; signal c3_p0_wr_en : std_logic; signal c3_p0_wr_mask : std_logic_vector(16-1 downto 0); signal c3_p0_wr_data : std_logic_vector(128-1 downto 0); signal c3_p0_wr_full : std_logic; signal c3_p0_wr_empty : std_logic; signal c3_p0_wr_count : std_logic_vector(6 downto 0); signal c3_p0_wr_underrun : std_logic; signal c3_p0_wr_error : std_logic; -- signal c3_p0_rd_clk : std_logic; signal c3_p0_rd_en : std_logic; signal c3_p0_rd_data : std_logic_vector(128-1 downto 0); signal c3_p0_rd_full : std_logic; signal c3_p0_rd_empty : std_logic; signal c3_p0_rd_count : std_logic_vector(6 downto 0); signal c3_p0_rd_overflow : std_logic; signal c3_p0_rd_error : std_logic; begin -- architecture rtl ----------------------------------------------------------------------------- -- MemoryTester for Port 0 ----------------------------------------------------------------------------- MemoryTester0 : block constant MEM_BYTE_ADDR_BITS : natural := 4; -- 16 Byte / Word constant MEM_WORD_ADDR_BITS : natural := ite(SIMULATION, 15, -- 32 KByte = 2 rows 27) -- 128 MB = 1 GBit -MEM_BYTE_ADDR_BITS; constant MEM_DATA_BITS : positive := 128; -- fixed value constant CPU_DATA_BITS : positive := 32; -- supported values: 8, 16, 32, 64, 128 constant CPU_ADDR_BITS : positive := log2ceil(MEM_DATA_BITS/CPU_DATA_BITS)+MEM_WORD_ADDR_BITS; signal cpu_rdy : std_logic; signal cpu_req : std_logic; signal cpu_write : std_logic; signal cpu_addr : unsigned(CPU_ADDR_BITS-1 downto 0); signal cpu_wdata : std_logic_vector(CPU_DATA_BITS-1 downto 0); signal cpu_rstb : std_logic; signal cpu_rdata : std_logic_vector(CPU_DATA_BITS-1 downto 0); signal mem_rdy : std_logic; signal mem_req : std_logic; signal mem_write : std_logic; signal mem_addr : unsigned(MEM_WORD_ADDR_BITS-1 downto 0); signal mem_wdata : std_logic_vector(MEM_DATA_BITS-1 downto 0); signal mem_wmask : std_logic_vector(MEM_DATA_BITS/8-1 downto 0); signal mem_rstb : std_logic; signal mem_rdata : std_logic_vector(MEM_DATA_BITS-1 downto 0); begin -- block MemoryTester0 fsm: entity work.memtest_fsm generic map ( A_BITS => CPU_ADDR_BITS, D_BITS => CPU_DATA_BITS) port map ( clk => c3_clk0, rst => c3_rst0, mem_rdy => cpu_rdy, mem_rstb => cpu_rstb, mem_rdata => cpu_rdata, mem_req => cpu_req, mem_write => cpu_write, mem_addr => cpu_addr, mem_wdata => cpu_wdata, status => memtest0_status); cache: entity poc.cache_mem generic map ( REPLACEMENT_POLICY => "LRU", CACHE_LINES => 512, -- 8 KiB cache / 128 bit per cache line ASSOCIATIVITY => 1, CPU_DATA_BITS => CPU_DATA_BITS, MEM_ADDR_BITS => MEM_WORD_ADDR_BITS, MEM_DATA_BITS => MEM_DATA_BITS, OUTSTANDING_REQ => 2) port map ( clk => c3_clk0, rst => c3_rst0, cpu_req => cpu_req, cpu_write => cpu_write, cpu_addr => cpu_addr, cpu_wdata => cpu_wdata, cpu_rdy => cpu_rdy, cpu_rstb => cpu_rstb, cpu_rdata => cpu_rdata, mem_req => mem_req, mem_write => mem_write, mem_addr => mem_addr, mem_wdata => mem_wdata, mem_wmask => mem_wmask, mem_rdy => mem_rdy, mem_rstb => mem_rstb, mem_rdata => mem_rdata); adapter: entity poc.ddr2_mem2mig_adapter_Spartan6 generic map ( D_BITS => MEM_DATA_BITS, MEM_A_BITS => MEM_WORD_ADDR_BITS, APP_A_BITS => c3_p0_cmd_byte_addr'length) port map ( mem_req => mem_req, mem_write => mem_write, mem_addr => mem_addr, mem_wdata => mem_wdata, mem_wmask => mem_wmask, mem_rdy => mem_rdy, mem_rstb => mem_rstb, mem_rdata => mem_rdata, mig_calib_done => c3_calib_done, mig_cmd_full => c3_p0_cmd_full, mig_wr_full => c3_p0_wr_full, mig_rd_empty => c3_p0_rd_empty, mig_rd_data => c3_p0_rd_data, mig_cmd_instr => c3_p0_cmd_instr, mig_cmd_en => c3_p0_cmd_en, mig_cmd_bl => c3_p0_cmd_bl, mig_cmd_byte_addr => c3_p0_cmd_byte_addr, mig_wr_data => c3_p0_wr_data, mig_wr_mask => c3_p0_wr_mask, mig_wr_en => c3_p0_wr_en, mig_rd_en => c3_p0_rd_en); end block MemoryTester0; ----------------------------------------------------------------------------- -- Memory Controller Instantiation ----------------------------------------------------------------------------- mig : entity poc.mig_Atlys_1x128 port map ( mcb3_dram_dq => mcb3_dram_dq, mcb3_dram_a => mcb3_dram_a, mcb3_dram_ba => mcb3_dram_ba, mcb3_dram_ras_n => mcb3_dram_ras_n, mcb3_dram_cas_n => mcb3_dram_cas_n, mcb3_dram_we_n => mcb3_dram_we_n, mcb3_dram_odt => mcb3_dram_odt, mcb3_dram_cke => mcb3_dram_cke, mcb3_dram_dm => mcb3_dram_dm, mcb3_dram_udqs => mcb3_dram_udqs, mcb3_dram_udqs_n => mcb3_dram_udqs_n, mcb3_rzq => mcb3_rzq, mcb3_dram_udm => mcb3_dram_udm, c3_sys_clk => Atlys_SystemClock_100MHz, c3_sys_rst_i => '0', -- active high c3_calib_done => c3_calib_done, c3_clk0 => c3_clk0, c3_rst0 => c3_rst0, mcb3_dram_dqs => mcb3_dram_dqs, mcb3_dram_dqs_n => mcb3_dram_dqs_n, mcb3_dram_ck => mcb3_dram_ck, mcb3_dram_ck_n => mcb3_dram_ck_n, c3_p0_cmd_clk => c3_clk0, c3_p0_cmd_en => c3_p0_cmd_en, c3_p0_cmd_instr => c3_p0_cmd_instr, c3_p0_cmd_bl => c3_p0_cmd_bl, c3_p0_cmd_byte_addr => c3_p0_cmd_byte_addr, c3_p0_cmd_empty => c3_p0_cmd_empty, c3_p0_cmd_full => c3_p0_cmd_full, c3_p0_wr_clk => c3_clk0, c3_p0_wr_en => c3_p0_wr_en, c3_p0_wr_mask => c3_p0_wr_mask, c3_p0_wr_data => c3_p0_wr_data, c3_p0_wr_full => c3_p0_wr_full, c3_p0_wr_empty => c3_p0_wr_empty, c3_p0_wr_count => c3_p0_wr_count, c3_p0_wr_underrun => c3_p0_wr_underrun, c3_p0_wr_error => c3_p0_wr_error, c3_p0_rd_clk => c3_clk0, c3_p0_rd_en => c3_p0_rd_en, c3_p0_rd_data => c3_p0_rd_data, c3_p0_rd_full => c3_p0_rd_full, c3_p0_rd_empty => c3_p0_rd_empty, c3_p0_rd_count => c3_p0_rd_count, c3_p0_rd_overflow => c3_p0_rd_overflow, c3_p0_rd_error => c3_p0_rd_error); ----------------------------------------------------------------------------- -- Status outputs ----------------------------------------------------------------------------- Atlys_GPIO_LED(7) <= c3_rst0; Atlys_GPIO_LED(6) <= '0'; Atlys_GPIO_LED(5) <= '0'; Atlys_GPIO_LED(4) <= '0'; Atlys_GPIO_LED(3) <= c3_calib_done; Atlys_GPIO_LED(2 downto 0) <= memtest0_status; end architecture rtl;

apache-2.0

32cdbb0a84d96b7470c60551cc264c28

MiddleMan5/233

Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_prog_rom_0_0/RAT_prog_rom_0_0_sim_netlist.vhdl

-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 -- Date : Thu Oct 26 22:45:02 2017 -- Host : Juice-Laptop running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_prog_rom_0_0/RAT_prog_rom_0_0_sim_netlist.vhdl -- Design : RAT_prog_rom_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7a35tcpg236-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity RAT_prog_rom_0_0_prog_rom is port ( INSTRUCTION : out STD_LOGIC_VECTOR ( 17 downto 0 ); CLK : in STD_LOGIC; ADDRESS : in STD_LOGIC_VECTOR ( 9 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of RAT_prog_rom_0_0_prog_rom : entity is "prog_rom"; end RAT_prog_rom_0_0_prog_rom; architecture STRUCTURE of RAT_prog_rom_0_0_prog_rom is signal NLW_ram_1024_x_18_DIBDI_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_ram_1024_x_18_DIPBDIP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_ram_1024_x_18_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_ram_1024_x_18_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of ram_1024_x_18 : label is "INDEPENDENT"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of ram_1024_x_18 : label is "RAMB16_S18"; attribute XILINX_TRANSFORM_PINMAP : string; attribute XILINX_TRANSFORM_PINMAP of ram_1024_x_18 : label is "ADDR[0]:ADDRARDADDR[4] ADDR[1]:ADDRARDADDR[5] ADDR[2]:ADDRARDADDR[6] ADDR[3]:ADDRARDADDR[7] ADDR[4]:ADDRARDADDR[8] ADDR[5]:ADDRARDADDR[9] ADDR[6]:ADDRARDADDR[10] ADDR[7]:ADDRARDADDR[11] ADDR[8]:ADDRARDADDR[12] ADDR[9]:ADDRARDADDR[13] CLK:CLKARDCLK DI[0]:DIADI[0] DI[10]:DIADI[10] DI[11]:DIADI[11] DI[12]:DIADI[12] DI[13]:DIADI[13] DI[14]:DIADI[14] DI[15]:DIADI[15] DI[1]:DIADI[1] DI[2]:DIADI[2] DI[3]:DIADI[3] DI[4]:DIADI[4] DI[5]:DIADI[5] DI[6]:DIADI[6] DI[7]:DIADI[7] DI[8]:DIADI[8] DI[9]:DIADI[9] DIP[0]:DIPADIP[0] DIP[1]:DIPADIP[1] DO[0]:DOADO[0] DO[10]:DOADO[10] DO[11]:DOADO[11] DO[12]:DOADO[12] DO[13]:DOADO[13] DO[14]:DOADO[14] DO[15]:DOADO[15] DO[1]:DOADO[1] DO[2]:DOADO[2] DO[3]:DOADO[3] DO[4]:DOADO[4] DO[5]:DOADO[5] DO[6]:DOADO[6] DO[7]:DOADO[7] DO[8]:DOADO[8] DO[9]:DOADO[9] DOP[0]:DOPADOP[0] DOP[1]:DOPADOP[1] EN:ENARDEN SSR:RSTRAMARSTRAM WE:WEA[1],WEA[0]"; attribute box_type : string; attribute box_type of ram_1024_x_18 : label is "PRIMITIVE"; begin ram_1024_x_18: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 0, DOB_REG => 0, INITP_00 => X"000000000000000000000000000000000000000000000000000000CF00000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000080804A400A5A6BFF2A20", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"00000", INIT_B => X"00000", READ_WIDTH_A => 18, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_WIDTH_A => 18 ) port map ( ADDRARDADDR(13 downto 4) => ADDRESS(9 downto 0), ADDRARDADDR(3 downto 0) => B"1111", ADDRBWRADDR(13 downto 0) => B"11111111111111", CLKARDCLK => CLK, CLKBWRCLK => '0', DIADI(15 downto 0) => B"0000000000000000", DIBDI(15 downto 0) => NLW_ram_1024_x_18_DIBDI_UNCONNECTED(15 downto 0), DIPADIP(1 downto 0) => B"00", DIPBDIP(1 downto 0) => NLW_ram_1024_x_18_DIPBDIP_UNCONNECTED(1 downto 0), DOADO(15 downto 0) => INSTRUCTION(15 downto 0), DOBDO(15 downto 0) => NLW_ram_1024_x_18_DOBDO_UNCONNECTED(15 downto 0), DOPADOP(1 downto 0) => INSTRUCTION(17 downto 16), DOPBDOP(1 downto 0) => NLW_ram_1024_x_18_DOPBDOP_UNCONNECTED(1 downto 0), ENARDEN => '1', ENBWREN => '0', REGCEAREGCE => '0', REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1 downto 0) => B"00", WEBWE(3 downto 0) => B"0000" ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity RAT_prog_rom_0_0 is port ( ADDRESS : in STD_LOGIC_VECTOR ( 9 downto 0 ); INSTRUCTION : out STD_LOGIC_VECTOR ( 17 downto 0 ); CLK : in STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of RAT_prog_rom_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of RAT_prog_rom_0_0 : entity is "RAT_prog_rom_0_0,prog_rom,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of RAT_prog_rom_0_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of RAT_prog_rom_0_0 : entity is "prog_rom,Vivado 2016.4"; end RAT_prog_rom_0_0; architecture STRUCTURE of RAT_prog_rom_0_0 is begin U0: entity work.RAT_prog_rom_0_0_prog_rom port map ( ADDRESS(9 downto 0) => ADDRESS(9 downto 0), CLK => CLK, INSTRUCTION(17 downto 0) => INSTRUCTION(17 downto 0) ); end STRUCTURE;

mit

b622b555d0e93a175b6f2d5239168180

BBN-Q/VHDL-Components

src/UpCounter.vhd

---- -- Original author: Blake Johnson -- Copyright 2015,2016 Raytheon BBN Technologies -- -- A basic up counter. ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity UpCounter is generic ( nbits : integer := 8 ); port ( clk : in std_logic; rst : in std_logic; en : in std_logic; load_value : in std_logic_vector(nbits-1 downto 0); load : in std_logic; Q : out std_logic_vector(nbits-1 downto 0) ); end UpCounter; architecture arch of UpCounter is signal value : std_logic_vector(nbits-1 downto 0) := (others => '0'); begin Q <= value; main : process ( clk ) begin if rising_edge(clk) then if rst = '1' then value <= (others => '0'); else if load = '1' then value <= load_value; elsif en = '1' then value <= std_logic_vector(unsigned(value) + 1); end if; end if; end if; end process; end arch;

mpl-2.0

ed4884aa5663f981e89a4acc17642697