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Prob101_circuit4 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- input d
- output q
The module should implement a combinational circuit. Read the simulation
waveforms to determine what the circuit does, then implement it.
time a b c d q
0ns 0 0 0 0 0
5ns 0 0 0 0 0
10ns 0 0 0 0 0
15ns 0 0 0 0 0
20ns 0 0 0 1 0
25ns 0 0 1 0 1
30ns 0 0 1 1 1
35ns 0 1 0 0 1
40ns 0 1 0 1 1
45ns 0 1 1 0 1
50ns 0 1 1 1 1
55ns 1 0 0 0 0
60ns 1 0 0 1 0
65ns 1 0 1 0 1
70ns 1 0 1 1 1
75ns 1 1 0 0 1
80ns 1 1 0 1 1
85ns 1 1 1 0 1
90ns 1 1 1 1 1
|
module RefModule (
input a,
input b,
input c,
input d,
output q
);
assign q = c | b;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b,c,d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a,b,c,d} <= 0;
@(negedge clk) wavedrom_start("Unknown circuit");
@(posedge clk) {a,b,c,d} <= 0;
repeat(18) @(posedge clk, negedge clk) {a,b,c,d} <= {a,b,c,d} + 1;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,c,d} <= $urandom;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic c;
logic d;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d );
RefModule good1 (
.a,
.b,
.c,
.d,
.q(q_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.d,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob102_circuit3 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- input d
- output q
The module should implement a combinational circuit. Read the simulation
waveforms to determine what the circuit does, then implement it.
time a b c d q
0ns 0 0 0 0 0
5ns 0 0 0 0 0
10ns 0 0 0 0 0
15ns 0 0 0 0 0
20ns 0 0 0 1 0
25ns 0 0 1 0 0
30ns 0 0 1 1 0
35ns 0 1 0 0 0
40ns 0 1 0 1 1
45ns 0 1 1 0 1
50ns 0 1 1 1 1
55ns 1 0 0 0 0
60ns 1 0 0 1 1
65ns 1 0 1 0 1
70ns 1 0 1 1 1
75ns 1 1 0 0 0
80ns 1 1 0 1 1
85ns 1 1 1 0 1
90ns 1 1 1 1 1
|
module RefModule (
input a,
input b,
input c,
input d,
output q
);
assign q = (a|b) & (c|d);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b,c,d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a,b,c,d} <= 0;
@(negedge clk) wavedrom_start("Unknown circuit");
@(posedge clk) {a,b,c,d} <= 0;
repeat(18) @(posedge clk, negedge clk) {a,b,c,d} <= {a,b,c,d} + 1;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,c,d} <= $urandom;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic c;
logic d;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d );
RefModule good1 (
.a,
.b,
.c,
.d,
.q(q_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.d,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob103_circuit2 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- input d
- output q
The module should implement a combinational circuit. Read the simulation
waveforms to determine what the circuit does, then implement it.
time a b c d q
0ns 0 0 0 0 1
5ns 0 0 0 0 1
10ns 0 0 0 0 1
15ns 0 0 0 0 1
20ns 0 0 0 1 0
25ns 0 0 1 0 0
30ns 0 0 1 1 1
35ns 0 1 0 0 0
40ns 0 1 0 1 1
45ns 0 1 1 0 1
50ns 0 1 1 1 0
55ns 1 0 0 0 0
60ns 1 0 0 1 1
65ns 1 0 1 0 1
70ns 1 0 1 1 0
75ns 1 1 0 0 1
80ns 1 1 0 1 0
85ns 1 1 1 0 0
90ns 1 1 1 1 1
|
module RefModule (
input a,
input b,
input c,
input d,
output q
);
assign q = ~a^b^c^d;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,b,c,d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a,b,c,d} <= 0;
@(negedge clk) wavedrom_start("Unknown circuit");
@(posedge clk) {a,b,c,d} <= 0;
repeat(18) @(posedge clk, negedge clk) {a,b,c,d} <= {a,b,c,d} + 1;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,c,d} <= $urandom;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic c;
logic d;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d );
RefModule good1 (
.a,
.b,
.c,
.d,
.q(q_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.d,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob104_mt2015_muxdff |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input L
- input q_in
- input r_in
- output Q
Consider this Verilog module "full_module":
module full_module (
input [2:0] r,
input L,
input clk,
output reg [2:0] q
always @(posedge clk) begin
if (L) begin
q <= r;
end else begin
q <= {q[1] ^ q[2], q[0], q[2]};
end
end
endmodule
You want to create a hierarchical Verilog design where a flipflop and 2-1
multiplexer are in a submodule named TopModule, and that submodule is
instantiated three times this code.
|
module RefModule (
input clk,
input L,
input q_in,
input r_in,
output reg Q
);
initial Q=0;
always @(posedge clk)
Q <= L ? r_in : q_in;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
/*
Midterm 2015 Question 5a. Build a flip-flop with a 2-to-1 mux before it.
*/
module stimulus_gen (
input clk,
output logic L,
output logic r_in,
output logic q_in
);
always @(posedge clk, negedge clk)
{L, r_in, q_in} <= $random % 8;
initial begin
repeat(100) @(posedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_Q;
int errortime_Q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic L;
logic q_in;
logic r_in;
logic Q_ref;
logic Q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,L,q_in,r_in,Q_ref,Q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.L,
.q_in,
.r_in );
RefModule good1 (
.clk,
.L,
.q_in,
.r_in,
.Q(Q_ref) );
TopModule top_module1 (
.clk,
.L,
.q_in,
.r_in,
.Q(Q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_Q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Q", stats1.errors_Q, stats1.errortime_Q);
else $display("Hint: Output '%s' has no mismatches.", "Q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { Q_ref } === ( { Q_ref } ^ { Q_dut } ^ { Q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (Q_ref !== ( Q_ref ^ Q_dut ^ Q_ref ))
begin if (stats1.errors_Q == 0) stats1.errortime_Q = $time;
stats1.errors_Q = stats1.errors_Q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob105_rotate100 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input load
- input ena ( 2 bits)
- input data (100 bits)
- output q (100 bits)
The module should implement a 100-bit left/right rotator, with
synchronous load and left/right enable. A rotator shifts-in the
shifted-out bit from the other end of the register, unlike a shifter that
discards the shifted-out bit and shifts in a zero. If enabled, a rotator
rotates the bits around and does not modify/discard them.
(1) load: Loads shift register with data[99:0] instead of rotating.
Synchronous active high.
(2) ena[1:0]: Synchronous. Chooses whether and which direction to
rotate:
(a) 2'b01 rotates right by one bit,
(b) 2'b10 rotates left by one bit,
(c) 2'b00 and 2'b11 do not rotate.
(3) q: The contents of the rotator.
|
module RefModule (
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q
);
always @(posedge clk) begin
if (load)
q <= data;
else if (ena == 2'h1)
q <= {q[0], q[99:1]};
else if (ena == 2'h2)
q <= {q[98:0], q[99]};
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg load,
output reg[1:0] ena,
output reg[99:0] data
);
always @(posedge clk)
data <= {$random,$random,$random,$random};
initial begin
load <= 1;
@(posedge clk);
@(posedge clk);
@(posedge clk);
repeat(4000) @(posedge clk, negedge clk) begin
load <= !($random & 31);
ena <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic load;
logic [1:0] ena;
logic [99:0] data;
logic [99:0] q_ref;
logic [99:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,ena,data,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.load,
.ena,
.data );
RefModule good1 (
.clk,
.load,
.ena,
.data,
.q(q_ref) );
TopModule top_module1 (
.clk,
.load,
.ena,
.data,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob106_always_nolatches |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input scancode (16 bits)
- output left
- output down
- output right
- output up
The module should process scancodes from a PS/2 keyboard for a game.
Given the last two bytes of scancodes received, you need to indicate
whether one of the arrow keys on the keyboard have been pressed. This
involves a fairly simple mapping, which can be implemented as a case
statement (or if-elseif) with four cases.
Scancode[15:0] | Arrow key
16'he06b | left arrow
16'he072 | down arrow
16'he074 | right arrow
16'he075 | up arrow
Anything else | none
Your circuit has one 16-bit input, and four outputs. Build this circuit
that recognizes these four scancodes and asserts the correct output.
|
module RefModule (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(*) begin
{up, left, down, right} = 0;
case (scancode)
16'he06b: left = 1;
16'he072: down = 1;
16'he074: right = 1;
16'he075: up = 1;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [15:0] scancode,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
@(negedge clk) wavedrom_start("Recognize arrow keys");
@(posedge clk) scancode <= 16'h0;
@(posedge clk) scancode <= 16'h1;
@(posedge clk) scancode <= 16'he075;
@(posedge clk) scancode <= 16'he06b;
@(posedge clk) scancode <= 16'he06c;
@(posedge clk) scancode <= 16'he072;
@(posedge clk) scancode <= 16'he074;
@(posedge clk) scancode <= 16'he076;
@(posedge clk) scancode <= 16'hffff;
@(negedge clk) wavedrom_stop();
repeat(30000) @(posedge clk, negedge clk) begin
scancode <= $urandom;
end
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_left;
int errortime_left;
int errors_down;
int errortime_down;
int errors_right;
int errortime_right;
int errors_up;
int errortime_up;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [15:0] scancode;
logic left_ref;
logic left_dut;
logic down_ref;
logic down_dut;
logic right_ref;
logic right_dut;
logic up_ref;
logic up_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,scancode,left_ref,left_dut,down_ref,down_dut,right_ref,right_dut,up_ref,up_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.scancode );
RefModule good1 (
.scancode,
.left(left_ref),
.down(down_ref),
.right(right_ref),
.up(up_ref) );
TopModule top_module1 (
.scancode,
.left(left_dut),
.down(down_dut),
.right(right_dut),
.up(up_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_left) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "left", stats1.errors_left, stats1.errortime_left);
else $display("Hint: Output '%s' has no mismatches.", "left");
if (stats1.errors_down) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "down", stats1.errors_down, stats1.errortime_down);
else $display("Hint: Output '%s' has no mismatches.", "down");
if (stats1.errors_right) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "right", stats1.errors_right, stats1.errortime_right);
else $display("Hint: Output '%s' has no mismatches.", "right");
if (stats1.errors_up) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "up", stats1.errors_up, stats1.errortime_up);
else $display("Hint: Output '%s' has no mismatches.", "up");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { left_ref, down_ref, right_ref, up_ref } === ( { left_ref, down_ref, right_ref, up_ref } ^ { left_dut, down_dut, right_dut, up_dut } ^ { left_ref, down_ref, right_ref, up_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (left_ref !== ( left_ref ^ left_dut ^ left_ref ))
begin if (stats1.errors_left == 0) stats1.errortime_left = $time;
stats1.errors_left = stats1.errors_left+1'b1; end
if (down_ref !== ( down_ref ^ down_dut ^ down_ref ))
begin if (stats1.errors_down == 0) stats1.errortime_down = $time;
stats1.errors_down = stats1.errors_down+1'b1; end
if (right_ref !== ( right_ref ^ right_dut ^ right_ref ))
begin if (stats1.errors_right == 0) stats1.errortime_right = $time;
stats1.errors_right = stats1.errors_right+1'b1; end
if (up_ref !== ( up_ref ^ up_dut ^ up_ref ))
begin if (stats1.errors_up == 0) stats1.errortime_up = $time;
stats1.errors_up = stats1.errors_up+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob107_fsm1s |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input in
- output out
Implement the following Moore state machine with two states, one input,
and one output. The reset state is B and reset is active-high
synchronous.
B (out=1) --in=0--> A
B (out=1) --in=1--> B
A (out=0) --in=0--> B
A (out=0) --in=1--> A
|
module RefModule (
input clk,
input in,
input reset,
output out
);
parameter A=0, B=1;
reg state;
reg next;
always_comb begin
case (state)
A: next = in ? A : B;
B: next = in ? B : A;
endcase
end
always @(posedge clk) begin
if (reset) state <= B;
else state <= next;
end
assign out = (state==B);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in,
output logic reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1;
in <= 0;
@(posedge clk);
@(posedge clk) reset <= 0; in <= 0;
@(posedge clk) in <= 1;
wavedrom_start();
reset_test(0);
@(posedge clk) in <= 0;
@(posedge clk) in <= 0;
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(negedge clk);
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk) begin
in <= $random;
reset <= !($random & 7);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic reset;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.reset );
RefModule good1 (
.clk,
.in,
.reset,
.out(out_ref) );
TopModule top_module1 (
.clk,
.in,
.reset,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob108_rule90 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk,
- input load,
- input data (512 bits)
- output q (512 bits)
The module should implement Rule 90, a one-dimensional cellular automaton
with interesting properties. The rules are simple. There is a
one-dimensional array of cells (on or off). At each time step, the next
state of each cell is the XOR of the cell's two current neighbours:
Left | Center | Right | Center's next state
1 | 1 | 1 | 0
1 | 1 | 0 | 1
1 | 0 | 1 | 0
1 | 0 | 0 | 1
0 | 1 | 1 | 1
0 | 1 | 0 | 0
0 | 0 | 1 | 1
0 | 0 | 0 | 0
In this circuit, create a 512-cell system (q[511:0]), and advance by one
time step each clock cycle. The load input indicates the state of the
system should be loaded with data[511:0]. Assume the boundaries (q[-1]
and q[512]) are both zero (off). Assume all sequential logic is triggered
on the positive edge of the clock.
|
module RefModule (
input clk,
input load,
input [511:0] data,
output reg [511:0] q
);
always @(posedge clk) begin
if (load)
q <= data;
else begin
q <= q[$bits(q)-1:1] ^ {q[$bits(q)-2:0], 1'b0} ;
end
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg load,
output reg[511:0] data,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
data <= 0;
data[0] <= 1'b1;
load <= 1;
@(posedge clk); wavedrom_start("Sierpiński triangle: See Hint.");
@(posedge clk);
@(posedge clk);
load <= 0;
repeat(10) @(posedge clk);
wavedrom_stop();
data <= 0;
data[256] <= 1'b1;
load <= 1;
@(posedge clk);
@(posedge clk);
@(posedge clk);
load <= 0;
repeat(1000) @(posedge clk) begin
end
data <= 512'h1000000000000001;
load <= 1;
@(posedge clk);
load <= 0;
repeat(1000) @(posedge clk) begin
end
data <= $random;
load <= 1;
@(posedge clk);
load <= 0;
repeat(1000) @(posedge clk) begin
end
data <= 0;
load <= 1;
repeat(20) @(posedge clk);
repeat(2) @(posedge clk) data <= data + 2;
@(posedge clk) begin
load <= 0;
data <= data + 1;
end
repeat(20) @(posedge clk) data <= data + 1;
repeat(500) @(posedge clk) begin
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic load;
logic [511:0] data;
logic [511:0] q_ref;
logic [511:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.load,
.data );
RefModule good1 (
.clk,
.load,
.data,
.q(q_ref) );
TopModule top_module1 (
.clk,
.load,
.data,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob109_fsm1 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input in
- output out
The module should implement a Moore machine with the diagram described
below:
B (1) --0--> A
B (1) --1--> B
A (0) --0--> B
A (0) --1--> A
It should asynchronously reset into state B if reset if high.
|
module RefModule (
input clk,
input in,
input areset,
output out
);
parameter A=0, B=1;
reg state;
reg next;
always_comb begin
case (state)
A: next = in ? A : B;
B: next = in ? B : A;
endcase
end
always @(posedge clk, posedge areset) begin
if (areset) state <= B;
else state <= next;
end
assign out = (state==B);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in,
output logic areset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign areset = reset;
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1;
in <= 0;
@(posedge clk) reset <= 0; in <= 0;
@(posedge clk) in <= 1;
wavedrom_start();
reset_test(1);
@(posedge clk) in <= 0;
@(posedge clk) in <= 0;
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(negedge clk);
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk) begin
in <= $random;
reset <= !($random & 7);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic areset;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,areset,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.areset );
RefModule good1 (
.clk,
.in,
.areset,
.out(out_ref) );
TopModule top_module1 (
.clk,
.in,
.areset,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob110_fsm2 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input j
- input k
- output out
The module should implement a Moore state machine with two states, two
inputs, and one output according to diagram described below. Reset is an
active-high asynchronous reset to state OFF.
OFF (out=0) --j=0--> OFF
OFF (out=0) --j=1--> ON
ON (out=1) --k=0--> ON
ON (out=1) --k=1--> OFF
|
module RefModule (
input clk,
input j,
input k,
input areset,
output out
);
parameter A=0, B=1;
reg state;
reg next;
always_comb begin
case (state)
A: next = j ? B : A;
B: next = k ? A : B;
endcase
end
always @(posedge clk, posedge areset) begin
if (areset) state <= A;
else state <= next;
end
assign out = (state==B);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic j, k,
output logic areset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign areset = reset;
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
reg [0:11][1:0] d = 24'b000101010010101111111111;
initial begin
reset <= 1;
j <= 0;
k <= 0;
@(posedge clk);
reset <= 0;
j <= 1;
@(posedge clk);
j <= 0;
wavedrom_start("Reset and transitions");
reset_test(1);
for (int i=0;i<12;i++)
@(posedge clk) {k, j} <= d[i];
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk) begin
{j,k} <= $random;
reset <= !($random & 7);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic j;
logic k;
logic areset;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,j,k,areset,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.j,
.k,
.areset );
RefModule good1 (
.clk,
.j,
.k,
.areset,
.out(out_ref) );
TopModule top_module1 (
.clk,
.j,
.k,
.areset,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob111_fsm2s |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input j
- input k
- output out
The module should implement a Moore state machine with two states, two
inputs, and one output according to diagram described below. Reset is an
active-high synchronous reset to state OFF.
OFF (out=0) --j=0--> OFF
OFF (out=0) --j=1--> ON
ON (out=1) --k=0--> ON
ON (out=1) --k=1--> OFF
|
module RefModule (
input clk,
input j,
input k,
input reset,
output out
);
parameter A=0, B=1;
reg state;
reg next;
always_comb begin
case (state)
A: next = j ? B : A;
B: next = k ? A : B;
endcase
end
always @(posedge clk) begin
if (reset) state <= A;
else state <= next;
end
assign out = (state==B);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic j, k,
output logic reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
reg [0:11][1:0] d = 24'b000101010010101111111111;
initial begin
reset <= 1;
j <= 0;
k <= 0;
@(posedge clk);
reset <= 0;
j <= 1;
@(posedge clk);
j <= 0;
wavedrom_start("Reset and transitions");
reset_test();
for (int i=0;i<12;i++)
@(posedge clk) {k, j} <= d[i];
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk) begin
{j,k} <= $random;
reset <= !($random & 7);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic j;
logic k;
logic reset;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,j,k,reset,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.j,
.k,
.reset );
RefModule good1 (
.clk,
.j,
.k,
.reset,
.out(out_ref) );
TopModule top_module1 (
.clk,
.j,
.k,
.reset,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob112_always_case2 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in (4 bits)
- output pos (2 bits)
The module should implement a priority encoder. A priority encoder is a
combinational circuit that, when given an input bit vector, outputs the
position of the first 1 bit in the vector. For example, a 8-bit priority
encoder given the input 8'b10010000 would output 3'd4, because bit[4] is
first bit that is high. Build a 4-bit priority encoder. For this problem,
if none of the input bits are high (i.e., input is zero), output zero.
Note that a 4-bit number has 16 possible combinations.
|
module RefModule (
input [3:0] in,
output reg [1:0] pos
);
always @(*) begin
case (in)
4'h0: pos = 2'h0;
4'h1: pos = 2'h0;
4'h2: pos = 2'h1;
4'h3: pos = 2'h0;
4'h4: pos = 2'h2;
4'h5: pos = 2'h0;
4'h6: pos = 2'h1;
4'h7: pos = 2'h0;
4'h8: pos = 2'h3;
4'h9: pos = 2'h0;
4'ha: pos = 2'h1;
4'hb: pos = 2'h0;
4'hc: pos = 2'h2;
4'hd: pos = 2'h0;
4'he: pos = 2'h1;
4'hf: pos = 2'h0;
default: pos = 2'b0;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [3:0] in,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
@(negedge clk) wavedrom_start("Priority encoder");
@(posedge clk) in <= 4'h1;
repeat(4) @(posedge clk) in <= in << 1;
in <= 0;
repeat(16) @(posedge clk) in <= in + 1;
@(negedge clk) wavedrom_stop();
repeat(50) @(posedge clk, negedge clk) begin
in <= $urandom;
end
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_pos;
int errortime_pos;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [3:0] in;
logic [1:0] pos_ref;
logic [1:0] pos_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,pos_ref,pos_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in );
RefModule good1 (
.in,
.pos(pos_ref) );
TopModule top_module1 (
.in,
.pos(pos_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_pos) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "pos", stats1.errors_pos, stats1.errortime_pos);
else $display("Hint: Output '%s' has no mismatches.", "pos");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { pos_ref } === ( { pos_ref } ^ { pos_dut } ^ { pos_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (pos_ref !== ( pos_ref ^ pos_dut ^ pos_ref ))
begin if (stats1.errors_pos == 0) stats1.errortime_pos = $time;
stats1.errors_pos = stats1.errors_pos+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob113_2012_q1g |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input x (4 bits)
- output f
The module should implement the function f shown in the Karnaugh map
below.
x[0]x[1]
x[2]x[3] 00 01 11 10
00 | 1 | 0 | 0 | 1 |
01 | 0 | 0 | 0 | 0 |
11 | 1 | 1 | 1 | 0 |
10 | 1 | 1 | 0 | 1 |
|
module RefModule (
input [3:0] x,
output logic f
);
always_comb begin
case (x)
4'h0: f = 1;
4'h1: f = 1;
4'h2: f = 0;
4'h3: f = 0;
4'h4: f = 1;
4'h5: f = 1;
4'h6: f = 1;
4'h7: f = 0;
4'h8: f = 0;
4'h9: f = 0;
4'ha: f = 0;
4'hb: f = 0;
4'hc: f = 1;
4'hd: f = 0;
4'he: f = 1;
4'hf: f = 1;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [3:0] x
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
x <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_f;
int errortime_f;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [3:0] x;
logic f_ref;
logic f_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,x,f_ref,f_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.x );
RefModule good1 (
.x,
.f(f_ref) );
TopModule top_module1 (
.x,
.f(f_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_f) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "f", stats1.errors_f, stats1.errortime_f);
else $display("Hint: Output '%s' has no mismatches.", "f");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { f_ref } === ( { f_ref } ^ { f_dut } ^ { f_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (f_ref !== ( f_ref ^ f_dut ^ f_ref ))
begin if (stats1.errors_f == 0) stats1.errortime_f = $time;
stats1.errors_f = stats1.errors_f+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob114_bugs_case |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input code (8 bits)
- output out (4 bits)
- output valid
The module should recognize 8-bit keyboard scancodes for keys 0 through
9. It should indicate whether one of the 10 cases were recognized
(valid), and if so, which key was detected. If the 8-bit input is 8'h45,
8'h16, 8'h1e, 8'h26, 8'h25, 8'h2e, 8'h36, 8'h3d, 8'h3e, or 8'h46, the
4-bit output will be set to 0, 1, 2, 3, 4, 5, 6, 7, 8, or 9 respectively,
the 1-bit valid would be set to 1. If the input does not match any of the
cases, both output signals would be set to 0.
|
module RefModule (
input [7:0] code,
output reg [3:0] out,
output reg valid
);
// uhh.. make a case statement: maps scancode to 0-9, but accidentally
// infer a latch? and have one of the entries be wrong? (duplicate
// case, using different base!)
always @(*) begin
out = 0;
valid = 1;
case (code)
8'h45: out = 0;
8'h16: out = 1;
8'h1e: out = 2;
8'h26: out = 3;
8'h25: out = 4;
8'h2e: out = 5;
8'h36: out = 6;
8'h3d: out = 7;
8'h3e: out = 8;
8'h46: out = 9;
default: valid = 0;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] code,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
code <= 8'h45;
@(negedge clk) wavedrom_start("Decode scancodes");
@(posedge clk) code <= 8'h45;
@(posedge clk) code <= 8'h03;
@(posedge clk) code <= 8'h46;
@(posedge clk) code <= 8'h16;
@(posedge clk) code <= 8'd26;
@(posedge clk) code <= 8'h1e;
@(posedge clk) code <= 8'h25;
@(posedge clk) code <= 8'h26;
@(posedge clk) code <= 8'h2e;
@(posedge clk) code <= $random;
@(posedge clk) code <= 8'h36;
@(posedge clk) code <= $random;
@(posedge clk) code <= 8'h3d;
@(posedge clk) code <= 8'h3e;
@(posedge clk) code <= 8'h45;
@(posedge clk) code <= 8'h46;
@(posedge clk) code <= $random;
@(posedge clk) code <= $random;
@(posedge clk) code <= $random;
@(posedge clk) code <= $random;
wavedrom_stop();
repeat(1000) @(posedge clk, negedge clk) begin
code <= $urandom;
end
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int errors_valid;
int errortime_valid;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] code;
logic [3:0] out_ref;
logic [3:0] out_dut;
logic valid_ref;
logic valid_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,code,out_ref,out_dut,valid_ref,valid_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.code );
RefModule good1 (
.code,
.out(out_ref),
.valid(valid_ref) );
TopModule top_module1 (
.code,
.out(out_dut),
.valid(valid_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
if (stats1.errors_valid) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "valid", stats1.errors_valid, stats1.errortime_valid);
else $display("Hint: Output '%s' has no mismatches.", "valid");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref, valid_ref } === ( { out_ref, valid_ref } ^ { out_dut, valid_dut } ^ { out_ref, valid_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
if (valid_ref !== ( valid_ref ^ valid_dut ^ valid_ref ))
begin if (stats1.errors_valid == 0) stats1.errortime_valid = $time;
stats1.errors_valid = stats1.errors_valid+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob115_shift18 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input load
- input ena
- input amount (2 bits)
- input data (64 bits)
- output q (64 bits)
The module should implement a 64-bit arithmetic shift register, with
synchronous load. The shifter can shift both left and right, and by 1 or
8 bit positions, selected by "amount." Assume the right shit is an
arithmetic right shift.
Signals are defined as below:
(1) load: Loads shift register with data[63:0] instead of shifting.
Active high.
(2) ena: Chooses whether to shift. Active high.
(3) amount: Chooses which direction and how much to shift.
(a) 2'b00: shift left by 1 bit.
(b) 2'b01: shift left by 8 bits.
(c) 2'b10: shift right by 1 bit.
(d) 2'b11: shift right by 8 bits.
(4) q: The contents of the shifter.
|
module RefModule (
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q
);
always @(posedge clk) begin
if (load)
q <= data;
else if (ena) case (amount)
2'b00: q <= {q[62:0], 1'b0};
2'b01: q <= {q[55:0], 8'b0};
2'b10: q <= {q[63], q[63:1]};
2'b11: q <= {{8{q[63]}}, q[63:8]};
default: q <= 64'hx;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg load,
output reg ena,
output reg[1:0] amount,
output reg[63:0] data,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
load <= 1;
ena <= 0;
data <= 'x;
amount <= 0;
@(posedge clk) data <= 64'h000100;
wavedrom_start("Shifting");
@(posedge clk) load <= 0; ena <= 1;
amount <= 2;
@(posedge clk) amount <= 2;
@(posedge clk) amount <= 2;
@(posedge clk) amount <= 1;
@(posedge clk) amount <= 1;
@(posedge clk) amount <= 0;
@(posedge clk) amount <= 0;
@(posedge clk) amount <= 3;
@(posedge clk) amount <= 3;
@(posedge clk) amount <= 2;
@(posedge clk) amount <= 2;
@(negedge clk);
wavedrom_stop();
@(posedge clk); load <= 1; data <= 64'hx;
@(posedge clk); load <= 1; data <= 64'h80000000_00000000;
wavedrom_start("Arithmetic right shift");
@(posedge clk) load <= 0; ena <= 1;
amount <= 2;
@(posedge clk) amount <= 2;
@(posedge clk) amount <= 2;
@(posedge clk) amount <= 2;
@(posedge clk) amount <= 2;
@(negedge clk);
wavedrom_stop();
@(posedge clk);
@(posedge clk);
repeat(4000) @(posedge clk, negedge clk) begin
load <= !($random & 31);
ena <= |($random & 15);
amount <= $random;
data <= {$random,$random};
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic load;
logic ena;
logic [1:0] amount;
logic [63:0] data;
logic [63:0] q_ref;
logic [63:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,ena,amount,data,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.load,
.ena,
.amount,
.data );
RefModule good1 (
.clk,
.load,
.ena,
.amount,
.data,
.q(q_ref) );
TopModule top_module1 (
.clk,
.load,
.ena,
.amount,
.data,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob116_m2014_q3 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input x (4 bits)
- output f
The module should implement the function f shown in the Karnaugh map
below. d is don't-care, which means you may choose to output whatever
value is convenient.
x[1]x[2]
x[3]x[4] 00 01 11 10
00 | d | 0 | d | d |
01 | 0 | d | 1 | 0 |
11 | 1 | 1 | d | d |
10 | 1 | 1 | 0 | d |
|
module RefModule (
input [3:0] x,
output logic f
);
always_comb begin
case (x)
4'h0: f = 1'bx;
4'h1: f = 1'bx;
4'h2: f = 0;
4'h3: f = 1'bx;
4'h4: f = 1;
4'h5: f = 1'bx;
4'h6: f = 1;
4'h7: f = 0;
4'h8: f = 0;
4'h9: f = 0;
4'ha: f = 1'bx;
4'hb: f = 1;
4'hc: f = 1;
4'hd: f = 1'bx;
4'he: f = 1;
4'hf: f = 1'bx;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [3:0] x
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
x <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_f;
int errortime_f;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [3:0] x;
logic f_ref;
logic f_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,x,f_ref,f_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.x );
RefModule good1 (
.x,
.f(f_ref) );
TopModule top_module1 (
.x,
.f(f_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_f) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "f", stats1.errors_f, stats1.errortime_f);
else $display("Hint: Output '%s' has no mismatches.", "f");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { f_ref } === ( { f_ref } ^ { f_dut } ^ { f_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (f_ref !== ( f_ref ^ f_dut ^ f_ref ))
begin if (stats1.errors_f == 0) stats1.errortime_f = $time;
stats1.errors_f = stats1.errors_f+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob117_circuit9 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input a
- output q (3 bits)
The module implements a sequential circuit. Read the simulation waveforms
to determine what the circuit does, then implement it.
time clk a q
0ns 0 1 x
5ns 1 1 4
10ns 0 1 4
15ns 1 1 4
20ns 0 1 4
25ns 1 1 4
30ns 0 1 4
35ns 1 1 4
40ns 0 1 4
45ns 1 0 4
50ns 0 0 4
55ns 1 0 5
60ns 0 0 5
65ns 1 0 6
70ns 0 0 6
75ns 1 0 0
80ns 0 0 0
85ns 1 0 1
90ns 0 0 1
|
module RefModule (
input clk,
input a,
output reg [2:0] q
);
always @(posedge clk)
if (a)
q <= 4;
else if (q == 6)
q <= 0;
else
q <= q + 1'b1;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
a <= 1;
@(negedge clk) {a} <= 1;
@(negedge clk) wavedrom_start("Unknown circuit");
repeat(2) @(posedge clk);
@(posedge clk) {a} <= 0;
repeat(11) @(posedge clk);
@(negedge clk) a <= 1;
repeat(5) @(posedge clk, negedge clk);
a <= 0;
repeat(4) @(posedge clk);
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
a <= &((5)'($urandom));
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic [2:0] q_ref;
logic [2:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,a,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a );
RefModule good1 (
.clk,
.a,
.q(q_ref) );
TopModule top_module1 (
.clk,
.a,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob118_history_shift |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input predict_valid
- input predict_taken
- input train_mispredicted
- input train_taken
- input train_history (32 bits)
- output predict_history (32 bits)
The module should implement a 32-bit global history shift register,
including support for rolling back state in response to a pipeline flush
caused by a branch misprediction. When a branch prediction is made
(predict_valid = 1), shift in predict_taken from the LSB side to update
the branch history for the predicted branch. (predict_history[0] is the
direction of the youngest branch.) When a branch misprediction occurs
(train_mispredicted = 1), load the branch history register with the
history after the completion of the mispredicted branch. This is the
history before the mispredicted branch (train_history) concatenated with
the actual result of the branch (train_taken). If both a prediction and
misprediction occur at the same time, the misprediction takes precedence,
because the pipeline flush will also flush out the branch that is
currently making a prediction. predict_history is the value of the branch
history register. areset is a positive edge triggered asynchronous reset
that resets the history counter to zero. Assume all sequential logic is
triggered on the positive edge of the clock.
|
module RefModule (
input clk,
input areset,
input predict_valid,
input predict_taken,
output logic [31:0] predict_history,
input train_mispredicted,
input train_taken,
input [31:0] train_history
);
always@(posedge clk, posedge areset)
if (areset) begin
predict_history = 0;
end else begin
if (train_mispredicted)
predict_history <= {train_history, train_taken};
else if (predict_valid)
predict_history <= {predict_history, predict_taken};
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen
(
input clk,
output logic areset,
output logic predict_valid,
output predict_taken,
output logic train_mispredicted,
output train_taken,
output [31:0] train_history,
input tb_match,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
output int wavedrom_hide_after_time
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
reg reset;
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
assign areset = reset;
logic predict_taken_r;
assign predict_taken = predict_valid ? predict_taken_r : 1'bx;
logic train_taken_r;
logic [31:0] train_history_r;
assign train_taken = train_mispredicted ? train_taken_r : 1'bx;
assign train_history = train_mispredicted ? train_history_r : 32'hx;
initial begin
@(posedge clk) reset <= 1;
@(posedge clk) reset <= 0;
predict_taken_r <= 1;
predict_valid <= 1;
train_mispredicted <= 0;
train_history_r <= 32'h5;
train_taken_r <= 1;
wavedrom_start("Asynchronous reset");
reset_test(1); // Test for asynchronous reset
wavedrom_stop();
@(posedge clk) reset <= 1;
predict_valid <= 0;
wavedrom_start("Predictions: Shift in");
repeat(2) @(posedge clk) {predict_valid, predict_taken_r} <= {$urandom};
reset <= 0;
predict_valid <= 1;
repeat(6) @(posedge clk) {predict_taken_r} <= {$urandom};
predict_valid <= 0;
repeat(3) @(posedge clk) {predict_taken_r} <= {$urandom};
predict_valid <= 1;
train_mispredicted <= 1;
@(posedge clk) train_mispredicted <= 0;
repeat(6) @(posedge clk) {predict_taken_r} <= {$urandom};
wavedrom_stop();
repeat(2000) @(posedge clk,negedge clk) begin
{predict_valid, predict_taken_r, train_taken_r} <= {$urandom};
train_history_r <= $urandom;
train_mispredicted <= !($urandom_range(0,31));
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_predict_history;
int errortime_predict_history;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic areset;
logic predict_valid;
logic predict_taken;
logic train_mispredicted;
logic train_taken;
logic [31:0] train_history;
logic [31:0] predict_history_ref;
logic [31:0] predict_history_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,predict_valid,predict_taken,train_mispredicted,train_taken,train_history,predict_history_ref,predict_history_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.areset,
.predict_valid,
.predict_taken,
.train_mispredicted,
.train_taken,
.train_history );
RefModule good1 (
.clk,
.areset,
.predict_valid,
.predict_taken,
.train_mispredicted,
.train_taken,
.train_history,
.predict_history(predict_history_ref) );
TopModule top_module1 (
.clk,
.areset,
.predict_valid,
.predict_taken,
.train_mispredicted,
.train_taken,
.train_history,
.predict_history(predict_history_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_predict_history) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "predict_history", stats1.errors_predict_history, stats1.errortime_predict_history);
else $display("Hint: Output '%s' has no mismatches.", "predict_history");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { predict_history_ref } === ( { predict_history_ref } ^ { predict_history_dut } ^ { predict_history_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (predict_history_ref !== ( predict_history_ref ^ predict_history_dut ^ predict_history_ref ))
begin if (stats1.errors_predict_history == 0) stats1.errortime_predict_history = $time;
stats1.errors_predict_history = stats1.errors_predict_history+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob119_fsm3 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input in
- output out
The module should implement a Moore state machine with the following
state transition table with one input, one output, and four states.
Implement this state machine. Include a positive edge triggered
asynchronous reset that resets the FSM to state A. Assume all sequential
logic is triggered on the positive edge of the clock.
state | next state in=0, next state in=1 | output
A | A, B | 0
B | C, B | 0
C | A, D | 0
D | C, B | 1
|
module RefModule (
input clk,
input in,
input areset,
output out
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state;
reg [1:0] next;
always_comb begin
case (state)
A: next = in ? B : A;
B: next = in ? B : C;
C: next = in ? D : A;
D: next = in ? B : C;
endcase
end
always @(posedge clk, posedge areset) begin
if (areset) state <= A;
else state <= next;
end
assign out = (state==D);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in,
output logic areset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign areset = reset;
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1;
in <= 0;
@(posedge clk) reset <= 0; in <= 1;
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
wavedrom_start();
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
@(posedge clk);
@(negedge clk) reset <= 1;
@(posedge clk) reset <= 0;
@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(negedge clk);
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk) begin
in <= $random;
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic areset;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,areset,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.areset );
RefModule good1 (
.clk,
.in,
.areset,
.out(out_ref) );
TopModule top_module1 (
.clk,
.in,
.areset,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob120_fsm3s |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input in
- output out
The module should implement a Moore state machine with the following
state transition table with one input, one output, and four states.
Include a synchronous active high reset that resets the FSM to state A.
Assume all sequential logic is triggered on the positive edge of the
clock.
State | Next state in=0, Next state in=1 | Output
A | A, B | 0
B | C, B | 0
C | A, D | 0
D | C, B | 1
|
module RefModule (
input clk,
input in,
input reset,
output out
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state;
reg [1:0] next;
always_comb begin
case (state)
A: next = in ? B : A;
B: next = in ? B : C;
C: next = in ? D : A;
D: next = in ? B : C;
endcase
end
always @(posedge clk) begin
if (reset) state <= A;
else state <= next;
end
assign out = (state==D);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in,
output logic reset,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1;
in <= 0;
@(posedge clk) reset <= 0; in <= 1;
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
wavedrom_start();
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
@(posedge clk);
@(negedge clk) reset <= 1;
@(posedge clk) reset <= 0;
@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(negedge clk);
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk) begin
in <= $random;
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic reset;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.reset );
RefModule good1 (
.clk,
.in,
.reset,
.out(out_ref) );
TopModule top_module1 (
.clk,
.in,
.reset,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob121_2014_q3bfsm |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input x
- output z
The module should implement a finite-state machine with the
state-assigned table shown below. Reset should synchronous active high
reset the FSM to state 000. Assume all sequential logic is triggered on
the positive edge of the clock.
Present state y[2:0] | Next state y[2:0] x=0, Next state y[2:0] x=1 | Output z
000 | 000, 001 | 0
001 | 001, 100 | 0
010 | 010, 001 | 0
011 | 001, 010 | 1
100 | 011, 100 | 1
|
module RefModule (
input clk,
input reset,
input x,
output reg z
);
parameter A=0, B=1, C=2, D=3, E=4;
reg [2:0] state, next;
always @(posedge clk) begin
if (reset) state <= A;
else state <= next;
end
always_comb begin
case (state)
A: next = x ? B : A;
B: next = x ? E : B;
C: next = x ? B : C;
D: next = x ? C : B;
E: next = x ? E : D;
default: next = 'x;
endcase
end
assign z = (state == D) || (state == E);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic reset,
output logic x
);
initial begin
reset = 1;
x = 0;
@(posedge clk);
@(posedge clk);
reset = 0;
@(posedge clk);
@(posedge clk);
repeat(500) @(negedge clk) begin
reset <= !($random & 63);
x <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic x;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,x,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset,
.x );
RefModule good1 (
.clk,
.reset,
.x,
.z(z_ref) );
TopModule top_module1 (
.clk,
.reset,
.x,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob122_kmap4 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- input d
- output out
The module should implement the Karnaugh map below.
ab
cd 00 01 11 10
00 | 0 | 1 | 0 | 1 |
01 | 1 | 0 | 1 | 0 |
11 | 0 | 1 | 0 | 1 |
10 | 1 | 0 | 1 | 0 |
|
module RefModule (
input a,
input b,
input c,
input d,
output reg out
);
always @(*) begin
case({a,b,c,d})
4'h0: out = 0;
4'h1: out = 1;
4'h3: out = 0;
4'h2: out = 1;
4'h4: out = 1;
4'h5: out = 0;
4'h7: out = 1;
4'h6: out = 0;
4'hc: out = 0;
4'hd: out = 1;
4'hf: out = 0;
4'he: out = 1;
4'h8: out = 1;
4'h9: out = 0;
4'hb: out = 1;
4'ha: out = 0;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b, c, d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b,c,d} <= 4'b0;
wavedrom_start();
repeat(16) @(posedge clk)
{a,b,c,d} <= count++;
@(negedge clk) wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{d,c,b,a} <= $urandom;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic c;
logic d;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d );
RefModule good1 (
.a,
.b,
.c,
.d,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.d,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob123_bugs_addsubz |
Consider the following adder-subtractor with a zero flag:
synthesis verilog_input_version verilog_2001
module TopModule (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
);
always @(*) begin
case (do_sub)
0: out = a+b;
1: out = a-b;
endcase
if (~out)
result_is_zero = 1;
end
endmodule
Unfortunately, this module has a bug. Implement a new version of this
module that fixes the bug.
|
module RefModule (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
);
always @(*) begin
case (do_sub)
0: out = a + b;
1: out = a - b;
endcase
result_is_zero = (out == 0);
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic do_sub,
output logic [7:0] a, b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
{a, b} <= 16'haabb;
do_sub <= 0;
@(negedge clk) wavedrom_start("");
@(posedge clk, negedge clk) do_sub <= 0;
@(posedge clk, negedge clk) do_sub <= 0;
@(posedge clk, negedge clk) do_sub <= 1;
@(posedge clk, negedge clk) do_sub <= 1;
@(posedge clk, negedge clk) {a, b} <= 16'h0303; do_sub <= 1'b0;
@(posedge clk, negedge clk) do_sub <= 0;
@(posedge clk, negedge clk) do_sub <= 1;
@(posedge clk, negedge clk) {a, b} <= 16'h0304; do_sub <= 1'b0;
@(posedge clk, negedge clk) do_sub <= 0;
@(posedge clk, negedge clk) do_sub <= 1;
@(posedge clk, negedge clk) {a, b} <= 16'hfd03; do_sub <= 1'b0;
@(posedge clk, negedge clk) do_sub <= 0;
@(posedge clk, negedge clk) do_sub <= 1;
@(posedge clk, negedge clk) {a, b} <= 16'hfd04; do_sub <= 1'b0;
@(posedge clk, negedge clk) do_sub <= 0;
@(posedge clk, negedge clk) do_sub <= 1;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk) begin
{a,b, do_sub} <= $urandom;
end
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int errors_result_is_zero;
int errortime_result_is_zero;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic do_sub;
logic [7:0] a;
logic [7:0] b;
logic [7:0] out_ref;
logic [7:0] out_dut;
logic result_is_zero_ref;
logic result_is_zero_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,do_sub,a,b,out_ref,out_dut,result_is_zero_ref,result_is_zero_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.do_sub,
.a,
.b );
RefModule good1 (
.do_sub,
.a,
.b,
.out(out_ref),
.result_is_zero(result_is_zero_ref) );
TopModule top_module1 (
.do_sub,
.a,
.b,
.out(out_dut),
.result_is_zero(result_is_zero_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
if (stats1.errors_result_is_zero) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "result_is_zero", stats1.errors_result_is_zero, stats1.errortime_result_is_zero);
else $display("Hint: Output '%s' has no mismatches.", "result_is_zero");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref, result_is_zero_ref } === ( { out_ref, result_is_zero_ref } ^ { out_dut, result_is_zero_dut } ^ { out_ref, result_is_zero_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
if (result_is_zero_ref !== ( result_is_zero_ref ^ result_is_zero_dut ^ result_is_zero_ref ))
begin if (stats1.errors_result_is_zero == 0) stats1.errortime_result_is_zero = $time;
stats1.errors_result_is_zero = stats1.errors_result_is_zero+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob124_rule110 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input load
- input data (512 bits)
- output q (512 bits)
The module should implement Rule 110, a one-dimensional cellular
automaton with interesting properties (such as being Turing-complete).
There is a one-dimensional array of cells (on or off). At each time step,
the state of each cell changes. In Rule 110, the next state of each cell
depends only on itself and its two neighbours, according to the following
table:
Left | Center | Right | Center's next state
1 | 1 | 1 | 0
1 | 1 | 0 | 1
1 | 0 | 1 | 1
1 | 0 | 0 | 0
0 | 1 | 1 | 1
0 | 1 | 0 | 1
0 | 0 | 1 | 1
0 | 0 | 0 | 0
In this circuit, create a 512-cell system (q[511:0]), and advance by one
time step each clock cycle. The synchronous active high load input
indicates the state of the system should be loaded with data[511:0].
Assume the boundaries (q[-1] and q[512]) are both zero (off). Assume all
sequential logic is triggered on the positive edge of the clock.
|
module RefModule (
input clk,
input load,
input [511:0] data,
output reg [511:0] q
);
always @(posedge clk) begin
if (load)
q <= data;
else begin
q <=
~((q[$bits(q)-1:1] & q[$bits(q)-1:0] & {q[$bits(q)-2:0], 1'b0}) |
(~q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) |
(q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) )
;
end
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg load,
output reg[511:0] data,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
data <= 0;
data[0] <= 1'b1;
load <= 1;
@(posedge clk); wavedrom_start("Load q[511:0] = 1: See Hint.");
@(posedge clk);
@(posedge clk);
load <= 0;
repeat(10) @(posedge clk);
wavedrom_stop();
data <= 0;
data[256] <= 1'b1;
load <= 1;
@(posedge clk);
@(posedge clk);
@(posedge clk);
load <= 0;
repeat(1000) @(posedge clk) begin
end
data <= 512'h4df;
load <= 1;
@(posedge clk);
load <= 0;
repeat(1000) @(posedge clk) begin
end
data <= $random;
load <= 1;
@(posedge clk);
load <= 0;
repeat(1000) @(posedge clk) begin
end
data <= 0;
load <= 1;
repeat (20) @(posedge clk);
@(posedge clk) data <= 2;
@(posedge clk) data <= 4;
@(posedge clk) begin
data <= 9;
load <= 0;
end
@(posedge clk) data <= 12;
repeat(100) @(posedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic load;
logic [511:0] data;
logic [511:0] q_ref;
logic [511:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.load,
.data );
RefModule good1 (
.clk,
.load,
.data,
.q(q_ref) );
TopModule top_module1 (
.clk,
.load,
.data,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob125_kmap3 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a
- input b
- input c
- input d
- output out
The module should implement the Karnaugh map below. d is don't-care,
which means you may choose to output whatever value is convenient.
ab
cd 01 00 10 11
00 | d | 0 | 1 | 1 |
01 | 0 | 0 | d | d |
11 | 0 | 1 | 1 | 1 |
10 | 0 | 1 | 1 | 1 |
|
module RefModule (
input a,
input b,
input c,
input d,
output reg out
);
always @(*) begin
case({a,b,c,d})
4'h0: out = 0;
4'h1: out = 0;
4'h3: out = 1;
4'h2: out = 1;
4'h4: out = 1'bx;
4'h5: out = 0;
4'h7: out = 0;
4'h6: out = 0;
4'hc: out = 1;
4'hd: out = 1'bx;
4'hf: out = 1;
4'he: out = 1;
4'h8: out = 1;
4'h9: out = 1'bx;
4'hb: out = 1;
4'ha: out = 1;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg a, b, c, d,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
int count; count = 0;
{a,b,c,d} <= 4'b0;
wavedrom_start();
repeat(16) @(posedge clk)
{a,b,c,d} <= count++;
@(negedge clk) wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
{d,c,b,a} <= $urandom;
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out;
int errortime_out;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic c;
logic d;
logic out_ref;
logic out_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,out_ref,out_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d );
RefModule good1 (
.a,
.b,
.c,
.d,
.out(out_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.d,
.out(out_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out", stats1.errors_out, stats1.errortime_out);
else $display("Hint: Output '%s' has no mismatches.", "out");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_ref } === ( { out_ref } ^ { out_dut } ^ { out_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_ref !== ( out_ref ^ out_dut ^ out_ref ))
begin if (stats1.errors_out == 0) stats1.errortime_out = $time;
stats1.errors_out = stats1.errors_out+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob126_circuit6 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a ( 3 bits)
- output q (16 bits)
The module should implement a combinational circuit. Read the simulation
waveforms to determine what the circuit does, then implement it.
time a q
0ns x x
5ns x x
10ns x x
15ns 0 1232
20ns 1 aee0
25ns 2 27d4
30ns 3 5a0e
35ns 4 2066
40ns 5 64ce
45ns 6 c526
50ns 7 2f19
55ns 0 1232
60ns 1 aee0
65ns 2 27d4
70ns 4 2066
75ns 1 aee0
80ns 1 aee0
85ns 3 5a0e
90ns 5 64ce
|
module RefModule (
input [2:0] a,
output reg [15:0] q
);
always @(*)
case (a)
0: q = 4658;
1: q = 44768;
2: q = 10196;
3: q = 23054;
4: q = 8294;
5: q = 25806;
6: q = 50470;
7: q = 12057;
endcase
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [2:0] a,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
@(negedge clk) wavedrom_start("Unknown circuit");
@(posedge clk) {a} <= 0;
repeat(10) @(posedge clk,negedge clk) a <= a + 1;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
a <= $urandom;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [2:0] a;
logic [15:0] q_ref;
logic [15:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a );
RefModule good1 (
.a,
.q(q_ref) );
TopModule top_module1 (
.a,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob127_lemmings1 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input bump_left
- input bump_right
- output walk_left
- output walk_right
The module should implement a simple game called Lemmings which involves
critters with fairly simple brains. So simple that we are going to model
it using a finite state machine. In the Lemmings' 2D world, Lemmings can
be in one of two states: walking left (walk_left is 1) or walking right
(walk_right is 1). It will switch directions if it hits an obstacle. In
particular, if a Lemming is bumped on the left (by receiving a 1 on
bump_left), it will walk right. If it's bumped on the right (by receiving
a 1 on bump_right), it will walk left. If it's bumped on both sides at
the same time, it will still switch directions.
The module should implement a Moore state machine with two states, two
inputs, and one output (internal to the module) that models this
behaviour. areset is positive edge triggered asynchronous resetting the
Lemming machine to walk left. Assume all sequential logic is triggered on
the positive edge of the clock.
|
module RefModule (
input clk,
input areset,
input bump_left,
input bump_right,
output walk_left,
output walk_right
);
parameter WL=0, WR=1;
reg state;
reg next;
always_comb begin
case (state)
WL: next = bump_left ? WR : WL;
WR: next = bump_right ? WL: WR;
endcase
end
always @(posedge clk, posedge areset) begin
if (areset) state <= WL;
else state <= next;
end
assign walk_left = (state==WL);
assign walk_right = (state==WR);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic areset,
output logic bump_left,
output logic bump_right,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign areset = reset;
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1'b1;
{bump_right, bump_left} <= 3'h3;
wavedrom_start("Asynchronous reset");
reset_test(1);
repeat(3) @(posedge clk);
{bump_right, bump_left} <= 2;
repeat(2) @(posedge clk);
{bump_right, bump_left} <= 1;
repeat(2) @(posedge clk);
wavedrom_stop();
@(posedge clk);
repeat(200) @(posedge clk, negedge clk) begin
{bump_right, bump_left} <= $random & $random;
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_walk_left;
int errortime_walk_left;
int errors_walk_right;
int errortime_walk_right;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic areset;
logic bump_left;
logic bump_right;
logic walk_left_ref;
logic walk_left_dut;
logic walk_right_ref;
logic walk_right_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,bump_left,bump_right,walk_left_ref,walk_left_dut,walk_right_ref,walk_right_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.areset,
.bump_left,
.bump_right );
RefModule good1 (
.clk,
.areset,
.bump_left,
.bump_right,
.walk_left(walk_left_ref),
.walk_right(walk_right_ref) );
TopModule top_module1 (
.clk,
.areset,
.bump_left,
.bump_right,
.walk_left(walk_left_dut),
.walk_right(walk_right_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_walk_left) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "walk_left", stats1.errors_walk_left, stats1.errortime_walk_left);
else $display("Hint: Output '%s' has no mismatches.", "walk_left");
if (stats1.errors_walk_right) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "walk_right", stats1.errors_walk_right, stats1.errortime_walk_right);
else $display("Hint: Output '%s' has no mismatches.", "walk_right");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { walk_left_ref, walk_right_ref } === ( { walk_left_ref, walk_right_ref } ^ { walk_left_dut, walk_right_dut } ^ { walk_left_ref, walk_right_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (walk_left_ref !== ( walk_left_ref ^ walk_left_dut ^ walk_left_ref ))
begin if (stats1.errors_walk_left == 0) stats1.errortime_walk_left = $time;
stats1.errors_walk_left = stats1.errors_walk_left+1'b1; end
if (walk_right_ref !== ( walk_right_ref ^ walk_right_dut ^ walk_right_ref ))
begin if (stats1.errors_walk_right == 0) stats1.errortime_walk_right = $time;
stats1.errors_walk_right = stats1.errors_walk_right+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob128_fsm_ps2 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input in (8 bits)
- output done
The PS/2 mouse protocol sends messages that are three bytes long.
However, within a continuous byte stream, it's not obvious where messages
start and end. The only indication is that the first byte of each three
byte message always has in[3]=1 (but in[3] of the other two bytes may be
1 or 0 depending on data).
The module should implement a finite state machine that will search for
message boundaries when given an input byte stream. The algorithm we'll
use is to discard bytes until we see one with in[3]=1. We then assume
that this is byte 1 of a message, and signal the receipt of a message
once all 3 bytes have been received (done). The FSM should signal done in
the cycle immediately after the third byte of each message was
successfully received. Reset should be active high synchronous. Assume
all sequential logic is triggered on the positive edge of the clock.
|
module RefModule (
input clk,
input [7:0] in,
input reset,
output done
);
parameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;
reg [1:0] state;
reg [1:0] next;
wire in3 = in[3];
always_comb begin
case (state)
BYTE1: next = in3 ? BYTE2 : BYTE1;
BYTE2: next = BYTE3;
BYTE3: next = DONE;
DONE: next = in3 ? BYTE2 : BYTE1;
endcase
end
always @(posedge clk) begin
if (reset) state <= BYTE1;
else state <= next;
end
assign done = (state==DONE);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] in,
output logic reset
);
initial begin
repeat(200) @(negedge clk) begin
in <= $random;
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_done;
int errortime_done;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] in;
logic reset;
logic done_ref;
logic done_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,done_ref,done_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.reset );
RefModule good1 (
.clk,
.in,
.reset,
.done(done_ref) );
TopModule top_module1 (
.clk,
.in,
.reset,
.done(done_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_done) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "done", stats1.errors_done, stats1.errortime_done);
else $display("Hint: Output '%s' has no mismatches.", "done");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { done_ref } === ( { done_ref } ^ { done_dut } ^ { done_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (done_ref !== ( done_ref ^ done_dut ^ done_ref ))
begin if (stats1.errors_done == 0) stats1.errortime_done = $time;
stats1.errors_done = stats1.errors_done+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob129_ece241_2013_q8 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input aresetn
- input x
- output z
The module should implement a Mealy-type finite state machine that
recognizes the sequence "101" on an input signal named x. Your FSM should
have an output signal, z, that is asserted to logic-1 when the "101"
sequence is detected. Your FSM should also have a negative edge triggered
asynchronous reset. You may only have 3 states in your state machine.
Your FSM should recognize overlapping sequences. Assume all sequential
logic is triggered on the positive edge of the clock.
|
module RefModule (
input clk,
input aresetn,
input x,
output reg z
);
parameter S=0, S1=1, S10=2;
reg[1:0] state, next;
always@(posedge clk, negedge aresetn)
if (!aresetn)
state <= S;
else
state <= next;
always_comb begin
case (state)
S: next = x ? S1 : S;
S1: next = x ? S1 : S10;
S10: next = x ? S1 : S;
default: next = 'x;
endcase
end
always_comb begin
case (state)
S: z = 0;
S1: z = 0;
S10: z = x;
default: z = 'x;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic aresetn,
output logic x,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign aresetn = ~reset;
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
initial begin
x <= 0;
repeat(3) @(posedge clk);
@(posedge clk) x <= 1;
@(posedge clk) x <= 0;
@(posedge clk) x <= 1;
end
initial begin
reset <= 1;
@(posedge clk) reset <= 0;
reset_test(1);
@(negedge clk) wavedrom_start();
@(posedge clk) x <= 0;
@(posedge clk) x <= 0;
@(posedge clk) x <= 0;
@(posedge clk) x <= 1;
@(posedge clk) x <= 0;
@(posedge clk) x <= 1;
@(posedge clk) x <= 0;
@(posedge clk) x <= 1;
@(posedge clk) x <= 1;
@(posedge clk) x <= 0;
@(posedge clk) x <= 1;
@(posedge clk) x <= 0;
@(negedge clk) wavedrom_stop();
repeat(400) @(posedge clk, negedge clk) begin
x <= $random;
reset <= ($random&31) == 0;
end
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic aresetn;
logic x;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,aresetn,x,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.aresetn,
.x );
RefModule good1 (
.clk,
.aresetn,
.x,
.z(z_ref) );
TopModule top_module1 (
.clk,
.aresetn,
.x,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob130_circuit5 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input a (4 bits)
- input b (4 bits)
- input c (4 bits)
- input d (4 bits)
- input e (4 bits)
- output q (4 bits)
The module should implement a combinational circuit. Read the simulation
waveforms to determine what the circuit does, then implement it.
time a b c d e q
0ns x x x x x x
5ns x x x x x x
10ns x x x x x x
15ns a b 0 d e b
20ns a b 1 d e e
25ns a b 2 d e a
30ns a b 3 d e d
35ns a b 4 d e f
40ns a b 5 d e f
45ns a b 6 d e f
50ns a b 7 d e f
55ns a b 8 d e f
60ns a b 9 d e f
65ns a b a d e f
70ns a b b d e f
75ns a b c d e f
80ns a b d d e f
85ns a b e d e f
90ns a b f d e f
|
module RefModule (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output reg [3:0] q
);
always @(*)
case (c)
0: q = b;
1: q = e;
2: q = a;
3: q = d;
default: q = 4'hf;
endcase
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [3:0] a,b,c,d,e,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
@(negedge clk) wavedrom_start("Unknown circuit");
@(posedge clk) {a,b,c,d,e} <= {20'hab0de};
repeat(18) @(posedge clk, negedge clk) c <= c + 1;
wavedrom_stop();
@(negedge clk) wavedrom_start("Unknown circuit");
@(posedge clk) {a,b,c,d,e} <= {20'h12034};
repeat(8) @(posedge clk, negedge clk) c <= c + 1;
@(posedge clk) {a,b,c,d,e} <= {20'h56078};
repeat(8) @(posedge clk, negedge clk) c <= c + 1;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
{a,b,c,d,e} <= $urandom;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [3:0] a;
logic [3:0] b;
logic [3:0] c;
logic [3:0] d;
logic [3:0] e;
logic [3:0] q_ref;
logic [3:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,a,b,c,d,e,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b,
.c,
.d,
.e );
RefModule good1 (
.a,
.b,
.c,
.d,
.e,
.q(q_ref) );
TopModule top_module1 (
.a,
.b,
.c,
.d,
.e,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob131_mt2015_q4 |
Module A implements the boolean function z = (x^y) & x.
Module B can be described by the following simulation waveform:
time x y z
0ns 0 0 1
5ns 0 0 1
10ns 0 0 1
15ns 0 0 1
20ns 0 0 1
25ns 1 0 0
30ns 1 0 0
35ns 0 1 0
40ns 0 1 0
45ns 1 1 1
50ns 1 1 1
55ns 0 0 1
60ns 0 1 0
65ns 0 1 0
70ns 1 1 1
75ns 0 1 0
80ns 0 1 0
85ns 0 1 0
90ns 1 0 0
Now consider a top-level module with the following interface:
- input x
- input y
- output z
The module is implemented with two A submodules and two B submodules. The
first input of all four submodules is connect to input 'x', and the
second input of all four submodules is connected to 'y'. The output of
the first A submodule is connected to a two-input OR, along with the
output of the first B submodule. The second pair of A and B submodules is
similarly connected to an AND gate. The output of the OR and the AND is
connected to an XOR, whose output is 'z'.
|
module RefModule (
input x,
input y,
output z
);
assign z = x|~y;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic x,
output logic y
);
always @(posedge clk, negedge clk)
{x, y} <= $random % 4;
initial begin
repeat(100) @(negedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic x;
logic y;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,x,y,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.x,
.y );
RefModule good1 (
.x,
.y,
.z(z_ref) );
TopModule top_module1 (
.x,
.y,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob132_always_if2 |
Consider the following adder-subtractor with a zero flag:
module TopModule (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving
);
always @(*) begin
if (cpu_overheated)
shut_off_computer = 1;
end
always @(*) begin
if (~arrived)
keep_driving = ~gas_tank_empty;
end
endmodule
Unfortunately, this module has a bug. Implement a new version of this
module that fixes the bug.
|
module RefModule (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving
);
always @(*) begin
if (cpu_overheated)
shut_off_computer = 1;
else
shut_off_computer = 0;
end
always @(*) begin
if (~arrived)
keep_driving = !gas_tank_empty;
else
keep_driving = 1'b0;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic cpu_overheated, arrived, gas_tank_empty,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
logic [2:0] s = 3'b010;
assign {cpu_overheated, arrived, gas_tank_empty} = s;
initial begin
@(negedge clk) wavedrom_start("");
@(posedge clk) s <= 3'b010;
@(posedge clk) s <= 3'b100;
@(posedge clk) s <= 3'b100;
@(posedge clk) s <= 3'b001;
@(posedge clk) s <= 3'b000;
@(posedge clk) s <= 3'b100;
@(posedge clk) s <= 3'b110;
@(posedge clk) s <= 3'b111;
@(posedge clk) s <= 3'b111;
@(posedge clk) s <= 3'b111;
wavedrom_stop();
repeat(100) @(posedge clk, negedge clk)
s <= $urandom;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_shut_off_computer;
int errortime_shut_off_computer;
int errors_keep_driving;
int errortime_keep_driving;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic cpu_overheated;
logic arrived;
logic gas_tank_empty;
logic shut_off_computer_ref;
logic shut_off_computer_dut;
logic keep_driving_ref;
logic keep_driving_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,cpu_overheated,arrived,gas_tank_empty,shut_off_computer_ref,shut_off_computer_dut,keep_driving_ref,keep_driving_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.cpu_overheated,
.arrived,
.gas_tank_empty );
RefModule good1 (
.cpu_overheated,
.arrived,
.gas_tank_empty,
.shut_off_computer(shut_off_computer_ref),
.keep_driving(keep_driving_ref) );
TopModule top_module1 (
.cpu_overheated,
.arrived,
.gas_tank_empty,
.shut_off_computer(shut_off_computer_dut),
.keep_driving(keep_driving_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_shut_off_computer) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "shut_off_computer", stats1.errors_shut_off_computer, stats1.errortime_shut_off_computer);
else $display("Hint: Output '%s' has no mismatches.", "shut_off_computer");
if (stats1.errors_keep_driving) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "keep_driving", stats1.errors_keep_driving, stats1.errortime_keep_driving);
else $display("Hint: Output '%s' has no mismatches.", "keep_driving");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { shut_off_computer_ref, keep_driving_ref } === ( { shut_off_computer_ref, keep_driving_ref } ^ { shut_off_computer_dut, keep_driving_dut } ^ { shut_off_computer_ref, keep_driving_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (shut_off_computer_ref !== ( shut_off_computer_ref ^ shut_off_computer_dut ^ shut_off_computer_ref ))
begin if (stats1.errors_shut_off_computer == 0) stats1.errortime_shut_off_computer = $time;
stats1.errors_shut_off_computer = stats1.errors_shut_off_computer+1'b1; end
if (keep_driving_ref !== ( keep_driving_ref ^ keep_driving_dut ^ keep_driving_ref ))
begin if (stats1.errors_keep_driving == 0) stats1.errortime_keep_driving = $time;
stats1.errors_keep_driving = stats1.errors_keep_driving+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob133_2014_q3fsm |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input s
- input w
- output z
The module should implement a finite state machine with inputs s and w.
Assume that the FSM begins in a reset state called A, as depicted below.
The FSM remains in state A as long as s = 0, and it moves to state B when
s = 1. Once in state B the FSM examines the value of the input w in the
next three clock cycles. If w = 1 in exactly two of these clock cycles,
then the FSM has to set an output z to 1 in the following clock cycle.
Otherwise z has to be 0. The FSM continues checking w for the next three
clock cycles, and so on. Use as few states as possible. Note that the s
input is used only in state A, so you need to consider just the w input.
Assume reset is active high synchronous. Assume all sequential logic is
triggered on the positive edge of the clock.
|
module RefModule (
input clk,
input reset,
input s,
input w,
output reg z
);
parameter A=0, B=1, C=2, S10=3, S11=4, S20=5, S21=6, S22=7;
reg [2:0] state, next;
always @(posedge clk) begin
if (reset) state <= A;
else state <= next;
end
always_comb begin
case (state)
A: next = s ? B : A;
B: next = w ? S11 : S10;
C: next = w ? S11 : S10;
S10: next = w ? S21 : S20;
S11: next = w ? S22 : S21;
S20: next = B;
S21: next = w ? C : B;
S22: next = w ? B : C;
default: next = 'x;
endcase
end
assign z = (state == C);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic reset,
output logic s, w,
input tb_match
);
bit spulse_fail = 0;
bit failed = 0;
always @(posedge clk, negedge clk)
if (!tb_match) failed = 1;
initial begin
reset <= 1;
s <= 0;
w <= 0;
@(posedge clk);
@(posedge clk);
reset <= 0;
@(posedge clk);
@(posedge clk);
s <= 1;
repeat(200) @(posedge clk, negedge clk) begin
w <= $random;
end
reset <= 1;
@(posedge clk);
reset <= 0;
@(posedge clk);
@(posedge clk);
repeat(200) @(posedge clk, negedge clk) begin
w <= $random;
end
@(posedge clk)
spulse_fail <= failed;
repeat(500) @(negedge clk) begin
reset <= !($random & 63);
s <= !($random & 7);
w <= $random;
end
if (failed && !spulse_fail) begin
$display ("Hint: Your state machine should ignore input 's' after the state A to B transition.");
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic s;
logic w;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,s,w,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset,
.s,
.w );
RefModule good1 (
.clk,
.reset,
.s,
.w,
.z(z_ref) );
TopModule top_module1 (
.clk,
.reset,
.s,
.w,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob134_2014_q3c |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input x
- input y (3 bits)
- output Y0
- output z
The module should implement the output logic and next state logic for an
FSM using the table shown below. Note that the output Y0 is Y[0] of the
next state signal.
Present state y[2:0] | Next state Y[2:0] x=0, Next state Y[2:0] x=1 | Output z
000 | 000, 001 | 0
001 | 001, 100 | 0
010 | 010, 001 | 0
011 | 001, 010 | 1
100 | 011, 100 | 1
|
module RefModule (
input clk,
input x,
input [2:0] y,
output reg Y0,
output reg z
);
always_comb begin
case ({y[2:0], x})
4'h0: Y0 = 0;
4'h1: Y0 = 1;
4'h2: Y0 = 1;
4'h3: Y0 = 0;
4'h4: Y0 = 0;
4'h5: Y0 = 1;
4'h6: Y0 = 1;
4'h7: Y0 = 0;
4'h8: Y0 = 1;
4'h9: Y0 = 0;
default: Y0 = 1'bx;
endcase
case (y[2:0])
3'h0: z = 0;
3'h1: z = 0;
3'h2: z = 0;
3'h3: z = 1;
3'h4: z = 1;
default: z = 1'bx;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic x,
output logic [2:0] y
);
initial begin
repeat(200) @(posedge clk, negedge clk) begin
y <= $random;
x <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_Y0;
int errortime_Y0;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic x;
logic [2:0] y;
logic Y0_ref;
logic Y0_dut;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,x,y,Y0_ref,Y0_dut,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.x,
.y );
RefModule good1 (
.clk,
.x,
.y,
.Y0(Y0_ref),
.z(z_ref) );
TopModule top_module1 (
.clk,
.x,
.y,
.Y0(Y0_dut),
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_Y0) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Y0", stats1.errors_Y0, stats1.errortime_Y0);
else $display("Hint: Output '%s' has no mismatches.", "Y0");
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { Y0_ref, z_ref } === ( { Y0_ref, z_ref } ^ { Y0_dut, z_dut } ^ { Y0_ref, z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (Y0_ref !== ( Y0_ref ^ Y0_dut ^ Y0_ref ))
begin if (stats1.errors_Y0 == 0) stats1.errortime_Y0 = $time;
stats1.errors_Y0 = stats1.errors_Y0+1'b1; end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob135_m2014_q6b |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input y (3 bits)
- input w
- output Y1
The module should implement the state machine shown below:
A (0) --0--> B
A (0) --1--> A
B (0) --0--> C
B (0) --1--> D
C (0) --0--> E
C (0) --1--> D
D (0) --0--> F
D (0) --1--> A
E (1) --0--> E
E (1) --1--> D
F (1) --0--> C
F (1) --1--> D
The FSM should be implemented using three flip-flops and state codes
y = 000, 001, ..., 101 for states A, B, ..., F, respectively. Implement
just the next-state logic for y[1]. The output Y1 is y[1].
|
module RefModule (
input [2:0] y,
input w,
output reg Y1
);
always_comb begin
case ({y, w})
4'h0: Y1 = 1'b0;
4'h1: Y1 = 1'b0;
4'h2: Y1 = 1'b1;
4'h3: Y1 = 1'b1;
4'h4: Y1 = 1'b0;
4'h5: Y1 = 1'b1;
4'h6: Y1 = 1'b0;
4'h7: Y1 = 1'b0;
4'h8: Y1 = 1'b0;
4'h9: Y1 = 1'b1;
4'ha: Y1 = 1'b1;
4'hb: Y1 = 1'b1;
default: Y1 = 1'bx;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg [2:0] y,
output reg w
);
initial begin
repeat(100) @(posedge clk, negedge clk) begin
{y,w} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_Y1;
int errortime_Y1;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [2:0] y;
logic w;
logic Y1_ref;
logic Y1_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,y,w,Y1_ref,Y1_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.y,
.w );
RefModule good1 (
.y,
.w,
.Y1(Y1_ref) );
TopModule top_module1 (
.y,
.w,
.Y1(Y1_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_Y1) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Y1", stats1.errors_Y1, stats1.errortime_Y1);
else $display("Hint: Output '%s' has no mismatches.", "Y1");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { Y1_ref } === ( { Y1_ref } ^ { Y1_dut } ^ { Y1_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (Y1_ref !== ( Y1_ref ^ Y1_dut ^ Y1_ref ))
begin if (stats1.errors_Y1 == 0) stats1.errortime_Y1 = $time;
stats1.errors_Y1 = stats1.errors_Y1+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob136_m2014_q6 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input w
- output z
The module should implement the state machine shown below:
A (0) --0--> B
A (0) --1--> A
B (0) --0--> C
B (0) --1--> D
C (0) --0--> E
C (0) --1--> D
D (0) --0--> F
D (0) --1--> A
E (1) --0--> E
E (1) --1--> D
F (1) --0--> C
F (1) --1--> D
Assume all sequential logic is triggered on the positive edge of the
clock.
|
module RefModule (
input clk,
input reset,
input w,
output z
);
parameter A=0, B=1, C=2, D=3, E=4, F=5;
reg [2:0] state, next;
always @(posedge clk)
if (reset)
state <= A;
else
state <= next;
always_comb begin
case(state)
A: next = w ? A : B;
B: next = w ? D : C;
C: next = w ? D : E;
D: next = w ? A : F;
E: next = w ? D : E;
F: next = w ? D : C;
default: next = 'x;
endcase
end
assign z = (state == E || state == F);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic reset,
output logic w
);
initial begin
repeat(200) @(posedge clk, negedge clk) begin
w <= $random;
reset <= ($random & 15) == 0;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic w;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,w,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset,
.w );
RefModule good1 (
.clk,
.reset,
.w,
.z(z_ref) );
TopModule top_module1 (
.clk,
.reset,
.w,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob137_fsm_serial |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input in
- output done
In many (older) serial communications protocols, each data byte is sent
along with a start bit and a stop bit, to help the receiver delimit bytes
from the stream of bits. One common scheme is to use one start bit (0), 8
data bits, and 1 stop bit (1). The line is also at logic 1 when nothing
is being transmitted (idle).
Implement a finite state machine that will identify when bytes have been
correctly received when given a stream of bits. It needs to identify the
start bit, wait for all 8 data bits, then verify that the stop bit was
correct. If the stop bit does not appear when expected, the FSM must wait
until it finds a stop bit before attempting to receive the next byte.
Include a active-high synchronous reset. Note that the serial protocol
sends the least significant bit first.
Assume all sequential logic is triggered on the positive edge of the
clock.
|
module RefModule (
input clk,
input in,
input reset,
output done
);
parameter B0=0, B1=1, B2=2, B3=3, B4=4, B5=5, B6=6, B7=7, START=8, STOP=9, DONE=10, ERR=11;
reg [3:0] state;
reg [3:0] next;
always_comb begin
case (state)
START: next = in ? START : B0; // start bit is 0
B0: next = B1;
B1: next = B2;
B2: next = B3;
B3: next = B4;
B4: next = B5;
B5: next = B6;
B6: next = B7;
B7: next = STOP;
STOP: next = in ? DONE : ERR; // stop bit is 1. Idle state is 1.
DONE: next = in ? START : B0;
ERR: next = in ? START : ERR;
endcase
end
always @(posedge clk) begin
if (reset) state <= START;
else state <= next;
end
assign done = (state==DONE);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in,
output logic reset
);
initial begin
reset <= 1;
in <= 1;
@(posedge clk);
reset <= 0;
in <= 0;
repeat(9) @(posedge clk);
in <= 1;
@(posedge clk);
in <= 0;
repeat(9) @(posedge clk);
in <= 1;
@(posedge clk);
in <= 0;
repeat(10) @(posedge clk);
in <= 1;
@(posedge clk);
in <= 0;
repeat(10) @(posedge clk);
in <= 1;
@(posedge clk);
in <= 0;
repeat(9) @(posedge clk);
in <= 1;
@(posedge clk);
repeat(800) @(posedge clk, negedge clk) begin
in <= $random;
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_done;
int errortime_done;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic reset;
logic done_ref;
logic done_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,done_ref,done_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.reset );
RefModule good1 (
.clk,
.in,
.reset,
.done(done_ref) );
TopModule top_module1 (
.clk,
.in,
.reset,
.done(done_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_done) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "done", stats1.errors_done, stats1.errortime_done);
else $display("Hint: Output '%s' has no mismatches.", "done");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { done_ref } === ( { done_ref } ^ { done_dut } ^ { done_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (done_ref !== ( done_ref ^ done_dut ^ done_ref ))
begin if (stats1.errors_done == 0) stats1.errortime_done = $time;
stats1.errors_done = stats1.errors_done+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob138_2012_q2fsm |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input w
- output z
The module should implement the state machine shown below:
A (0) --1--> B
A (0) --0--> A
B (0) --1--> C
B (0) --0--> D
C (0) --1--> E
C (0) --0--> D
D (0) --1--> F
D (0) --0--> A
E (1) --1--> E
E (1) --0--> D
F (1) --1--> C
F (1) --0--> D
Reset resets into state A and is synchronous active-high. Assume all
sequential logic is triggered on the positive edge of the clock.
Use separate always blocks for the state table and the state flip-flops.
Describe the FSM output, which is called _z_, using either continuous
assignment statement(s) or an always block (at your discretion). Assign
any state codes that you wish to use.
|
module RefModule (
input clk,
input reset,
input w,
output z
);
parameter A=0,B=1,C=2,D=3,E=4,F=5;
reg[2:0] state, next;
always @(posedge clk)
if (reset) state <= A;
else state <= next;
always_comb begin
case (state)
A: next = w ? B : A;
B: next = w ? C : D;
C: next = w ? E : D;
D: next = w ? F : A;
E: next = w ? E : D;
F: next = w ? C : D;
default: next = 'x;
endcase
end
assign z = (state == E) || (state == F);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic reset,
output logic w
);
initial begin
repeat(200) @(negedge clk) begin
reset <= ($random & 'h1f) == 0;
w <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_z;
int errortime_z;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic w;
logic z_ref;
logic z_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,w,z_ref,z_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset,
.w );
RefModule good1 (
.clk,
.reset,
.w,
.z(z_ref) );
TopModule top_module1 (
.clk,
.reset,
.w,
.z(z_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_z) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "z", stats1.errors_z, stats1.errortime_z);
else $display("Hint: Output '%s' has no mismatches.", "z");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { z_ref } === ( { z_ref } ^ { z_dut } ^ { z_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (z_ref !== ( z_ref ^ z_dut ^ z_ref ))
begin if (stats1.errors_z == 0) stats1.errortime_z = $time;
stats1.errors_z = stats1.errors_z+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob139_2013_q2bfsm |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input resetn
- input x
- input y
- output f
- output g
Consider a finite state machine that is used to control some type of
motor. The FSM has inputs x and y, which come from the motor, and
produces outputs f and g, which control the motor. There is also a clock
input called clk and a reset input (synchronous, active low) called
resetn. The FSM has to work as follows. As long as the reset input is
asserted, the FSM stays in a beginning state, called state A. When the
reset signal is de-asserted, then after the next clock edge the FSM has
to set the output f to 1 for one clock cycle. Then, the FSM has to
monitor the x input. When x has produced the values 1, 0, 1 in three
successive clock cycles, then g should be set to 1 on the following clock
cycle. While maintaining g = 1 the FSM has to monitor the y input. If y
has the value 1 within at most two clock cycles, then the FSM should
maintain g = 1 permanently (that is, until reset). But if y does not
become 1 within two clock cycles, then the FSM should set g = 0
permanently (until reset). Assume all sequential logic is triggered on
the positive edge of the clock.
|
module RefModule (
input clk,
input resetn,
input x,
input y,
output f,
output g
);
parameter A=0, B=1, S0=2, S1=3, S10=4, G1=5, G2=6, P0=7, P1=8;
reg [3:0] state, next;
always @(posedge clk) begin
if (~resetn) state <= A;
else state <= next;
end
always_comb begin
case (state)
A: next = B;
B: next = S0;
S0: next = x ? S1 : S0;
S1: next = x ? S1 : S10;
S10: next = x? G1 : S0;
G1: next = y ? P1 : G2;
G2: next = y ? P1 : P0;
P0: next = P0;
P1: next = P1;
default: next = 'x;
endcase
end
assign f = (state == B);
assign g = (state == G1) || (state == G2) || (state == P1);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic resetn,
output logic x, y
);
initial begin
resetn = 0;
x = 0;
y = 0;
@(posedge clk);
@(posedge clk);
resetn = 1;
repeat(500) @(negedge clk) begin
resetn <= ($random & 31) != 0;
{x,y} <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_f;
int errortime_f;
int errors_g;
int errortime_g;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic resetn;
logic x;
logic y;
logic f_ref;
logic f_dut;
logic g_ref;
logic g_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,resetn,x,y,f_ref,f_dut,g_ref,g_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.resetn,
.x,
.y );
RefModule good1 (
.clk,
.resetn,
.x,
.y,
.f(f_ref),
.g(g_ref) );
TopModule top_module1 (
.clk,
.resetn,
.x,
.y,
.f(f_dut),
.g(g_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_f) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "f", stats1.errors_f, stats1.errortime_f);
else $display("Hint: Output '%s' has no mismatches.", "f");
if (stats1.errors_g) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "g", stats1.errors_g, stats1.errortime_g);
else $display("Hint: Output '%s' has no mismatches.", "g");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { f_ref, g_ref } === ( { f_ref, g_ref } ^ { f_dut, g_dut } ^ { f_ref, g_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (f_ref !== ( f_ref ^ f_dut ^ f_ref ))
begin if (stats1.errors_f == 0) stats1.errortime_f = $time;
stats1.errors_f = stats1.errors_f+1'b1; end
if (g_ref !== ( g_ref ^ g_dut ^ g_ref ))
begin if (stats1.errors_g == 0) stats1.errortime_g = $time;
stats1.errors_g = stats1.errors_g+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob140_fsm_hdlc |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input in
- output disc
- output flag
- output err
Synchronous HDLC framing involves decoding a continuous bit stream of
data to look for bit patterns that indicate the beginning and end of
frames (packets). Seeing exactly 6 consecutive 1s (i.e., 01111110) is a
"flag" that indicate frame boundaries. To avoid the data stream from
accidentally containing "flags", the sender inserts a zero after every 5
consecutive 1s which the receiver must detect and discard. We also need
to signal an error if there are 7 or more consecutive 1s. Create a
Moore-type finite state machine to recognize these three sequences:
(1) 0111110: Signal a bit needs to be discarded (disc).
(2) 01111110: Flag the beginning/end of a frame (flag).
(3) 01111111...: Error (7 or more 1s) (err).
When the FSM is reset, it should be in a state that behaves as though the
previous input were 0. The reset signal is active high synchronous. The
output signals should be asserted for a complete cycle beginning on the
clock cycle after the condition occurs. Assume all sequential
logic is triggered on the positive edge of the clock.
|
module RefModule (
input clk,
input reset,
input in,
output disc,
output flag,
output err
);
parameter [3:0] S0=0, S1=1, S2=2, S3=3, S4=4, S5=5, S6=6, SERR=7, SDISC=8, SFLAG=9;
reg [3:0] state, next;
assign disc = state == SDISC;
assign flag = state == SFLAG;
assign err = state == SERR;
always @(posedge clk) begin
case (state)
S0: state <= in ? S1 : S0;
S1: state <= in ? S2 : S0;
S2: state <= in ? S3 : S0;
S3: state <= in ? S4 : S0;
S4: state <= in ? S5 : S0;
S5: state <= in ? S6 : SDISC;
S6: state <= in ? SERR : SFLAG;
SERR: state <= in ? SERR : S0;
SFLAG: state <= in ? S1 : S0;
SDISC: state <= in ? S1 : S0;
default: state <= 'x;
endcase
if (reset) state <= S0;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic reset, in
);
initial begin
reset <= 1;
in <= 0;
@(posedge clk);
repeat(800) @(posedge clk, negedge clk) begin
reset <= !($random & 31);
in <= |($random&7);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_disc;
int errortime_disc;
int errors_flag;
int errortime_flag;
int errors_err;
int errortime_err;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic in;
logic disc_ref;
logic disc_dut;
logic flag_ref;
logic flag_dut;
logic err_ref;
logic err_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,in,disc_ref,disc_dut,flag_ref,flag_dut,err_ref,err_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset,
.in );
RefModule good1 (
.clk,
.reset,
.in,
.disc(disc_ref),
.flag(flag_ref),
.err(err_ref) );
TopModule top_module1 (
.clk,
.reset,
.in,
.disc(disc_dut),
.flag(flag_dut),
.err(err_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_disc) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "disc", stats1.errors_disc, stats1.errortime_disc);
else $display("Hint: Output '%s' has no mismatches.", "disc");
if (stats1.errors_flag) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "flag", stats1.errors_flag, stats1.errortime_flag);
else $display("Hint: Output '%s' has no mismatches.", "flag");
if (stats1.errors_err) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "err", stats1.errors_err, stats1.errortime_err);
else $display("Hint: Output '%s' has no mismatches.", "err");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { disc_ref, flag_ref, err_ref } === ( { disc_ref, flag_ref, err_ref } ^ { disc_dut, flag_dut, err_dut } ^ { disc_ref, flag_ref, err_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (disc_ref !== ( disc_ref ^ disc_dut ^ disc_ref ))
begin if (stats1.errors_disc == 0) stats1.errortime_disc = $time;
stats1.errors_disc = stats1.errors_disc+1'b1; end
if (flag_ref !== ( flag_ref ^ flag_dut ^ flag_ref ))
begin if (stats1.errors_flag == 0) stats1.errortime_flag = $time;
stats1.errors_flag = stats1.errors_flag+1'b1; end
if (err_ref !== ( err_ref ^ err_dut ^ err_ref ))
begin if (stats1.errors_err == 0) stats1.errortime_err = $time;
stats1.errors_err = stats1.errors_err+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob141_count_clock |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input ena
- output pm
- output hh (8 bits)
- output mm (8 bits)
- output ss (8 bits)
Create a set of counters suitable for use as a 12-hour clock (with am/pm
indicator). Your counters are clocked by a fast-running clk, with a pulse
on ena whenever your clock should increment (i.e., once per second, while
"clk" is much faster than once per second). The signal "pm" is asserted
if the clock is PM, or is otherwise AM. hh, mm, and ss are two BCD
(Binary- Coded Decimal) digits each for hours (01-12), minutes (00-59),
and seconds (00-59). Reset is the active high synchronous signal that
resets the clock to "12:00 AM." Reset has higher priority than enable and
can occur even when not enabled. Assume all sequential logic is triggered
on the positive edge of the clock.
|
module RefModule (
input clk,
input reset,
input ena,
output reg pm,
output reg [7:0] hh,
output reg [7:0] mm,
output reg [7:0] ss
);
wire [6:0] enable = {
{hh[7:0],mm[7:0],ss[7:0]}==24'h115959,
{hh[3:0],mm[7:0],ss[7:0]}==20'h95959,
{mm[7:0],ss[7:0]}==16'h5959,
{mm[3:0],ss[7:0]}==12'h959,
ss[7:0]==8'h59,
ss[3:0] == 4'h9,
1'b1};
always @(posedge clk)
if (reset)
{pm,hh,mm,ss} <= 25'h0120000;
else if (ena) begin
if (enable[0] && ss[3:0] == 9) ss[3:0] <= 0;
else if (enable[0]) ss[3:0] <= ss[3:0] + 1;
if (enable[1] && ss[7:4] == 4'h5) ss[7:4] <= 0;
else if (enable[1]) ss[7:4] <= ss[7:4] + 1;
if (enable[2] && mm[3:0] == 9) mm[3:0] <= 0;
else if (enable[2]) mm[3:0] <= mm[3:0] + 1;
if (enable[3] && mm[7:4] == 4'h5) mm[7:4] <= 0;
else if (enable[3]) mm[7:4] <= mm[7:4] + 1;
if (enable[4] && hh[3:0] == 4'h9) hh[3:0] <= 0;
else if (enable[4]) hh[3:0] <= hh[3:0] + 1;
if (enable[4] && hh[7:0] == 8'h12) hh[7:0] <= 8'h1;
else if (enable[5]) hh[7:4] <= hh[7:4] + 1;
if (enable[6]) pm <= ~pm;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset,
output reg ena,
input [7:0] hh_dut, mm_dut, ss_dut,
input pm_dut,
input tb_match,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
logic bcd_fail = 0;
logic reset_fail = 0;
always @(posedge clk) begin
if ((hh_dut[3:0] >= 4'ha) ||
(hh_dut[7:4] >= 4'ha) ||
(mm_dut[3:0] >= 4'ha) ||
(mm_dut[7:4] >= 4'ha) ||
(ss_dut[3:0] >= 4'ha) ||
(ss_dut[7:4] >= 4'ha))
bcd_fail <= 1'b1;
end
initial begin
reset <= 1;
ena <= 1;
wavedrom_start("Reset and count to 10");
reset_test();
repeat(12) @(posedge clk);
wavedrom_stop();
ena <= 1'b1;
reset <= 1'b1;
@(posedge clk);
@(posedge clk)
if (!tb_match) begin
$display("Hint: Clock seems to reset to %02x:%02x:%02x %s (Should be 12:00:00 AM).", hh_dut, mm_dut, ss_dut, pm_dut ? "PM": "AM");
reset_fail <= 1'b1;
end
reset <= 1'b0;
@(posedge clk);
@(posedge clk);
@(posedge clk);
ena <= 1'b0;
reset <= 1'b1;
@(posedge clk);
@(posedge clk)
if (!tb_match && !reset_fail)
$display("Hint: Reset has higher priority than enable and should occur even if not enabled.");
repeat(400) @(posedge clk, negedge clk) begin
reset <= !($random & 31);
ena <= !($random & 3);
end
reset <= 1;
@(posedge clk) begin
{reset, ena} <= 2'b1;
end
repeat(55) @(posedge clk);
wavedrom_start("Minute roll-over");
repeat(10) @(posedge clk);
wavedrom_stop();
repeat(3530) @(posedge clk);
wavedrom_start("Hour roll-over");
repeat(10) @(posedge clk);
wavedrom_stop();
repeat(39590) @(posedge clk);
wavedrom_start("PM roll-over");
repeat(10) @(posedge clk);
wavedrom_stop();
repeat(132745) @(posedge clk);
repeat(50) @(posedge clk, negedge clk) begin
ena <= !($random & 7);
end
reset <= 1'b1;
repeat(5) @(posedge clk);
if (bcd_fail)
$display("Hint: Non-BCD values detected. Are you sure you're using two-digit BCD representation for hh, mm, and ss?");
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_pm;
int errortime_pm;
int errors_hh;
int errortime_hh;
int errors_mm;
int errortime_mm;
int errors_ss;
int errortime_ss;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic ena;
logic pm_ref;
logic pm_dut;
logic [7:0] hh_ref;
logic [7:0] hh_dut;
logic [7:0] mm_ref;
logic [7:0] mm_dut;
logic [7:0] ss_ref;
logic [7:0] ss_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,ena,pm_ref,pm_dut,hh_ref,hh_dut,mm_ref,mm_dut,ss_ref,ss_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset,
.ena );
RefModule good1 (
.clk,
.reset,
.ena,
.pm(pm_ref),
.hh(hh_ref),
.mm(mm_ref),
.ss(ss_ref) );
TopModule top_module1 (
.clk,
.reset,
.ena,
.pm(pm_dut),
.hh(hh_dut),
.mm(mm_dut),
.ss(ss_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_pm) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "pm", stats1.errors_pm, stats1.errortime_pm);
else $display("Hint: Output '%s' has no mismatches.", "pm");
if (stats1.errors_hh) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "hh", stats1.errors_hh, stats1.errortime_hh);
else $display("Hint: Output '%s' has no mismatches.", "hh");
if (stats1.errors_mm) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "mm", stats1.errors_mm, stats1.errortime_mm);
else $display("Hint: Output '%s' has no mismatches.", "mm");
if (stats1.errors_ss) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "ss", stats1.errors_ss, stats1.errortime_ss);
else $display("Hint: Output '%s' has no mismatches.", "ss");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { pm_ref, hh_ref, mm_ref, ss_ref } === ( { pm_ref, hh_ref, mm_ref, ss_ref } ^ { pm_dut, hh_dut, mm_dut, ss_dut } ^ { pm_ref, hh_ref, mm_ref, ss_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (pm_ref !== ( pm_ref ^ pm_dut ^ pm_ref ))
begin if (stats1.errors_pm == 0) stats1.errortime_pm = $time;
stats1.errors_pm = stats1.errors_pm+1'b1; end
if (hh_ref !== ( hh_ref ^ hh_dut ^ hh_ref ))
begin if (stats1.errors_hh == 0) stats1.errortime_hh = $time;
stats1.errors_hh = stats1.errors_hh+1'b1; end
if (mm_ref !== ( mm_ref ^ mm_dut ^ mm_ref ))
begin if (stats1.errors_mm == 0) stats1.errortime_mm = $time;
stats1.errors_mm = stats1.errors_mm+1'b1; end
if (ss_ref !== ( ss_ref ^ ss_dut ^ ss_ref ))
begin if (stats1.errors_ss == 0) stats1.errortime_ss = $time;
stats1.errors_ss = stats1.errors_ss+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob142_lemmings2 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input bump_left
- input bump_right
- input ground
- output walk_left
- output walk_right
- output aaah
The game Lemmings involves critters with fairly simple brains. So simple
that we are going to model it using a finite state machine. In the
Lemmings' 2D world, Lemmings can be in one of two states: walking left
(walk_left is 1) or walking right (walk_right is 1). It will switch
directions if it hits an obstacle. In particular, if a Lemming is bumped
on the left (by receiving a 1 on bump_left), it will walk right. If it's
bumped on the right (by receiving a 1 on bump_right), it will walk left.
If it's bumped on both sides at the same time, it will still switch
directions.
In addition to walking left and right and changing direction when bumped,
when ground=0, the Lemming will fall and say "aaah!". When the ground
reappears (ground=1), the Lemming will resume walking in the same
direction as before the fall. Being bumped while falling does not affect
the walking direction, and being bumped in the same cycle as ground
disappears (but not yet falling), or when the ground reappears while
still falling, also does not affect the walking direction.
Implement a Moore state machine that models this behaviour. areset is
positive edge triggered asynchronous reseting the Lemming machine to walk
left. Assume all sequential logic is triggered on the positive edge of
the clock.
|
module RefModule (
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
parameter WL=0, WR=1, FALLL=2, FALLR=3;
reg [1:0] state;
reg [1:0] next;
always_comb begin
case (state)
WL: next = ground ? (bump_left ? WR : WL) : FALLL;
WR: next = ground ? (bump_right ? WL: WR) : FALLR;
FALLL: next = ground ? WL : FALLL;
FALLR: next = ground ? WR : FALLR;
endcase
end
always @(posedge clk, posedge areset) begin
if (areset) state <= WL;
else state <= next;
end
assign walk_left = (state==WL);
assign walk_right = (state==WR);
assign aaah = (state == FALLL) || (state == FALLR);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic areset,
output logic bump_left,
output logic bump_right,
output logic ground,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign areset = reset;
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1'b1;
{bump_left, bump_right, ground} <= 3'h1;
reset_test(1);
{bump_right, bump_left} <= 3'h0;
wavedrom_start("Falling");
repeat(3) @(posedge clk);
{bump_right, bump_left, ground} <= 0;
repeat(3) @(posedge clk);
{bump_right, bump_left, ground} <= 3;
repeat(2) @(posedge clk);
{bump_right, bump_left, ground} <= 0;
repeat(3) @(posedge clk);
{bump_right, bump_left, ground} <= 1;
repeat(2) @(posedge clk);
wavedrom_stop();
reset <= 1'b1;
@(posedge clk);
repeat(400) @(posedge clk, negedge clk) begin
{bump_right, bump_left} <= $random & $random;
ground <= |($random & 7);
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_walk_left;
int errortime_walk_left;
int errors_walk_right;
int errortime_walk_right;
int errors_aaah;
int errortime_aaah;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic areset;
logic bump_left;
logic bump_right;
logic ground;
logic walk_left_ref;
logic walk_left_dut;
logic walk_right_ref;
logic walk_right_dut;
logic aaah_ref;
logic aaah_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,bump_left,bump_right,ground,walk_left_ref,walk_left_dut,walk_right_ref,walk_right_dut,aaah_ref,aaah_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.areset,
.bump_left,
.bump_right,
.ground );
RefModule good1 (
.clk,
.areset,
.bump_left,
.bump_right,
.ground,
.walk_left(walk_left_ref),
.walk_right(walk_right_ref),
.aaah(aaah_ref) );
TopModule top_module1 (
.clk,
.areset,
.bump_left,
.bump_right,
.ground,
.walk_left(walk_left_dut),
.walk_right(walk_right_dut),
.aaah(aaah_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_walk_left) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "walk_left", stats1.errors_walk_left, stats1.errortime_walk_left);
else $display("Hint: Output '%s' has no mismatches.", "walk_left");
if (stats1.errors_walk_right) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "walk_right", stats1.errors_walk_right, stats1.errortime_walk_right);
else $display("Hint: Output '%s' has no mismatches.", "walk_right");
if (stats1.errors_aaah) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "aaah", stats1.errors_aaah, stats1.errortime_aaah);
else $display("Hint: Output '%s' has no mismatches.", "aaah");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { walk_left_ref, walk_right_ref, aaah_ref } === ( { walk_left_ref, walk_right_ref, aaah_ref } ^ { walk_left_dut, walk_right_dut, aaah_dut } ^ { walk_left_ref, walk_right_ref, aaah_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (walk_left_ref !== ( walk_left_ref ^ walk_left_dut ^ walk_left_ref ))
begin if (stats1.errors_walk_left == 0) stats1.errortime_walk_left = $time;
stats1.errors_walk_left = stats1.errors_walk_left+1'b1; end
if (walk_right_ref !== ( walk_right_ref ^ walk_right_dut ^ walk_right_ref ))
begin if (stats1.errors_walk_right == 0) stats1.errortime_walk_right = $time;
stats1.errors_walk_right = stats1.errors_walk_right+1'b1; end
if (aaah_ref !== ( aaah_ref ^ aaah_dut ^ aaah_ref ))
begin if (stats1.errors_aaah == 0) stats1.errortime_aaah = $time;
stats1.errors_aaah = stats1.errors_aaah+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob143_fsm_onehot |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input in
- input state (10 bits)
- output next_state (10 bits)
- output out1
- output out2
Given the follow state machine with 1 input and 2 outputs (the outputs
are given as "(out1, out2)"):
S0 (0, 0) --0--> S0
S0 (0, 0) --1--> S1
S1 (0, 0) --0--> S0
S1 (0, 0) --1--> S2
S2 (0, 0) --0--> S0
S2 (0, 0) --1--> S3
S3 (0, 0) --0--> S0
S3 (0, 0) --1--> S4
S4 (0, 0) --0--> S0
S4 (0, 0) --1--> S5
S5 (0, 0) --0--> S8
S5 (0, 0) --1--> S6
S6 (0, 0) --0--> S9
S6 (0, 0) --1--> S7
S7 (0, 1) --0--> S0
S7 (0, 1) --1--> S7
S8 (1, 0) --0--> S0
S8 (1, 0) --1--> S1
S9 (1, 1) --0--> S0
S9 (1, 1) --1--> S1
Suppose this state machine uses one-hot encoding, where state[0] through
state[9] correspond to the states S0 though S9, respectively. The outputs
are zero unless otherwise specified.
The module should implement the state transition logic and output logic
portions of the state machine (but not the state flip-flops). You are
given the current state in state[9:0] and must produce next_state[9:0]
and the two outputs. Derive the logic equations by inspection assuming a
one-hot encoding.
|
module RefModule (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2
);
assign out1 = state[8] | state[9];
assign out2 = state[7] | state[9];
assign next_state[0] = !in && (|state[4:0] | state[7] | state[8] | state[9]);
assign next_state[1] = in && (state[0] | state[8] | state[9]);
assign next_state[2] = in && state[1];
assign next_state[3] = in && state[2];
assign next_state[4] = in && state[3];
assign next_state[5] = in && state[4];
assign next_state[6] = in && state[5];
assign next_state[7] = in && (state[6] | state[7]);
assign next_state[8] = !in && state[5];
assign next_state[9] = !in && state[6];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in,
output logic [9:0] state,
input tb_match,
input [9:0] next_state_ref,
input [9:0] next_state_dut,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
int errored1 = 0;
int errored2 = 0;
int onehot_error = 0;
reg [9:0] state_error = 10'h0;
initial begin
repeat(2) @(posedge clk);
forever @(posedge clk, negedge clk)
state_error <= state_error | (next_state_ref^next_state_dut);
end
initial begin
state <= 0;
@(negedge clk) wavedrom_start();
for (int i=0;i<10;i++) begin
@(negedge clk, posedge clk);
state <= 1<< i;
in <= 0;
end
for (int i=0;i<10;i++) begin
@(negedge clk, posedge clk);
state <= 1<< i;
in <= 1;
end
@(negedge clk) wavedrom_stop();
// Test the one-hot cases first.
repeat(200) @(posedge clk, negedge clk) begin
state <= 1<< ($unsigned($random) % 10);
in <= $random;
if (!tb_match) onehot_error++;
end
// Two-hot.
errored1 = 0;
repeat(400) @(posedge clk, negedge clk) begin
state <= (1<< ($unsigned($random) % 10)) | (1<< ($unsigned($random) % 10));
in <= $random;
if (!tb_match)
errored1++;
end
if (!onehot_error && errored1)
$display ("Hint: Your circuit passed when given only one-hot inputs, but not with two-hot inputs.");
// Random.
errored2 = 0;
repeat(800) @(posedge clk, negedge clk) begin
state <= $random;
in <= $random;
if (!tb_match)
errored2++;
end
if (!onehot_error && errored2)
$display ("Hint: Your circuit passed when given only one-hot inputs, but not with random inputs.");
if (!onehot_error && (errored1 || errored2))
$display("Hint: Are you doing something more complicated than deriving state transition equations by inspection?\n");
for (int i=0;i<$bits(state_error);i++)
$display("Hint: next_state[%0d] is %s.", i, (state_error[i] === 1'b0) ? "correct": "incorrect");
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_next_state;
int errortime_next_state;
int errors_out1;
int errortime_out1;
int errors_out2;
int errortime_out2;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic [9:0] state;
logic [9:0] next_state_ref;
logic [9:0] next_state_dut;
logic out1_ref;
logic out1_dut;
logic out2_ref;
logic out2_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,in,state,next_state_ref,next_state_dut,out1_ref,out1_dut,out2_ref,out2_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.state );
RefModule good1 (
.in,
.state,
.next_state(next_state_ref),
.out1(out1_ref),
.out2(out2_ref) );
TopModule top_module1 (
.in,
.state,
.next_state(next_state_dut),
.out1(out1_dut),
.out2(out2_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_next_state) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "next_state", stats1.errors_next_state, stats1.errortime_next_state);
else $display("Hint: Output '%s' has no mismatches.", "next_state");
if (stats1.errors_out1) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out1", stats1.errors_out1, stats1.errortime_out1);
else $display("Hint: Output '%s' has no mismatches.", "out1");
if (stats1.errors_out2) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out2", stats1.errors_out2, stats1.errortime_out2);
else $display("Hint: Output '%s' has no mismatches.", "out2");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { next_state_ref, out1_ref, out2_ref } === ( { next_state_ref, out1_ref, out2_ref } ^ { next_state_dut, out1_dut, out2_dut } ^ { next_state_ref, out1_ref, out2_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (next_state_ref !== ( next_state_ref ^ next_state_dut ^ next_state_ref ))
begin if (stats1.errors_next_state == 0) stats1.errortime_next_state = $time;
stats1.errors_next_state = stats1.errors_next_state+1'b1; end
if (out1_ref !== ( out1_ref ^ out1_dut ^ out1_ref ))
begin if (stats1.errors_out1 == 0) stats1.errortime_out1 = $time;
stats1.errors_out1 = stats1.errors_out1+1'b1; end
if (out2_ref !== ( out2_ref ^ out2_dut ^ out2_ref ))
begin if (stats1.errors_out2 == 0) stats1.errortime_out2 = $time;
stats1.errors_out2 = stats1.errors_out2+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob144_conwaylife |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input load
- input data (256 bits)
- output q (256 bits)
The module should implemement a "game" played on a two-dimensional grid
of cells, where each cell is either 1 (alive) or 0 (dead). At each time
step, each cell changes state depending on how many neighbours it has:
(1) 0-1 neighbour: Cell becomes 0.
(2) 2 neighbours: Cell state does not change.
(3) 3 neighbours: Cell becomes 1.
(4) 4+ neighbours: Cell becomes 0.
The game is formulated for an infinite grid. In this circuit, we will use
a 16x16 grid. To make things more interesting, we will use a 16x16
toroid, where the sides wrap around to the other side of the grid. For
example, the corner cell (0,0) has 8 neighbours: (15,1), (15,0), (15,15),
(0,1), (0,15), (1,1), (1,0), and (1,15). The 16x16 grid is represented by
a length 256 vector, where each row of 16 cells is represented by a
sub-vector: q[15:0] is row 0, q[31:16] is row 1, etc.
(1) load: Loads data into q at the next clock edge, for loading initial
state. Active high synchronous.
(2) q: The 16x16 current state of the game, updated every clock cycle.
The game state should advance by one timestep every clock cycle. Assume
all sequential logic is triggered on the positive edge of the clock.
|
module RefModule (
input clk,
input load,
input [255:0] data,
output reg [255:0] q
);
logic [323:0] q_pad;
always@(*) begin
for (int i=0;i<16;i++)
q_pad[18*(i+1)+1 +: 16] = q[16*i +: 16];
q_pad[1 +: 16] = q[16*15 +: 16];
q_pad[18*17+1 +: 16] = q[0 +: 16];
for (int i=0; i<18; i++) begin
q_pad[i*18] = q_pad[i*18+16];
q_pad[i*18+17] = q_pad[i*18+1];
end
end
always @(posedge clk) begin
for (int i=0;i<16;i++)
for (int j=0;j<16;j++) begin
q[i*16+j] <=
((q_pad[(i+1)*18+j+1 -1+18] + q_pad[(i+1)*18+j+1 +18] + q_pad[(i+1)*18+j+1 +1+18] +
q_pad[(i+1)*18+j+1 -1] + q_pad[(i+1)*18+j+1+1] +
q_pad[(i+1)*18+j+1 -1-18] + q_pad[(i+1)*18+j+1 -18] + q_pad[(i+1)*18+j+1 +1-18]) & 3'h7 | q[i*16+j]) == 3'h3;
end
if (load)
q <= data;
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
input tb_match,
input [255:0] q_ref,
input [255:0] q_dut,
output reg load,
output reg[255:0] data
);
logic errored = 0;
int blinker_cycle = 0;
initial begin
data <= 3'h7; // Simple blinker, period 2
load <= 1;
@(posedge clk);
load <= 0;
data <= 4'hx;
errored = 0;
blinker_cycle = 0;
repeat(5) @(posedge clk) begin
blinker_cycle++;
if (!tb_match) begin
if (!errored) begin
errored = 1;
$display("Hint: The first test case is a blinker (initial state = 256'h7). First mismatch occurred at cycle %0d.\nHint:", blinker_cycle);
end
end
if (errored) begin
$display ("Hint: Cycle %0d: Your game state Reference game state", blinker_cycle);
for (int i=15;i>=0;i--) begin
$display("Hint: q[%3d:%3d] %016b %016b", i*16+15, i*16, q_dut [ i*16 +: 16 ], q_ref[ i*16 +: 16 ]);
end
$display("Hint:\nHint:\n");
end
end
data <= 48'h000200010007; // Glider, Traveling diagonal down-right.
load <= 1;
@(posedge clk);
@(posedge clk);
@(posedge clk);
load <= 0;
data <= 4'hx;
errored = 0;
blinker_cycle = 0;
repeat(100) @(posedge clk) begin
blinker_cycle++;
if (!tb_match) begin
if (!errored) begin
errored = 1;
$display("Hint: The second test case is a glider (initial state = 256'h000200010007). First mismatch occurred at cycle %0d.\nHint:", blinker_cycle);
end
end
if (errored && blinker_cycle < 20) begin
$display ("Hint: Cycle %0d: Your game state Reference game state", blinker_cycle);
for (int i=15;i>=0;i--) begin
$display("Hint: q[%3d:%3d] %016b %016b", i*16+15, i*16, q_dut [ i*16 +: 16 ], q_ref[ i*16 +: 16 ]);
end
$display("Hint:\nHint:\n");
end
end
data <= 48'h0040001000ce; // Acorn
load <= 1;
@(posedge clk);
load <= 0;
repeat(2000) @(posedge clk);
data <= {$random,$random,$random,$random,$random,$random,$random,$random}; // Some random test cases.
load <= 1;
@(posedge clk);
load <= 0;
repeat(200) @(posedge clk);
data <= {$random,$random,$random,$random,$random,$random,$random,$random}& // Random with more zeros.
{$random,$random,$random,$random,$random,$random,$random,$random}&
{$random,$random,$random,$random,$random,$random,$random,$random}&
{$random,$random,$random,$random,$random,$random,$random,$random};
load <= 1;
@(posedge clk);
load <= 0;
repeat(200) @(posedge clk);
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic load;
logic [255:0] data;
logic [255:0] q_ref;
logic [255:0] q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,load,data,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.load,
.data );
RefModule good1 (
.clk,
.load,
.data,
.q(q_ref) );
TopModule top_module1 (
.clk,
.load,
.data,
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref } === ( { q_ref } ^ { q_dut } ^ { q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob145_circuit8 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clock
- input a
- output p
- output q
The module should implement a sequential circuit. Read the simulation
waveforms to determine what the circuit does, then implement it.
time clk a p q
0ns 0 0 x x
5ns 0 0 x x
10ns 0 0 x x
15ns 0 0 x x
20ns 0 0 x x
25ns 1 0 0 x
30ns 1 0 0 x
35ns 1 0 0 x
40ns 1 0 0 x
45ns 1 0 0 x
50ns 1 0 0 x
55ns 0 0 0 0
60ns 0 0 0 0
65ns 0 0 0 0
70ns 0 1 0 0
75ns 0 0 0 0
80ns 0 1 0 0
85ns 1 0 0 0
90ns 1 1 1 0
95ns 1 0 0 0
100ns 1 1 1 0
105ns 1 0 0 0
110ns 1 1 1 0
115ns 0 0 1 1
120ns 0 1 1 1
125ns 0 0 1 1
130ns 0 1 1 1
135ns 0 0 1 1
140ns 0 0 1 1
145ns 1 0 0 1
150ns 1 0 0 1
155ns 1 0 0 1
160ns 1 0 0 1
165ns 1 1 1 1
170ns 1 0 0 1
175ns 0 1 0 0
180ns 0 0 0 0
185ns 0 1 0 0
190ns 0 0 0 0
|
module RefModule (
input clock,
input a,
output reg p,
output reg q
);
always @(negedge clock)
q <= a;
always @(*)
if (clock)
p = a;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic clock=0,
output logic a,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
always begin
repeat(3) @(posedge clk);
clock = ~clock;
end
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
a <= 0;
@(negedge clock) {a} <= 0;
@(negedge clk) wavedrom_start("Unknown circuit");
@(posedge clk) {a} <= 0;
repeat(14) @(posedge clk,negedge clk) a <= ~a;
repeat(5) @(posedge clk, negedge clk);
repeat(8) @(posedge clk,negedge clk) a <= ~a;
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
a <= $urandom;
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_p;
int errortime_p;
int errors_q;
int errortime_q;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic clock;
logic a;
logic p_ref;
logic p_dut;
logic q_ref;
logic q_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clock,a,p_ref,p_dut,q_ref,q_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.clock,
.a );
RefModule good1 (
.clock,
.a,
.p(p_ref),
.q(q_ref) );
TopModule top_module1 (
.clock,
.a,
.p(p_dut),
.q(q_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_p) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "p", stats1.errors_p, stats1.errortime_p);
else $display("Hint: Output '%s' has no mismatches.", "p");
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { p_ref, q_ref } === ( { p_ref, q_ref } ^ { p_dut, q_dut } ^ { p_ref, q_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (p_ref !== ( p_ref ^ p_dut ^ p_ref ))
begin if (stats1.errors_p == 0) stats1.errortime_p = $time;
stats1.errors_p = stats1.errors_p+1'b1; end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob146_fsm_serialdata |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input in
- input reset
- output out_byte (8 bits)
- output done
In many (older) serial communications protocols, each data byte is sent
along with a start bit and a stop bit, to help the receiver delimit bytes
from the stream of bits. One common scheme is to use one start bit (0), 8
data bits, and 1 stop bit (1). The line is also at logic 1 when nothing
is being transmitted (idle). Design a finite state machine that will
identify when bytes have been correctly received when given a stream of
bits. It needs to identify the start bit, wait for all 8 data bits, then
verify that the stop bit was correct. The module will also output the
correctly-received data byte. `out_byte` needs to be valid when `done` is
1, and is don't-care otherwise. If the stop bit does not appear when
expected, the FSM must wait until it finds a stop bit before attempting
to receive the next byte. Include a active-high synchronous reset. Note
that the serial protocol sends the least significant bit first. It should
assert done each time it finds a stop bit. Assume all sequential logic is
triggered on the positive edge of the clock.
|
module RefModule (
input clk,
input in,
input reset,
output [7:0] out_byte,
output done
);
parameter B0=0, B1=1, B2=2, B3=3, B4=4, B5=5, B6=6, B7=7, START=8, STOP=9, DONE=10, ERR=11;
reg [3:0] state;
reg [3:0] next;
reg [9:0] byte_r;
always_comb begin
case (state)
START: next = in ? START : B0; // start bit is 0
B0: next = B1;
B1: next = B2;
B2: next = B3;
B3: next = B4;
B4: next = B5;
B5: next = B6;
B6: next = B7;
B7: next = STOP;
STOP: next = in ? DONE : ERR; // stop bit is 1. Idle state is 1.
DONE: next = in ? START : B0;
ERR: next = in ? START : ERR;
endcase
end
always @(posedge clk) begin
if (reset) state <= START;
else state <= next;
end
always @(posedge clk) begin
byte_r <= {in, byte_r[9:1]};
end
assign done = (state==DONE);
assign out_byte = done ? byte_r[8:1] : 8'hx;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic in,
output logic reset
);
initial begin
reset <= 1;
in <= 1;
@(posedge clk);
reset <= 0;
in <= 0;
repeat(9) @(posedge clk);
in <= 1;
@(posedge clk);
in <= 0;
repeat(9) @(posedge clk);
in <= 1;
@(posedge clk);
in <= 0;
repeat(10) @(posedge clk);
in <= 1;
@(posedge clk);
in <= 0;
repeat(10) @(posedge clk);
in <= 1;
@(posedge clk);
in <= 0;
repeat(9) @(posedge clk);
in <= 1;
@(posedge clk);
repeat(800) @(posedge clk, negedge clk) begin
in <= $random;
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_byte;
int errortime_out_byte;
int errors_done;
int errortime_done;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic in;
logic reset;
logic [7:0] out_byte_ref;
logic [7:0] out_byte_dut;
logic done_ref;
logic done_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_byte_ref,out_byte_dut,done_ref,done_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.reset );
RefModule good1 (
.clk,
.in,
.reset,
.out_byte(out_byte_ref),
.done(done_ref) );
TopModule top_module1 (
.clk,
.in,
.reset,
.out_byte(out_byte_dut),
.done(done_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_byte) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_byte", stats1.errors_out_byte, stats1.errortime_out_byte);
else $display("Hint: Output '%s' has no mismatches.", "out_byte");
if (stats1.errors_done) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "done", stats1.errors_done, stats1.errortime_done);
else $display("Hint: Output '%s' has no mismatches.", "done");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_byte_ref, done_ref } === ( { out_byte_ref, done_ref } ^ { out_byte_dut, done_dut } ^ { out_byte_ref, done_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_byte_ref !== ( out_byte_ref ^ out_byte_dut ^ out_byte_ref ))
begin if (stats1.errors_out_byte == 0) stats1.errortime_out_byte = $time;
stats1.errors_out_byte = stats1.errors_out_byte+1'b1; end
if (done_ref !== ( done_ref ^ done_dut ^ done_ref ))
begin if (stats1.errors_done == 0) stats1.errortime_done = $time;
stats1.errors_done = stats1.errors_done+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob147_circuit10 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input a
- input b
- output q
- output state
The module should implement a sequential circuit. The circuit consists of
combinational logic and one bit of memory (i.e., one flip-flop). The
output of the flip-flop has been made observable through the output
state. Assume all sequential logic is triggered on the positive edge of
the clock.
Read the simulation waveforms to determine what the circuit does, then
implement it.
time clk a b state q
0ns 0 1 x x x
5ns 1 1 x x x
10ns 0 0 0 x x
15ns 1 0 0 0 0
20ns 0 0 0 0 0
25ns 1 0 0 0 0
30ns 0 0 0 0 0
35ns 1 0 0 0 0
40ns 0 0 0 0 0
45ns 1 0 1 0 1
50ns 0 0 1 0 1
55ns 1 1 0 0 1
60ns 0 1 0 0 1
65ns 1 1 1 0 0
70ns 0 1 1 0 0
75ns 1 0 0 1 1
80ns 0 0 0 1 1
85ns 1 1 1 0 0
90ns 0 1 1 0 0
95ns 1 1 1 1 1
100ns 0 1 1 1 1
105ns 1 1 1 1 1
110ns 0 1 1 1 1
115ns 1 1 0 1 0
120ns 0 1 0 1 0
125ns 1 0 1 1 0
130ns 0 0 1 1 0
135ns 1 0 0 1 1
140ns 0 0 0 1 1
145ns 1 0 0 0 0
150ns 0 0 0 0 0
155ns 1 0 0 0 0
160ns 0 0 0 0 0
165ns 1 0 0 0 0
170ns 0 0 0 0 0
175ns 1 0 0 0 0
180ns 0 0 0 0 0
185ns 1 0 0 0 0
190ns 0 0 0 0 0
|
module RefModule (
input clk,
input a,
input b,
output q,
output state
);
reg c;
always @(posedge clk)
c <= a&b | a&c | b&c;
assign q = a^b^c;
assign state = c;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic a,
output logic b,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
a <= 1;
@(negedge clk) {a,b} <= 0;
@(negedge clk) wavedrom_start("Unknown circuit");
repeat(3) @(posedge clk);
{a,b} <= 1;
@(posedge clk) {a,b} <= 2;
@(posedge clk) {a,b} <= 3;
@(posedge clk) {a,b} <= 0;
@(posedge clk) {a,b} <= 3;
@(posedge clk) {a,b} <= 3;
@(posedge clk) {a,b} <= 3;
@(posedge clk) {a,b} <= 2;
@(posedge clk) {a,b} <= 1;
@(posedge clk) {a,b} <= 0;
@(posedge clk) {a,b} <= 0;
@(posedge clk) {a,b} <= 0;
@(negedge clk);
wavedrom_stop();
repeat(200) @(posedge clk, negedge clk)
a <= &((5)'($urandom));
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_q;
int errortime_q;
int errors_state;
int errortime_state;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic a;
logic b;
logic q_ref;
logic q_dut;
logic state_ref;
logic state_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,a,b,q_ref,q_dut,state_ref,state_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.a,
.b );
RefModule good1 (
.clk,
.a,
.b,
.q(q_ref),
.state(state_ref) );
TopModule top_module1 (
.clk,
.a,
.b,
.q(q_dut),
.state(state_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_q) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "q", stats1.errors_q, stats1.errortime_q);
else $display("Hint: Output '%s' has no mismatches.", "q");
if (stats1.errors_state) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "state", stats1.errors_state, stats1.errortime_state);
else $display("Hint: Output '%s' has no mismatches.", "state");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { q_ref, state_ref } === ( { q_ref, state_ref } ^ { q_dut, state_dut } ^ { q_ref, state_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (q_ref !== ( q_ref ^ q_dut ^ q_ref ))
begin if (stats1.errors_q == 0) stats1.errortime_q = $time;
stats1.errors_q = stats1.errors_q+1'b1; end
if (state_ref !== ( state_ref ^ state_dut ^ state_ref ))
begin if (stats1.errors_state == 0) stats1.errortime_state = $time;
stats1.errors_state = stats1.errors_state+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob148_2013_q2afsm |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input resetn
- input r (3 bits)
- output g (3 bits)
The module should implement the FSM described by the state diagram shown
below:
A --r0=0,r1=0,r2=0--> A
A -------r0=1-------> B
A -----r0=0,r1=1----> C
A --r0=0,r1=0,r2=0--> D
B (g0=1) -------r0=1-------> B
B (g0=1) -------r0=0-------> A
C (g1=1) -------r1=1-------> C
C (g1=1) -------r1=0-------> A
Resetn is an active-low synchronous reset that resets into state A. This
FSM acts as an arbiter circuit, which controls access to some type of
resource by three requesting devices. Each device makes its request for
the resource by setting a signal _r[i]_ = 1, where _r[i]_ is either
_r[0]_, _r[1]_, or _r[2]_. Each r[i] is an input signal to the FSM, and
represents one of the three devices. The FSM stays in state _A_ as long
as there are no requests. When one or more request occurs, then the FSM
decides which device receives a grant to use the resource and changes to
a state that sets that device's _g[i]_ signal to 1. Each _g[i]_ is an
output from the FSM. There is a priority system, in that device 0 has a
higher priority than device 1, and device 2 has the lowest priority.
Hence, for example, device 2 will only receive a grant if it is the only
device making a request when the FSM is in state _A_. Once a device, _i_,
is given a grant by the FSM, that device continues to receive the grant
as long as its request, _r[i]_ = 1.
Implement a module that represents this FSM. Use separate always blocks
for the state table and the state flip-flops, as done in lectures.
Describe the FSM outputs, _g[i]_, using either continuous assignment
statement(s) or an always block (at your discretion). Assign any state
codes that you wish to use. Assume all sequential logic is triggered on
the positive edge of the clock.
|
module RefModule (
input clk,
input resetn,
input [2:0] r,
output [2:0] g
);
parameter A=0, B=1, C=2, D=3;
reg [1:0] state, next;
always @(posedge clk) begin
if (~resetn) state <= A;
else state <= next;
end
always@(state,r) begin
case (state)
A: if (r[0]) next = B;
else if (r[1]) next = C;
else if (r[2]) next = D;
else next = A;
B: next = r[0] ? B : A;
C: next = r[1] ? C : A;
D: next = r[2] ? D : A;
default: next = 'x;
endcase
end
assign g[0] = (state == B);
assign g[1] = (state == C);
assign g[2] = (state == D);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic resetn,
output logic [2:0] r,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign resetn = ~reset;
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1;
r <= 0;
@(posedge clk);
r <= 1;
reset_test();
r <= 0;
wavedrom_start("");
@(posedge clk) r <= 0;
@(posedge clk) r <= 7;
@(posedge clk) r <= 7;
@(posedge clk) r <= 7;
@(posedge clk) r <= 6;
@(posedge clk) r <= 6;
@(posedge clk) r <= 6;
@(posedge clk) r <= 4;
@(posedge clk) r <= 4;
@(posedge clk) r <= 4;
@(posedge clk) r <= 0;
@(posedge clk) r <= 0;
@(posedge clk) r <= 4;
@(posedge clk) r <= 6;
@(posedge clk) r <= 7;
@(posedge clk) r <= 7;
@(posedge clk) r <= 7;
@(negedge clk);
wavedrom_stop();
@(posedge clk);
reset <= 0;
@(posedge clk);
@(posedge clk);
repeat(500) @(negedge clk) begin
reset <= ($random & 63) == 0;
r <= $random;
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_g;
int errortime_g;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic resetn;
logic [2:0] r;
logic [2:0] g_ref;
logic [2:0] g_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,resetn,r,g_ref,g_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.resetn,
.r );
RefModule good1 (
.clk,
.resetn,
.r,
.g(g_ref) );
TopModule top_module1 (
.clk,
.resetn,
.r,
.g(g_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_g) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "g", stats1.errors_g, stats1.errortime_g);
else $display("Hint: Output '%s' has no mismatches.", "g");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { g_ref } === ( { g_ref } ^ { g_dut } ^ { g_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (g_ref !== ( g_ref ^ g_dut ^ g_ref ))
begin if (stats1.errors_g == 0) stats1.errortime_g = $time;
stats1.errors_g = stats1.errors_g+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob149_ece241_2013_q4 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input s (3 bits)
- output fr2
- output fr1
- output fr0
- output dfr
A large reservior of water serves several users. In order to keep the
level of water succificently high, three sensors are placed vertically at
5-inch intervals. When the water level is above the highest sensor s[2],
the input flow rate should be zero. When the level is below the lowest
sensor s[0], the flow rate should be at maximum (both Nominal flow valve
and Supplemental flow valve opened). The flow rate when the level is
between the upper and lower sensors is determined by two factors: the
water level and the level previous to the last sensor change. Each water
level has a nominal flow rate associated with it as show in the table
below. If the sensor change indicates that the previous level was lower
than the current level, the flow rate should be increased by opening the
Supplemental flow valve (controlled by dfr).
Water Level | Sensors Asserted | Nominal Flow Rate Inputs to be Asserted
Above s[2] | s[0], s[1], s[2] | None
Between s[2] and s[1] | s[0], s[1] | fr0
Between s[1] and s[0] | s[0] | fr0, fr1
Below s[0] | None | fr0, fr1, fr2
Also include an active-high synchronous reset that resets the state
machine to a state equivalent to if the water level had been low for a
long time (no sensors asserted, and all four outputs asserted).
|
module RefModule (
input clk,
input reset,
input [2:0] s,
output reg fr2,
output reg fr1,
output reg fr0,
output reg dfr
);
parameter A2=0, B1=1, B2=2, C1=3, C2=4, D1=5;
reg [2:0] state, next;
always @(posedge clk) begin
if (reset) state <= A2;
else state <= next;
end
always@(*) begin
case (state)
A2: next = s[0] ? B1 : A2;
B1: next = s[1] ? C1 : (s[0] ? B1 : A2);
B2: next = s[1] ? C1 : (s[0] ? B2 : A2);
C1: next = s[2] ? D1 : (s[1] ? C1 : B2);
C2: next = s[2] ? D1 : (s[1] ? C2 : B2);
D1: next = s[2] ? D1 : C2;
default: next = 'x;
endcase
end
reg [3:0] fr;
assign {fr2, fr1, fr0, dfr} = fr;
always_comb begin
case (state)
A2: fr = 4'b1111;
B1: fr = 4'b0110;
B2: fr = 4'b0111;
C1: fr = 4'b0010;
C2: fr = 4'b0011;
D1: fr = 4'b0000;
default: fr = 'x;
endcase
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic reset,
output logic [2:0] s,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
wire [3:0][2:0] val = { 3'h7, 3'h3, 3'h1, 3'h0 };
integer sval;
initial begin
reset <= 1;
s <= 1;
reset_test();
@(posedge clk) s <= 0;
@(posedge clk) s <= 0;
@(negedge clk) wavedrom_start("Water rises to highest level, then down to lowest level.");
@(posedge clk) s <= 0;
@(posedge clk) s <= 1;
@(posedge clk) s <= 3;
@(posedge clk) s <= 7;
@(posedge clk) s <= 7;
@(posedge clk) s <= 3;
@(posedge clk) s <= 3;
@(posedge clk) s <= 1;
@(posedge clk) s <= 1;
@(posedge clk) s <= 0;
@(posedge clk) s <= 0;
@(negedge clk) wavedrom_stop();
sval = 0;
repeat(1000) begin
@(posedge clk);
sval = sval + (sval == 3 ? 0 : $random&1);
s <= val[sval];
@(negedge clk);
sval = sval - (sval == 0 ? 0 : $random&1);
s <= val[sval];
end
$finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_fr2;
int errortime_fr2;
int errors_fr1;
int errortime_fr1;
int errors_fr0;
int errortime_fr0;
int errors_dfr;
int errortime_dfr;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic [2:0] s;
logic fr2_ref;
logic fr2_dut;
logic fr1_ref;
logic fr1_dut;
logic fr0_ref;
logic fr0_dut;
logic dfr_ref;
logic dfr_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,s,fr2_ref,fr2_dut,fr1_ref,fr1_dut,fr0_ref,fr0_dut,dfr_ref,dfr_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset,
.s );
RefModule good1 (
.clk,
.reset,
.s,
.fr2(fr2_ref),
.fr1(fr1_ref),
.fr0(fr0_ref),
.dfr(dfr_ref) );
TopModule top_module1 (
.clk,
.reset,
.s,
.fr2(fr2_dut),
.fr1(fr1_dut),
.fr0(fr0_dut),
.dfr(dfr_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_fr2) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "fr2", stats1.errors_fr2, stats1.errortime_fr2);
else $display("Hint: Output '%s' has no mismatches.", "fr2");
if (stats1.errors_fr1) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "fr1", stats1.errors_fr1, stats1.errortime_fr1);
else $display("Hint: Output '%s' has no mismatches.", "fr1");
if (stats1.errors_fr0) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "fr0", stats1.errors_fr0, stats1.errortime_fr0);
else $display("Hint: Output '%s' has no mismatches.", "fr0");
if (stats1.errors_dfr) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "dfr", stats1.errors_dfr, stats1.errortime_dfr);
else $display("Hint: Output '%s' has no mismatches.", "dfr");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { fr2_ref, fr1_ref, fr0_ref, dfr_ref } === ( { fr2_ref, fr1_ref, fr0_ref, dfr_ref } ^ { fr2_dut, fr1_dut, fr0_dut, dfr_dut } ^ { fr2_ref, fr1_ref, fr0_ref, dfr_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (fr2_ref !== ( fr2_ref ^ fr2_dut ^ fr2_ref ))
begin if (stats1.errors_fr2 == 0) stats1.errortime_fr2 = $time;
stats1.errors_fr2 = stats1.errors_fr2+1'b1; end
if (fr1_ref !== ( fr1_ref ^ fr1_dut ^ fr1_ref ))
begin if (stats1.errors_fr1 == 0) stats1.errortime_fr1 = $time;
stats1.errors_fr1 = stats1.errors_fr1+1'b1; end
if (fr0_ref !== ( fr0_ref ^ fr0_dut ^ fr0_ref ))
begin if (stats1.errors_fr0 == 0) stats1.errortime_fr0 = $time;
stats1.errors_fr0 = stats1.errors_fr0+1'b1; end
if (dfr_ref !== ( dfr_ref ^ dfr_dut ^ dfr_ref ))
begin if (stats1.errors_dfr == 0) stats1.errortime_dfr = $time;
stats1.errors_dfr = stats1.errors_dfr+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob150_review2015_fsmonehot |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input d
- input done_counting
- input ack
- input state (10 bits)
- output B3_next
- output S_next
- output S1_next
- output Count_next
- output Wait_next
- output done
- output counting
- output shift_ena
The module should implement the following Moore state machine with 3
input (d, done_counting, ack) and 3 outputs (shift_ena, counting, done).
Unless otherwise stated in the diagram below, assume outputs are 0 and
inputs are don't cares.
S () --d=0--> S
S () --d=1--> S1
S1 () --d=0--> S
S1 () --d=1--> S11
S11 () --d=0--> S110
S11 () --d=1--> S11
S110 () --d=0--> S
S110 () --d=1--> B0
B0 (shift_ena=1) --(always go to next cycle)--> B1
B1 (shift_ena=1) --(always go to next cycle)--> B2
B2 (shift_ena=1) --(always go to next cycle)--> B3
B3 (shift_ena=1) --(always go to next cycle)--> Count
Count (counting=1) --!(done_counting)--> Count
Count (counting=1) ---(done_counting)--> Wait
Wait (done=1) --ack=0--> Wait
Wait (done=1) --ack=1--> S
At reset, the state machine starts in state "S". Derive next-state logic
equations and output logic equations by inspection assuming the following
one-hot encoding is used: (S, S1, S11, S110, B0, B1, B2, B3, Count, Wait)
= (10'b0000000001, 10'b0000000010, 10'b0000000100, ... , 10'b1000000000)
Derive state transition and output logic equations by inspection assuming
a one-hot encoding. Implement only the state transition logic and output
logic (the combinational logic portion) for this state machine.
Write code that generates the following equations:
- B3_next (next-state logic for state B3)
- S_next
- S1_next
- Count_next
- Wait_next
- done -- output logic
- counting
- shift_ena
|
module RefModule (
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
);
parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;
assign B3_next = state[B2];
assign S_next = state[S]&~d | state[S1]&~d | state[S110]&~d | state[Wait]&ack;
assign S1_next = state[S]&d;
assign Count_next = state[B3] | state[Count]&~done_counting;
assign Wait_next = state[Count]&done_counting | state[Wait]&~ack;
assign done = state[Wait];
assign counting = state[Count];
assign shift_ena = |state[B3:B0];
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg d, done_counting, ack,
output reg [9:0] state,
input tb_match
);
bit failed = 0;
bit fail_onehot = 0;
always @(posedge clk, negedge clk)
if (!tb_match)
failed <= 1;
initial begin
{d, done_counting, ack} <= 3'h0;
state <= 10'h0;
repeat(300) @(posedge clk, negedge clk) begin
{d, done_counting, ack} = $random;
state <= 1<< ($unsigned($random) % 10);
end
@(posedge clk) fail_onehot <= failed;
repeat(3000) @(posedge clk, negedge clk) begin
{d, done_counting, ack} = $random;
state <= $random;
end
@(posedge clk);
if (!fail_onehot && failed) begin
$display ("Hint: Your circuit passed when given only one-hot inputs, but not with random inputs.");
$display ("Hint: Are you doing something more complicated than deriving state transition equations by inspection?\n");
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_B3_next;
int errortime_B3_next;
int errors_S_next;
int errortime_S_next;
int errors_S1_next;
int errortime_S1_next;
int errors_Count_next;
int errortime_Count_next;
int errors_Wait_next;
int errortime_Wait_next;
int errors_done;
int errortime_done;
int errors_counting;
int errortime_counting;
int errors_shift_ena;
int errortime_shift_ena;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic d;
logic done_counting;
logic ack;
logic [9:0] state;
logic B3_next_ref;
logic B3_next_dut;
logic S_next_ref;
logic S_next_dut;
logic S1_next_ref;
logic S1_next_dut;
logic Count_next_ref;
logic Count_next_dut;
logic Wait_next_ref;
logic Wait_next_dut;
logic done_ref;
logic done_dut;
logic counting_ref;
logic counting_dut;
logic shift_ena_ref;
logic shift_ena_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,d,done_counting,ack,state,B3_next_ref,B3_next_dut,S_next_ref,S_next_dut,S1_next_ref,S1_next_dut,Count_next_ref,Count_next_dut,Wait_next_ref,Wait_next_dut,done_ref,done_dut,counting_ref,counting_dut,shift_ena_ref,shift_ena_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.d,
.done_counting,
.ack,
.state );
RefModule good1 (
.d,
.done_counting,
.ack,
.state,
.B3_next(B3_next_ref),
.S_next(S_next_ref),
.S1_next(S1_next_ref),
.Count_next(Count_next_ref),
.Wait_next(Wait_next_ref),
.done(done_ref),
.counting(counting_ref),
.shift_ena(shift_ena_ref) );
TopModule top_module1 (
.d,
.done_counting,
.ack,
.state,
.B3_next(B3_next_dut),
.S_next(S_next_dut),
.S1_next(S1_next_dut),
.Count_next(Count_next_dut),
.Wait_next(Wait_next_dut),
.done(done_dut),
.counting(counting_dut),
.shift_ena(shift_ena_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_B3_next) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "B3_next", stats1.errors_B3_next, stats1.errortime_B3_next);
else $display("Hint: Output '%s' has no mismatches.", "B3_next");
if (stats1.errors_S_next) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "S_next", stats1.errors_S_next, stats1.errortime_S_next);
else $display("Hint: Output '%s' has no mismatches.", "S_next");
if (stats1.errors_S1_next) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "S1_next", stats1.errors_S1_next, stats1.errortime_S1_next);
else $display("Hint: Output '%s' has no mismatches.", "S1_next");
if (stats1.errors_Count_next) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Count_next", stats1.errors_Count_next, stats1.errortime_Count_next);
else $display("Hint: Output '%s' has no mismatches.", "Count_next");
if (stats1.errors_Wait_next) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "Wait_next", stats1.errors_Wait_next, stats1.errortime_Wait_next);
else $display("Hint: Output '%s' has no mismatches.", "Wait_next");
if (stats1.errors_done) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "done", stats1.errors_done, stats1.errortime_done);
else $display("Hint: Output '%s' has no mismatches.", "done");
if (stats1.errors_counting) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "counting", stats1.errors_counting, stats1.errortime_counting);
else $display("Hint: Output '%s' has no mismatches.", "counting");
if (stats1.errors_shift_ena) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "shift_ena", stats1.errors_shift_ena, stats1.errortime_shift_ena);
else $display("Hint: Output '%s' has no mismatches.", "shift_ena");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { B3_next_ref, S_next_ref, S1_next_ref, Count_next_ref, Wait_next_ref, done_ref, counting_ref, shift_ena_ref } === ( { B3_next_ref, S_next_ref, S1_next_ref, Count_next_ref, Wait_next_ref, done_ref, counting_ref, shift_ena_ref } ^ { B3_next_dut, S_next_dut, S1_next_dut, Count_next_dut, Wait_next_dut, done_dut, counting_dut, shift_ena_dut } ^ { B3_next_ref, S_next_ref, S1_next_ref, Count_next_ref, Wait_next_ref, done_ref, counting_ref, shift_ena_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (B3_next_ref !== ( B3_next_ref ^ B3_next_dut ^ B3_next_ref ))
begin if (stats1.errors_B3_next == 0) stats1.errortime_B3_next = $time;
stats1.errors_B3_next = stats1.errors_B3_next+1'b1; end
if (S_next_ref !== ( S_next_ref ^ S_next_dut ^ S_next_ref ))
begin if (stats1.errors_S_next == 0) stats1.errortime_S_next = $time;
stats1.errors_S_next = stats1.errors_S_next+1'b1; end
if (S1_next_ref !== ( S1_next_ref ^ S1_next_dut ^ S1_next_ref ))
begin if (stats1.errors_S1_next == 0) stats1.errortime_S1_next = $time;
stats1.errors_S1_next = stats1.errors_S1_next+1'b1; end
if (Count_next_ref !== ( Count_next_ref ^ Count_next_dut ^ Count_next_ref ))
begin if (stats1.errors_Count_next == 0) stats1.errortime_Count_next = $time;
stats1.errors_Count_next = stats1.errors_Count_next+1'b1; end
if (Wait_next_ref !== ( Wait_next_ref ^ Wait_next_dut ^ Wait_next_ref ))
begin if (stats1.errors_Wait_next == 0) stats1.errortime_Wait_next = $time;
stats1.errors_Wait_next = stats1.errors_Wait_next+1'b1; end
if (done_ref !== ( done_ref ^ done_dut ^ done_ref ))
begin if (stats1.errors_done == 0) stats1.errortime_done = $time;
stats1.errors_done = stats1.errors_done+1'b1; end
if (counting_ref !== ( counting_ref ^ counting_dut ^ counting_ref ))
begin if (stats1.errors_counting == 0) stats1.errortime_counting = $time;
stats1.errors_counting = stats1.errors_counting+1'b1; end
if (shift_ena_ref !== ( shift_ena_ref ^ shift_ena_dut ^ shift_ena_ref ))
begin if (stats1.errors_shift_ena == 0) stats1.errortime_shift_ena = $time;
stats1.errors_shift_ena = stats1.errors_shift_ena+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob151_review2015_fsm |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input data
- input done_counting
- input ack
- output shift_ena
- output counting
- output done
The module should implement a timer that:
(1) is started when a particular pattern (1101) is detected,
(2) shifts in 4 more bits to determine the duration to delay,
(3) waits for the counters to finish counting, and
(4) notifies the user and waits for the user to acknowledge the timer.
In this problem, implement just the finite-state machine that controls
the timer. The data path (counters and some comparators) are not included
here.
The serial data is available on the data input pin. When the pattern 1101
is received, the state machine must then assert output shift_ena for
exactly 4 clock cycles. After that, the state machine asserts its
counting output to indicate it is waiting for the counters, and waits
until input done_counting is high.At that point, the state machine must
assert done to notify the user the timer has timed out, and waits until
input ack is 1 before being reset to look for the next occurrence of the
start sequence (1101). The state machine should have a active high
synchronous reset, setting the state to where it begins searching for the
input sequence 1101. Assume all sequential logic is triggered on the
positive edge of the clock.
|
module RefModule (
input clk,
input reset,
input data,
output reg shift_ena,
output reg counting,
input done_counting,
output reg done,
input ack
);
typedef enum logic[3:0] {
S, S1, S11, S110, B0, B1, B2, B3, Count, Wait
} States;
States state, next;
always_comb begin
case (state)
S: next = States'(data ? S1: S);
S1: next = States'(data ? S11: S);
S11: next = States'(data ? S11 : S110);
S110: next = States'(data ? B0 : S);
B0: next = B1;
B1: next = B2;
B2: next = B3;
B3: next = Count;
Count: next = States'(done_counting ? Wait : Count);
Wait: next = States'(ack ? S : Wait);
default: next = States'(4'bx);
endcase
end
always @(posedge clk) begin
if (reset) state <= S;
else state <= next;
end
always_comb begin
shift_ena = 0; counting = 0; done = 0;
if (state == B0 || state == B1 || state == B2 || state == B3)
shift_ena = 1;
if (state == Count)
counting = 1;
if (state == Wait)
done = 1;
if (|state === 1'bx) begin
{shift_ena, counting, done} = 'x;
end
end
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output reg reset,
output reg data, done_counting, ack,
input tb_match
);
bit failed = 0;
always @(posedge clk, negedge clk)
if (!tb_match)
failed <= 1;
initial begin
@(posedge clk);
failed <= 0;
reset <= 1;
data <= 0;
done_counting <= 1'bx;
ack <= 1'bx;
@(posedge clk)
data <= 1;
reset <= 0;
@(posedge clk) data <= 0;
@(posedge clk) data <= 0;
@(posedge clk) data <= 1;
@(posedge clk) data <= 1;
@(posedge clk) data <= 0;
@(posedge clk) data <= 1;
@(posedge clk);
data <= 1'bx;
repeat(4) @(posedge clk);
done_counting <= 1'b0;
repeat(4) @(posedge clk);
done_counting <= 1'b1;
@(posedge clk);
done_counting <= 1'bx;
ack <= 1'b0;
repeat(3) @(posedge clk);
ack <= 1'b1;
@(posedge clk);
ack <= 1'b0;
data <= 1'b1;
@(posedge clk);
ack <= 1'bx;
data <= 1'b1;
@(posedge clk);
data <= 1'b0;
@(posedge clk);
data <= 1'b1;
@(posedge clk);
data <= 1'bx;
repeat(4) @(posedge clk);
done_counting <= 1'b0;
repeat(4) @(posedge clk);
done_counting <= 1'b1;
@(posedge clk);
if (failed)
$display("Hint: Your FSM didn't pass the sample timing diagram posted with the problem statement. Perhaps try debugging that?");
repeat(5000) @(posedge clk, negedge clk) begin
reset <= !($random & 255);
data <= $random;
done_counting <= !($random & 31);
ack <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_shift_ena;
int errortime_shift_ena;
int errors_counting;
int errortime_counting;
int errors_done;
int errortime_done;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic data;
logic done_counting;
logic ack;
logic shift_ena_ref;
logic shift_ena_dut;
logic counting_ref;
logic counting_dut;
logic done_ref;
logic done_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,data,done_counting,ack,shift_ena_ref,shift_ena_dut,counting_ref,counting_dut,done_ref,done_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset,
.data,
.done_counting,
.ack );
RefModule good1 (
.clk,
.reset,
.data,
.done_counting,
.ack,
.shift_ena(shift_ena_ref),
.counting(counting_ref),
.done(done_ref) );
TopModule top_module1 (
.clk,
.reset,
.data,
.done_counting,
.ack,
.shift_ena(shift_ena_dut),
.counting(counting_dut),
.done(done_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_shift_ena) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "shift_ena", stats1.errors_shift_ena, stats1.errortime_shift_ena);
else $display("Hint: Output '%s' has no mismatches.", "shift_ena");
if (stats1.errors_counting) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "counting", stats1.errors_counting, stats1.errortime_counting);
else $display("Hint: Output '%s' has no mismatches.", "counting");
if (stats1.errors_done) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "done", stats1.errors_done, stats1.errortime_done);
else $display("Hint: Output '%s' has no mismatches.", "done");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { shift_ena_ref, counting_ref, done_ref } === ( { shift_ena_ref, counting_ref, done_ref } ^ { shift_ena_dut, counting_dut, done_dut } ^ { shift_ena_ref, counting_ref, done_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (shift_ena_ref !== ( shift_ena_ref ^ shift_ena_dut ^ shift_ena_ref ))
begin if (stats1.errors_shift_ena == 0) stats1.errortime_shift_ena = $time;
stats1.errors_shift_ena = stats1.errors_shift_ena+1'b1; end
if (counting_ref !== ( counting_ref ^ counting_dut ^ counting_ref ))
begin if (stats1.errors_counting == 0) stats1.errortime_counting = $time;
stats1.errors_counting = stats1.errors_counting+1'b1; end
if (done_ref !== ( done_ref ^ done_dut ^ done_ref ))
begin if (stats1.errors_done == 0) stats1.errortime_done = $time;
stats1.errors_done = stats1.errors_done+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob152_lemmings3 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input bump_left
- input bump_right
- input ground
- input dig
- output walk_left
- output walk_right
- output aaah
- output digging
The game Lemmings involves critters with fairly simple brains. So simple
that we are going to model it using a finite state machine. In the
Lemmings' 2D world, Lemmings can be in one of two states: walking left
(walk_left is 1) or walking right (walk_right is 1). It will switch
directions if it hits an obstacle. In particular, if a Lemming is bumped
on the left (by receiving a 1 on bump_left), it will walk right. If it's
bumped on the right (by receiving a 1 on bump_right), it will walk left.
If it's bumped on both sides at the same time, it will still switch
directions.
In addition to walking left and right and changing direction when bumped,
when ground=0, the Lemming will fall and say "aaah!". When the ground
reappears (ground=1), the Lemming will resume walking in the same
direction as before the fall. Being bumped while falling does not affect
the walking direction, and being bumped in the same cycle as ground
disappears (but not yet falling), or when the ground reappears while
still falling, also does not affect the walking direction.
In addition to walking and falling, Lemmings can sometimes be told to do
useful things, like dig (it starts digging when dig=1). A Lemming can dig
if it is currently walking on ground (ground=1 and not falling), and will
continue digging until it reaches the other side (ground=0). At that
point, since there is no ground, it will fall (aaah!), then continue
walking in its original direction once it hits ground again. As with
falling, being bumped while digging has no effect, and being told to dig
when falling or when there is no ground is ignored. (In other words, a
walking Lemming can fall, dig, or switch directions. If more than one of
these conditions are satisfied, fall has higher precedence than dig,
which has higher precedence than switching directions.)
Implement a Moore state machine that models this behaviour. areset is
positive edge triggered asynchronous reseting the Lemming machine to walk
left. Assume all sequential logic is triggered on the positive edge of
the clock.
|
module RefModule (
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter WL=0, WR=1, FALLL=2, FALLR=3, DIGL=4, DIGR=5;
reg [2:0] state;
reg [2:0] next;
always_comb begin
case (state)
WL: if (!ground) next = FALLL;
else if (dig) next = DIGL;
else if (bump_left) next = WR;
else next = WL;
WR:
if (!ground) next = FALLR;
else if (dig) next = DIGR;
else if (bump_right) next = WL;
else next = WR;
FALLL: next = ground ? WL : FALLL;
FALLR: next = ground ? WR : FALLR;
DIGL: next = ground ? DIGL : FALLL;
DIGR: next = ground ? DIGR : FALLR;
endcase
end
always @(posedge clk, posedge areset) begin
if (areset) state <= WL;
else state <= next;
end
assign walk_left = (state==WL);
assign walk_right = (state==WR);
assign aaah = (state == FALLL) || (state == FALLR);
assign digging = (state == DIGL) || (state == DIGR);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic areset,
output logic bump_left,
output logic bump_right,
output logic dig,
output logic ground,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign areset = reset;
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
wire [0:13][3:0] d = {
4'h2,
4'h2,
4'h3,
4'h2,
4'ha,
4'h2,
4'h0,
4'h0,
4'h0,
4'h3,
4'h2,
4'h2,
4'h2,
4'h2
};
initial begin
reset <= 1'b1;
{bump_left, bump_right, ground, dig} <= 4'h2;
reset_test(1);
reset <= 1'b1;
@(posedge clk);
reset <= 0;
@(negedge clk);
wavedrom_start("Digging");
for (int i=0;i<14;i++)
@(posedge clk) {bump_left, bump_right, ground, dig} <= d[i];
wavedrom_stop();
repeat(400) @(posedge clk, negedge clk) begin
{dig, bump_right, bump_left} <= $random & $random;
ground <= |($random & 7);
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_walk_left;
int errortime_walk_left;
int errors_walk_right;
int errortime_walk_right;
int errors_aaah;
int errortime_aaah;
int errors_digging;
int errortime_digging;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic areset;
logic bump_left;
logic bump_right;
logic ground;
logic dig;
logic walk_left_ref;
logic walk_left_dut;
logic walk_right_ref;
logic walk_right_dut;
logic aaah_ref;
logic aaah_dut;
logic digging_ref;
logic digging_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,bump_left,bump_right,ground,dig,walk_left_ref,walk_left_dut,walk_right_ref,walk_right_dut,aaah_ref,aaah_dut,digging_ref,digging_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.areset,
.bump_left,
.bump_right,
.ground,
.dig );
RefModule good1 (
.clk,
.areset,
.bump_left,
.bump_right,
.ground,
.dig,
.walk_left(walk_left_ref),
.walk_right(walk_right_ref),
.aaah(aaah_ref),
.digging(digging_ref) );
TopModule top_module1 (
.clk,
.areset,
.bump_left,
.bump_right,
.ground,
.dig,
.walk_left(walk_left_dut),
.walk_right(walk_right_dut),
.aaah(aaah_dut),
.digging(digging_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_walk_left) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "walk_left", stats1.errors_walk_left, stats1.errortime_walk_left);
else $display("Hint: Output '%s' has no mismatches.", "walk_left");
if (stats1.errors_walk_right) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "walk_right", stats1.errors_walk_right, stats1.errortime_walk_right);
else $display("Hint: Output '%s' has no mismatches.", "walk_right");
if (stats1.errors_aaah) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "aaah", stats1.errors_aaah, stats1.errortime_aaah);
else $display("Hint: Output '%s' has no mismatches.", "aaah");
if (stats1.errors_digging) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "digging", stats1.errors_digging, stats1.errortime_digging);
else $display("Hint: Output '%s' has no mismatches.", "digging");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } === ( { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } ^ { walk_left_dut, walk_right_dut, aaah_dut, digging_dut } ^ { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (walk_left_ref !== ( walk_left_ref ^ walk_left_dut ^ walk_left_ref ))
begin if (stats1.errors_walk_left == 0) stats1.errortime_walk_left = $time;
stats1.errors_walk_left = stats1.errors_walk_left+1'b1; end
if (walk_right_ref !== ( walk_right_ref ^ walk_right_dut ^ walk_right_ref ))
begin if (stats1.errors_walk_right == 0) stats1.errortime_walk_right = $time;
stats1.errors_walk_right = stats1.errors_walk_right+1'b1; end
if (aaah_ref !== ( aaah_ref ^ aaah_dut ^ aaah_ref ))
begin if (stats1.errors_aaah == 0) stats1.errortime_aaah = $time;
stats1.errors_aaah = stats1.errors_aaah+1'b1; end
if (digging_ref !== ( digging_ref ^ digging_dut ^ digging_ref ))
begin if (stats1.errors_digging == 0) stats1.errortime_digging = $time;
stats1.errors_digging = stats1.errors_digging+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob153_gshare |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input predict_valid,
- input predict_pc (7 bits)
- output predict_taken
- output predict_history (7 bits)
- input train_valid
- input train_taken
- input train_mispredicted
- input train_history (7 bits)
- input train_pc (7 bits)
The module should implement a gshare branch predictor with 7-bit pc and
7-bit global history, hashed (using xor) into a 7-bit index. This index
accesses a 128-entry table of two-bit saturating counters. The branch
predictor should contain a 7-bit global branch history register. The
branch predictor has two sets of interfaces: One for doing predictions
and one for doing training. The prediction interface is used in the
processor's Fetch stage to ask the branch predictor for branch direction
predictions for the instructions being fetched. Once these branches
proceed down the pipeline and are executed, the true outcomes of the
branches become known. The branch predictor is then trained using the
actual branch direction outcomes.
When a branch prediction is requested (predict_valid = 1) for a given pc,
the branch predictor produces the predicted branch direction and state of
the branch history register used to make the prediction. The branch
history register is then updated (at the next positive clock edge) for
the predicted branch.
When training for a branch is requested (train_valid = 1), the branch
predictor is told the pc and branch history register value for the branch
that is being trained, as well as the actual branch outcome and whether
the branch was a misprediction (needing a pipeline flush). Update the
pattern history table (PHT) to train the branch predictor to predict this
branch more accurately next time. In addition, if the branch being
trained is mispredicted, also recover the branch history register to the
state immediately after the mispredicting branch completes execution.
If training for a misprediction and a prediction (for a different,
younger instruction) occurs in the same cycle, both operations will want
to modify the branch history register. When this happens, training takes
precedence, because the branch being predicted will be discarded anyway.
If training and prediction of the same PHT entry happen at the same time,
the prediction sees the PHT state before training because training only
modifies the PHT at the next positive clock edge. The following timing
diagram shows the timing when training and predicting PHT entry 0 at the
same time. The training request at cycle 4 changes the PHT entry state in
cycle 5, but the prediction request in cycle 4 outputs the PHT state at
cycle 4, without considering the effect of the training request in cycle
4. Reset is asynchronous active-high.
Assume all sequential logic is triggered on the positive edge of the
clock.
|
module RefModule (
input clk,
input areset,
input predict_valid,
input [6:0] predict_pc,
output predict_taken,
output [6:0] predict_history,
input train_valid,
input train_taken,
input train_mispredicted,
input [6:0] train_history,
input [6:0] train_pc
);
parameter n = 7;
logic [1:0] pht [2**n-1:0];
parameter [1:0] SNT = 0, LNT = 1, LT = 2, ST = 3;
logic [n-1:0] predict_history_r;
wire [n-1:0] predict_index = predict_history_r ^ predict_pc;
wire [n-1:0] train_index = train_history ^ train_pc;
always@(posedge clk, posedge areset)
if (areset) begin
for (integer i=0; i<2**n; i=i+1)
pht[i] = LNT;
predict_history_r = 0;
end else begin
if (predict_valid)
predict_history_r <= {predict_history_r, predict_taken};
if(train_valid) begin
if(pht[train_index] < 3 && train_taken)
pht[train_index] <= pht[train_index] + 1;
else if(pht[train_index] > 0 && !train_taken)
pht[train_index] <= pht[train_index] - 1;
if (train_mispredicted)
predict_history_r <= {train_history, train_taken};
end
end
assign predict_taken = predict_valid ? pht[predict_index][1] : 1'bx;
assign predict_history = predict_valid ? predict_history_r : {n{1'bx}};
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen
#(parameter N=7)
(
input clk,
output logic areset,
output logic predict_valid,
output [N-1:0] predict_pc,
output logic train_valid,
output train_taken,
output train_mispredicted,
output [N-1:0] train_history,
output [N-1:0] train_pc,
input tb_match,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
output int wavedrom_hide_after_time
);
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
reg reset;
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
assign areset = reset;
logic [N-1:0] predict_pc_r;
logic train_taken_r;
logic train_mispredicted_r;
logic [N-1:0] train_history_r;
logic [N-1:0] train_pc_r;
assign predict_pc = predict_valid ? predict_pc_r : {N{1'bx}};
assign train_taken = train_valid ? train_taken_r : 1'bx;
assign train_mispredicted = train_valid ? train_mispredicted_r : 1'bx;
assign train_history = train_valid ? train_history_r : {N{1'bx}};
assign train_pc = train_valid ? train_pc_r : {N{1'bx}};
initial begin
@(posedge clk) reset <= 1;
@(posedge clk) reset <= 0;
predict_valid <= 1;
train_mispredicted_r <= 1;
train_history_r <= 7'h7f;
train_pc_r <= 7'h4;
train_taken_r <= 1;
train_valid <= 1;
predict_valid <= 1;
predict_pc_r <= 4;
wavedrom_start("Asynchronous reset");
reset_test(1); // Test for asynchronous reset
wavedrom_stop();
@(posedge clk) reset <= 1;
predict_valid <= 0;
wavedrom_start("Training entries (pc = 0xa, history = 0 and 2)");
predict_pc_r <= 7'ha;
predict_valid <= 1;
train_history_r <= 7'h0;
train_pc_r <= 7'ha;
train_taken_r <= 1;
train_valid <= 0;
train_mispredicted_r <= 0;
@(negedge clk) reset <= 0;
@(posedge clk) train_valid <= 1;
@(posedge clk) train_history_r <= 7'h2;
@(posedge clk) train_valid <= 0;
repeat(4) @(posedge clk);
train_history_r <= 7'h0;
train_taken_r <= 0;
train_valid <= 1;
@(posedge clk) train_valid <= 0;
repeat(8) @(posedge clk);
wavedrom_stop();
@(posedge clk);
wavedrom_start("History register recovery on misprediction");
reset <= 1;
predict_pc_r <= 7'ha;
predict_valid <= 1;
train_history_r <= 7'h0;
train_pc_r <= 7'ha;
train_taken_r <= 1;
train_valid <= 0;
train_mispredicted_r <= 1;
@(negedge clk) reset <= 0;
@(posedge clk);
@(posedge clk) train_valid <= 1;
@(posedge clk) train_valid <= 0;
@(posedge clk) train_valid <= 1;
train_history_r <= 7'h10;
train_taken_r <= 0;
@(posedge clk) train_valid <= 0;
repeat(4) @(posedge clk);
train_history_r <= 7'h0;
train_taken_r <= 0;
train_valid <= 1;
@(posedge clk) train_valid <= 0;
@(posedge clk) train_valid <= 1;
train_history_r <= 7'h20;
@(posedge clk) train_valid <= 0;
repeat(3) @(posedge clk);
wavedrom_stop();
repeat(1000) @(posedge clk,negedge clk) begin
{predict_valid, predict_pc_r, train_pc_r, train_taken_r, train_valid} <= {$urandom};
train_history_r <= $urandom;
train_mispredicted_r <= !($urandom_range(0,31));
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_predict_taken;
int errortime_predict_taken;
int errors_predict_history;
int errortime_predict_history;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic areset;
logic predict_valid;
logic [6:0] predict_pc;
logic train_valid;
logic train_taken;
logic train_mispredicted;
logic [6:0] train_history;
logic [6:0] train_pc;
logic predict_taken_ref;
logic predict_taken_dut;
logic [6:0] predict_history_ref;
logic [6:0] predict_history_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,predict_valid,predict_pc,train_valid,train_taken,train_mispredicted,train_history,train_pc,predict_taken_ref,predict_taken_dut,predict_history_ref,predict_history_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.areset,
.predict_valid,
.predict_pc,
.train_valid,
.train_taken,
.train_mispredicted,
.train_history,
.train_pc );
RefModule good1 (
.clk,
.areset,
.predict_valid,
.predict_pc,
.train_valid,
.train_taken,
.train_mispredicted,
.train_history,
.train_pc,
.predict_taken(predict_taken_ref),
.predict_history(predict_history_ref) );
TopModule top_module1 (
.clk,
.areset,
.predict_valid,
.predict_pc,
.train_valid,
.train_taken,
.train_mispredicted,
.train_history,
.train_pc,
.predict_taken(predict_taken_dut),
.predict_history(predict_history_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_predict_taken) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "predict_taken", stats1.errors_predict_taken, stats1.errortime_predict_taken);
else $display("Hint: Output '%s' has no mismatches.", "predict_taken");
if (stats1.errors_predict_history) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "predict_history", stats1.errors_predict_history, stats1.errortime_predict_history);
else $display("Hint: Output '%s' has no mismatches.", "predict_history");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { predict_taken_ref, predict_history_ref } === ( { predict_taken_ref, predict_history_ref } ^ { predict_taken_dut, predict_history_dut } ^ { predict_taken_ref, predict_history_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (predict_taken_ref !== ( predict_taken_ref ^ predict_taken_dut ^ predict_taken_ref ))
begin if (stats1.errors_predict_taken == 0) stats1.errortime_predict_taken = $time;
stats1.errors_predict_taken = stats1.errors_predict_taken+1'b1; end
if (predict_history_ref !== ( predict_history_ref ^ predict_history_dut ^ predict_history_ref ))
begin if (stats1.errors_predict_history == 0) stats1.errortime_predict_history = $time;
stats1.errors_predict_history = stats1.errors_predict_history+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob154_fsm_ps2data |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input in (8 bits)
- output out_bytes (24 bits)
- output done
The module should implement a finite state machine that will search for
message boundaries when given an input byte stream. The algorithm we'll
use is to discard bytes until we see one with in[3]=1. We then assume
that this is byte 1 of a message, and signal the receipt of a message
once all 3 bytes have been received (done). The FSM should signal done in
the cycle immediately after the third byte of each message was
successfully received.
Implement the datapath module that will output the 24-bit (3 byte)
message whenever a packet is received (out_bytes[23:16] is the first
byte, out_bytes[15:8] is the second byte, etc.). The reset signal is
active high synchronous. out_bytes needs to be valid whenever the done
signal is asserted. You may output anything at other times (i.e.,
don't-care). Assume all sequential logic is triggered on the positive
edge of the clock.
Here is an example waveform:
time clk rst in done out_bytes
0ns 0 1 0 x x
5ns 1 1 0 0 x
10ns 0 1 0 0 x
15ns 1 0 2c 0 x
20ns 0 0 2c 0 x
25ns 1 0 81 0 x
30ns 0 0 81 0 x
35ns 1 0 9 0 x
40ns 0 0 9 0 x
45ns 1 0 6b 1 2c8109
50ns 0 0 6b 1 2c8109
55ns 1 0 d 0 x
60ns 0 0 d 0 x
65ns 1 0 8d 0 x
70ns 0 0 8d 0 x
75ns 1 0 6d 1 6b0d8d
80ns 0 0 6d 1 6b0d8d
85ns 1 0 12 0 x
90ns 0 0 12 0 x
95ns 1 0 1 0 x
100ns 0 0 1 0 x
105ns 1 0 d 1 6d1201
110ns 0 0 d 1 6d1201
115ns 1 0 76 0 x
120ns 0 0 76 0 x
125ns 1 0 3d 0 x
130ns 0 0 3d 0 x
135ns 1 0 ed 1 d763d
140ns 0 0 ed 1 d763d
145ns 1 0 8c 0 x
150ns 0 0 8c 0 x
155ns 1 0 f9 0 x
160ns 0 0 f9 0 x
165ns 1 0 ce 1 ed8cf9
170ns 0 0 ce 1 ed8cf9
175ns 1 0 c5 0 x
180ns 0 0 c5 0 x
185ns 1 0 aa 0 x
190ns 0 0 aa 0 x
|
module RefModule (
input clk,
input [7:0] in,
input reset,
output [23:0] out_bytes,
output done
);
parameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3;
reg [1:0] state;
reg [1:0] next;
wire in3 = in[3];
always_comb begin
case (state)
BYTE1: next = in3 ? BYTE2 : BYTE1;
BYTE2: next = BYTE3;
BYTE3: next = DONE;
DONE: next = in3 ? BYTE2 : BYTE1;
endcase
end
always @(posedge clk) begin
if (reset) state <= BYTE1;
else state <= next;
end
assign done = (state==DONE);
reg [23:0] out_bytes_r;
always @(posedge clk)
out_bytes_r <= {out_bytes_r[15:0], in};
// Implementations may vary: Allow user to do anything while the output
// doesn't have to be valid.
assign out_bytes = done ? out_bytes_r : 'x;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic [7:0] in,
output logic reset
);
initial begin
repeat(200) @(negedge clk) begin
in <= $random;
reset <= !($random & 31);
end
reset <= 1'b0;
in <= '0;
repeat(10) @(posedge clk);
repeat(200) begin
in <= $random;
in[3] <= 1'b1;
@(posedge clk);
in <= $random;
@(posedge clk);
in <= $random;
@(posedge clk);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_out_bytes;
int errortime_out_bytes;
int errors_done;
int errortime_done;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic [7:0] in;
logic reset;
logic [23:0] out_bytes_ref;
logic [23:0] out_bytes_dut;
logic done_ref;
logic done_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,in,reset,out_bytes_ref,out_bytes_dut,done_ref,done_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.in,
.reset );
RefModule good1 (
.clk,
.in,
.reset,
.out_bytes(out_bytes_ref),
.done(done_ref) );
TopModule top_module1 (
.clk,
.in,
.reset,
.out_bytes(out_bytes_dut),
.done(done_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_out_bytes) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "out_bytes", stats1.errors_out_bytes, stats1.errortime_out_bytes);
else $display("Hint: Output '%s' has no mismatches.", "out_bytes");
if (stats1.errors_done) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "done", stats1.errors_done, stats1.errortime_done);
else $display("Hint: Output '%s' has no mismatches.", "done");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { out_bytes_ref, done_ref } === ( { out_bytes_ref, done_ref } ^ { out_bytes_dut, done_dut } ^ { out_bytes_ref, done_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (out_bytes_ref !== ( out_bytes_ref ^ out_bytes_dut ^ out_bytes_ref ))
begin if (stats1.errors_out_bytes == 0) stats1.errortime_out_bytes = $time;
stats1.errors_out_bytes = stats1.errors_out_bytes+1'b1; end
if (done_ref !== ( done_ref ^ done_dut ^ done_ref ))
begin if (stats1.errors_done == 0) stats1.errortime_done = $time;
stats1.errors_done = stats1.errors_done+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob155_lemmings4 |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input areset
- input bump_left
- input bump_right
- input ground
- input dig
- output walk_left
- output walk_right
- output aaah
- output digging
The game Lemmings involves critters with fairly simple brains. So simple
that we are going to model it using a finite state machine. In the
Lemmings' 2D world, Lemmings can be in one of two states: walking left
(walk_left is 1) or walking right (walk_right is 1). It will switch
directions if it hits an obstacle. In particular, if a Lemming is bumped
on the left (by receiving a 1 on bump_left), it will walk right. If it's
bumped on the right (by receiving a 1 on bump_right), it will walk left.
If it's bumped on both sides at the same time, it will still switch
directions.
In addition to walking left and right and changing direction when bumped,
when ground=0, the Lemming will fall and say ""aaah!"". When the ground
reappears (ground=1), the Lemming will resume walking in the same
direction as before the fall. Being bumped while falling does not affect
the walking direction, and being bumped in the same cycle as ground
disappears (but not yet falling), or when the ground reappears while
still falling, also does not affect the walking direction.
In addition to walking and falling, Lemmings can sometimes be told to do
useful things, like dig (it starts digging when dig=1). A Lemming can dig
if it is currently walking on ground (ground=1 and not falling), and will
continue digging until it reaches the other side (ground=0). At that
point, since there is no ground, it will fall (aaah!), then continue
walking in its original direction once it hits ground again. As with
falling, being bumped while digging has no effect, and being told to dig
when falling or when there is no ground is ignored. (In other words, a
walking Lemming can fall, dig, or switch directions. If more than one of
these conditions are satisfied, fall has higher precedence than dig,
which has higher precedence than switching directions.)
Although Lemmings can walk, fall, and dig, Lemmings aren't invulnerable.
If a Lemming falls for too long then hits the ground, it can splatter. In
particular, if a Lemming falls for more than 20 clock cycles then hits
the ground, it will splatter and cease walking, falling, or digging (all
4 outputs become 0), forever (Or until the FSM gets reset). There is no
upper limit on how far a Lemming can fall before hitting the ground.
Lemmings only splatter when hitting the ground; they do not splatter in
mid-air.
Implement a Moore state machine that models this behaviour. areset is
positive edge triggered asynchronous reseting the Lemming machine to walk
left.
Assume all sequential logic is triggered on the positive edge of the
clock.
|
module RefModule (
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter WL=0, WR=1, FALLL=2, FALLR=3, DIGL=4, DIGR=5, DEAD=6;
reg [2:0] state;
reg [2:0] next;
reg [4:0] fall_counter;
always_comb begin
case (state)
WL: if (!ground) next = FALLL;
else if (dig) next = DIGL;
else if (bump_left) next = WR;
else next = WL;
WR:
if (!ground) next = FALLR;
else if (dig) next = DIGR;
else if (bump_right) next = WL;
else next = WR;
FALLL: next = ground ? (fall_counter >= 20 ? DEAD : WL) : FALLL;
FALLR: next = ground ? (fall_counter >= 20 ? DEAD : WR) : FALLR;
DIGL: next = ground ? DIGL : FALLL;
DIGR: next = ground ? DIGR : FALLR;
DEAD: next = DEAD;
endcase
end
always @(posedge clk, posedge areset) begin
if (areset) state <= WL;
else state <= next;
end
always @(posedge clk) begin
if (state == FALLL || state == FALLR) begin
if (fall_counter < 20)
fall_counter <= fall_counter + 1'b1;
end
else
fall_counter <= 0;
end
assign walk_left = (state==WL);
assign walk_right = (state==WR);
assign aaah = (state == FALLL) || (state == FALLR);
assign digging = (state == DIGL) || (state == DIGR);
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
module stimulus_gen (
input clk,
output logic areset,
output logic bump_left,
output logic bump_right,
output logic dig,
output logic ground,
output reg[511:0] wavedrom_title,
output reg wavedrom_enable,
input tb_match
);
reg reset;
assign areset = reset;
task reset_test(input async=0);
bit arfail, srfail, datafail;
@(posedge clk);
@(posedge clk) reset <= 0;
repeat(3) @(posedge clk);
@(negedge clk) begin datafail = !tb_match ; reset <= 1; end
@(posedge clk) arfail = !tb_match;
@(posedge clk) begin
srfail = !tb_match;
reset <= 0;
end
if (srfail)
$display("Hint: Your reset doesn't seem to be working.");
else if (arfail && (async || !datafail))
$display("Hint: Your reset should be %0s, but doesn't appear to be.", async ? "asynchronous" : "synchronous");
// Don't warn about synchronous reset if the half-cycle before is already wrong. It's more likely
// a functionality error than the reset being implemented asynchronously.
endtask
// Add two ports to module stimulus_gen:
// output [511:0] wavedrom_title
// output reg wavedrom_enable
task wavedrom_start(input[511:0] title = "");
endtask
task wavedrom_stop;
#1;
endtask
initial begin
reset <= 1'b1;
@(posedge clk);
reset <= 0;
{bump_left, bump_right, ground, dig} <= 2;
repeat(2) @(posedge clk);
{bump_left, bump_right, ground, dig} <= 3;
@(posedge clk);
{bump_left, bump_right, ground, dig} <= 2;
@(posedge clk);
{bump_left, bump_right, ground, dig} <= 10;
@(posedge clk);
{bump_left, bump_right, ground, dig} <= 2;
@(posedge clk);
{bump_left, bump_right, ground, dig} <= 0;
repeat(3) @(posedge clk);
{bump_left, bump_right, ground, dig} <= 3;
@(posedge clk);
{bump_left, bump_right, ground, dig} <= 2;
repeat(4) @(posedge clk);
{bump_left, bump_right, ground, dig} <= 0; // Fall
repeat(20) @(posedge clk);
{bump_left, bump_right, ground, dig} <= 2; // Survive
repeat(1) @(posedge clk);
{bump_left, bump_right, ground, dig} <= 0; // Fall
repeat(21) @(posedge clk);
{bump_left, bump_right, ground, dig} <= 2; // Splat after falling left
repeat(20) @(posedge clk) begin
{dig, bump_right, bump_left} <= $random & $random; // See if it's handled correctly.
ground <= |($random & 7);
end
reset <= 1;
{bump_left, bump_right, ground, dig} <= 2; // Normal
@(posedge clk)
reset <= 0; // Resurrect.
bump_left <= 1;
repeat(5) @(posedge clk);
{bump_left, bump_right, ground, dig} <= 0; // Fall
repeat(21) @(posedge clk);
{bump_left, bump_right, ground, dig} <= 2; // Splat after falling right
repeat(20) @(posedge clk) begin
{dig, bump_right, bump_left} <= $random & $random; // See if it's handled correctly.
ground <= |($random & 7);
end
reset <= 1;
@(posedge clk)
reset <= 0; // Resurrect.
{bump_left, bump_right, ground, dig} <= 2; // Normal
wavedrom_start("Splat?");
@(posedge clk);
{bump_left, bump_right, ground, dig} <= 0; // Fall
repeat(24) @(posedge clk);
{bump_left, bump_right, ground, dig} <= 2; // Splat? (24-cycles)
repeat(2) @(posedge clk);
wavedrom_stop();
reset <= 1;
@(posedge clk)
reset <= 0; // Resurrect.
{bump_left, bump_right, ground, dig} <= 2; // Normal
@(posedge clk);
@(posedge clk);
{bump_left, bump_right, ground, dig} <= 0; // Fall
repeat(35) @(posedge clk);
{bump_left, bump_right, ground, dig} <= 2; // Splat? (Test for 5-bit non-saturating counter)
repeat(2) @(posedge clk);
repeat(20) @(posedge clk) begin
{dig, bump_right, bump_left} <= $random & $random; // See if it's handled correctly.
ground <= |($random & 7);
end
reset <= 1;
{bump_left, bump_right, ground, dig} <= 2; // Normal
@(posedge clk);
reset <= 0; // Resurrect.
@(posedge clk);
{bump_left, bump_right, ground, dig} <= 0; // Fall
repeat(67) @(posedge clk);
{bump_left, bump_right, ground, dig} <= 2; // Splat? (Test for 6-bit non-saturating counter)
repeat(20) @(posedge clk) begin
{dig, bump_right, bump_left} <= $random & $random; // See if it's handled correctly.
ground <= |($random & 7);
end
reset <= 1;
{bump_left, bump_right, ground, dig} <= 2; // Normal
@(posedge clk)
reset <= 0; // Resurrect.
repeat(400) @(posedge clk, negedge clk) begin
{dig, bump_right, bump_left} <= $random & $random;
ground <= |($random & 7);
reset <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_walk_left;
int errortime_walk_left;
int errors_walk_right;
int errortime_walk_right;
int errors_aaah;
int errortime_aaah;
int errors_digging;
int errortime_digging;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic areset;
logic bump_left;
logic bump_right;
logic ground;
logic dig;
logic walk_left_ref;
logic walk_left_dut;
logic walk_right_ref;
logic walk_right_dut;
logic aaah_ref;
logic aaah_dut;
logic digging_ref;
logic digging_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,areset,bump_left,bump_right,ground,dig,walk_left_ref,walk_left_dut,walk_right_ref,walk_right_dut,aaah_ref,aaah_dut,digging_ref,digging_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.areset,
.bump_left,
.bump_right,
.ground,
.dig );
RefModule good1 (
.clk,
.areset,
.bump_left,
.bump_right,
.ground,
.dig,
.walk_left(walk_left_ref),
.walk_right(walk_right_ref),
.aaah(aaah_ref),
.digging(digging_ref) );
TopModule top_module1 (
.clk,
.areset,
.bump_left,
.bump_right,
.ground,
.dig,
.walk_left(walk_left_dut),
.walk_right(walk_right_dut),
.aaah(aaah_dut),
.digging(digging_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_walk_left) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "walk_left", stats1.errors_walk_left, stats1.errortime_walk_left);
else $display("Hint: Output '%s' has no mismatches.", "walk_left");
if (stats1.errors_walk_right) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "walk_right", stats1.errors_walk_right, stats1.errortime_walk_right);
else $display("Hint: Output '%s' has no mismatches.", "walk_right");
if (stats1.errors_aaah) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "aaah", stats1.errors_aaah, stats1.errortime_aaah);
else $display("Hint: Output '%s' has no mismatches.", "aaah");
if (stats1.errors_digging) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "digging", stats1.errors_digging, stats1.errortime_digging);
else $display("Hint: Output '%s' has no mismatches.", "digging");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } === ( { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } ^ { walk_left_dut, walk_right_dut, aaah_dut, digging_dut } ^ { walk_left_ref, walk_right_ref, aaah_ref, digging_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (walk_left_ref !== ( walk_left_ref ^ walk_left_dut ^ walk_left_ref ))
begin if (stats1.errors_walk_left == 0) stats1.errortime_walk_left = $time;
stats1.errors_walk_left = stats1.errors_walk_left+1'b1; end
if (walk_right_ref !== ( walk_right_ref ^ walk_right_dut ^ walk_right_ref ))
begin if (stats1.errors_walk_right == 0) stats1.errortime_walk_right = $time;
stats1.errors_walk_right = stats1.errors_walk_right+1'b1; end
if (aaah_ref !== ( aaah_ref ^ aaah_dut ^ aaah_ref ))
begin if (stats1.errors_aaah == 0) stats1.errortime_aaah = $time;
stats1.errors_aaah = stats1.errors_aaah+1'b1; end
if (digging_ref !== ( digging_ref ^ digging_dut ^ digging_ref ))
begin if (stats1.errors_digging == 0) stats1.errortime_digging = $time;
stats1.errors_digging = stats1.errors_digging+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Prob156_review2015_fancytimer |
I would like you to implement a module named TopModule with the following
interface. All input and output ports are one bit unless otherwise
specified.
- input clk
- input reset
- input data
- output count (4 bits)
- output counting
- output done
- input ack
The module should implement a timer with one input that:
(1) is started when a particular input pattern (1101) is detected,
(2) shifts in 4 more bits to determine the duration to delay,
(3) waits for the counters to finish counting, and
(4) notifies the user and waits for the user to acknowledge the timer.
The serial data is available on the data input pin. When the pattern 1101
is received, the circuit must then shift in the next 4 bits,
most-significant-bit first. These 4 bits determine the duration of the
timer delay, referred to as delay[3:0]. After that, the state machine
asserts its counting output to indicate it is counting. Once the 1101 and
delay[3:0] have been read, the circuit no longer looks at the data input
until it resumes searching after everything else is done.
The state machine must count for exactly (delay[3:0] + 1) * 1000 clock
cycles. e.g., delay=0 means count 1000 cycles, and delay=5 means count
6000 cycles. Also output the current remaining time. This should be equal
to delay for 1000 cycles, then delay-1 for 1000 cycles, and so on until
it is 0 for 1000 cycles.
When the circuit isn't counting, the count[3:0] output is don't-care
(whatever value is convenient for you to implement). At that point, the
circuit must assert done to notify the user the timer has timed out, and
waits until input ack is 1 before being reset to look for the next
occurrence of the start sequence (1101).
The circuit should reset into a state where it begins searching for the
input sequence 1101. The reset signal is active high synchronous. Assume
all sequential logic is triggered on the positive edge of the clock.
|
module RefModule (
input wire clk,
input wire reset,
input wire data,
output wire [3:0] count,
output reg counting,
output reg done,
input wire ack
);
typedef enum logic[3:0] {
S, S1, S11, S110, B0, B1, B2, B3, Count, Wait
} States;
States state, next;
reg shift_ena;
reg [9:0] fcount;
reg [3:0] scount;
wire done_counting = (scount == 0) && (fcount == 999);
always_comb begin
case (state)
S: next = States'(data ? S1: S);
S1: next = States'(data ? S11: S);
S11: next = States'(data ? S11 : S110);
S110: next = States'(data ? B0 : S);
B0: next = B1;
B1: next = B2;
B2: next = B3;
B3: next = Count;
Count: next = States'(done_counting ? Wait : Count);
Wait: next = States'(ack ? S : Wait);
default: next = States'(4'bx);
endcase
end
always @(posedge clk) begin
if (reset) state <= S;
else state <= next;
end
always_comb begin
shift_ena = 0; counting = 0; done = 0;
if (state == B0 || state == B1 || state == B2 || state == B3)
shift_ena = 1;
if (state == Count)
counting = 1;
if (state == Wait)
done = 1;
if (|state === 1'bx) begin
{shift_ena, counting, done} = 'x;
end
end
// Shift register
always @(posedge clk) begin
if (shift_ena)
scount <= {scount[2:0], data};
else if (counting && fcount == 999)
scount <= scount - 1'b1;
end
// Fast counter
always @(posedge clk)
if (!counting)
fcount <= 10'h0;
else if (fcount == 999)
fcount <= 10'h0;
else
fcount <= fcount + 1'b1;
assign count = counting ? scount : 'x;
endmodule
| `timescale 1 ps/1 ps
`define OK 12
`define INCORRECT 13
`default_nettype none
module stimulus_gen (
input wire clk,
output reg reset,
output reg data,
output reg ack,
input wire tb_match,
input wire counting_dut
);
bit failed = 0;
int counting_cycles = 0;
always @(posedge clk, negedge clk)
if (!tb_match)
failed <= 1;
always @(posedge clk)
if (counting_dut)
counting_cycles++;
initial begin
@(posedge clk);
failed <= 0;
reset <= 1;
data <= 0;
ack <= 1'bx;
@(posedge clk)
data <= 1;
reset <= 0;
@(posedge clk) data <= 0;
@(posedge clk) data <= 0;
@(posedge clk) data <= 1;
@(posedge clk) data <= 1;
@(posedge clk) data <= 0;
@(posedge clk) data <= 1;
@(posedge clk) data <= 0;
@(posedge clk) data <= 0;
@(posedge clk) data <= 0;
@(posedge clk) data <= 1;
@(posedge clk);
data <= 1'bx;
repeat(2000) @(posedge clk);
ack <= 1'b0;
repeat(3) @(posedge clk);
ack <= 1'b1;
@(posedge clk);
ack <= 1'b0;
data <= 1'b1;
if (counting_cycles != 2000)
$display("Hint: The first test case should count for 2000 cycles. Your circuit counted %0d", counting_cycles);
counting_cycles <= 0;
@(posedge clk);
ack <= 1'bx;
data <= 1'b1;
@(posedge clk);
data <= 1'b0;
@(posedge clk);
data <= 1'b1;
@(posedge clk); data <= 1'b1;
@(posedge clk); data <= 1'b1;
@(posedge clk); data <= 1'b1;
@(posedge clk); data <= 1'b0;
repeat(14800) @(posedge clk);
ack <= 1'b0;
repeat(400) @(posedge clk);
if (counting_cycles != 15000)
$display("Hint: The second test case should count for 15000 cycles. Your circuit counted %0d", counting_cycles);
counting_cycles <= 0;
if (failed)
$display("Hint: Your FSM didn't pass the sample timing diagram posted with the problem statement. Perhaps try debugging that?");
repeat(1000) @(posedge clk, negedge clk) begin
reset <= !($random & 8191);
data <= $random;
ack <= !($random & 31);
end
repeat(100000) @(posedge clk) begin
reset <= !($random & 8191);
data <= $random;
ack <= !($random & 31);
end
#1 $finish;
end
endmodule
module tb();
typedef struct packed {
int errors;
int errortime;
int errors_count;
int errortime_count;
int errors_counting;
int errortime_counting;
int errors_done;
int errortime_done;
int clocks;
} stats;
stats stats1;
wire[511:0] wavedrom_title;
wire wavedrom_enable;
int wavedrom_hide_after_time;
reg clk=0;
initial forever
#5 clk = ~clk;
logic reset;
logic data;
logic ack;
logic [3:0] count_ref;
logic [3:0] count_dut;
logic counting_ref;
logic counting_dut;
logic done_ref;
logic done_dut;
initial begin
$dumpfile("wave.vcd");
$dumpvars(1, stim1.clk, tb_mismatch ,clk,reset,data,ack,count_ref,count_dut,counting_ref,counting_dut,done_ref,done_dut );
end
wire tb_match; // Verification
wire tb_mismatch = ~tb_match;
stimulus_gen stim1 (
.clk,
.* ,
.reset,
.data,
.ack );
RefModule good1 (
.clk,
.reset,
.data,
.ack,
.count(count_ref),
.counting(counting_ref),
.done(done_ref) );
TopModule top_module1 (
.clk,
.reset,
.data,
.ack,
.count(count_dut),
.counting(counting_dut),
.done(done_dut) );
bit strobe = 0;
task wait_for_end_of_timestep;
repeat(5) begin
strobe <= !strobe; // Try to delay until the very end of the time step.
@(strobe);
end
endtask
final begin
if (stats1.errors_count) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "count", stats1.errors_count, stats1.errortime_count);
else $display("Hint: Output '%s' has no mismatches.", "count");
if (stats1.errors_counting) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "counting", stats1.errors_counting, stats1.errortime_counting);
else $display("Hint: Output '%s' has no mismatches.", "counting");
if (stats1.errors_done) $display("Hint: Output '%s' has %0d mismatches. First mismatch occurred at time %0d.", "done", stats1.errors_done, stats1.errortime_done);
else $display("Hint: Output '%s' has no mismatches.", "done");
$display("Hint: Total mismatched samples is %1d out of %1d samples\n", stats1.errors, stats1.clocks);
$display("Simulation finished at %0d ps", $time);
$display("Mismatches: %1d in %1d samples", stats1.errors, stats1.clocks);
end
// Verification: XORs on the right makes any X in good_vector match anything, but X in dut_vector will only match X.
assign tb_match = ( { count_ref, counting_ref, done_ref } === ( { count_ref, counting_ref, done_ref } ^ { count_dut, counting_dut, done_dut } ^ { count_ref, counting_ref, done_ref } ) );
// Use explicit sensitivity list here. @(*) causes NetProc::nex_input() to be called when trying to compute
// the sensitivity list of the @(strobe) process, which isn't implemented.
always @(posedge clk, negedge clk) begin
stats1.clocks++;
if (!tb_match) begin
if (stats1.errors == 0) stats1.errortime = $time;
stats1.errors++;
end
if (count_ref !== ( count_ref ^ count_dut ^ count_ref ))
begin if (stats1.errors_count == 0) stats1.errortime_count = $time;
stats1.errors_count = stats1.errors_count+1'b1; end
if (counting_ref !== ( counting_ref ^ counting_dut ^ counting_ref ))
begin if (stats1.errors_counting == 0) stats1.errortime_counting = $time;
stats1.errors_counting = stats1.errors_counting+1'b1; end
if (done_ref !== ( done_ref ^ done_dut ^ done_ref ))
begin if (stats1.errors_done == 0) stats1.errortime_done = $time;
stats1.errors_done = stats1.errors_done+1'b1; end
end
// add timeout after 100K cycles
initial begin
#1000000
$display("TIMEOUT");
$finish();
end
endmodule
|
Subsets and Splits