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;
; Sharp OZ family functions
;
; ported from the OZ-7xx SDK by by Alexander R. Pruss
; by Stefano Bodrato - Oct. 2003
;
; Serial libraries
; serial control commands
;
; ------
; $Id: ozparity.asm,v 1.3 2016-06-27 21:25:36 dom Exp $
;
SECTION code_clib
PUBLIC ozparity
PUBLIC _ozparity
ozparity:
_ozparity:
ld hl,2
add hl,sp
in a,(43h)
and 1+2+4+40h+80h
or (hl)
out (43h),a
ret
| {
"language": "Assembly"
} |
//===----------------------------------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is dual licensed under the MIT and the University of Illinois Open
// Source Licenses. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include <experimental/string_view>
int main () {}
| {
"language": "Assembly"
} |
glabel func_80A9BFA8
/* 01008 80A9BFA8 27BDFFE8 */ addiu $sp, $sp, 0xFFE8 ## $sp = FFFFFFE8
/* 0100C 80A9BFAC AFBF0014 */ sw $ra, 0x0014($sp)
/* 01010 80A9BFB0 AFA5001C */ sw $a1, 0x001C($sp)
/* 01014 80A9BFB4 848E019C */ lh $t6, 0x019C($a0) ## 0000019C
/* 01018 80A9BFB8 00803825 */ or $a3, $a0, $zero ## $a3 = 00000000
/* 0101C 80A9BFBC 24840028 */ addiu $a0, $a0, 0x0028 ## $a0 = 00000028
/* 01020 80A9BFC0 29C10079 */ slti $at, $t6, 0x0079
/* 01024 80A9BFC4 1420000D */ bne $at, $zero, .L80A9BFFC
/* 01028 80A9BFC8 3C063F19 */ lui $a2, 0x3F19 ## $a2 = 3F190000
/* 0102C 80A9BFCC 8CE5000C */ lw $a1, 0x000C($a3) ## 0000000C
/* 01030 80A9BFD0 AFA70018 */ sw $a3, 0x0018($sp)
/* 01034 80A9BFD4 0C01DE80 */ jal Math_ApproxF
/* 01038 80A9BFD8 34C6999A */ ori $a2, $a2, 0x999A ## $a2 = 3F19999A
/* 0103C 80A9BFDC 10400007 */ beq $v0, $zero, .L80A9BFFC
/* 01040 80A9BFE0 8FA70018 */ lw $a3, 0x0018($sp)
/* 01044 80A9BFE4 84EF019C */ lh $t7, 0x019C($a3) ## 0000019C
/* 01048 80A9BFE8 29E100AA */ slti $at, $t7, 0x00AA
/* 0104C 80A9BFEC 54200004 */ bnel $at, $zero, .L80A9C000
/* 01050 80A9BFF0 8FBF0014 */ lw $ra, 0x0014($sp)
/* 01054 80A9BFF4 0C2A7003 */ jal func_80A9C00C
/* 01058 80A9BFF8 00E02025 */ or $a0, $a3, $zero ## $a0 = 00000000
.L80A9BFFC:
/* 0105C 80A9BFFC 8FBF0014 */ lw $ra, 0x0014($sp)
.L80A9C000:
/* 01060 80A9C000 27BD0018 */ addiu $sp, $sp, 0x0018 ## $sp = 00000000
/* 01064 80A9C004 03E00008 */ jr $ra
/* 01068 80A9C008 00000000 */ nop
| {
"language": "Assembly"
} |
;
; File: lib16\s2fat12.inc
;
; Descrição:
; Suporte ao sistema de arquivos fat12 para 16bit real mode.
; Obs: fat12 também pode ser usado em HDs, VHDs e outras mídias, como
; emuladores de floppy.
;
; Histórico:
; Versão: 1.0, 2013 - Created.
; Versão: 1.0, 2016 - Revision.
;
;------------------------------------------------------------------------------
; ReadSectors:
;
; Reads "cx" sectors from disk starting at "ax" into memory location "es:bx".
; ~Lê 'cx' setores do 'disco' começando em 'ax' e coloca na memória em 'es:bx'.
;------------------------------------------------------------------------------
;s2fat12ReadSectors:
ReadSectors:
rmain:
mov di, word 0x0005 ;five retries for error
.SECTORLOOP:
push ax
push bx
push cx
call LBACHS
mov ax, 0x0201 ;BIOS read sector. Read one sector.
mov ch, BYTE [absoluteTrack] ;track
mov cl, BYTE [absoluteSector] ;sector
mov dh, BYTE [absoluteHead] ;head
mov dl, BYTE [DriveNumber] ;drive
.rSec:
int 0x13 ;invoke BIOS
jc .rSec ;test for read error
.SUCCESS:
call Window.StatusBar
mov si, msgProgress
call PoeString
pop cx
pop bx
pop ax
add bx, WORD [BytesPerSector] ;queue next buffer
inc ax ;queue next sector
loop rmain ;read next sector
ret
;----------------------------------------------------------------------
; ClusterLBA - convert FAT cluster into LBA addressing scheme
;
; LBA = (cluster - 2) * sectors per cluster
;----------------------------------------------------------------------
ClusterLBA:
sub ax, 0x0002 ;zero base cluster number
xor cx, cx
mov cl, BYTE [SectorsPerCluster] ;convert byte to word
mul cx
add ax, WORD [datasector] ;base data sector
ret
;---------------------------------------------------------------------------
; LBACHS - Convert LBA addressing scheme to CHS addressing scheme.
;
; absolute sector = (logical sector / sectors per track) + 1
; absolute head = (logical sector / sectors per track) MOD number of heads
; absolute track = logical sector / (sectors per track * number of heads)
;---------------------------------------------------------------------------
LBACHS:
xor dx, dx ;prepare dx:ax for operation
div WORD [SectorsPerTrack] ;'18' calculate
inc dl ;adjust for sector 0
mov BYTE [absoluteSector], dl
xor dx, dx ;prepare dx:ax for operation
div WORD [NumHeads] ;calculate... '2'
mov BYTE [absoluteHead], dl
mov BYTE [absoluteTrack], al
ret
;------------------------------------
; carregar_begin:
; @todo: renomear.
;
;load_begin:
carregar_begin:
;@todo , rever esse salvamento de cs:ip
pop ax
mov word [salva_carregar_ip], ax
pop ax
mov word [salva_carregar_cs], ax
cli
;registradores
xor ax, ax
xor bx, bx
xor cx, cx
xor dx, dx
;segmentos
mov ax, word 0x0000 ;segmento 0
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
;pilha
mov ax, word 0x0000
mov ss, ax
mov sp, word 0xFFFF
sti
call Device.ResetFloppy ;reseta FDC.
;Carrega o arquivo.
load_kernel32_sys:
push ax
mov ax, word [carregar_nome]
mov word [ImageNamePos], ax ;; Atualiza o endereço do nome do arquivo a ser lido
mov ax, word [carregar_seg]
mov word [destino_seg] , ax ;; Atualiza o Segmento que será carregado o arquivo
mov ax, word [carregar_off]
mov word [destino_off] , ax ;; Atualiza o Offset que será carregado o arquivo
pop ax
;Load root.
LOAD_ROOT:
; compute 'size' of root directory and store in "cx"
xor cx, cx
xor dx, dx
mov ax, 0x0020 ;; 32 byte directory entry
mul WORD [MaxRootEntries] ;; 0x00E0 224
div WORD [BytesPerSector] ;; 0x0200
xchg ax, cx
; compute 'location' of root directory and store in "ax"
; 2*9+1='19'
mov al, BYTE [TotalFATs] ;numero de fats
mul WORD [SectorsPerFAT] ;'vezes' os setores por FATs
add ax, WORD [ReservedSectors];; 1 ;'setores reservados'
mov WORD [datasector],ax ;base of root directory
add WORD [datasector],cx ;add o 'size' = 14 ...
;; read root directory into memory (7C00:0200)
mov bx, buffer
call ReadSectors
; browse root directory for binary image
mov cx, WORD [MaxRootEntries] ;; load loop counter
mov di, buffer ; locate first root entry
.LOOP:
push cx
mov cx, 0x000B ;; eleven character name
mov si, word [ImageNamePos] ;;'ImageNamePos' comtem o endereço do nome do arquivo
push di
rep cmpsb ; test for entry match
pop di
je LOAD_FAT
pop cx
add di, 0x0020 ;; queue next directory entry
loop .LOOP
jmp FAILURE
;Load fat.
LOAD_FAT:
mov dx, WORD [di + 0x001A] ;; di= 200+20+1a
mov WORD [cluster], dx ; file's first cluster
;compute size of FAT and store in "cx"
xor ax, ax
mov al, BYTE [TotalFATs];;
mul WORD [SectorsPerFAT];;
mov cx, ax
; compute location of FAT and store in "ax"
mov ax, WORD [ReservedSectors] ; adjust for bootsector
; read FAT into memory (7C00:0200)
mov bx, buffer ; copy FAT above bootcode
call ReadSectors
; read image file into memory ;; 'es:bx' (0050:0000)
;
; Obs:
; Os segmentos sarão atualizados para carregar o arquivo, depois de
; carregado o arquivo, os segmentos precisam voltar pra zero.
;
mov ax, word [destino_seg] ;Destination for image.
mov es, ax
mov bx, word [destino_off] ;Destination for image.
push bx
;Load image.
LOAD_IMAGE:
mov ax, WORD [cluster] ; cluster to read
pop bx ; buffer to read into
call ClusterLBA ; convert cluster to LBA
xor cx, cx
mov cl, BYTE [SectorsPerCluster] ; sectors to read
call ReadSectors
push bx
;Compute next cluster.
mov ax, WORD [cluster] ; identify current cluster
mov cx, ax ; copy current cluster
mov dx, ax ; copy current cluster
shr dx, 0x0001 ; divide by two
add cx, dx ; sum for (3/2)
mov bx, buffer ; location of FAT in memory
add bx, cx ; index into FAT
mov dx, WORD [bx] ; read two bytes from FAT
test ax, 0x0001
jnz .ODD_CLUSTER
.EVEN_CLUSTER:
and dx, 0000111111111111b ;Take low twelve bits.
jmp .DONE
.ODD_CLUSTER:
shr dx, 0x0004 ;Take high twelve bits.
.DONE:
mov WORD [cluster], dx ;Store new cluster.
cmp dx, 0x0FF0 ;Test for end of file.
jb LOAD_IMAGE
carregar_end:
;Post message.
pusha
call Window.ClearScreen
call Window.StatusBar
mov si, word [carregar_msg]
call PoeString
popa
; Retornando de forma segura, usando cs:ip salvos.
mov ax, word [salva_carregar_cs]
push ax
mov ax, word [salva_carregar_ip]
push ax
xor ax, ax
retf
;----------------------------
; FAILURE:
; Erro fatal, abortar.
;
FAILURE:
call Window.StatusBar
mov si, msgFailure
call PoeString
mov ah, 0x00
int 0x16
int 0x19
;Variáveis.
carregar_nome: dw 0 ;Nome.
carregar_seg: dw 0 ;Segmento.
carregar_off: dw 0 ;Offset.
carregar_msg: dw 0 ;Mensagem.
;Mensagens.
msg_debug_root db "fat12: 1 root",0
msg_debug_fat db "fat12: 2 fat",0
msg_debug_img db "fat12: 3 image",0
msg_debug_end db "fat12: 4 Ok",0
;----------------------------------------
; buffer:
; BUFFER, usado para carregar FAT e ROOTDIR.
; @todo: Rever esse buffer, precisamos de espaço no boot manager.
;
buffer:
times (512*2) db 0
;
; End.
;
| {
"language": "Assembly"
} |
! Copyright 2000-2016 The OpenSSL Project Authors. All Rights Reserved.
!
! Licensed under the OpenSSL license (the "License"). You may not use
! this file except in compliance with the License. You can obtain a copy
! in the file LICENSE in the source distribution or at
! https://www.openssl.org/source/license.html
!
! To expand the m4 macros: m4 -B 8192 des_enc.m4 > des_enc.S
!
! Global registers 1 to 5 are used. This is the same as done by the
! cc compiler. The UltraSPARC load/store little endian feature is used.
!
! Instruction grouping often refers to one CPU cycle.
!
! Assemble through gcc: gcc -c -mcpu=ultrasparc -o des_enc.o des_enc.S
!
! Assemble through cc: cc -c -xarch=v8plusa -o des_enc.o des_enc.S
!
! Performance improvement according to './apps/openssl speed des'
!
! 32-bit build:
! 23% faster than cc-5.2 -xarch=v8plus -xO5
! 115% faster than gcc-3.2.1 -m32 -mcpu=ultrasparc -O5
! 64-bit build:
! 50% faster than cc-5.2 -xarch=v9 -xO5
! 100% faster than gcc-3.2.1 -m64 -mcpu=ultrasparc -O5
!
.ident "des_enc.m4 2.1"
.file "des_enc-sparc.S"
#include <openssl/opensslconf.h>
#ifdef OPENSSL_FIPSCANISTER
#include <openssl/fipssyms.h>
#endif
#if defined(__SUNPRO_C) && defined(__sparcv9)
# define ABI64 /* They've said -xarch=v9 at command line */
#elif defined(__GNUC__) && defined(__arch64__)
# define ABI64 /* They've said -m64 at command line */
#endif
#ifdef ABI64
.register %g2,#scratch
.register %g3,#scratch
# define FRAME -192
# define BIAS 2047
# define LDPTR ldx
# define STPTR stx
# define ARG0 128
# define ARGSZ 8
#else
# define FRAME -96
# define BIAS 0
# define LDPTR ld
# define STPTR st
# define ARG0 68
# define ARGSZ 4
#endif
#define LOOPS 7
#define global0 %g0
#define global1 %g1
#define global2 %g2
#define global3 %g3
#define global4 %g4
#define global5 %g5
#define local0 %l0
#define local1 %l1
#define local2 %l2
#define local3 %l3
#define local4 %l4
#define local5 %l5
#define local7 %l6
#define local6 %l7
#define in0 %i0
#define in1 %i1
#define in2 %i2
#define in3 %i3
#define in4 %i4
#define in5 %i5
#define in6 %i6
#define in7 %i7
#define out0 %o0
#define out1 %o1
#define out2 %o2
#define out3 %o3
#define out4 %o4
#define out5 %o5
#define out6 %o6
#define out7 %o7
#define stub stb
changequote({,})
! Macro definitions:
! {ip_macro}
!
! The logic used in initial and final permutations is the same as in
! the C code. The permutations are done with a clever shift, xor, and
! technique.
!
! The macro also loads address sbox 1 to 5 to global 1 to 5, address
! sbox 6 to local6, and addres sbox 8 to out3.
!
! Rotates the halfs 3 left to bring the sbox bits in convenient positions.
!
! Loads key first round from address in parameter 5 to out0, out1.
!
! After the the original LibDES initial permutation, the resulting left
! is in the variable initially used for right and vice versa. The macro
! implements the possibility to keep the halfs in the original registers.
!
! parameter 1 left
! parameter 2 right
! parameter 3 result left (modify in first round)
! parameter 4 result right (use in first round)
! parameter 5 key address
! parameter 6 1/2 for include encryption/decryption
! parameter 7 1 for move in1 to in3
! parameter 8 1 for move in3 to in4, 2 for move in4 to in3
! parameter 9 1 for load ks3 and ks2 to in4 and in3
define(ip_macro, {
! {ip_macro}
! $1 $2 $4 $3 $5 $6 $7 $8 $9
ld [out2+256], local1
srl $2, 4, local4
xor local4, $1, local4
ifelse($7,1,{mov in1, in3},{nop})
ld [out2+260], local2
and local4, local1, local4
ifelse($8,1,{mov in3, in4},{})
ifelse($8,2,{mov in4, in3},{})
ld [out2+280], out4 ! loop counter
sll local4, 4, local1
xor $1, local4, $1
ld [out2+264], local3
srl $1, 16, local4
xor $2, local1, $2
ifelse($9,1,{LDPTR KS3, in4},{})
xor local4, $2, local4
nop !sethi %hi(DES_SPtrans), global1 ! sbox addr
ifelse($9,1,{LDPTR KS2, in3},{})
and local4, local2, local4
nop !or global1, %lo(DES_SPtrans), global1 ! sbox addr
sll local4, 16, local1
xor $2, local4, $2
srl $2, 2, local4
xor $1, local1, $1
sethi %hi(16711680), local5
xor local4, $1, local4
and local4, local3, local4
or local5, 255, local5
sll local4, 2, local2
xor $1, local4, $1
srl $1, 8, local4
xor $2, local2, $2
xor local4, $2, local4
add global1, 768, global4
and local4, local5, local4
add global1, 1024, global5
ld [out2+272], local7
sll local4, 8, local1
xor $2, local4, $2
srl $2, 1, local4
xor $1, local1, $1
ld [$5], out0 ! key 7531
xor local4, $1, local4
add global1, 256, global2
ld [$5+4], out1 ! key 8642
and local4, local7, local4
add global1, 512, global3
sll local4, 1, local1
xor $1, local4, $1
sll $1, 3, local3
xor $2, local1, $2
sll $2, 3, local2
add global1, 1280, local6 ! address sbox 8
srl $1, 29, local4
add global1, 1792, out3 ! address sbox 8
srl $2, 29, local1
or local4, local3, $4
or local2, local1, $3
ifelse($6, 1, {
ld [out2+284], local5 ! 0x0000FC00 used in the rounds
or local2, local1, $3
xor $4, out0, local1
call .des_enc.1
and local1, 252, local1
},{})
ifelse($6, 2, {
ld [out2+284], local5 ! 0x0000FC00 used in the rounds
or local2, local1, $3
xor $4, out0, local1
call .des_dec.1
and local1, 252, local1
},{})
})
! {rounds_macro}
!
! The logic used in the DES rounds is the same as in the C code,
! except that calculations for sbox 1 and sbox 5 begin before
! the previous round is finished.
!
! In each round one half (work) is modified based on key and the
! other half (use).
!
! In this version we do two rounds in a loop repeated 7 times
! and two rounds separately.
!
! One half has the bits for the sboxes in the following positions:
!
! 777777xx555555xx333333xx111111xx
!
! 88xx666666xx444444xx222222xx8888
!
! The bits for each sbox are xor-ed with the key bits for that box.
! The above xx bits are cleared, and the result used for lookup in
! the sbox table. Each sbox entry contains the 4 output bits permuted
! into 32 bits according to the P permutation.
!
! In the description of DES, left and right are switched after
! each round, except after last round. In this code the original
! left and right are kept in the same register in all rounds, meaning
! that after the 16 rounds the result for right is in the register
! originally used for left.
!
! parameter 1 first work (left in first round)
! parameter 2 first use (right in first round)
! parameter 3 enc/dec 1/-1
! parameter 4 loop label
! parameter 5 key address register
! parameter 6 optional address for key next encryption/decryption
! parameter 7 not empty for include retl
!
! also compares in2 to 8
define(rounds_macro, {
! {rounds_macro}
! $1 $2 $3 $4 $5 $6 $7 $8 $9
xor $2, out0, local1
ld [out2+284], local5 ! 0x0000FC00
ba $4
and local1, 252, local1
.align 32
$4:
! local6 is address sbox 6
! out3 is address sbox 8
! out4 is loop counter
ld [global1+local1], local1
xor $2, out1, out1 ! 8642
xor $2, out0, out0 ! 7531
! fmovs %f0, %f0 ! fxor used for alignment
srl out1, 4, local0 ! rotate 4 right
and out0, local5, local3 ! 3
! fmovs %f0, %f0
ld [$5+$3*8], local7 ! key 7531 next round
srl local3, 8, local3 ! 3
and local0, 252, local2 ! 2
! fmovs %f0, %f0
ld [global3+local3],local3 ! 3
sll out1, 28, out1 ! rotate
xor $1, local1, $1 ! 1 finished, local1 now sbox 7
ld [global2+local2], local2 ! 2
srl out0, 24, local1 ! 7
or out1, local0, out1 ! rotate
ldub [out2+local1], local1 ! 7 (and 0xFC)
srl out1, 24, local0 ! 8
and out1, local5, local4 ! 4
ldub [out2+local0], local0 ! 8 (and 0xFC)
srl local4, 8, local4 ! 4
xor $1, local2, $1 ! 2 finished local2 now sbox 6
ld [global4+local4],local4 ! 4
srl out1, 16, local2 ! 6
xor $1, local3, $1 ! 3 finished local3 now sbox 5
ld [out3+local0],local0 ! 8
and local2, 252, local2 ! 6
add global1, 1536, local5 ! address sbox 7
ld [local6+local2], local2 ! 6
srl out0, 16, local3 ! 5
xor $1, local4, $1 ! 4 finished
ld [local5+local1],local1 ! 7
and local3, 252, local3 ! 5
xor $1, local0, $1 ! 8 finished
ld [global5+local3],local3 ! 5
xor $1, local2, $1 ! 6 finished
subcc out4, 1, out4
ld [$5+$3*8+4], out0 ! key 8642 next round
xor $1, local7, local2 ! sbox 5 next round
xor $1, local1, $1 ! 7 finished
srl local2, 16, local2 ! sbox 5 next round
xor $1, local3, $1 ! 5 finished
ld [$5+$3*16+4], out1 ! key 8642 next round again
and local2, 252, local2 ! sbox5 next round
! next round
xor $1, local7, local7 ! 7531
ld [global5+local2], local2 ! 5
srl local7, 24, local3 ! 7
xor $1, out0, out0 ! 8642
ldub [out2+local3], local3 ! 7 (and 0xFC)
srl out0, 4, local0 ! rotate 4 right
and local7, 252, local1 ! 1
sll out0, 28, out0 ! rotate
xor $2, local2, $2 ! 5 finished local2 used
srl local0, 8, local4 ! 4
and local0, 252, local2 ! 2
ld [local5+local3], local3 ! 7
srl local0, 16, local5 ! 6
or out0, local0, out0 ! rotate
ld [global2+local2], local2 ! 2
srl out0, 24, local0
ld [$5+$3*16], out0 ! key 7531 next round
and local4, 252, local4 ! 4
and local5, 252, local5 ! 6
ld [global4+local4], local4 ! 4
xor $2, local3, $2 ! 7 finished local3 used
and local0, 252, local0 ! 8
ld [local6+local5], local5 ! 6
xor $2, local2, $2 ! 2 finished local2 now sbox 3
srl local7, 8, local2 ! 3 start
ld [out3+local0], local0 ! 8
xor $2, local4, $2 ! 4 finished
and local2, 252, local2 ! 3
ld [global1+local1], local1 ! 1
xor $2, local5, $2 ! 6 finished local5 used
ld [global3+local2], local2 ! 3
xor $2, local0, $2 ! 8 finished
add $5, $3*16, $5 ! enc add 8, dec add -8 to key pointer
ld [out2+284], local5 ! 0x0000FC00
xor $2, out0, local4 ! sbox 1 next round
xor $2, local1, $2 ! 1 finished
xor $2, local2, $2 ! 3 finished
bne $4
and local4, 252, local1 ! sbox 1 next round
! two rounds more:
ld [global1+local1], local1
xor $2, out1, out1
xor $2, out0, out0
srl out1, 4, local0 ! rotate
and out0, local5, local3
ld [$5+$3*8], local7 ! key 7531
srl local3, 8, local3
and local0, 252, local2
ld [global3+local3],local3
sll out1, 28, out1 ! rotate
xor $1, local1, $1 ! 1 finished, local1 now sbox 7
ld [global2+local2], local2
srl out0, 24, local1
or out1, local0, out1 ! rotate
ldub [out2+local1], local1
srl out1, 24, local0
and out1, local5, local4
ldub [out2+local0], local0
srl local4, 8, local4
xor $1, local2, $1 ! 2 finished local2 now sbox 6
ld [global4+local4],local4
srl out1, 16, local2
xor $1, local3, $1 ! 3 finished local3 now sbox 5
ld [out3+local0],local0
and local2, 252, local2
add global1, 1536, local5 ! address sbox 7
ld [local6+local2], local2
srl out0, 16, local3
xor $1, local4, $1 ! 4 finished
ld [local5+local1],local1
and local3, 252, local3
xor $1, local0, $1
ld [global5+local3],local3
xor $1, local2, $1 ! 6 finished
cmp in2, 8
ifelse($6,{}, {}, {ld [out2+280], out4}) ! loop counter
xor $1, local7, local2 ! sbox 5 next round
xor $1, local1, $1 ! 7 finished
ld [$5+$3*8+4], out0
srl local2, 16, local2 ! sbox 5 next round
xor $1, local3, $1 ! 5 finished
and local2, 252, local2
! next round (two rounds more)
xor $1, local7, local7 ! 7531
ld [global5+local2], local2
srl local7, 24, local3
xor $1, out0, out0 ! 8642
ldub [out2+local3], local3
srl out0, 4, local0 ! rotate
and local7, 252, local1
sll out0, 28, out0 ! rotate
xor $2, local2, $2 ! 5 finished local2 used
srl local0, 8, local4
and local0, 252, local2
ld [local5+local3], local3
srl local0, 16, local5
or out0, local0, out0 ! rotate
ld [global2+local2], local2
srl out0, 24, local0
ifelse($6,{}, {}, {ld [$6], out0}) ! key next encryption/decryption
and local4, 252, local4
and local5, 252, local5
ld [global4+local4], local4
xor $2, local3, $2 ! 7 finished local3 used
and local0, 252, local0
ld [local6+local5], local5
xor $2, local2, $2 ! 2 finished local2 now sbox 3
srl local7, 8, local2 ! 3 start
ld [out3+local0], local0
xor $2, local4, $2
and local2, 252, local2
ld [global1+local1], local1
xor $2, local5, $2 ! 6 finished local5 used
ld [global3+local2], local2
srl $1, 3, local3
xor $2, local0, $2
ifelse($6,{}, {}, {ld [$6+4], out1}) ! key next encryption/decryption
sll $1, 29, local4
xor $2, local1, $2
ifelse($7,{}, {}, {retl})
xor $2, local2, $2
})
! {fp_macro}
!
! parameter 1 right (original left)
! parameter 2 left (original right)
! parameter 3 1 for optional store to [in0]
! parameter 4 1 for load input/output address to local5/7
!
! The final permutation logic switches the halfes, meaning that
! left and right ends up the the registers originally used.
define(fp_macro, {
! {fp_macro}
! $1 $2 $3 $4 $5 $6 $7 $8 $9
! initially undo the rotate 3 left done after initial permutation
! original left is received shifted 3 right and 29 left in local3/4
sll $2, 29, local1
or local3, local4, $1
srl $2, 3, $2
sethi %hi(0x55555555), local2
or $2, local1, $2
or local2, %lo(0x55555555), local2
srl $2, 1, local3
sethi %hi(0x00ff00ff), local1
xor local3, $1, local3
or local1, %lo(0x00ff00ff), local1
and local3, local2, local3
sethi %hi(0x33333333), local4
sll local3, 1, local2
xor $1, local3, $1
srl $1, 8, local3
xor $2, local2, $2
xor local3, $2, local3
or local4, %lo(0x33333333), local4
and local3, local1, local3
sethi %hi(0x0000ffff), local1
sll local3, 8, local2
xor $2, local3, $2
srl $2, 2, local3
xor $1, local2, $1
xor local3, $1, local3
or local1, %lo(0x0000ffff), local1
and local3, local4, local3
sethi %hi(0x0f0f0f0f), local4
sll local3, 2, local2
ifelse($4,1, {LDPTR INPUT, local5})
xor $1, local3, $1
ifelse($4,1, {LDPTR OUTPUT, local7})
srl $1, 16, local3
xor $2, local2, $2
xor local3, $2, local3
or local4, %lo(0x0f0f0f0f), local4
and local3, local1, local3
sll local3, 16, local2
xor $2, local3, local1
srl local1, 4, local3
xor $1, local2, $1
xor local3, $1, local3
and local3, local4, local3
sll local3, 4, local2
xor $1, local3, $1
! optional store:
ifelse($3,1, {st $1, [in0]})
xor local1, local2, $2
ifelse($3,1, {st $2, [in0+4]})
})
! {fp_ip_macro}
!
! Does initial permutation for next block mixed with
! final permutation for current block.
!
! parameter 1 original left
! parameter 2 original right
! parameter 3 left ip
! parameter 4 right ip
! parameter 5 1: load ks1/ks2 to in3/in4, add 120 to in4
! 2: mov in4 to in3
!
! also adds -8 to length in2 and loads loop counter to out4
define(fp_ip_macro, {
! {fp_ip_macro}
! $1 $2 $3 $4 $5 $6 $7 $8 $9
define({temp1},{out4})
define({temp2},{local3})
define({ip1},{local1})
define({ip2},{local2})
define({ip4},{local4})
define({ip5},{local5})
! $1 in local3, local4
ld [out2+256], ip1
sll out5, 29, temp1
or local3, local4, $1
srl out5, 3, $2
ifelse($5,2,{mov in4, in3})
ld [out2+272], ip5
srl $4, 4, local0
or $2, temp1, $2
srl $2, 1, temp1
xor temp1, $1, temp1
and temp1, ip5, temp1
xor local0, $3, local0
sll temp1, 1, temp2
xor $1, temp1, $1
and local0, ip1, local0
add in2, -8, in2
sll local0, 4, local7
xor $3, local0, $3
ld [out2+268], ip4
srl $1, 8, temp1
xor $2, temp2, $2
ld [out2+260], ip2
srl $3, 16, local0
xor $4, local7, $4
xor temp1, $2, temp1
xor local0, $4, local0
and temp1, ip4, temp1
and local0, ip2, local0
sll temp1, 8, temp2
xor $2, temp1, $2
sll local0, 16, local7
xor $4, local0, $4
srl $2, 2, temp1
xor $1, temp2, $1
ld [out2+264], temp2 ! ip3
srl $4, 2, local0
xor $3, local7, $3
xor temp1, $1, temp1
xor local0, $3, local0
and temp1, temp2, temp1
and local0, temp2, local0
sll temp1, 2, temp2
xor $1, temp1, $1
sll local0, 2, local7
xor $3, local0, $3
srl $1, 16, temp1
xor $2, temp2, $2
srl $3, 8, local0
xor $4, local7, $4
xor temp1, $2, temp1
xor local0, $4, local0
and temp1, ip2, temp1
and local0, ip4, local0
sll temp1, 16, temp2
xor $2, temp1, local4
sll local0, 8, local7
xor $4, local0, $4
srl $4, 1, local0
xor $3, local7, $3
srl local4, 4, temp1
xor local0, $3, local0
xor $1, temp2, $1
and local0, ip5, local0
sll local0, 1, local7
xor temp1, $1, temp1
xor $3, local0, $3
xor $4, local7, $4
sll $3, 3, local5
and temp1, ip1, temp1
sll temp1, 4, temp2
xor $1, temp1, $1
ifelse($5,1,{LDPTR KS2, in4})
sll $4, 3, local2
xor local4, temp2, $2
! reload since used as temporar:
ld [out2+280], out4 ! loop counter
srl $3, 29, local0
ifelse($5,1,{add in4, 120, in4})
ifelse($5,1,{LDPTR KS1, in3})
srl $4, 29, local7
or local0, local5, $4
or local2, local7, $3
})
! {load_little_endian}
!
! parameter 1 address
! parameter 2 destination left
! parameter 3 destination right
! parameter 4 temporar
! parameter 5 label
define(load_little_endian, {
! {load_little_endian}
! $1 $2 $3 $4 $5 $6 $7 $8 $9
! first in memory to rightmost in register
$5:
ldub [$1+3], $2
ldub [$1+2], $4
sll $2, 8, $2
or $2, $4, $2
ldub [$1+1], $4
sll $2, 8, $2
or $2, $4, $2
ldub [$1+0], $4
sll $2, 8, $2
or $2, $4, $2
ldub [$1+3+4], $3
ldub [$1+2+4], $4
sll $3, 8, $3
or $3, $4, $3
ldub [$1+1+4], $4
sll $3, 8, $3
or $3, $4, $3
ldub [$1+0+4], $4
sll $3, 8, $3
or $3, $4, $3
$5a:
})
! {load_little_endian_inc}
!
! parameter 1 address
! parameter 2 destination left
! parameter 3 destination right
! parameter 4 temporar
! parameter 4 label
!
! adds 8 to address
define(load_little_endian_inc, {
! {load_little_endian_inc}
! $1 $2 $3 $4 $5 $6 $7 $8 $9
! first in memory to rightmost in register
$5:
ldub [$1+3], $2
ldub [$1+2], $4
sll $2, 8, $2
or $2, $4, $2
ldub [$1+1], $4
sll $2, 8, $2
or $2, $4, $2
ldub [$1+0], $4
sll $2, 8, $2
or $2, $4, $2
ldub [$1+3+4], $3
add $1, 8, $1
ldub [$1+2+4-8], $4
sll $3, 8, $3
or $3, $4, $3
ldub [$1+1+4-8], $4
sll $3, 8, $3
or $3, $4, $3
ldub [$1+0+4-8], $4
sll $3, 8, $3
or $3, $4, $3
$5a:
})
! {load_n_bytes}
!
! Loads 1 to 7 bytes little endian
! Remaining bytes are zeroed.
!
! parameter 1 address
! parameter 2 length
! parameter 3 destination register left
! parameter 4 destination register right
! parameter 5 temp
! parameter 6 temp2
! parameter 7 label
! parameter 8 return label
define(load_n_bytes, {
! {load_n_bytes}
! $1 $2 $5 $6 $7 $8 $7 $8 $9
$7.0: call .+8
sll $2, 2, $6
add %o7,$7.jmp.table-$7.0,$5
add $5, $6, $5
mov 0, $4
ld [$5], $5
jmp %o7+$5
mov 0, $3
$7.7:
ldub [$1+6], $5
sll $5, 16, $5
or $3, $5, $3
$7.6:
ldub [$1+5], $5
sll $5, 8, $5
or $3, $5, $3
$7.5:
ldub [$1+4], $5
or $3, $5, $3
$7.4:
ldub [$1+3], $5
sll $5, 24, $5
or $4, $5, $4
$7.3:
ldub [$1+2], $5
sll $5, 16, $5
or $4, $5, $4
$7.2:
ldub [$1+1], $5
sll $5, 8, $5
or $4, $5, $4
$7.1:
ldub [$1+0], $5
ba $8
or $4, $5, $4
.align 4
$7.jmp.table:
.word 0
.word $7.1-$7.0
.word $7.2-$7.0
.word $7.3-$7.0
.word $7.4-$7.0
.word $7.5-$7.0
.word $7.6-$7.0
.word $7.7-$7.0
})
! {store_little_endian}
!
! parameter 1 address
! parameter 2 source left
! parameter 3 source right
! parameter 4 temporar
define(store_little_endian, {
! {store_little_endian}
! $1 $2 $3 $4 $5 $6 $7 $8 $9
! rightmost in register to first in memory
$5:
and $2, 255, $4
stub $4, [$1+0]
srl $2, 8, $4
and $4, 255, $4
stub $4, [$1+1]
srl $2, 16, $4
and $4, 255, $4
stub $4, [$1+2]
srl $2, 24, $4
stub $4, [$1+3]
and $3, 255, $4
stub $4, [$1+0+4]
srl $3, 8, $4
and $4, 255, $4
stub $4, [$1+1+4]
srl $3, 16, $4
and $4, 255, $4
stub $4, [$1+2+4]
srl $3, 24, $4
stub $4, [$1+3+4]
$5a:
})
! {store_n_bytes}
!
! Stores 1 to 7 bytes little endian
!
! parameter 1 address
! parameter 2 length
! parameter 3 source register left
! parameter 4 source register right
! parameter 5 temp
! parameter 6 temp2
! parameter 7 label
! parameter 8 return label
define(store_n_bytes, {
! {store_n_bytes}
! $1 $2 $5 $6 $7 $8 $7 $8 $9
$7.0: call .+8
sll $2, 2, $6
add %o7,$7.jmp.table-$7.0,$5
add $5, $6, $5
ld [$5], $5
jmp %o7+$5
nop
$7.7:
srl $3, 16, $5
and $5, 0xff, $5
stub $5, [$1+6]
$7.6:
srl $3, 8, $5
and $5, 0xff, $5
stub $5, [$1+5]
$7.5:
and $3, 0xff, $5
stub $5, [$1+4]
$7.4:
srl $4, 24, $5
stub $5, [$1+3]
$7.3:
srl $4, 16, $5
and $5, 0xff, $5
stub $5, [$1+2]
$7.2:
srl $4, 8, $5
and $5, 0xff, $5
stub $5, [$1+1]
$7.1:
and $4, 0xff, $5
ba $8
stub $5, [$1]
.align 4
$7.jmp.table:
.word 0
.word $7.1-$7.0
.word $7.2-$7.0
.word $7.3-$7.0
.word $7.4-$7.0
.word $7.5-$7.0
.word $7.6-$7.0
.word $7.7-$7.0
})
define(testvalue,{1})
define(register_init, {
! For test purposes:
sethi %hi(testvalue), local0
or local0, %lo(testvalue), local0
ifelse($1,{},{}, {mov local0, $1})
ifelse($2,{},{}, {mov local0, $2})
ifelse($3,{},{}, {mov local0, $3})
ifelse($4,{},{}, {mov local0, $4})
ifelse($5,{},{}, {mov local0, $5})
ifelse($6,{},{}, {mov local0, $6})
ifelse($7,{},{}, {mov local0, $7})
ifelse($8,{},{}, {mov local0, $8})
mov local0, local1
mov local0, local2
mov local0, local3
mov local0, local4
mov local0, local5
mov local0, local7
mov local0, local6
mov local0, out0
mov local0, out1
mov local0, out2
mov local0, out3
mov local0, out4
mov local0, out5
mov local0, global1
mov local0, global2
mov local0, global3
mov local0, global4
mov local0, global5
})
.section ".text"
.align 32
.des_enc:
! key address in3
! loads key next encryption/decryption first round from [in4]
rounds_macro(in5, out5, 1, .des_enc.1, in3, in4, retl)
.align 32
.des_dec:
! implemented with out5 as first parameter to avoid
! register exchange in ede modes
! key address in4
! loads key next encryption/decryption first round from [in3]
rounds_macro(out5, in5, -1, .des_dec.1, in4, in3, retl)
! void DES_encrypt1(data, ks, enc)
! *******************************
.align 32
.global DES_encrypt1
.type DES_encrypt1,#function
DES_encrypt1:
save %sp, FRAME, %sp
sethi %hi(.PIC.DES_SPtrans-1f),global1
or global1,%lo(.PIC.DES_SPtrans-1f),global1
1: call .+8
add %o7,global1,global1
sub global1,.PIC.DES_SPtrans-.des_and,out2
ld [in0], in5 ! left
cmp in2, 0 ! enc
be .encrypt.dec
ld [in0+4], out5 ! right
! parameter 6 1/2 for include encryption/decryption
! parameter 7 1 for move in1 to in3
! parameter 8 1 for move in3 to in4, 2 for move in4 to in3
ip_macro(in5, out5, in5, out5, in3, 0, 1, 1)
rounds_macro(in5, out5, 1, .des_encrypt1.1, in3, in4) ! in4 not used
fp_macro(in5, out5, 1) ! 1 for store to [in0]
ret
restore
.encrypt.dec:
add in1, 120, in3 ! use last subkey for first round
! parameter 6 1/2 for include encryption/decryption
! parameter 7 1 for move in1 to in3
! parameter 8 1 for move in3 to in4, 2 for move in4 to in3
ip_macro(in5, out5, out5, in5, in4, 2, 0, 1) ! include dec, ks in4
fp_macro(out5, in5, 1) ! 1 for store to [in0]
ret
restore
.DES_encrypt1.end:
.size DES_encrypt1,.DES_encrypt1.end-DES_encrypt1
! void DES_encrypt2(data, ks, enc)
!*********************************
! encrypts/decrypts without initial/final permutation
.align 32
.global DES_encrypt2
.type DES_encrypt2,#function
DES_encrypt2:
save %sp, FRAME, %sp
sethi %hi(.PIC.DES_SPtrans-1f),global1
or global1,%lo(.PIC.DES_SPtrans-1f),global1
1: call .+8
add %o7,global1,global1
sub global1,.PIC.DES_SPtrans-.des_and,out2
! Set sbox address 1 to 6 and rotate halfs 3 left
! Errors caught by destest? Yes. Still? *NO*
!sethi %hi(DES_SPtrans), global1 ! address sbox 1
!or global1, %lo(DES_SPtrans), global1 ! sbox 1
add global1, 256, global2 ! sbox 2
add global1, 512, global3 ! sbox 3
ld [in0], out5 ! right
add global1, 768, global4 ! sbox 4
add global1, 1024, global5 ! sbox 5
ld [in0+4], in5 ! left
add global1, 1280, local6 ! sbox 6
add global1, 1792, out3 ! sbox 8
! rotate
sll in5, 3, local5
mov in1, in3 ! key address to in3
sll out5, 3, local7
srl in5, 29, in5
srl out5, 29, out5
add in5, local5, in5
add out5, local7, out5
cmp in2, 0
! we use our own stackframe
be .encrypt2.dec
STPTR in0, [%sp+BIAS+ARG0+0*ARGSZ]
ld [in3], out0 ! key 7531 first round
mov LOOPS, out4 ! loop counter
ld [in3+4], out1 ! key 8642 first round
sethi %hi(0x0000FC00), local5
call .des_enc
mov in3, in4
! rotate
sll in5, 29, in0
srl in5, 3, in5
sll out5, 29, in1
add in5, in0, in5
srl out5, 3, out5
LDPTR [%sp+BIAS+ARG0+0*ARGSZ], in0
add out5, in1, out5
st in5, [in0]
st out5, [in0+4]
ret
restore
.encrypt2.dec:
add in3, 120, in4
ld [in4], out0 ! key 7531 first round
mov LOOPS, out4 ! loop counter
ld [in4+4], out1 ! key 8642 first round
sethi %hi(0x0000FC00), local5
mov in5, local1 ! left expected in out5
mov out5, in5
call .des_dec
mov local1, out5
.encrypt2.finish:
! rotate
sll in5, 29, in0
srl in5, 3, in5
sll out5, 29, in1
add in5, in0, in5
srl out5, 3, out5
LDPTR [%sp+BIAS+ARG0+0*ARGSZ], in0
add out5, in1, out5
st out5, [in0]
st in5, [in0+4]
ret
restore
.DES_encrypt2.end:
.size DES_encrypt2, .DES_encrypt2.end-DES_encrypt2
! void DES_encrypt3(data, ks1, ks2, ks3)
! **************************************
.align 32
.global DES_encrypt3
.type DES_encrypt3,#function
DES_encrypt3:
save %sp, FRAME, %sp
sethi %hi(.PIC.DES_SPtrans-1f),global1
or global1,%lo(.PIC.DES_SPtrans-1f),global1
1: call .+8
add %o7,global1,global1
sub global1,.PIC.DES_SPtrans-.des_and,out2
ld [in0], in5 ! left
add in2, 120, in4 ! ks2
ld [in0+4], out5 ! right
mov in3, in2 ! save ks3
! parameter 6 1/2 for include encryption/decryption
! parameter 7 1 for mov in1 to in3
! parameter 8 1 for mov in3 to in4
! parameter 9 1 for load ks3 and ks2 to in4 and in3
ip_macro(in5, out5, in5, out5, in3, 1, 1, 0, 0)
call .des_dec
mov in2, in3 ! preload ks3
call .des_enc
nop
fp_macro(in5, out5, 1)
ret
restore
.DES_encrypt3.end:
.size DES_encrypt3,.DES_encrypt3.end-DES_encrypt3
! void DES_decrypt3(data, ks1, ks2, ks3)
! **************************************
.align 32
.global DES_decrypt3
.type DES_decrypt3,#function
DES_decrypt3:
save %sp, FRAME, %sp
sethi %hi(.PIC.DES_SPtrans-1f),global1
or global1,%lo(.PIC.DES_SPtrans-1f),global1
1: call .+8
add %o7,global1,global1
sub global1,.PIC.DES_SPtrans-.des_and,out2
ld [in0], in5 ! left
add in3, 120, in4 ! ks3
ld [in0+4], out5 ! right
mov in2, in3 ! ks2
! parameter 6 1/2 for include encryption/decryption
! parameter 7 1 for mov in1 to in3
! parameter 8 1 for mov in3 to in4
! parameter 9 1 for load ks3 and ks2 to in4 and in3
ip_macro(in5, out5, out5, in5, in4, 2, 0, 0, 0)
call .des_enc
add in1, 120, in4 ! preload ks1
call .des_dec
nop
fp_macro(out5, in5, 1)
ret
restore
.DES_decrypt3.end:
.size DES_decrypt3,.DES_decrypt3.end-DES_decrypt3
! void DES_ncbc_encrypt(input, output, length, schedule, ivec, enc)
! *****************************************************************
.align 32
.global DES_ncbc_encrypt
.type DES_ncbc_encrypt,#function
DES_ncbc_encrypt:
save %sp, FRAME, %sp
define({INPUT}, { [%sp+BIAS+ARG0+0*ARGSZ] })
define({OUTPUT}, { [%sp+BIAS+ARG0+1*ARGSZ] })
define({IVEC}, { [%sp+BIAS+ARG0+4*ARGSZ] })
sethi %hi(.PIC.DES_SPtrans-1f),global1
or global1,%lo(.PIC.DES_SPtrans-1f),global1
1: call .+8
add %o7,global1,global1
sub global1,.PIC.DES_SPtrans-.des_and,out2
cmp in5, 0 ! enc
be .ncbc.dec
STPTR in4, IVEC
! addr left right temp label
load_little_endian(in4, in5, out5, local3, .LLE1) ! iv
addcc in2, -8, in2 ! bytes missing when first block done
bl .ncbc.enc.seven.or.less
mov in3, in4 ! schedule
.ncbc.enc.next.block:
load_little_endian(in0, out4, global4, local3, .LLE2) ! block
.ncbc.enc.next.block_1:
xor in5, out4, in5 ! iv xor
xor out5, global4, out5 ! iv xor
! parameter 8 1 for move in3 to in4, 2 for move in4 to in3
ip_macro(in5, out5, in5, out5, in3, 0, 0, 2)
.ncbc.enc.next.block_2:
!// call .des_enc ! compares in2 to 8
! rounds inlined for alignment purposes
add global1, 768, global4 ! address sbox 4 since register used below
rounds_macro(in5, out5, 1, .ncbc.enc.1, in3, in4) ! include encryption ks in3
bl .ncbc.enc.next.block_fp
add in0, 8, in0 ! input address
! If 8 or more bytes are to be encrypted after this block,
! we combine final permutation for this block with initial
! permutation for next block. Load next block:
load_little_endian(in0, global3, global4, local5, .LLE12)
! parameter 1 original left
! parameter 2 original right
! parameter 3 left ip
! parameter 4 right ip
! parameter 5 1: load ks1/ks2 to in3/in4, add 120 to in4
! 2: mov in4 to in3
!
! also adds -8 to length in2 and loads loop counter to out4
fp_ip_macro(out0, out1, global3, global4, 2)
store_little_endian(in1, out0, out1, local3, .SLE10) ! block
ld [in3], out0 ! key 7531 first round next block
mov in5, local1
xor global3, out5, in5 ! iv xor next block
ld [in3+4], out1 ! key 8642
add global1, 512, global3 ! address sbox 3 since register used
xor global4, local1, out5 ! iv xor next block
ba .ncbc.enc.next.block_2
add in1, 8, in1 ! output address
.ncbc.enc.next.block_fp:
fp_macro(in5, out5)
store_little_endian(in1, in5, out5, local3, .SLE1) ! block
addcc in2, -8, in2 ! bytes missing when next block done
bpos .ncbc.enc.next.block
add in1, 8, in1
.ncbc.enc.seven.or.less:
cmp in2, -8
ble .ncbc.enc.finish
nop
add in2, 8, local1 ! bytes to load
! addr, length, dest left, dest right, temp, temp2, label, ret label
load_n_bytes(in0, local1, global4, out4, local2, local3, .LNB1, .ncbc.enc.next.block_1)
! Loads 1 to 7 bytes little endian to global4, out4
.ncbc.enc.finish:
LDPTR IVEC, local4
store_little_endian(local4, in5, out5, local5, .SLE2) ! ivec
ret
restore
.ncbc.dec:
STPTR in0, INPUT
cmp in2, 0 ! length
add in3, 120, in3
LDPTR IVEC, local7 ! ivec
ble .ncbc.dec.finish
mov in3, in4 ! schedule
STPTR in1, OUTPUT
mov in0, local5 ! input
load_little_endian(local7, in0, in1, local3, .LLE3) ! ivec
.ncbc.dec.next.block:
load_little_endian(local5, in5, out5, local3, .LLE4) ! block
! parameter 6 1/2 for include encryption/decryption
! parameter 7 1 for mov in1 to in3
! parameter 8 1 for mov in3 to in4
ip_macro(in5, out5, out5, in5, in4, 2, 0, 1) ! include decryprion ks in4
fp_macro(out5, in5, 0, 1) ! 1 for input and output address to local5/7
! in2 is bytes left to be stored
! in2 is compared to 8 in the rounds
xor out5, in0, out4 ! iv xor
bl .ncbc.dec.seven.or.less
xor in5, in1, global4 ! iv xor
! Load ivec next block now, since input and output address might be the same.
load_little_endian_inc(local5, in0, in1, local3, .LLE5) ! iv
store_little_endian(local7, out4, global4, local3, .SLE3)
STPTR local5, INPUT
add local7, 8, local7
addcc in2, -8, in2
bg .ncbc.dec.next.block
STPTR local7, OUTPUT
.ncbc.dec.store.iv:
LDPTR IVEC, local4 ! ivec
store_little_endian(local4, in0, in1, local5, .SLE4)
.ncbc.dec.finish:
ret
restore
.ncbc.dec.seven.or.less:
load_little_endian_inc(local5, in0, in1, local3, .LLE13) ! ivec
store_n_bytes(local7, in2, global4, out4, local3, local4, .SNB1, .ncbc.dec.store.iv)
.DES_ncbc_encrypt.end:
.size DES_ncbc_encrypt, .DES_ncbc_encrypt.end-DES_ncbc_encrypt
! void DES_ede3_cbc_encrypt(input, output, lenght, ks1, ks2, ks3, ivec, enc)
! **************************************************************************
.align 32
.global DES_ede3_cbc_encrypt
.type DES_ede3_cbc_encrypt,#function
DES_ede3_cbc_encrypt:
save %sp, FRAME, %sp
define({KS1}, { [%sp+BIAS+ARG0+3*ARGSZ] })
define({KS2}, { [%sp+BIAS+ARG0+4*ARGSZ] })
define({KS3}, { [%sp+BIAS+ARG0+5*ARGSZ] })
sethi %hi(.PIC.DES_SPtrans-1f),global1
or global1,%lo(.PIC.DES_SPtrans-1f),global1
1: call .+8
add %o7,global1,global1
sub global1,.PIC.DES_SPtrans-.des_and,out2
LDPTR [%fp+BIAS+ARG0+7*ARGSZ], local3 ! enc
LDPTR [%fp+BIAS+ARG0+6*ARGSZ], local4 ! ivec
cmp local3, 0 ! enc
be .ede3.dec
STPTR in4, KS2
STPTR in5, KS3
load_little_endian(local4, in5, out5, local3, .LLE6) ! ivec
addcc in2, -8, in2 ! bytes missing after next block
bl .ede3.enc.seven.or.less
STPTR in3, KS1
.ede3.enc.next.block:
load_little_endian(in0, out4, global4, local3, .LLE7)
.ede3.enc.next.block_1:
LDPTR KS2, in4
xor in5, out4, in5 ! iv xor
xor out5, global4, out5 ! iv xor
LDPTR KS1, in3
add in4, 120, in4 ! for decryption we use last subkey first
nop
ip_macro(in5, out5, in5, out5, in3)
.ede3.enc.next.block_2:
call .des_enc ! ks1 in3
nop
call .des_dec ! ks2 in4
LDPTR KS3, in3
call .des_enc ! ks3 in3 compares in2 to 8
nop
bl .ede3.enc.next.block_fp
add in0, 8, in0
! If 8 or more bytes are to be encrypted after this block,
! we combine final permutation for this block with initial
! permutation for next block. Load next block:
load_little_endian(in0, global3, global4, local5, .LLE11)
! parameter 1 original left
! parameter 2 original right
! parameter 3 left ip
! parameter 4 right ip
! parameter 5 1: load ks1/ks2 to in3/in4, add 120 to in4
! 2: mov in4 to in3
!
! also adds -8 to length in2 and loads loop counter to out4
fp_ip_macro(out0, out1, global3, global4, 1)
store_little_endian(in1, out0, out1, local3, .SLE9) ! block
mov in5, local1
xor global3, out5, in5 ! iv xor next block
ld [in3], out0 ! key 7531
add global1, 512, global3 ! address sbox 3
xor global4, local1, out5 ! iv xor next block
ld [in3+4], out1 ! key 8642
add global1, 768, global4 ! address sbox 4
ba .ede3.enc.next.block_2
add in1, 8, in1
.ede3.enc.next.block_fp:
fp_macro(in5, out5)
store_little_endian(in1, in5, out5, local3, .SLE5) ! block
addcc in2, -8, in2 ! bytes missing when next block done
bpos .ede3.enc.next.block
add in1, 8, in1
.ede3.enc.seven.or.less:
cmp in2, -8
ble .ede3.enc.finish
nop
add in2, 8, local1 ! bytes to load
! addr, length, dest left, dest right, temp, temp2, label, ret label
load_n_bytes(in0, local1, global4, out4, local2, local3, .LNB2, .ede3.enc.next.block_1)
.ede3.enc.finish:
LDPTR [%fp+BIAS+ARG0+6*ARGSZ], local4 ! ivec
store_little_endian(local4, in5, out5, local5, .SLE6) ! ivec
ret
restore
.ede3.dec:
STPTR in0, INPUT
add in5, 120, in5
STPTR in1, OUTPUT
mov in0, local5
add in3, 120, in3
STPTR in3, KS1
cmp in2, 0
ble .ede3.dec.finish
STPTR in5, KS3
LDPTR [%fp+BIAS+ARG0+6*ARGSZ], local7 ! iv
load_little_endian(local7, in0, in1, local3, .LLE8)
.ede3.dec.next.block:
load_little_endian(local5, in5, out5, local3, .LLE9)
! parameter 6 1/2 for include encryption/decryption
! parameter 7 1 for mov in1 to in3
! parameter 8 1 for mov in3 to in4
! parameter 9 1 for load ks3 and ks2 to in4 and in3
ip_macro(in5, out5, out5, in5, in4, 2, 0, 0, 1) ! inc .des_dec ks3 in4
call .des_enc ! ks2 in3
LDPTR KS1, in4
call .des_dec ! ks1 in4
nop
fp_macro(out5, in5, 0, 1) ! 1 for input and output address local5/7
! in2 is bytes left to be stored
! in2 is compared to 8 in the rounds
xor out5, in0, out4
bl .ede3.dec.seven.or.less
xor in5, in1, global4
load_little_endian_inc(local5, in0, in1, local3, .LLE10) ! iv next block
store_little_endian(local7, out4, global4, local3, .SLE7) ! block
STPTR local5, INPUT
addcc in2, -8, in2
add local7, 8, local7
bg .ede3.dec.next.block
STPTR local7, OUTPUT
.ede3.dec.store.iv:
LDPTR [%fp+BIAS+ARG0+6*ARGSZ], local4 ! ivec
store_little_endian(local4, in0, in1, local5, .SLE8) ! ivec
.ede3.dec.finish:
ret
restore
.ede3.dec.seven.or.less:
load_little_endian_inc(local5, in0, in1, local3, .LLE14) ! iv
store_n_bytes(local7, in2, global4, out4, local3, local4, .SNB2, .ede3.dec.store.iv)
.DES_ede3_cbc_encrypt.end:
.size DES_ede3_cbc_encrypt,.DES_ede3_cbc_encrypt.end-DES_ede3_cbc_encrypt
.align 256
.type .des_and,#object
.size .des_and,284
.des_and:
! This table is used for AND 0xFC when it is known that register
! bits 8-31 are zero. Makes it possible to do three arithmetic
! operations in one cycle.
.byte 0, 0, 0, 0, 4, 4, 4, 4
.byte 8, 8, 8, 8, 12, 12, 12, 12
.byte 16, 16, 16, 16, 20, 20, 20, 20
.byte 24, 24, 24, 24, 28, 28, 28, 28
.byte 32, 32, 32, 32, 36, 36, 36, 36
.byte 40, 40, 40, 40, 44, 44, 44, 44
.byte 48, 48, 48, 48, 52, 52, 52, 52
.byte 56, 56, 56, 56, 60, 60, 60, 60
.byte 64, 64, 64, 64, 68, 68, 68, 68
.byte 72, 72, 72, 72, 76, 76, 76, 76
.byte 80, 80, 80, 80, 84, 84, 84, 84
.byte 88, 88, 88, 88, 92, 92, 92, 92
.byte 96, 96, 96, 96, 100, 100, 100, 100
.byte 104, 104, 104, 104, 108, 108, 108, 108
.byte 112, 112, 112, 112, 116, 116, 116, 116
.byte 120, 120, 120, 120, 124, 124, 124, 124
.byte 128, 128, 128, 128, 132, 132, 132, 132
.byte 136, 136, 136, 136, 140, 140, 140, 140
.byte 144, 144, 144, 144, 148, 148, 148, 148
.byte 152, 152, 152, 152, 156, 156, 156, 156
.byte 160, 160, 160, 160, 164, 164, 164, 164
.byte 168, 168, 168, 168, 172, 172, 172, 172
.byte 176, 176, 176, 176, 180, 180, 180, 180
.byte 184, 184, 184, 184, 188, 188, 188, 188
.byte 192, 192, 192, 192, 196, 196, 196, 196
.byte 200, 200, 200, 200, 204, 204, 204, 204
.byte 208, 208, 208, 208, 212, 212, 212, 212
.byte 216, 216, 216, 216, 220, 220, 220, 220
.byte 224, 224, 224, 224, 228, 228, 228, 228
.byte 232, 232, 232, 232, 236, 236, 236, 236
.byte 240, 240, 240, 240, 244, 244, 244, 244
.byte 248, 248, 248, 248, 252, 252, 252, 252
! 5 numbers for initil/final permutation
.word 0x0f0f0f0f ! offset 256
.word 0x0000ffff ! 260
.word 0x33333333 ! 264
.word 0x00ff00ff ! 268
.word 0x55555555 ! 272
.word 0 ! 276
.word LOOPS ! 280
.word 0x0000FC00 ! 284
.global DES_SPtrans
.type DES_SPtrans,#object
.size DES_SPtrans,2048
.align 64
DES_SPtrans:
.PIC.DES_SPtrans:
! nibble 0
.word 0x02080800, 0x00080000, 0x02000002, 0x02080802
.word 0x02000000, 0x00080802, 0x00080002, 0x02000002
.word 0x00080802, 0x02080800, 0x02080000, 0x00000802
.word 0x02000802, 0x02000000, 0x00000000, 0x00080002
.word 0x00080000, 0x00000002, 0x02000800, 0x00080800
.word 0x02080802, 0x02080000, 0x00000802, 0x02000800
.word 0x00000002, 0x00000800, 0x00080800, 0x02080002
.word 0x00000800, 0x02000802, 0x02080002, 0x00000000
.word 0x00000000, 0x02080802, 0x02000800, 0x00080002
.word 0x02080800, 0x00080000, 0x00000802, 0x02000800
.word 0x02080002, 0x00000800, 0x00080800, 0x02000002
.word 0x00080802, 0x00000002, 0x02000002, 0x02080000
.word 0x02080802, 0x00080800, 0x02080000, 0x02000802
.word 0x02000000, 0x00000802, 0x00080002, 0x00000000
.word 0x00080000, 0x02000000, 0x02000802, 0x02080800
.word 0x00000002, 0x02080002, 0x00000800, 0x00080802
! nibble 1
.word 0x40108010, 0x00000000, 0x00108000, 0x40100000
.word 0x40000010, 0x00008010, 0x40008000, 0x00108000
.word 0x00008000, 0x40100010, 0x00000010, 0x40008000
.word 0x00100010, 0x40108000, 0x40100000, 0x00000010
.word 0x00100000, 0x40008010, 0x40100010, 0x00008000
.word 0x00108010, 0x40000000, 0x00000000, 0x00100010
.word 0x40008010, 0x00108010, 0x40108000, 0x40000010
.word 0x40000000, 0x00100000, 0x00008010, 0x40108010
.word 0x00100010, 0x40108000, 0x40008000, 0x00108010
.word 0x40108010, 0x00100010, 0x40000010, 0x00000000
.word 0x40000000, 0x00008010, 0x00100000, 0x40100010
.word 0x00008000, 0x40000000, 0x00108010, 0x40008010
.word 0x40108000, 0x00008000, 0x00000000, 0x40000010
.word 0x00000010, 0x40108010, 0x00108000, 0x40100000
.word 0x40100010, 0x00100000, 0x00008010, 0x40008000
.word 0x40008010, 0x00000010, 0x40100000, 0x00108000
! nibble 2
.word 0x04000001, 0x04040100, 0x00000100, 0x04000101
.word 0x00040001, 0x04000000, 0x04000101, 0x00040100
.word 0x04000100, 0x00040000, 0x04040000, 0x00000001
.word 0x04040101, 0x00000101, 0x00000001, 0x04040001
.word 0x00000000, 0x00040001, 0x04040100, 0x00000100
.word 0x00000101, 0x04040101, 0x00040000, 0x04000001
.word 0x04040001, 0x04000100, 0x00040101, 0x04040000
.word 0x00040100, 0x00000000, 0x04000000, 0x00040101
.word 0x04040100, 0x00000100, 0x00000001, 0x00040000
.word 0x00000101, 0x00040001, 0x04040000, 0x04000101
.word 0x00000000, 0x04040100, 0x00040100, 0x04040001
.word 0x00040001, 0x04000000, 0x04040101, 0x00000001
.word 0x00040101, 0x04000001, 0x04000000, 0x04040101
.word 0x00040000, 0x04000100, 0x04000101, 0x00040100
.word 0x04000100, 0x00000000, 0x04040001, 0x00000101
.word 0x04000001, 0x00040101, 0x00000100, 0x04040000
! nibble 3
.word 0x00401008, 0x10001000, 0x00000008, 0x10401008
.word 0x00000000, 0x10400000, 0x10001008, 0x00400008
.word 0x10401000, 0x10000008, 0x10000000, 0x00001008
.word 0x10000008, 0x00401008, 0x00400000, 0x10000000
.word 0x10400008, 0x00401000, 0x00001000, 0x00000008
.word 0x00401000, 0x10001008, 0x10400000, 0x00001000
.word 0x00001008, 0x00000000, 0x00400008, 0x10401000
.word 0x10001000, 0x10400008, 0x10401008, 0x00400000
.word 0x10400008, 0x00001008, 0x00400000, 0x10000008
.word 0x00401000, 0x10001000, 0x00000008, 0x10400000
.word 0x10001008, 0x00000000, 0x00001000, 0x00400008
.word 0x00000000, 0x10400008, 0x10401000, 0x00001000
.word 0x10000000, 0x10401008, 0x00401008, 0x00400000
.word 0x10401008, 0x00000008, 0x10001000, 0x00401008
.word 0x00400008, 0x00401000, 0x10400000, 0x10001008
.word 0x00001008, 0x10000000, 0x10000008, 0x10401000
! nibble 4
.word 0x08000000, 0x00010000, 0x00000400, 0x08010420
.word 0x08010020, 0x08000400, 0x00010420, 0x08010000
.word 0x00010000, 0x00000020, 0x08000020, 0x00010400
.word 0x08000420, 0x08010020, 0x08010400, 0x00000000
.word 0x00010400, 0x08000000, 0x00010020, 0x00000420
.word 0x08000400, 0x00010420, 0x00000000, 0x08000020
.word 0x00000020, 0x08000420, 0x08010420, 0x00010020
.word 0x08010000, 0x00000400, 0x00000420, 0x08010400
.word 0x08010400, 0x08000420, 0x00010020, 0x08010000
.word 0x00010000, 0x00000020, 0x08000020, 0x08000400
.word 0x08000000, 0x00010400, 0x08010420, 0x00000000
.word 0x00010420, 0x08000000, 0x00000400, 0x00010020
.word 0x08000420, 0x00000400, 0x00000000, 0x08010420
.word 0x08010020, 0x08010400, 0x00000420, 0x00010000
.word 0x00010400, 0x08010020, 0x08000400, 0x00000420
.word 0x00000020, 0x00010420, 0x08010000, 0x08000020
! nibble 5
.word 0x80000040, 0x00200040, 0x00000000, 0x80202000
.word 0x00200040, 0x00002000, 0x80002040, 0x00200000
.word 0x00002040, 0x80202040, 0x00202000, 0x80000000
.word 0x80002000, 0x80000040, 0x80200000, 0x00202040
.word 0x00200000, 0x80002040, 0x80200040, 0x00000000
.word 0x00002000, 0x00000040, 0x80202000, 0x80200040
.word 0x80202040, 0x80200000, 0x80000000, 0x00002040
.word 0x00000040, 0x00202000, 0x00202040, 0x80002000
.word 0x00002040, 0x80000000, 0x80002000, 0x00202040
.word 0x80202000, 0x00200040, 0x00000000, 0x80002000
.word 0x80000000, 0x00002000, 0x80200040, 0x00200000
.word 0x00200040, 0x80202040, 0x00202000, 0x00000040
.word 0x80202040, 0x00202000, 0x00200000, 0x80002040
.word 0x80000040, 0x80200000, 0x00202040, 0x00000000
.word 0x00002000, 0x80000040, 0x80002040, 0x80202000
.word 0x80200000, 0x00002040, 0x00000040, 0x80200040
! nibble 6
.word 0x00004000, 0x00000200, 0x01000200, 0x01000004
.word 0x01004204, 0x00004004, 0x00004200, 0x00000000
.word 0x01000000, 0x01000204, 0x00000204, 0x01004000
.word 0x00000004, 0x01004200, 0x01004000, 0x00000204
.word 0x01000204, 0x00004000, 0x00004004, 0x01004204
.word 0x00000000, 0x01000200, 0x01000004, 0x00004200
.word 0x01004004, 0x00004204, 0x01004200, 0x00000004
.word 0x00004204, 0x01004004, 0x00000200, 0x01000000
.word 0x00004204, 0x01004000, 0x01004004, 0x00000204
.word 0x00004000, 0x00000200, 0x01000000, 0x01004004
.word 0x01000204, 0x00004204, 0x00004200, 0x00000000
.word 0x00000200, 0x01000004, 0x00000004, 0x01000200
.word 0x00000000, 0x01000204, 0x01000200, 0x00004200
.word 0x00000204, 0x00004000, 0x01004204, 0x01000000
.word 0x01004200, 0x00000004, 0x00004004, 0x01004204
.word 0x01000004, 0x01004200, 0x01004000, 0x00004004
! nibble 7
.word 0x20800080, 0x20820000, 0x00020080, 0x00000000
.word 0x20020000, 0x00800080, 0x20800000, 0x20820080
.word 0x00000080, 0x20000000, 0x00820000, 0x00020080
.word 0x00820080, 0x20020080, 0x20000080, 0x20800000
.word 0x00020000, 0x00820080, 0x00800080, 0x20020000
.word 0x20820080, 0x20000080, 0x00000000, 0x00820000
.word 0x20000000, 0x00800000, 0x20020080, 0x20800080
.word 0x00800000, 0x00020000, 0x20820000, 0x00000080
.word 0x00800000, 0x00020000, 0x20000080, 0x20820080
.word 0x00020080, 0x20000000, 0x00000000, 0x00820000
.word 0x20800080, 0x20020080, 0x20020000, 0x00800080
.word 0x20820000, 0x00000080, 0x00800080, 0x20020000
.word 0x20820080, 0x00800000, 0x20800000, 0x20000080
.word 0x00820000, 0x00020080, 0x20020080, 0x20800000
.word 0x00000080, 0x20820000, 0x00820080, 0x00000000
.word 0x20000000, 0x20800080, 0x00020000, 0x00820080
| {
"language": "Assembly"
} |
#
# example from
#
# Jon Baker, Fora Chan,
# "The location of transition states:
# A comparison of Cartesian, Z-Matrix, and Natural Internal Coordinates",
# J.Comp.Chem. 17 (1996) 888-904.
#
# Example 8.
#
start ts_example_8
memory total 80 mb
geometry autosym units angstrom noautoz print
zmatrix
C1
C2 1 L1
O3 2 L2 1 A1
C4 3 L3 2 A2 1 D1
O5 1 L4 2 A3 3 D2
H6 1 L5 2 A4 3 D3
H7 1 L6 2 A5 3 D4
H8 2 L7 3 A6 4 D5
H9 2 L8 3 A7 4 D6
H10 4 L9 3 A8 2 D7
variables
L1 1.487
L2 1.458
L3 1.365
L4 1.812
L5 1.095
L6 1.096
L7 1.119
L8 1.120
L9 1.094
A1 108.2
A2 111.4
A3 94.8
A4 118.7
A5 118.1
A6 106.2
A7 104.3
A8 116.3
D1 8.6
D2 -20.2
D3 -123.0
D4 86.0
D5 -112.9
D6 130.0
D7 -155.7
end
end
basis
c library 3-21g
o library 3-21g
h library 3-21g
end
scf
#print low
doublet
uhf
nr 0.0
maxiter 50
end
driver
maxiter 400
end
task scf freq
task scf saddle
task scf freq
| {
"language": "Assembly"
} |
.sect .text; .sect .rom; .sect .data; .sect .bss
.define __read
.sect .text
__read:
mov ax,3
jmp syscal
| {
"language": "Assembly"
} |
.global v1
.global v2
.size v2, 4100
.global v3
.section .tdata,"awT",%progbits
v1:
.word 0xdeaddead
v2:
.zero 4100
v3:
.word 0xcafecafe
.text
ldrsb x29, [x4, #:tprel_lo12_nc:v2]
# should not issue overflow error.
ldrsb x18, [x7, #:tprel_lo12_nc:v3]
| {
"language": "Assembly"
} |
#
#
# Nim's Runtime Library
# (c) Copyright 2015 Rokas Kupstys
#
# See the file "copying.txt", included in this
# distribution, for details about the copyright.
#
# Partially based on code from musl libc Copyright © 2005-2014 Rich Felker, et al.
.globl narch_coroExecWithStack
.globl narch_setjmp
.globl narch_longjmp
.text
# SysV ABI - first argument is rdi.
# MS ABI - first argument is rcx.
#if defined(__MINGW32__) || defined(__MINGW64__)
#define REG_ARG1 rcx
#define REG_ARG2 rdx
#else
#define REG_ARG1 rdi
#define REG_ARG2 rsi
#endif
narch_coroExecWithStack:
mov %REG_ARG2, %rsp # swap stack with one passed to func
sub $0x30, %rsp # shadow space (for ms ABI) 0x20 + 0x10 for possible misalignment
and $-0x10, %rsp # 16-byte stack alignment
call *%REG_ARG1
narch_setjmp:
add $0x10, %REG_ARG1 # 16-byte alignment
and $-0x10, %REG_ARG1
mov %rbx, 0x00(%REG_ARG1) # jmp_buf, move registers onto it
mov %rbp, 0x08(%REG_ARG1)
mov %r12, 0x10(%REG_ARG1)
mov %r13, 0x18(%REG_ARG1)
mov %r14, 0x20(%REG_ARG1)
mov %r15, 0x28(%REG_ARG1)
lea 0x08(%rsp), %rdx # this is our rsp WITHOUT current ret addr
mov %rdx, 0x30(%REG_ARG1)
mov (%rsp), %rdx # save return addr ptr for new rip
mov %rdx, 0x38(%REG_ARG1)
mov %rsi, 0x40(%REG_ARG1)
mov %rdi, 0x48(%REG_ARG1)
#if defined(__MINGW32__) || defined(__MINGW64__)
movaps %xmm6, 0x50(%REG_ARG1)
movaps %xmm7, 0x60(%REG_ARG1)
movaps %xmm8, 0x70(%REG_ARG1)
movaps %xmm9, 0x80(%REG_ARG1)
movaps %xmm10, 0x90(%REG_ARG1)
movaps %xmm11, 0xA0(%REG_ARG1)
movaps %xmm12, 0xB0(%REG_ARG1)
movaps %xmm13, 0xC0(%REG_ARG1)
movaps %xmm14, 0xD0(%REG_ARG1)
movaps %xmm15, 0xE0(%REG_ARG1)
#endif
xor %rax, %rax # always return 0
ret
narch_longjmp:
add $0x10, %REG_ARG1 # 16-byte alignment
and $-0x10, %REG_ARG1 #
mov %REG_ARG2, %rax # val will be longjmp return
test %rax, %rax
jnz narch_longjmp_1
inc %rax # if val==0, val=1 per longjmp semantics
narch_longjmp_1:
mov 0x00(%REG_ARG1), %rbx # jmp_buf, restore regs from it
mov 0x08(%REG_ARG1), %rbp
mov 0x10(%REG_ARG1), %r12
mov 0x18(%REG_ARG1), %r13
mov 0x20(%REG_ARG1), %r14
mov 0x28(%REG_ARG1), %r15
mov 0x30(%REG_ARG1), %rsp # this ends up being the stack pointer
mov 0x38(%REG_ARG1), %rdx # this is the instruction pointer
mov 0x40(%REG_ARG1), %rsi
mov 0x48(%REG_ARG1), %rdi
#if defined(__MINGW32__) || defined(__MINGW64__)
movaps 0x50(%REG_ARG1), %xmm6
movaps 0x60(%REG_ARG1), %xmm7
movaps 0x70(%REG_ARG1), %xmm8
movaps 0x80(%REG_ARG1), %xmm9
movaps 0x90(%REG_ARG1), %xmm10
movaps 0xA0(%REG_ARG1), %xmm11
movaps 0xB0(%REG_ARG1), %xmm12
movaps 0xC0(%REG_ARG1), %xmm13
movaps 0xD0(%REG_ARG1), %xmm14
movaps 0xE0(%REG_ARG1), %xmm15
#endif
jmp *%rdx # goto saved address without altering rsp
| {
"language": "Assembly"
} |
# Lightbeam
Lightbeam is an optimising one-pass streaming compiler for WebAssembly, intended for use in [Wasmtime][wasmtime].
[wasmtime]: https://github.com/bytecodealliance/wasmtime
## Quality of output
Already - with a very small number of relatively simple optimisation rules - Lightbeam produces surprisingly high-quality output considering how restricted it is. It even produces better code than Cranelift, Firefox or both for some workloads. Here's a very simple example, this recursive fibonacci function in Rust:
```rust
fn fib(n: i32) -> i32 {
if n == 0 || n == 1 {
1
} else {
fib(n - 1) + fib(n - 2)
}
}
```
When compiled with optimisations enabled, rustc will produce the following WebAssembly:
```rust
(module
(func $fib (param $p0 i32) (result i32)
(local $l1 i32)
(set_local $l1
(i32.const 1))
(block $B0
(br_if $B0
(i32.lt_u
(get_local $p0)
(i32.const 2)))
(set_local $l1
(i32.const 1))
(loop $L1
(set_local $l1
(i32.add
(call $fib
(i32.add
(get_local $p0)
(i32.const -1)))
(get_local $l1)))
(br_if $L1
(i32.gt_u
(tee_local $p0
(i32.add
(get_local $p0)
(i32.const -2)))
(i32.const 1)))))
(get_local $l1)))
```
Firefox's optimising compiler produces the following assembly (labels cleaned up somewhat):
```asm
fib:
sub rsp, 0x18
cmp qword ptr [r14 + 0x28], rsp
jae stack_overflow
mov dword ptr [rsp + 0xc], edi
cmp edi, 2
jae .Lelse
mov eax, 1
mov dword ptr [rsp + 8], eax
jmp .Lreturn
.Lelse:
mov dword ptr [rsp + 0xc], edi
mov eax, 1
mov dword ptr [rsp + 8], eax
.Lloop:
mov edi, dword ptr [rsp + 0xc]
add edi, -1
call 0
mov ecx, dword ptr [rsp + 8]
add ecx, eax
mov dword ptr [rsp + 8], ecx
mov ecx, dword ptr [rsp + 0xc]
add ecx, -2
mov dword ptr [rsp + 0xc], ecx
cmp ecx, 1
ja .Lloop
.Lreturn:
mov eax, dword ptr [rsp + 8]
nop
add rsp, 0x18
ret
```
Cranelift with optimisations enabled produces similar:
```asm
fib:
push rbp
mov rbp, rsp
sub rsp, 0x20
mov qword ptr [rsp + 0x10], rdi
mov dword ptr [rsp + 0x1c], esi
mov eax, 1
mov dword ptr [rsp + 0x18], eax
mov eax, dword ptr [rsp + 0x1c]
cmp eax, 2
jb .Lreturn
movabs rax, 0
mov qword ptr [rsp + 8], rax
.Lloop:
mov eax, dword ptr [rsp + 0x1c]
add eax, -1
mov rcx, qword ptr [rsp + 8]
mov rdx, qword ptr [rsp + 0x10]
mov rdi, rdx
mov esi, eax
call rcx
mov ecx, dword ptr [rsp + 0x18]
add eax, ecx
mov dword ptr [rsp + 0x18], eax
mov eax, dword ptr [rsp + 0x1c]
add eax, -2
mov dword ptr [rsp + 0x1c], eax
mov eax, dword ptr [rsp + 0x1c]
cmp eax, 1
ja .Lloop
.Lreturn:
mov eax, dword ptr [rsp + 0x18]
add rsp, 0x20
pop rbp
ret
```
Whereas Lightbeam produces smaller code with far fewer memory accesses than both (and fewer blocks than Firefox's output):
```asm
fib:
cmp esi, 2
mov eax, 1
jb .Lreturn
mov eax, 1
.Lloop:
mov rcx, rsi
add ecx, 0xffffffff
push rsi
push rax
push rax
mov rsi, rcx
call fib
add eax, [rsp + 8]
mov rcx, [rsp + 0x10]
add ecx, 0xfffffffe
cmp ecx, 1
mov rsi, rcx
lea rsp, [rsp + 0x18]
ja .Lloop
.Lreturn:
ret
```
Now obviously I'm not advocating for replacing Firefox's optimising compiler with Lightbeam since the latter can only really produce better code when receiving optimised WebAssembly (and so debug-mode or hand-written WebAssembly may produce much worse output). However, this shows that even with the restrictions of a streaming compiler it's absolutely possible to produce high-quality assembly output. For the assembly above, the Lightbeam output runs within 15% of native speed. This is paramount for one of Lightbeam's intended usecases for real-time systems that want good runtime performance but cannot tolerate compiler bombs.
## Specification compliance
Lightbeam passes 100% of the specification test suite, but that doesn't necessarily mean that it's 100% specification-compliant. Hopefully as we run a fuzzer against it we can find any issues and get Lightbeam to a state where it can be used in production.
## Getting involved
You can file issues in the [Wasmtime issue tracker][Wasmtime issue tracker]. If you want to get involved jump into the [Bytecode Alliance Zulip][bytecodealliance-zulip] and someone can direct you to the right place. I wish I could say "the most useful thing you can do is play with it and open issues where you find problems" but until it passes the spec suite that won't be very helpful.
[bytecodealliance-zulip]: https://bytecodealliance.zulipchat.com/
[Wasmtime issue tracker]: https://github.com/bytecodealliance/wasmtime/issues
| {
"language": "Assembly"
} |
;
; grenade_EXPLODE.m
;
; Action code for the asynchronous grenade explosion.
;
; This file should be assembled as position independent code.
;
; Chip Morningstar
; Lucasfilm Ltd.
; 3-May-1986
;
include "action_head.i"
actionStart
/* Create an explosion on the screen */
complexSound 0,actor_noid ; BOOM!
lda actor_noid
chainTo v_delete_object ; Nuke the grenade itself
actionEnd
| {
"language": "Assembly"
} |
dnl X86_64 mpn_rsh_divrem_hensel_qr_1_2
dnl Copyright 2009 Jason Moxham
dnl This file is part of the MPIR Library.
dnl The MPIR Library is free software; you can redistribute it and/or modify
dnl it under the terms of the GNU Lesser General Public License as published
dnl by the Free Software Foundation; either version 2.1 of the License, or (at
dnl your option) any later version.
dnl The MPIR Library is distributed in the hope that it will be useful, but
dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
dnl License for more details.
dnl You should have received a copy of the GNU Lesser General Public License
dnl along with the MPIR Library; see the file COPYING.LIB. If not, write
dnl to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
dnl Boston, MA 02110-1301, USA.
include(`../config.m4')
C (rdi,rdx)=( (rsi,rdx)-r9 / rcx ) >> r8 rdx>=1
C rax=hensel remainder from div
C This is divrem_hensel_1_2 with shifting on the output of the quotient
define(`MOVQ',`movd')
ASM_START()
PROLOGUE(mpn_rsh_divrem_hensel_qr_1_2)
C // 3limb minimum for the mo
mov %r9,%r10
mov $2,%r9
sub %rdx,%r9
lea -16(%rdi,%rdx,8),%rdi
lea -16(%rsi,%rdx,8),%rsi
push %r12
push %r13
push %r14
mov %rcx,%rdx
C // rdx is 3 bit inverse
mov $64,%rax
sub %r8,%rax
MOVQ %r8,%mm0
MOVQ %rax,%mm1
mov %rdx,%rax
imul %ecx,%edx
mov $2,%r11
sub %rdx,%r11
imul %eax,%r11d
C //r11 has 4 bits
mov %r11,%rax
imul %ecx,%r11d
mov $2,%rdx
sub %r11,%rdx
imul %eax,%edx
C //rdx has 8 bits
mov %rdx,%rax
imul %ecx,%edx
mov $2,%r11
sub %rdx,%r11
imul %eax,%r11d
C //r11 has 16 bits
mov %r11,%rax
imul %ecx,%r11d
mov $2,%rdx
sub %r11,%rdx
imul %eax,%edx
C // rdx has 32 bits
mov %rdx,%rax
imul %rcx,%rdx
mov $2,%r11
sub %rdx,%r11
imul %rax,%r11
C //r11 has 64 bits
mov %r11,%rax
mov %r11,%r12
mul %rcx
neg %rdx
imul %rdx,%r12
C // r12,r11 has 128 bits
C // for the first limb we can not store (as we have to shift) so we need to
C // do first limb separately , we could do it as normal as an extention of
C // the loop , but if we do it as a 1 limb inverse then we can start it
C // eailer , ie interleave it with the calculation of the 2limb inverse
mov %r11,%r13
mov %r12,%r14
mov (%rsi,%r9,8),%r11
sub %r10,%r11
sbb %r10,%r10
imul %r13,%r11
MOVQ %r11,%mm2
psrlq %mm0,%mm2
mov %rcx,%rax
mul %r11
mov 8(%rsi,%r9,8),%r11
mov 16(%rsi,%r9,8),%r12
add %r10,%r10
sbb %rdx,%r11
sbb $0,%r12
sbb %r10,%r10
add $2,%r9
jc L(skiplp)
ALIGN(16)
L(lp):
mov %r12,%r8
mov %r13,%rax
mul %r11
MOVQ %rax,%mm3
movq %mm3,%mm4
psllq %mm1,%mm3
psrlq %mm0,%mm4
por %mm3,%mm2
movq %mm2,-16(%rdi,%r9,8)
imul %r14,%r11
imul %r13,%r12
add %r11,%rdx
add %r12,%rdx
mov 8(%rsi,%r9,8),%r11
mov 16(%rsi,%r9,8),%r12
MOVQ %rdx,%mm3
movq %mm3,%mm2
psllq %mm1,%mm3
psrlq %mm0,%mm2
por %mm3,%mm4
movq %mm4,-8(%rdi,%r9,8)
mov %rcx,%rax
mul %rdx
add %r10,%r10
sbb $0,%r11
sbb $0,%r12
sbb %r10,%r10
cmp %rax,%r8
sbb %rdx,%r11
sbb $0,%r12
sbb $0,%r10
add $2,%r9
jnc L(lp)
L(skiplp):
mov %r12,%r8
mov %r13,%rax
mul %r11
MOVQ %rax,%mm3
movq %mm3,%mm4
psllq %mm1,%mm3
psrlq %mm0,%mm4
por %mm3,%mm2
movq %mm2,-16(%rdi,%r9,8)
imul %r14,%r11
imul %r13,%r12
add %r11,%rdx
add %r12,%rdx
cmp $0,%r9
jne L(case0)
L(case1):
mov 8(%rsi,%r9,8),%r11
MOVQ %rdx,%mm3
movq %mm3,%mm2
psllq %mm1,%mm3
psrlq %mm0,%mm2
por %mm3,%mm4
movq %mm4,-8(%rdi,%r9,8)
mov %rcx,%rax
mul %rdx
add %r10,%r10
sbb $0,%r11
sbb %r10,%r10
cmp %rax,%r8
sbb %rdx,%r11
sbb $0,%r10
mov %r11,%rax
imul %r13,%rax
MOVQ %rax,%mm3
movq %mm3,%mm4
psllq %mm1,%mm3
psrlq %mm0,%mm4
por %mm3,%mm2
movq %mm2,(%rdi,%r9,8)
movq %mm4,8(%rdi,%r9,8)
mul %rcx
add %r10,%r10
mov $0,%rax
adc %rdx,%rax
pop %r14
pop %r13
pop %r12
emms
ret
L(case0):
MOVQ %rdx,%mm3
movq %mm3,%mm2
psllq %mm1,%mm3
psrlq %mm0,%mm2
por %mm3,%mm4
movq %mm4,-8(%rdi,%r9,8)
movq %mm2,(%rdi,%r9,8)
mov %rcx,%rax
mul %rdx
cmp %rax,%r8
mov $0,%rax
adc %rdx,%rax
sub %r10,%rax
pop %r14
pop %r13
pop %r12
emms
ret
EPILOGUE()
| {
"language": "Assembly"
} |
/**************************************************************************
*
* Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
#ifndef OP12_TEX
#define OP12_TEX(a) OP12(a)
#endif
#ifndef OP14_TEX
#define OP14_TEX(a) OP14(a)
#endif
#ifndef OP00_LBL
#define OP00_LBL(a) OP00(a)
#endif
#ifndef OP01_LBL
#define OP01_LBL(a) OP01(a)
#endif
OP11(ARL)
OP11(MOV)
OP11(LIT)
OP11(RCP)
OP11(RSQ)
OP11(EXP)
OP11(LOG)
OP12(MUL)
OP12(ADD)
OP12(DP3)
OP12(DP4)
OP12(DST)
OP12(MIN)
OP12(MAX)
OP12(SLT)
OP12(SGE)
OP13(MAD)
OP12(SUB)
OP13(LRP)
OP13(CND)
OP13(DP2A)
OP11(FRC)
OP13(CLAMP)
OP11(FLR)
OP11(ROUND)
OP11(EX2)
OP11(LG2)
OP12(POW)
OP12(XPD)
OP11(ABS)
OP11(RCC)
OP12(DPH)
OP11(COS)
OP11(DDX)
OP11(DDY)
OP00(KILP)
OP11(PK2H)
OP11(PK2US)
OP11(PK4B)
OP11(PK4UB)
OP12(RFL)
OP12(SEQ)
OP12(SFL)
OP12(SGT)
OP11(SIN)
OP12(SLE)
OP12(SNE)
OP12(STR)
OP12_TEX(TEX)
OP14_TEX(TXD)
OP12_TEX(TXP)
OP11(UP2H)
OP11(UP2US)
OP11(UP4B)
OP11(UP4UB)
OP13(X2D)
OP11(ARA)
OP11(ARR)
OP01(BRA)
OP00_LBL(CAL)
OP00(RET)
OP11(SSG)
OP13(CMP)
OP11(SCS)
OP12_TEX(TXB)
OP11(NRM)
OP12(DIV)
OP12(DP2)
OP12_TEX(TXL)
OP00(BRK)
OP01_LBL(IF)
OP00_LBL(ELSE)
OP00(ENDIF)
OP01(PUSHA)
OP10(POPA)
OP11(CEIL)
OP11(I2F)
OP11(NOT)
OP11(TRUNC)
OP12(SHL)
OP12(AND)
OP12(OR)
OP12(MOD)
OP12(XOR)
OP13(SAD)
OP12_TEX(TXF)
OP12_TEX(TXQ)
OP00(CONT)
OP00(EMIT)
OP00(ENDPRIM)
OP00_LBL(BGNLOOP)
OP00(BGNSUB)
OP00_LBL(ENDLOOP)
OP00(ENDSUB)
OP00(NOP)
OP11(NRM4)
OP01(CALLNZ)
OP01(IFC)
OP01(BREAKC)
OP01(KIL)
OP00(END)
OP11(F2I)
OP12(IDIV)
OP12(IMAX)
OP12(IMIN)
OP11(INEG)
OP12(ISGE)
OP12(ISHR)
OP12(ISLT)
OP11(F2U)
OP11(U2F)
OP12(UADD)
OP12(UDIV)
OP13(UMAD)
OP12(UMAX)
OP12(UMIN)
OP12(UMOD)
OP12(UMUL)
OP12(USEQ)
OP12(USGE)
OP12(USHR)
OP12(USLT)
OP12(USNE)
OP01(SWITCH)
OP01(CASE)
OP00(DEFAULT)
OP00(ENDSWITCH)
OP13(SAMPLE)
OP12(SAMPLE_I)
OP12(SAMPLE_I_MS)
OP14(SAMPLE_B)
OP14(SAMPLE_C)
OP14(SAMPLE_C_LZ)
OP15(SAMPLE_D)
OP13(SAMPLE_L)
OP13(GATHER4)
OP12(SVIEWINFO)
OP13(SAMPLE_POS)
OP12(SAMPLE_INFO)
#undef OP00
#undef OP01
#undef OP10
#undef OP11
#undef OP12
#undef OP13
#ifdef OP14
#undef OP14
#endif
#ifdef OP15
#undef OP15
#endif
#undef OP00_LBL
#undef OP01_LBL
#undef OP12_TEX
#undef OP14_TEX
| {
"language": "Assembly"
} |
KnowsMove:
ld a, MON_MOVES
call GetPartyParamLocation
ld a, [wPutativeTMHMMove]
ld b, a
ld c, NUM_MOVES
.loop
ld a, [hli]
cp b
jr z, .knows_move
dec c
jr nz, .loop
and a
ret
.knows_move
ld hl, .KnowsMoveText
call PrintText
scf
ret
.KnowsMoveText:
text_far _KnowsMoveText
text_end
| {
"language": "Assembly"
} |
/* Copyright (C) 1997, 1998, 2002, 2004 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Miguel de Icaza <miguel@gnu.ai.mit.edu>, 1997.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
#include <sysdep-cancel.h>
#include <socketcall.h>
#define P(a, b) P2(a, b)
#define P2(a, b) a##b
#ifndef NARGS
#ifdef socket
#error NARGS not defined
#endif
#define NARGS 3
#endif
.text
/* The socket-oriented system calls are handled unusually in Linux.
They are all gated through the single `socketcall' system call number.
`socketcall' takes two arguments: the first is the subcode, specifying
which socket function is being called; and the second is a pointer to
the arguments to the specific function.
The .S files for the other calls just #define socket and #include this. */
#ifndef __socket
# ifndef NO_WEAK_ALIAS
# define __socket P(__,socket)
# else
# define __socket socket
# endif
#endif
.globl __syscall_error
ENTRY(__socket)
/* Drop up to 6 arguments (recvfrom) into the memory allocated by
the caller for varargs, since that's really what we have. */
stx %o0, [%sp + STACK_BIAS + 128 + 0]
stx %o1, [%sp + STACK_BIAS + 128 + 8]
#if NARGS > 2
stx %o2, [%sp + STACK_BIAS + 128 + 16]
#if NARGS > 3
stx %o3, [%sp + STACK_BIAS + 128 + 24]
#if NARGS > 4
stx %o4, [%sp + STACK_BIAS + 128 + 32]
#if NARGS > 5
stx %o5, [%sp + STACK_BIAS + 128 + 40]
#endif
#endif
#endif
#endif
#if defined NEED_CANCELLATION && defined CENABLE
SINGLE_THREAD_P
cmp %g1, 0
bne .Lsocket_cancel
#endif
mov P(SOCKOP_,socket), %o0 /* arg 1: socket subfunction */
add %sp, STACK_BIAS + 128, %o1 /* arg 2: parameter block */
LOADSYSCALL(socketcall)
ta 0x6d
bcc,pt %xcc, 1f
mov %o7, %g1
call __syscall_error
mov %g1, %o7
1: retl
nop
#if defined NEED_CANCELLATION && defined CENABLE
.Lsocket_cancel:
save %sp, -160, %sp
cfi_def_cfa_register (%fp)
cfi_window_save
cfi_register (%o7, %i7)
CENABLE
nop
mov %o0, %l0
add %sp, 160 + STACK_BIAS + 128, %o1
mov P(SOCKOP_,socket), %o0
LOADSYSCALL(socketcall)
ta 0x6d
bcc,pt %xcc, 1f
mov %o0, %l1
CDISABLE;
mov %l0, %o0;
call __syscall_error;
mov %l1, %o0;
ba,pt %xcc, 2f
mov -1, %l1;
1: CDISABLE
mov %l0, %o0
2: jmpl %i7 + 8, %g0
restore %g0, %l1, %o0
#endif
END(__socket)
#ifndef NO_WEAK_ALIAS
weak_alias (__socket, socket)
#endif
| {
"language": "Assembly"
} |
// Copyright 2014 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build linux
// +build ppc64 ppc64le
// +build !gccgo
#include "textflag.h"
//
// System calls for ppc64, Linux
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
BR syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
BR syscall·Syscall6(SB)
TEXT ·SyscallNoError(SB),NOSPLIT,$0-48
BL runtime·entersyscall(SB)
MOVD a1+8(FP), R3
MOVD a2+16(FP), R4
MOVD a3+24(FP), R5
MOVD R0, R6
MOVD R0, R7
MOVD R0, R8
MOVD trap+0(FP), R9 // syscall entry
SYSCALL R9
MOVD R3, r1+32(FP)
MOVD R4, r2+40(FP)
BL runtime·exitsyscall(SB)
RET
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
BR syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
BR syscall·RawSyscall6(SB)
TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-48
MOVD a1+8(FP), R3
MOVD a2+16(FP), R4
MOVD a3+24(FP), R5
MOVD R0, R6
MOVD R0, R7
MOVD R0, R8
MOVD trap+0(FP), R9 // syscall entry
SYSCALL R9
MOVD R3, r1+32(FP)
MOVD R4, r2+40(FP)
RET
| {
"language": "Assembly"
} |
/*********************************************************************/
/* Copyright 2009, 2010 The University of Texas at Austin. */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or */
/* without modification, are permitted provided that the following */
/* conditions are met: */
/* */
/* 1. Redistributions of source code must retain the above */
/* copyright notice, this list of conditions and the following */
/* disclaimer. */
/* */
/* 2. Redistributions in binary form must reproduce the above */
/* copyright notice, this list of conditions and the following */
/* disclaimer in the documentation and/or other materials */
/* provided with the distribution. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
/* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
/* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
/* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
/* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
/* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
/* POSSIBILITY OF SUCH DAMAGE. */
/* */
/* The views and conclusions contained in the software and */
/* documentation are those of the authors and should not be */
/* interpreted as representing official policies, either expressed */
/* or implied, of The University of Texas at Austin. */
/*********************************************************************/
#define ASSEMBLER
#include "common.h"
#if defined(linux) || defined(__FreeBSD__)
#ifndef __64BIT__
#define M r3
#define N r4
#define A r6
#define LDA r7
#define X r8
#define INCX r9
#define Y r10
#define INCY r5
#else
#define M r3
#define N r4
#define A r8
#define LDA r9
#define X r10
#define INCX r5
#define Y r6
#define INCY r7
#endif
#endif
#if defined(_AIX) || defined(__APPLE__)
#if !defined(__64BIT__) && defined(DOUBLE)
#define M r3
#define N r4
#define A r10
#define LDA r5
#define X r6
#define INCX r7
#define Y r8
#define INCY r9
#else
#define M r3
#define N r4
#define A r8
#define LDA r9
#define X r10
#define INCX r5
#define Y r6
#define INCY r7
#endif
#endif
#define I r11
#define J r12
#define AO1 r14
#define AO2 r15
#define AO3 r16
#define AO4 r17
#define Y1 r18
#define Y2 r19
#define PREA r20
#define YY r21
#define BUFFER r22
#define y01 f0
#define y02 f1
#define y03 f2
#define y04 f3
#define y05 f4
#define y06 f5
#define y07 f6
#define y08 f7
#define y09 f8
#define y10 f9
#define y11 f10
#define y12 f11
#define y13 f12
#define y14 f13
#define y15 f14
#define y16 f15
#define alpha1r f16
#define alpha1i f17
#define alpha2r f18
#define alpha2i f19
#define alpha3r f20
#define alpha3i f21
#define alpha4r f22
#define alpha4i f23
#define a1 f24
#define a2 f25
#define a3 f26
#define a4 f27
#define a5 f28
#define a6 f29
#define a7 f30
#define a8 f31
#define alpha_r f14
#define alpha_i f15
#if defined(PPCG4)
#define PREFETCHSIZE_A (3 * 4)
#endif
#if defined(POWER6)
#define PREFETCHSIZE_A (3 * 4)
#endif
#ifndef XCONJ
#define FMADDR FMADD
#define FMSUBR FNMSUB
#else
#define FMADDR FNMSUB
#define FMSUBR FMADD
#endif
#ifndef CONJ
#define FMADDX FMADD
#define FMSUBX FNMSUB
#else
#define FMADDX FNMSUB
#define FMSUBX FMADD
#endif
#ifndef NEEDPARAM
#ifndef __64BIT__
#define STACKSIZE 232
#define ALPHA_R 208(SP)
#define ALPHA_I 216(SP)
#define FZERO 224(SP)
#else
#define STACKSIZE 280
#define ALPHA_R 256(SP)
#define ALPHA_I 264(SP)
#define FZERO 272(SP)
#endif
PROLOGUE
PROFCODE
addi SP, SP, -STACKSIZE
li r0, 0
stfd f14, 0(SP)
stfd f15, 8(SP)
stfd f16, 16(SP)
stfd f17, 24(SP)
stfd f18, 32(SP)
stfd f19, 40(SP)
stfd f20, 48(SP)
stfd f21, 56(SP)
stfd f22, 64(SP)
stfd f23, 72(SP)
stfd f24, 80(SP)
stfd f25, 88(SP)
stfd f26, 96(SP)
stfd f27, 104(SP)
stfd f28, 112(SP)
stfd f29, 120(SP)
stfd f30, 128(SP)
stfd f31, 136(SP)
#ifdef __64BIT__
std r0, FZERO
std r14, 144(SP)
std r15, 152(SP)
std r16, 160(SP)
std r17, 168(SP)
std r18, 176(SP)
std r19, 184(SP)
std r20, 192(SP)
std r21, 200(SP)
std r22, 208(SP)
#else
stw r0, 0 + FZERO
stw r0, 4 + FZERO
stw r14, 144(SP)
stw r15, 148(SP)
stw r16, 152(SP)
stw r17, 156(SP)
stw r18, 160(SP)
stw r19, 164(SP)
stw r20, 168(SP)
stw r21, 172(SP)
stw r22, 176(SP)
#endif
#if defined(linux) || defined(__FreeBSD__)
#ifndef __64BIT__
lwz INCY, FRAMESLOT(0) + STACKSIZE(SP)
lwz BUFFER, FRAMESLOT(1) + STACKSIZE(SP)
#else
ld INCX, FRAMESLOT(0) + STACKSIZE(SP)
ld Y, FRAMESLOT(1) + STACKSIZE(SP)
ld INCY, FRAMESLOT(2) + STACKSIZE(SP)
ld BUFFER, FRAMESLOT(3) + STACKSIZE(SP)
#endif
#endif
#if defined(_AIX) || defined(__APPLE__)
#ifndef __64BIT__
#ifdef DOUBLE
lwz LDA, FRAMESLOT(0) + STACKSIZE(SP)
lwz X, FRAMESLOT(1) + STACKSIZE(SP)
lwz INCX, FRAMESLOT(2) + STACKSIZE(SP)
lwz Y, FRAMESLOT(3) + STACKSIZE(SP)
lwz INCY, FRAMESLOT(4) + STACKSIZE(SP)
lwz BUFFER, FRAMESLOT(5) + STACKSIZE(SP)
#else
lwz INCX, FRAMESLOT(0) + STACKSIZE(SP)
lwz Y, FRAMESLOT(1) + STACKSIZE(SP)
lwz INCY, FRAMESLOT(2) + STACKSIZE(SP)
lwz BUFFER, FRAMESLOT(3) + STACKSIZE(SP)
#endif
#else
ld INCX, FRAMESLOT(0) + STACKSIZE(SP)
ld Y, FRAMESLOT(1) + STACKSIZE(SP)
ld INCY, FRAMESLOT(2) + STACKSIZE(SP)
ld BUFFER, FRAMESLOT(3) + STACKSIZE(SP)
#endif
#endif
stfd f1, ALPHA_R
stfd f2, ALPHA_I
slwi LDA, LDA, ZBASE_SHIFT
slwi INCX, INCX, ZBASE_SHIFT
slwi INCY, INCY, ZBASE_SHIFT
addi INCX, INCX, -SIZE
addi INCY, INCY, -SIZE
addi A, A, -SIZE
cmpwi cr0, M, 0
ble- LL(999)
sub X, X, INCX
cmpwi cr0, N, 0
sub Y, Y, INCY
ble- LL(999)
li PREA, PREFETCHSIZE_A * SIZE
mr YY, Y
lfd f0, FZERO
cmpi cr0, 0, INCY, SIZE
beq LL(10)
addi YY, BUFFER, -SIZE
addi Y1, BUFFER, -SIZE
addi r0, M, 3
srawi. r0, r0, 2
mtspr CTR, r0
.align 4
LL(02):
STFDU f0, 1 * SIZE(Y1)
STFDU f0, 1 * SIZE(Y1)
STFDU f0, 1 * SIZE(Y1)
STFDU f0, 1 * SIZE(Y1)
STFDU f0, 1 * SIZE(Y1)
STFDU f0, 1 * SIZE(Y1)
STFDU f0, 1 * SIZE(Y1)
STFDU f0, 1 * SIZE(Y1)
bdnz LL(02)
.align 4
LL(10):
srawi. J, N, 2
ble LL(20)
.align 4
LL(11):
lfd alpha_r, ALPHA_R
lfd alpha_i, ALPHA_I
LFDUX a1, X, INCX
LFDU a2, 1 * SIZE(X)
LFDUX a3, X, INCX
LFDU a4, 1 * SIZE(X)
LFDUX a5, X, INCX
LFDU a6, 1 * SIZE(X)
LFDUX a7, X, INCX
LFDU a8, 1 * SIZE(X)
FMUL alpha1r, alpha_r, a1
FMUL alpha1i, alpha_i, a1
FMUL alpha2r, alpha_r, a3
FMUL alpha2i, alpha_i, a3
FMUL alpha3r, alpha_r, a5
mr Y1, YY
FMUL alpha3i, alpha_i, a5
mr Y2, YY
FMUL alpha4r, alpha_r, a7
mr AO1, A
FMUL alpha4i, alpha_i, a7
add AO2, A, LDA
FMSUBR alpha1r, alpha_i, a2, alpha1r
add AO3, AO2, LDA
FMADDR alpha1i, alpha_r, a2, alpha1i
add AO4, AO3, LDA
FMSUBR alpha2r, alpha_i, a4, alpha2r
add A, AO4, LDA
FMADDR alpha2i, alpha_r, a4, alpha2i
FMSUBR alpha3r, alpha_i, a6, alpha3r
srawi. r0, M, 2
FMADDR alpha3i, alpha_r, a6, alpha3i
FMSUBR alpha4r, alpha_i, a8, alpha4r
mtspr CTR, r0
FMADDR alpha4i, alpha_r, a8, alpha4i
ble LL(15)
.align 4
LFDU a1, 1 * SIZE(AO1)
LFDU y01, 1 * SIZE(Y1)
LFDU a2, 1 * SIZE(AO1)
LFDU y02, 1 * SIZE(Y1)
LFDU a3, 1 * SIZE(AO1)
LFDU y03, 1 * SIZE(Y1)
LFDU a4, 1 * SIZE(AO1)
LFDU y04, 1 * SIZE(Y1)
LFDU a5, 1 * SIZE(AO1)
LFDU y05, 1 * SIZE(Y1)
LFDU a6, 1 * SIZE(AO1)
LFDU y06, 1 * SIZE(Y1)
LFDU a7, 1 * SIZE(AO1)
LFDU y07, 1 * SIZE(Y1)
LFDU a8, 1 * SIZE(AO1)
LFDU y08, 1 * SIZE(Y1)
FMADD y09, alpha1r, a1, y01
FMADD y10, alpha1i, a1, y02
FMADD y11, alpha1r, a3, y03
FMADD y12, alpha1i, a3, y04
FMADD y13, alpha1r, a5, y05
FMADD y14, alpha1i, a5, y06
FMADD y15, alpha1r, a7, y07
FMADD y16, alpha1i, a7, y08
bdz LL(13)
.align 4
LL(12):
FMSUBX y09, alpha1i, a2, y09
LFDU a1, 1 * SIZE(AO2)
FMADDX y10, alpha1r, a2, y10
LFDU a2, 1 * SIZE(AO2)
FMSUBX y11, alpha1i, a4, y11
LFDU a3, 1 * SIZE(AO2)
FMADDX y12, alpha1r, a4, y12
LFDU a4, 1 * SIZE(AO2)
#ifdef PPCG4
dcbt AO2, PREA
#endif
FMSUBX y13, alpha1i, a6, y13
LFDU a5, 1 * SIZE(AO2)
FMADDX y14, alpha1r, a6, y14
LFDU a6, 1 * SIZE(AO2)
FMSUBX y15, alpha1i, a8, y15
LFDU a7, 1 * SIZE(AO2)
FMADDX y16, alpha1r, a8, y16
LFDU a8, 1 * SIZE(AO2)
#if defined(PPCG4) && defined(DOUBLE)
dcbt AO2, PREA
#endif
FMADD y09, alpha2r, a1, y09
LFDU y01, 1 * SIZE(Y1)
FMADD y10, alpha2i, a1, y10
LFDU y02, 1 * SIZE(Y1)
FMADD y11, alpha2r, a3, y11
LFDU y03, 1 * SIZE(Y1)
FMADD y12, alpha2i, a3, y12
LFDU y04, 1 * SIZE(Y1)
#ifdef PPCG4
dcbtst Y1, PREA
#endif
FMADD y13, alpha2r, a5, y13
FMADD y14, alpha2i, a5, y14
FMADD y15, alpha2r, a7, y15
FMADD y16, alpha2i, a7, y16
FMSUBX y09, alpha2i, a2, y09
LFDU a1, 1 * SIZE(AO3)
FMADDX y10, alpha2r, a2, y10
LFDU a2, 1 * SIZE(AO3)
FMSUBX y11, alpha2i, a4, y11
LFDU a3, 1 * SIZE(AO3)
FMADDX y12, alpha2r, a4, y12
LFDU a4, 1 * SIZE(AO3)
#ifdef PPCG4
dcbt AO3, PREA
#endif
FMSUBX y13, alpha2i, a6, y13
LFDU a5, 1 * SIZE(AO3)
FMADDX y14, alpha2r, a6, y14
LFDU a6, 1 * SIZE(AO3)
FMSUBX y15, alpha2i, a8, y15
LFDU a7, 1 * SIZE(AO3)
FMADDX y16, alpha2r, a8, y16
LFDU a8, 1 * SIZE(AO3)
#if defined(PPCG4) && defined(DOUBLE)
dcbt AO3, PREA
#endif
FMADD y09, alpha3r, a1, y09
LFDU y05, 1 * SIZE(Y1)
FMADD y10, alpha3i, a1, y10
LFDU y06, 1 * SIZE(Y1)
FMADD y11, alpha3r, a3, y11
LFDU y07, 1 * SIZE(Y1)
FMADD y12, alpha3i, a3, y12
LFDU y08, 1 * SIZE(Y1)
#if defined(PPCG4) && defined(DOUBLE)
dcbtst Y1, PREA
#endif
FMADD y13, alpha3r, a5, y13
FMADD y14, alpha3i, a5, y14
FMADD y15, alpha3r, a7, y15
FMADD y16, alpha3i, a7, y16
FMSUBX y09, alpha3i, a2, y09
LFDU a1, 1 * SIZE(AO4)
FMADDX y10, alpha3r, a2, y10
LFDU a2, 1 * SIZE(AO4)
FMSUBX y11, alpha3i, a4, y11
LFDU a3, 1 * SIZE(AO4)
FMADDX y12, alpha3r, a4, y12
LFDU a4, 1 * SIZE(AO4)
#ifdef PPCG4
dcbt AO4, PREA
#endif
FMSUBX y13, alpha3i, a6, y13
LFDU a5, 1 * SIZE(AO4)
FMADDX y14, alpha3r, a6, y14
LFDU a6, 1 * SIZE(AO4)
FMSUBX y15, alpha3i, a8, y15
LFDU a7, 1 * SIZE(AO4)
FMADDX y16, alpha3r, a8, y16
LFDU a8, 1 * SIZE(AO4)
#if defined(PPCG4) && defined(DOUBLE)
dcbt AO4, PREA
#endif
FMADD y09, alpha4r, a1, y09
FMADD y10, alpha4i, a1, y10
FMADD y11, alpha4r, a3, y11
FMADD y12, alpha4i, a3, y12
FMADD y13, alpha4r, a5, y13
FMADD y14, alpha4i, a5, y14
FMADD y15, alpha4r, a7, y15
FMADD y16, alpha4i, a7, y16
FMSUBX y09, alpha4i, a2, y09
LFDU a1, 1 * SIZE(AO1)
FMADDX y10, alpha4r, a2, y10
LFDU a2, 1 * SIZE(AO1)
FMSUBX y11, alpha4i, a4, y11
LFDU a3, 1 * SIZE(AO1)
FMADDX y12, alpha4r, a4, y12
LFDU a4, 1 * SIZE(AO1)
#ifdef PPCG4
dcbt AO1, PREA
#endif
FMSUBX y13, alpha4i, a6, y13
LFDU a5, 1 * SIZE(AO1)
FMADDX y14, alpha4r, a6, y14
LFDU a6, 1 * SIZE(AO1)
FMSUBX y15, alpha4i, a8, y15
LFDU a7, 1 * SIZE(AO1)
FMADDX y16, alpha4r, a8, y16
LFDU a8, 1 * SIZE(AO1)
#if defined(PPCG4) && defined(DOUBLE)
dcbt AO1, PREA
#endif
STFDU y09, 1 * SIZE(Y2)
FMADD y09, alpha1r, a1, y01
STFDU y10, 1 * SIZE(Y2)
FMADD y10, alpha1i, a1, y02
STFDU y11, 1 * SIZE(Y2)
FMADD y11, alpha1r, a3, y03
STFDU y12, 1 * SIZE(Y2)
FMADD y12, alpha1i, a3, y04
STFDU y13, 1 * SIZE(Y2)
FMADD y13, alpha1r, a5, y05
STFDU y14, 1 * SIZE(Y2)
FMADD y14, alpha1i, a5, y06
STFDU y15, 1 * SIZE(Y2)
FMADD y15, alpha1r, a7, y07
STFDU y16, 1 * SIZE(Y2)
FMADD y16, alpha1i, a7, y08
bdnz LL(12)
.align 4
LL(13):
FMSUBX y09, alpha1i, a2, y09
LFDU a1, 1 * SIZE(AO2)
FMADDX y10, alpha1r, a2, y10
LFDU a2, 1 * SIZE(AO2)
FMSUBX y11, alpha1i, a4, y11
LFDU a3, 1 * SIZE(AO2)
FMADDX y12, alpha1r, a4, y12
LFDU a4, 1 * SIZE(AO2)
FMSUBX y13, alpha1i, a6, y13
LFDU a5, 1 * SIZE(AO2)
FMADDX y14, alpha1r, a6, y14
LFDU a6, 1 * SIZE(AO2)
FMSUBX y15, alpha1i, a8, y15
LFDU a7, 1 * SIZE(AO2)
FMADDX y16, alpha1r, a8, y16
LFDU a8, 1 * SIZE(AO2)
FMADD y09, alpha2r, a1, y09
FMADD y10, alpha2i, a1, y10
FMADD y11, alpha2r, a3, y11
FMADD y12, alpha2i, a3, y12
FMADD y13, alpha2r, a5, y13
FMADD y14, alpha2i, a5, y14
FMADD y15, alpha2r, a7, y15
FMADD y16, alpha2i, a7, y16
FMSUBX y09, alpha2i, a2, y09
LFDU a1, 1 * SIZE(AO3)
FMADDX y10, alpha2r, a2, y10
LFDU a2, 1 * SIZE(AO3)
FMSUBX y11, alpha2i, a4, y11
LFDU a3, 1 * SIZE(AO3)
FMADDX y12, alpha2r, a4, y12
LFDU a4, 1 * SIZE(AO3)
FMSUBX y13, alpha2i, a6, y13
LFDU a5, 1 * SIZE(AO3)
FMADDX y14, alpha2r, a6, y14
LFDU a6, 1 * SIZE(AO3)
FMSUBX y15, alpha2i, a8, y15
LFDU a7, 1 * SIZE(AO3)
FMADDX y16, alpha2r, a8, y16
LFDU a8, 1 * SIZE(AO3)
FMADD y09, alpha3r, a1, y09
FMADD y10, alpha3i, a1, y10
FMADD y11, alpha3r, a3, y11
FMADD y12, alpha3i, a3, y12
FMADD y13, alpha3r, a5, y13
FMADD y14, alpha3i, a5, y14
FMADD y15, alpha3r, a7, y15
FMADD y16, alpha3i, a7, y16
FMSUBX y09, alpha3i, a2, y09
LFDU a1, 1 * SIZE(AO4)
FMADDX y10, alpha3r, a2, y10
LFDU a2, 1 * SIZE(AO4)
FMSUBX y11, alpha3i, a4, y11
LFDU a3, 1 * SIZE(AO4)
FMADDX y12, alpha3r, a4, y12
LFDU a4, 1 * SIZE(AO4)
FMSUBX y13, alpha3i, a6, y13
LFDU a5, 1 * SIZE(AO4)
FMADDX y14, alpha3r, a6, y14
LFDU a6, 1 * SIZE(AO4)
FMSUBX y15, alpha3i, a8, y15
LFDU a7, 1 * SIZE(AO4)
FMADDX y16, alpha3r, a8, y16
LFDU a8, 1 * SIZE(AO4)
FMADD y09, alpha4r, a1, y09
FMADD y10, alpha4i, a1, y10
FMADD y11, alpha4r, a3, y11
FMADD y12, alpha4i, a3, y12
FMADD y13, alpha4r, a5, y13
FMADD y14, alpha4i, a5, y14
FMADD y15, alpha4r, a7, y15
FMADD y16, alpha4i, a7, y16
FMSUBX y09, alpha4i, a2, y09
FMADDX y10, alpha4r, a2, y10
FMSUBX y11, alpha4i, a4, y11
FMADDX y12, alpha4r, a4, y12
FMSUBX y13, alpha4i, a6, y13
STFDU y09, 1 * SIZE(Y2)
FMADDX y14, alpha4r, a6, y14
STFDU y10, 1 * SIZE(Y2)
FMSUBX y15, alpha4i, a8, y15
STFDU y11, 1 * SIZE(Y2)
FMADDX y16, alpha4r, a8, y16
STFDU y12, 1 * SIZE(Y2)
STFDU y13, 1 * SIZE(Y2)
STFDU y14, 1 * SIZE(Y2)
STFDU y15, 1 * SIZE(Y2)
STFDU y16, 1 * SIZE(Y2)
.align 4
LL(15):
andi. r0, M, 2
ble LL(17)
LFDU a1, 1 * SIZE(AO1)
LFDU y01, 1 * SIZE(Y1)
LFDU a2, 1 * SIZE(AO1)
LFDU y02, 1 * SIZE(Y1)
LFDU a3, 1 * SIZE(AO1)
LFDU y03, 1 * SIZE(Y1)
LFDU a4, 1 * SIZE(AO1)
LFDU y04, 1 * SIZE(Y1)
FMADD y01, alpha1r, a1, y01
LFDU a5, 1 * SIZE(AO2)
FMADD y02, alpha1i, a1, y02
LFDU a6, 1 * SIZE(AO2)
FMADD y03, alpha1r, a3, y03
LFDU a7, 1 * SIZE(AO2)
FMADD y04, alpha1i, a3, y04
LFDU a8, 1 * SIZE(AO2)
FMSUBX y01, alpha1i, a2, y01
LFDU a1, 1 * SIZE(AO3)
FMADDX y02, alpha1r, a2, y02
LFDU a2, 1 * SIZE(AO3)
FMSUBX y03, alpha1i, a4, y03
LFDU a3, 1 * SIZE(AO3)
FMADDX y04, alpha1r, a4, y04
LFDU a4, 1 * SIZE(AO3)
FMADD y01, alpha2r, a5, y01
FMADD y02, alpha2i, a5, y02
FMADD y03, alpha2r, a7, y03
FMADD y04, alpha2i, a7, y04
FMSUBX y01, alpha2i, a6, y01
LFDU a5, 1 * SIZE(AO4)
FMADDX y02, alpha2r, a6, y02
LFDU a6, 1 * SIZE(AO4)
FMSUBX y03, alpha2i, a8, y03
LFDU a7, 1 * SIZE(AO4)
FMADDX y04, alpha2r, a8, y04
LFDU a8, 1 * SIZE(AO4)
FMADD y01, alpha3r, a1, y01
FMADD y02, alpha3i, a1, y02
FMADD y03, alpha3r, a3, y03
FMADD y04, alpha3i, a3, y04
FMSUBX y01, alpha3i, a2, y01
FMADDX y02, alpha3r, a2, y02
FMSUBX y03, alpha3i, a4, y03
FMADDX y04, alpha3r, a4, y04
FMADD y01, alpha4r, a5, y01
FMADD y02, alpha4i, a5, y02
FMADD y03, alpha4r, a7, y03
FMADD y04, alpha4i, a7, y04
FMSUBX y01, alpha4i, a6, y01
FMADDX y02, alpha4r, a6, y02
FMSUBX y03, alpha4i, a8, y03
FMADDX y04, alpha4r, a8, y04
STFDU y01, 1 * SIZE(Y2)
STFDU y02, 1 * SIZE(Y2)
STFDU y03, 1 * SIZE(Y2)
STFDU y04, 1 * SIZE(Y2)
.align 4
LL(17):
andi. r0, M, 1
ble LL(19)
LFDU y01, 1 * SIZE(Y1)
LFDU y02, 1 * SIZE(Y1)
LFDU a1, 1 * SIZE(AO1)
LFDU a2, 1 * SIZE(AO1)
LFDU a3, 1 * SIZE(AO2)
LFDU a4, 1 * SIZE(AO2)
FMADD y01, alpha1r, a1, y01
LFDU a5, 1 * SIZE(AO3)
FMADD y02, alpha1i, a1, y02
LFDU a6, 1 * SIZE(AO3)
FMSUBX y01, alpha1i, a2, y01
LFDU a7, 1 * SIZE(AO4)
FMADDX y02, alpha1r, a2, y02
LFDU a8, 1 * SIZE(AO4)
FMADD y01, alpha2r, a3, y01
FMADD y02, alpha2i, a3, y02
FMSUBX y01, alpha2i, a4, y01
FMADDX y02, alpha2r, a4, y02
FMADD y01, alpha3r, a5, y01
FMADD y02, alpha3i, a5, y02
FMSUBX y01, alpha3i, a6, y01
FMADDX y02, alpha3r, a6, y02
FMADD y01, alpha4r, a7, y01
FMADD y02, alpha4i, a7, y02
FMSUBX y01, alpha4i, a8, y01
FMADDX y02, alpha4r, a8, y02
STFDU y01, 1 * SIZE(Y2)
STFDU y02, 1 * SIZE(Y2)
.align 4
LL(19):
addi J, J, -1
cmpi cr0, 0, J, 0
bgt LL(11)
.align 4
LL(20):
andi. J, N, 2
ble LL(30)
lfd alpha_r, ALPHA_R
lfd alpha_i, ALPHA_I
LFDUX a1, X, INCX
LFDU a2, 1 * SIZE(X)
LFDUX a3, X, INCX
LFDU a4, 1 * SIZE(X)
FMUL alpha1r, alpha_r, a1
mr Y1, YY
FMUL alpha1i, alpha_i, a1
mr Y2, YY
FMUL alpha2r, alpha_r, a3
mr AO1, A
FMUL alpha2i, alpha_i, a3
add AO2, A, LDA
FMSUBR alpha1r, alpha_i, a2, alpha1r
add A, AO2, LDA
FMADDR alpha1i, alpha_r, a2, alpha1i
srawi. r0, M, 2
FMSUBR alpha2r, alpha_i, a4, alpha2r
mtspr CTR, r0
FMADDR alpha2i, alpha_r, a4, alpha2i
ble LL(25)
.align 4
LFDU a1, 1 * SIZE(AO1)
LFDU y01, 1 * SIZE(Y1)
LFDU a2, 1 * SIZE(AO1)
LFDU y02, 1 * SIZE(Y1)
LFDU a3, 1 * SIZE(AO1)
LFDU y03, 1 * SIZE(Y1)
LFDU a4, 1 * SIZE(AO1)
LFDU y04, 1 * SIZE(Y1)
LFDU a5, 1 * SIZE(AO1)
LFDU y05, 1 * SIZE(Y1)
LFDU a6, 1 * SIZE(AO1)
LFDU y06, 1 * SIZE(Y1)
LFDU a7, 1 * SIZE(AO1)
LFDU y07, 1 * SIZE(Y1)
LFDU a8, 1 * SIZE(AO1)
LFDU y08, 1 * SIZE(Y1)
FMADD y09, alpha1r, a1, y01
FMADD y10, alpha1i, a1, y02
FMADD y11, alpha1r, a3, y03
FMADD y12, alpha1i, a3, y04
FMADD y13, alpha1r, a5, y05
FMADD y14, alpha1i, a5, y06
FMADD y15, alpha1r, a7, y07
FMADD y16, alpha1i, a7, y08
bdz LL(23)
.align 4
LL(22):
FMSUBX y09, alpha1i, a2, y09
LFDU a1, 1 * SIZE(AO2)
FMADDX y10, alpha1r, a2, y10
LFDU a2, 1 * SIZE(AO2)
FMSUBX y11, alpha1i, a4, y11
LFDU a3, 1 * SIZE(AO2)
FMADDX y12, alpha1r, a4, y12
LFDU a4, 1 * SIZE(AO2)
#ifdef PPCG4
dcbt AO2, PREA
#endif
FMSUBX y13, alpha1i, a6, y13
LFDU a5, 1 * SIZE(AO2)
FMADDX y14, alpha1r, a6, y14
LFDU a6, 1 * SIZE(AO2)
FMSUBX y15, alpha1i, a8, y15
LFDU a7, 1 * SIZE(AO2)
FMADDX y16, alpha1r, a8, y16
LFDU a8, 1 * SIZE(AO2)
#if defined(PPCG4) && defined(DOUBLE)
dcbt AO2, PREA
#endif
FMADD y09, alpha2r, a1, y09
LFDU y01, 1 * SIZE(Y1)
FMADD y10, alpha2i, a1, y10
LFDU y02, 1 * SIZE(Y1)
FMADD y11, alpha2r, a3, y11
LFDU y03, 1 * SIZE(Y1)
FMADD y12, alpha2i, a3, y12
LFDU y04, 1 * SIZE(Y1)
#ifdef PPCG4
dcbtst Y1, PREA
#endif
FMADD y13, alpha2r, a5, y13
LFDU y05, 1 * SIZE(Y1)
FMADD y14, alpha2i, a5, y14
LFDU y06, 1 * SIZE(Y1)
FMADD y15, alpha2r, a7, y15
LFDU y07, 1 * SIZE(Y1)
FMADD y16, alpha2i, a7, y16
LFDU y08, 1 * SIZE(Y1)
#if defined(PPCG4) && defined(DOUBLE)
dcbtst Y1, PREA
#endif
FMSUBX y09, alpha2i, a2, y09
LFDU a1, 1 * SIZE(AO1)
FMADDX y10, alpha2r, a2, y10
LFDU a2, 1 * SIZE(AO1)
FMSUBX y11, alpha2i, a4, y11
LFDU a3, 1 * SIZE(AO1)
FMADDX y12, alpha2r, a4, y12
LFDU a4, 1 * SIZE(AO1)
#ifdef PPCG4
dcbt AO1, PREA
#endif
FMSUBX y13, alpha2i, a6, y13
LFDU a5, 1 * SIZE(AO1)
FMADDX y14, alpha2r, a6, y14
LFDU a6, 1 * SIZE(AO1)
FMSUBX y15, alpha2i, a8, y15
LFDU a7, 1 * SIZE(AO1)
FMADDX y16, alpha2r, a8, y16
LFDU a8, 1 * SIZE(AO1)
#if defined(PPCG4) && defined(DOUBLE)
dcbt AO1, PREA
#endif
STFDU y09, 1 * SIZE(Y2)
FMADD y09, alpha1r, a1, y01
STFDU y10, 1 * SIZE(Y2)
FMADD y10, alpha1i, a1, y02
STFDU y11, 1 * SIZE(Y2)
FMADD y11, alpha1r, a3, y03
STFDU y12, 1 * SIZE(Y2)
FMADD y12, alpha1i, a3, y04
STFDU y13, 1 * SIZE(Y2)
FMADD y13, alpha1r, a5, y05
STFDU y14, 1 * SIZE(Y2)
FMADD y14, alpha1i, a5, y06
STFDU y15, 1 * SIZE(Y2)
FMADD y15, alpha1r, a7, y07
STFDU y16, 1 * SIZE(Y2)
FMADD y16, alpha1i, a7, y08
bdnz LL(22)
.align 4
LL(23):
FMSUBX y09, alpha1i, a2, y09
LFDU a1, 1 * SIZE(AO2)
FMADDX y10, alpha1r, a2, y10
LFDU a2, 1 * SIZE(AO2)
FMSUBX y11, alpha1i, a4, y11
LFDU a3, 1 * SIZE(AO2)
FMADDX y12, alpha1r, a4, y12
LFDU a4, 1 * SIZE(AO2)
FMSUBX y13, alpha1i, a6, y13
LFDU a5, 1 * SIZE(AO2)
FMADDX y14, alpha1r, a6, y14
LFDU a6, 1 * SIZE(AO2)
FMSUBX y15, alpha1i, a8, y15
LFDU a7, 1 * SIZE(AO2)
FMADDX y16, alpha1r, a8, y16
LFDU a8, 1 * SIZE(AO2)
FMADD y09, alpha2r, a1, y09
FMADD y10, alpha2i, a1, y10
FMADD y11, alpha2r, a3, y11
FMADD y12, alpha2i, a3, y12
FMADD y13, alpha2r, a5, y13
FMADD y14, alpha2i, a5, y14
FMADD y15, alpha2r, a7, y15
FMADD y16, alpha2i, a7, y16
FMSUBX y09, alpha2i, a2, y09
FMADDX y10, alpha2r, a2, y10
FMSUBX y11, alpha2i, a4, y11
FMADDX y12, alpha2r, a4, y12
FMSUBX y13, alpha2i, a6, y13
STFDU y09, 1 * SIZE(Y2)
FMADDX y14, alpha2r, a6, y14
STFDU y10, 1 * SIZE(Y2)
FMSUBX y15, alpha2i, a8, y15
STFDU y11, 1 * SIZE(Y2)
FMADDX y16, alpha2r, a8, y16
STFDU y12, 1 * SIZE(Y2)
STFDU y13, 1 * SIZE(Y2)
STFDU y14, 1 * SIZE(Y2)
STFDU y15, 1 * SIZE(Y2)
STFDU y16, 1 * SIZE(Y2)
.align 4
LL(25):
andi. r0, M, 2
ble LL(27)
LFDU a1, 1 * SIZE(AO1)
LFDU y01, 1 * SIZE(Y1)
LFDU a2, 1 * SIZE(AO1)
LFDU y02, 1 * SIZE(Y1)
LFDU a3, 1 * SIZE(AO1)
LFDU y03, 1 * SIZE(Y1)
LFDU a4, 1 * SIZE(AO1)
LFDU y04, 1 * SIZE(Y1)
FMADD y01, alpha1r, a1, y01
LFDU a5, 1 * SIZE(AO2)
FMADD y02, alpha1i, a1, y02
LFDU a6, 1 * SIZE(AO2)
FMADD y03, alpha1r, a3, y03
LFDU a7, 1 * SIZE(AO2)
FMADD y04, alpha1i, a3, y04
LFDU a8, 1 * SIZE(AO2)
FMSUBX y01, alpha1i, a2, y01
FMADDX y02, alpha1r, a2, y02
FMSUBX y03, alpha1i, a4, y03
FMADDX y04, alpha1r, a4, y04
FMADD y01, alpha2r, a5, y01
FMADD y02, alpha2i, a5, y02
FMADD y03, alpha2r, a7, y03
FMADD y04, alpha2i, a7, y04
FMSUBX y01, alpha2i, a6, y01
FMADDX y02, alpha2r, a6, y02
FMSUBX y03, alpha2i, a8, y03
FMADDX y04, alpha2r, a8, y04
STFDU y01, 1 * SIZE(Y2)
STFDU y02, 1 * SIZE(Y2)
STFDU y03, 1 * SIZE(Y2)
STFDU y04, 1 * SIZE(Y2)
.align 4
LL(27):
andi. r0, M, 1
ble LL(30)
LFDU y01, 1 * SIZE(Y1)
LFDU y02, 1 * SIZE(Y1)
LFDU a1, 1 * SIZE(AO1)
LFDU a2, 1 * SIZE(AO1)
LFDU a3, 1 * SIZE(AO2)
LFDU a4, 1 * SIZE(AO2)
FMADD y01, alpha1r, a1, y01
FMADD y02, alpha1i, a1, y02
FMSUBX y01, alpha1i, a2, y01
FMADDX y02, alpha1r, a2, y02
FMADD y01, alpha2r, a3, y01
FMADD y02, alpha2i, a3, y02
FMSUBX y01, alpha2i, a4, y01
FMADDX y02, alpha2r, a4, y02
STFDU y01, 1 * SIZE(Y2)
STFDU y02, 1 * SIZE(Y2)
.align 4
LL(30):
andi. J, N, 1
ble LL(990)
.align 4
lfd alpha_r, ALPHA_R
lfd alpha_i, ALPHA_I
LFDUX a1, X, INCX
LFDU a2, 1 * SIZE(X)
FMUL alpha1r, alpha_r, a1
mr Y1, YY
mr Y2, YY
FMUL alpha1i, alpha_i, a1
mr AO1, A
add A, A, LDA
FMSUBR alpha1r, alpha_i, a2, alpha1r
srawi. r0, M, 2
mtspr CTR, r0
FMADDR alpha1i, alpha_r, a2, alpha1i
ble LL(35)
.align 4
LFDU a1, 1 * SIZE(AO1)
LFDU y01, 1 * SIZE(Y1)
LFDU a2, 1 * SIZE(AO1)
LFDU y02, 1 * SIZE(Y1)
LFDU a3, 1 * SIZE(AO1)
LFDU y03, 1 * SIZE(Y1)
LFDU a4, 1 * SIZE(AO1)
LFDU y04, 1 * SIZE(Y1)
LFDU a5, 1 * SIZE(AO1)
LFDU y05, 1 * SIZE(Y1)
LFDU a6, 1 * SIZE(AO1)
LFDU y06, 1 * SIZE(Y1)
LFDU a7, 1 * SIZE(AO1)
LFDU y07, 1 * SIZE(Y1)
LFDU a8, 1 * SIZE(AO1)
LFDU y08, 1 * SIZE(Y1)
FMADD y09, alpha1r, a1, y01
FMADD y10, alpha1i, a1, y02
FMADD y11, alpha1r, a3, y03
FMADD y12, alpha1i, a3, y04
FMADD y13, alpha1r, a5, y05
FMADD y14, alpha1i, a5, y06
FMADD y15, alpha1r, a7, y07
FMADD y16, alpha1i, a7, y08
bdz LL(33)
.align 4
LL(32):
FMSUBX y09, alpha1i, a2, y09
LFDU a1, 1 * SIZE(AO1)
FMADDX y10, alpha1r, a2, y10
LFDU a2, 1 * SIZE(AO1)
FMSUBX y11, alpha1i, a4, y11
LFDU a3, 1 * SIZE(AO1)
FMADDX y12, alpha1r, a4, y12
LFDU a4, 1 * SIZE(AO1)
#ifdef PPCG4
dcbt AO1, PREA
#endif
LFDU y01, 1 * SIZE(Y1)
LFDU y02, 1 * SIZE(Y1)
LFDU y03, 1 * SIZE(Y1)
LFDU y04, 1 * SIZE(Y1)
#ifdef PPCG4
dcbtst Y1, PREA
#endif
FMSUBX y13, alpha1i, a6, y13
LFDU a5, 1 * SIZE(AO1)
FMADDX y14, alpha1r, a6, y14
LFDU a6, 1 * SIZE(AO1)
FMSUBX y15, alpha1i, a8, y15
LFDU a7, 1 * SIZE(AO1)
FMADDX y16, alpha1r, a8, y16
LFDU a8, 1 * SIZE(AO1)
#if defined(PPCG4) && defined(DOUBLE)
dcbt AO1, PREA
#endif
LFDU y05, 1 * SIZE(Y1)
LFDU y06, 1 * SIZE(Y1)
LFDU y07, 1 * SIZE(Y1)
LFDU y08, 1 * SIZE(Y1)
#if defined(PPCG4) && defined(DOUBLE)
dcbtst Y1, PREA
#endif
STFDU y09, 1 * SIZE(Y2)
FMADD y09, alpha1r, a1, y01
STFDU y10, 1 * SIZE(Y2)
FMADD y10, alpha1i, a1, y02
STFDU y11, 1 * SIZE(Y2)
FMADD y11, alpha1r, a3, y03
STFDU y12, 1 * SIZE(Y2)
FMADD y12, alpha1i, a3, y04
STFDU y13, 1 * SIZE(Y2)
FMADD y13, alpha1r, a5, y05
STFDU y14, 1 * SIZE(Y2)
FMADD y14, alpha1i, a5, y06
STFDU y15, 1 * SIZE(Y2)
FMADD y15, alpha1r, a7, y07
STFDU y16, 1 * SIZE(Y2)
FMADD y16, alpha1i, a7, y08
bdnz LL(32)
.align 4
LL(33):
FMSUBX y09, alpha1i, a2, y09
FMADDX y10, alpha1r, a2, y10
FMSUBX y11, alpha1i, a4, y11
FMADDX y12, alpha1r, a4, y12
FMSUBX y13, alpha1i, a6, y13
STFDU y09, 1 * SIZE(Y2)
FMADDX y14, alpha1r, a6, y14
STFDU y10, 1 * SIZE(Y2)
FMSUBX y15, alpha1i, a8, y15
STFDU y11, 1 * SIZE(Y2)
FMADDX y16, alpha1r, a8, y16
STFDU y12, 1 * SIZE(Y2)
STFDU y13, 1 * SIZE(Y2)
STFDU y14, 1 * SIZE(Y2)
STFDU y15, 1 * SIZE(Y2)
STFDU y16, 1 * SIZE(Y2)
.align 4
LL(35):
andi. r0, M, 2
ble LL(37)
LFDU a1, 1 * SIZE(AO1)
LFDU y01, 1 * SIZE(Y1)
LFDU a2, 1 * SIZE(AO1)
LFDU y02, 1 * SIZE(Y1)
LFDU a3, 1 * SIZE(AO1)
LFDU y03, 1 * SIZE(Y1)
LFDU a4, 1 * SIZE(AO1)
LFDU y04, 1 * SIZE(Y1)
FMADD y01, alpha1r, a1, y01
FMADD y02, alpha1i, a1, y02
FMADD y03, alpha1r, a3, y03
FMADD y04, alpha1i, a3, y04
FMSUBX y01, alpha1i, a2, y01
FMADDX y02, alpha1r, a2, y02
FMSUBX y03, alpha1i, a4, y03
FMADDX y04, alpha1r, a4, y04
STFDU y01, 1 * SIZE(Y2)
STFDU y02, 1 * SIZE(Y2)
STFDU y03, 1 * SIZE(Y2)
STFDU y04, 1 * SIZE(Y2)
.align 4
LL(37):
andi. r0, M, 1
ble LL(990)
LFDU y01, 1 * SIZE(Y1)
LFDU a1, 1 * SIZE(AO1)
LFDU y02, 1 * SIZE(Y1)
LFDU a2, 1 * SIZE(AO1)
FMADD y01, alpha1r, a1, y01
FMADD y02, alpha1i, a1, y02
FMSUBX y01, alpha1i, a2, y01
FMADDX y02, alpha1r, a2, y02
STFDU y01, 1 * SIZE(Y2)
STFDU y02, 1 * SIZE(Y2)
.align 4
LL(990):
cmpi cr0, 0, INCY, SIZE
beq LL(999)
addi YY, BUFFER, -SIZE
mr Y1, Y
srawi. r0, M, 2
mtspr CTR, r0
ble LL(995)
.align 4
LL(991):
LFDUX f0, Y, INCY
LFDU f1, 1 * SIZE(Y)
LFDUX f2, Y, INCY
LFDU f3, 1 * SIZE(Y)
LFDUX f4, Y, INCY
LFDU f5, 1 * SIZE(Y)
LFDUX f6, Y, INCY
LFDU f7, 1 * SIZE(Y)
LFDU f8, 1 * SIZE(YY)
LFDU f9, 1 * SIZE(YY)
LFDU f10, 1 * SIZE(YY)
LFDU f11, 1 * SIZE(YY)
LFDU f12, 1 * SIZE(YY)
LFDU f13, 1 * SIZE(YY)
LFDU f14, 1 * SIZE(YY)
LFDU f15, 1 * SIZE(YY)
FADD f8, f8, f0
FADD f9, f9, f1
FADD f10, f10, f2
FADD f11, f11, f3
FADD f12, f12, f4
FADD f13, f13, f5
FADD f14, f14, f6
FADD f15, f15, f7
STFDUX f8, Y1, INCY
STFDU f9, 1 * SIZE(Y1)
STFDUX f10, Y1, INCY
STFDU f11, 1 * SIZE(Y1)
STFDUX f12, Y1, INCY
STFDU f13, 1 * SIZE(Y1)
STFDUX f14, Y1, INCY
STFDU f15, 1 * SIZE(Y1)
bdnz LL(991)
.align 4
LL(995):
andi. J, M, 2
ble LL(996)
LFDUX f0, Y, INCY
LFDU f1, 1 * SIZE(Y)
LFDUX f2, Y, INCY
LFDU f3, 1 * SIZE(Y)
LFDU f8, 1 * SIZE(YY)
LFDU f9, 1 * SIZE(YY)
LFDU f10, 1 * SIZE(YY)
LFDU f11, 1 * SIZE(YY)
FADD f8, f8, f0
FADD f9, f9, f1
FADD f10, f10, f2
FADD f11, f11, f3
STFDUX f8, Y1, INCY
STFDU f9, 1 * SIZE(Y1)
STFDUX f10, Y1, INCY
STFDU f11, 1 * SIZE(Y1)
.align 4
LL(996):
andi. J, M, 1
ble LL(999)
LFDUX f0, Y, INCY
LFDU f1, 1 * SIZE(Y)
LFDU f8, 1 * SIZE(YY)
LFDU f9, 1 * SIZE(YY)
FADD f8, f8, f0
FADD f9, f9, f1
STFDUX f8, Y1, INCY
STFDU f9, 1 * SIZE(Y1)
.align 4
LL(999):
li r3, 0
lfd f14, 0(SP)
lfd f15, 8(SP)
lfd f16, 16(SP)
lfd f17, 24(SP)
lfd f18, 32(SP)
lfd f19, 40(SP)
lfd f20, 48(SP)
lfd f21, 56(SP)
lfd f22, 64(SP)
lfd f23, 72(SP)
lfd f24, 80(SP)
lfd f25, 88(SP)
lfd f26, 96(SP)
lfd f27, 104(SP)
lfd f28, 112(SP)
lfd f29, 120(SP)
lfd f30, 128(SP)
lfd f31, 136(SP)
#ifdef __64BIT__
ld r14, 144(SP)
ld r15, 152(SP)
ld r16, 160(SP)
ld r17, 168(SP)
ld r18, 176(SP)
ld r19, 184(SP)
ld r20, 192(SP)
ld r21, 200(SP)
ld r22, 208(SP)
#else
lwz r14, 144(SP)
lwz r15, 148(SP)
lwz r16, 152(SP)
lwz r17, 156(SP)
lwz r18, 160(SP)
lwz r19, 164(SP)
lwz r20, 168(SP)
lwz r21, 172(SP)
lwz r22, 176(SP)
#endif
addi SP, SP, STACKSIZE
blr
EPILOGUE
#endif
| {
"language": "Assembly"
} |
// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \
// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s
ldr x0, some_label
ldr w3, some_label
ldrsw x9, some_label
prfm pldl3keep, some_label
// OBJ: Relocations [
// OBJ-NEXT: Section (2) .rela.text {
// OBJ-NEXT: 0x0 R_AARCH64_LD_PREL_LO19 some_label 0x0
// OBJ-NEXT: 0x4 R_AARCH64_LD_PREL_LO19 some_label 0x0
// OBJ-NEXT: 0x8 R_AARCH64_LD_PREL_LO19 some_label 0x0
// OBJ-NEXT: 0xC R_AARCH64_LD_PREL_LO19 some_label 0x0
// OBJ-NEXT: }
// OBJ-NEXT: ]
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 -emit-llvm -o - %s | FileCheck %s
int bork(unsigned long long x) {
// CHECK: llvm.cttz.i64
// CHECK: llvm.cttz.i64
// CHECK-NOT: lshr
return __builtin_ctzll(x);
}
| {
"language": "Assembly"
} |
// Copyright 2012 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// This code was translated into a form compatible with 6a from the public
// domain sources in SUPERCOP: http://bench.cr.yp.to/supercop.html
// +build amd64,!gccgo,!appengine
DATA ·REDMASK51(SB)/8, $0x0007FFFFFFFFFFFF
GLOBL ·REDMASK51(SB), 8, $8
DATA ·_121666_213(SB)/8, $996687872
GLOBL ·_121666_213(SB), 8, $8
DATA ·_2P0(SB)/8, $0xFFFFFFFFFFFDA
GLOBL ·_2P0(SB), 8, $8
DATA ·_2P1234(SB)/8, $0xFFFFFFFFFFFFE
GLOBL ·_2P1234(SB), 8, $8
| {
"language": "Assembly"
} |
# Check the various features of the ShTest format.
#
# RUN: not %{lit} -j 1 -v %{inputs}/shtest-output-printing > %t.out
# RUN: FileCheck --input-file %t.out %s
#
# END.
# CHECK: -- Testing:
# CHECK: FAIL: shtest-output-printing :: basic.txt
# CHECK-NEXT: *** TEST 'shtest-output-printing :: basic.txt' FAILED ***
# CHECK-NEXT: Script:
# CHECK-NEXT: --
# CHECK: --
# CHECK-NEXT: Exit Code: 1
#
# CHECK: Command Output
# CHECK-NEXT: --
# CHECK-NEXT: $ "true"
# CHECK-NEXT: $ "echo" "hi"
# CHECK-NEXT: # command output:
# CHECK-NEXT: hi
#
# CHECK: $ "wc" "missing-file"
# CHECK-NEXT: # redirected output from '{{.*(/|\\\\)}}basic.txt.tmp.out':
# CHECK-NEXT: missing-file{{.*}} No such file or directory
# CHECK: note: command had no output on stdout or stderr
# CHECK-NEXT: error: command failed with exit status: 1
| {
"language": "Assembly"
} |
config BR2_PACKAGE_ZYRE
bool "zyre"
depends on BR2_INSTALL_LIBSTDCPP # zeromq
depends on BR2_TOOLCHAIN_HAS_THREADS # zeromq
depends on BR2_USE_MMU # czmq
select BR2_PACKAGE_CZMQ
select BR2_PACKAGE_ZEROMQ
help
An open-source framework for proximity-based peer-to-peer
applications.
http://zyre.org
comment "zyre needs a toolchain w/ C++, threads"
depends on BR2_USE_MMU
depends on !(BR2_INSTALL_LIBSTDCPP && BR2_TOOLCHAIN_HAS_THREADS)
| {
"language": "Assembly"
} |
; Test to make sure llvm.invariant.start calls are not treated as clobbers.
; RUN: opt < %s -newgvn -S | FileCheck %s
declare {}* @llvm.invariant.start.p0i8(i64, i8* nocapture) nounwind readonly
declare void @llvm.invariant.end.p0i8({}*, i64, i8* nocapture) nounwind
; We forward store to the load across the invariant.start intrinsic
define i8 @forward_store() {
; CHECK-LABEL: @forward_store
; CHECK: call {}* @llvm.invariant.start.p0i8(i64 1, i8* %a)
; CHECK-NOT: load
; CHECK: ret i8 0
%a = alloca i8
store i8 0, i8* %a
%i = call {}* @llvm.invariant.start.p0i8(i64 1, i8* %a)
%r = load i8, i8* %a
ret i8 %r
}
declare i8 @dummy(i8* nocapture) nounwind readonly
; We forward store to the load in the non-local analysis case,
; i.e. invariant.start is in another basic block.
define i8 @forward_store_nonlocal(i1 %cond) {
; CHECK-LABEL: forward_store_nonlocal
; CHECK: call {}* @llvm.invariant.start.p0i8(i64 1, i8* %a)
; CHECK: ret i8 0
; CHECK: ret i8 %val
%a = alloca i8
store i8 0, i8* %a
%i = call {}* @llvm.invariant.start.p0i8(i64 1, i8* %a)
br i1 %cond, label %loadblock, label %exit
loadblock:
%r = load i8, i8* %a
ret i8 %r
exit:
%val = call i8 @dummy(i8* %a)
ret i8 %val
}
; We should not value forward %foo to the invariant.end corresponding to %bar.
define i8 @forward_store1() {
; CHECK-LABEL: forward_store1
; CHECK: %foo = call {}* @llvm.invariant.start.p0i8
; CHECK-NOT: load
; CHECK: %bar = call {}* @llvm.invariant.start.p0i8
; CHECK: call void @llvm.invariant.end.p0i8({}* %bar, i64 1, i8* %a)
; CHECK: ret i8 0
%a = alloca i8
store i8 0, i8* %a
%foo = call {}* @llvm.invariant.start.p0i8(i64 1, i8* %a)
%r = load i8, i8* %a
%bar = call {}* @llvm.invariant.start.p0i8(i64 1, i8* %a)
call void @llvm.invariant.end.p0i8({}* %bar, i64 1, i8* %a)
ret i8 %r
}
| {
"language": "Assembly"
} |
.FUNCT GO
START::
?FCN: CALL QUEUE,I-LANTERN,200
SET 'CURRENT-LAMP,LAMP
MUL 8,21
PUT CPOBJS,STACK,1
MUL 8,21
ADD STACK,1
PUT CPOBJS,STACK,LORE-BOOK
MUL 8,32
PUT CPOBJS,STACK,1
MUL 8,32
ADD STACK,1
PUT CPOBJS,STACK,CP-SLOT
SET 'LIT,TRUE-VALUE
SET 'WINNER,ADVENTURER
SET 'PLAYER,WINNER
SET 'MLOC,MRB
SET 'HERE,ZORK2-STAIR
RANDOM 70
ADD 70,STACK
CALL QUEUE,I-CLEFT,STACK
PUT STACK,0,1
CALL QUEUE,I-VIEW-CHANGE,4
PUT STACK,0,1
SET 'P-IT-LOC,HERE
SET 'P-IT-OBJECT,FALSE-VALUE
FSET? HERE,TOUCHBIT /?CND1
PRINTI "As in a dream, you see yourself tumbling down a great, dark staircase. All about you are shadowy images of struggles against fierce opponents and diabolical traps. These give way to another round of images: of imposing stone figures, a cool, clear lake, and, now, of an old, yet oddly youthful man. He turns toward you slowly, his long, silver hair dancing about him in a fresh breeze. ""You have reached the final test, my friend! You are proved clever and powerful, but this is not yet enough! Seek me when you feel yourself worthy!"" The dream dissolves around you as his last words echo through the void...."
CRLF
CRLF
CALL V-VERSION
CRLF
?CND1: MOVE WINNER,HERE
MOVE LAMP,HERE
CALL V-LOOK
CALL MAIN-LOOP
JUMP ?FCN
.FUNCT MAIN-LOOP,ICNT,OCNT,NUM,CNT,OBJ,TBL,V,PTBL,OBJ1,TMP,?TMP1
?PRG1: SET 'CNT,0
SET 'OBJ,FALSE-VALUE
SET 'PTBL,TRUE-VALUE
CALL PARSER >P-WON
ZERO? P-WON /?ELS5
GET P-PRSI,P-MATCHLEN >ICNT
GET P-PRSO,P-MATCHLEN >OCNT
ZERO? OCNT \?ELS10
PUSH OCNT
JUMP ?CND6
?ELS10: GRTR? OCNT,1 \?ELS12
SET 'TBL,P-PRSO
ZERO? ICNT \?ELS15
SET 'OBJ,FALSE-VALUE
JUMP ?CND13
?ELS15: GET P-PRSI,1 >OBJ
?CND13: PUSH OCNT
JUMP ?CND6
?ELS12: GRTR? ICNT,1 \?ELS19
SET 'PTBL,FALSE-VALUE
SET 'TBL,P-PRSI
GET P-PRSO,1 >OBJ
PUSH ICNT
JUMP ?CND6
?ELS19: PUSH 1
?CND6: SET 'NUM,STACK
ZERO? OBJ \?CND22
EQUAL? ICNT,1 \?CND22
GET P-PRSI,1 >OBJ
?CND22: EQUAL? PRSA,V?WALK \?ELS29
CALL PERFORM,PRSA,PRSO >V
JUMP ?CND27
?ELS29: ZERO? NUM \?ELS31
GETB P-SYNTAX,P-SBITS
BAND STACK,P-SONUMS
ZERO? STACK \?ELS34
CALL PERFORM,PRSA >V
SET 'PRSO,FALSE-VALUE
JUMP ?CND27
?ELS34: ZERO? LIT \?ELS36
PRINTI "It's too dark to see."
CRLF
JUMP ?CND27
?ELS36: PRINTI "There isn't anything to "
GET P-ITBL,P-VERBN >TMP
ZERO? P-OFLAG /?ELS45
GET TMP,0
PRINTB STACK
JUMP ?CND43
?ELS45: GETB TMP,2 >?TMP1
GETB TMP,3
CALL WORD-PRINT,?TMP1,STACK
?CND43: PRINTI "!"
CRLF
SET 'V,FALSE-VALUE
JUMP ?CND27
?ELS31:
?PRG53: IGRTR? 'CNT,NUM \?ELS57
JUMP ?CND27
?ELS57: ZERO? PTBL /?ELS62
GET P-PRSO,CNT >OBJ1
JUMP ?CND60
?ELS62: GET P-PRSI,CNT >OBJ1
?CND60: GRTR? NUM,1 \?CND66
PRINTD OBJ1
PRINTI ": "
?CND66: ZERO? PTBL /?ELS75
PUSH OBJ1
JUMP ?CND71
?ELS75: PUSH OBJ
?CND71: SET 'PRSO,STACK
ZERO? PTBL /?ELS83
PUSH OBJ
JUMP ?CND79
?ELS83: PUSH OBJ1
?CND79: SET 'PRSI,STACK
CALL PERFORM,PRSA,PRSO,PRSI >V
EQUAL? V,M-FATAL \?PRG53
?CND27: EQUAL? PRSA,V?WAIT /?CND90
EQUAL? PRSA,V?VERSION,V?SCORE,V?RESTORE /?CND90
EQUAL? PRSA,V?SAVE,V?WALK,V?AGAIN \?ELS92
JUMP ?CND90
?ELS92: SET 'L-PRSA,PRSA
SET 'L-PRSO,PRSO
SET 'L-PRSI,PRSI
?CND90: EQUAL? V,M-FATAL \?CND3
SET 'P-CONT,FALSE-VALUE
JUMP ?CND3
?ELS5: SET 'P-CONT,FALSE-VALUE
?CND3: ZERO? P-WON /?PRG1
EQUAL? PRSA,V?RESTORE,V?UNSCRIPT,V?SCRIPT /?PRG1
EQUAL? PRSA,V?SCORE,V?RESTART,V?QUIT /?PRG1
EQUAL? PRSA,V?VERSION,V?SAVE,V?VERBOSE /?PRG1
EQUAL? PRSA,V?SUPER-BRIEF,V?BRIEF,V?TELL \?ELS108
JUMP ?PRG1
?ELS108: INC 'MOVES
CALL CLOCKER >V
JUMP ?PRG1
.FUNCT PERFORM,A,O=0,I=0,V,OA,OO,OI
SET 'OA,PRSA
SET 'OO,PRSO
SET 'OI,PRSI
EQUAL? IT,I,O \?CND1
EQUAL? P-IT-LOC,HERE /?CND1
PRINTI "I don't see what you are referring to."
CRLF
RETURN 2
?CND1: EQUAL? O,IT \?CND10
SET 'O,P-IT-OBJECT
?CND10: EQUAL? I,IT \?CND13
SET 'I,P-IT-OBJECT
?CND13: SET 'PRSA,A
SET 'PRSO,O
ZERO? PRSO /?CND16
EQUAL? PRSA,V?WALK /?CND16
SET 'P-IT-OBJECT,PRSO
SET 'P-IT-LOC,HERE
?CND16: SET 'PRSI,I
GETP WINNER,P?ACTION
CALL STACK >V
ZERO? V /?ELS23
JUMP ?CND21
?ELS23: LOC WINNER
GETP STACK,P?ACTION
CALL STACK,M-BEG >V
ZERO? V /?ELS25
JUMP ?CND21
?ELS25: GET PREACTIONS,A
CALL STACK >V
ZERO? V /?ELS27
JUMP ?CND21
?ELS27: ZERO? I /?ELS29
GETP I,P?ACTION
CALL STACK >V
ZERO? V /?ELS29
JUMP ?CND21
?ELS29: ZERO? O /?ELS33
EQUAL? A,V?WALK /?ELS33
GETP O,P?ACTION
CALL STACK >V
ZERO? V /?ELS33
JUMP ?CND21
?ELS33: GET ACTIONS,A
CALL STACK >V
ZERO? V /?CND21
?CND21: EQUAL? V,M-FATAL /?CND38
LOC WINNER
EQUAL? STACK,PRSO \?CND41
SET 'PRSO,FALSE-VALUE
?CND41: LOC WINNER
GETP STACK,P?ACTION
CALL STACK,M-END >V
?CND38: SET 'PRSA,OA
SET 'PRSO,OO
SET 'PRSI,OI
RETURN V
.ENDI
| {
"language": "Assembly"
} |
;/*****************************************************************************
; * @file: startup_LPC177x_8x.s
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
; * for the NXP LPC177x_8x Device Series
; * @version: V1.20
; * @date: 07. October 2010
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2010 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 16: Watchdog Timer
DCD TIMER0_IRQHandler ; 17: Timer0
DCD TIMER1_IRQHandler ; 18: Timer1
DCD TIMER2_IRQHandler ; 19: Timer2
DCD TIMER3_IRQHandler ; 20: Timer3
DCD UART0_IRQHandler ; 21: UART0
DCD UART1_IRQHandler ; 22: UART1
DCD UART2_IRQHandler ; 23: UART2
DCD UART3_IRQHandler ; 24: UART3
DCD PWM1_IRQHandler ; 25: PWM1
DCD I2C0_IRQHandler ; 26: I2C0
DCD I2C1_IRQHandler ; 27: I2C1
DCD I2C2_IRQHandler ; 28: I2C2
DCD SPIFI_IRQHandler ; 29: SPIFI
DCD SSP0_IRQHandler ; 30: SSP0
DCD SSP1_IRQHandler ; 31: SSP1
DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
DCD RTC_IRQHandler ; 33: Real Time Clock
DCD EINT0_IRQHandler ; 34: External Interrupt 0
DCD EINT1_IRQHandler ; 35: External Interrupt 1
DCD EINT2_IRQHandler ; 36: External Interrupt 2
DCD EINT3_IRQHandler ; 37: External Interrupt 3
DCD ADC_IRQHandler ; 38: A/D Converter
DCD BOD_IRQHandler ; 39: Brown-Out Detect
DCD USB_IRQHandler ; 40: USB
DCD CAN_IRQHandler ; 41: CAN
DCD DMA_IRQHandler ; 42: General Purpose DMA
DCD I2S_IRQHandler ; 43: I2S
DCD ENET_IRQHandler ; 44: Ethernet
DCD MCI_IRQHandler ; 45: SD/MMC card I/F
DCD MCPWM_IRQHandler ; 46: Motor Control PWM
DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup
DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup
DCD UART4_IRQHandler ; 51: UART4
DCD SSP2_IRQHandler ; 52: SSP2
DCD LCD_IRQHandler ; 53: LCD
DCD GPIO_IRQHandler ; 54: GPIO
DCD PWM0_IRQHandler ; 55: PWM0
DCD EEPROM_IRQHandler ; 56: EEPROM
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT PWM1_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT SPIFI_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT PLL0_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT I2S_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT MCI_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
EXPORT PLL1_IRQHandler [WEAK]
EXPORT USBActivity_IRQHandler [WEAK]
EXPORT CANActivity_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT SSP2_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT GPIO_IRQHandler [WEAK]
EXPORT PWM0_IRQHandler [WEAK]
EXPORT EEPROM_IRQHandler [WEAK]
WDT_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
PWM1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
SPIFI_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
PLL0_IRQHandler
RTC_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
ADC_IRQHandler
BOD_IRQHandler
USB_IRQHandler
CAN_IRQHandler
DMA_IRQHandler
I2S_IRQHandler
ENET_IRQHandler
MCI_IRQHandler
MCPWM_IRQHandler
QEI_IRQHandler
PLL1_IRQHandler
USBActivity_IRQHandler
CANActivity_IRQHandler
UART4_IRQHandler
SSP2_IRQHandler
LCD_IRQHandler
GPIO_IRQHandler
PWM0_IRQHandler
EEPROM_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
| {
"language": "Assembly"
} |
/*
* Debugging boot sector. Reads the first directory
* sector from disk and displays it.
*
* It relies on the _volid field in the FAT header containing
* the LBA of the root directory.
*/
#include "x16.h"
#define DIROFF 0x00200 /* where to read the root directory (offset) */
#define LOADSEG (0x10000/16) /* where to load code (64KB) */
#define LOADOFF 0
/*
* FAT directory entry.
*/
#define Dname 0x00
#define Dext 0x08
#define Dattr 0x0B
#define Dtime 0x16
#define Ddate 0x18
#define Dstart 0x1A
#define Dlengthlo 0x1C
#define Dlengthhi 0x1E
#define Dirsz 0x20
/*
* We keep data on the stack, indexed by rBP.
*/
#define Xdrive 0x00 /* boot drive, passed by BIOS in rDL */
#define Xrootlo 0x02 /* offset of root directory */
#define Xroothi 0x04
#define Xrootsz 0x06 /* file data area */
#define Xtotal 0x08 /* sum of allocated data above */
#define Xdap 0x00 /* disc address packet */
TEXT _magic(SB), $0
BYTE $0xEB; BYTE $0x3C; /* jmp .+ 0x3C (_start0x3E) */
BYTE $0x90 /* nop */
TEXT _version(SB), $0
BYTE $0x00; BYTE $0x00; BYTE $0x00; BYTE $0x00;
BYTE $0x00; BYTE $0x00; BYTE $0x00; BYTE $0x00
TEXT _sectsize(SB), $0
BYTE $0x00; BYTE $0x00
TEXT _clustsize(SB), $0
BYTE $0x00
TEXT _nresrv(SB), $0
BYTE $0x00; BYTE $0x00
TEXT _nfats(SB), $0
BYTE $0x00
TEXT _rootsize(SB), $0
BYTE $0x00; BYTE $0x00
TEXT _volsize(SB), $0
BYTE $0x00; BYTE $0x00
TEXT _mediadesc(SB), $0
BYTE $0x00
TEXT _fatsize(SB), $0
BYTE $0x00; BYTE $0x00
TEXT _trksize(SB), $0
BYTE $0x00; BYTE $0x00
TEXT _nheads(SB), $0
BYTE $0x00; BYTE $0x00
TEXT _nhiddenlo(SB), $0
BYTE $0x00; BYTE $0x00
TEXT _nhiddenhi(SB), $0
BYTE $0x00; BYTE $0x00;
TEXT _bigvolsize(SB), $0
BYTE $0x00; BYTE $0x00; BYTE $0x00; BYTE $0x00;
TEXT _driveno(SB), $0
BYTE $0x00
TEXT _reserved0(SB), $0
BYTE $0x00
TEXT _bootsig(SB), $0
BYTE $0x00
TEXT _volid(SB), $0
BYTE $0x00; BYTE $0x00; BYTE $0x00; BYTE $0x00;
TEXT _label(SB), $0
BYTE $0x00; BYTE $0x00; BYTE $0x00; BYTE $0x00;
BYTE $0x00; BYTE $0x00; BYTE $0x00; BYTE $0x00
BYTE $0x00; BYTE $0x00; BYTE $0x00
TEXT _type(SB), $0
BYTE $0x00; BYTE $0x00; BYTE $0x00; BYTE $0x00;
BYTE $0x00; BYTE $0x00; BYTE $0x00; BYTE $0x00;
_start0x3E:
CLI
CLR(rAX)
MTSR(rAX, rSS) /* 0000 -> rSS */
MTSR(rAX, rDS) /* 0000 -> rDS, source segment */
MTSR(rAX, rES)
LWI(_magic-Xtotal(SB), rSP)
MW(rSP, rBP) /* set the indexed-data pointer */
SBPB(rDL, Xdrive) /* save the boot drive */
STI
LWI(confidence(SB), rSI) /* for that warm, fuzzy feeling */
CALL(BIOSputs(SB))
LBI(0x41, rAH) /* check extensions present */
LWI(0x55AA, rBX)
LXB(Xdrive, xBP, rDL) /* drive */
SYSCALL(0x13) /* CF set on failure */
JCS _jmp01
CMPI(0xAA55, rBX)
JNE _jmp01
ANDI(0x0001, rCX)
JEQ _jmp01
/* rCX contains 0x0001 */
SBPWI(0x0010, Xdap+0) /* reserved + packet size */
SBPW(rCX, Xdap+2) /* reserved + # of blocks to transfer */
DEC(rCX)
SBPW(rCX, Xdap+12)
SBPW(rCX, Xdap+14)
/* BIOSread will do this CALL(dreset(SB)) */
_jmp00:
LW(_volid(SB), rAX) /* Xrootlo */
LW(_volid+2(SB), rDX) /* Xroothi */
LWI(_magic+DIROFF(SB), rBX)
CALL(BIOSread(SB)) /* read the root directory */
CALL(printnl(SB))
LWI(_magic+DIROFF(SB), rBX)
LWI((512/2), rCX)
CALL(printbuf(SB))
xloop:
JMP xloop
_jmp01:
TEXT buggery(SB), $0
LWI(error(SB), rSI)
CALL(BIOSputs(SB))
xbuggery:
JMP xbuggery
/*
* Read a sector from a disc. On entry:
* rDX:rAX sector number
* rES:rBX buffer address
*/
TEXT BIOSread(SB), $0
LWI(5, rDI) /* retry count (ATAPI ZIPs suck) */
_retry:
PUSHA /* may be trashed by SYSCALL */
SBPW(rBX, Xdap+4) /* transfer buffer :offset */
MFSR(rES, rDI) /* transfer buffer seg: */
SBPW(rDI, Xdap+6)
SBPW(rAX, Xdap+8) /* LBA (64-bits) */
SBPW(rDX, Xdap+10)
MW(rBP, rSI) /* disk address packet */
LBI(0x42, rAH) /* extended read */
LBPB(Xdrive, rDL) /* form drive */
SYSCALL(0x13) /* CF set on failure */
JCC _BIOSreadret
POPA
DEC(rDI) /* too many retries? */
JEQ _ioerror
CALL(dreset(SB))
JMP _retry
_ioerror:
LWI(ioerror(SB), rSI)
CALL(BIOSputs(SB))
JMP xbuggery
_BIOSreadret:
POPA
RET
TEXT dreset(SB), $0
PUSHA
CLR(rAX) /* rAH == 0 == reset disc system */
LBPB(Xdrive, rDL)
SYSCALL(0x13)
ORB(rAH, rAH) /* status (0 == success) */
POPA
JNE _ioerror
RET
TEXT printsharp(SB), $0
LWI(sharp(SB), rSI)
_doprint:
CALL(BIOSputs(SB))
RET
TEXT printspace(SB), $0
LWI(space(SB), rSI)
JMP _doprint
TEXT printnl(SB), $0
LWI(nl(SB), rSI)
JMP _doprint
/*
* Output a string to the display.
* String argument is in rSI.
*/
TEXT BIOSputs(SB), $0
PUSHA
CLR(rBX)
_BIOSputs:
LODSB
ORB(rAL, rAL)
JEQ _BIOSputsret
LBI(0x0E, rAH)
SYSCALL(0x10)
JMP _BIOSputs
_BIOSputsret:
POPA
RET
/*
* Output a register to the display.
*/
TEXT printAX(SB), $0
PUSHW(rAX)
PUSHW(rBX)
PUSHW(rCX)
PUSHW(rDI)
LWI(4, rCX)
LWI(numbuf+4(SB), rSI)
_nextchar:
DEC(rSI)
MW(rAX, rBX)
ANDI(0x000F, rBX)
ADDI(0x30, rBX) /* 0x30 = '0' */
CMPI(0x39, rBX) /* 0x39 = '9' */
JLE _dowrite
ADDI(0x07, rBX) /* 0x07 = 'A'-(1+'9')*/
_dowrite:
SXB(rBL, 0, xSI)
SHRI(4, rAX)
DEC(rCX)
JNE _nextchar
LWI(numbuf(SB), rSI)
CALL(BIOSputs(SB))
POPW(rDI)
POPW(rCX)
POPW(rBX)
POPW(rAX)
CALL(printspace(SB))
RET
TEXT printDXAX(SB), $0
PUSHW(rAX)
MW(rDX, rAX)
CALL(printAX(SB))
POPW(rAX)
CALL(printAX(SB))
RET
TEXT printBX(SB), $0
PUSHW(rAX)
MW(rBX, rAX)
CALL(printAX(SB))
POPW(rAX)
RET
/*
* Output some number of words to the display
* rDS:rDI - buffer
* rCX: number of words
*/
TEXT printbuf(SB), $0
PUSHW(rAX)
PUSHW(rBX)
PUSHW(rCX)
_nextword:
LXW(0, xBX, rAX)
CALL(printAX(SB))
INC(rBX)
INC(rBX)
DEC(rCX)
JNE _nextword
POPW(rCX)
POPW(rBX)
POPW(rAX)
RET
TEXT error(SB), $0
BYTE $'E';
TEXT ioerror(SB), $0
BYTE $'I';
TEXT nl(SB), $0
BYTE $'\r';
BYTE $'\n';
BYTE $'\z';
TEXT numbuf(SB), $0
BYTE $'X'; BYTE $'X'; BYTE $'X'; BYTE $'X';
BYTE $'\z';
TEXT space(SB), $0
BYTE $' ';
BYTE $'\z';
TEXT sharp(SB), $0
BYTE $'#'; BYTE $'\z';
| {
"language": "Assembly"
} |
ENTRY (Start)
SECTIONS
{
. = 0x8000;
_start = .;
_text_start = .;
.text :
{
KEEP(*(.text.boot))
*(.text)
}
. = ALIGN(4096);
_text_end = .;
_rodata_start = .;
.rodata :
{
*(.rodata)
}
. = ALIGN(4096);
_rodata_end = .;
_data_start = .;
.data :
{
*(.data)
}
. = ALIGN(4096);
_data_end = .;
_bss_start = .;
.bss :
{
bss = .;
*(.bss)
}
. = ALIGN(4096);
_bss_end = .;
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx*)
}
__exidx_end = .;
_end = .;
}
| {
"language": "Assembly"
} |
glabel func_8003937C
/* AB051C 8003937C 27BDFFD8 */ addiu $sp, $sp, -0x28
/* AB0520 80039380 AFA60030 */ sw $a2, 0x30($sp)
/* AB0524 80039384 AFBF0014 */ sw $ra, 0x14($sp)
/* AB0528 80039388 3C068016 */ lui $a2, %hi(D_8015BD10) # $a2, 0x8016
/* AB052C 8003938C AFA40028 */ sw $a0, 0x28($sp)
/* AB0530 80039390 AFA70034 */ sw $a3, 0x34($sp)
/* AB0534 80039394 0C00E2F8 */ jal func_80038BE0
/* AB0538 80039398 24C6BD10 */ addiu $a2, %lo(D_8015BD10) # addiu $a2, $a2, -0x42f0
/* AB053C 8003939C 3C058016 */ lui $a1, %hi(D_8015BD34) # $a1, 0x8016
/* AB0540 800393A0 3C068016 */ lui $a2, %hi(D_8015BD38) # $a2, 0x8016
/* AB0544 800393A4 3C078016 */ lui $a3, %hi(D_8015BD3C) # $a3, 0x8016
/* AB0548 800393A8 24E7BD3C */ addiu $a3, %lo(D_8015BD3C) # addiu $a3, $a3, -0x42c4
/* AB054C 800393AC 24C6BD38 */ addiu $a2, %lo(D_8015BD38) # addiu $a2, $a2, -0x42c8
/* AB0550 800393B0 24A5BD34 */ addiu $a1, %lo(D_8015BD34) # addiu $a1, $a1, -0x42cc
/* AB0554 800393B4 0C00E275 */ jal func_800389D4
/* AB0558 800393B8 8FA40028 */ lw $a0, 0x28($sp)
/* AB055C 800393BC 8FAE0028 */ lw $t6, 0x28($sp)
/* AB0560 800393C0 8FA20030 */ lw $v0, 0x30($sp)
/* AB0564 800393C4 3C018016 */ lui $at, %hi(D_8015BD40)
/* AB0568 800393C8 85CF000E */ lh $t7, 0xe($t6)
/* AB056C 800393CC 3C048016 */ lui $a0, %hi(D_8015BD08) # $a0, 0x8016
/* AB0570 800393D0 3C058016 */ lui $a1, %hi(D_8015BD10)
/* AB0574 800393D4 448F2000 */ mtc1 $t7, $f4
/* AB0578 800393D8 24A5BD10 */ addiu $a1, %lo(D_8015BD10)
/* AB057C 800393DC 2484BD08 */ addiu $a0, %lo(D_8015BD08) # addiu $a0, $a0, -0x42f8
/* AB0580 800393E0 468021A0 */ cvt.s.w $f6, $f4
/* AB0584 800393E4 27A6001C */ addiu $a2, $sp, 0x1c
/* AB0588 800393E8 E426BD40 */ swc1 $f6, %lo(D_8015BD40)($at)
/* AB058C 800393EC C4480000 */ lwc1 $f8, ($v0)
/* AB0590 800393F0 3C018016 */ lui $at, %hi(D_8015BD0C) # $at, 0x8016
/* AB0594 800393F4 4600428D */ trunc.w.s $f10, $f8
/* AB0598 800393F8 C7A80034 */ lwc1 $f8, 0x34($sp)
/* AB059C 800393FC 44195000 */ mfc1 $t9, $f10
/* AB05A0 80039400 4600428D */ trunc.w.s $f10, $f8
/* AB05A4 80039404 A439BD08 */ sh $t9, %lo(D_8015BD08)($at)
/* AB05A8 80039408 C4500004 */ lwc1 $f16, 4($v0)
/* AB05AC 8003940C 440D5000 */ mfc1 $t5, $f10
/* AB05B0 80039410 4600848D */ trunc.w.s $f18, $f16
/* AB05B4 80039414 44099000 */ mfc1 $t1, $f18
/* AB05B8 80039418 00000000 */ nop
/* AB05BC 8003941C A429BD0A */ sh $t1, %lo(D_8015BD0A)($at)
/* AB05C0 80039420 C4440008 */ lwc1 $f4, 8($v0)
/* AB05C4 80039424 A42DBD0E */ sh $t5, %lo(D_8015BD0E)($at)
/* AB05C8 80039428 4600218D */ trunc.w.s $f6, $f4
/* AB05CC 8003942C 440B3000 */ mfc1 $t3, $f6
/* AB05D0 80039430 0C033A4D */ jal Math3D_TriVsSphIntersect
/* AB05D4 80039434 A42BBD0C */ sh $t3, %lo(D_8015BD0C)($at)
/* AB05D8 80039438 8FBF0014 */ lw $ra, 0x14($sp)
/* AB05DC 8003943C 27BD0028 */ addiu $sp, $sp, 0x28
/* AB05E0 80039440 03E00008 */ jr $ra
/* AB05E4 80039444 00000000 */ nop
| {
"language": "Assembly"
} |
glabel func_80045508
/* ABC6A8 80045508 27BDFFA8 */ addiu $sp, $sp, -0x58
/* ABC6AC 8004550C AFBF001C */ sw $ra, 0x1c($sp)
/* ABC6B0 80045510 AFB10018 */ sw $s1, 0x18($sp)
/* ABC6B4 80045514 AFB00014 */ sw $s0, 0x14($sp)
/* ABC6B8 80045518 AFA5005C */ sw $a1, 0x5c($sp)
/* ABC6BC 8004551C 24820074 */ addiu $v0, $a0, 0x74
/* ABC6C0 80045520 8C4F0000 */ lw $t7, ($v0)
/* ABC6C4 80045524 24850050 */ addiu $a1, $a0, 0x50
/* ABC6C8 80045528 00C08025 */ move $s0, $a2
/* ABC6CC 8004552C ACCF0000 */ sw $t7, ($a2)
/* ABC6D0 80045530 8C4E0004 */ lw $t6, 4($v0)
/* ABC6D4 80045534 00E08825 */ move $s1, $a3
/* ABC6D8 80045538 ACCE0004 */ sw $t6, 4($a2)
/* ABC6DC 8004553C 8C4F0008 */ lw $t7, 8($v0)
/* ABC6E0 80045540 ACCF0008 */ sw $t7, 8($a2)
/* ABC6E4 80045544 AFA5002C */ sw $a1, 0x2c($sp)
/* ABC6E8 80045548 AFA40058 */ sw $a0, 0x58($sp)
/* ABC6EC 8004554C AFA00034 */ sw $zero, 0x34($sp)
/* ABC6F0 80045550 0C010F46 */ jal func_80043D18
/* ABC6F4 80045554 AFA20028 */ sw $v0, 0x28($sp)
/* ABC6F8 80045558 8FA30034 */ lw $v1, 0x34($sp)
/* ABC6FC 8004555C 10400067 */ beqz $v0, .L800456FC
/* ABC700 80045560 AFA2003C */ sw $v0, 0x3c($sp)
/* ABC704 80045564 8FB8002C */ lw $t8, 0x2c($sp)
/* ABC708 80045568 2605000C */ addiu $a1, $s0, 0xc
/* ABC70C 8004556C 2604001C */ addiu $a0, $s0, 0x1c
/* ABC710 80045570 8F080000 */ lw $t0, ($t8)
/* ABC714 80045574 AE280000 */ sw $t0, ($s1)
/* ABC718 80045578 8F190004 */ lw $t9, 4($t8)
/* ABC71C 8004557C AE390004 */ sw $t9, 4($s1)
/* ABC720 80045580 8F080008 */ lw $t0, 8($t8)
/* ABC724 80045584 AE280008 */ sw $t0, 8($s1)
/* ABC728 80045588 0C01F0FD */ jal OLib_Vec3fToVecSphGeo
/* ABC72C 8004558C AFA50024 */ sw $a1, 0x24($sp)
/* ABC730 80045590 86090020 */ lh $t1, 0x20($s0)
/* ABC734 80045594 8FAA005C */ lw $t2, 0x5c($sp)
/* ABC738 80045598 02203025 */ move $a2, $s1
/* ABC73C 8004559C 29212EE1 */ slti $at, $t1, 0x2ee1
/* ABC740 800455A0 54200004 */ bnezl $at, .L800455B4
/* ABC744 800455A4 8FA40058 */ lw $a0, 0x58($sp)
/* ABC748 800455A8 854B0006 */ lh $t3, 6($t2)
/* ABC74C 800455AC A60B0022 */ sh $t3, 0x22($s0)
/* ABC750 800455B0 8FA40058 */ lw $a0, 0x58($sp)
.L800455B4:
/* ABC754 800455B4 0C010F46 */ jal func_80043D18
/* ABC758 800455B8 8FA50028 */ lw $a1, 0x28($sp)
/* ABC75C 800455BC 14400023 */ bnez $v0, .L8004564C
/* ABC760 800455C0 AFA20038 */ sw $v0, 0x38($sp)
/* ABC764 800455C4 87AC006A */ lh $t4, 0x6a($sp)
/* ABC768 800455C8 8FAE002C */ lw $t6, 0x2c($sp)
/* ABC76C 800455CC 318D0001 */ andi $t5, $t4, 1
/* ABC770 800455D0 11A0001C */ beqz $t5, .L80045644
/* ABC774 800455D4 00000000 */ nop
/* ABC778 800455D8 8DD80000 */ lw $t8, ($t6)
/* ABC77C 800455DC 27A50040 */ addiu $a1, $sp, 0x40
/* ABC780 800455E0 02203025 */ move $a2, $s1
/* ABC784 800455E4 AE380000 */ sw $t8, ($s1)
/* ABC788 800455E8 8DCF0004 */ lw $t7, 4($t6)
/* ABC78C 800455EC AE2F0004 */ sw $t7, 4($s1)
/* ABC790 800455F0 8DD80008 */ lw $t8, 8($t6)
/* ABC794 800455F4 AE380008 */ sw $t8, 8($s1)
/* ABC798 800455F8 8FB90058 */ lw $t9, 0x58($sp)
/* ABC79C 800455FC 8F29005C */ lw $t1, 0x5c($t9)
/* ABC7A0 80045600 ACA90000 */ sw $t1, ($a1)
/* ABC7A4 80045604 8F280060 */ lw $t0, 0x60($t9)
/* ABC7A8 80045608 ACA80004 */ sw $t0, 4($a1)
/* ABC7AC 8004560C 8F290064 */ lw $t1, 0x64($t9)
/* ABC7B0 80045610 ACA90008 */ sw $t1, 8($a1)
/* ABC7B4 80045614 0C010F46 */ jal func_80043D18
/* ABC7B8 80045618 8FA40058 */ lw $a0, 0x58($sp)
/* ABC7BC 8004561C 54400004 */ bnezl $v0, .L80045630
/* ABC7C0 80045620 8E2A0018 */ lw $t2, 0x18($s1)
/* ABC7C4 80045624 10000036 */ b .L80045700
/* ABC7C8 80045628 24020003 */ li $v0, 3
/* ABC7CC 8004562C 8E2A0018 */ lw $t2, 0x18($s1)
.L80045630:
/* ABC7D0 80045630 8E0B0018 */ lw $t3, 0x18($s0)
/* ABC7D4 80045634 554B000C */ bnel $t2, $t3, .L80045668
/* ABC7D8 80045638 2630000C */ addiu $s0, $s1, 0xc
/* ABC7DC 8004563C 10000030 */ b .L80045700
/* ABC7E0 80045640 24020003 */ li $v0, 3
.L80045644:
/* ABC7E4 80045644 1000002E */ b .L80045700
/* ABC7E8 80045648 24020003 */ li $v0, 3
.L8004564C:
/* ABC7EC 8004564C 8E2C0018 */ lw $t4, 0x18($s1)
/* ABC7F0 80045650 8E0D0018 */ lw $t5, 0x18($s0)
/* ABC7F4 80045654 558D0004 */ bnel $t4, $t5, .L80045668
/* ABC7F8 80045658 2630000C */ addiu $s0, $s1, 0xc
/* ABC7FC 8004565C 10000028 */ b .L80045700
/* ABC800 80045660 24020003 */ li $v0, 3
/* ABC804 80045664 2630000C */ addiu $s0, $s1, 0xc
.L80045668:
/* ABC808 80045668 02002825 */ move $a1, $s0
/* ABC80C 8004566C 0C01F0FD */ jal OLib_Vec3fToVecSphGeo
/* ABC810 80045670 2624001C */ addiu $a0, $s1, 0x1c
/* ABC814 80045674 862E0020 */ lh $t6, 0x20($s1)
/* ABC818 80045678 8FAF005C */ lw $t7, 0x5c($sp)
/* ABC81C 8004567C 02002825 */ move $a1, $s0
/* ABC820 80045680 29C12EE1 */ slti $at, $t6, 0x2ee1
/* ABC824 80045684 54200005 */ bnezl $at, .L8004569C
/* ABC828 80045688 8FA8003C */ lw $t0, 0x3c($sp)
/* ABC82C 8004568C 85F80006 */ lh $t8, 6($t7)
/* ABC830 80045690 27198001 */ addiu $t9, $t8, -0x7fff
/* ABC834 80045694 A6390022 */ sh $t9, 0x22($s1)
/* ABC838 80045698 8FA8003C */ lw $t0, 0x3c($sp)
.L8004569C:
/* ABC83C 8004569C 8FA90038 */ lw $t1, 0x38($sp)
/* ABC840 800456A0 11090003 */ beq $t0, $t1, .L800456B0
/* ABC844 800456A4 00000000 */ nop
/* ABC848 800456A8 10000014 */ b .L800456FC
/* ABC84C 800456AC 24030003 */ li $v1, 3
.L800456B0:
/* ABC850 800456B0 0C032BFB */ jal Math3D_Cos
/* ABC854 800456B4 8FA40024 */ lw $a0, 0x24($sp)
/* ABC858 800456B8 3C01BF00 */ li $at, 0xBF000000 # 0.000000
/* ABC85C 800456BC 44812000 */ mtc1 $at, $f4
/* ABC860 800456C0 3C013F00 */ li $at, 0x3F000000 # 0.000000
/* ABC864 800456C4 4604003C */ c.lt.s $f0, $f4
/* ABC868 800456C8 00000000 */ nop
/* ABC86C 800456CC 45020004 */ bc1fl .L800456E0
/* ABC870 800456D0 44813000 */ mtc1 $at, $f6
/* ABC874 800456D4 10000009 */ b .L800456FC
/* ABC878 800456D8 24030006 */ li $v1, 6
/* ABC87C 800456DC 44813000 */ mtc1 $at, $f6
.L800456E0:
/* ABC880 800456E0 24030002 */ li $v1, 2
/* ABC884 800456E4 4600303C */ c.lt.s $f6, $f0
/* ABC888 800456E8 00000000 */ nop
/* ABC88C 800456EC 45000003 */ bc1f .L800456FC
/* ABC890 800456F0 00000000 */ nop
/* ABC894 800456F4 10000001 */ b .L800456FC
/* ABC898 800456F8 24030003 */ li $v1, 3
.L800456FC:
/* ABC89C 800456FC 00601025 */ move $v0, $v1
.L80045700:
/* ABC8A0 80045700 8FBF001C */ lw $ra, 0x1c($sp)
/* ABC8A4 80045704 8FB00014 */ lw $s0, 0x14($sp)
/* ABC8A8 80045708 8FB10018 */ lw $s1, 0x18($sp)
/* ABC8AC 8004570C 03E00008 */ jr $ra
/* ABC8B0 80045710 27BD0058 */ addiu $sp, $sp, 0x58
| {
"language": "Assembly"
} |
/*********************************************************************/
/* Copyright 2009, 2010 The University of Texas at Austin. */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or */
/* without modification, are permitted provided that the following */
/* conditions are met: */
/* */
/* 1. Redistributions of source code must retain the above */
/* copyright notice, this list of conditions and the following */
/* disclaimer. */
/* */
/* 2. Redistributions in binary form must reproduce the above */
/* copyright notice, this list of conditions and the following */
/* disclaimer in the documentation and/or other materials */
/* provided with the distribution. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
/* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
/* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
/* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
/* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
/* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
/* POSSIBILITY OF SUCH DAMAGE. */
/* */
/* The views and conclusions contained in the software and */
/* documentation are those of the authors and should not be */
/* interpreted as representing official policies, either expressed */
/* or implied, of The University of Texas at Austin. */
/*********************************************************************/
#define ASSEMBLER
#include "common.h"
#ifndef WINDOWS_ABI
#define M ARG1 /* rdi */
#define N ARG2 /* rsi */
#define A ARG3 /* rdx */
#define LDA ARG4 /* rcx */
#define B ARG5 /* r8 */
#define I %r9
#define J %r10
#define AO1 %r11
#define AO2 %r12
#else
#define STACKSIZE 256
#define M ARG1 /* rcx */
#define N ARG2 /* rdx */
#define A ARG3 /* r8 */
#define LDA ARG4 /* r9 */
#define OLD_B 40 + 24 + STACKSIZE(%rsp)
#define B %r10
#define I %r11
#define J %r12
#define AO1 %r13
#define AO2 %r14
#endif
#if defined(CORE2) || defined(PENRYN) || defined(DUNNINGTON)
#define RPREFETCHSIZE 16
#define WPREFETCHSIZE 48
#endif
#if defined(PENTIUM4) || defined(GENERIC) || defined(NANO)
#define RPREFETCHSIZE 32
#define WPREFETCHSIZE 80
#endif
#ifdef OPTERON
#define RPREFETCHSIZE 32
#define WPREFETCHSIZE 48
#define movsd movlpd
#endif
#if defined(BARCELONA) || defined(SHANGHAI)
#define RPREFETCHSIZE 32
#define WPREFETCHSIZE 48
#endif
PROLOGUE
PROFCODE
#ifdef WINDOWS_ABI
pushq %r14
pushq %r13
#endif
pushq %r12
#ifdef WINDOWS_ABI
subq $STACKSIZE, %rsp
movups %xmm6, 0(%rsp)
movups %xmm7, 16(%rsp)
movups %xmm8, 32(%rsp)
movups %xmm9, 48(%rsp)
movups %xmm10, 64(%rsp)
movups %xmm11, 80(%rsp)
movups %xmm12, 96(%rsp)
movups %xmm13, 112(%rsp)
movups %xmm14, 128(%rsp)
movups %xmm15, 144(%rsp)
movq OLD_B, B
#endif
salq $ZBASE_SHIFT, LDA
movq N, J
sarq $1, J
jle .L20
ALIGN_4
.L12:
movq A, AO1
leaq (A, LDA), AO2
leaq (A, LDA, 2), A
movq M, I
sarq $2, I
jle .L14
ALIGN_4
.L13:
#ifdef HAVE_3DNOW
prefetchw (WPREFETCHSIZE + 0) * SIZE(B)
prefetchw (WPREFETCHSIZE + 8) * SIZE(B)
#endif
#ifndef DOUBLE
movlps 0 * SIZE(AO1), %xmm0
movhps 0 * SIZE(AO2), %xmm0
movlps 2 * SIZE(AO1), %xmm1
movhps 2 * SIZE(AO2), %xmm1
movlps 4 * SIZE(AO1), %xmm2
movhps 4 * SIZE(AO2), %xmm2
movlps 6 * SIZE(AO1), %xmm3
movhps 6 * SIZE(AO2), %xmm3
#if defined(PENTIUM4) || defined(GENERIC) || defined(NANO)
prefetcht0 RPREFETCHSIZE * SIZE(AO1)
prefetcht0 RPREFETCHSIZE * SIZE(AO2)
prefetcht0 WPREFETCHSIZE * SIZE(B)
#endif
movaps %xmm0, 0 * SIZE(B)
movaps %xmm1, 4 * SIZE(B)
movaps %xmm2, 8 * SIZE(B)
movaps %xmm3, 12 * SIZE(B)
#else
movsd 0 * SIZE(AO1), %xmm0
movhpd 1 * SIZE(AO1), %xmm0
movsd 0 * SIZE(AO2), %xmm1
movhpd 1 * SIZE(AO2), %xmm1
#if defined(CORE2) || defined(PENRYN) || defined(DUNNINGTON)
prefetcht2 RPREFETCHSIZE * SIZE(AO1)
#endif
movsd 2 * SIZE(AO1), %xmm2
movhpd 3 * SIZE(AO1), %xmm2
movsd 2 * SIZE(AO2), %xmm3
movhpd 3 * SIZE(AO2), %xmm3
movsd 4 * SIZE(AO1), %xmm4
movhpd 5 * SIZE(AO1), %xmm4
movsd 4 * SIZE(AO2), %xmm5
movhpd 5 * SIZE(AO2), %xmm5
#if defined(CORE2) || defined(PENRYN) || defined(DUNNINGTON)
prefetcht2 RPREFETCHSIZE * SIZE(AO2)
#endif
movsd 6 * SIZE(AO1), %xmm6
movhpd 7 * SIZE(AO1), %xmm6
movsd 6 * SIZE(AO2), %xmm7
movhpd 7 * SIZE(AO2), %xmm7
#if defined(PENTIUM4) || defined(GENERIC) || defined(NANO)
prefetcht0 RPREFETCHSIZE * SIZE(AO1)
prefetcht0 RPREFETCHSIZE * SIZE(AO2)
prefetcht0 WPREFETCHSIZE * SIZE(B)
#endif
movapd %xmm0, 0 * SIZE(B)
movapd %xmm1, 2 * SIZE(B)
movapd %xmm2, 4 * SIZE(B)
movapd %xmm3, 6 * SIZE(B)
#if defined(CORE2) || defined(PENRYN) || defined(DUNNINGTON)
prefetcht2 WPREFETCHSIZE * SIZE(B)
#endif
movapd %xmm4, 8 * SIZE(B)
movapd %xmm5, 10 * SIZE(B)
movapd %xmm6, 12 * SIZE(B)
movapd %xmm7, 14 * SIZE(B)
#endif
addq $8 * SIZE, AO1
addq $8 * SIZE, AO2
subq $-16 * SIZE, B
decq I
jg .L13
ALIGN_4
.L14:
movq M, I
andq $3, I
jle .L16
ALIGN_4
.L15:
#ifndef DOUBLE
movlps 0 * SIZE(AO1), %xmm0
movhps 0 * SIZE(AO2), %xmm0
movaps %xmm0, 0 * SIZE(B)
#else
movsd 0 * SIZE(AO1), %xmm0
movhpd 1 * SIZE(AO1), %xmm0
movsd 0 * SIZE(AO2), %xmm1
movhpd 1 * SIZE(AO2), %xmm1
movapd %xmm0, 0 * SIZE(B)
movapd %xmm1, 2 * SIZE(B)
#endif
addq $2 * SIZE, AO1
addq $2 * SIZE, AO2
addq $4 * SIZE, B
decq I
jg .L15
ALIGN_4
.L16:
decq J
jg .L12
ALIGN_4
.L20:
testq $1, N
jle .L999
movq A, AO1
movq M, I
sarq $2, I
jle .L24
ALIGN_4
.L23:
#ifdef HAVE_3DNOW
prefetchw (WPREFETCHSIZE + 0) * SIZE(B)
prefetchw (WPREFETCHSIZE + 8) * SIZE(B)
#endif
#ifndef DOUBLE
movlps 0 * SIZE(AO1), %xmm0
movhps 2 * SIZE(AO1), %xmm0
movlps 4 * SIZE(AO1), %xmm1
movhps 6 * SIZE(AO1), %xmm1
movaps %xmm0, 0 * SIZE(B)
movaps %xmm1, 4 * SIZE(B)
#else
movsd 0 * SIZE(AO1), %xmm0
movhpd 1 * SIZE(AO1), %xmm0
movsd 2 * SIZE(AO1), %xmm1
movhpd 3 * SIZE(AO1), %xmm1
movsd 4 * SIZE(AO1), %xmm2
movhpd 5 * SIZE(AO1), %xmm2
movsd 6 * SIZE(AO1), %xmm3
movhpd 7 * SIZE(AO1), %xmm3
movapd %xmm0, 0 * SIZE(B)
movapd %xmm1, 2 * SIZE(B)
movapd %xmm2, 4 * SIZE(B)
movapd %xmm3, 6 * SIZE(B)
#endif
#if defined(PENTIUM4) || defined(GENERIC) || defined(NANO)
prefetcht0 RPREFETCHSIZE * SIZE(AO1)
prefetcht0 RPREFETCHSIZE * SIZE(AO2)
prefetcht0 WPREFETCHSIZE * SIZE(B)
#endif
addq $8 * SIZE, AO1
addq $8 * SIZE, B
decq I
jg .L23
ALIGN_4
.L24:
movq M, I
andq $3, I
jle .L999
ALIGN_4
.L25:
#ifndef DOUBLE
movlps 0 * SIZE(AO1), %xmm0
movlps %xmm0, 0 * SIZE(B)
#else
movsd 0 * SIZE(AO1), %xmm0
movhpd 1 * SIZE(AO1), %xmm0
movapd %xmm0, 0 * SIZE(B)
#endif
addq $2 * SIZE, AO1
addq $2 * SIZE, B
decq I
jg .L25
ALIGN_4
.L999:
#ifdef WINDOWS_ABI
movups 0(%rsp), %xmm6
movups 16(%rsp), %xmm7
movups 32(%rsp), %xmm8
movups 48(%rsp), %xmm9
movups 64(%rsp), %xmm10
movups 80(%rsp), %xmm11
movups 96(%rsp), %xmm12
movups 112(%rsp), %xmm13
movups 128(%rsp), %xmm14
movups 144(%rsp), %xmm15
addq $STACKSIZE, %rsp
#endif
popq %r12
#ifdef WINDOWS_ABI
popq %r13
popq %r14
#endif
ret
EPILOGUE
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 -fobjc-gc -triple x86_64-apple-darwin10 -fobjc-runtime=macosx-fragile-10.5 -emit-llvm -o - %s | FileCheck %s
namespace test0 {
extern id x;
struct A {
id x;
A();
};
A::A() : x(test0::x) {}
// CHECK-LABEL: define void @_ZN5test01AC2Ev(
// CHECK: [[THIS:%.*]] = alloca [[TEST0:%.*]]*, align 8
// CHECK-NEXT: store
// CHECK-NEXT: [[T0:%.*]] = load [[TEST0]]*, [[TEST0]]** [[THIS]]
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[TEST0]], [[TEST0]]* [[T0]], i32 0, i32 0
// CHECK-NEXT: [[T2:%.*]] = load i8*, i8** @_ZN5test01xE
// CHECK-NEXT: call i8* @objc_assign_strongCast(i8* [[T2]], i8** [[T1]])
// CHECK-NEXT: ret void
}
| {
"language": "Assembly"
} |
;******************************************************************************
;* FFT transform with SSE/3DNow optimizations
;* Copyright (c) 2008 Loren Merritt
;* Copyright (c) 2011 Vitor Sessak
;*
;* This algorithm (though not any of the implementation details) is
;* based on libdjbfft by D. J. Bernstein.
;*
;* This file is part of Libav.
;*
;* Libav is free software; you can redistribute it and/or
;* modify it under the terms of the GNU Lesser General Public
;* License as published by the Free Software Foundation; either
;* version 2.1 of the License, or (at your option) any later version.
;*
;* Libav is distributed in the hope that it will be useful,
;* but WITHOUT ANY WARRANTY; without even the implied warranty of
;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
;* Lesser General Public License for more details.
;*
;* You should have received a copy of the GNU Lesser General Public
;* License along with Libav; if not, write to the Free Software
;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
;******************************************************************************
; These functions are not individually interchangeable with the C versions.
; While C takes arrays of FFTComplex, SSE/3DNow leave intermediate results
; in blocks as conventient to the vector size.
; i.e. {4x real, 4x imaginary, 4x real, ...} (or 2x respectively)
%include "libavutil/x86/x86util.asm"
%if ARCH_X86_64
%define pointer resq
%else
%define pointer resd
%endif
struc FFTContext
.nbits: resd 1
.reverse: resd 1
.revtab: pointer 1
.tmpbuf: pointer 1
.mdctsize: resd 1
.mdctbits: resd 1
.tcos: pointer 1
.tsin: pointer 1
.fftperm: pointer 1
.fftcalc: pointer 1
.imdctcalc:pointer 1
.imdcthalf:pointer 1
endstruc
SECTION_RODATA 32
%define M_SQRT1_2 0.70710678118654752440
%define M_COS_PI_1_8 0.923879532511287
%define M_COS_PI_3_8 0.38268343236509
ps_cos16_1: dd 1.0, M_COS_PI_1_8, M_SQRT1_2, M_COS_PI_3_8, 1.0, M_COS_PI_1_8, M_SQRT1_2, M_COS_PI_3_8
ps_cos16_2: dd 0, M_COS_PI_3_8, M_SQRT1_2, M_COS_PI_1_8, 0, -M_COS_PI_3_8, -M_SQRT1_2, -M_COS_PI_1_8
ps_root2: times 8 dd M_SQRT1_2
ps_root2mppm: dd -M_SQRT1_2, M_SQRT1_2, M_SQRT1_2, -M_SQRT1_2, -M_SQRT1_2, M_SQRT1_2, M_SQRT1_2, -M_SQRT1_2
ps_p1p1m1p1: dd 0, 0, 1<<31, 0, 0, 0, 1<<31, 0
perm1: dd 0x00, 0x02, 0x03, 0x01, 0x03, 0x00, 0x02, 0x01
perm2: dd 0x00, 0x01, 0x02, 0x03, 0x01, 0x00, 0x02, 0x03
ps_p1p1m1p1root2: dd 1.0, 1.0, -1.0, 1.0, M_SQRT1_2, M_SQRT1_2, M_SQRT1_2, M_SQRT1_2
ps_m1m1p1m1p1m1m1m1: dd 1<<31, 1<<31, 0, 1<<31, 0, 1<<31, 1<<31, 1<<31
ps_m1m1m1m1: times 4 dd 1<<31
ps_m1p1: dd 1<<31, 0
%assign i 16
%rep 13
cextern cos_ %+ i
%assign i i<<1
%endrep
%if ARCH_X86_64
%define pointer dq
%else
%define pointer dd
%endif
%macro IF0 1+
%endmacro
%macro IF1 1+
%1
%endmacro
SECTION .text
%macro T2_3DNOW 4 ; z0, z1, mem0, mem1
mova %1, %3
mova %2, %1
pfadd %1, %4
pfsub %2, %4
%endmacro
%macro T4_3DNOW 6 ; z0, z1, z2, z3, tmp0, tmp1
mova %5, %3
pfsub %3, %4
pfadd %5, %4 ; {t6,t5}
pxor %3, [ps_m1p1] ; {t8,t7}
mova %6, %1
movd [r0+12], %3
punpckhdq %3, [r0+8]
pfadd %1, %5 ; {r0,i0}
pfsub %6, %5 ; {r2,i2}
mova %4, %2
pfadd %2, %3 ; {r1,i1}
pfsub %4, %3 ; {r3,i3}
SWAP %3, %6
%endmacro
; in: %1 = {r0,i0,r2,i2,r4,i4,r6,i6}
; %2 = {r1,i1,r3,i3,r5,i5,r7,i7}
; %3, %4, %5 tmp
; out: %1 = {r0,r1,r2,r3,i0,i1,i2,i3}
; %2 = {r4,r5,r6,r7,i4,i5,i6,i7}
%macro T8_AVX 5
vsubps %5, %1, %2 ; v = %1 - %2
vaddps %3, %1, %2 ; w = %1 + %2
vmulps %2, %5, [ps_p1p1m1p1root2] ; v *= vals1
vpermilps %2, %2, [perm1]
vblendps %1, %2, %3, 0x33 ; q = {w1,w2,v4,v2,w5,w6,v7,v6}
vshufps %5, %3, %2, 0x4e ; r = {w3,w4,v1,v3,w7,w8,v8,v5}
vsubps %4, %5, %1 ; s = r - q
vaddps %1, %5, %1 ; u = r + q
vpermilps %1, %1, [perm2] ; k = {u1,u2,u3,u4,u6,u5,u7,u8}
vshufps %5, %4, %1, 0xbb
vshufps %3, %4, %1, 0xee
vperm2f128 %3, %3, %5, 0x13
vxorps %4, %4, [ps_m1m1p1m1p1m1m1m1] ; s *= {1,1,-1,-1,1,-1,-1,-1}
vshufps %2, %1, %4, 0xdd
vshufps %1, %1, %4, 0x88
vperm2f128 %4, %2, %1, 0x02 ; v = {k1,k3,s1,s3,k2,k4,s2,s4}
vperm2f128 %1, %1, %2, 0x13 ; w = {k6,k8,s6,s8,k5,k7,s5,s7}
vsubps %5, %1, %3
vblendps %1, %5, %1, 0x55 ; w -= {0,s7,0,k7,0,s8,0,k8}
vsubps %2, %4, %1 ; %2 = v - w
vaddps %1, %4, %1 ; %1 = v + w
%endmacro
; In SSE mode do one fft4 transforms
; in: %1={r0,i0,r2,i2} %2={r1,i1,r3,i3}
; out: %1={r0,r1,r2,r3} %2={i0,i1,i2,i3}
;
; In AVX mode do two fft4 transforms
; in: %1={r0,i0,r2,i2,r4,i4,r6,i6} %2={r1,i1,r3,i3,r5,i5,r7,i7}
; out: %1={r0,r1,r2,r3,r4,r5,r6,r7} %2={i0,i1,i2,i3,i4,i5,i6,i7}
%macro T4_SSE 3
subps %3, %1, %2 ; {t3,t4,-t8,t7}
addps %1, %1, %2 ; {t1,t2,t6,t5}
xorps %3, %3, [ps_p1p1m1p1]
shufps %2, %1, %3, 0xbe ; {t6,t5,t7,t8}
shufps %1, %1, %3, 0x44 ; {t1,t2,t3,t4}
subps %3, %1, %2 ; {r2,i2,r3,i3}
addps %1, %1, %2 ; {r0,i0,r1,i1}
shufps %2, %1, %3, 0xdd ; {i0,i1,i2,i3}
shufps %1, %1, %3, 0x88 ; {r0,r1,r2,r3}
%endmacro
; In SSE mode do one FFT8
; in: %1={r0,r1,r2,r3} %2={i0,i1,i2,i3} %3={r4,i4,r6,i6} %4={r5,i5,r7,i7}
; out: %1={r0,r1,r2,r3} %2={i0,i1,i2,i3} %1={r4,r5,r6,r7} %2={i4,i5,i6,i7}
;
; In AVX mode do two FFT8
; in: %1={r0,i0,r2,i2,r8, i8, r10,i10} %2={r1,i1,r3,i3,r9, i9, r11,i11}
; %3={r4,i4,r6,i6,r12,i12,r14,i14} %4={r5,i5,r7,i7,r13,i13,r15,i15}
; out: %1={r0,r1,r2,r3,r8, r9, r10,r11} %2={i0,i1,i2,i3,i8, i9, i10,i11}
; %3={r4,r5,r6,r7,r12,r13,r14,r15} %4={i4,i5,i6,i7,i12,i13,i14,i15}
%macro T8_SSE 6
addps %6, %3, %4 ; {t1,t2,t3,t4}
subps %3, %3, %4 ; {r5,i5,r7,i7}
shufps %4, %3, %3, 0xb1 ; {i5,r5,i7,r7}
mulps %3, %3, [ps_root2mppm] ; {-r5,i5,r7,-i7}
mulps %4, %4, [ps_root2]
addps %3, %3, %4 ; {t8,t7,ta,t9}
shufps %4, %6, %3, 0x9c ; {t1,t4,t7,ta}
shufps %6, %6, %3, 0x36 ; {t3,t2,t9,t8}
subps %3, %6, %4 ; {t6,t5,tc,tb}
addps %6, %6, %4 ; {t1,t2,t9,ta}
shufps %5, %6, %3, 0x8d ; {t2,ta,t6,tc}
shufps %6, %6, %3, 0xd8 ; {t1,t9,t5,tb}
subps %3, %1, %6 ; {r4,r5,r6,r7}
addps %1, %1, %6 ; {r0,r1,r2,r3}
subps %4, %2, %5 ; {i4,i5,i6,i7}
addps %2, %2, %5 ; {i0,i1,i2,i3}
%endmacro
%macro INTERL 5
%if cpuflag(avx)
vunpckhps %3, %2, %1
vunpcklps %2, %2, %1
vextractf128 %4(%5), %2, 0
vextractf128 %4 %+ H(%5), %3, 0
vextractf128 %4(%5 + 1), %2, 1
vextractf128 %4 %+ H(%5 + 1), %3, 1
%elif cpuflag(sse)
mova %3, %2
unpcklps %2, %1
unpckhps %3, %1
mova %4(%5), %2
mova %4(%5+1), %3
%endif
%endmacro
; scheduled for cpu-bound sizes
%macro PASS_SMALL 3 ; (to load m4-m7), wre, wim
IF%1 mova m4, Z(4)
IF%1 mova m5, Z(5)
mova m0, %2 ; wre
mova m1, %3 ; wim
mulps m2, m4, m0 ; r2*wre
IF%1 mova m6, Z2(6)
mulps m3, m5, m1 ; i2*wim
IF%1 mova m7, Z2(7)
mulps m4, m4, m1 ; r2*wim
mulps m5, m5, m0 ; i2*wre
addps m2, m2, m3 ; r2*wre + i2*wim
mulps m3, m1, m7 ; i3*wim
subps m5, m5, m4 ; i2*wre - r2*wim
mulps m1, m1, m6 ; r3*wim
mulps m4, m0, m6 ; r3*wre
mulps m0, m0, m7 ; i3*wre
subps m4, m4, m3 ; r3*wre - i3*wim
mova m3, Z(0)
addps m0, m0, m1 ; i3*wre + r3*wim
subps m1, m4, m2 ; t3
addps m4, m4, m2 ; t5
subps m3, m3, m4 ; r2
addps m4, m4, Z(0) ; r0
mova m6, Z(2)
mova Z(4), m3
mova Z(0), m4
subps m3, m5, m0 ; t4
subps m4, m6, m3 ; r3
addps m3, m3, m6 ; r1
mova Z2(6), m4
mova Z(2), m3
mova m2, Z(3)
addps m3, m5, m0 ; t6
subps m2, m2, m1 ; i3
mova m7, Z(1)
addps m1, m1, Z(3) ; i1
mova Z2(7), m2
mova Z(3), m1
subps m4, m7, m3 ; i2
addps m3, m3, m7 ; i0
mova Z(5), m4
mova Z(1), m3
%endmacro
; scheduled to avoid store->load aliasing
%macro PASS_BIG 1 ; (!interleave)
mova m4, Z(4) ; r2
mova m5, Z(5) ; i2
mova m0, [wq] ; wre
mova m1, [wq+o1q] ; wim
mulps m2, m4, m0 ; r2*wre
mova m6, Z2(6) ; r3
mulps m3, m5, m1 ; i2*wim
mova m7, Z2(7) ; i3
mulps m4, m4, m1 ; r2*wim
mulps m5, m5, m0 ; i2*wre
addps m2, m2, m3 ; r2*wre + i2*wim
mulps m3, m1, m7 ; i3*wim
mulps m1, m1, m6 ; r3*wim
subps m5, m5, m4 ; i2*wre - r2*wim
mulps m4, m0, m6 ; r3*wre
mulps m0, m0, m7 ; i3*wre
subps m4, m4, m3 ; r3*wre - i3*wim
mova m3, Z(0)
addps m0, m0, m1 ; i3*wre + r3*wim
subps m1, m4, m2 ; t3
addps m4, m4, m2 ; t5
subps m3, m3, m4 ; r2
addps m4, m4, Z(0) ; r0
mova m6, Z(2)
mova Z(4), m3
mova Z(0), m4
subps m3, m5, m0 ; t4
subps m4, m6, m3 ; r3
addps m3, m3, m6 ; r1
IF%1 mova Z2(6), m4
IF%1 mova Z(2), m3
mova m2, Z(3)
addps m5, m5, m0 ; t6
subps m2, m2, m1 ; i3
mova m7, Z(1)
addps m1, m1, Z(3) ; i1
IF%1 mova Z2(7), m2
IF%1 mova Z(3), m1
subps m6, m7, m5 ; i2
addps m5, m5, m7 ; i0
IF%1 mova Z(5), m6
IF%1 mova Z(1), m5
%if %1==0
INTERL m1, m3, m7, Z, 2
INTERL m2, m4, m0, Z2, 6
mova m1, Z(0)
mova m2, Z(4)
INTERL m5, m1, m3, Z, 0
INTERL m6, m2, m7, Z, 4
%endif
%endmacro
%macro PUNPCK 3
mova %3, %1
punpckldq %1, %2
punpckhdq %3, %2
%endmacro
%define Z(x) [r0+mmsize*x]
%define Z2(x) [r0+mmsize*x]
%define ZH(x) [r0+mmsize*x+mmsize/2]
INIT_YMM avx
align 16
fft8_avx:
mova m0, Z(0)
mova m1, Z(1)
T8_AVX m0, m1, m2, m3, m4
mova Z(0), m0
mova Z(1), m1
ret
align 16
fft16_avx:
mova m2, Z(2)
mova m3, Z(3)
T4_SSE m2, m3, m7
mova m0, Z(0)
mova m1, Z(1)
T8_AVX m0, m1, m4, m5, m7
mova m4, [ps_cos16_1]
mova m5, [ps_cos16_2]
vmulps m6, m2, m4
vmulps m7, m3, m5
vaddps m7, m7, m6
vmulps m2, m2, m5
vmulps m3, m3, m4
vsubps m3, m3, m2
vblendps m2, m7, m3, 0xf0
vperm2f128 m3, m7, m3, 0x21
vaddps m4, m2, m3
vsubps m2, m3, m2
vperm2f128 m2, m2, m2, 0x01
vsubps m3, m1, m2
vaddps m1, m1, m2
vsubps m5, m0, m4
vaddps m0, m0, m4
vextractf128 Z(0), m0, 0
vextractf128 ZH(0), m1, 0
vextractf128 Z(1), m0, 1
vextractf128 ZH(1), m1, 1
vextractf128 Z(2), m5, 0
vextractf128 ZH(2), m3, 0
vextractf128 Z(3), m5, 1
vextractf128 ZH(3), m3, 1
ret
align 16
fft32_avx:
call fft16_avx
mova m0, Z(4)
mova m1, Z(5)
T4_SSE m0, m1, m4
mova m2, Z(6)
mova m3, Z(7)
T8_SSE m0, m1, m2, m3, m4, m6
; m0={r0,r1,r2,r3,r8, r9, r10,r11} m1={i0,i1,i2,i3,i8, i9, i10,i11}
; m2={r4,r5,r6,r7,r12,r13,r14,r15} m3={i4,i5,i6,i7,i12,i13,i14,i15}
vperm2f128 m4, m0, m2, 0x20
vperm2f128 m5, m1, m3, 0x20
vperm2f128 m6, m0, m2, 0x31
vperm2f128 m7, m1, m3, 0x31
PASS_SMALL 0, [cos_32], [cos_32+32]
ret
fft32_interleave_avx:
call fft32_avx
mov r2d, 32
.deint_loop:
mova m2, Z(0)
mova m3, Z(1)
vunpcklps m0, m2, m3
vunpckhps m1, m2, m3
vextractf128 Z(0), m0, 0
vextractf128 ZH(0), m1, 0
vextractf128 Z(1), m0, 1
vextractf128 ZH(1), m1, 1
add r0, mmsize*2
sub r2d, mmsize/4
jg .deint_loop
ret
INIT_XMM sse
align 16
fft4_avx:
fft4_sse:
mova m0, Z(0)
mova m1, Z(1)
T4_SSE m0, m1, m2
mova Z(0), m0
mova Z(1), m1
ret
align 16
fft8_sse:
mova m0, Z(0)
mova m1, Z(1)
T4_SSE m0, m1, m2
mova m2, Z(2)
mova m3, Z(3)
T8_SSE m0, m1, m2, m3, m4, m5
mova Z(0), m0
mova Z(1), m1
mova Z(2), m2
mova Z(3), m3
ret
align 16
fft16_sse:
mova m0, Z(0)
mova m1, Z(1)
T4_SSE m0, m1, m2
mova m2, Z(2)
mova m3, Z(3)
T8_SSE m0, m1, m2, m3, m4, m5
mova m4, Z(4)
mova m5, Z(5)
mova Z(0), m0
mova Z(1), m1
mova Z(2), m2
mova Z(3), m3
T4_SSE m4, m5, m6
mova m6, Z2(6)
mova m7, Z2(7)
T4_SSE m6, m7, m0
PASS_SMALL 0, [cos_16], [cos_16+16]
ret
%macro FFT48_3DNOW 0
align 16
fft4 %+ SUFFIX:
T2_3DNOW m0, m1, Z(0), Z(1)
mova m2, Z(2)
mova m3, Z(3)
T4_3DNOW m0, m1, m2, m3, m4, m5
PUNPCK m0, m1, m4
PUNPCK m2, m3, m5
mova Z(0), m0
mova Z(1), m4
mova Z(2), m2
mova Z(3), m5
ret
align 16
fft8 %+ SUFFIX:
T2_3DNOW m0, m1, Z(0), Z(1)
mova m2, Z(2)
mova m3, Z(3)
T4_3DNOW m0, m1, m2, m3, m4, m5
mova Z(0), m0
mova Z(2), m2
T2_3DNOW m4, m5, Z(4), Z(5)
T2_3DNOW m6, m7, Z2(6), Z2(7)
PSWAPD m0, m5
PSWAPD m2, m7
pxor m0, [ps_m1p1]
pxor m2, [ps_m1p1]
pfsub m5, m0
pfadd m7, m2
pfmul m5, [ps_root2]
pfmul m7, [ps_root2]
T4_3DNOW m1, m3, m5, m7, m0, m2
mova Z(5), m5
mova Z2(7), m7
mova m0, Z(0)
mova m2, Z(2)
T4_3DNOW m0, m2, m4, m6, m5, m7
PUNPCK m0, m1, m5
PUNPCK m2, m3, m7
mova Z(0), m0
mova Z(1), m5
mova Z(2), m2
mova Z(3), m7
PUNPCK m4, Z(5), m5
PUNPCK m6, Z2(7), m7
mova Z(4), m4
mova Z(5), m5
mova Z2(6), m6
mova Z2(7), m7
ret
%endmacro
%if ARCH_X86_32
INIT_MMX 3dnowext
FFT48_3DNOW
INIT_MMX 3dnow
FFT48_3DNOW
%endif
%define Z(x) [zcq + o1q*(x&6) + mmsize*(x&1)]
%define Z2(x) [zcq + o3q + mmsize*(x&1)]
%define ZH(x) [zcq + o1q*(x&6) + mmsize*(x&1) + mmsize/2]
%define Z2H(x) [zcq + o3q + mmsize*(x&1) + mmsize/2]
%macro DECL_PASS 2+ ; name, payload
align 16
%1:
DEFINE_ARGS zc, w, n, o1, o3
lea o3q, [nq*3]
lea o1q, [nq*8]
shl o3q, 4
.loop:
%2
add zcq, mmsize*2
add wq, mmsize
sub nd, mmsize/8
jg .loop
rep ret
%endmacro
%macro FFT_DISPATCH 2; clobbers 5 GPRs, 8 XMMs
lea r2, [dispatch_tab%1]
mov r2, [r2 + (%2q-2)*gprsize]
%ifdef PIC
lea r3, [$$]
add r2, r3
%endif
call r2
%endmacro ; FFT_DISPATCH
INIT_YMM avx
DECL_PASS pass_avx, PASS_BIG 1
DECL_PASS pass_interleave_avx, PASS_BIG 0
cglobal fft_calc, 2,5,8
mov r3d, [r0 + FFTContext.nbits]
mov r0, r1
mov r1, r3
FFT_DISPATCH _interleave %+ SUFFIX, r1
REP_RET
INIT_XMM sse
DECL_PASS pass_sse, PASS_BIG 1
DECL_PASS pass_interleave_sse, PASS_BIG 0
%macro FFT_CALC_FUNC 0
cglobal fft_calc, 2,5,8
mov r3d, [r0 + FFTContext.nbits]
PUSH r1
PUSH r3
mov r0, r1
mov r1, r3
FFT_DISPATCH _interleave %+ SUFFIX, r1
POP rcx
POP r4
cmp rcx, 3+(mmsize/16)
jg .end
mov r2, -1
add rcx, 3
shl r2, cl
sub r4, r2
.loop:
%if mmsize == 8
PSWAPD m0, [r4 + r2 + 4]
mova [r4 + r2 + 4], m0
%else
movaps xmm0, [r4 + r2]
movaps xmm1, xmm0
unpcklps xmm0, [r4 + r2 + 16]
unpckhps xmm1, [r4 + r2 + 16]
movaps [r4 + r2], xmm0
movaps [r4 + r2 + 16], xmm1
%endif
add r2, mmsize*2
jl .loop
.end:
%if cpuflag(3dnow)
femms
RET
%else
REP_RET
%endif
%endmacro
%if ARCH_X86_32
INIT_MMX 3dnow
FFT_CALC_FUNC
INIT_MMX 3dnowext
FFT_CALC_FUNC
%endif
INIT_XMM sse
FFT_CALC_FUNC
cglobal fft_permute, 2,7,1
mov r4, [r0 + FFTContext.revtab]
mov r5, [r0 + FFTContext.tmpbuf]
mov ecx, [r0 + FFTContext.nbits]
mov r2, 1
shl r2, cl
xor r0, r0
%if ARCH_X86_32
mov r1, r1m
%endif
.loop:
movaps xmm0, [r1 + 8*r0]
movzx r6, word [r4 + 2*r0]
movzx r3, word [r4 + 2*r0 + 2]
movlps [r5 + 8*r6], xmm0
movhps [r5 + 8*r3], xmm0
add r0, 2
cmp r0, r2
jl .loop
shl r2, 3
add r1, r2
add r5, r2
neg r2
; nbits >= 2 (FFT4) and sizeof(FFTComplex)=8 => at least 32B
.loopcopy:
movaps xmm0, [r5 + r2]
movaps xmm1, [r5 + r2 + 16]
movaps [r1 + r2], xmm0
movaps [r1 + r2 + 16], xmm1
add r2, 32
jl .loopcopy
REP_RET
%if ARCH_X86_32
INIT_MMX 3dnow
%define mulps pfmul
%define addps pfadd
%define subps pfsub
%define unpcklps punpckldq
%define unpckhps punpckhdq
DECL_PASS pass_3dnow, PASS_SMALL 1, [wq], [wq+o1q]
DECL_PASS pass_interleave_3dnow, PASS_BIG 0
%define pass_3dnowext pass_3dnow
%define pass_interleave_3dnowext pass_interleave_3dnow
%endif
%ifdef PIC
%define SECTION_REL - $$
%else
%define SECTION_REL
%endif
%macro DECL_FFT 1-2 ; nbits, suffix
%ifidn %0, 1
%xdefine fullsuffix SUFFIX
%else
%xdefine fullsuffix %2 %+ SUFFIX
%endif
%xdefine list_of_fft fft4 %+ SUFFIX SECTION_REL, fft8 %+ SUFFIX SECTION_REL
%if %1>=5
%xdefine list_of_fft list_of_fft, fft16 %+ SUFFIX SECTION_REL
%endif
%if %1>=6
%xdefine list_of_fft list_of_fft, fft32 %+ fullsuffix SECTION_REL
%endif
%assign n 1<<%1
%rep 17-%1
%assign n2 n/2
%assign n4 n/4
%xdefine list_of_fft list_of_fft, fft %+ n %+ fullsuffix SECTION_REL
align 16
fft %+ n %+ fullsuffix:
call fft %+ n2 %+ SUFFIX
add r0, n*4 - (n&(-2<<%1))
call fft %+ n4 %+ SUFFIX
add r0, n*2 - (n2&(-2<<%1))
call fft %+ n4 %+ SUFFIX
sub r0, n*6 + (n2&(-2<<%1))
lea r1, [cos_ %+ n]
mov r2d, n4/2
jmp pass %+ fullsuffix
%assign n n*2
%endrep
%undef n
align 8
dispatch_tab %+ fullsuffix: pointer list_of_fft
%endmacro ; DECL_FFT
INIT_YMM avx
DECL_FFT 6
DECL_FFT 6, _interleave
INIT_XMM sse
DECL_FFT 5
DECL_FFT 5, _interleave
%if ARCH_X86_32
INIT_MMX 3dnow
DECL_FFT 4
DECL_FFT 4, _interleave
INIT_MMX 3dnowext
DECL_FFT 4
DECL_FFT 4, _interleave
%endif
%if CONFIG_MDCT
%macro IMDCT_CALC_FUNC 0
cglobal imdct_calc, 3,5,3
mov r3d, [r0 + FFTContext.mdctsize]
mov r4, [r0 + FFTContext.imdcthalf]
add r1, r3
PUSH r3
PUSH r1
%if ARCH_X86_32
push r2
push r1
push r0
%else
sub rsp, 8+32*WIN64 ; allocate win64 shadow space
%endif
call r4
%if ARCH_X86_32
add esp, 12
%else
add rsp, 8+32*WIN64
%endif
POP r1
POP r3
lea r0, [r1 + 2*r3]
mov r2, r3
sub r3, mmsize
neg r2
mova m2, [ps_m1m1m1m1]
.loop:
%if mmsize == 8
PSWAPD m0, [r1 + r3]
PSWAPD m1, [r0 + r2]
pxor m0, m2
%else
mova m0, [r1 + r3]
mova m1, [r0 + r2]
shufps m0, m0, 0x1b
shufps m1, m1, 0x1b
xorps m0, m2
%endif
mova [r0 + r3], m1
mova [r1 + r2], m0
sub r3, mmsize
add r2, mmsize
jl .loop
%if cpuflag(3dnow)
femms
RET
%else
REP_RET
%endif
%endmacro
%if ARCH_X86_32
INIT_MMX 3dnow
IMDCT_CALC_FUNC
INIT_MMX 3dnowext
IMDCT_CALC_FUNC
%endif
INIT_XMM sse
IMDCT_CALC_FUNC
INIT_XMM sse
%undef mulps
%undef addps
%undef subps
%undef unpcklps
%undef unpckhps
%macro PREROTATER 5 ;-2*k, 2*k, input+n4, tcos+n8, tsin+n8
%if mmsize == 8 ; j*2+2-n4, n4-2-j*2, input+n4, tcos+n8, tsin+n8
PSWAPD m0, [%3+%2*4]
movq m2, [%3+%1*4-8]
movq m3, m0
punpckldq m0, m2
punpckhdq m2, m3
movd m1, [%4+%1*2-4] ; tcos[j]
movd m3, [%4+%2*2] ; tcos[n4-j-1]
punpckldq m1, [%5+%1*2-4] ; tsin[j]
punpckldq m3, [%5+%2*2] ; tsin[n4-j-1]
mova m4, m0
PSWAPD m5, m1
pfmul m0, m1
pfmul m4, m5
mova m6, m2
PSWAPD m5, m3
pfmul m2, m3
pfmul m6, m5
%if cpuflag(3dnowext)
pfpnacc m0, m4
pfpnacc m2, m6
%else
SBUTTERFLY dq, 0, 4, 1
SBUTTERFLY dq, 2, 6, 3
pxor m4, m7
pxor m6, m7
pfadd m0, m4
pfadd m2, m6
%endif
%else
movaps xmm0, [%3+%2*4]
movaps xmm1, [%3+%1*4-0x10]
movaps xmm2, xmm0
shufps xmm0, xmm1, 0x88
shufps xmm1, xmm2, 0x77
movlps xmm4, [%4+%2*2]
movlps xmm5, [%5+%2*2+0x0]
movhps xmm4, [%4+%1*2-0x8]
movhps xmm5, [%5+%1*2-0x8]
movaps xmm2, xmm0
movaps xmm3, xmm1
mulps xmm0, xmm5
mulps xmm1, xmm4
mulps xmm2, xmm4
mulps xmm3, xmm5
subps xmm1, xmm0
addps xmm2, xmm3
movaps xmm0, xmm1
unpcklps xmm1, xmm2
unpckhps xmm0, xmm2
%endif
%endmacro
%macro CMUL 6 ;j, xmm0, xmm1, 3, 4, 5
%if cpuflag(sse)
mulps m6, %3, [%5+%1]
mulps m7, %2, [%5+%1]
mulps %2, %2, [%6+%1]
mulps %3, %3, [%6+%1]
subps %2, %2, m6
addps %3, %3, m7
%elif cpuflag(3dnow)
mova m6, [%1+%2*2]
mova %3, [%1+%2*2+8]
mova %4, m6
mova m7, %3
pfmul m6, [%5+%2]
pfmul %3, [%6+%2]
pfmul %4, [%6+%2]
pfmul m7, [%5+%2]
pfsub %3, m6
pfadd %4, m7
%endif
%endmacro
%macro POSROTATESHUF 5 ;j, k, z+n8, tcos+n8, tsin+n8
.post:
%if cpuflag(avx)
vmovaps ymm1, [%3+%1*2]
vmovaps ymm0, [%3+%1*2+0x20]
vmovaps ymm3, [%3+%2*2]
vmovaps ymm2, [%3+%2*2+0x20]
CMUL %1, ymm0, ymm1, %3, %4, %5
CMUL %2, ymm2, ymm3, %3, %4, %5
vshufps ymm1, ymm1, ymm1, 0x1b
vshufps ymm3, ymm3, ymm3, 0x1b
vperm2f128 ymm1, ymm1, ymm1, 0x01
vperm2f128 ymm3, ymm3, ymm3, 0x01
vunpcklps ymm6, ymm2, ymm1
vunpckhps ymm4, ymm2, ymm1
vunpcklps ymm7, ymm0, ymm3
vunpckhps ymm5, ymm0, ymm3
vextractf128 [%3+%1*2], ymm7, 0
vextractf128 [%3+%1*2+0x10], ymm5, 0
vextractf128 [%3+%1*2+0x20], ymm7, 1
vextractf128 [%3+%1*2+0x30], ymm5, 1
vextractf128 [%3+%2*2], ymm6, 0
vextractf128 [%3+%2*2+0x10], ymm4, 0
vextractf128 [%3+%2*2+0x20], ymm6, 1
vextractf128 [%3+%2*2+0x30], ymm4, 1
sub %2, 0x20
add %1, 0x20
jl .post
%elif cpuflag(sse)
movaps xmm1, [%3+%1*2]
movaps xmm0, [%3+%1*2+0x10]
CMUL %1, xmm0, xmm1, %3, %4, %5
movaps xmm5, [%3+%2*2]
movaps xmm4, [%3+%2*2+0x10]
CMUL %2, xmm4, xmm5, %3, %4, %5
shufps xmm1, xmm1, 0x1b
shufps xmm5, xmm5, 0x1b
movaps xmm6, xmm4
unpckhps xmm4, xmm1
unpcklps xmm6, xmm1
movaps xmm2, xmm0
unpcklps xmm0, xmm5
unpckhps xmm2, xmm5
movaps [%3+%2*2], xmm6
movaps [%3+%2*2+0x10], xmm4
movaps [%3+%1*2], xmm0
movaps [%3+%1*2+0x10], xmm2
sub %2, 0x10
add %1, 0x10
jl .post
%elif cpuflag(3dnow)
CMUL %3, %1, m0, m1, %4, %5
CMUL %3, %2, m2, m3, %4, %5
movd [%3+%1*2+ 0], m0
movd [%3+%2*2+12], m1
movd [%3+%2*2+ 0], m2
movd [%3+%1*2+12], m3
psrlq m0, 32
psrlq m1, 32
psrlq m2, 32
psrlq m3, 32
movd [%3+%1*2+ 8], m0
movd [%3+%2*2+ 4], m1
movd [%3+%2*2+ 8], m2
movd [%3+%1*2+ 4], m3
sub %2, 8
add %1, 8
jl .post
%endif
%endmacro
%macro DECL_IMDCT 0
cglobal imdct_half, 3,12,8; FFTContext *s, FFTSample *output, const FFTSample *input
%if ARCH_X86_64
%define rrevtab r7
%define rtcos r8
%define rtsin r9
%else
%define rrevtab r6
%define rtsin r6
%define rtcos r5
%endif
mov r3d, [r0+FFTContext.mdctsize]
add r2, r3
shr r3, 1
mov rtcos, [r0+FFTContext.tcos]
mov rtsin, [r0+FFTContext.tsin]
add rtcos, r3
add rtsin, r3
%if ARCH_X86_64 == 0
push rtcos
push rtsin
%endif
shr r3, 1
mov rrevtab, [r0+FFTContext.revtab]
add rrevtab, r3
%if ARCH_X86_64 == 0
push rrevtab
%endif
%if mmsize == 8
sub r3, 2
%else
sub r3, 4
%endif
%if ARCH_X86_64 || mmsize == 8
xor r4, r4
sub r4, r3
%endif
%if notcpuflag(3dnowext) && mmsize == 8
movd m7, [ps_m1m1m1m1]
%endif
.pre:
%if ARCH_X86_64 == 0
;unspill
%if mmsize != 8
xor r4, r4
sub r4, r3
%endif
mov rtcos, [esp+8]
mov rtsin, [esp+4]
%endif
PREROTATER r4, r3, r2, rtcos, rtsin
%if mmsize == 8
mov r6, [esp] ; rrevtab = ptr+n8
movzx r5, word [rrevtab+r4-2] ; rrevtab[j]
movzx r6, word [rrevtab+r3] ; rrevtab[n4-j-1]
mova [r1+r5*8], m0
mova [r1+r6*8], m2
add r4, 2
sub r3, 2
%else
%if ARCH_X86_64
movzx r5, word [rrevtab+r4-4]
movzx r6, word [rrevtab+r4-2]
movzx r10, word [rrevtab+r3]
movzx r11, word [rrevtab+r3+2]
movlps [r1+r5 *8], xmm0
movhps [r1+r6 *8], xmm0
movlps [r1+r10*8], xmm1
movhps [r1+r11*8], xmm1
add r4, 4
%else
mov r6, [esp]
movzx r5, word [r6+r4-4]
movzx r4, word [r6+r4-2]
movlps [r1+r5*8], xmm0
movhps [r1+r4*8], xmm0
movzx r5, word [r6+r3]
movzx r4, word [r6+r3+2]
movlps [r1+r5*8], xmm1
movhps [r1+r4*8], xmm1
%endif
sub r3, 4
%endif
jns .pre
mov r5, r0
mov r6, r1
mov r0, r1
mov r1d, [r5+FFTContext.nbits]
FFT_DISPATCH SUFFIX, r1
mov r0d, [r5+FFTContext.mdctsize]
add r6, r0
shr r0, 1
%if ARCH_X86_64 == 0
%define rtcos r2
%define rtsin r3
mov rtcos, [esp+8]
mov rtsin, [esp+4]
%endif
neg r0
mov r1, -mmsize
sub r1, r0
POSROTATESHUF r0, r1, r6, rtcos, rtsin
%if ARCH_X86_64 == 0
add esp, 12
%endif
%if mmsize == 8
femms
%endif
RET
%endmacro
DECL_IMDCT
%if ARCH_X86_32
INIT_MMX 3dnow
DECL_IMDCT
INIT_MMX 3dnowext
DECL_IMDCT
%endif
INIT_YMM avx
DECL_IMDCT
%endif ; CONFIG_MDCT
| {
"language": "Assembly"
} |
### FILE="Main.annotation"
# Copyright: Public domain.
# Filename: SUM-CHECK_END_OF_RECORD_MARKS.agc
# Purpose: Part of the source code for Solarium build 55. This
# is for the Command Module's (CM) Apollo Guidance
# Computer (AGC), for Apollo 4.
# Assembler: yaYUL --block1
# Contact: Jim Lawton <jim DOT lawton AT gmail DOT com>
# Website: www.ibiblio.org/apollo/index.html
# Page scans: www.ibiblio.org/apollo/ScansForConversion/Solarium055/
# Mod history: 2009-09-15 JL Created.
## Page 759
# EACH VALID BANK MUST HAVE AN EOR CONSISTING OF TWO TC SELF WORDS TO
# SIGNIFY THE END OF GOOD PARITY DATA.
BANK 1
TC
TC
BANK 2
TC
TC
BANK 3
TC
TC
BANK 4
TC
TC
BANK 5
TC
TC
BANK 6
TC
TC
BANK 7
TC
TC
BANK 10
TC
TC
BANK 11
TC
TC
BANK 12
TC
## Page 760
TC
TC
BANK 13
TC
TC
BANK 14
TC
TC
BANK 21
TC
TC
BANK 22
TC
TC
BANK 23
TC
TC
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## Page 761
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# END OF REVISION 0 OF PROGRAM SOLRUM55 BY NASA 1021108-021 LAST ASSEMBLED ON NOV 26, 1966
| {
"language": "Assembly"
} |
# RUN: not llvm-mc -triple i386-unknown-unknown < %s 2>&1 | FileCheck %s
add $1\@, %eax
# CHECK: :[[@LINE-1]]:8: error: unexpected token in argument list
.macro A @
mov %eax, %eax
.endm
# CHECK: :[[@LINE-3]]:10: error: expected identifier in '.macro' directive
.rept 2
addi $8, $8, \@
.endr
# CHECK: error: unknown token in expression
# CHECK: :[[@LINE-4]]:1: note: while in macro instantiation
# CHECK-NEXT: .rept 2
.rep 3
addi $9, $9, \@
.endr
# CHECK: error: unknown token in expression
# CHECK: :[[@LINE-4]]:1: note: while in macro instantiation
# CHECK-NEXT: .rep 3
| {
"language": "Assembly"
} |
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
; CHECK: vpunpcklbw %xmm
; CHECK-NEXT: vpunpckhbw %xmm
; CHECK-NEXT: vpshufd $85
; CHECK-NEXT: vinsertf128 $1
define <32 x i8> @funcA(<32 x i8> %a) nounwind uwtable readnone ssp {
entry:
%shuffle = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
ret <32 x i8> %shuffle
}
; CHECK: vpunpckhwd %xmm
; CHECK-NEXT: vpshufd $85
; CHECK-NEXT: vinsertf128 $1
define <16 x i16> @funcB(<16 x i16> %a) nounwind uwtable readnone ssp {
entry:
%shuffle = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
ret <16 x i16> %shuffle
}
; CHECK: vmovq
; CHECK-NEXT: vmovlhps %xmm
; CHECK-NEXT: vinsertf128 $1
define <4 x i64> @funcC(i64 %q) nounwind uwtable readnone ssp {
entry:
%vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
%vecinit2.i = insertelement <4 x i64> %vecinit.i, i64 %q, i32 1
%vecinit4.i = insertelement <4 x i64> %vecinit2.i, i64 %q, i32 2
%vecinit6.i = insertelement <4 x i64> %vecinit4.i, i64 %q, i32 3
ret <4 x i64> %vecinit6.i
}
; CHECK: vpermilpd $0
; CHECK-NEXT: vinsertf128 $1
define <4 x double> @funcD(double %q) nounwind uwtable readnone ssp {
entry:
%vecinit.i = insertelement <4 x double> undef, double %q, i32 0
%vecinit2.i = insertelement <4 x double> %vecinit.i, double %q, i32 1
%vecinit4.i = insertelement <4 x double> %vecinit2.i, double %q, i32 2
%vecinit6.i = insertelement <4 x double> %vecinit4.i, double %q, i32 3
ret <4 x double> %vecinit6.i
}
; Test this simple opt:
; shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
; To:
; shuffle (vload ptr)), undef, <1, 1, 1, 1>
; CHECK: vmovdqa
; CHECK-NEXT: vpshufd $-1
; CHECK-NEXT: vinsertf128 $1
define <8 x float> @funcE() nounwind {
allocas:
%udx495 = alloca [18 x [18 x float]], align 32
br label %for_test505.preheader
for_test505.preheader: ; preds = %for_test505.preheader, %allocas
br i1 undef, label %for_exit499, label %for_test505.preheader
for_exit499: ; preds = %for_test505.preheader
br i1 undef, label %__load_and_broadcast_32.exit1249, label %load.i1247
load.i1247: ; preds = %for_exit499
%ptr1227 = getelementptr [18 x [18 x float]]* %udx495, i64 0, i64 1, i64 1
%ptr.i1237 = bitcast float* %ptr1227 to i32*
%val.i1238 = load i32* %ptr.i1237, align 4
%ret6.i1245 = insertelement <8 x i32> undef, i32 %val.i1238, i32 6
%ret7.i1246 = insertelement <8 x i32> %ret6.i1245, i32 %val.i1238, i32 7
%phitmp = bitcast <8 x i32> %ret7.i1246 to <8 x float>
br label %__load_and_broadcast_32.exit1249
__load_and_broadcast_32.exit1249: ; preds = %load.i1247, %for_exit499
%load_broadcast12281250 = phi <8 x float> [ %phitmp, %load.i1247 ], [ undef, %for_exit499 ]
ret <8 x float> %load_broadcast12281250
}
; CHECK: vpshufd $0
; CHECK-NEXT: vinsertf128 $1
define <8 x float> @funcF(i32 %val) nounwind {
%ret6 = insertelement <8 x i32> undef, i32 %val, i32 6
%ret7 = insertelement <8 x i32> %ret6, i32 %val, i32 7
%tmp = bitcast <8 x i32> %ret7 to <8 x float>
ret <8 x float> %tmp
}
; CHECK: vpshufd $0
; CHECK-NEXT: vinsertf128 $1
define <8 x float> @funcG(<8 x float> %a) nounwind uwtable readnone ssp {
entry:
%shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x float> %shuffle
}
; CHECK: vextractf128 $1
; CHECK-NEXT: vpshufd
; CHECK-NEXT: vinsertf128 $1
define <8 x float> @funcH(<8 x float> %a) nounwind uwtable readnone ssp {
entry:
%shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
ret <8 x float> %shuffle
}
| {
"language": "Assembly"
} |
;------------------------------------------------------------------------------
;
; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
;
; InterlockedCompareExchange64.Asm
;
; Abstract:
;
; InterlockedCompareExchange64 function
;
; Notes:
;
;------------------------------------------------------------------------------
DEFAULT REL
SECTION .text
;------------------------------------------------------------------------------
; UINT64
; EFIAPI
; InternalSyncCompareExchange64 (
; IN volatile UINT64 *Value,
; IN UINT64 CompareValue,
; IN UINT64 ExchangeValue
; );
;------------------------------------------------------------------------------
global ASM_PFX(InternalSyncCompareExchange64)
ASM_PFX(InternalSyncCompareExchange64):
mov rax, rdx
lock cmpxchg [rcx], r8
ret
| {
"language": "Assembly"
} |
// RUN: not llvm-mc -triple aarch64--none-eabi -filetype obj < %s -o /dev/null 2>&1 | FileCheck %s
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup value out of range
adr x0, distant
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup value out of range
ldr x0, distant
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup not sufficiently aligned
ldr x0, unaligned
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup value out of range
b.eq distant
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup not sufficiently aligned
b.eq unaligned
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup value out of range
ldr x0, [x1, distant-.]
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup must be 8-byte aligned
ldr x0, [x1, unaligned-.]
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup value out of range
ldr w0, [x1, distant-.]
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup must be 4-byte aligned
ldr w0, [x1, unaligned-.]
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup value out of range
ldrh w0, [x1, distant-.]
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup must be 2-byte aligned
ldrh w0, [x1, unaligned-.]
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup value out of range
ldrb w0, [x1, distant-.]
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup value out of range
ldr q0, [x1, distant-.]
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup must be 16-byte aligned
ldr q0, [x1, unaligned-.]
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup value out of range
tbz x0, #1, distant
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup not sufficiently aligned
tbz x0, #1, unaligned
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup value out of range
b distant
// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: fixup not sufficiently aligned
b unaligned
.byte 0
unaligned:
.byte 0
.space 1<<27
.balign 8
distant:
.word 0
| {
"language": "Assembly"
} |
// Copyright 2012 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// This code was translated into a form compatible with 6a from the public
// domain sources in SUPERCOP: https://bench.cr.yp.to/supercop.html
// +build amd64,!gccgo,!appengine
#include "const_amd64.h"
// func ladderstep(inout *[5][5]uint64)
TEXT ·ladderstep(SB),0,$296-8
MOVQ inout+0(FP),DI
MOVQ 40(DI),SI
MOVQ 48(DI),DX
MOVQ 56(DI),CX
MOVQ 64(DI),R8
MOVQ 72(DI),R9
MOVQ SI,AX
MOVQ DX,R10
MOVQ CX,R11
MOVQ R8,R12
MOVQ R9,R13
ADDQ ·_2P0(SB),AX
ADDQ ·_2P1234(SB),R10
ADDQ ·_2P1234(SB),R11
ADDQ ·_2P1234(SB),R12
ADDQ ·_2P1234(SB),R13
ADDQ 80(DI),SI
ADDQ 88(DI),DX
ADDQ 96(DI),CX
ADDQ 104(DI),R8
ADDQ 112(DI),R9
SUBQ 80(DI),AX
SUBQ 88(DI),R10
SUBQ 96(DI),R11
SUBQ 104(DI),R12
SUBQ 112(DI),R13
MOVQ SI,0(SP)
MOVQ DX,8(SP)
MOVQ CX,16(SP)
MOVQ R8,24(SP)
MOVQ R9,32(SP)
MOVQ AX,40(SP)
MOVQ R10,48(SP)
MOVQ R11,56(SP)
MOVQ R12,64(SP)
MOVQ R13,72(SP)
MOVQ 40(SP),AX
MULQ 40(SP)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 40(SP),AX
SHLQ $1,AX
MULQ 48(SP)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 40(SP),AX
SHLQ $1,AX
MULQ 56(SP)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 40(SP),AX
SHLQ $1,AX
MULQ 64(SP)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 40(SP),AX
SHLQ $1,AX
MULQ 72(SP)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 48(SP),AX
MULQ 48(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 48(SP),AX
SHLQ $1,AX
MULQ 56(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 48(SP),AX
SHLQ $1,AX
MULQ 64(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 48(SP),DX
IMUL3Q $38,DX,AX
MULQ 72(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 56(SP),AX
MULQ 56(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 56(SP),DX
IMUL3Q $38,DX,AX
MULQ 64(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 56(SP),DX
IMUL3Q $38,DX,AX
MULQ 72(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 64(SP),DX
IMUL3Q $19,DX,AX
MULQ 64(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 64(SP),DX
IMUL3Q $38,DX,AX
MULQ 72(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 72(SP),DX
IMUL3Q $19,DX,AX
MULQ 72(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ $REDMASK51,DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
ANDQ DX,SI
MOVQ CX,R8
SHRQ $51,CX
ADDQ R10,CX
ANDQ DX,R8
MOVQ CX,R9
SHRQ $51,CX
ADDQ R12,CX
ANDQ DX,R9
MOVQ CX,AX
SHRQ $51,CX
ADDQ R14,CX
ANDQ DX,AX
MOVQ CX,R10
SHRQ $51,CX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,80(SP)
MOVQ R8,88(SP)
MOVQ R9,96(SP)
MOVQ AX,104(SP)
MOVQ R10,112(SP)
MOVQ 0(SP),AX
MULQ 0(SP)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 0(SP),AX
SHLQ $1,AX
MULQ 8(SP)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 0(SP),AX
SHLQ $1,AX
MULQ 16(SP)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 0(SP),AX
SHLQ $1,AX
MULQ 24(SP)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 0(SP),AX
SHLQ $1,AX
MULQ 32(SP)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 8(SP),AX
MULQ 8(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 8(SP),AX
SHLQ $1,AX
MULQ 16(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 8(SP),AX
SHLQ $1,AX
MULQ 24(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 8(SP),DX
IMUL3Q $38,DX,AX
MULQ 32(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 16(SP),AX
MULQ 16(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 16(SP),DX
IMUL3Q $38,DX,AX
MULQ 24(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 16(SP),DX
IMUL3Q $38,DX,AX
MULQ 32(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 24(SP),DX
IMUL3Q $19,DX,AX
MULQ 24(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 24(SP),DX
IMUL3Q $38,DX,AX
MULQ 32(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 32(SP),DX
IMUL3Q $19,DX,AX
MULQ 32(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ $REDMASK51,DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
ANDQ DX,SI
MOVQ CX,R8
SHRQ $51,CX
ADDQ R10,CX
ANDQ DX,R8
MOVQ CX,R9
SHRQ $51,CX
ADDQ R12,CX
ANDQ DX,R9
MOVQ CX,AX
SHRQ $51,CX
ADDQ R14,CX
ANDQ DX,AX
MOVQ CX,R10
SHRQ $51,CX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,120(SP)
MOVQ R8,128(SP)
MOVQ R9,136(SP)
MOVQ AX,144(SP)
MOVQ R10,152(SP)
MOVQ SI,SI
MOVQ R8,DX
MOVQ R9,CX
MOVQ AX,R8
MOVQ R10,R9
ADDQ ·_2P0(SB),SI
ADDQ ·_2P1234(SB),DX
ADDQ ·_2P1234(SB),CX
ADDQ ·_2P1234(SB),R8
ADDQ ·_2P1234(SB),R9
SUBQ 80(SP),SI
SUBQ 88(SP),DX
SUBQ 96(SP),CX
SUBQ 104(SP),R8
SUBQ 112(SP),R9
MOVQ SI,160(SP)
MOVQ DX,168(SP)
MOVQ CX,176(SP)
MOVQ R8,184(SP)
MOVQ R9,192(SP)
MOVQ 120(DI),SI
MOVQ 128(DI),DX
MOVQ 136(DI),CX
MOVQ 144(DI),R8
MOVQ 152(DI),R9
MOVQ SI,AX
MOVQ DX,R10
MOVQ CX,R11
MOVQ R8,R12
MOVQ R9,R13
ADDQ ·_2P0(SB),AX
ADDQ ·_2P1234(SB),R10
ADDQ ·_2P1234(SB),R11
ADDQ ·_2P1234(SB),R12
ADDQ ·_2P1234(SB),R13
ADDQ 160(DI),SI
ADDQ 168(DI),DX
ADDQ 176(DI),CX
ADDQ 184(DI),R8
ADDQ 192(DI),R9
SUBQ 160(DI),AX
SUBQ 168(DI),R10
SUBQ 176(DI),R11
SUBQ 184(DI),R12
SUBQ 192(DI),R13
MOVQ SI,200(SP)
MOVQ DX,208(SP)
MOVQ CX,216(SP)
MOVQ R8,224(SP)
MOVQ R9,232(SP)
MOVQ AX,240(SP)
MOVQ R10,248(SP)
MOVQ R11,256(SP)
MOVQ R12,264(SP)
MOVQ R13,272(SP)
MOVQ 224(SP),SI
IMUL3Q $19,SI,AX
MOVQ AX,280(SP)
MULQ 56(SP)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 232(SP),DX
IMUL3Q $19,DX,AX
MOVQ AX,288(SP)
MULQ 48(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 200(SP),AX
MULQ 40(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 200(SP),AX
MULQ 48(SP)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 200(SP),AX
MULQ 56(SP)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 200(SP),AX
MULQ 64(SP)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 200(SP),AX
MULQ 72(SP)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 208(SP),AX
MULQ 40(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 208(SP),AX
MULQ 48(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 208(SP),AX
MULQ 56(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 208(SP),AX
MULQ 64(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 208(SP),DX
IMUL3Q $19,DX,AX
MULQ 72(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 216(SP),AX
MULQ 40(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 216(SP),AX
MULQ 48(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 216(SP),AX
MULQ 56(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 216(SP),DX
IMUL3Q $19,DX,AX
MULQ 64(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 216(SP),DX
IMUL3Q $19,DX,AX
MULQ 72(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 224(SP),AX
MULQ 40(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 224(SP),AX
MULQ 48(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 280(SP),AX
MULQ 64(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 280(SP),AX
MULQ 72(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 232(SP),AX
MULQ 40(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 288(SP),AX
MULQ 56(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 288(SP),AX
MULQ 64(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 288(SP),AX
MULQ 72(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ $REDMASK51,DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
MOVQ CX,R8
SHRQ $51,CX
ANDQ DX,SI
ADDQ R10,CX
MOVQ CX,R9
SHRQ $51,CX
ANDQ DX,R8
ADDQ R12,CX
MOVQ CX,AX
SHRQ $51,CX
ANDQ DX,R9
ADDQ R14,CX
MOVQ CX,R10
SHRQ $51,CX
ANDQ DX,AX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,40(SP)
MOVQ R8,48(SP)
MOVQ R9,56(SP)
MOVQ AX,64(SP)
MOVQ R10,72(SP)
MOVQ 264(SP),SI
IMUL3Q $19,SI,AX
MOVQ AX,200(SP)
MULQ 16(SP)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 272(SP),DX
IMUL3Q $19,DX,AX
MOVQ AX,208(SP)
MULQ 8(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 240(SP),AX
MULQ 0(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 240(SP),AX
MULQ 8(SP)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 240(SP),AX
MULQ 16(SP)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 240(SP),AX
MULQ 24(SP)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 240(SP),AX
MULQ 32(SP)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 248(SP),AX
MULQ 0(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 248(SP),AX
MULQ 8(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 248(SP),AX
MULQ 16(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 248(SP),AX
MULQ 24(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 248(SP),DX
IMUL3Q $19,DX,AX
MULQ 32(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 256(SP),AX
MULQ 0(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 256(SP),AX
MULQ 8(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 256(SP),AX
MULQ 16(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 256(SP),DX
IMUL3Q $19,DX,AX
MULQ 24(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 256(SP),DX
IMUL3Q $19,DX,AX
MULQ 32(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 264(SP),AX
MULQ 0(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 264(SP),AX
MULQ 8(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 200(SP),AX
MULQ 24(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 200(SP),AX
MULQ 32(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 272(SP),AX
MULQ 0(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 208(SP),AX
MULQ 16(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 208(SP),AX
MULQ 24(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 208(SP),AX
MULQ 32(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ $REDMASK51,DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
MOVQ CX,R8
SHRQ $51,CX
ANDQ DX,SI
ADDQ R10,CX
MOVQ CX,R9
SHRQ $51,CX
ANDQ DX,R8
ADDQ R12,CX
MOVQ CX,AX
SHRQ $51,CX
ANDQ DX,R9
ADDQ R14,CX
MOVQ CX,R10
SHRQ $51,CX
ANDQ DX,AX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,DX
MOVQ R8,CX
MOVQ R9,R11
MOVQ AX,R12
MOVQ R10,R13
ADDQ ·_2P0(SB),DX
ADDQ ·_2P1234(SB),CX
ADDQ ·_2P1234(SB),R11
ADDQ ·_2P1234(SB),R12
ADDQ ·_2P1234(SB),R13
ADDQ 40(SP),SI
ADDQ 48(SP),R8
ADDQ 56(SP),R9
ADDQ 64(SP),AX
ADDQ 72(SP),R10
SUBQ 40(SP),DX
SUBQ 48(SP),CX
SUBQ 56(SP),R11
SUBQ 64(SP),R12
SUBQ 72(SP),R13
MOVQ SI,120(DI)
MOVQ R8,128(DI)
MOVQ R9,136(DI)
MOVQ AX,144(DI)
MOVQ R10,152(DI)
MOVQ DX,160(DI)
MOVQ CX,168(DI)
MOVQ R11,176(DI)
MOVQ R12,184(DI)
MOVQ R13,192(DI)
MOVQ 120(DI),AX
MULQ 120(DI)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 120(DI),AX
SHLQ $1,AX
MULQ 128(DI)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 120(DI),AX
SHLQ $1,AX
MULQ 136(DI)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 120(DI),AX
SHLQ $1,AX
MULQ 144(DI)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 120(DI),AX
SHLQ $1,AX
MULQ 152(DI)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 128(DI),AX
MULQ 128(DI)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 128(DI),AX
SHLQ $1,AX
MULQ 136(DI)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 128(DI),AX
SHLQ $1,AX
MULQ 144(DI)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 128(DI),DX
IMUL3Q $38,DX,AX
MULQ 152(DI)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 136(DI),AX
MULQ 136(DI)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 136(DI),DX
IMUL3Q $38,DX,AX
MULQ 144(DI)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 136(DI),DX
IMUL3Q $38,DX,AX
MULQ 152(DI)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 144(DI),DX
IMUL3Q $19,DX,AX
MULQ 144(DI)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 144(DI),DX
IMUL3Q $38,DX,AX
MULQ 152(DI)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 152(DI),DX
IMUL3Q $19,DX,AX
MULQ 152(DI)
ADDQ AX,R12
ADCQ DX,R13
MOVQ $REDMASK51,DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
ANDQ DX,SI
MOVQ CX,R8
SHRQ $51,CX
ADDQ R10,CX
ANDQ DX,R8
MOVQ CX,R9
SHRQ $51,CX
ADDQ R12,CX
ANDQ DX,R9
MOVQ CX,AX
SHRQ $51,CX
ADDQ R14,CX
ANDQ DX,AX
MOVQ CX,R10
SHRQ $51,CX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,120(DI)
MOVQ R8,128(DI)
MOVQ R9,136(DI)
MOVQ AX,144(DI)
MOVQ R10,152(DI)
MOVQ 160(DI),AX
MULQ 160(DI)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 160(DI),AX
SHLQ $1,AX
MULQ 168(DI)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 160(DI),AX
SHLQ $1,AX
MULQ 176(DI)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 160(DI),AX
SHLQ $1,AX
MULQ 184(DI)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 160(DI),AX
SHLQ $1,AX
MULQ 192(DI)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 168(DI),AX
MULQ 168(DI)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 168(DI),AX
SHLQ $1,AX
MULQ 176(DI)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 168(DI),AX
SHLQ $1,AX
MULQ 184(DI)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 168(DI),DX
IMUL3Q $38,DX,AX
MULQ 192(DI)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 176(DI),AX
MULQ 176(DI)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 176(DI),DX
IMUL3Q $38,DX,AX
MULQ 184(DI)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 176(DI),DX
IMUL3Q $38,DX,AX
MULQ 192(DI)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 184(DI),DX
IMUL3Q $19,DX,AX
MULQ 184(DI)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 184(DI),DX
IMUL3Q $38,DX,AX
MULQ 192(DI)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 192(DI),DX
IMUL3Q $19,DX,AX
MULQ 192(DI)
ADDQ AX,R12
ADCQ DX,R13
MOVQ $REDMASK51,DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
ANDQ DX,SI
MOVQ CX,R8
SHRQ $51,CX
ADDQ R10,CX
ANDQ DX,R8
MOVQ CX,R9
SHRQ $51,CX
ADDQ R12,CX
ANDQ DX,R9
MOVQ CX,AX
SHRQ $51,CX
ADDQ R14,CX
ANDQ DX,AX
MOVQ CX,R10
SHRQ $51,CX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,160(DI)
MOVQ R8,168(DI)
MOVQ R9,176(DI)
MOVQ AX,184(DI)
MOVQ R10,192(DI)
MOVQ 184(DI),SI
IMUL3Q $19,SI,AX
MOVQ AX,0(SP)
MULQ 16(DI)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 192(DI),DX
IMUL3Q $19,DX,AX
MOVQ AX,8(SP)
MULQ 8(DI)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 160(DI),AX
MULQ 0(DI)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 160(DI),AX
MULQ 8(DI)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 160(DI),AX
MULQ 16(DI)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 160(DI),AX
MULQ 24(DI)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 160(DI),AX
MULQ 32(DI)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 168(DI),AX
MULQ 0(DI)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 168(DI),AX
MULQ 8(DI)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 168(DI),AX
MULQ 16(DI)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 168(DI),AX
MULQ 24(DI)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 168(DI),DX
IMUL3Q $19,DX,AX
MULQ 32(DI)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 176(DI),AX
MULQ 0(DI)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 176(DI),AX
MULQ 8(DI)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 176(DI),AX
MULQ 16(DI)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 176(DI),DX
IMUL3Q $19,DX,AX
MULQ 24(DI)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 176(DI),DX
IMUL3Q $19,DX,AX
MULQ 32(DI)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 184(DI),AX
MULQ 0(DI)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 184(DI),AX
MULQ 8(DI)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 0(SP),AX
MULQ 24(DI)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 0(SP),AX
MULQ 32(DI)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 192(DI),AX
MULQ 0(DI)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 8(SP),AX
MULQ 16(DI)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 8(SP),AX
MULQ 24(DI)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 8(SP),AX
MULQ 32(DI)
ADDQ AX,R12
ADCQ DX,R13
MOVQ $REDMASK51,DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
MOVQ CX,R8
SHRQ $51,CX
ANDQ DX,SI
ADDQ R10,CX
MOVQ CX,R9
SHRQ $51,CX
ANDQ DX,R8
ADDQ R12,CX
MOVQ CX,AX
SHRQ $51,CX
ANDQ DX,R9
ADDQ R14,CX
MOVQ CX,R10
SHRQ $51,CX
ANDQ DX,AX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,160(DI)
MOVQ R8,168(DI)
MOVQ R9,176(DI)
MOVQ AX,184(DI)
MOVQ R10,192(DI)
MOVQ 144(SP),SI
IMUL3Q $19,SI,AX
MOVQ AX,0(SP)
MULQ 96(SP)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 152(SP),DX
IMUL3Q $19,DX,AX
MOVQ AX,8(SP)
MULQ 88(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 120(SP),AX
MULQ 80(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 120(SP),AX
MULQ 88(SP)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 120(SP),AX
MULQ 96(SP)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 120(SP),AX
MULQ 104(SP)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 120(SP),AX
MULQ 112(SP)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 128(SP),AX
MULQ 80(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 128(SP),AX
MULQ 88(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 128(SP),AX
MULQ 96(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 128(SP),AX
MULQ 104(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 128(SP),DX
IMUL3Q $19,DX,AX
MULQ 112(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 136(SP),AX
MULQ 80(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 136(SP),AX
MULQ 88(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 136(SP),AX
MULQ 96(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 136(SP),DX
IMUL3Q $19,DX,AX
MULQ 104(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 136(SP),DX
IMUL3Q $19,DX,AX
MULQ 112(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 144(SP),AX
MULQ 80(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 144(SP),AX
MULQ 88(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 0(SP),AX
MULQ 104(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 0(SP),AX
MULQ 112(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 152(SP),AX
MULQ 80(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 8(SP),AX
MULQ 96(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 8(SP),AX
MULQ 104(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 8(SP),AX
MULQ 112(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ $REDMASK51,DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
MOVQ CX,R8
SHRQ $51,CX
ANDQ DX,SI
ADDQ R10,CX
MOVQ CX,R9
SHRQ $51,CX
ANDQ DX,R8
ADDQ R12,CX
MOVQ CX,AX
SHRQ $51,CX
ANDQ DX,R9
ADDQ R14,CX
MOVQ CX,R10
SHRQ $51,CX
ANDQ DX,AX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,40(DI)
MOVQ R8,48(DI)
MOVQ R9,56(DI)
MOVQ AX,64(DI)
MOVQ R10,72(DI)
MOVQ 160(SP),AX
MULQ ·_121666_213(SB)
SHRQ $13,AX
MOVQ AX,SI
MOVQ DX,CX
MOVQ 168(SP),AX
MULQ ·_121666_213(SB)
SHRQ $13,AX
ADDQ AX,CX
MOVQ DX,R8
MOVQ 176(SP),AX
MULQ ·_121666_213(SB)
SHRQ $13,AX
ADDQ AX,R8
MOVQ DX,R9
MOVQ 184(SP),AX
MULQ ·_121666_213(SB)
SHRQ $13,AX
ADDQ AX,R9
MOVQ DX,R10
MOVQ 192(SP),AX
MULQ ·_121666_213(SB)
SHRQ $13,AX
ADDQ AX,R10
IMUL3Q $19,DX,DX
ADDQ DX,SI
ADDQ 80(SP),SI
ADDQ 88(SP),CX
ADDQ 96(SP),R8
ADDQ 104(SP),R9
ADDQ 112(SP),R10
MOVQ SI,80(DI)
MOVQ CX,88(DI)
MOVQ R8,96(DI)
MOVQ R9,104(DI)
MOVQ R10,112(DI)
MOVQ 104(DI),SI
IMUL3Q $19,SI,AX
MOVQ AX,0(SP)
MULQ 176(SP)
MOVQ AX,SI
MOVQ DX,CX
MOVQ 112(DI),DX
IMUL3Q $19,DX,AX
MOVQ AX,8(SP)
MULQ 168(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 80(DI),AX
MULQ 160(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 80(DI),AX
MULQ 168(SP)
MOVQ AX,R8
MOVQ DX,R9
MOVQ 80(DI),AX
MULQ 176(SP)
MOVQ AX,R10
MOVQ DX,R11
MOVQ 80(DI),AX
MULQ 184(SP)
MOVQ AX,R12
MOVQ DX,R13
MOVQ 80(DI),AX
MULQ 192(SP)
MOVQ AX,R14
MOVQ DX,R15
MOVQ 88(DI),AX
MULQ 160(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 88(DI),AX
MULQ 168(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 88(DI),AX
MULQ 176(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 88(DI),AX
MULQ 184(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 88(DI),DX
IMUL3Q $19,DX,AX
MULQ 192(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 96(DI),AX
MULQ 160(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 96(DI),AX
MULQ 168(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 96(DI),AX
MULQ 176(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 96(DI),DX
IMUL3Q $19,DX,AX
MULQ 184(SP)
ADDQ AX,SI
ADCQ DX,CX
MOVQ 96(DI),DX
IMUL3Q $19,DX,AX
MULQ 192(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 104(DI),AX
MULQ 160(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ 104(DI),AX
MULQ 168(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 0(SP),AX
MULQ 184(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 0(SP),AX
MULQ 192(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 112(DI),AX
MULQ 160(SP)
ADDQ AX,R14
ADCQ DX,R15
MOVQ 8(SP),AX
MULQ 176(SP)
ADDQ AX,R8
ADCQ DX,R9
MOVQ 8(SP),AX
MULQ 184(SP)
ADDQ AX,R10
ADCQ DX,R11
MOVQ 8(SP),AX
MULQ 192(SP)
ADDQ AX,R12
ADCQ DX,R13
MOVQ $REDMASK51,DX
SHLQ $13,CX:SI
ANDQ DX,SI
SHLQ $13,R9:R8
ANDQ DX,R8
ADDQ CX,R8
SHLQ $13,R11:R10
ANDQ DX,R10
ADDQ R9,R10
SHLQ $13,R13:R12
ANDQ DX,R12
ADDQ R11,R12
SHLQ $13,R15:R14
ANDQ DX,R14
ADDQ R13,R14
IMUL3Q $19,R15,CX
ADDQ CX,SI
MOVQ SI,CX
SHRQ $51,CX
ADDQ R8,CX
MOVQ CX,R8
SHRQ $51,CX
ANDQ DX,SI
ADDQ R10,CX
MOVQ CX,R9
SHRQ $51,CX
ANDQ DX,R8
ADDQ R12,CX
MOVQ CX,AX
SHRQ $51,CX
ANDQ DX,R9
ADDQ R14,CX
MOVQ CX,R10
SHRQ $51,CX
ANDQ DX,AX
IMUL3Q $19,CX,CX
ADDQ CX,SI
ANDQ DX,R10
MOVQ SI,80(DI)
MOVQ R8,88(DI)
MOVQ R9,96(DI)
MOVQ AX,104(DI)
MOVQ R10,112(DI)
RET
| {
"language": "Assembly"
} |
/* Definitions for rtems targeting a PowerPC using elf.
Copyright (C) 1996, 1997, 2000, 2001, 2002, 2003, 2004, 2005
Free Software Foundation, Inc.
Contributed by Joel Sherrill (joel@OARcorp.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 2, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA. */
/* Specify predefined symbols in preprocessor. */
#undef TARGET_OS_CPP_BUILTINS
#define TARGET_OS_CPP_BUILTINS() \
do \
{ \
builtin_define_std ("PPC"); \
builtin_define ("__rtems__"); \
builtin_define ("__USE_INIT_FINI__"); \
builtin_assert ("system=rtems"); \
builtin_assert ("cpu=powerpc"); \
builtin_assert ("machine=powerpc"); \
TARGET_OS_SYSV_CPP_BUILTINS (); \
} \
while (0)
#undef CPP_OS_DEFAULT_SPEC
#define CPP_OS_DEFAULT_SPEC "%(cpp_os_rtems)"
#define CPP_OS_RTEMS_SPEC "\
%{!mcpu*: %{!Dppc*: %{!Dmpc*: -Dmpc750} } }\
%{mcpu=403: %{!Dppc*: %{!Dmpc*: -Dppc403} } } \
%{mcpu=505: %{!Dppc*: %{!Dmpc*: -Dmpc505} } } \
%{mcpu=601: %{!Dppc*: %{!Dmpc*: -Dppc601} } } \
%{mcpu=602: %{!Dppc*: %{!Dmpc*: -Dppc602} } } \
%{mcpu=603: %{!Dppc*: %{!Dmpc*: -Dppc603} } } \
%{mcpu=603e: %{!Dppc*: %{!Dmpc*: -Dppc603e} } } \
%{mcpu=604: %{!Dppc*: %{!Dmpc*: -Dmpc604} } } \
%{mcpu=750: %{!Dppc*: %{!Dmpc*: -Dmpc750} } } \
%{mcpu=821: %{!Dppc*: %{!Dmpc*: -Dmpc821} } } \
%{mcpu=860: %{!Dppc*: %{!Dmpc*: -Dmpc860} } }"
#undef SUBSUBTARGET_EXTRA_SPECS
#define SUBSUBTARGET_EXTRA_SPECS \
{ "cpp_os_rtems", CPP_OS_RTEMS_SPEC }
| {
"language": "Assembly"
} |
;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f429xx.s
;* Author : MCD Application Team
;* Description : STM32F429xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD 0 ; Reserved
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
DCD UART7_IRQHandler ; UART7
DCD UART8_IRQHandler ; UART8
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD SPI6_IRQHandler ; SPI6
DCD SAI1_IRQHandler ; SAI1
DCD LTDC_IRQHandler ; LTDC
DCD LTDC_ER_IRQHandler ; LTDC error
DCD DMA2D_IRQHandler ; DMA2D
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Stream0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream0_IRQHandler
B DMA1_Stream0_IRQHandler
PUBWEAK DMA1_Stream1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream1_IRQHandler
B DMA1_Stream1_IRQHandler
PUBWEAK DMA1_Stream2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream2_IRQHandler
B DMA1_Stream2_IRQHandler
PUBWEAK DMA1_Stream3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream3_IRQHandler
B DMA1_Stream3_IRQHandler
PUBWEAK DMA1_Stream4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream4_IRQHandler
B DMA1_Stream4_IRQHandler
PUBWEAK DMA1_Stream5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream5_IRQHandler
B DMA1_Stream5_IRQHandler
PUBWEAK DMA1_Stream6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream6_IRQHandler
B DMA1_Stream6_IRQHandler
PUBWEAK ADC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM9_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM9_IRQHandler
B TIM1_BRK_TIM9_IRQHandler
PUBWEAK TIM1_UP_TIM10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM10_IRQHandler
B TIM1_UP_TIM10_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM11_IRQHandler
B TIM1_TRG_COM_TIM11_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK TIM8_BRK_TIM12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_BRK_TIM12_IRQHandler
B TIM8_BRK_TIM12_IRQHandler
PUBWEAK TIM8_UP_TIM13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_UP_TIM13_IRQHandler
B TIM8_UP_TIM13_IRQHandler
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_TRG_COM_TIM14_IRQHandler
B TIM8_TRG_COM_TIM14_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK DMA1_Stream7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream7_IRQHandler
B DMA1_Stream7_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Stream0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream0_IRQHandler
B DMA2_Stream0_IRQHandler
PUBWEAK DMA2_Stream1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream1_IRQHandler
B DMA2_Stream1_IRQHandler
PUBWEAK DMA2_Stream2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream2_IRQHandler
B DMA2_Stream2_IRQHandler
PUBWEAK DMA2_Stream3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream3_IRQHandler
B DMA2_Stream3_IRQHandler
PUBWEAK DMA2_Stream4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream4_IRQHandler
B DMA2_Stream4_IRQHandler
PUBWEAK ETH_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ETH_IRQHandler
B ETH_IRQHandler
PUBWEAK ETH_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
ETH_WKUP_IRQHandler
B ETH_WKUP_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_Stream5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream5_IRQHandler
B DMA2_Stream5_IRQHandler
PUBWEAK DMA2_Stream6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream6_IRQHandler
B DMA2_Stream6_IRQHandler
PUBWEAK DMA2_Stream7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream7_IRQHandler
B DMA2_Stream7_IRQHandler
PUBWEAK USART6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS_EP1_OUT_IRQHandler
B OTG_HS_EP1_OUT_IRQHandler
PUBWEAK OTG_HS_EP1_IN_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS_EP1_IN_IRQHandler
B OTG_HS_EP1_IN_IRQHandler
PUBWEAK OTG_HS_WKUP_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS_WKUP_IRQHandler
B OTG_HS_WKUP_IRQHandler
PUBWEAK OTG_HS_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
OTG_HS_IRQHandler
B OTG_HS_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK HASH_RNG_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
HASH_RNG_IRQHandler
B HASH_RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK UART7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART7_IRQHandler
B UART7_IRQHandler
PUBWEAK UART8_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
UART8_IRQHandler
B UART8_IRQHandler
PUBWEAK SPI4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI4_IRQHandler
B SPI4_IRQHandler
PUBWEAK SPI5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI5_IRQHandler
B SPI5_IRQHandler
PUBWEAK SPI6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI6_IRQHandler
B SPI6_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK LTDC_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
LTDC_IRQHandler
B LTDC_IRQHandler
PUBWEAK LTDC_ER_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
LTDC_ER_IRQHandler
B LTDC_ER_IRQHandler
PUBWEAK DMA2D_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2D_IRQHandler
B DMA2D_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
| {
"language": "Assembly"
} |
; RUN: llc < %s -march=bpfel -show-mc-encoding | FileCheck --check-prefix=CHECK-EL %s
; RUN: llc < %s -march=bpfeb -show-mc-encoding | FileCheck --check-prefix=CHECK-EB %s
; Function Attrs: nounwind uwtable
define i32 @ld_b(i64 %foo, i64* nocapture %bar, i8* %ctx, i8* %ctx2) #0 {
%1 = tail call i64 @llvm.bpf.load.byte(i8* %ctx, i64 123) #2
%2 = add i64 %1, %foo
%3 = load volatile i64, i64* %bar, align 8
%4 = add i64 %2, %3
%5 = tail call i64 @llvm.bpf.load.byte(i8* %ctx2, i64 %foo) #2
%6 = add i64 %4, %5
%7 = load volatile i64, i64* %bar, align 8
%8 = add i64 %6, %7
%9 = trunc i64 %8 to i32
ret i32 %9
; CHECK-LABEL: ld_b:
; CHECK-EL: r0 = *(u8 *)skb[123]
; CHECK-EL: r0 = *(u8 *)skb[r
; CHECK-EB: r0 = *(u8 *)skb[123]
; CHECK-EB: r0 = *(u8 *)skb[r
}
declare i64 @llvm.bpf.load.byte(i8*, i64) #1
; Function Attrs: nounwind uwtable
define i32 @ld_h(i8* %ctx, i8* %ctx2, i32 %foo) #0 {
%1 = tail call i64 @llvm.bpf.load.half(i8* %ctx, i64 123) #2
%2 = sext i32 %foo to i64
%3 = tail call i64 @llvm.bpf.load.half(i8* %ctx2, i64 %2) #2
%4 = add i64 %3, %1
%5 = trunc i64 %4 to i32
ret i32 %5
; CHECK-LABEL: ld_h:
; CHECK-EL: r0 = *(u16 *)skb[r
; CHECK-EL: r0 = *(u16 *)skb[123]
; CHECK-EB: r0 = *(u16 *)skb[r
; CHECK-EB: r0 = *(u16 *)skb[123]
}
declare i64 @llvm.bpf.load.half(i8*, i64) #1
; Function Attrs: nounwind uwtable
define i32 @ld_w(i8* %ctx, i8* %ctx2, i32 %foo) #0 {
%1 = tail call i64 @llvm.bpf.load.word(i8* %ctx, i64 123) #2
%2 = sext i32 %foo to i64
%3 = tail call i64 @llvm.bpf.load.word(i8* %ctx2, i64 %2) #2
%4 = add i64 %3, %1
%5 = trunc i64 %4 to i32
ret i32 %5
; CHECK-LABEL: ld_w:
; CHECK-EL: r0 = *(u32 *)skb[r
; CHECK-EL: r0 = *(u32 *)skb[123]
; CHECK-EB: r0 = *(u32 *)skb[r
; CHECK-EB: r0 = *(u32 *)skb[123]
}
declare i64 @llvm.bpf.load.word(i8*, i64) #1
define i32 @ld_pseudo() #0 {
entry:
%call = tail call i64 @llvm.bpf.pseudo(i64 2, i64 3)
tail call void inttoptr (i64 4 to void (i64, i32)*)(i64 %call, i32 4) #2
ret i32 0
; CHECK-LABEL: ld_pseudo:
; CHECK-EL: ld_pseudo r1, 2, 3 # encoding: [0x18,0x21,0x00,0x00,0x03,0x00,0x00,0x00
; CHECK-EB: ld_pseudo r1, 2, 3 # encoding: [0x18,0x12,0x00,0x00,0x00,0x00,0x00,0x03
}
declare i64 @llvm.bpf.pseudo(i64, i64) #2
define i32 @bswap(i64 %a, i64 %b, i64 %c) #0 {
entry:
%0 = tail call i64 @llvm.bswap.i64(i64 %a)
%conv = trunc i64 %b to i32
%1 = tail call i32 @llvm.bswap.i32(i32 %conv)
%conv1 = zext i32 %1 to i64
%add = add i64 %conv1, %0
%conv2 = trunc i64 %c to i16
%2 = tail call i16 @llvm.bswap.i16(i16 %conv2)
%conv3 = zext i16 %2 to i64
%add4 = add i64 %add, %conv3
%conv5 = trunc i64 %add4 to i32
ret i32 %conv5
; CHECK-LABEL: bswap:
; CHECK-EL: r1 = be64 r1 # encoding: [0xdc,0x01,0x00,0x00,0x40,0x00,0x00,0x00]
; CHECK-EL: r0 = be32 r0 # encoding: [0xdc,0x00,0x00,0x00,0x20,0x00,0x00,0x00]
; CHECK-EL: r0 += r1 # encoding: [0x0f,0x10,0x00,0x00,0x00,0x00,0x00,0x00]
; CHECK-EL: r3 = be16 r3 # encoding: [0xdc,0x03,0x00,0x00,0x10,0x00,0x00,0x00]
; CHECK-EL: r0 += r3 # encoding: [0x0f,0x30,0x00,0x00,0x00,0x00,0x00,0x00]
; CHECK-EB: r1 = le64 r1 # encoding: [0xd4,0x10,0x00,0x00,0x00,0x00,0x00,0x40]
; CHECK-EB: r0 = le32 r0 # encoding: [0xd4,0x00,0x00,0x00,0x00,0x00,0x00,0x20]
; CHECK-EB: r0 += r1 # encoding: [0x0f,0x01,0x00,0x00,0x00,0x00,0x00,0x00]
; CHECK-EB: r3 = le16 r3 # encoding: [0xd4,0x30,0x00,0x00,0x00,0x00,0x00,0x10]
; CHECK-EB: r0 += r3 # encoding: [0x0f,0x03,0x00,0x00,0x00,0x00,0x00,0x00]
}
declare i64 @llvm.bswap.i64(i64) #1
declare i32 @llvm.bswap.i32(i32) #1
declare i16 @llvm.bswap.i16(i16) #1
| {
"language": "Assembly"
} |
;
; ZX81 libraries
;
;--------------------------------------------------------------
; This code comes from the FidoNET Sinclair newsgroup
;--------------------------------------------------------------
;
; $Id: mirrortxt.asm,v 1.3 2016-06-26 20:32:08 dom Exp $
;
;----------------------------------------------------------------
;
; mirrortxt() - mirror text display
;
;----------------------------------------------------------------
SECTION code_clib
PUBLIC mirrortxt
PUBLIC _mirrortxt
mirrortxt:
_mirrortxt:
LD HL,(400CH) ; Puts the adress of the displayfile in HL
LD DE,0010H ; This is the middle of the screen
ADD HL,DE ; Add to displayfile
LD D,H ; leave result in DE
LD E,L ;
INC DE ; counting up
LD B,16H ; B as counter 22 lines
.MIR1 LD A,(HL) ; Character in accumulator
CP 76H ; look for end line
JR Z,MIR2 ; If b not 0 goto 409E
EX DE,HL ; temporary storage
LD C,(HL) ;
LD (HL),A ; Print to Dfile
EX DE,HL ; get value back again
LD (HL),C ; print to Dfile
DEC HL ; counting down
INC DE ;
JR MIR1 ; Get next character
.MIR2 LD DE,0031H ; Go to middle of next line
ADD HL,DE ;
LD D,H ;
LD E,L ;
INC DE ;
DJNZ MIR1 ; until screen full repeat routine
RET
| {
"language": "Assembly"
} |
/*
dct64_x86_64_float: SSE optimized dct64 for x86-64 (float output version)
copyright 1995-2013 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Taihei Monma
*/
#include "mangle.h"
#define samples %rdx
#define costab %rcx
#define out0 %rdi
#define out1 %rsi
/*
void dct64_real_avx(real *out0, real *out1, real *samples);
*/
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN32
costab_avx:
.long 1056974725
.long 1057056395
.long 1057223771
.long 1057485416
.long 1057855544
.long 1058356026
.long 1059019886
.long 1059897405
.long 1061067246
.long 1062657950
.long 1064892987
.long 1066774581
.long 1069414683
.long 1073984175
.long 1079645762
.long 1092815430
.long 1057005197
.long 1057342072
.long 1058087743
.long 1059427869
.long 1061799040
.long 1065862217
.long 1071413542
.long 1084439708
.long 1057128951
.long 1058664893
.long 1063675095
.long 1076102863
.long 1057655764
.long 1067924853
.long 1060439283
.long 0
.text
ALIGN16
.globl ASM_NAME(dct64_real_avx)
ASM_NAME(dct64_real_avx):
#ifdef IS_MSABI
push %rbp
mov %rsp, %rbp
sub $112, %rsp
movaps %xmm6, (%rsp)
movaps %xmm7, 16(%rsp)
movaps %xmm8, 32(%rsp)
movaps %xmm9, 48(%rsp)
movaps %xmm10, 64(%rsp)
movaps %xmm11, 80(%rsp)
movaps %xmm12, 96(%rsp)
push %rdi
push %rsi
mov %rcx, %rdi
mov %rdx, %rsi
mov %r8, %rdx
#endif
leaq costab_avx(%rip), costab
vmovups (samples), %ymm0 # input[0,1,2,3,4,5,6,7]
vmovups 32(samples), %ymm1 # input[8,9,10,11,12,13,14,15]
vperm2f128 $0x23, 64(samples), %ymm2, %ymm2
vperm2f128 $0x23, 96(samples), %ymm3, %ymm3
vshufps $0x1b, %ymm2, %ymm2, %ymm2 # input[23,22,21,20,19,18,17,16]
vshufps $0x1b, %ymm3, %ymm3, %ymm3 # input[31,30,29,28,27,26,25,24]
vsubps %ymm2, %ymm1, %ymm6
vsubps %ymm3, %ymm0, %ymm7
vaddps %ymm0, %ymm3, %ymm4 # bufs[0,1,2,3,4,5,6,7]
vaddps %ymm1, %ymm2, %ymm5 # bufs[8,9,10,11,12,13,14,15]
vmulps (costab), %ymm7, %ymm7 # bufs[31,30,29,28,27,26,25,24] cos64[0,1,2,3,4,5,6,7]
vmulps 32(costab), %ymm6, %ymm6 # bufs[23,22,21,20,19,18,17,16] cos64[8,9,10,11,12,13,14,15]
vmovaps 64(costab), %ymm8 # cos32[0,1,2,3,4,5,6,7]
vshufps $0x1b, %ymm5, %ymm5, %ymm5
vshufps $0x1b, %ymm6, %ymm6, %ymm6
vperm2f128 $0x01, %ymm5, %ymm5, %ymm5 # bufs[15,14,13,12,11,10,9,8]
vperm2f128 $0x01, %ymm6, %ymm6, %ymm6 # bufs[16,17,18,19,20,21,22,23]
vsubps %ymm5, %ymm4, %ymm1
vsubps %ymm6, %ymm7, %ymm3
vaddps %ymm5, %ymm4, %ymm0 # bufs[32,33,34,35,36,37,38,39]
vaddps %ymm6, %ymm7, %ymm2 # bufs[48,49,50,51,52,53,54,55]
vmulps %ymm1, %ymm8, %ymm1 # bufs[47,46,45,44,43,42,41,40]
vmulps %ymm3, %ymm8, %ymm3 # bufs[63,62,61,60,59,58,57,56]
vmovaps 96(costab), %ymm8 # cos16[0,1,2,3]:cos8[0,1]:cos4[0]:-
vperm2f128 $0x00, %ymm8, %ymm8, %ymm9 # cos16[0,1,2,3,0,1,2,3]
vperm2f128 $0x20, %ymm1, %ymm0, %ymm4 # bufs[32,33,34,35,47,46,45,44]
vperm2f128 $0x31, %ymm1, %ymm0, %ymm5
vshufps $0x1b, %ymm5, %ymm5, %ymm5 # bufs[39,38,37,36,40,41,42,43]
vperm2f128 $0x20, %ymm3, %ymm2, %ymm6 # bufs[48,49,50,51,63,62,61,60]
vperm2f128 $0x31, %ymm3, %ymm2, %ymm7
vshufps $0x1b, %ymm7, %ymm7, %ymm7 # bufs[55,54,53,52,56,57,58,59]
vsubps %ymm5, %ymm4, %ymm1
vsubps %ymm7, %ymm6, %ymm3
vaddps %ymm5, %ymm4, %ymm0 # bufs[0,1,2,3,8,9,10,11]
vaddps %ymm7, %ymm6, %ymm2 # bufs[16,17,18,19,24,25,26,27]
vmulps %ymm1, %ymm9, %ymm1 # bufs[7,6,5,4,15,14,13,12]
vmulps %ymm3, %ymm9, %ymm3 # bufs[23,22,21,20,31,30,29,28]
vperm2f128 $0x11, %ymm8, %ymm8, %ymm8 # cos8[0,1]:cos4[0]:-:cos8[0,1]:cos4[0]:-
vmovddup %ymm8, %ymm9 # cos8[0,1,0,1,0,1,0,1]
vunpcklps %ymm1, %ymm0, %ymm4 # bufs[0,7,1,6,8,15,9,14]
vunpckhps %ymm1, %ymm0, %ymm5 # bufs[2,5,3,4,10,13,11,12]
vunpcklps %ymm3, %ymm2, %ymm6 # bufs[16,23,17,22,24,31,25,30]
vunpckhps %ymm3, %ymm2, %ymm7 # bufs[18,21,19,20,26,29,27,28]
vshufps $0xd8, %ymm4, %ymm4, %ymm4 # bufs[0,1,7,6,8,9,15,14]
vshufps $0x72, %ymm5, %ymm5, %ymm5 # bufs[3,2,4,5,11,10,12,13]
vshufps $0xd8, %ymm6, %ymm6, %ymm6 # bufs[16,17,23,22,24,25,31,30]
vshufps $0x72, %ymm7, %ymm7, %ymm7 # bufs[19,18,20,21,27,26,28,29]
vsubps %ymm5, %ymm4, %ymm1
vsubps %ymm7, %ymm6, %ymm3
vaddps %ymm5, %ymm4, %ymm0 # bufs[32,33,36,37,40,41,44,45]
vaddps %ymm7, %ymm6, %ymm2 # bufs[48,49,52,53,56,57,60,61]
vmulps %ymm1, %ymm9, %ymm1 # bufs[35,34,39,38,43,42,47,46]
vmulps %ymm3, %ymm9, %ymm3 # bufs[51,50,55,54,59,58,63,62]
vpermilps $0xaa, %ymm8, %ymm8 # cos4[0,0,0,0,0,0,0,0]
vshufps $0xd8, %ymm0, %ymm0, %ymm0 # bufs[32,36,33,37,40,44,41,45]
vshufps $0xd8, %ymm1, %ymm1, %ymm1 # bufs[35,39,34,38,43,47,42,46]
vshufps $0xd8, %ymm2, %ymm2, %ymm2 # bufs[48,52,49,53,56,60,57,61]
vshufps $0xd8, %ymm3, %ymm3, %ymm3 # bufs[51,55,50,54,59,63,58,62]
vunpcklps %ymm1, %ymm0, %ymm4 # bufs[32,35,36,39,40,43,44,47]
vunpckhps %ymm1, %ymm0, %ymm5 # bufs[33,34,37,38,41,42,45,46]
vunpcklps %ymm3, %ymm2, %ymm6 # bufs[48,51,52,55,56,59,60,63]
vunpckhps %ymm3, %ymm2, %ymm7 # bufs[49,50,53,54,57,58,61,62]
vsubps %ymm5, %ymm4, %ymm1
vsubps %ymm7, %ymm6, %ymm3
vaddps %ymm5, %ymm4, %ymm0 # bufs[0,2,4,6,8,10,12,14]
vaddps %ymm7, %ymm6, %ymm2 # bufs[16,18,20,22,24,26,28,30]
vmulps %ymm1, %ymm8, %ymm1 # bufs[1,3,5,7,9,11,13,15]
vmulps %ymm3, %ymm8, %ymm3 # bufs[17,19,21,23,25,27,29,31]
vxorps %ymm8, %ymm8, %ymm8
vblendps $0xaa, %ymm1, %ymm8, %ymm5
vblendps $0xaa, %ymm3, %ymm8, %ymm6
vaddps %ymm5, %ymm0, %ymm0
vaddps %ymm6, %ymm2, %ymm2
vunpcklps %ymm1, %ymm0, %ymm4 # bufs[0,1,2,3,8,9,10,11]
vunpckhps %ymm1, %ymm0, %ymm5 # bufs[4,5,6,7,12,13,14,15]
vunpcklps %ymm3, %ymm2, %ymm6 # bufs[16,17,18,19,24,25,26,27]
vunpckhps %ymm3, %ymm2, %ymm7 # bufs[20,21,22,23,28,29,30,31]
vextractf128 $0x1, %ymm4, %xmm0 # bufs[8,9,10,11]
vextractf128 $0x1, %ymm5, %xmm1 # bufs[12,13,14,15]
vextractf128 $0x1, %ymm6, %xmm2 # bufs[24,25,26,27]
vextractf128 $0x1, %ymm7, %xmm3 # bufs[28,29,30,31]
vshufps $0x1e, %xmm5, %xmm5, %xmm9 # bufs[6,7,5,4]
vshufps $0x1e, %xmm1, %xmm1, %xmm10 # bufs[14,15,13,12]
vshufps $0x1e, %xmm7, %xmm7, %xmm11 # bufs[22,23,21,20]
vshufps $0x1e, %xmm3, %xmm3, %xmm12 # bufs[30,31,29,28]
vblendps $0x7, %xmm9, %xmm8, %xmm9 # bufs[6,7,5,-]
vblendps $0x7, %xmm10, %xmm8, %xmm10 # bufs[14,15,13,-]
vblendps $0x7, %xmm11, %xmm8, %xmm11 # bufs[22,23,21,-]
vblendps $0x7, %xmm12, %xmm8, %xmm12 # bufs[30,31,29,-]
vaddps %xmm5, %xmm9, %xmm5
vaddps %xmm1, %xmm10, %xmm1
vaddps %xmm7, %xmm11, %xmm7
vaddps %xmm3, %xmm12, %xmm3
prefetcht0 1024(out0)
vshufps $0x1e, %xmm0, %xmm0, %xmm9 # bufs[10,11,9,8]
vshufps $0x1e, %xmm2, %xmm2, %xmm10 # bufs[26,27,25,24]
vaddps %xmm1, %xmm0, %xmm0
vaddps %xmm3, %xmm2, %xmm2
vblendps $0x7, %xmm9, %xmm8, %xmm9 # bufs[10,11,9,-]
vblendps $0x7, %xmm10, %xmm8, %xmm10 # bufs[26,27,25,-]
vaddps %xmm1, %xmm9, %xmm1
vaddps %xmm3, %xmm10, %xmm3
vzeroupper
prefetcht0 1024(out1)
addq $1024, out0
movq $-128, %rax
movss %xmm4, (out0)
movss %xmm0, (out0,%rax,1)
movss %xmm5, (out0,%rax,2)
movss %xmm1, -128(out0,%rax,2)
leaq (out0,%rax,4), out0
movhlps %xmm4, %xmm9
movhlps %xmm0, %xmm10
movhlps %xmm5, %xmm11
movhlps %xmm1, %xmm12
vmovss %xmm9, (out0)
vmovss %xmm10, (out0,%rax,1)
vmovss %xmm11, (out0,%rax,2)
vmovss %xmm12, -128(out0,%rax,2)
leaq (out0,%rax,4), out0
negq %rax
shufps $0xb1, %xmm4, %xmm4
shufps $0xb1, %xmm0, %xmm0
shufps $0xb1, %xmm5, %xmm5
shufps $0xb1, %xmm1, %xmm1
movss %xmm4, (out0)
movss %xmm4, (out1)
leaq (out1,%rax,1), out1
movss %xmm0, (out1)
movss %xmm5, (out1,%rax,1)
movss %xmm1, (out1,%rax,2)
leaq (out1,%rax,4), out1
movhlps %xmm4, %xmm4
movhlps %xmm0, %xmm0
movhlps %xmm5, %xmm5
movhlps %xmm1, %xmm1
movss %xmm4, -128(out1)
movss %xmm0, (out1)
movss %xmm5, (out1,%rax,1)
movss %xmm1, (out1,%rax,2)
leaq -64(out0,%rax,8), out0
negq %rax
vshufps $0x1e, %xmm6, %xmm6, %xmm0
vblendps $0x7, %xmm0, %xmm8, %xmm0
addps %xmm2, %xmm6
addps %xmm7, %xmm2
addps %xmm3, %xmm7
addps %xmm0, %xmm3
movss %xmm6, (out0)
movss %xmm2, (out0,%rax,1)
movss %xmm7, (out0,%rax,2)
movss %xmm3, -128(out0,%rax,2)
leaq (out0,%rax,4), out0
movhlps %xmm6, %xmm0
movhlps %xmm2, %xmm1
movhlps %xmm7, %xmm4
movhlps %xmm3, %xmm5
movss %xmm0, (out0)
movss %xmm1, (out0,%rax,1)
movss %xmm4, (out0,%rax,2)
movss %xmm5, -128(out0,%rax,2)
leaq 64(out1,%rax,4), out1
negq %rax
shufps $0xb1, %xmm6, %xmm6
shufps $0xb1, %xmm2, %xmm2
shufps $0xb1, %xmm7, %xmm7
shufps $0xb1, %xmm3, %xmm3
movss %xmm6, -128(out1)
movss %xmm2, (out1)
movss %xmm7, (out1,%rax,1)
movss %xmm3, (out1,%rax,2)
leaq (out1,%rax,4), out1
movhlps %xmm6, %xmm6
movhlps %xmm2, %xmm2
movhlps %xmm7, %xmm7
movhlps %xmm3, %xmm3
movss %xmm6, -128(out1)
movss %xmm2, (out1)
movss %xmm7, (out1,%rax,1)
movss %xmm3, (out1,%rax,2)
#ifdef IS_MSABI
pop %rsi
pop %rdi
movaps (%rsp), %xmm6
movaps 16(%rsp), %xmm7
movaps 32(%rsp), %xmm8
movaps 48(%rsp), %xmm9
movaps 64(%rsp), %xmm10
movaps 80(%rsp), %xmm11
movaps 96(%rsp), %xmm12
mov %rbp, %rsp
pop %rbp
#endif
ret
NONEXEC_STACK
| {
"language": "Assembly"
} |
Basic tests for sample profiles.
1- Show all functions
RUN: llvm-profdata show --sample %p/Inputs/sample-profile.proftext | FileCheck %s --check-prefix=SHOW1
SHOW1-DAG: Function: main: 184019, 0, 7 sampled lines
SHOW1-DAG: 9: 2064, calls: _Z3fooi:631 _Z3bari:1471
SHOW1-DAG: Function: _Z3fooi: 7711, 610, 1 sampled lines
SHOW1-DAG: Function: _Z3bari: 20301, 1437, 1 sampled lines
SHOW1-DAG: 1: 1437
2- Show only bar
RUN: llvm-profdata show --sample --function=_Z3bari %p/Inputs/sample-profile.proftext | FileCheck %s --check-prefix=SHOW2
SHOW2: Function: _Z3bari: 20301, 1437, 1 sampled lines
SHOW2: 1: 1437
SHOW2-NOT: Function: main: 184019, 0, 7 sampled lines
SHOW2-NOT: Function: _Z3fooi: 7711, 610, 1 sampled lines
3- Convert the profile to binary encoding and check that they are both
identical.
RUN: llvm-profdata merge --sample %p/Inputs/sample-profile.proftext --binary -o - | llvm-profdata show --sample - -o %t-binary
RUN: llvm-profdata show --sample %p/Inputs/sample-profile.proftext -o %t-text
RUN: diff %t-binary %t-text
4- Merge the binary and text encodings of the profile and check that the
counters have doubled.
RUN: llvm-profdata merge --sample %p/Inputs/sample-profile.proftext -o %t-binprof
RUN: llvm-profdata merge --sample --text %p/Inputs/sample-profile.proftext %t-binprof -o - | FileCheck %s --check-prefix=MERGE1
MERGE1: main:368038:0
MERGE1: 9: 4128 _Z3fooi:1262 _Z3bari:2942
MERGE1: _Z3bari:40602:2874
MERGE1: _Z3fooi:15422:1220
5- Detect invalid text encoding (e.g. instrumentation profile text format).
RUN: not llvm-profdata show --sample %p/Inputs/foo3bar3-1.proftext 2>&1 | FileCheck %s --check-prefix=BADTEXT
BADTEXT: error: {{.+}}: Unrecognized sample profile encoding format
| {
"language": "Assembly"
} |
;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f412zx.s
;* Author : MCD Application Team
;* Description : STM32F412Zx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD 0 ; Reserved
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global interrupt
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI4_IRQHandler ; SPI4
DCD SPI5_IRQHandler ; SPI5
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD QUADSPI_IRQHandler ; QuadSPI
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event
DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SPI5_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT FMPI2C1_EV_IRQHandler [WEAK]
EXPORT FMPI2C1_ER_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
DFSDM1_FLT0_IRQHandler
DFSDM1_FLT1_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
RNG_IRQHandler
FPU_IRQHandler
SPI4_IRQHandler
SPI5_IRQHandler
QUADSPI_IRQHandler
FMPI2C1_EV_IRQHandler
FMPI2C1_ER_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
| {
"language": "Assembly"
} |
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--"
define void @test_fneg_f32() {
entry:
ret void
}
define void @test_fneg_f64() {
entry:
ret void
}
...
---
name: test_fneg_f32
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.1:
liveins: %s0
; CHECK-LABEL: name: test_fneg_f32
; CHECK: [[VAR:%[0-9]+]](s32) = COPY %s0
; CHECK: [[ZERO:%[0-9]+]](s32) = G_FCONSTANT float -0.000000e+00
; CHECK: [[RES:%[0-9]+]](s32) = G_FSUB [[ZERO]], [[VAR]]
; CHECK: %s0 = COPY [[RES]](s32)
%0(s32) = COPY %s0
%1(s32) = G_FNEG %0
%s0 = COPY %1(s32)
...
---
name: test_fneg_f64
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.1:
liveins: %d0
; CHECK-LABEL: name: test_fneg_f64
; CHECK: [[VAR:%[0-9]+]](s64) = COPY %d0
; CHECK: [[ZERO:%[0-9]+]](s64) = G_FCONSTANT double -0.000000e+00
; CHECK: [[RES:%[0-9]+]](s64) = G_FSUB [[ZERO]], [[VAR]]
; CHECK: %d0 = COPY [[RES]](s64)
%0(s64) = COPY %d0
%1(s64) = G_FNEG %0
%d0 = COPY %1(s64)
...
| {
"language": "Assembly"
} |
line 1
#include("include/include1.vm")
line 2
#parse("include/include1.vm")
line 3 | {
"language": "Assembly"
} |
comment "qt needs a toolchain w/ C++, threads"
depends on !BR2_avr32
depends on BR2_USE_MMU
depends on !BR2_INSTALL_LIBSTDCPP || !BR2_TOOLCHAIN_HAS_THREADS
menuconfig BR2_PACKAGE_QT
bool "Qt"
depends on !BR2_avr32 # lacks TLS
depends on BR2_USE_MMU # fork
depends on BR2_INSTALL_LIBSTDCPP
depends on BR2_TOOLCHAIN_HAS_THREADS
help
Qt is a cross-platform application and UI framework for
developers using C++.
http://qt-project.org
if BR2_PACKAGE_QT
choice
prompt "Qt installation"
help
Selects the type of installation: standard or embedded
config BR2_PACKAGE_QT_EMBEDDED
bool "Qt embedded"
help
The embedded Qt installation targets embedded systems without X.org.
Provides backends for framebuffer.
If unsure, say Y.
comment "Qt standard (X11) not available (need X.org)"
depends on !BR2_PACKAGE_XORG7
config BR2_PACKAGE_QT_X11
bool "Qt standard (X11)"
depends on BR2_PACKAGE_XORG7
select BR2_PACKAGE_FONTCONFIG
select BR2_PACKAGE_XLIB_LIBXI
select BR2_PACKAGE_XLIB_LIBX11
select BR2_PACKAGE_XLIB_LIBXRENDER
select BR2_PACKAGE_XLIB_LIBXCURSOR
select BR2_PACKAGE_XLIB_LIBXRANDR
select BR2_PACKAGE_XLIB_LIBXEXT
select BR2_PACKAGE_XLIB_LIBXV
select BR2_PACKAGE_QT_SYSTEMFREETYPE
select BR2_PACKAGE_QT_GUI_MODULE
help
The standard Qt installation provides X.org backend. If you don't want to
use X.org, say N.
endchoice
config BR2_PACKAGE_QT_DEBUG
bool "Compile with debug support"
help
If unsure, say N.
config BR2_PACKAGE_QT_DEMOS
bool "Compile and install Qt demos (with code)"
select BR2_PACKAGE_QT_GUI_MODULE
help
If unsure, say N.
config BR2_PACKAGE_QT_TRANSLATION_FILES
bool "Install translation files"
help
Install binary .qm translation files.
Say y if you need these files. They will take about 8 MB
on the target root filesystem.
config BR2_PACKAGE_QT_EXAMPLES
bool "Compile and install Qt examples (with code)"
select BR2_PACKAGE_QT_GUI_MODULE
help
If unsure, say N.
choice
prompt "Library type"
help
Selects the library type: Shared or Static
config BR2_PACKAGE_QT_SHARED
bool "Shared library"
depends on !BR2_STATIC_LIBS
help
Create and use shared Qt libraries.
If you have multiple programs that depend on Qt or intend to use
plugins, say Y.
config BR2_PACKAGE_QT_STATIC
bool "Static Library"
help
Create and use static Qt libraries.
If you don't have multiple programs on the target that depends on
Qt, then this will save you quite some of storage space.
If unsure, say Y.
endchoice
config BR2_PACKAGE_QT_LICENSE_APPROVED
bool "Approve free license"
help
Select this if you approve one of the available free licenses for the
Qt4 library.
By doing this you will not be asked while the library is compiled.
Please read and understand the license terms before approving this.
LGPL v2.1: http://doc.trolltech.com/4.5/lgpl.html
GPL v3.0: http://doc.trolltech.com/4.5/gpl.html
config BR2_PACKAGE_QT_CONFIG_FILE
string "Config file"
help
Configure options allow to set which modules are being
compiled or not in Qt, but Qt also provide a more
fine-grained mechanism to configure which features should be
enabled or disabled, through a header file. Examples of such
header files can be found in src/corelib/global/qconfig-*.h
in the Qt sources.
This option allows to set the path of such a configuration
file, which Buildroot will give to Qt at compile time.
config BR2_PACKAGE_QT_QT3SUPPORT
bool "Compatibility with Qt3"
depends on BR2_PACKAGE_QT_GUI_MODULE
help
Turns on support for older Qt3. This will create an additional
library with proxy code and increase the space required on target.
If unsure say n.
config BR2_PACKAGE_QT_GUI_MODULE
bool "Gui Module"
select BR2_PACKAGE_QT_NETWORK
default y
help
Turns on support for Gui applications. If your board doesn't have
video output, or you don't require Qt GUI, say n.
if BR2_PACKAGE_QT_GUI_MODULE
if BR2_PACKAGE_QT_EMBEDDED
menu "Pixel depths"
comment "Deselecting each option leads to Qt's default (8,16,32)"
config BR2_PACKAGE_QT_PIXEL_DEPTH_1
bool "1 bpp, black/white"
config BR2_PACKAGE_QT_PIXEL_DEPTH_4
bool "4 bpp, grayscale"
config BR2_PACKAGE_QT_PIXEL_DEPTH_8
bool "8 bpp, paletted"
default y
config BR2_PACKAGE_QT_PIXEL_DEPTH_12
bool "12 bpp, rgb 4-4-4"
config BR2_PACKAGE_QT_PIXEL_DEPTH_15
bool "15 bpp, rgb 5-5-5"
config BR2_PACKAGE_QT_PIXEL_DEPTH_16
bool "16 bpp, rgb 5-6-5"
default y
config BR2_PACKAGE_QT_PIXEL_DEPTH_18
bool "18 bpp, rgb 6-6-6"
config BR2_PACKAGE_QT_PIXEL_DEPTH_24
bool "24 bpp, rgb 8-8-8"
config BR2_PACKAGE_QT_PIXEL_DEPTH_32
bool "32 bpp, argb 8-8-8-8 and rgb 8-8-8"
default y
endmenu
menu "Fonts"
config BR2_PACKAGE_QT_FONT_MICRO
bool "micro"
default y
config BR2_PACKAGE_QT_FONT_FIXED
bool "fixed"
default y
config BR2_PACKAGE_QT_FONT_HELVETICA
bool "helvetica"
default y
config BR2_PACKAGE_QT_FONT_JAPANESE
bool "japanese"
config BR2_PACKAGE_QT_FONT_UNIFONT
bool "unicode"
endmenu
endif # BR2_PACKAGE_QT_EMBEDDED
choice
prompt "freetype2 support"
default BR2_PACKAGE_QT_NOFREETYPE
help
Select freetype2 support.
config BR2_PACKAGE_QT_NOFREETYPE
bool "no freetype2 support"
depends on BR2_PACKAGE_QT_EMBEDDED
help
Do not compile in Freetype2 support.
comment "Qt freetype2 needs Qt embedded"
depends on BR2_PACKAGE_QT_X11
config BR2_PACKAGE_QT_QTFREETYPE
bool "Qt freetype2"
depends on BR2_PACKAGE_QT_EMBEDDED
help
Use the libfreetype bundled with Qt.
config BR2_PACKAGE_QT_SYSTEMFREETYPE
bool "System freetype2"
select BR2_PACKAGE_FREETYPE
help
Use shared libfreetype from the target system.
See http://www.freetype.org/
endchoice
config BR2_PACKAGE_QT_GIF
bool "Enable GIF support"
help
This compiles and installs the plugin for GIF reading support.
config BR2_PACKAGE_QT_LIBMNG
bool "Enable libmng support"
help
This compiles and installs the plugin for MNG support.
choice
prompt "JPEG support"
default BR2_PACKAGE_QT_NOJPEG
help
Select libjpeg support.
config BR2_PACKAGE_QT_NOJPEG
bool "No jpeg support"
help
Disable JPEG support
config BR2_PACKAGE_QT_SYSTEMJPEG
select BR2_PACKAGE_JPEG
bool "System libjpeg"
help
Link against system libjpeg
config BR2_PACKAGE_QT_QTJPEG
bool "Use Qt bundled libjpeg"
help
Link against libjpeg proveded with Qt
endchoice
choice
prompt "PNG support"
default BR2_PACKAGE_QT_NOPNG
help
Select which library to use if PNG support should be enabled.
config BR2_PACKAGE_QT_NOPNG
bool "No PNG support"
config BR2_PACKAGE_QT_SYSTEMPNG
bool "System libpng"
select BR2_PACKAGE_LIBPNG
config BR2_PACKAGE_QT_QTPNG
bool "Use Qt bundled libpng"
endchoice
choice
prompt "TIFF support"
default BR2_PACKAGE_QT_NOTIFF
help
Select which library to use if TIFF support should be enabled.
config BR2_PACKAGE_QT_NOTIFF
bool "No TIFF support"
config BR2_PACKAGE_QT_SYSTEMTIFF
bool "System libtiff"
select BR2_PACKAGE_TIFF
config BR2_PACKAGE_QT_QTTIFF
bool "Use Qt bundled libtiff"
endchoice
endif # BR2_PACKAGE_QT_GUI_MODULE
choice
prompt "zlib support"
default BR2_PACKAGE_QT_QTZLIB
help
Select zlib support.
config BR2_PACKAGE_QT_QTZLIB
bool "Qt zlib"
help
Use the zlib bundled with Qt.
config BR2_PACKAGE_QT_SYSTEMZLIB
bool "System zlib"
select BR2_PACKAGE_ZLIB
help
Use the shared zlib from the system.
endchoice
source "package/qt/Config.sql.in"
if BR2_PACKAGE_QT_GUI_MODULE
if BR2_PACKAGE_QT_EMBEDDED
source "package/qt/Config.gfx.in"
source "package/qt/Config.mouse.in"
source "package/qt/Config.keyboard.in"
endif
config BR2_PACKAGE_QT_PHONON
bool "Phonon Module"
depends on BR2_PACKAGE_GSTREAMER
select BR2_PACKAGE_GST_PLUGINS_BASE
default y
help
Build the Phonon module. Support for different audio/video
formats can be configured at the GStreamer package.
If unsure, say n.
comment "Phonon module needs gstreamer"
depends on !BR2_PACKAGE_GSTREAMER
config BR2_PACKAGE_QT_PHONON_BACKEND
bool "Phonon Module Backend"
depends on BR2_PACKAGE_QT_PHONON
help
Build the platform Phonon plugin.
If unsure, say n.
config BR2_PACKAGE_QT_OPENGL_ES
bool "OpenGL ES v2.x support"
depends on BR2_PACKAGE_HAS_LIBGLES
depends on BR2_PACKAGE_HAS_LIBEGL
help
Enable the OpenGL ES v2.x support.
endif
config BR2_PACKAGE_QT_DBUS
bool "DBus Module"
select BR2_PACKAGE_DBUS
depends on BR2_TOOLCHAIN_HAS_THREADS # dbus
depends on BR2_USE_MMU # dbus
help
Build the Qt DBus module.
comment "DBus Module needs a toolchain w/ threads"
depends on BR2_USE_MMU
depends on !BR2_TOOLCHAIN_HAS_THREADS
config BR2_PACKAGE_QT_XML
bool "XML Module"
default y
help
Build the XML module.
config BR2_PACKAGE_QT_XMLPATTERNS
bool "XML Patterns Module"
depends on BR2_PACKAGE_QT_XML
help
Build QtXmlPatterns module.
If unsure, say n
config BR2_PACKAGE_QT_MULTIMEDIA
bool "Multimedia Module"
depends on BR2_PACKAGE_QT_GUI_MODULE
help
Build QtMultimedia module.
config BR2_PACKAGE_QT_AUDIO_BACKEND
bool "QtMultimedia Audio backend"
depends on BR2_PACKAGE_QT_MULTIMEDIA
select BR2_PACKAGE_ALSA_LIB
depends on BR2_TOOLCHAIN_HAS_THREADS # alsa-lib
help
Build the ALSA audio backend into QtMultimedia
config BR2_PACKAGE_QT_SVG
bool "SVG Module"
depends on BR2_PACKAGE_QT_GUI_MODULE
help
Build the SVG module.
If unsure, say n
config BR2_PACKAGE_QT_NETWORK
bool "Network Module"
default y
help
Install the Network module.
if unsure, say y
config BR2_PACKAGE_QT_ARCH_SUPPORTS_WEBKIT
bool
# see src/3rdparty/webkit/Source/JavaScriptCore/wtf/Platform.h
# see http://lists.busybox.net/pipermail/buildroot/2014-November/112605.html
default y if BR2_arm || BR2_armeb || BR2_i386 || BR2_microblazeel || \
BR2_microblazebe || BR2_mips || BR2_mipsel || \
(BR2_mips64 || BR2_mips64el) && !BR2_MIPS_NABI32 || BR2_powerpc || \
BR2_powerpc64 || BR2_powerpc64el || BR2_sh4 || BR2_sh4eb || \
BR2_sh4a || BR2_sh4aeb || BR2_sparc || BR2_x86_64
config BR2_PACKAGE_QT_WEBKIT
bool "WebKit Module"
depends on BR2_PACKAGE_QT_SHARED
depends on BR2_PACKAGE_QT_GUI_MODULE
depends on BR2_PACKAGE_QT_NETWORK
depends on BR2_PACKAGE_QT_ARCH_SUPPORTS_WEBKIT
depends on BR2_TOOLCHAIN_HAS_THREADS_NPTL # needs pthread_getattr_np()
help
Build the WebKit module.
If unsure, say n.
comment "WebKit needs shared library/NPTL toolchain/gui/network support"
depends on !(BR2_PACKAGE_QT_SHARED && BR2_PACKAGE_QT_GUI_MODULE && BR2_PACKAGE_QT_NETWORK)
depends on !BR2_TOOLCHAIN_HAS_THREADS_NPTL
depends on BR2_PACKAGE_QT_ARCH_SUPPORTS_WEBKIT
config BR2_PACKAGE_QT_STL
bool "STL support"
help
Compile STL support.
If unsure, say n.
config BR2_PACKAGE_QT_OPENSSL
bool "Enable OpenSSL support"
depends on BR2_PACKAGE_QT_NETWORK
select BR2_PACKAGE_OPENSSL
help
Enable support for the OpenSSL encryption library. If you use
QSslSocket say y here, otherwise, say no to save space on the
target.
If unsure, say n.
config BR2_PACKAGE_QT_ARCH_SUPPORTS_SCRIPT
bool
# see http://lists.busybox.net/pipermail/buildroot/2014-November/112605.html
default y if BR2_arm || BR2_armeb || aarch64 || BR2_i386 || \
BR2_microblazeel || BR2_microblazebe || BR2_mips || BR2_mipsel || \
BR2_mips64 || BR2_mips64el || BR2_nios2 || BR2_powerpc || \
BR2_powerpc64 || BR2_powerpc64el || BR2_sh4 || BR2_sh4eb || \
BR2_sh4a || BR2_sh4aeb || BR2_sparc || BR2_x86_64
config BR2_PACKAGE_QT_SCRIPT
bool "Script Module"
depends on BR2_PACKAGE_QT_ARCH_SUPPORTS_SCRIPT
depends on BR2_TOOLCHAIN_HAS_THREADS_NPTL # needs pthread_getattr_np()
default y
help
Build the Qt Script module.
if unsure, say y.
comment "Script Module needs a toolchain with NPTL"
depends on !BR2_TOOLCHAIN_HAS_THREADS_NPTL
depends on BR2_PACKAGE_QT_ARCH_SUPPORTS_SCRIPT
config BR2_PACKAGE_QT_SCRIPTTOOLS
bool "Script Tools Module"
depends on BR2_PACKAGE_QT_SCRIPT
depends on BR2_PACKAGE_QT_GUI_MODULE
help
Build the Qt Script Tools module.
if unsure, say n.
config BR2_PACKAGE_QT_DECLARATIVE
bool "Declarative module"
depends on BR2_PACKAGE_QT_SCRIPT
depends on BR2_PACKAGE_QT_GUI_MODULE
depends on BR2_PACKAGE_QT_SQL_MODULE
help
Build the Qt Declarative Module for qml support
if unsure, say n.
config BR2_PACKAGE_QT_TEST
bool "Test Module"
help
Install the Test module.
endif # BR2_PACKAGE_QT
| {
"language": "Assembly"
} |
polygon
1
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END
END
| {
"language": "Assembly"
} |
#include "os.h"
#include <mp.h>
#include <libsec.h>
// decrypt rsa using garner's algorithm for the chinese remainder theorem
// seminumerical algorithms, knuth, pp 253-254
// applied cryptography, menezes et al, pg 612
mpint*
rsadecrypt(RSApriv *rsa, mpint *in, mpint *out)
{
mpint *v1, *v2;
if(out == nil)
out = mpnew(0);
// convert in to modular representation
v1 = mpnew(0);
mpmod(in, rsa->p, v1);
v2 = mpnew(0);
mpmod(in, rsa->q, v2);
// exponentiate the modular rep
mpexp(v1, rsa->kp, rsa->p, v1);
mpexp(v2, rsa->kq, rsa->q, v2);
// out = v1 + p*((v2-v1)*c2 mod q)
mpsub(v2, v1, v2);
mpmul(v2, rsa->c2, v2);
mpmod(v2, rsa->q, v2);
mpmul(v2, rsa->p, out);
mpadd(v1, out, out);
mpfree(v1);
mpfree(v2);
return out;
}
| {
"language": "Assembly"
} |
; **************************************************************************************************
; **************************************************************************************************
; THIS WILL NOT RUN ON REAL HARDWARE UNLESS YOU BURN THE NATIVE CODE AT THE BOTTOM
; OF THIS FILE INTO THE GIGATRONS ROM AT THE CORRECT ADDRESS, EMULATION ONLY!
; **************************************************************************************************
; **************************************************************************************************
; sprite test
vram EQU 0x0800
buff0 EQU 0x08A0
buff1 EQU 0x08A4
REENTER EQU 0x03CB
frameCount EQU 0x0E
sysFn EQU 0x22
srcAddr EQU 0x30
dstAddr EQU 0x32
backBuffer EQU 0x34
spriteData EQU 0x36
vbase EQU 0x38
pixels EQU 0x3A
xyPos EQU 0x3C
xyVel EQU 0x3E
frame EQU 0x40
rowBuffer0 EQU 0x50
rowBuffer1 EQU 0x54
rowBuffer2 EQU 0x58
rowBuffer3 EQU 0x5C
xExtent EQU 0x9C
yExtent EQU 0x74
_startAddress_ EQU 0x0200 ; entry point for the code, if this is missing defaults to 0x0200
_callTable_ EQU 0x007E ; call addresses are automatically stored here by the assembler, it grows downwards
; *NOTE* gt1 spec only allows for one zero page segment, .vasm files use this for the call table
; do *NOT* make this address higher than 0x00BE, it will conflict with future ROM loading mechanisms
; do *NOT* define constants, (DB or DW), between 0x30 -> 0x44 and 0xc0 -> 0xFF, these addresses are
; used by the loader and the vCPU stack, you can create variables in these areas as long as you don't
; corrupt your nested CALL return addresses on the stack
_singleStepWatch_ EQU xyPos ; the single step debugger watches this variable location to decide when to step,
; choose a variable that is updated often
SYS_SpriteRow_118 EQU 0x2300 ; 16 pixel memory copy
LDWI vram
STW vbase ; vram base address
STW pixels ; pixel address
LDWI 0x0101
STW xyPos
LDWI 0x0101
STW xyVel ; XY velocity
LDWI buff0
STW spriteData
LDWI buff1
STW backBuffer
LDWI SYS_SpriteRow_118
STW sysFn
LDW vbase ; generate vram address
ADDW xyPos
STW pixels
STW srcAddr
LDW backBuffer
STW dstAddr
SYS 118
LD frameCount
STW frame
xbounds LD xyPos ; x position bounds checking
BEQ xflip
SUBI xExtent
BLT ybounds
xflip LD xyVel
XORI 0xFE ; flip x velocity
ST xyVel
ybounds LD xyPos+1 ; y position bounds checking
BEQ yflip
SUBI yExtent
BLT velocity
yflip LD xyVel+1
XORI 0xFE ; flip y velocity
ST xyVel+1
velocity LD xyPos
ADDW xyVel
ST xyPos
LD xyPos+1
ADDW xyVel+1
ST xyPos+1
vblank LD frameCount
SUBW frame
BEQ vblank
LD frameCount
STW frame
LDW backBuffer
STW srcAddr
LDW pixels
STW dstAddr
SYS 118
LDW vbase ; generate vram address
ADDW xyPos
STW pixels
STW srcAddr
LDW backBuffer
STW dstAddr
SYS 118
LDW srcAddr
STW dstAddr
LDW spriteData
STW srcAddr
SYS 118
BRA xbounds
; native code routines that are written into the emulator's fake ROM using either the DBR/DWR commands or the native instruction set
; the native instruction assembler has access to the same functionality as the vasm assembler, (labels, equates, mutables, etc).
; it's only caveats are:
; 1: each instruction is prefaced with a period to clearly differentiate it from a vasm instruction
; 2: you cannot mix and match vasm instructions with native instructions within the same segment, (in reality they are executed in
; completely different parts of the memory map, i.e. native in fake ROM and vasm in RAM)
; 3: you must follow the SYS calling conventions exactly
SYS_SpriteRow_118 .LD [srcAddr],X ; src line 0
.LD [srcAddr+1],Y
.LD [Y,X]
.ST [rowBuffer0+0]
.ST [Y,X++] ; hack increment
.LD [Y,X]
.ST [rowBuffer0+1]
.ST [Y,X++] ; hack increment
.LD [Y,X]
.ST [rowBuffer0+2]
.ST [Y,X++] ; hack increment
.LD [Y,X]
.ST [rowBuffer0+3]
.LD [srcAddr],X ; src line1
.LD 0x01
.ADDA [srcAddr+1],Y
.LD [Y,X]
.ST [rowBuffer1+0]
.ST [Y,X++] ; hack increment
.LD [Y,X]
.ST [rowBuffer1+1]
.ST [Y,X++] ; hack increment
.LD [Y,X]
.ST [rowBuffer1+2]
.ST [Y,X++] ; hack increment
.LD [Y,X]
.ST [rowBuffer1+3]
.LD [srcAddr],X ; src line2
.LD 0x02
.ADDA [srcAddr+1],Y
.LD [Y,X]
.ST [rowBuffer2+0]
.ST [Y,X++] ; hack increment
.LD [Y,X]
.ST [rowBuffer2+1]
.ST [Y,X++] ; hack increment
.LD [Y,X]
.ST [rowBuffer2+2]
.ST [Y,X++] ; hack increment
.LD [Y,X]
.ST [rowBuffer2+3]
.LD [srcAddr],X ; src line3
.LD 0x03
.ADDA [srcAddr+1],Y
.LD [Y,X]
.ST [rowBuffer3+0]
.ST [Y,X++] ; hack increment
.LD [Y,X]
.ST [rowBuffer3+1]
.ST [Y,X++] ; hack increment
.LD [Y,X]
.ST [rowBuffer3+2]
.ST [Y,X++] ; hack increment
.LD [Y,X]
.ST [rowBuffer3+3]
.LD [dstAddr],X ; dst line 0
.LD [dstAddr+1],Y
.LD [rowBuffer0+0]
.ST [Y,X++]
.LD [rowBuffer0+1]
.ST [Y,X++]
.LD [rowBuffer0+2]
.ST [Y,X++]
.LD [rowBuffer0+3]
.ST [Y,X++]
.LD [dstAddr],X ; dst line 1
.LD 0x01
.ADDA [dstAddr+1],Y
.LD [rowBuffer1+0]
.ST [Y,X++]
.LD [rowBuffer1+1]
.ST [Y,X++]
.LD [rowBuffer1+2]
.ST [Y,X++]
.LD [rowBuffer1+3]
.ST [Y,X++]
.LD [dstAddr],X ; dst line 2
.LD 0x02
.ADDA [dstAddr+1],Y
.LD [rowBuffer2+0]
.ST [Y,X++]
.LD [rowBuffer2+1]
.ST [Y,X++]
.LD [rowBuffer2+2]
.ST [Y,X++]
.LD [rowBuffer2+3]
.ST [Y,X++]
.LD [dstAddr],X ; dst line 3
.LD 0x03
.ADDA [dstAddr+1],Y
.LD [rowBuffer3+0]
.ST [Y,X++]
.LD [rowBuffer3+1]
.ST [Y,X++]
.LD [rowBuffer3+2]
.ST [Y,X++]
.LD [rowBuffer3+3]
.ST [Y,X++]
.LD REENTER >>8,y
.JMP y,REENTER
.LD 0xC5 ; 0 - ((14 + number of instructions + 3) / 2), odd(14 + number of instructions) = true
| {
"language": "Assembly"
} |
; RUN: opt < %s -lowerinvoke -disable-output -enable-correct-eh-support
define i32 @foo() {
invoke i32 @foo( )
to label %Ok unwind label %Crap ; <i32>:1 [#uses=0]
Ok: ; preds = %0
invoke i32 @foo( )
to label %Ok2 unwind label %Crap ; <i32>:2 [#uses=0]
Ok2: ; preds = %Ok
ret i32 2
Crap: ; preds = %Ok, %0
ret i32 1
}
define i32 @bar(i32 %blah) {
br label %doit
doit: ; preds = %0
;; Value live across an unwind edge.
%B2 = add i32 %blah, 1 ; <i32> [#uses=1]
invoke i32 @foo( )
to label %Ok unwind label %Crap ; <i32>:1 [#uses=0]
Ok: ; preds = %doit
invoke i32 @foo( )
to label %Ok2 unwind label %Crap ; <i32>:2 [#uses=0]
Ok2: ; preds = %Ok
ret i32 2
Crap: ; preds = %Ok, %doit
ret i32 %B2
}
| {
"language": "Assembly"
} |
# Special mode for GDB that allows to debug/disassemble REAL MODE x86 code
#
# It has been designed to be used with QEMU or BOCHS gdb-stub
#
# 08/2011 Hugo Mercier - GPL v3 license
#
# Freely inspired from "A user-friendly gdb configuration file" widely available
# on the Internet
set confirm off
set verbose off
set prompt \033[31mreal-mode-gdb$ \033[0m
set output-radix 0d10
set input-radix 0d10
# These make gdb never pause in its output
set height 0
set width 0
# Intel syntax
set disassembly-flavor intel
# Real mode
#set architecture i8086
set $SHOW_CONTEXT = 1
set $REAL_MODE = 1
# By default A20 is present
set $ADDRESS_MASK = 0x1FFFFF
# nb of instructions to display
set $CODE_SIZE = 10
define enable-a20
set $ADDRESS_MASK = 0x1FFFFF
end
define disable-a20
set $ADDRESS_MASK = 0x0FFFFF
end
# convert segment:offset address to physical address
define r2p
if $argc < 2
printf "Arguments: segment offset\n"
else
set $ADDR = (((unsigned long)$arg0 & 0xFFFF) << 4) + (((unsigned long)$arg1 & 0xFFFF) & $ADDRESS_MASK)
printf "0x%05X\n", $ADDR
end
end
document r2p
Convert segment:offset address to physical address
Set the global variable $ADDR to the computed one
end
# get address of Interruption
define int_addr
if $argc < 1
printf "Argument: interruption_number\n"
else
set $offset = (unsigned short)*($arg0 * 4)
set $segment = (unsigned short)*($arg0 * 4 + 2)
r2p $segment $offset
printf "%04X:%04X\n", $segment, $offset
end
end
document int_addr
Get address of interruption
end
define compute_regs
set $rax = ((unsigned long)$eax & 0xFFFF)
set $rbx = ((unsigned long)$ebx & 0xFFFF)
set $rcx = ((unsigned long)$ecx & 0xFFFF)
set $rdx = ((unsigned long)$edx & 0xFFFF)
set $rsi = ((unsigned long)$esi & 0xFFFF)
set $rdi = ((unsigned long)$edi & 0xFFFF)
set $rbp = ((unsigned long)$ebp & 0xFFFF)
set $rsp = ((unsigned long)$esp & 0xFFFF)
set $rcs = ((unsigned long)$cs & 0xFFFF)
set $rds = ((unsigned long)$ds & 0xFFFF)
set $res = ((unsigned long)$es & 0xFFFF)
set $rss = ((unsigned long)$ss & 0xFFFF)
set $rip = ((((unsigned long)$cs & 0xFFFF) << 4) + ((unsigned long)$eip & 0xFFFF)) & $ADDRESS_MASK
set $r_ss_sp = ((((unsigned long)$ss & 0xFFFF) << 4) + ((unsigned long)$esp & 0xFFFF)) & $ADDRESS_MASK
set $r_ss_bp = ((((unsigned long)$ss & 0xFFFF) << 4) + ((unsigned long)$ebp & 0xFFFF)) & $ADDRESS_MASK
end
define print_regs
printf "AX: %04X BX: %04X ", $rax, $rbx
printf "CX: %04X DX: %04X\n", $rcx, $rdx
printf "SI: %04X DI: %04X ", $rsi, $rdi
printf "SP: %04X BP: %04X\n", $rsp, $rbp
printf "CS: %04X DS: %04X ", $rcs, $rds
printf "ES: %04X SS: %04X\n", $res, $rss
printf "\n"
printf "IP: %04X EIP:%08X\n", ((unsigned short)$eip & 0xFFFF), $eip
printf "CS:IP: %04X:%04X (0x%05X)\n", $rcs, ((unsigned short)$eip & 0xFFFF), $rip
printf "SS:SP: %04X:%04X (0x%05X)\n", $rss, $rsp, $r_ss_sp
printf "SS:BP: %04X:%04X (0x%05X)\n", $rss, $rbp, $r_ss_bp
end
document print_regs
Print CPU registers
end
define print_eflags
printf "OF <%d> DF <%d> IF <%d> TF <%d>",\
(($eflags >> 0xB) & 1), (($eflags >> 0xA) & 1), \
(($eflags >> 9) & 1), (($eflags >> 8) & 1)
printf " SF <%d> ZF <%d> AF <%d> PF <%d> CF <%d>\n",\
(($eflags >> 7) & 1), (($eflags >> 6) & 1),\
(($eflags >> 4) & 1), (($eflags >> 2) & 1), ($eflags & 1)
printf "ID <%d> VIP <%d> VIF <%d> AC <%d>",\
(($eflags >> 0x15) & 1), (($eflags >> 0x14) & 1), \
(($eflags >> 0x13) & 1), (($eflags >> 0x12) & 1)
printf " VM <%d> RF <%d> NT <%d> IOPL <%d>\n",\
(($eflags >> 0x11) & 1), (($eflags >> 0x10) & 1),\
(($eflags >> 0xE) & 1), (($eflags >> 0xC) & 3)
end
document print_eflags
Print eflags register.
end
# dump content of bytes in memory
# arg0 : addr
# arg1 : nb of bytes
define _dump_memb
if $argc < 2
printf "Arguments: address number_of_bytes\n"
else
set $_nb = $arg1
set $_i = 0
set $_addr = $arg0
while ($_i < $_nb)
printf "%02X ", *((unsigned char*)$_addr + $_i)
set $_i++
end
end
end
# dump content of memory in words
# arg0 : addr
# arg1 : nb of words
define _dump_memw
if $argc < 2
printf "Arguments: address number_of_words\n"
else
set $_nb = $arg1
set $_i = 0
set $_addr = $arg0
while ($_i < $_nb)
printf "%04X ", *((unsigned short*)$_addr + $_i)
set $_i++
end
end
end
# display data at given address
define print_data
if ($argc > 0)
set $seg = $arg0
set $off = $arg1
set $raddr = ($arg0 << 16) + $arg1
set $maddr = ($arg0 << 4) + $arg1
set $w = 16
set $i = (int)0
while ($i < 4)
printf "%08X: ", ($raddr + $i * $w)
set $j = (int)0
while ($j < $w)
printf "%02X ", *(unsigned char*)($maddr + $i * $w + $j)
set $j++
end
printf " "
set $j = (int)0
while ($j < $w)
set $c = *(unsigned char*)($maddr + $i * $w + $j)
if ($c > 32) && ($c < 128)
printf "%c", $c
else
printf "."
end
set $j++
end
printf "\n"
set $i++
end
end
end
define context
printf "---------------------------[ STACK ]---\n"
_dump_memw $r_ss_sp 8
printf "\n"
set $_a = $r_ss_sp + 16
_dump_memw $_a 8
printf "\n"
printf "---------------------------[ DS:SI ]---\n"
print_data $ds $rsi
printf "---------------------------[ ES:DI ]---\n"
print_data $es $rdi
printf "----------------------------[ CPU ]----\n"
print_regs
print_eflags
printf "---------------------------[ CODE ]----\n"
set $_code_size = $CODE_SIZE
# disassemble
# first call x/i with an address
# subsequent calls to x/i will increment address
if ($_code_size > 0)
x /i $rip
set $_code_size--
end
while ($_code_size > 0)
x /i
set $_code_size--
end
end
document context
Print context window, i.e. regs, stack, ds:esi and disassemble cs:eip.
end
define hook-stop
compute_regs
if ($SHOW_CONTEXT > 0)
context
end
end
document hook-stop
!!! FOR INTERNAL USE ONLY - DO NOT CALL !!!
end
# add a breakpoint on an interrupt
define break_int
set $offset = (unsigned short)*($arg0 * 4)
set $segment = (unsigned short)*($arg0 * 4 + 2)
break *$offset
end
define break_int_if_ah
if ($argc < 2)
printf "Arguments: INT_N AH\n"
else
set $addr = (unsigned short)*($arg0 * 4)
set $segment = (unsigned short)*($arg0 * 4 + 2)
break *$addr if ((unsigned long)$eax & 0xFF00) == ($arg1 << 8)
end
end
document break_int_if_ah
Install a breakpoint on INT N only if AH is equal to the expected value
end
define break_int_if_ax
if ($argc < 2)
printf "Arguments: INT_N AX\n"
else
set $addr = (unsigned short)*($arg0 * 4)
set $segment = (unsigned short)*($arg0 * 4 + 2)
break *$addr if ((unsigned long)$eax & 0xFFFF) == $arg1
end
end
document break_int_if_ax
Install a breakpoint on INT N only if AX is equal to the expected value
end
define stepo
## we know that an opcode starting by 0xE8 has a fixed length
## for the 0xFF opcodes, we can enumerate what is possible to have
set $lip = $rip
set $offset = 0
# first, get rid of segment prefixes, if any
set $_byte1 = *(unsigned char *)$rip
# CALL DS:xx CS:xx, etc.
if ($_byte1 == 0x3E || $_byte1 == 0x26 || $_byte1 == 0x2E || $_byte1 == 0x36 || $_byte1 == 0x3E || $_byte1 == 0x64 || $_byte1 == 0x65)
set $lip = $rip + 1
set $_byte1 = *(unsigned char*)$lip
set $offset = 1
end
set $_byte2 = *(unsigned char *)($lip+1)
set $_byte3 = *(unsigned char *)($lip+2)
set $noffset = 0
if ($_byte1 == 0xE8)
# call near
set $noffset = 3
else
if ($_byte1 == 0xFF)
# A "ModR/M" byte follows
set $_mod = ($_byte2 & 0xC0) >> 6
set $_reg = ($_byte2 & 0x38) >> 3
set $_rm = ($_byte2 & 7)
#printf "mod: %d reg: %d rm: %d\n", $_mod, $_reg, $_rm
# only for CALL instructions
if ($_reg == 2 || $_reg == 3)
# default offset
set $noffset = 2
if ($_mod == 0)
if ($_rm == 6)
# a 16bit address follows
set $noffset = 4
end
else
if ($_mod == 1)
# a 8bit displacement follows
set $noffset = 3
else
if ($_mod == 2)
# 16bit displacement
set $noffset = 4
end
end
end
end
# end of _reg == 2 or _reg == 3
else
# else byte1 != 0xff
if ($_byte1 == 0x9A)
# call far
set $noffset = 5
else
if ($_byte1 == 0xCD)
# INTERRUPT CASE
set $noffset = 2
end
end
end
# end of byte1 == 0xff
end
# else byte1 != 0xe8
# if we have found a call to bypass we set a temporary breakpoint on next instruction and continue
if ($noffset != 0)
set $_nextaddress = $eip + $offset + $noffset
printf "Setting BP to %04X\n", $_nextaddress
tbreak *$_nextaddress
continue
# else we just single step
else
nexti
end
end
document stepo
Step over calls
This function will set a temporary breakpoint on next instruction after the call so the call will be bypassed
You can safely use it instead nexti since it will single step code if it's not a call instruction (unless you want to go into the call function)
end
define step_until_iret
set $SHOW_CONTEXT=0
set $_found = 0
while (!$_found)
if (*(unsigned char*)$rip == 0xCF)
set $_found = 1
else
stepo
end
end
set $SHOW_CONTEXT=1
context
end
define step_until_ret
set $SHOW_CONTEXT=0
set $_found = 0
while (!$_found)
set $_p = *(unsigned char*)$rip
if ($_p == 0xC3 || $_p == 0xCB || $_p == 0xC2 || $_p == 0xCA)
set $_found = 1
else
stepo
end
end
set $SHOW_CONTEXT=1
context
end
define step_until_int
set $SHOW_CONTEXT = 0
while (*(unsigned char*)$rip != 0xCD)
stepo
end
set $SHOW_CONTEXT = 1
context
end
# Find a pattern in memory
# The pattern is given by a string as arg0
# If another argument is present it gives the starting address (0 otherwise)
define find_in_mem
if ($argc >= 2)
set $_addr = $arg1
else
set $_addr = 0
end
set $_found = 0
set $_tofind = $arg0
while ($_addr < $ADDRESS_MASK) && (!$_found)
if ($_addr % 0x100 == 0)
printf "%08X\n", $_addr
end
set $_i = 0
set $_found = 1
while ($_tofind[$_i] != 0 && $_found == 1)
set $_b = *((char*)$_addr + $_i)
set $_t = (char)$_tofind[$_i]
if ($_t != $_b)
set $_found = 0
end
set $_i++
end
if ($_found == 1)
printf "Code found at 0x%05X\n", $_addr
end
set $_addr++
end
end
document find_in_mem
Find a pattern in memory
The pattern is given by a string as arg0
If another argument is present it gives the starting address (0 otherwise)
end
define step_until_code
set $_tofind = $arg0
set $SHOW_CONTEXT = 0
set $_found = 0
while (!$_found)
set $_i = 0
set $_found = 1
while ($_tofind[$_i] != 0 && $_found == 1)
set $_b = *((char*)$rip + $_i)
set $_t = (char)$_tofind[$_i]
if ($_t != $_b)
set $_found = 0
end
set $_i++
end
if ($_found == 0)
stepo
end
end
set $SHOW_CONTEXT = 1
context
end
| {
"language": "Assembly"
} |
CODE (roll) ( "2 3 4 5 4 --> 2 4 5 5". See B311 )
CX POPx, CX 2 ADDxi, CALLn, lblchkPS @ RPCn, CX 2 SUBxi,
SI SP MOVxx, SI CX ADDxx,
DI SI MOVxx, DI 2 ADDxi, STD, REPZ, MOVSB,
;CODE
CODE 2DROP 2 chkPS, SP 4 ADDxi, ;CODE
CODE 2DUP 2 chkPS,
AX POPx, BX POPx,
BX PUSHx, AX PUSHx, BX PUSHx, AX PUSHx,
;CODE
CODE S0 AX PS_ADDR MOVxI, AX PUSHx, ;CODE
CODE 'S SP PUSHx, ;CODE
CODE AND 2 chkPS,
AX POPx, BX POPx, AX BX ANDxx, AX PUSHx, ;CODE
CODE OR 2 chkPS,
AX POPx, BX POPx, AX BX ORxx, AX PUSHx, ;CODE
| {
"language": "Assembly"
} |
var
_stack_top: record end; external name '_stack_top';
_data: record end; external name '_data';
_edata: record end; external name '_edata';
_text_start: record end; external name '_text_start';
_etext: record end; external name '_etext';
_bss_start: record end; external name '_bss_start';
_bss_end: record end; external name '_bss_end';
procedure Pascalmain; external name 'PASCALMAIN';
procedure HaltProc; assembler; nostackframe; public name'_haltproc';
asm
.Lloop:
b .Lloop
end;
procedure Startup; assembler; nostackframe; [public, alias: '_START'];
asm
ldr r1,.L_etext
ldr r2,.L_data
ldr r3,.L_edata
.Lcopyloop:
cmp r2,r3
ittt ls
ldrls r0,[r1],#4
strls r0,[r2],#4
bls .Lcopyloop
// clear onboard ram
ldr r1,.L_bss_start
ldr r2,.L_bss_end
mov r0,#0
.Lzeroloop:
cmp r1,r2
itt ls
strls r0,[r1],#4
bls .Lzeroloop
{$ifdef REMAP_VECTTAB}
ldr r0, .Lvtor
ldr r1, .Ltext_start
str r1, [r0]
{$endif REMAP_VECTTAB}
bl PASCALMAIN
b HaltProc
.L_bss_start:
.long _bss_start
.L_bss_end:
.long _bss_end
.L_etext:
.long _etext
.L_data:
.long _data
.L_edata:
.long _edata
{$ifdef REMAP_VECTTAB}
.Lvtor:
.long 0xE000ED08
.Ltext_start:
.long _text_start
{$endif REMAP_VECTTAB}
end; | {
"language": "Assembly"
} |
; PR1271
; RUN: opt < %s -instcombine -S | grep and
define i1 @test(i32 %tmp13) {
entry:
%tmp14 = shl i32 %tmp13, 12 ; <i32> [#uses=1]
%tmp15 = lshr i32 %tmp14, 12 ; <i32> [#uses=1]
%res = icmp ne i32 %tmp15, 0 ; <i1>:3 [#uses=1]
ret i1 %res
}
| {
"language": "Assembly"
} |
# SPDX-License-Identifier: GPL-2.0-only
config TEGRA_MC
bool "NVIDIA Tegra Memory Controller support"
default y
depends on ARCH_TEGRA
help
This driver supports the Memory Controller (MC) hardware found on
NVIDIA Tegra SoCs.
config TEGRA20_EMC
bool "NVIDIA Tegra20 External Memory Controller driver"
default y
depends on ARCH_TEGRA_2x_SOC
help
This driver is for the External Memory Controller (EMC) found on
Tegra20 chips. The EMC controls the external DRAM on the board.
This driver is required to change memory timings / clock rate for
external memory.
config TEGRA30_EMC
bool "NVIDIA Tegra30 External Memory Controller driver"
default y
depends on TEGRA_MC && ARCH_TEGRA_3x_SOC
help
This driver is for the External Memory Controller (EMC) found on
Tegra30 chips. The EMC controls the external DRAM on the board.
This driver is required to change memory timings / clock rate for
external memory.
config TEGRA124_EMC
bool "NVIDIA Tegra124 External Memory Controller driver"
default y
depends on TEGRA_MC && ARCH_TEGRA_124_SOC
help
This driver is for the External Memory Controller (EMC) found on
Tegra124 chips. The EMC controls the external DRAM on the board.
This driver is required to change memory timings / clock rate for
external memory.
config TEGRA210_EMC_TABLE
bool
depends on ARCH_TEGRA_210_SOC
config TEGRA210_EMC
tristate "NVIDIA Tegra210 External Memory Controller driver"
depends on TEGRA_MC && ARCH_TEGRA_210_SOC
select TEGRA210_EMC_TABLE
help
This driver is for the External Memory Controller (EMC) found on
Tegra210 chips. The EMC controls the external DRAM on the board.
This driver is required to change memory timings / clock rate for
external memory.
| {
"language": "Assembly"
} |
//Original:/testcases/core/c_cc2stat_cc_av1/c_cc2stat_cc_av1.dsp
// Spec Reference: cc2stat cc av1
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
// test CC = AV1 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AV1 = 0
CC = AV1; //
R0 = CC; //
imm32 R7, _AV1;
ASTAT = R7; // cc = 0, AV1 = 1
CC = AV1; //
R1 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV1 = 0
CC = AV1; //
R2 = CC; //
imm32 R7, (_CC|_AV1);
ASTAT = R7; // cc = 1, AV1 = 1
CC = AV1; //
R3 = CC; //
// test cc |= AV1 (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV1 = 0
CC |= AV1; //
R4 = CC; //
imm32 R7, _AV1;
ASTAT = R7; // cc = 0, AV1 = 1
CC |= AV1; //
R5 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV1 = 0
CC |= AV1; //
R6 = CC; //
imm32 R7, (_CC|_AV1);
ASTAT = R7; // cc = 1, AV1 = 1
CC |= AV1; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _SET;
CHECKREG r6, _SET;
CHECKREG r7, _SET;
// test CC &= AV1 (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV1 = 0
CC &= AV1; //
R4 = CC; //
imm32 R7, _AV1;
ASTAT = R7; // cc = 0, AV1 = 1
CC &= AV1; //
R5 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV1 = 0
CC &= AV1; //
R6 = CC; //
imm32 R7, (_CC|_AV1);
ASTAT = R7; // cc = 1, AV1 = 1
CC &= AV1; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _UNSET;
CHECKREG r6, _UNSET;
CHECKREG r7, _SET;
// test CC ^= AV1 (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV1 = 0
CC ^= AV1; //
R4 = CC; //
imm32 R7, _AV1;
ASTAT = R7; // cc = 0, AV1 = 1
CC ^= AV1; //
R5 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV1 = 0
CC ^= AV1; //
R6 = CC; //
imm32 R7, (_CC|_AV1);
ASTAT = R7; // cc = 1, AV1 = 1
CC ^= AV1; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _SET;
CHECKREG r6, _SET;
CHECKREG r7, _UNSET;
// test AV1 = CC 0-0, 0-1, 1-0, 1-1
R7 = 0x00;
ASTAT = R7; // cc = 0, AV1 = 0
AV1 = CC; //
R0 = ASTAT; //
imm32 R7, _AV1;
ASTAT = R7; // cc = 0, AV1 = 1
AV1 = CC; //
R1 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV1 = 0
AV1 = CC; //
R2 = ASTAT; //
imm32 R7, (_CC|_AV1);
ASTAT = R7; // cc = 1, AV1 = 1
AV1 = CC; //
R3 = ASTAT; //
// test AV1 |= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV1 = 0
AV1 |= CC; //
R4 = ASTAT; //
imm32 R7, _AV1;
ASTAT = R7; // cc = 0, AV1 = 1
AV1 |= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV1 = 0
AV1 |= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AV1);
ASTAT = R7; // cc = 1, AV1 = 1
AV1 |= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AV1);
CHECKREG r3, (_CC|_AV1);
CHECKREG r4, _UNSET;
CHECKREG r5, _AV1;
CHECKREG r6, (_CC|_AV1);
CHECKREG r7, (_CC|_AV1);
// test AV1 &= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV1 = 0
AV1 &= CC; //
R4 = ASTAT; //
imm32 R7, _AV1;
ASTAT = R7; // cc = 0, AV1 = 1
AV1 &= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV1 = 0
AV1 &= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AV1);
ASTAT = R7; // cc = 1, AV1 = 1
AV1 &= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AV1);
CHECKREG r3, (_CC|_AV1);
CHECKREG r4, _UNSET;
CHECKREG r5, _UNSET;
CHECKREG r6, _CC;
CHECKREG r7, (_CC|_AV1);
// test AV1 ^= CC (0-0, 0-1, 1-0, 1-1)
R7 = 0x00;
ASTAT = R7; // cc = 0, AV1 = 0
AV1 ^= CC; //
R4 = ASTAT; //
imm32 R7, _AV1;
ASTAT = R7; // cc = 0, AV1 = 1
AV1 ^= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AV1 = 0
AV1 ^= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AV1);
ASTAT = R7; // cc = 1, AV1 = 1
AV1 ^= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AV1);
CHECKREG r3, (_CC|_AV1);
CHECKREG r4, _UNSET;
CHECKREG r5, _AV1;
CHECKREG r6, (_CC|_AV1);
CHECKREG r7, _CC;
pass
| {
"language": "Assembly"
} |
; money_into_atm:
; Uses PW ramps
byte 0x2d ;Gate Ramp ADSR Wave
byte 0x0,0x8,0x20,0x0,0xd0,0xff ; Start_Freq,Duration,Increment
byte 0x94,0xb9 ; ADSR
byte 0x50 ; Waveform
byte 0x10 ;Extd
byte 0x4 ; Extended Command ByteDur
byte 0x80,0x0 ; Set Duration
byte 0x20 ;Wave
byte 0x0 ; Waveform
byte 0x2 ;Stop
byte 0x0 ; next_sfx_number
; money_into_atm.pw:
; Pulsewidth Ramp starts here
byte 0x5 ;Gate Ramp
byte 0x0,0x4,0x7,0x0,0x60,0x4 ; Start_Freq,Duration,Increment
byte 0x80 ;loop
byte 0x7,0x1 ; reverse_rel_branch,count
byte 0x2 ;Stop
byte 0x0 ; next_sfx_number
| {
"language": "Assembly"
} |
function overlap_1 (.text) {
0x4000d5: eax = -1144978688
0x4000da: ecx = 83886080
0x4000df: eax += ecx
0x4000e1: jmp ret_0x4000d7
ret_0x4000d7:
0x4000d7: eax += ecx
0x4000d9: ebx = 185
0x4000de: eax += -185874431
0x4000e3: eax += ebx
0x4000e5: ret
}
function overlap_2 (.text) {
0x4000e6: ecx = 0
0x4000e8: ecx--
0x4000ea: ecx++
# 0x4000ec: jne 0x4000ef
if == {
0x4000ee: eax = -555169487
}
unk_4000ef:
0x4000ef: ecx = 0
loop {
loop:
0x4000f1: call obfuscated_call
0x4000f6: ecx++
# 0x4000f8: cmp ecx, 0xf
# 0x4000fb: jle 0x4000f1
if (ecx > 15) goto break_0x4000fd
} ; loop
break_0x4000fd:
0x4000fd: ret
}
| {
"language": "Assembly"
} |
; RUN: opt -loop-unswitch -verify-loop-info -verify-dom-info -disable-output < %s
; Loop unswitch should be able to unswitch these loops and
; preserve LCSSA and LoopSimplify forms.
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv6-apple-darwin9"
@delim1 = external global i32 ; <i32*> [#uses=1]
@delim2 = external global i32 ; <i32*> [#uses=1]
define i32 @ineqn(i8* %s, i8* %p) nounwind readonly {
entry:
%0 = load i32, i32* @delim1, align 4 ; <i32> [#uses=1]
%1 = load i32, i32* @delim2, align 4 ; <i32> [#uses=1]
br label %bb8.outer
bb: ; preds = %bb8
%2 = icmp eq i8* %p_addr.0, %s ; <i1> [#uses=1]
br i1 %2, label %bb10, label %bb2
bb2: ; preds = %bb
%3 = getelementptr inbounds i8, i8* %p_addr.0, i32 1 ; <i8*> [#uses=3]
switch i32 %ineq.0.ph, label %bb8.backedge [
i32 0, label %bb3
i32 1, label %bb6
]
bb8.backedge: ; preds = %bb6, %bb5, %bb2
br label %bb8
bb3: ; preds = %bb2
%4 = icmp eq i32 %8, %0 ; <i1> [#uses=1]
br i1 %4, label %bb8.outer.loopexit, label %bb5
bb5: ; preds = %bb3
br i1 %6, label %bb6, label %bb8.backedge
bb6: ; preds = %bb5, %bb2
%5 = icmp eq i32 %8, %1 ; <i1> [#uses=1]
br i1 %5, label %bb7, label %bb8.backedge
bb7: ; preds = %bb6
%.lcssa1 = phi i8* [ %3, %bb6 ] ; <i8*> [#uses=1]
br label %bb8.outer.backedge
bb8.outer.backedge: ; preds = %bb8.outer.loopexit, %bb7
%.lcssa2 = phi i8* [ %.lcssa1, %bb7 ], [ %.lcssa, %bb8.outer.loopexit ] ; <i8*> [#uses=1]
%ineq.0.ph.be = phi i32 [ 0, %bb7 ], [ 1, %bb8.outer.loopexit ] ; <i32> [#uses=1]
br label %bb8.outer
bb8.outer.loopexit: ; preds = %bb3
%.lcssa = phi i8* [ %3, %bb3 ] ; <i8*> [#uses=1]
br label %bb8.outer.backedge
bb8.outer: ; preds = %bb8.outer.backedge, %entry
%ineq.0.ph = phi i32 [ 0, %entry ], [ %ineq.0.ph.be, %bb8.outer.backedge ] ; <i32> [#uses=3]
%p_addr.0.ph = phi i8* [ %p, %entry ], [ %.lcssa2, %bb8.outer.backedge ] ; <i8*> [#uses=1]
%6 = icmp eq i32 %ineq.0.ph, 1 ; <i1> [#uses=1]
br label %bb8
bb8: ; preds = %bb8.outer, %bb8.backedge
%p_addr.0 = phi i8* [ %p_addr.0.ph, %bb8.outer ], [ %3, %bb8.backedge ] ; <i8*> [#uses=3]
%7 = load i8, i8* %p_addr.0, align 1 ; <i8> [#uses=2]
%8 = sext i8 %7 to i32 ; <i32> [#uses=2]
%9 = icmp eq i8 %7, 0 ; <i1> [#uses=1]
br i1 %9, label %bb10, label %bb
bb10: ; preds = %bb8, %bb
%.0 = phi i32 [ %ineq.0.ph, %bb ], [ 0, %bb8 ] ; <i32> [#uses=1]
ret i32 %.0
}
; This is a simplified form of ineqn from above. It triggers some
; different cases in the loop-unswitch code.
define void @simplified_ineqn() nounwind readonly {
entry:
br label %bb8.outer
bb8.outer: ; preds = %bb6, %bb2, %entry
%x = phi i32 [ 0, %entry ], [ 0, %bb6 ], [ 1, %bb2 ] ; <i32> [#uses=1]
br i1 undef, label %return, label %bb2
bb2: ; preds = %bb
switch i32 %x, label %bb6 [
i32 0, label %bb8.outer
]
bb6: ; preds = %bb2
br i1 undef, label %bb8.outer, label %bb2
return: ; preds = %bb8, %bb
ret void
}
; This function requires special handling to preserve LCSSA form.
; PR4934
define void @pnp_check_irq() nounwind noredzone {
entry:
%conv56 = trunc i64 undef to i32 ; <i32> [#uses=1]
br label %while.cond.i
while.cond.i: ; preds = %while.cond.i.backedge, %entry
%call.i25 = call i8* @pci_get_device() nounwind noredzone ; <i8*> [#uses=2]
br i1 undef, label %if.then65, label %while.body.i
while.body.i: ; preds = %while.cond.i
br i1 undef, label %if.then31.i.i, label %while.cond.i.backedge
while.cond.i.backedge: ; preds = %if.then31.i.i, %while.body.i
br label %while.cond.i
if.then31.i.i: ; preds = %while.body.i
switch i32 %conv56, label %while.cond.i.backedge [
i32 14, label %if.then42.i.i
i32 15, label %if.then42.i.i
]
if.then42.i.i: ; preds = %if.then31.i.i, %if.then31.i.i
%call.i25.lcssa48 = phi i8* [ %call.i25, %if.then31.i.i ], [ %call.i25, %if.then31.i.i ] ; <i8*> [#uses=0]
unreachable
if.then65: ; preds = %while.cond.i
unreachable
}
declare i8* @pci_get_device() noredzone
| {
"language": "Assembly"
} |
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* or http://www.opensolaris.org/os/licensing.
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1995,1999 by Sun Microsystems, Inc.
* All rights reserved.
*/
/*
* sysconfig_impl.h:
*
* platform-specific variables for the SUN private sysconfig syscall
*
*/
#ifndef _SYS_SYSCONFIG_IMPL_H
#define _SYS_SYSCONFIG_IMPL_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* _SYS_SYSCONFIG_IMPL_H */
| {
"language": "Assembly"
} |
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System calls for 386, Linux
//
// See ../runtime/sys_linux_386.s for the reason why we always use int 0x80
// instead of the glibc-specific "CALL 0x10(GS)".
#define INVOKE_SYSCALL INT $0x80
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-28
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-40
JMP syscall·Syscall6(SB)
TEXT ·SyscallNoError(SB),NOSPLIT,$0-24
CALL runtime·entersyscall(SB)
MOVL trap+0(FP), AX // syscall entry
MOVL a1+4(FP), BX
MOVL a2+8(FP), CX
MOVL a3+12(FP), DX
MOVL $0, SI
MOVL $0, DI
INVOKE_SYSCALL
MOVL AX, r1+16(FP)
MOVL DX, r2+20(FP)
CALL runtime·exitsyscall(SB)
RET
TEXT ·RawSyscall(SB),NOSPLIT,$0-28
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-40
JMP syscall·RawSyscall6(SB)
TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-24
MOVL trap+0(FP), AX // syscall entry
MOVL a1+4(FP), BX
MOVL a2+8(FP), CX
MOVL a3+12(FP), DX
MOVL $0, SI
MOVL $0, DI
INVOKE_SYSCALL
MOVL AX, r1+16(FP)
MOVL DX, r2+20(FP)
RET
TEXT ·socketcall(SB),NOSPLIT,$0-36
JMP syscall·socketcall(SB)
TEXT ·rawsocketcall(SB),NOSPLIT,$0-36
JMP syscall·rawsocketcall(SB)
TEXT ·seek(SB),NOSPLIT,$0-28
JMP syscall·seek(SB)
| {
"language": "Assembly"
} |
.late_rodata
glabel D_80AD7254
.float 3000.0
glabel D_80AD7258
.float 0.2
glabel D_80AD725C
.float 1500.0
.text
glabel func_80AD4CA4
/* 011A4 80AD4CA4 27BDFFD8 */ addiu $sp, $sp, 0xFFD8 ## $sp = FFFFFFD8
/* 011A8 80AD4CA8 AFB00018 */ sw $s0, 0x0018($sp)
/* 011AC 80AD4CAC 00808025 */ or $s0, $a0, $zero ## $s0 = 00000000
/* 011B0 80AD4CB0 AFBF001C */ sw $ra, 0x001C($sp)
/* 011B4 80AD4CB4 AFA5002C */ sw $a1, 0x002C($sp)
/* 011B8 80AD4CB8 0C02927F */ jal SkelAnime_FrameUpdateMatrix
/* 011BC 80AD4CBC 2484014C */ addiu $a0, $a0, 0x014C ## $a0 = 0000014C
/* 011C0 80AD4CC0 86030196 */ lh $v1, 0x0196($s0) ## 00000196
/* 011C4 80AD4CC4 02002025 */ or $a0, $s0, $zero ## $a0 = 00000000
/* 011C8 80AD4CC8 3C0580AD */ lui $a1, %hi(D_80AD7104) ## $a1 = 80AD0000
/* 011CC 80AD4CCC 10600002 */ beq $v1, $zero, .L80AD4CD8
/* 011D0 80AD4CD0 246EFFFF */ addiu $t6, $v1, 0xFFFF ## $t6 = FFFFFFFF
/* 011D4 80AD4CD4 A60E0196 */ sh $t6, 0x0196($s0) ## 00000196
.L80AD4CD8:
/* 011D8 80AD4CD8 0C00B6EC */ jal func_8002DBB0
/* 011DC 80AD4CDC 24A57104 */ addiu $a1, $a1, %lo(D_80AD7104) ## $a1 = 80AD7104
/* 011E0 80AD4CE0 3C0180AD */ lui $at, %hi(D_80AD7254) ## $at = 80AD0000
/* 011E4 80AD4CE4 C4247254 */ lwc1 $f4, %lo(D_80AD7254)($at)
/* 011E8 80AD4CE8 02002025 */ or $a0, $s0, $zero ## $a0 = 00000000
/* 011EC 80AD4CEC 3C0580AD */ lui $a1, %hi(D_80AD7104) ## $a1 = 80AD0000
/* 011F0 80AD4CF0 4600203C */ c.lt.s $f4, $f0
/* 011F4 80AD4CF4 00004025 */ or $t0, $zero, $zero ## $t0 = 00000000
/* 011F8 80AD4CF8 45020015 */ bc1fl .L80AD4D50
/* 011FC 80AD4CFC 8603008A */ lh $v1, 0x008A($s0) ## 0000008A
/* 01200 80AD4D00 0C00B6B0 */ jal func_8002DAC0
/* 01204 80AD4D04 24A57104 */ addiu $a1, $a1, %lo(D_80AD7104) ## $a1 = 80AD7104
/* 01208 80AD4D08 8603008A */ lh $v1, 0x008A($s0) ## 0000008A
/* 0120C 80AD4D0C 24018000 */ addiu $at, $zero, 0x8000 ## $at = FFFF8000
/* 01210 80AD4D10 00627823 */ subu $t7, $v1, $v0
/* 01214 80AD4D14 01E1C021 */ addu $t8, $t7, $at
/* 01218 80AD4D18 0018CC00 */ sll $t9, $t8, 16
/* 0121C 80AD4D1C 00194C03 */ sra $t1, $t9, 16
/* 01220 80AD4D20 44893000 */ mtc1 $t1, $f6 ## $f6 = 0.00
/* 01224 80AD4D24 3C0180AD */ lui $at, %hi(D_80AD7258) ## $at = 80AD0000
/* 01228 80AD4D28 C42A7258 */ lwc1 $f10, %lo(D_80AD7258)($at)
/* 0122C 80AD4D2C 46803220 */ cvt.s.w $f8, $f6
/* 01230 80AD4D30 460A4402 */ mul.s $f16, $f8, $f10
/* 01234 80AD4D34 4600848D */ trunc.w.s $f18, $f16
/* 01238 80AD4D38 44089000 */ mfc1 $t0, $f18
/* 0123C 80AD4D3C 00000000 */ nop
/* 01240 80AD4D40 00084400 */ sll $t0, $t0, 16
/* 01244 80AD4D44 10000002 */ beq $zero, $zero, .L80AD4D50
/* 01248 80AD4D48 00084403 */ sra $t0, $t0, 16
/* 0124C 80AD4D4C 8603008A */ lh $v1, 0x008A($s0) ## 0000008A
.L80AD4D50:
/* 01250 80AD4D50 00682823 */ subu $a1, $v1, $t0
/* 01254 80AD4D54 00052C00 */ sll $a1, $a1, 16
/* 01258 80AD4D58 00052C03 */ sra $a1, $a1, 16
/* 0125C 80AD4D5C 260400B6 */ addiu $a0, $s0, 0x00B6 ## $a0 = 000000B6
/* 01260 80AD4D60 24060006 */ addiu $a2, $zero, 0x0006 ## $a2 = 00000006
/* 01264 80AD4D64 0C01E1EF */ jal Math_SmoothScaleMaxS
/* 01268 80AD4D68 24070400 */ addiu $a3, $zero, 0x0400 ## $a3 = 00000400
/* 0126C 80AD4D6C 02002025 */ or $a0, $s0, $zero ## $a0 = 00000000
/* 01270 80AD4D70 0C2B5155 */ jal func_80AD4554
/* 01274 80AD4D74 8FA5002C */ lw $a1, 0x002C($sp)
/* 01278 80AD4D78 86040196 */ lh $a0, 0x0196($s0) ## 00000196
/* 0127C 80AD4D7C 860B00B6 */ lh $t3, 0x00B6($s0) ## 000000B6
/* 01280 80AD4D80 34018000 */ ori $at, $zero, 0x8000 ## $at = 00008000
/* 01284 80AD4D84 000422C0 */ sll $a0, $a0, 11
/* 01288 80AD4D88 00042400 */ sll $a0, $a0, 16
/* 0128C 80AD4D8C 01616021 */ addu $t4, $t3, $at
/* 01290 80AD4D90 A60C0032 */ sh $t4, 0x0032($s0) ## 00000032
/* 01294 80AD4D94 0C01DE1C */ jal Math_Sins
## sins?
/* 01298 80AD4D98 00042403 */ sra $a0, $a0, 16
/* 0129C 80AD4D9C 3C014040 */ lui $at, 0x4040 ## $at = 40400000
/* 012A0 80AD4DA0 44812000 */ mtc1 $at, $f4 ## $f4 = 3.00
/* 012A4 80AD4DA4 00000000 */ nop
/* 012A8 80AD4DA8 46040182 */ mul.s $f6, $f0, $f4
/* 012AC 80AD4DAC E7A60024 */ swc1 $f6, 0x0024($sp)
/* 012B0 80AD4DB0 0C01DE0D */ jal Math_Coss
## coss?
/* 012B4 80AD4DB4 860400B6 */ lh $a0, 0x00B6($s0) ## 000000B6
/* 012B8 80AD4DB8 C7AA0024 */ lwc1 $f10, 0x0024($sp)
/* 012BC 80AD4DBC C6080024 */ lwc1 $f8, 0x0024($s0) ## 00000024
/* 012C0 80AD4DC0 860400B6 */ lh $a0, 0x00B6($s0) ## 000000B6
/* 012C4 80AD4DC4 46005402 */ mul.s $f16, $f10, $f0
/* 012C8 80AD4DC8 46104481 */ sub.s $f18, $f8, $f16
/* 012CC 80AD4DCC 0C01DE1C */ jal Math_Sins
## sins?
/* 012D0 80AD4DD0 E6120024 */ swc1 $f18, 0x0024($s0) ## 00000024
/* 012D4 80AD4DD4 C7A60024 */ lwc1 $f6, 0x0024($sp)
/* 012D8 80AD4DD8 C604002C */ lwc1 $f4, 0x002C($s0) ## 0000002C
/* 012DC 80AD4DDC 860D0196 */ lh $t5, 0x0196($s0) ## 00000196
/* 012E0 80AD4DE0 46003282 */ mul.s $f10, $f6, $f0
/* 012E4 80AD4DE4 3C0180AD */ lui $at, %hi(D_80AD725C) ## $at = 80AD0000
/* 012E8 80AD4DE8 460A2200 */ add.s $f8, $f4, $f10
/* 012EC 80AD4DEC 11A00008 */ beq $t5, $zero, .L80AD4E10
/* 012F0 80AD4DF0 E608002C */ swc1 $f8, 0x002C($s0) ## 0000002C
/* 012F4 80AD4DF4 C430725C */ lwc1 $f16, %lo(D_80AD725C)($at)
/* 012F8 80AD4DF8 C6120090 */ lwc1 $f18, 0x0090($s0) ## 00000090
/* 012FC 80AD4DFC 02002025 */ or $a0, $s0, $zero ## $a0 = 00000000
/* 01300 80AD4E00 4612803C */ c.lt.s $f16, $f18
/* 01304 80AD4E04 00000000 */ nop
/* 01308 80AD4E08 45000005 */ bc1f .L80AD4E20
/* 0130C 80AD4E0C 00000000 */ nop
.L80AD4E10:
/* 01310 80AD4E10 0C2B5064 */ jal func_80AD4190
/* 01314 80AD4E14 02002025 */ or $a0, $s0, $zero ## $a0 = 00000000
/* 01318 80AD4E18 10000004 */ beq $zero, $zero, .L80AD4E2C
/* 0131C 80AD4E1C 02002025 */ or $a0, $s0, $zero ## $a0 = 00000000
.L80AD4E20:
/* 01320 80AD4E20 0C2B511C */ jal func_80AD4470
/* 01324 80AD4E24 8FA5002C */ lw $a1, 0x002C($sp)
/* 01328 80AD4E28 02002025 */ or $a0, $s0, $zero ## $a0 = 00000000
.L80AD4E2C:
/* 0132C 80AD4E2C 0C00BE5D */ jal func_8002F974
/* 01330 80AD4E30 24053072 */ addiu $a1, $zero, 0x3072 ## $a1 = 00003072
/* 01334 80AD4E34 8FBF001C */ lw $ra, 0x001C($sp)
/* 01338 80AD4E38 8FB00018 */ lw $s0, 0x0018($sp)
/* 0133C 80AD4E3C 27BD0028 */ addiu $sp, $sp, 0x0028 ## $sp = 00000000
/* 01340 80AD4E40 03E00008 */ jr $ra
/* 01344 80AD4E44 00000000 */ nop
| {
"language": "Assembly"
} |
#include "z_en_nb.h"
#define FLAGS 0x00000039
#define THIS ((EnNb*)thisx)
void EnNb_Init(Actor* thisx, GlobalContext* globalCtx);
void EnNb_Destroy(Actor* thisx, GlobalContext* globalCtx);
void EnNb_Update(Actor* thisx, GlobalContext* globalCtx);
void EnNb_Draw(Actor* thisx, GlobalContext* globalCtx);
/*
const ActorInit En_Nb_InitVars = {
ACTOR_EN_NB,
ACTORTYPE_NPC,
FLAGS,
OBJECT_NB,
sizeof(EnNb),
(ActorFunc)EnNb_Init,
(ActorFunc)EnNb_Destroy,
(ActorFunc)EnNb_Update,
(ActorFunc)EnNb_Draw
};
*/
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BBFDB0.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BBFE60.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BBFE8C.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BBFF24.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BBFF90.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BBFFD4.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC0050.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC00AC.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC01DC.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC045C.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC04FC.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC05A8.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC06C4.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC0800.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC08E0.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC0978.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC0A18.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC0B98.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC0C0C.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC0C80.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC0D08.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC0D1C.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC0D84.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC0EAC.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/EnNb_Init.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/EnNb_Destroy.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/EnNb_Update.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC1174.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC11B4.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/func_80BC1278.asm")
GLOBAL_ASM("asm/non_matchings/ovl_En_Nb_0x80BBFDB0/EnNb_Draw.asm")
| {
"language": "Assembly"
} |
// Copyright 2018 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System calls for ppc64, AIX are implemented in runtime/syscall_aix.go
//
TEXT ·syscall6(SB),NOSPLIT,$0-88
JMP syscall·syscall6(SB)
TEXT ·rawSyscall6(SB),NOSPLIT,$0-88
JMP syscall·rawSyscall6(SB)
| {
"language": "Assembly"
} |
config BR2_PACKAGE_NCDU
bool "ncdu"
depends on BR2_USE_MMU # system()
select BR2_PACKAGE_NCURSES
help
ncdu is a disk usage analyzer with an ncurses interface
http://dev.yorhel.nl/ncdu
| {
"language": "Assembly"
} |
// RUN: rm -rf %t
// RUN: mkdir %t
// RUN: cp -r %S/Inputs/include-relative %t/include-relative
// RUN: cd %t
// RUN: %clang_cc1 -fmodules -fimplicit-module-maps -x c -verify -fmodules-cache-path=%t -I include-relative %s
// expected-no-diagnostics
#include "a.h"
int f() { return n; }
| {
"language": "Assembly"
} |
# Copyright 2013 the V8 project authors. All rights reserved.
# Copyright (C) 2005, 2006, 2007, 2008, 2009 Apple Inc. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY APPLE INC. AND ITS CONTRIBUTORS ``AS IS'' AND ANY
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR ITS CONTRIBUTORS BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Test for regression against REGRESSION: RegExp("[^\s$]+", "g") returns extra matches
On success, you will see a series of "PASS" messages, followed by "TEST COMPLETE".
PASS while (match = re.exec(" abcdefg")) accumulate += match + "; "; accumulate is "abcdefg; "
PASS while (match = re.exec("123456789")) accumulate += match + "; "; accumulate is "1; 2; 3; 4; 5; 6; 7; 8; 9; "
PASS successfullyParsed is true
TEST COMPLETE
| {
"language": "Assembly"
} |
; RUN: opt < %s -loop-simplify -licm -disable-output
define void @main() {
entry:
br i1 false, label %Out, label %loop
loop: ; preds = %loop, %entry
%LI = icmp sgt i32 0, 0 ; <i1> [#uses=1]
br i1 %LI, label %loop, label %Out
Out: ; preds = %loop, %entry
ret void
}
| {
"language": "Assembly"
} |
/*
* Moniker generated from PCX/1record.pcx with pixel 13 masked out
*/
@visMoniker NewRecordSCGAMoniker = {
size = standard;
style = icon;
aspectRatio = verySquished;
color = gray1;
cachedSize = 32, 18;
gstring {
GSFillBitmapAtCP(72),
Bitmap (32,18,BMC_PACKBITS,BMF_MONO),
0xfd, 0x00,
0xfd, 0x00,
0x03, 0x08, 0x00, 0x00, 0x20,
0x03, 0x04, 0x00, 0x00, 0x40,
0xfd, 0x00,
0xfd, 0x00,
0x03, 0x00, 0xff, 0xfe, 0x00,
0x03, 0x00, 0x80, 0x02, 0x00,
0x03, 0x00, 0x80, 0x02, 0x00,
0x03, 0x0c, 0x80, 0x02, 0x30,
0x03, 0x00, 0x80, 0x02, 0x00,
0x03, 0x00, 0xff, 0xfe, 0x00,
0xfd, 0x00,
0xfd, 0x00,
0x03, 0x02, 0x00, 0x00, 0x20,
0x03, 0x04, 0x00, 0x00, 0x10,
0xfd, 0x00,
0xfd, 0x00,
GSEndString()
}
}
| {
"language": "Assembly"
} |
/*
decode_3dnow.s - 3DNow! optimized synth_1to1()
copyright ?-2007 by the mpg123 project - free software under the terms of the LGPL 2.1
see COPYING and AUTHORS files in distribution or http://mpg123.org
initially written by Syuuhei Kashiyama
This code based 'decode_3dnow.s' by Syuuhei Kashiyama
<squash@mb.kcom.ne.jp>,only two types of changes have been made:
- remove PREFETCH instruction for speedup
- change function name for support 3DNow! automatic detect
- femms moved to before 'call dct64_3dnow'
You can find Kashiyama's original 3dnow! support patch
(for mpg123-0.59o) at
http://user.ecc.u-tokyo.ac.jp/~g810370/linux-simd/ (Japanese).
by KIMURA Takuhiro <kim@hannah.ipc.miyakyo-u.ac.jp> - until 31.Mar.1999
<kim@comtec.co.jp> - after 1.Apr.1999
Replacement of synth_1to1() with AMD's 3DNow! SIMD operations support
Syuuhei Kashiyama <squash@mb.kcom.ne.jp>
The author of this program disclaim whole expressed or implied
warranties with regard to this program, and in no event shall the
author of this program liable to whatever resulted from the use of
this program. Use it at your own risk.
*/
#include "mangle.h"
#ifdef ACCURATE_ROUNDING
#ifndef __APPLE__
.section .rodata
#else
.data
#endif
ALIGN8
max_s16:
.long 1191181824 /* 32767.0 */
.long 1191181824
min_s16:
.long -956301312 /* -32768.0 */
.long -956301312
ftoi_magic:
.long 1262485504 /* 2^23 + 2^22 */
.long 1262485504
#endif
.text
ALIGN16
.globl ASM_NAME(synth_1to1_3dnow_asm)
/* int synth_1to1_3dnow_asm(real *bandPtr, int channel, unsigned char *out, unsigned char *buffs, int *bo, real *decwin); */
ASM_NAME(synth_1to1_3dnow_asm):
subl $24,%esp
pushl %ebp
pushl %edi
xorl %ebp,%ebp
pushl %esi
pushl %ebx
/* stack old: 0=ebx 4=esi 8=edi 12=ebp 16,20,24,28,32,36=local 40=back 44=bandptr 48=channel 52=out 56=pnt */
/* stack new: 0=ebx 4=esi 8=edi 12=ebp 16,20,24,28,32,36=local 40=back 44=bandptr 48=channel 52=out 56=buffs 60=bo 64=decwin */
#define OUT 52(%esp)
#define CHANNEL 48(%esp)
#define BANDPTR 44(%esp)
#define BUFFS 56(%esp)
#define BO 60(%esp)
#define DECWIN 64(%esp)
#define LOCAL0 16(%esp)
#define LOCAL1 20(%esp)
#define EBXSAVE 24(%esp)
#define LOCAL5 36(%esp)
#ifdef ACCURATE_ROUNDING
#undef _EBX_
#define _EBX_ %eax
GET_GOT
/* FIXME */
#if PIC
movl _EBX_, EBXSAVE
#endif
#endif
movl OUT,%esi
movl %esi,LOCAL0 /* save buffer start (samples pointer) to another local var */
movl CHANNEL,%ebx
movl BO,%esi /* bo address */
movl (%esi),%edx /* bo value */
femms
testl %ebx,%ebx
jne .L26
/* if(!channel) */
decl %edx /* --bo */
andl $15,%edx
movl %edx,(%esi) /* save bo */
movl BUFFS,%ecx
jmp .L27
.L26: /* if(channel) */
addl $2,LOCAL0 /* samples++ */
movl BUFFS,%ecx
addl $2176,%ecx
.L27:
/* edx (and it's lower end) still holds bo value */
testb $1,%dl /* bo & 0x1 */
je .L28
movl %edx,LOCAL5
movl %ecx,%ebx
movl BANDPTR,%esi
movl %edx,%edi
pushl %esi
sall $2,%edi
movl %ebx,%eax
movl %edi,24(%esp) /* LOCAL1, actually */
addl %edi,%eax
pushl %eax
movl %edx,%eax
incl %eax
andl $15,%eax
leal 1088(,%eax,4),%eax
addl %ebx,%eax
pushl %eax
call FUNC(dct64_3dnow)
addl $12,%esp
jmp .L29
.L28:
leal 1(%edx),%esi
movl BANDPTR,%edi
movl %esi,LOCAL5
leal 1092(%ecx,%edx,4),%eax
pushl %edi
leal 1088(%ecx),%ebx
pushl %eax
sall $2,%esi
leal (%ecx,%edx,4),%eax
pushl %eax
call FUNC(dct64_3dnow)
addl $12,%esp
movl %esi,LOCAL1
.L29:
movl DECWIN,%edx
addl $64,%edx
movl $16,%ecx
subl LOCAL1,%edx
movl LOCAL0,%edi
pcmpeqb %mm7,%mm7
pslld $31,%mm7
movq (%edx),%mm0
movq (%ebx),%mm1
ALIGN32
.L33:
#if defined(ACCURATE_ROUNDING) && defined(PIC)
movl EBXSAVE, _EBX_
#endif
movq 8(%edx),%mm3
pfmul %mm1,%mm0
movq 8(%ebx),%mm4
movq 16(%edx),%mm5
pfmul %mm4,%mm3
movq 16(%ebx),%mm6
pfadd %mm3,%mm0
movq 24(%edx),%mm1
pfmul %mm6,%mm5
movq 24(%ebx),%mm2
pfadd %mm5,%mm0
movq 32(%edx),%mm3
pfmul %mm2,%mm1
movq 32(%ebx),%mm4
pfadd %mm1,%mm0
movq 40(%edx),%mm5
pfmul %mm4,%mm3
movq 40(%ebx),%mm6
pfadd %mm3,%mm0
movq 48(%edx),%mm1
pfmul %mm6,%mm5
movq 48(%ebx),%mm2
pfadd %mm0,%mm5
movq 56(%edx),%mm3
pfmul %mm1,%mm2
movq 56(%ebx),%mm4
pfadd %mm5,%mm2
addl $64,%ebx
subl $-128,%edx
movq (%edx),%mm0
pfmul %mm4,%mm3
movq (%ebx),%mm1
pfadd %mm3,%mm2
movq %mm2,%mm3
psrlq $32,%mm3
pfsub %mm3,%mm2
incl %ebp
#ifdef ACCURATE_ROUNDING
pfmin LOCAL_VAR(max_s16),%mm2
pfmax LOCAL_VAR(min_s16),%mm2
pfadd LOCAL_VAR(ftoi_magic),%mm2
#else
pf2id %mm2,%mm2
packssdw %mm2,%mm2
#endif
movd %mm2,%eax
movw %ax,0(%edi)
addl $4,%edi
decl %ecx
jnz .L33
#if defined(ACCURATE_ROUNDING) && defined(PIC)
movl EBXSAVE, _EBX_
#endif
movd (%ebx),%mm0
movd (%edx),%mm1
punpckldq 8(%ebx),%mm0
punpckldq 8(%edx),%mm1
movd 16(%ebx),%mm3
movd 16(%edx),%mm4
pfmul %mm1,%mm0
punpckldq 24(%ebx),%mm3
punpckldq 24(%edx),%mm4
movd 32(%ebx),%mm5
movd 32(%edx),%mm6
pfmul %mm4,%mm3
punpckldq 40(%ebx),%mm5
punpckldq 40(%edx),%mm6
pfadd %mm3,%mm0
movd 48(%ebx),%mm1
movd 48(%edx),%mm2
pfmul %mm6,%mm5
punpckldq 56(%ebx),%mm1
punpckldq 56(%edx),%mm2
pfadd %mm5,%mm0
pfmul %mm2,%mm1
pfadd %mm1,%mm0
pfacc %mm1,%mm0
#ifdef ACCURATE_ROUNDING
pfmin LOCAL_VAR(max_s16),%mm0
pfmax LOCAL_VAR(min_s16),%mm0
pfadd LOCAL_VAR(ftoi_magic),%mm0
#else
pf2id %mm0,%mm0
packssdw %mm0,%mm0
#endif
movd %mm0,%eax
movw %ax,0(%edi)
incl %ebp
movl LOCAL5,%esi
addl $-64,%ebx
movl $15,%ebp
addl $4,%edi
leal -128(%edx,%esi,8),%edx
movl $15,%ecx
movd (%ebx),%mm0
movd -4(%edx),%mm1
punpckldq 4(%ebx),%mm0
punpckldq -8(%edx),%mm1
ALIGN32
.L46:
#if defined(ACCURATE_ROUNDING) && defined(PIC)
movl EBXSAVE, _EBX_
#endif
movd 8(%ebx),%mm3
movd -12(%edx),%mm4
pfmul %mm1,%mm0
punpckldq 12(%ebx),%mm3
punpckldq -16(%edx),%mm4
movd 16(%ebx),%mm5
movd -20(%edx),%mm6
pfmul %mm4,%mm3
punpckldq 20(%ebx),%mm5
punpckldq -24(%edx),%mm6
pfadd %mm3,%mm0
movd 24(%ebx),%mm1
movd -28(%edx),%mm2
pfmul %mm6,%mm5
punpckldq 28(%ebx),%mm1
punpckldq -32(%edx),%mm2
pfadd %mm5,%mm0
movd 32(%ebx),%mm3
movd -36(%edx),%mm4
pfmul %mm2,%mm1
punpckldq 36(%ebx),%mm3
punpckldq -40(%edx),%mm4
pfadd %mm1,%mm0
movd 40(%ebx),%mm5
movd -44(%edx),%mm6
pfmul %mm4,%mm3
punpckldq 44(%ebx),%mm5
punpckldq -48(%edx),%mm6
pfadd %mm3,%mm0
movd 48(%ebx),%mm1
movd -52(%edx),%mm2
pfmul %mm6,%mm5
punpckldq 52(%ebx),%mm1
punpckldq -56(%edx),%mm2
pfadd %mm0,%mm5
movd 56(%ebx),%mm3
movd -60(%edx),%mm4
pfmul %mm2,%mm1
punpckldq 60(%ebx),%mm3
punpckldq (%edx),%mm4
pfadd %mm1,%mm5
addl $-128,%edx
addl $-64,%ebx
movd (%ebx),%mm0
movd -4(%edx),%mm1
pfmul %mm4,%mm3
punpckldq 4(%ebx),%mm0
punpckldq -8(%edx),%mm1
pfadd %mm5,%mm3
pfacc %mm3,%mm3
incl %ebp
pxor %mm7,%mm3
#ifdef ACCURATE_ROUNDING
pfmin LOCAL_VAR(max_s16),%mm3
pfmax LOCAL_VAR(min_s16),%mm3
pfadd LOCAL_VAR(ftoi_magic),%mm3
#else
pf2id %mm3,%mm3
packssdw %mm3,%mm3
#endif
movd %mm3,%eax
movw %ax,(%edi)
addl $4,%edi
decl %ecx
jnz .L46
femms
movl %ebp,%eax
popl %ebx
popl %esi
popl %edi
popl %ebp
addl $24,%esp
ret
#if defined(PIC) && defined(__APPLE__)
.section __IMPORT,__jump_table,symbol_stubs,self_modifying_code+pure_instructions,5
L_dct64_3dnow:
.indirect_symbol ASM_NAME(dct64_3dnow)
hlt ; hlt ; hlt ; hlt ; hlt
#endif
NONEXEC_STACK
| {
"language": "Assembly"
} |
config IIO_ST_LSM6DSX
tristate "ST_LSM6DSx driver for STM 6-axis IMU MEMS sensors"
depends on (I2C || SPI)
select IIO_BUFFER
select IIO_KFIFO_BUF
select IIO_ST_LSM6DSX_I2C if (I2C)
select IIO_ST_LSM6DSX_SPI if (SPI_MASTER)
help
Say yes here to build support for STMicroelectronics LSM6DSx imu
sensor. Supported devices: lsm6ds3, lsm6ds3h, lsm6dsl, lsm6dsm
To compile this driver as a module, choose M here: the module
will be called st_lsm6dsx.
config IIO_ST_LSM6DSX_I2C
tristate
depends on IIO_ST_LSM6DSX
select REGMAP_I2C
config IIO_ST_LSM6DSX_SPI
tristate
depends on IIO_ST_LSM6DSX
select REGMAP_SPI
| {
"language": "Assembly"
} |
; DRAW XOR SPRITE 2 BYTE DEFINITION ROTATED, ON RIGHT BORDER
; 01.2006 aralbrec, Sprite Pack v3.0
; sinclair spectrum version
PUBLIC SP1_DRAW_XOR2RB
EXTERN SP1_DRAW_XOR2LB
EXTERN SP1RETSPRDRAW, SP1V_ROTTBL, SP1V_PIXELBUFFER
; following data segment copied into struct sp1_cs
ld de,0
nop
ld hl,0
call SP1_DRAW_XOR2RB
; following draw code called by way of SP1UpdateNow
;
; a = hor rot table
; bc = graphic disp
; de = graphic def ptr (mask,graph) pairs
; hl = left graphic def ptr
;
; 46 + 106*4 - 6 + 10 = 474 cycles
.SP1_DRAW_XOR2RB
cp SP1V_ROTTBL/256
jp z, SP1RETSPRDRAW
add hl,bc
ld d,a
inc d
; d = shift table
; hl = left sprite def (mask,graph) pairs
.SP1Xor2RBRotate
jp SP1_DRAW_XOR2LB + 7
| {
"language": "Assembly"
} |
; crt0.s - Startup code for the mrisc1. This code initializes the C
; run-time model.
;
;
; Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
;
; The authors hereby grant permission to use, copy, modify, distribute,
; and license this software and its documentation for any purpose, provided
; that existing copyright notices are retained in all copies and that this
; notice is included verbatim in any distributions. No written agreement,
; license, or royalty fee is required for any of the authorized uses.
; Modifications to this software may be copyrighted by their authors
; and need not follow the licensing terms described here, provided that
; the new terms are clearly indicated on the first page of each file where
; they apply.
;
; Create a label for the start of the eh_frame section.
.section .eh_frame
__eh_frame_begin:
.text
.global _start
_start:
;; Initialize the stack pointer
ldui sp, #%hi16(__stack)
addui sp, sp, #%lo16(__stack)
or fp, sp, sp
;; Zero the bss space
ldui r9, #%hi16(__bss_start)
addui r9, r9, #%lo16(__bss_start)
ldui r10, #%hi16(__bss_end)
addui r10, r10, #%lo16(__bss_end)
or r0, r0, r0
brle r10, r9, .Lnext1
or r0, r0, r0
.Lcpy0:
stw r0, r9, #0
addi r9, r9, #4
or r0, r0, r0 ; nop
brle r9, r10, .Lcpy0
or r0, r0, r0 ; nop
.Lnext1:
;; Copy data from ROM to Frame Buffer (on-chip memory)
ldui r9, #%hi16(_fbdata_start)
ori r9, r9, #%lo16(_fbdata_start)
ldui r10, #%hi16(_fbdata_end)
ori r10, r10, #%lo16(_fbdata_end)
ldui r11, #%hi16(_fbdata_vma)
brle r10, r9, .Lnext2
ori r11, r11, #%lo16(_fbdata_vma)
.Lcpy1:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy1
addi r11, r11, #$4
.Lnext2:
;; Zero the frame buffer bss section
ldui r9, #%hi16(_fbbss_start)
ori r9, r9, #%lo16(_fbbss_start)
ldui r10, #%hi16(_fbbss_end)
ori r10, r10, #%lo16(_fbbss_end)
or r0, r0, r0
brle r10, r9, .Lnext3
or r0, r0, r0
.Lcpy2:
stw r0, r9, #$0
addi r9, r9, #$4
or r0, r0, r0
brle r9, r10, .Lcpy2
or r0, r0, r0
.Lnext3:
;; Call global and static constructors
ldui r10, #%hi16(_init)
ori r10, r10, #%lo16(_init)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Call main
ldui r10, #%hi16(main)
ori r10, r10, #%lo16(main)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; DJK - Added 12Nov01. Pass main's return value to exit.
or r1, r11, r0
;; Jump to exit
ldui r10, #%hi16(exit)
ori r10, r10, #%lo16(exit)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Exit does not return, however, this code is to catch an
;; error if it does. Set the processor into sleep mode.
ori r1, r0, #$1
stw r1, r0, #%lo16(_DEBUG_HALT_REG)
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
.Lend:
jmp .Lend
or r0, r0, r0
| {
"language": "Assembly"
} |
/*-
* Copyright (c) 2001 Mike Barcroft <mike@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <stdlib.h>
intmax_t imaxabs(intmax_t j)
{
return (j < 0 ? -j : j);
}
| {
"language": "Assembly"
} |
// List below shows all Chinese phonememes from eSpeakNG
// with some of syllables of Mbrola cn1 voice
// from: http://www.tcts.fpms.ac.be/synthesis/mbrola/dba/cn1/cn1.zip
// Note, that one eSpeakNG phoneme is written with several letters, e.g.
// 'ai' is one phoneme. Look for details at `phonemes/ph_zh` file
0 _ NULL 0 _
0 @ NULL 0 a
0 ai NULL 0 ai
1 a n 0 an
0 Au NULL 50 ao
0 ei NULL 50 e i
0 A NULL 0 a
0 a NULL 0 a
0 E NULL 0 e
0 f NULL 0 f
0 i. NULL 0 i
0 i[ NULL 0 i
0 iA NULL 50 i a
0 iAu NULL 50 i ao
0 iE NULL 0 ie
0 i NULL 0 i
0 io NULL 50 i o
0 iou NULL 50 j ou
0 yE NULL 50 y e
0 yi NULL 50 y i
0 y NULL 0 y
0 y& NULL 50 y a
0 y@ NULL 50 y e
0 yu NULL 50 y u
0 j NULL 0 j
0 kh NULL 0 ch
0 k NULL 0 k
0 l NULL 0 l
0 N NULL 0 n
0 N- NULL 0 n
0 n NULL 0 n
0 @ NULL 0 @
0 ong NULL 0 ong
0 o NULL 0 o
0 o- NULL 0 o
0 ou NULL 50 o u
0 ph NULL 50 p h
0 p NULL 0 p
0 @r NULL 0 r
0 S; NULL 0 x
0 s. NULL 0 x
0 th NULL 50 t _
0 t NULL 0 t
0 tS;h NULL 0 x
0 ts.h NULL 0 x
0 tsh NULL 50 sh
0 tS; NULL 0 x
0 ts NULL 0 x
0 ts. NULL 0 x
0 uai NULL 50 u ai
0 uA NULL 50 u a
0 ua NULL 50 u a
0 uei NULL 50 u ei
0 u NULL 0 u
0 u@ NULL 50 u u
0 uo NULL 50 u o
0 x NULL 0 h
1 i e 0 ie
1 iE NULL 0 ie
1 tS; h 0 x
8 A NULL 0 a
// TODO: To improve voice quality,
// many eSpeakNG phoneme pairs should be translated into syllables of Mbrola cn1 voice
// In general, additional lines should be in form:
// 1 ph1 ph2 0 mb1
// where 1 indicates that two successive eSpeakNG phonemes ph1 and ph2 should be checked,
// but mb1 is one Mbrola syllable from list below.
// Look for details at: https://github.com/espeak-ng/espeak-ng/blob/master/docs/mbrola.md
// Full list of Mbrola cn1 voice syllable pairs is following:
//
// _-_ _-en j-iu _-o t-ao
// _-a en-_ _-ju o-_ t-e
// a-_ en-en ju-an _-ong t-eng
// a-a _-eng j-ue ong-_ _-ti
// _-ai eng-_ j-un ong-ong t-i
// ai-_ eng-eng j-v o-o ti-an
// ai-ai _-er _-k _-ou ti-ao
// _-an er-_ k-a ou-_ t-ie
// an-_ er-er k-ai ou-ou t-ing
// an-an _-f k-an _-p t-ong
// _-ang f-a k-ang p-a t-ou
// ang-_ f-an k-ao p-ai _-tu
// ang-ang f-ang k-e p-an t-u
// _-ao f-ei k-en p-ang tu-an
// ao-_ f-en k-eng p-ao t-ui
// ao-ao f-eng k-ong p-ei t-un
// _-b f-o k-ou p-en tu-o
// b-a f-ou _-ku p-eng _-u
// b-ai f-u k-u _-pi u-_
// b-an _-g ku-a p-i _-ue
// b-ang g-a ku-ai pi-an ue-_
// b-ao g-ai ku-an pi-ao ue-ue
// b-ei g-an ku-ang p-ie ui-_
// b-en g-ang k-ui p-in ui-ui
// b-eng g-ao k-un p-ing _-un
// _-bi g-e ku-o p-o un-_
// b-i g-ei _-l p-ou un-un
// bi-an g-en l-a p-u u-u
// bi-ao g-eng l-ai _-q _-v
// b-ie g-ong l-an _-qi v-_
// b-in g-ou l-ang q-i v-v
// b-ing _-gu l-ao qi-a _-w
// b-o g-u l-e qi-an w-a
// b-u gu-a l-ei qi-ang w-ai
// _-c gu-ai l-eng qi-ao w-an
// c-a gu-an _-li q-ie w-ang
// c-ai gu-ang l-i q-in w-ei
// c-an g-ui li-a q-ing w-en
// c-ang g-un li-an qi-ong w-eng
// c-ao gu-o li-ang q-iu w-o
// c-e _-h li-ao _-qu w-u
// c-en h-a l-ie qu-an _-x
// c-eng h-ai l-in q-ue _-xi
// _-ch h-an l-ing q-un x-i
// ch-a h-ang l-iu q-v xi-a
// ch-ai h-ao ll-_ _-r xi-an
// ch-an h-e ll-ll r-an xi-ang
// ch-ang h-ei l-ong r-ang xi-ao
// ch-ao h-en l-ou r-ao x-ie
// ch-e h-eng _-lu r-e x-in
// ch-en h-ong l-u r-en x-ing
// ch-eng h-ou lu-an r-eng xi-ong
// ch-ll _-hu l-ue r-ll x-iu
// ch-ong h-u l-un r-ong _-xu
// ch-ou hu-a lu-o r-ou xu-an
// _-chu hu-ai l-v _-ru x-ue
// ch-u hu-an _-m r-u x-un
// chu-a hu-ang m-a ru-an x-v
// chu-ai h-ui m-ai r-ui _-z
// chu-an h-un m-an r-un z-a
// chu-ang hu-o m-ang ru-o z-ai
// ch-ui _-i m-ao _-s z-an
// ch-un i-_ m-e s-a z-ang
// chu-o _-ie m-ei s-ai z-ao
// c-ii ie-_ m-en s-an z-e
// c-ong ie-ie m-eng s-ang z-ei
// c-ou i-i _-mi s-ao z-en
// _-cu ii-_ m-i s-e z-eng
// c-u ii-ii mi-an s-en _-zh
// cu-an _-in mi-ao s-eng zh-a
// c-ui in-_ m-ie _-sh zh-ai
// c-un _-ing m-in sh-a zh-an
// cu-o ing-_ m-ing sh-ai zh-ang
// _-d ing-ing m-iu sh-an zh-ao
// d-a in-in m-o sh-ang zh-e
// d-ai _-iu m-ou sh-ao zh-ei
// d-an iu-_ m-u sh-e zh-en
// d-ang iu-iu _-n sh-ei zh-eng
// d-ao _-y n-a sh-en zh-ll
// d-e y-a n-ai sh-eng zh-ong
// d-ei y-an n-an sh-ll zh-ou
// d-en y-ang n-ang sh-ou _-zhu
// d-eng y-ao n-ao _-shu zh-u
// _-di y-e n-e sh-u zhu-a
// d-i y-i n-ei shu-a zhu-ai
// di-a y-in n-en shu-ai zhu-an
// di-an y-ing n-eng shu-an zhu-ang
// di-ao y-ong _-ni shu-ang zh-ui
// d-ie y-ou n-i sh-ui zh-un
// d-ing _-yu ni-an sh-un zhu-o
// d-iu yu-an ni-ang shu-o z-ii
// d-ong y-ue ni-ao s-ii z-ong
// d-ou y-un n-ie s-ong z-ou
// _-du y-v n-in s-ou _-zu
// d-u _-j n-ing _-su z-u
// du-an _-ji n-iu s-u zu-an
// d-ui j-i n-ong su-an z-ui
// d-un ji-a n-ou s-ui z-un
// du-o ji-an _-nu s-un zu-o
// _-e ji-ang n-u su-o
// e-_ ji-ao nu-an _-t
// e-e j-ie n-ue t-a
// _-ei j-in n-un t-ai
// ei-_ j-ing nu-o t-an
// ei-ei ji-ong n-v t-ang
| {
"language": "Assembly"
} |
/*
* Copyright (c) 2020 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "qemu_x86.dts"
| {
"language": "Assembly"
} |
GPR0 FFFFFFFFFFFFFFFD
GPR1 FFFFC00000000000
GPR2 0000000000000000
GPR3 FFFFFFFFFFFFFFE6
GPR4 0000C1FFFC000000
GPR5 FFFFC00000000000
GPR6 FFFFFFFFFFFFFFFE
GPR7 0000000000000000
GPR8 0000000000000000
GPR9 0000000000000000
GPR10 0000000000000000
GPR11 000000000000000C
GPR12 0000000000000000
GPR13 000000000000003E
GPR14 0000000000000000
GPR15 FFFFBFFFFFFE3FE0
GPR16 0000000000000000
GPR17 00000000FFFFFFFF
GPR18 FFFFFFFFFFFFFFEE
GPR19 0000000000000000
GPR20 0000000000000000
GPR21 000000000000000C
GPR22 0000000000000000
GPR23 0000000000000000
GPR24 FFFFC0000000000C
GPR25 FFFFFFFFFFFFFFFF
GPR26 FFFFFFFFFFFFFFE0
GPR27 0000000000000000
GPR28 0000000000000000
GPR29 0000000000000000
GPR30 0000000015555555
GPR31
CR 0000000050995593
LR 0000000000000000
CTR 00000000FFFFFFFF
XER 00000000A0040000
| {
"language": "Assembly"
} |
<?xml version="1.0" encoding="UTF-8"?>
<refentry xmlns="http://docbook.org/ns/docbook" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:svg="http://www.w3.org/2000/svg" xmlns:ns3="http://www.w3.org/1999/xhtml" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:db="http://docbook.org/ns/docbook" xmlns:scilab="http://www.scilab.org" xml:id="insertion" xml:lang="pt">
<refnamediv>
<refname>insertion</refname>
<refpurpose>atribuição ou modificação parcial de variáveis</refpurpose>
</refnamediv>
<refnamediv xml:id="assignation">
<refname>assignation</refname>
<refpurpose>atribuição parcial de variáveis</refpurpose>
</refnamediv>
<refsynopsisdiv>
<title>Seqüência de Chamamento</title>
<synopsis>x(i,j)=a
x(i)=a
l(i)=a
l(k1)...(kn)(i)=a or l(list(k1,...,kn,i))=a
l(k1)...(kn)(i,j)=a or l(list(k1,...,kn,list(i,j))=a
</synopsis>
</refsynopsisdiv>
<refsection>
<title>Parâmetros</title>
<variablelist>
<varlistentry>
<term>x</term>
<listitem>
<para>matriz de qualquer tipo</para>
</listitem>
</varlistentry>
<varlistentry>
<term>l</term>
<listitem>
<para>lista</para>
</listitem>
</varlistentry>
<varlistentry>
<term>i,j</term>
<listitem>
<para>índices</para>
</listitem>
</varlistentry>
<varlistentry>
<term>k1,...kn</term>
<listitem>
<para>índices com valores inteiros</para>
</listitem>
</varlistentry>
<varlistentry>
<term>a</term>
<listitem>
<para>novo valor de entrada</para>
</listitem>
</varlistentry>
</variablelist>
</refsection>
<refsection>
<title>Descrição</title>
<variablelist>
<varlistentry>
<term>CASO DE MATRIZES</term>
<listitem>
<para>
Se <literal>x</literal> é uma matriz, os índices
<literal>i</literal> e <literal>j</literal>, podem ser:
</para>
<variablelist>
<varlistentry>
<term>Escalares reais, vetores ou matrizes</term>
<listitem>
<para>neste caso, os valores fornecidos como índices devem ser
inteiros e apenas suas partes inteiras são levadas em
consideração.
</para>
<itemizedlist>
<listitem>
<para>
Se <literal>a</literal> é uma matriz com dimensões
<literal>(size(i,'*'),size(j,'*'))</literal>,
<literal>x(i,j)=a</literal> retorna uma nova matriz
<literal>x</literal> tal que
<literal>x(int(i(l)),int(j(k)))=a(l,k) </literal> para
<literal>l</literal> de 1 a <literal>size(i,'*')</literal>
e <literal>k</literal> de 1 a
<literal>size(j,'*')</literal>, as outras entradas
iniciais de <literal>x</literal> não são
modificadas.
</para>
</listitem>
<listitem>
<para>
Se <literal>a</literal> é um escalar,
<literal>x(i,j)=a</literal> retorna uma nova matriz
<literal>x</literal> tal que
<literal>x(int(i(l)),int(j(k)))=a</literal> para
<literal>l</literal> de 1 a <literal>size(i,'*')</literal>
e <literal>k</literal> de 1 a
<literal>size(j,'*')</literal>, as outras entradas
iniciais de <literal>x</literal> não são
modificadas.
</para>
</listitem>
<listitem>
<para>
Se o valor máximo de <literal>i</literal> ou
<literal>j</literal> exceder a dimensão correspondente da
matriz <literal>x</literal> , o array <literal>x</literal>
é previamente estendido para as dimensões requeridas com
entradas 0 para matrizes padrões, strings de comprimento 0
para matrizes de strings e valores falsos para matrizes de
booleanos.
</para>
</listitem>
<listitem>
<para>
<literal>x(i,j)=[]</literal> cancela linhas
especificadas por <literal>i</literal> se
<literal>j</literal> corresponde a todas as colunas de
<literal>x</literal> ou cancela colunas especificadas por
<literal>j</literal> se <literal>i</literal> corresponde a
todas as linhas de <literal>x</literal>. Em outros casos
<literal>x(i,j)=[]</literal> produz um erro.
</para>
</listitem>
<listitem>
<para>
<literal>x(i)=a</literal> com <literal>a</literal>
um vetor retorna a nova matriz <literal>x</literal> tal
que <literal>x(int(i(l)))=a(l)</literal> para
<literal>l</literal> de 1 a <literal>size(i,'*')</literal>
, outras entradas iniciais de <literal>x</literal> não são
modificadas.
</para>
</listitem>
<listitem>
<para>
<literal>x(i)=a</literal> com <literal>a</literal>
um escalar retorna uma nova matriz <literal>x</literal>
tal que <literal>x(int(i(l)))=a</literal> para
<literal>l</literal> de 1 a <literal>size(i,'*')</literal>
, outras entradas iniciais de <literal>x</literal> não são
modificadas.
</para>
<para>
Se o valor máximo de <literal>i</literal> exceder
<literal>size(x,1)</literal>, <literal>x</literal> é
previamente estendida para a dimensão requerida com
entradas 0 para matrizes padrões, strings de comprimento 0
para matrizes de strings e valores falsos para matrizes de
booleanos.
</para>
<variablelist>
<varlistentry>
<term>Se</term>
<listitem>
<para>
<literal>x</literal> é uma matriz 1x1
</para>
<para>
<literal>a</literal> pode ser um vetor linha
(respectivamente coluna) com dimensão
<literal>size(i,'*')</literal>. A matriz
<literal>x</literal> resultante é um vetor linha
(respectivamente coluna).
</para>
</listitem>
</varlistentry>
<varlistentry>
<term>Se</term>
<listitem>
<para>
<literal>x</literal> é um vetor linha
</para>
<para>
<literal>a</literal> deve ser um vetor linha
de dimensão <literal>size(i,'*')</literal>
</para>
</listitem>
</varlistentry>
<varlistentry>
<term>Se</term>
<listitem>
<para>
<literal>x</literal> é um vetor coluna
</para>
<para>
<literal>a</literal> deve ser um vetor coluna
de dimensão <literal>size(i,'*')</literal>
</para>
</listitem>
</varlistentry>
<varlistentry>
<term>Se</term>
<listitem>
<para>
<literal>x</literal> é uma matriz geral
</para>
<para>
<literal>a</literal> deve ser um vetor linha
ou coluna de dimensão <literal>size(i,'*')</literal>
e o valor máximo de <literal>i</literal> não pode
exceder <literal>size(x,'*')</literal>,
</para>
</listitem>
</varlistentry>
</variablelist>
</listitem>
<listitem>
<para>
<literal>x(i)=[]</literal> cancela entradas
especificadas por <literal>i</literal>.
</para>
</listitem>
</itemizedlist>
</listitem>
</varlistentry>
<varlistentry>
<term>O símbolo :</term>
<listitem>
<para>
O símbolo <literal>':'</literal> significa "todos os
elementos".
</para>
<itemizedlist>
<listitem>
<para>
<literal>x(i,:)=a</literal> é interpretado como
<literal>x(i,1:size(x,2))=a</literal>
</para>
</listitem>
<listitem>
<para>
<literal>x(:,j)=a</literal> é interpretado como
<literal>x(1:size(x,1),j)=a</literal>
</para>
</listitem>
<listitem>
<para>
<literal>x(:)=a</literal> retorna em
<literal>x</literal> a matriz <literal>a</literal> de
forma redefinida de acordo com as dimensões de x.
<literal>size(x,'*')</literal> deve ser igual a
<literal>size(a,'*')</literal>
</para>
</listitem>
</itemizedlist>
</listitem>
</varlistentry>
<varlistentry>
<term>Vetores de booleanos</term>
<listitem>
<para>
se um índice (<literal>i</literal> ou
<literal>j</literal> ) é um vetor de booleanos, é interpretado
como <literal>find(i)</literal> ou, respectivamente,
<literal>find(j)</literal>
</para>
</listitem>
</varlistentry>
<varlistentry>
<term>Polinômios</term>
<listitem>
<para>
se um índice (<literal>i</literal> ou
<literal>j</literal> ) é um vetor de polinômios ou um vetor de
polinômios implícito, é interpretado como
<literal>horner(i,m)</literal> ou respectivamente
<literal>horner(j,n)</literal> onde <literal>m</literal> e
<literal>n</literal> são as dimensões associadas de
<literal>x</literal>. Mesmo se esse recurso funcionar para
todos os polinômios, é recomendado utilizar polinômios em
<literal>$</literal> para legibilidade.
</para>
</listitem>
</varlistentry>
</variablelist>
</listitem>
</varlistentry>
<varlistentry>
<term>CASO DE LISTAS OU TLISTS</term>
<listitem>
<itemizedlist>
<listitem>
<para>
Se estiverem presentes, os <literal>ki</literal> fornecem
o endereço para uma entrada de sub-lista da estrutura de dados
<literal>l</literal> data structure. Eles permitem uma extração
recursiva sem cópias intermediárias. As instruções
<literal>l(k1)...(kn)(i)=a</literal> e
<literal>l(list(k1,...,kn,i)=a)</literal> são interpretadas
como:
</para>
<para>
<literal>lk1 = l(k1)</literal>
<literal> .. = ..
</literal>
</para>
<para>
<literal>lkn = lkn-1(kn)</literal>
<literal> lkn(i) =
a
</literal>
</para>
<para>
<literal>lkn-1(kn) = lkn</literal>
<literal> .. = ..
</literal>
<literal>l(k1) = lk1</literal>
</para>
<para>
E as instruções <literal>l(k1)...(kn)(i,j)=a</literal> e
<literal>l(list(k1,...,kn,list(i,j))=a</literal> são
interpretadas como:
</para>
<para>
<literal>lk1 = l(k1)</literal>
<literal> .. = ..
</literal>
</para>
<para>
<literal>lkn = lkn-1(kn)</literal>
<literal>lkn(i,j) =
a
</literal>
</para>
<para>
<literal>lkn-1(kn) = lkn</literal>
<literal> .. = ..
</literal>
<literal>l(k1)= lk1</literal>
</para>
</listitem>
<listitem>
<para>
<literal>i</literal> pode ser :
</para>
<itemizedlist>
<listitem>
<para>Um escalar real não-negativo.
<literal>l(0)=a</literal> adiciona uma entrada à "esquerda"
da lista, <literal>l(i)=a</literal> configura a entrada
<literal>i</literal> da lista <literal>l</literal> como
<literal>a</literal>. Se <literal>i>size(l)</literal>,
<literal>l</literal> é previamente estendido com entradas de
comprimento 0 (indefinidas). <literal>l(i)=null()</literal>
suprime a <literal>i</literal>-ésima entrada da
lista.
</para>
</listitem>
<listitem>
<para>
Um polinômio. Se <literal>i</literal> é um polinômio,
é interpretado como <literal>horner(i,m)</literal> onde
<literal>m=size(l)</literal>. Mesmo se este recurso
funcionar para todos os polinômios, é recomendado utilizar
polinômios em <literal>$</literal> para legibilidade.
</para>
</listitem>
</itemizedlist>
</listitem>
<listitem>
<para>
<literal>k1,..kn</literal> podem ser :
</para>
<itemizedlist>
<listitem>
<para>Escalares reais positivos.</para>
</listitem>
<listitem>
<para>Polinômios, interpretados como
<literal>horner(ki,m)</literal> onde <literal>m</literal> é
o tamanho da sub-lista correspondente.
</para>
</listitem>
<listitem>
<para>Strings associados a nomes de entradas de uma
sub-lista.
</para>
</listitem>
</itemizedlist>
</listitem>
</itemizedlist>
</listitem>
</varlistentry>
</variablelist>
</refsection>
<refsection>
<title>Observações</title>
<para>Para tipos de matrizes "soft-coded" como funções racionais e
sistemas lineares de espaços de estados, a sintaxe <literal>x(i)</literal>
não pode ser usada para inserção de entradas em vetores devido a confusões
com inserção de entradas em listas. A sintaxe <literal>x(1,j)</literal> ou
<literal>x(i,1)</literal> deve ser usada.
</para>
</refsection>
<refsection>
<title>Exemplos</title>
<programlisting role="example"><![CDATA[
// CASO DE MATRIZES
a=[1 2 3;4 5 6]
a(1,2)=10
a([1 1],2)=[-1;-2]
a(:,1)=[8;5]
a(1,3:-1:1)=[77 44 99]
a(1)=%s
a(6)=%s+1
a(:)=1:6
a([%t %f],1)=33
a(1:2,$-1)=[2;4]
a($:-1:1,1)=[8;7]
a($)=123
//
x='teste'
x([4 5])=['4','5']
//
b=[1/%s,(%s+1)/(%s-1)]
b(1,1)=0
b(1,$)=b(1,$)+1
b(2)=[1 2] // o numerador
// CASO DE LISTAS OU TLISTS
l=list(1,'qwerw',%s)
l(1)='Modificado'
l(0)='Adicionado'
l(6)=['mais um';'adicionado']
//
//
dts=list(1,tlist(['x';'a';'b'],10,[2 3]));
dts(2).a=33
dts(2)('b')(1,2)=-100
]]></programlisting>
</refsection>
<refsection role="see also">
<title>Ver Também</title>
<simplelist type="inline">
<member>
<link linkend="find">find</link>
</member>
<member>
<link linkend="horner">horner</link>
</member>
<member>
<link linkend="parentheses">parentheses</link>
</member>
<member>
<link linkend="extraction">extraction</link>
</member>
</simplelist>
</refsection>
</refentry>
| {
"language": "Assembly"
} |
; RUN: llc < %s -mcpu=g5 | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
define void @foo(float* noalias nocapture %a, float* noalias nocapture %b) #0 {
vector.ph:
br label %vector.body
vector.body: ; preds = %vector.body, %vector.ph
%index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
%0 = getelementptr inbounds float* %b, i64 %index
%1 = bitcast float* %0 to <4 x float>*
%wide.load = load <4 x float>* %1, align 4
%.sum11 = or i64 %index, 4
%2 = getelementptr float* %b, i64 %.sum11
%3 = bitcast float* %2 to <4 x float>*
%wide.load8 = load <4 x float>* %3, align 4
%4 = fadd <4 x float> %wide.load, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
%5 = fadd <4 x float> %wide.load8, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
%6 = getelementptr inbounds float* %a, i64 %index
%7 = bitcast float* %6 to <4 x float>*
store <4 x float> %4, <4 x float>* %7, align 4
%.sum12 = or i64 %index, 4
%8 = getelementptr float* %a, i64 %.sum12
%9 = bitcast float* %8 to <4 x float>*
store <4 x float> %5, <4 x float>* %9, align 4
%index.next = add i64 %index, 8
%10 = icmp eq i64 %index.next, 16000
br i1 %10, label %for.end, label %vector.body
; CHECK: @foo
; CHECK-DAG: li [[C0:[0-9]+]], 0
; CHECK-DAG: li [[C16:[0-9]+]], 16
; CHECK-DAG: li [[C31:[0-9]+]], 31
; CHECK-DAG: lvx [[CNST:[0-9]+]],
; CHECK: .LBB0_1:
; CHECK-DAG: lvsl [[PC:[0-9]+]], [[B1:[0-9]+]], [[C0]]
; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
; CHECK-DAG: add [[B3:[0-9]+]], [[B1]], [[C0]]
; CHECK-DAG: lvx [[LD2:[0-9]+]], [[B3]], [[C16]]
; CHECK-DAG: lvx [[LD3:[0-9]+]], [[B3]], [[C31]]
; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[PC]]
; CHECK-DAG: vperm [[R2:[0-9]+]], [[LD2]], [[LD3]], [[PC]]
; CHECK-DAG: vaddfp {{[0-9]+}}, [[R1]], [[CNST]]
; CHECK-DAG: vaddfp {{[0-9]+}}, [[R2]], [[CNST]]
; CHECK: blr
for.end: ; preds = %vector.body
ret void
}
attributes #0 = { nounwind }
| {
"language": "Assembly"
} |
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
;
; EXTRQ
;
define <2 x i64> @test_extrq_call(<2 x i64> %x, <16 x i8> %y) {
; CHECK-LABEL: @test_extrq_call(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> [[X:%.*]], <16 x i8> [[Y:%.*]]) #1
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %y) nounwind
ret <2 x i64> %1
}
define <2 x i64> @test_extrq_zero_arg0(<2 x i64> %x, <16 x i8> %y) {
; CHECK-LABEL: @test_extrq_zero_arg0(
; CHECK-NEXT: ret <2 x i64> <i64 0, i64 undef>
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> zeroinitializer, <16 x i8> %y) nounwind
ret <2 x i64> %1
}
define <2 x i64> @test_extrq_zero_arg1(<2 x i64> %x, <16 x i8> %y) {
; CHECK-LABEL: @test_extrq_zero_arg1(
; CHECK-NEXT: ret <2 x i64> [[X:%.*]]
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> zeroinitializer) nounwind
ret <2 x i64> %1
}
define <2 x i64> @test_extrq_to_extqi(<2 x i64> %x, <16 x i8> %y) {
; CHECK-LABEL: @test_extrq_to_extqi(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> [[X:%.*]], i8 8, i8 15)
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> <i8 8, i8 15, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>) nounwind
ret <2 x i64> %1
}
define <2 x i64> @test_extrq_constant(<2 x i64> %x, <16 x i8> %y) {
; CHECK-LABEL: @test_extrq_constant(
; CHECK-NEXT: ret <2 x i64> <i64 255, i64 undef>
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> <i64 -1, i64 55>, <16 x i8> <i8 8, i8 15, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>) nounwind
ret <2 x i64> %1
}
define <2 x i64> @test_extrq_constant_undef(<2 x i64> %x, <16 x i8> %y) {
; CHECK-LABEL: @test_extrq_constant_undef(
; CHECK-NEXT: ret <2 x i64> <i64 65535, i64 undef>
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> <i64 -1, i64 undef>, <16 x i8> <i8 16, i8 15, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>) nounwind
ret <2 x i64> %1
}
define <2 x i64> @test_extrq_call_constexpr(<2 x i64> %x) {
; CHECK-LABEL: @test_extrq_call_constexpr(
; CHECK-NEXT: ret <2 x i64> [[X:%.*]]
;
%1 = call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> bitcast (<2 x i64> <i64 0, i64 undef> to <16 x i8>))
ret <2 x i64> %1
}
;
; EXTRQI
;
define <2 x i64> @test_extrqi_call(<2 x i64> %x) {
; CHECK-LABEL: @test_extrqi_call(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> [[X:%.*]], i8 8, i8 23)
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 8, i8 23)
ret <2 x i64> %1
}
define <2 x i64> @test_extrqi_shuffle_1zuu(<2 x i64> %x) {
; CHECK-LABEL: @test_extrqi_shuffle_1zuu(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[X:%.*]] to <16 x i8>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[TMP3]]
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 32, i8 32)
ret <2 x i64> %1
}
define <2 x i64> @test_extrqi_shuffle_2zzzzzzzuuuuuuuu(<2 x i64> %x) {
; CHECK-LABEL: @test_extrqi_shuffle_2zzzzzzzuuuuuuuu(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[X:%.*]] to <16 x i8>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> <i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 2, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[TMP3]]
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 8, i8 16)
ret <2 x i64> %1
}
define <2 x i64> @test_extrqi_undef(<2 x i64> %x) {
; CHECK-LABEL: @test_extrqi_undef(
; CHECK-NEXT: ret <2 x i64> undef
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> zeroinitializer, i8 32, i8 33)
ret <2 x i64> %1
}
define <2 x i64> @test_extrqi_zero(<2 x i64> %x) {
; CHECK-LABEL: @test_extrqi_zero(
; CHECK-NEXT: ret <2 x i64> <i64 0, i64 undef>
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> zeroinitializer, i8 3, i8 18)
ret <2 x i64> %1
}
define <2 x i64> @test_extrqi_constant(<2 x i64> %x) {
; CHECK-LABEL: @test_extrqi_constant(
; CHECK-NEXT: ret <2 x i64> <i64 7, i64 undef>
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> <i64 -1, i64 55>, i8 3, i8 18)
ret <2 x i64> %1
}
define <2 x i64> @test_extrqi_constant_undef(<2 x i64> %x) {
; CHECK-LABEL: @test_extrqi_constant_undef(
; CHECK-NEXT: ret <2 x i64> <i64 15, i64 undef>
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> <i64 -1, i64 undef>, i8 4, i8 18)
ret <2 x i64> %1
}
define <2 x i64> @test_extrqi_call_constexpr() {
; CHECK-LABEL: @test_extrqi_call_constexpr(
; CHECK-NEXT: ret <2 x i64> zeroinitializer
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> bitcast (<16 x i8> trunc (<16 x i16> bitcast (<4 x i64> <i64 0, i64 undef, i64 2, i64 undef> to <16 x i16>) to <16 x i8>) to <2 x i64>), i8 8, i8 16)
ret <2 x i64> %1
}
;
; INSERTQ
;
define <2 x i64> @test_insertq_call(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertq_call(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]]) #1
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind
ret <2 x i64> %1
}
define <2 x i64> @test_insertq_to_insertqi(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertq_to_insertqi(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> [[X:%.*]], <2 x i64> <i64 8, i64 undef>, i8 18, i8 2)
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> <i64 8, i64 658>) nounwind
ret <2 x i64> %1
}
define <2 x i64> @test_insertq_constant(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertq_constant(
; CHECK-NEXT: ret <2 x i64> <i64 32, i64 undef>
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> <i64 0, i64 0>, <2 x i64> <i64 8, i64 658>) nounwind
ret <2 x i64> %1
}
define <2 x i64> @test_insertq_constant_undef(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertq_constant_undef(
; CHECK-NEXT: ret <2 x i64> <i64 33, i64 undef>
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> <i64 1, i64 undef>, <2 x i64> <i64 8, i64 658>) nounwind
ret <2 x i64> %1
}
define <2 x i64> @test_insertq_call_constexpr(<2 x i64> %x) {
; CHECK-LABEL: @test_insertq_call_constexpr(
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> [[X:%.*]], <2 x i64> <i64 0, i64 undef>, i8 2, i8 0)
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> bitcast (<16 x i8> trunc (<16 x i16> bitcast (<4 x i64> <i64 0, i64 undef, i64 2, i64 undef> to <16 x i16>) to <16 x i8>) to <2 x i64>))
ret <2 x i64> %1
}
;
; INSERTQI
;
define <16 x i8> @test_insertqi_shuffle_04uu(<16 x i8> %v, <16 x i8> %i) {
; CHECK-LABEL: @test_insertqi_shuffle_04uu(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> [[V:%.*]], <16 x i8> [[I:%.*]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK-NEXT: ret <16 x i8> [[TMP1]]
;
%1 = bitcast <16 x i8> %v to <2 x i64>
%2 = bitcast <16 x i8> %i to <2 x i64>
%3 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %2, i8 32, i8 32)
%4 = bitcast <2 x i64> %3 to <16 x i8>
ret <16 x i8> %4
}
define <16 x i8> @test_insertqi_shuffle_8123uuuu(<16 x i8> %v, <16 x i8> %i) {
; CHECK-LABEL: @test_insertqi_shuffle_8123uuuu(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> [[I:%.*]], <16 x i8> [[V:%.*]], <16 x i32> <i32 0, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK-NEXT: ret <16 x i8> [[TMP1]]
;
%1 = bitcast <16 x i8> %v to <2 x i64>
%2 = bitcast <16 x i8> %i to <2 x i64>
%3 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %2, i8 16, i8 0)
%4 = bitcast <2 x i64> %3 to <16 x i8>
ret <16 x i8> %4
}
define <2 x i64> @test_insertqi_constant(<2 x i64> %v, <2 x i64> %i) {
; CHECK-LABEL: @test_insertqi_constant(
; CHECK-NEXT: ret <2 x i64> <i64 -131055, i64 undef>
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> <i64 -1, i64 -1>, <2 x i64> <i64 8, i64 0>, i8 16, i8 1)
ret <2 x i64> %1
}
define <2 x i64> @test_insertqi_call_constexpr(<2 x i64> %x) {
; CHECK-LABEL: @test_insertqi_call_constexpr(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> [[X:%.*]], <2 x i64> <i64 0, i64 undef>, i8 48, i8 3)
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> bitcast (<16 x i8> trunc (<16 x i16> bitcast (<4 x i64> <i64 0, i64 undef, i64 2, i64 undef> to <16 x i16>) to <16 x i8>) to <2 x i64>), i8 48, i8 3)
ret <2 x i64> %1
}
; The result of this insert is the second arg, since the top 64 bits of
; the result are undefined, and we copy the bottom 64 bits from the
; second arg
define <2 x i64> @testInsert64Bits(<2 x i64> %v, <2 x i64> %i) {
; CHECK-LABEL: @testInsert64Bits(
; CHECK-NEXT: ret <2 x i64> [[I:%.*]]
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 64, i8 0)
ret <2 x i64> %1
}
define <2 x i64> @testZeroLength(<2 x i64> %v, <2 x i64> %i) {
; CHECK-LABEL: @testZeroLength(
; CHECK-NEXT: ret <2 x i64> [[I:%.*]]
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 0, i8 0)
ret <2 x i64> %1
}
define <2 x i64> @testUndefinedInsertq_1(<2 x i64> %v, <2 x i64> %i) {
; CHECK-LABEL: @testUndefinedInsertq_1(
; CHECK-NEXT: ret <2 x i64> undef
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 0, i8 16)
ret <2 x i64> %1
}
define <2 x i64> @testUndefinedInsertq_2(<2 x i64> %v, <2 x i64> %i) {
; CHECK-LABEL: @testUndefinedInsertq_2(
; CHECK-NEXT: ret <2 x i64> undef
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 48, i8 32)
ret <2 x i64> %1
}
define <2 x i64> @testUndefinedInsertq_3(<2 x i64> %v, <2 x i64> %i) {
; CHECK-LABEL: @testUndefinedInsertq_3(
; CHECK-NEXT: ret <2 x i64> undef
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %v, <2 x i64> %i, i8 64, i8 16)
ret <2 x i64> %1
}
;
; Vector Demanded Bits
;
define <2 x i64> @test_extrq_arg0(<2 x i64> %x, <16 x i8> %y) {
; CHECK-LABEL: @test_extrq_arg0(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> [[X:%.*]], <16 x i8> [[Y:%.*]]) #1
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = shufflevector <2 x i64> %x, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %1, <16 x i8> %y) nounwind
ret <2 x i64> %2
}
define <2 x i64> @test_extrq_arg1(<2 x i64> %x, <16 x i8> %y) {
; CHECK-LABEL: @test_extrq_arg1(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> [[X:%.*]], <16 x i8> [[Y:%.*]]) #1
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = shufflevector <16 x i8> %y, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
%2 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %1) nounwind
ret <2 x i64> %2
}
define <2 x i64> @test_extrq_args01(<2 x i64> %x, <16 x i8> %y) {
; CHECK-LABEL: @test_extrq_args01(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> [[X:%.*]], <16 x i8> [[Y:%.*]]) #1
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = shufflevector <2 x i64> %x, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = shufflevector <16 x i8> %y, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
%3 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %1, <16 x i8> %2) nounwind
ret <2 x i64> %3
}
define <2 x i64> @test_extrq_ret(<2 x i64> %x, <16 x i8> %y) {
; CHECK-LABEL: @test_extrq_ret(
; CHECK-NEXT: ret <2 x i64> undef
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %y) nounwind
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
ret <2 x i64> %2
}
define <2 x i64> @test_extrqi_arg0(<2 x i64> %x) {
; CHECK-LABEL: @test_extrqi_arg0(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> [[X:%.*]], i8 3, i8 2)
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = shufflevector <2 x i64> %x, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %1, i8 3, i8 2)
ret <2 x i64> %2
}
define <2 x i64> @test_extrqi_ret(<2 x i64> %x) {
; CHECK-LABEL: @test_extrqi_ret(
; CHECK-NEXT: ret <2 x i64> undef
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2) nounwind
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
ret <2 x i64> %2
}
define <2 x i64> @test_insertq_arg0(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertq_arg0(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]]) #1
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = shufflevector <2 x i64> %x, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %1, <2 x i64> %y) nounwind
ret <2 x i64> %2
}
define <2 x i64> @test_insertq_ret(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertq_ret(
; CHECK-NEXT: ret <2 x i64> undef
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
ret <2 x i64> %2
}
define <2 x i64> @test_insertqi_arg0(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertqi_arg0(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]], i8 3, i8 2) #1
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = shufflevector <2 x i64> %x, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %y, i8 3, i8 2) nounwind
ret <2 x i64> %2
}
define <2 x i64> @test_insertqi_arg1(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertqi_arg1(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]], i8 3, i8 2) #1
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = shufflevector <2 x i64> %y, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %1, i8 3, i8 2) nounwind
ret <2 x i64> %2
}
define <2 x i64> @test_insertqi_args01(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertqi_args01(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]], i8 3, i8 2) #1
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%1 = shufflevector <2 x i64> %x, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = shufflevector <2 x i64> %y, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%3 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %2, i8 3, i8 2) nounwind
ret <2 x i64> %3
}
define <2 x i64> @test_insertqi_ret(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertqi_ret(
; CHECK-NEXT: ret <2 x i64> undef
;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 3, i8 2) nounwind
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
ret <2 x i64> %2
}
; CHECK: declare <2 x i64> @llvm.x86.sse4a.extrq
declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind
; CHECK: declare <2 x i64> @llvm.x86.sse4a.extrqi
declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind
; CHECK: declare <2 x i64> @llvm.x86.sse4a.insertq
declare <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64>, <2 x i64>) nounwind
; CHECK: declare <2 x i64> @llvm.x86.sse4a.insertqi
declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind
| {
"language": "Assembly"
} |
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK-LABEL: f0:
; CHECK: p0 = bitsset(r0,r1)
define i32 @f0(i32 %a0, i32 %a1) #0 {
b0:
%v0 = and i32 %a0, %a1
%v1 = icmp eq i32 %v0, %a1
%v2 = select i1 %v1, i32 2, i32 3
ret i32 %v2
}
; CHECK-LABEL: f1:
; CHECK: p0 = bitsclr(r0,r1)
define i32 @f1(i32 %a0, i32 %a1) #0 {
b0:
%v0 = and i32 %a0, %a1
%v1 = icmp eq i32 %v0, 0
%v2 = select i1 %v1, i32 2, i32 3
ret i32 %v2
}
; CHECK-LABEL: f2:
; CHECK: p0 = bitsclr(r0,#37)
define i32 @f2(i32 %a0) #0 {
b0:
%v0 = and i32 %a0, 37
%v1 = icmp eq i32 %v0, 0
%v2 = select i1 %v1, i32 2, i32 3
ret i32 %v2
}
attributes #0 = { nounwind "target-cpu"="hexagonv55" }
| {
"language": "Assembly"
} |
// RUN: %target-run-simple-swift | %FileCheck %s
// REQUIRES: executable_test
do {
defer { print("deferred 1") }
defer { print("deferred 2") }
print("start!")
// CHECK-NOT: deferred
// CHECK-LABEL: start!
// CHECK-NEXT: deferred 2
// CHECK-NEXT: deferred 1
}
// ensure #function ignores defer blocks
do {
print("top-level #function")
let name = #function
defer { print(name == #function ? "good" : "bad") }
// CHECK-LABEL: top-level #function
// CHECK-NEXT: good
}
func foo() {
print("foo()")
let name = #function
defer { print(name == #function ? "good" : "bad") }
// CHECK-LABEL: foo()
// CHECK-NEXT: good
}
foo()
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 %s -emit-llvm -o - -ffake-address-space-map | FileCheck %s
int test_func(constant char* foo);
kernel void str_array_decy() {
test_func("Test string literal");
}
// CHECK: i8 addrspace(2)* getelementptr inbounds ([20 x i8], [20 x i8] addrspace(2)*
// CHECK-NOT: addrspacecast
| {
"language": "Assembly"
} |
---
layout: page
title: "Q40756: Bad Code for Expression Parameter of outp() with -Oi"
permalink: /pubs/pc/reference/microsoft/kb/Q40756/
---
## Q40756: Bad Code for Expression Parameter of outp() with -Oi
Article: Q40756
Version(s): 5.10
Operating System: MS-DOS
Flags: ENDUSER | SR# G881205-7390
Last Modified: 15-JAN-1990
When compiling the source line below, the Microsoft C Compiler Version
5.10 generates incorrect code in some cases for the intrinsic outp and
outpw functions when the -Oi option is used and the second parameter
is an expression. Workarounds are listed below.
The following is the C source line and the generated code:
outp(port + INT_ENABLE_OFF, (i == SIO_CNT) ? 3 : 1);
cmp WORD PTR [bp-6], 8 ;i
je $L20003 ;error !
mov ax, 3
jmp SHORT $L20004
$L20003:
mov ax, 1
$L20004:
push ax
mov ax, WORD PTR [bp-4] ;port
inc ax
push ax
call FAR PTR _outp
This assembly code would be equal to a source line such as the
following:
outp(port + IN_ENABLE_OFF, (i == SIO_CNT) ? 1 : 3);
This is the exact reverse of the original source line. Therefore, the
generated assembler code should read as follows:
cmp WORD PTR [bp-6], 8 ;i
jne $L20003 ;
mov ax, 3
jmp SHORT $L20004
$L20003:
mov ax, 1
$L20004:
push ax
mov ax, WORD PTR [bp-4] ;port
inc ax
push ax
call FAR PTR _outp
There are two workarounds:
1. Use a temporary variable -- for example:
x = (i == SIO_CNT) ? 1 : 3;
outp(port + stuff, x);
2. Don't use -Oi.
3. Use -Oi, but use the "#pragma function(outp outpw)" statement to
have the non-intrinsic version of the function used.
| {
"language": "Assembly"
} |
// RUN: %clang -target x86_64-unknown-linux -### %s -flto=full 2>&1 | FileCheck --check-prefix=UNIT %s
// RUN: %clang -target x86_64-unknown-linux -### %s -flto=thin 2>&1 | FileCheck --check-prefix=UNIT %s
// RUN: %clang -target x86_64-apple-darwin13.3.0 -### %s -flto=full 2>&1 | FileCheck --check-prefix=UNIT %s
// RUN: %clang -target x86_64-apple-darwin13.3.0 -### %s -flto=thin 2>&1 | FileCheck --check-prefix=NOUNIT %s
// RUN: %clang -target x86_64-scei-ps4 -### %s -flto=full 2>&1 | FileCheck --check-prefix=UNIT %s
// RUN: %clang -target x86_64-scei-ps4 -### %s -flto=thin 2>&1 | FileCheck --check-prefix=NOUNIT %s
// UNIT: "-flto-unit"
// NOUNIT-NOT: "-flto-unit"
| {
"language": "Assembly"
} |
#if 0
//
// Generated by Microsoft (R) D3D Shader Disassembler
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position 0 xyzw 0 NONE float xyzw
// TEXCOORD 0 xy 1 NONE float xy
// COLOR 0 xyzw 2 NONE float xyzw
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// COLOR 0 xyzw 0 NONE float xyzw
// TEXCOORD 0 xy 1 NONE float xy
// SV_Position 0 xyzw 2 POS float xyzw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c1 cb0 0 1 ( FLT, FLT, FLT, FLT)
// c2 cb0 4 4 ( FLT, FLT, FLT, FLT)
//
//
// Runtime generated constant mappings:
//
// Target Reg Constant Description
// ---------- --------------------------------------------------
// c0 Vertex Shader position offset
//
//
// Level9 shader bytecode:
//
vs_2_0
dcl_texcoord v0 // vin<0,1,2,3>
dcl_texcoord1 v1 // vin<4,5>
dcl_texcoord2 v2 // vin<6,7,8,9>
#line 43 "D:\Microsoft\DirectXTK\Src\Shaders\Common.fxh"
dp4 oPos.z, v0, c4 // ::VSAlphaTestVcNoFog<8>
#line 82 "D:\Microsoft\DirectXTK\Src\Shaders\AlphaTestEffect.fx"
mul oT0, v2, c1 // ::VSAlphaTestVcNoFog<0,1,2,3>
#line 43 "D:\Microsoft\DirectXTK\Src\Shaders\Common.fxh"
dp4 r0.x, v0, c2 // ::vout<0>
dp4 r0.y, v0, c3 // ::vout<1>
dp4 r0.z, v0, c5 // ::vout<3>
#line 74 "D:\Microsoft\DirectXTK\Src\Shaders\AlphaTestEffect.fx"
mad oPos.xy, r0.z, c0, r0 // ::VSAlphaTestVcNoFog<6,7>
mov oPos.w, r0.z // ::VSAlphaTestVcNoFog<9>
#line 81
mov oT1.xy, v1 // ::VSAlphaTestVcNoFog<4,5>
// approximately 8 instruction slots used
vs_4_0
dcl_constantbuffer CB0[8], immediateIndexed
dcl_input v0.xyzw
dcl_input v1.xy
dcl_input v2.xyzw
dcl_output o0.xyzw
dcl_output o1.xy
dcl_output_siv o2.xyzw, position
mul o0.xyzw, v2.xyzw, cb0[0].xyzw
mov o1.xy, v1.xyxx
dp4 o2.x, v0.xyzw, cb0[4].xyzw
dp4 o2.y, v0.xyzw, cb0[5].xyzw
dp4 o2.z, v0.xyzw, cb0[6].xyzw
dp4 o2.w, v0.xyzw, cb0[7].xyzw
ret
// Approximately 0 instruction slots used
#endif
const BYTE AlphaTestEffect_VSAlphaTestVcNoFog[] =
{
68, 88, 66, 67, 5, 5,
148, 150, 213, 52, 240, 235,
251, 19, 26, 3, 56, 247,
90, 70, 1, 0, 0, 0,
52, 6, 0, 0, 4, 0,
0, 0, 48, 0, 0, 0,
40, 4, 0, 0, 76, 5,
0, 0, 192, 5, 0, 0,
65, 111, 110, 57, 240, 3,
0, 0, 240, 3, 0, 0,
0, 2, 254, 255, 176, 3,
0, 0, 64, 0, 0, 0,
2, 0, 36, 0, 0, 0,
60, 0, 0, 0, 60, 0,
0, 0, 36, 0, 1, 0,
60, 0, 0, 0, 0, 0,
1, 0, 1, 0, 0, 0,
0, 0, 0, 0, 4, 0,
4, 0, 2, 0, 0, 0,
0, 0, 0, 0, 0, 0,
0, 2, 254, 255, 254, 255,
193, 0, 68, 66, 85, 71,
40, 0, 0, 0, 216, 2,
0, 0, 0, 0, 0, 0,
2, 0, 0, 0, 140, 0,
0, 0, 11, 0, 0, 0,
148, 0, 0, 0, 3, 0,
0, 0, 156, 2, 0, 0,
236, 0, 0, 0, 68, 58,
92, 77, 105, 99, 114, 111,
115, 111, 102, 116, 92, 68,
105, 114, 101, 99, 116, 88,
84, 75, 92, 83, 114, 99,
92, 83, 104, 97, 100, 101,
114, 115, 92, 67, 111, 109,
109, 111, 110, 46, 102, 120,
104, 0, 68, 58, 92, 77,
105, 99, 114, 111, 115, 111,
102, 116, 92, 68, 105, 114,
101, 99, 116, 88, 84, 75,
92, 83, 114, 99, 92, 83,
104, 97, 100, 101, 114, 115,
92, 65, 108, 112, 104, 97,
84, 101, 115, 116, 69, 102,
102, 101, 99, 116, 46, 102,
120, 0, 40, 0, 0, 0,
86, 0, 0, 0, 0, 0,
255, 255, 12, 3, 0, 0,
0, 0, 255, 255, 24, 3,
0, 0, 0, 0, 255, 255,
36, 3, 0, 0, 43, 0,
0, 0, 48, 3, 0, 0,
82, 0, 1, 0, 64, 3,
0, 0, 43, 0, 0, 0,
80, 3, 0, 0, 43, 0,
0, 0, 96, 3, 0, 0,
43, 0, 0, 0, 112, 3,
0, 0, 74, 0, 1, 0,
128, 3, 0, 0, 74, 0,
1, 0, 148, 3, 0, 0,
81, 0, 1, 0, 160, 3,
0, 0, 86, 83, 65, 108,
112, 104, 97, 84, 101, 115,
116, 86, 99, 78, 111, 70,
111, 103, 0, 68, 105, 102,
102, 117, 115, 101, 0, 171,
1, 0, 3, 0, 1, 0,
4, 0, 1, 0, 0, 0,
0, 0, 0, 0, 84, 101,
120, 67, 111, 111, 114, 100,
0, 171, 171, 171, 1, 0,
3, 0, 1, 0, 2, 0,
1, 0, 0, 0, 0, 0,
0, 0, 80, 111, 115, 105,
116, 105, 111, 110, 80, 83,
0, 171, 255, 0, 0, 0,
8, 1, 0, 0, 24, 1,
0, 0, 36, 1, 0, 0,
52, 1, 0, 0, 8, 1,
0, 0, 5, 0, 0, 0,
1, 0, 10, 0, 1, 0,
3, 0, 64, 1, 0, 0,
3, 0, 0, 0, 255, 255,
255, 255, 8, 0, 255, 255,
4, 0, 0, 0, 0, 0,
1, 0, 2, 0, 3, 0,
8, 0, 0, 0, 6, 0,
7, 0, 255, 255, 255, 255,
9, 0, 0, 0, 255, 255,
255, 255, 255, 255, 9, 0,
10, 0, 0, 0, 4, 0,
5, 0, 255, 255, 255, 255,
118, 105, 110, 0, 80, 111,
115, 105, 116, 105, 111, 110,
0, 67, 111, 108, 111, 114,
0, 171, 168, 1, 0, 0,
8, 1, 0, 0, 24, 1,
0, 0, 36, 1, 0, 0,
177, 1, 0, 0, 8, 1,
0, 0, 5, 0, 0, 0,
1, 0, 10, 0, 1, 0,
3, 0, 184, 1, 0, 0,
0, 0, 0, 0, 0, 0,
1, 0, 2, 0, 3, 0,
1, 0, 0, 0, 4, 0,
5, 0, 255, 255, 255, 255,
2, 0, 0, 0, 6, 0,
7, 0, 8, 0, 9, 0,
118, 111, 117, 116, 0, 80,
111, 115, 95, 112, 115, 0,
83, 112, 101, 99, 117, 108,
97, 114, 0, 171, 171, 171,
1, 0, 3, 0, 1, 0,
3, 0, 1, 0, 0, 0,
0, 0, 0, 0, 70, 111,
103, 70, 97, 99, 116, 111,
114, 0, 171, 171, 0, 0,
3, 0, 1, 0, 1, 0,
1, 0, 0, 0, 0, 0,
0, 0, 9, 2, 0, 0,
8, 1, 0, 0, 255, 0,
0, 0, 8, 1, 0, 0,
16, 2, 0, 0, 28, 2,
0, 0, 44, 2, 0, 0,
56, 2, 0, 0, 5, 0,
0, 0, 1, 0, 12, 0,
1, 0, 4, 0, 72, 2,
0, 0, 5, 0, 0, 0,
0, 0, 255, 255, 255, 255,
255, 255, 6, 0, 0, 0,
255, 255, 1, 0, 255, 255,
255, 255, 7, 0, 0, 0,
255, 255, 255, 255, 3, 0,
255, 255, 0, 0, 0, 0,
236, 0, 0, 0, 88, 1,
0, 0, 5, 0, 0, 0,
104, 1, 0, 0, 236, 0,
0, 0, 164, 1, 0, 0,
208, 1, 0, 0, 3, 0,
0, 0, 224, 1, 0, 0,
0, 0, 0, 0, 4, 2,
0, 0, 104, 2, 0, 0,
3, 0, 0, 0, 120, 2,
0, 0, 77, 105, 99, 114,
111, 115, 111, 102, 116, 32,
40, 82, 41, 32, 72, 76,
83, 76, 32, 83, 104, 97,
100, 101, 114, 32, 67, 111,
109, 112, 105, 108, 101, 114,
32, 49, 48, 46, 49, 0,
31, 0, 0, 2, 5, 0,
0, 128, 0, 0, 15, 144,
31, 0, 0, 2, 5, 0,
1, 128, 1, 0, 15, 144,
31, 0, 0, 2, 5, 0,
2, 128, 2, 0, 15, 144,
9, 0, 0, 3, 0, 0,
4, 192, 0, 0, 228, 144,
4, 0, 228, 160, 5, 0,
0, 3, 0, 0, 15, 224,
2, 0, 228, 144, 1, 0,
228, 160, 9, 0, 0, 3,
0, 0, 1, 128, 0, 0,
228, 144, 2, 0, 228, 160,
9, 0, 0, 3, 0, 0,
2, 128, 0, 0, 228, 144,
3, 0, 228, 160, 9, 0,
0, 3, 0, 0, 4, 128,
0, 0, 228, 144, 5, 0,
228, 160, 4, 0, 0, 4,
0, 0, 3, 192, 0, 0,
170, 128, 0, 0, 228, 160,
0, 0, 228, 128, 1, 0,
0, 2, 0, 0, 8, 192,
0, 0, 170, 128, 1, 0,
0, 2, 1, 0, 3, 224,
1, 0, 228, 144, 255, 255,
0, 0, 83, 72, 68, 82,
28, 1, 0, 0, 64, 0,
1, 0, 71, 0, 0, 0,
89, 0, 0, 4, 70, 142,
32, 0, 0, 0, 0, 0,
8, 0, 0, 0, 95, 0,
0, 3, 242, 16, 16, 0,
0, 0, 0, 0, 95, 0,
0, 3, 50, 16, 16, 0,
1, 0, 0, 0, 95, 0,
0, 3, 242, 16, 16, 0,
2, 0, 0, 0, 101, 0,
0, 3, 242, 32, 16, 0,
0, 0, 0, 0, 101, 0,
0, 3, 50, 32, 16, 0,
1, 0, 0, 0, 103, 0,
0, 4, 242, 32, 16, 0,
2, 0, 0, 0, 1, 0,
0, 0, 56, 0, 0, 8,
242, 32, 16, 0, 0, 0,
0, 0, 70, 30, 16, 0,
2, 0, 0, 0, 70, 142,
32, 0, 0, 0, 0, 0,
0, 0, 0, 0, 54, 0,
0, 5, 50, 32, 16, 0,
1, 0, 0, 0, 70, 16,
16, 0, 1, 0, 0, 0,
17, 0, 0, 8, 18, 32,
16, 0, 2, 0, 0, 0,
70, 30, 16, 0, 0, 0,
0, 0, 70, 142, 32, 0,
0, 0, 0, 0, 4, 0,
0, 0, 17, 0, 0, 8,
34, 32, 16, 0, 2, 0,
0, 0, 70, 30, 16, 0,
0, 0, 0, 0, 70, 142,
32, 0, 0, 0, 0, 0,
5, 0, 0, 0, 17, 0,
0, 8, 66, 32, 16, 0,
2, 0, 0, 0, 70, 30,
16, 0, 0, 0, 0, 0,
70, 142, 32, 0, 0, 0,
0, 0, 6, 0, 0, 0,
17, 0, 0, 8, 130, 32,
16, 0, 2, 0, 0, 0,
70, 30, 16, 0, 0, 0,
0, 0, 70, 142, 32, 0,
0, 0, 0, 0, 7, 0,
0, 0, 62, 0, 0, 1,
73, 83, 71, 78, 108, 0,
0, 0, 3, 0, 0, 0,
8, 0, 0, 0, 80, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 3, 0,
0, 0, 0, 0, 0, 0,
15, 15, 0, 0, 92, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 3, 0,
0, 0, 1, 0, 0, 0,
3, 3, 0, 0, 101, 0,
0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 3, 0,
0, 0, 2, 0, 0, 0,
15, 15, 0, 0, 83, 86,
95, 80, 111, 115, 105, 116,
105, 111, 110, 0, 84, 69,
88, 67, 79, 79, 82, 68,
0, 67, 79, 76, 79, 82,
0, 171, 79, 83, 71, 78,
108, 0, 0, 0, 3, 0,
0, 0, 8, 0, 0, 0,
80, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
3, 0, 0, 0, 0, 0,
0, 0, 15, 0, 0, 0,
86, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
3, 0, 0, 0, 1, 0,
0, 0, 3, 12, 0, 0,
95, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0,
3, 0, 0, 0, 2, 0,
0, 0, 15, 0, 0, 0,
67, 79, 76, 79, 82, 0,
84, 69, 88, 67, 79, 79,
82, 68, 0, 83, 86, 95,
80, 111, 115, 105, 116, 105,
111, 110, 0, 171
};
| {
"language": "Assembly"
} |
/*****************************************************************
|
| Neptune - Trust Anchors
|
| This file is automatically generated by a script, do not edit!
|
| Copyright (c) 2002-2010, Axiomatic Systems, LLC.
| All rights reserved.
|
| Redistribution and use in source and binary forms, with or without
| modification, are permitted provided that the following conditions are met:
| * Redistributions of source code must retain the above copyright
| notice, this list of conditions and the following disclaimer.
| * Redistributions in binary form must reproduce the above copyright
| notice, this list of conditions and the following disclaimer in the
| documentation and/or other materials provided with the distribution.
| * Neither the name of Axiomatic Systems nor the
| names of its contributors may be used to endorse or promote products
| derived from this software without specific prior written permission.
|
| THIS SOFTWARE IS PROVIDED BY AXIOMATIC SYSTEMS ''AS IS'' AND ANY
| EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
| WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
| DISCLAIMED. IN NO EVENT SHALL AXIOMATIC SYSTEMS BE LIABLE FOR ANY
| DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
| (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
| LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
| ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
| (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
| SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
****************************************************************/
/* TDC OCES Root CA */
const unsigned char NptTlsTrustAnchor_Base_0083_Data[1309] = {
0x30,0x82,0x05,0x19,0x30,0x82,0x04,0x01
,0xa0,0x03,0x02,0x01,0x02,0x02,0x04,0x3e
,0x48,0xbd,0xc4,0x30,0x0d,0x06,0x09,0x2a
,0x86,0x48,0x86,0xf7,0x0d,0x01,0x01,0x05
,0x05,0x00,0x30,0x31,0x31,0x0b,0x30,0x09
,0x06,0x03,0x55,0x04,0x06,0x13,0x02,0x44
,0x4b,0x31,0x0c,0x30,0x0a,0x06,0x03,0x55
,0x04,0x0a,0x13,0x03,0x54,0x44,0x43,0x31
,0x14,0x30,0x12,0x06,0x03,0x55,0x04,0x03
,0x13,0x0b,0x54,0x44,0x43,0x20,0x4f,0x43
,0x45,0x53,0x20,0x43,0x41,0x30,0x1e,0x17
,0x0d,0x30,0x33,0x30,0x32,0x31,0x31,0x30
,0x38,0x33,0x39,0x33,0x30,0x5a,0x17,0x0d
,0x33,0x37,0x30,0x32,0x31,0x31,0x30,0x39
,0x30,0x39,0x33,0x30,0x5a,0x30,0x31,0x31
,0x0b,0x30,0x09,0x06,0x03,0x55,0x04,0x06
,0x13,0x02,0x44,0x4b,0x31,0x0c,0x30,0x0a
,0x06,0x03,0x55,0x04,0x0a,0x13,0x03,0x54
,0x44,0x43,0x31,0x14,0x30,0x12,0x06,0x03
,0x55,0x04,0x03,0x13,0x0b,0x54,0x44,0x43
,0x20,0x4f,0x43,0x45,0x53,0x20,0x43,0x41
,0x30,0x82,0x01,0x22,0x30,0x0d,0x06,0x09
,0x2a,0x86,0x48,0x86,0xf7,0x0d,0x01,0x01
,0x01,0x05,0x00,0x03,0x82,0x01,0x0f,0x00
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,0x0a,0x19,0x8f,0xc9,0x01,0x3e,0x74,0x5d
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,0x71,0xa6,0x98,0x6f,0xb6,0x7c,0xbd,0x37
,0x7f,0xbe,0xe1,0x93,0x25,0x6d,0x6f,0xf0
,0x0a,0xad,0x17,0x18,0xe1,0x03,0xbc,0x07
,0x29,0xc8,0xad,0x26,0xe8,0xf8,0x61,0xf0
,0xfd,0x21,0x09,0x7e,0x9a,0x8e,0xa9,0x68
,0x7d,0x48,0x62,0x72,0xbd,0x00,0xea,0x01
,0x99,0xb8,0x06,0x82,0x51,0x81,0x4e,0xf1
,0xf5,0xb4,0x91,0x54,0xb9,0x23,0x7a,0x00
,0x9a,0x9f,0x5d,0x8d,0xe0,0x3c,0x64,0xb9
,0x1a,0x12,0x92,0x2a,0xc7,0x82,0x44,0x72
,0x39,0xdc,0xe2,0x3c,0xc6,0xd8,0x55,0xf5
,0x15,0x4e,0xc8,0x05,0x0e,0xdb,0xc6,0xd0
,0x62,0xa6,0xec,0x15,0xb4,0xb5,0x02,0x82
,0xdb,0xac,0x8c,0xa2,0x81,0xf0,0x9b,0x99
,0x31,0xf5,0x20,0x20,0xa8,0x88,0x61,0x0a
,0x07,0x9f,0x94,0xfc,0xd0,0xd7,0x1b,0xcc
,0x2e,0x17,0xf3,0x04,0x27,0x76,0x67,0xeb
,0x54,0x83,0xfd,0xa4,0x90,0x7e,0x06,0x3d
,0x04,0xa3,0x43,0x2d,0xda,0xfc,0x0b,0x62
,0xea,0x2f,0x5f,0x62,0x53};
const unsigned int NptTlsTrustAnchor_Base_0083_Size = 1309;
| {
"language": "Assembly"
} |
// Modified by Princeton University on June 9th, 2015
/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T1 Processor File: fdivd_rnd_pinf.s
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
/***********************************************************************
* Name: fdivd_rnd_pinf.s
* Date: 11/6/02
*
*
**********************************************************************/
#define ENABLE_T0_Fp_disabled_0x20
#include "boot.s"
.global sam_fast_immu_miss
.global sam_fast_dmmu_miss
.text
.global main
! Testing fdivd with rounding mode pinf
!// fdivd_rnd_pinf
!//
!// Tests FDIVD in round to positive infinity mode
!// Inputs are positive and negative:
!// - infinity by infinity
!// - infinity by NaN
!// - NaN by infinity
!// - NaN by NaN
!// - infinity by norm/denorm/zero
!// - NaN by norm/denorm/zero
!// - norm/denorm/zero by infinity
!// - norm/denorm/zero by NaN
!// - norm/denorm/zero by norm/denorm/zero
main:
! Common code
wr %g0, 0x4, %fprs ! make sure fef is 1
setx source1, %l0, %l1
setx source2, %l0, %l2
setx result, %l0, %l3
setx fcc_result, %l0, %l4
setx cexc_flag, %l0, %l5
setx fsr_rounding_mode, %l0, %l6
setx scratch, %l0, %l7
set 345, %g1 ! Set loop count
set 0x0, %g2 ! Set loop iterator
fdivd_loop:
ldx [%l6+0x0], %fsr
! instruction specific code
sll %g2, 0x3, %g3
ldx [%l6], %fsr ! Load fsr with rounding mode
ldd [%l1+%g3], %f0 ! Load source 1
ldd [%l2+%g3], %f2 ! Load source 2
fdivd %f0, %f2, %f4 ! Perform the operation
std %f4, [%l7+0x0] ! Store the result for comparison
stx %fsr, [%l7+0x8] ! Store the fsr for comparison
ldx [%l7+0x0], %g4 ! Load result from memory for comparison
ldx [%l7+0x8], %g5 ! Load fsr from memory for comparison
sll %g2, 0x3, %g3
ldx [%l5+%g3], %g6 ! Load fsr with expected cexc mode
mov 0x0f, %g3 ! Mask for nv
and %g3, %g6, %g7 ! Mask off nv
srl %g7, 0x3, %g7 ! Shift to get of
or %g7, %g6, %g6 ! Generate correct nx with of
mov 0x01, %g3 ! Mask to get nx
and %g3, %g6, %g7 ! Mask off all but nx
sll %g7, 0x2, %g7 ! Shift to align nx and uf
or %g7, 0x1b, %g7 ! Mask for all cexc bits
and %g7, %g6, %g6 ! Generate correct uf for denorm
sll %g6, 0x5, %g7 ! Generate aexc
or %g6, %g7, %g7 ! Generate expected fsr
ldx [%l6], %g6 ! Load fsr with rounding mode
or %g6, %g7, %g7 ! Generate expected fsr
sll %g2, 0x3, %g3
ldx [%l3+%g3], %g6 ! Load expected result
subcc %g4, %g6, %g0 ! Compare
bne,a test_fail ! If not equal, test failed
nop
subcc %g5, %g7, %g0 ! Compare
bne,a test_fail ! If not equal, test failed
nop
add %g2, 0x1, %g2 ! Increment loop iterator
subcc %g2, %g1, %g0 ! Compare
bne,a fdivd_loop ! Loop
nop
/*******************************************************
* Exit code
*******************************************************/
test_pass:
ta T_GOOD_TRAP
test_fail:
ta T_BAD_TRAP
/*******************************************************
* Data section
*******************************************************/
.data
fsr_rounding_mode:
.xword 0x0000000080000000
source1:
.xword 0x7ff0000000000000
.xword 0x7ff0000000000000
.xword 0xfff0000000000000
.xword 0xfff0000000000000
.xword 0x7ff0000000000000
.xword 0x7ff0000000000000
.xword 0x7ff0000000000000
.xword 0x7ff0000000000000
.xword 0xfff0000000000000
.xword 0xfff0000000000000
.xword 0xfff0000000000000
.xword 0xfff0000000000000
.xword 0x7ff0123456789abc
.xword 0xfff0123456789abc
.xword 0x7fffedcba9876543
.xword 0xffffedcba9876543
.xword 0x7ff0123456789abc
.xword 0xfff0123456789abc
.xword 0x7fffedcba9876543
.xword 0xffffedcba9876543
.xword 0x7ff012345678000c
.xword 0x7ff012345678000c
.xword 0x7ff0123456789abc
.xword 0x7ff0123456789abc
.xword 0xfff012345678000c
.xword 0xfff012345678000c
.xword 0xfff0123456789abc
.xword 0xfff0123456789abc
.xword 0x7fffedcba9876543
.xword 0x7fffedcba9876543
.xword 0x7fffedcba9870003
.xword 0x7fffedcba9870003
.xword 0xffffedcba9876543
.xword 0xffffedcba9876543
.xword 0xffffedcba9870003
.xword 0xffffedcba9870003
.xword 0xfff0123456789abc
.xword 0xfff0123456789abc
.xword 0x7ff0123456789abc
.xword 0x7ff0123456789abc
.xword 0xffffedcba9876543
.xword 0xffffedcba9876543
.xword 0x7fffedcba9876543
.xword 0x7fffedcba9876543
.xword 0x7ff0000000000000
.xword 0x7ff0000000000000
.xword 0x7ff0000000000000
.xword 0x7ff0000000000000
.xword 0x7ff0000000000000
.xword 0x7ff0000000000000
.xword 0x7ff0000000000000
.xword 0x7ff0000000000000
.xword 0x7ff0000000000000
.xword 0x7ff0000000000000
.xword 0x7ff0000000000000
.xword 0x7ff0000000000000
.xword 0xfff0000000000000
.xword 0xfff0000000000000
.xword 0xfff0000000000000
.xword 0xfff0000000000000
.xword 0xfff0000000000000
.xword 0xfff0000000000000
.xword 0xfff0000000000000
.xword 0xfff0000000000000
.xword 0xfff0000000000000
.xword 0xfff0000000000000
.xword 0xfff0000000000000
.xword 0xfff0000000000000
.xword 0x7ff0123456789abc
.xword 0x7ff0123456789abc
.xword 0x7ff0123456789abc
.xword 0x7ff0123456789abc
.xword 0x7ff0123456789abc
.xword 0x7ff0123456789abc
.xword 0x7ff0123456789abc
.xword 0x7ff0123456789abc
.xword 0x7ff0123456789abc
.xword 0x7ff0123456789abc
.xword 0x7ff0123456789abc
.xword 0x7ff0123456789abc
.xword 0xfff0123456789abc
.xword 0xfff0123456789abc
.xword 0xfff0123456789abc
.xword 0xfff0123456789abc
.xword 0xfff0123456789abc
.xword 0xfff0123456789abc
.xword 0xfff0123456789abc
.xword 0xfff0123456789abc
.xword 0xfff0123456789abc
.xword 0xfff0123456789abc
.xword 0xfff0123456789abc
.xword 0xfff0123456789abc
.xword 0x7fffedcba9876543
.xword 0x7fffedcba9876543
.xword 0x7fffedcba9876543
.xword 0x7fffedcba9876543
.xword 0x7fffedcba9876543
.xword 0x7fffedcba9876543
.xword 0x7fffedcba9876543
.xword 0x7fffedcba9876543
.xword 0x7fffedcba9876543
.xword 0x7fffedcba9876543
.xword 0x7fffedcba9876543
.xword 0x7fffedcba9876543
.xword 0xffffedcba9876543
.xword 0xffffedcba9876543
.xword 0xffffedcba9876543
.xword 0xffffedcba9876543
.xword 0xffffedcba9876543
.xword 0xffffedcba9876543
.xword 0xffffedcba9876543
.xword 0xffffedcba9876543
.xword 0xffffedcba9876543
.xword 0xffffedcba9876543
.xword 0xffffedcba9876543
.xword 0xffffedcba9876543
.xword 0x7fefffffffffffff
.xword 0x3ff0000000000000
.xword 0x0010000000000000
.xword 0x000fffffffffffff
.xword 0x0000000000000001
.xword 0x0000000000000000
.xword 0xffefffffffffffff
.xword 0xbff0000000000000
.xword 0x8010000000000000
.xword 0x800fffffffffffff
.xword 0x8000000000000001
.xword 0x8000000000000000
.xword 0x7fefffffffffffff
.xword 0x3ff0000000000000
.xword 0x0010000000000000
.xword 0x000fffffffffffff
.xword 0x0000000000000001
.xword 0x0000000000000000
.xword 0xffefffffffffffff
.xword 0xbff0000000000000
.xword 0x8010000000000000
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| {
"language": "Assembly"
} |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in
; the documentation and/or other materials provided with the
; distribution.
; * Neither the name of Intel Corporation nor the names of its
; contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Function API:
; UINT16 crc16_t10dif_by4(
; UINT16 init_crc, //initial CRC value, 16 bits
; const unsigned char *buf, //buffer pointer to calculate CRC on
; UINT64 len //buffer length in bytes (64-bit data)
; );
;
; Authors:
; Erdinc Ozturk
; Vinodh Gopal
; James Guilford
;
; Reference paper titled "Fast CRC Computation for Generic Polynomials Using PCLMULQDQ Instruction"
; URL: http://download.intel.com/design/intarch/papers/323102.pdf
;
%include "reg_sizes.asm"
%define fetch_dist 1024
[bits 64]
default rel
section .text
%ifidn __OUTPUT_FORMAT__, win64
%xdefine arg1 rcx
%xdefine arg2 rdx
%xdefine arg3 r8
%xdefine arg1_low32 ecx
%else
%xdefine arg1 rdi
%xdefine arg2 rsi
%xdefine arg3 rdx
%xdefine arg1_low32 edi
%endif
align 16
global crc16_t10dif_by4:function
crc16_t10dif_by4:
; adjust the 16-bit initial_crc value, scale it to 32 bits
shl arg1_low32, 16
; After this point, code flow is exactly same as a 32-bit CRC.
; The only difference is before returning eax, we will shift
; it right 16 bits, to scale back to 16 bits.
sub rsp,16*4+8
; push the xmm registers into the stack to maintain
movdqa [rsp+16*2],xmm6
movdqa [rsp+16*3],xmm7
; check if smaller than 128B
cmp arg3, 128
; for sizes less than 128, we can't fold 64B at a time...
jl _less_than_128
; load the initial crc value
movd xmm6, arg1_low32 ; initial crc
; crc value does not need to be byte-reflected, but it needs to
; be moved to the high part of the register.
; because data will be byte-reflected and will align with
; initial crc at correct place.
pslldq xmm6, 12
movdqa xmm7, [SHUF_MASK]
; receive the initial 64B data, xor the initial crc value
movdqu xmm0, [arg2]
movdqu xmm1, [arg2+16]
movdqu xmm2, [arg2+32]
movdqu xmm3, [arg2+48]
pshufb xmm0, xmm7
; XOR the initial_crc value
pxor xmm0, xmm6
pshufb xmm1, xmm7
pshufb xmm2, xmm7
pshufb xmm3, xmm7
movdqa xmm6, [rk3] ;xmm6 has rk3 and rk4
;imm value of pclmulqdq instruction
;will determine which constant to use
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; we subtract 128 instead of 64 to save one instruction from the loop
sub arg3, 128
; at this section of the code, there is 64*x+y (0<=y<64) bytes of
; buffer. The _fold_64_B_loop
; loop will fold 64B at a time until we have 64+y Bytes of buffer
; fold 64B at a time. This section of the code folds 4 xmm
; registers in parallel
_fold_64_B_loop:
; update the buffer pointer
add arg2, 64 ; buf += 64;
prefetchnta [arg2+fetch_dist+0]
movdqu xmm4, xmm0
movdqu xmm5, xmm1
pclmulqdq xmm0, xmm6 , 0x11
pclmulqdq xmm1, xmm6 , 0x11
pclmulqdq xmm4, xmm6, 0x0
pclmulqdq xmm5, xmm6, 0x0
pxor xmm0, xmm4
pxor xmm1, xmm5
prefetchnta [arg2+fetch_dist+32]
movdqu xmm4, xmm2
movdqu xmm5, xmm3
pclmulqdq xmm2, xmm6, 0x11
pclmulqdq xmm3, xmm6, 0x11
pclmulqdq xmm4, xmm6, 0x0
pclmulqdq xmm5, xmm6, 0x0
pxor xmm2, xmm4
pxor xmm3, xmm5
movdqu xmm4, [arg2]
movdqu xmm5, [arg2+16]
pshufb xmm4, xmm7
pshufb xmm5, xmm7
pxor xmm0, xmm4
pxor xmm1, xmm5
movdqu xmm4, [arg2+32]
movdqu xmm5, [arg2+48]
pshufb xmm4, xmm7
pshufb xmm5, xmm7
pxor xmm2, xmm4
pxor xmm3, xmm5
sub arg3, 64
; check if there is another 64B in the buffer to be able to fold
jge _fold_64_B_loop
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
add arg2, 64
; at this point, the buffer pointer is pointing at the last y Bytes of the buffer
; the 64B of folded data is in 4 of the xmm registers: xmm0, xmm1, xmm2, xmm3
; fold the 4 xmm registers to 1 xmm register with different constants
movdqa xmm6, [rk1] ;xmm6 has rk1 and rk2
;imm value of pclmulqdq instruction will
;determine which constant to use
movdqa xmm4, xmm0
pclmulqdq xmm0, xmm6, 0x11
pclmulqdq xmm4, xmm6, 0x0
pxor xmm1, xmm4
pxor xmm1, xmm0
movdqa xmm4, xmm1
pclmulqdq xmm1, xmm6, 0x11
pclmulqdq xmm4, xmm6, 0x0
pxor xmm2, xmm4
pxor xmm2, xmm1
movdqa xmm4, xmm2
pclmulqdq xmm2, xmm6, 0x11
pclmulqdq xmm4, xmm6, 0x0
pxor xmm3, xmm4
pxor xmm3, xmm2
; instead of 64, we add 48 to the loop counter to save 1 instruction from the loop
; instead of a cmp instruction, we use the negative flag with the jl instruction
add arg3, 64-16
jl _final_reduction_for_128
; now we have 16+y bytes left to reduce. 16 Bytes
; is in register xmm3 and the rest is in memory
; we can fold 16 bytes at a time if y>=16
; continue folding 16B at a time
_16B_reduction_loop:
movdqa xmm4, xmm3
pclmulqdq xmm3, xmm6, 0x11
pclmulqdq xmm4, xmm6, 0x0
pxor xmm3, xmm4
movdqu xmm0, [arg2]
pshufb xmm0, xmm7
pxor xmm3, xmm0
add arg2, 16
sub arg3, 16
; instead of a cmp instruction, we utilize the flags with the jge instruction
; equivalent of: cmp arg3, 16-16
; check if there is any more 16B in the buffer to be able to fold
jge _16B_reduction_loop
;now we have 16+z bytes left to reduce, where 0<= z < 16.
;first, we reduce the data in the xmm3 register
_final_reduction_for_128:
; check if any more data to fold. If not, compute the CRC of the final 128 bits
add arg3, 16
je _128_done
; here we are getting data that is less than 16 bytes.
; since we know that there was data before the pointer,
; we can offset the input pointer before the actual point,
; to receive exactly 16 bytes.
; after that the registers need to be adjusted.
_get_last_two_xmms:
movdqa xmm2, xmm3
movdqu xmm1, [arg2 - 16 + arg3]
pshufb xmm1, xmm7
; get rid of the extra data that was loaded before
; load the shift constant
lea rax, [pshufb_shf_table + 16]
sub rax, arg3
movdqu xmm0, [rax]
; shift xmm2 to the left by arg3 bytes
pshufb xmm2, xmm0
; shift xmm3 to the right by 16-arg3 bytes
pxor xmm0, [mask1]
pshufb xmm3, xmm0
pblendvb xmm1, xmm2 ;xmm0 is implicit
; fold 16 Bytes
movdqa xmm2, xmm1
movdqa xmm4, xmm3
pclmulqdq xmm3, xmm6, 0x11
pclmulqdq xmm4, xmm6, 0x0
pxor xmm3, xmm4
pxor xmm3, xmm2
_128_done:
; compute crc of a 128-bit value
movdqa xmm6, [rk5] ; rk5 and rk6 in xmm6
movdqa xmm0, xmm3
;64b fold
pclmulqdq xmm3, xmm6, 0x1
pslldq xmm0, 8
pxor xmm3, xmm0
;32b fold
movdqa xmm0, xmm3
pand xmm0, [mask2]
psrldq xmm3, 12
pclmulqdq xmm3, xmm6, 0x10
pxor xmm3, xmm0
;barrett reduction
_barrett:
movdqa xmm6, [rk7] ; rk7 and rk8 in xmm6
movdqa xmm0, xmm3
pclmulqdq xmm3, xmm6, 0x01
pslldq xmm3, 4
pclmulqdq xmm3, xmm6, 0x11
pslldq xmm3, 4
pxor xmm3, xmm0
pextrd eax, xmm3,1
_cleanup:
; scale the result back to 16 bits
shr eax, 16
movdqa xmm6, [rsp+16*2]
movdqa xmm7, [rsp+16*3]
add rsp,16*4+8
ret
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
align 16
_less_than_128:
; check if there is enough buffer to be able to fold 16B at a time
cmp arg3, 32
jl _less_than_32
movdqa xmm7, [SHUF_MASK]
; if there is, load the constants
movdqa xmm6, [rk1] ; rk1 and rk2 in xmm6
movd xmm0, arg1_low32 ; get the initial crc value
pslldq xmm0, 12 ; align it to its correct place
movdqu xmm3, [arg2] ; load the plaintext
pshufb xmm3, xmm7 ; byte-reflect the plaintext
pxor xmm3, xmm0
; update the buffer pointer
add arg2, 16
; update the counter. subtract 32 instead of 16 to save one instruction from the loop
sub arg3, 32
jmp _16B_reduction_loop
align 16
_less_than_32:
; mov initial crc to the return value. this is necessary for zero-length buffers.
mov eax, arg1_low32
test arg3, arg3
je _cleanup
movdqa xmm7, [SHUF_MASK]
movd xmm0, arg1_low32 ; get the initial crc value
pslldq xmm0, 12 ; align it to its correct place
cmp arg3, 16
je _exact_16_left
jl _less_than_16_left
movdqu xmm3, [arg2] ; load the plaintext
pshufb xmm3, xmm7 ; byte-reflect the plaintext
pxor xmm3, xmm0 ; xor the initial crc value
add arg2, 16
sub arg3, 16
movdqa xmm6, [rk1] ; rk1 and rk2 in xmm6
jmp _get_last_two_xmms
align 16
_less_than_16_left:
; use stack space to load data less than 16 bytes, zero-out the 16B in memory first.
pxor xmm1, xmm1
mov r11, rsp
movdqa [r11], xmm1
cmp arg3, 4
jl _only_less_than_4
; backup the counter value
mov r9, arg3
cmp arg3, 8
jl _less_than_8_left
; load 8 Bytes
mov rax, [arg2]
mov [r11], rax
add r11, 8
sub arg3, 8
add arg2, 8
_less_than_8_left:
cmp arg3, 4
jl _less_than_4_left
; load 4 Bytes
mov eax, [arg2]
mov [r11], eax
add r11, 4
sub arg3, 4
add arg2, 4
_less_than_4_left:
cmp arg3, 2
jl _less_than_2_left
; load 2 Bytes
mov ax, [arg2]
mov [r11], ax
add r11, 2
sub arg3, 2
add arg2, 2
_less_than_2_left:
cmp arg3, 1
jl _zero_left
; load 1 Byte
mov al, [arg2]
mov [r11], al
_zero_left:
movdqa xmm3, [rsp]
pshufb xmm3, xmm7
pxor xmm3, xmm0 ; xor the initial crc value
; shl r9, 4
lea rax, [pshufb_shf_table + 16]
sub rax, r9
movdqu xmm0, [rax]
pxor xmm0, [mask1]
pshufb xmm3, xmm0
jmp _128_done
align 16
_exact_16_left:
movdqu xmm3, [arg2]
pshufb xmm3, xmm7
pxor xmm3, xmm0 ; xor the initial crc value
jmp _128_done
_only_less_than_4:
cmp arg3, 3
jl _only_less_than_3
; load 3 Bytes
mov al, [arg2]
mov [r11], al
mov al, [arg2+1]
mov [r11+1], al
mov al, [arg2+2]
mov [r11+2], al
movdqa xmm3, [rsp]
pshufb xmm3, xmm7
pxor xmm3, xmm0 ; xor the initial crc value
psrldq xmm3, 5
jmp _barrett
_only_less_than_3:
cmp arg3, 2
jl _only_less_than_2
; load 2 Bytes
mov al, [arg2]
mov [r11], al
mov al, [arg2+1]
mov [r11+1], al
movdqa xmm3, [rsp]
pshufb xmm3, xmm7
pxor xmm3, xmm0 ; xor the initial crc value
psrldq xmm3, 6
jmp _barrett
_only_less_than_2:
; load 1 Byte
mov al, [arg2]
mov [r11], al
movdqa xmm3, [rsp]
pshufb xmm3, xmm7
pxor xmm3, xmm0 ; xor the initial crc value
psrldq xmm3, 7
jmp _barrett
section .data
; precomputed constants
; these constants are precomputed from the poly: 0x8bb70000 (0x8bb7 scaled to 32 bits)
align 16
; Q = 0x18BB70000
; rk1 = 2^(32*3) mod Q << 32
; rk2 = 2^(32*5) mod Q << 32
; rk3 = 2^(32*15) mod Q << 32
; rk4 = 2^(32*17) mod Q << 32
; rk5 = 2^(32*3) mod Q << 32
; rk6 = 2^(32*2) mod Q << 32
; rk7 = floor(2^64/Q)
; rk8 = Q
rk1:
DQ 0x2d56000000000000
rk2:
DQ 0x06df000000000000
rk3:
DQ 0x044c000000000000
rk4:
DQ 0xe658000000000000
rk5:
DQ 0x2d56000000000000
rk6:
DQ 0x1368000000000000
rk7:
DQ 0x00000001f65a57f8
rk8:
DQ 0x000000018bb70000
mask1:
dq 0x8080808080808080, 0x8080808080808080
mask2:
dq 0xFFFFFFFFFFFFFFFF, 0x00000000FFFFFFFF
SHUF_MASK:
dq 0x08090A0B0C0D0E0F, 0x0001020304050607
pshufb_shf_table:
; use these values for shift constants for the pshufb instruction
; different alignments result in values as shown:
; dq 0x8887868584838281, 0x008f8e8d8c8b8a89 ; shl 15 (16-1) / shr1
; dq 0x8988878685848382, 0x01008f8e8d8c8b8a ; shl 14 (16-3) / shr2
; dq 0x8a89888786858483, 0x0201008f8e8d8c8b ; shl 13 (16-4) / shr3
; dq 0x8b8a898887868584, 0x030201008f8e8d8c ; shl 12 (16-4) / shr4
; dq 0x8c8b8a8988878685, 0x04030201008f8e8d ; shl 11 (16-5) / shr5
; dq 0x8d8c8b8a89888786, 0x0504030201008f8e ; shl 10 (16-6) / shr6
; dq 0x8e8d8c8b8a898887, 0x060504030201008f ; shl 9 (16-7) / shr7
; dq 0x8f8e8d8c8b8a8988, 0x0706050403020100 ; shl 8 (16-8) / shr8
; dq 0x008f8e8d8c8b8a89, 0x0807060504030201 ; shl 7 (16-9) / shr9
; dq 0x01008f8e8d8c8b8a, 0x0908070605040302 ; shl 6 (16-10) / shr10
; dq 0x0201008f8e8d8c8b, 0x0a09080706050403 ; shl 5 (16-11) / shr11
; dq 0x030201008f8e8d8c, 0x0b0a090807060504 ; shl 4 (16-12) / shr12
; dq 0x04030201008f8e8d, 0x0c0b0a0908070605 ; shl 3 (16-13) / shr13
; dq 0x0504030201008f8e, 0x0d0c0b0a09080706 ; shl 2 (16-14) / shr14
; dq 0x060504030201008f, 0x0e0d0c0b0a090807 ; shl 1 (16-15) / shr15
dq 0x8786858483828100, 0x8f8e8d8c8b8a8988
dq 0x0706050403020100, 0x000e0d0c0b0a0908
;;; func core, ver, snum
slversion crc16_t10dif_by4, 05, 02, 0016
| {
"language": "Assembly"
} |
/*
;uInt longest_match_x64(
; deflate_state *s,
; IPos cur_match); // current match
; gvmat64.S -- Asm portion of the optimized longest_match for 32 bits x86_64
; (AMD64 on Athlon 64, Opteron, Phenom
; and Intel EM64T on Pentium 4 with EM64T, Pentium D, Core 2 Duo, Core I5/I7)
; this file is translation from gvmat64.asm to GCC 4.x (for Linux, Mac XCode)
; Copyright (C) 1995-2010 Jean-loup Gailly, Brian Raiter and Gilles Vollant.
;
; File written by Gilles Vollant, by converting to assembly the longest_match
; from Jean-loup Gailly in deflate.c of zLib and infoZip zip.
; and by taking inspiration on asm686 with masm, optimised assembly code
; from Brian Raiter, written 1998
;
; This software is provided 'as-is', without any express or implied
; warranty. In no event will the authors be held liable for any damages
; arising from the use of this software.
;
; Permission is granted to anyone to use this software for any purpose,
; including commercial applications, and to alter it and redistribute it
; freely, subject to the following restrictions:
;
; 1. The origin of this software must not be misrepresented; you must not
; claim that you wrote the original software. If you use this software
; in a product, an acknowledgment in the product documentation would be
; appreciated but is not required.
; 2. Altered source versions must be plainly marked as such, and must not be
; misrepresented as being the original software
; 3. This notice may not be removed or altered from any source distribution.
;
; http://www.zlib.net
; http://www.winimage.com/zLibDll
; http://www.muppetlabs.com/~breadbox/software/assembly.html
;
; to compile this file for zLib, I use option:
; gcc -c -arch x86_64 gvmat64.S
;uInt longest_match(s, cur_match)
; deflate_state *s;
; IPos cur_match; // current match /
;
; with XCode for Mac, I had strange error with some jump on intel syntax
; this is why BEFORE_JMP and AFTER_JMP are used
*/
#define BEFORE_JMP .att_syntax
#define AFTER_JMP .intel_syntax noprefix
#ifndef NO_UNDERLINE
# define match_init _match_init
# define longest_match _longest_match
#endif
.intel_syntax noprefix
.globl match_init, longest_match
.text
longest_match:
#define LocalVarsSize 96
/*
; register used : rax,rbx,rcx,rdx,rsi,rdi,r8,r9,r10,r11,r12
; free register : r14,r15
; register can be saved : rsp
*/
#define chainlenwmask (rsp + 8 - LocalVarsSize)
#define nicematch (rsp + 16 - LocalVarsSize)
#define save_rdi (rsp + 24 - LocalVarsSize)
#define save_rsi (rsp + 32 - LocalVarsSize)
#define save_rbx (rsp + 40 - LocalVarsSize)
#define save_rbp (rsp + 48 - LocalVarsSize)
#define save_r12 (rsp + 56 - LocalVarsSize)
#define save_r13 (rsp + 64 - LocalVarsSize)
#define save_r14 (rsp + 72 - LocalVarsSize)
#define save_r15 (rsp + 80 - LocalVarsSize)
/*
; all the +4 offsets are due to the addition of pending_buf_size (in zlib
; in the deflate_state structure since the asm code was first written
; (if you compile with zlib 1.0.4 or older, remove the +4).
; Note : these value are good with a 8 bytes boundary pack structure
*/
#define MAX_MATCH 258
#define MIN_MATCH 3
#define MIN_LOOKAHEAD (MAX_MATCH+MIN_MATCH+1)
/*
;;; Offsets for fields in the deflate_state structure. These numbers
;;; are calculated from the definition of deflate_state, with the
;;; assumption that the compiler will dword-align the fields. (Thus,
;;; changing the definition of deflate_state could easily cause this
;;; program to crash horribly, without so much as a warning at
;;; compile time. Sigh.)
; all the +zlib1222add offsets are due to the addition of fields
; in zlib in the deflate_state structure since the asm code was first written
; (if you compile with zlib 1.0.4 or older, use "zlib1222add equ (-4)").
; (if you compile with zlib between 1.0.5 and 1.2.2.1, use "zlib1222add equ 0").
; if you compile with zlib 1.2.2.2 or later , use "zlib1222add equ 8").
*/
/* you can check the structure offset by running
#include <stdlib.h>
#include <stdio.h>
#include "deflate.h"
void print_depl()
{
deflate_state ds;
deflate_state *s=&ds;
printf("size pointer=%u\n",(int)sizeof(void*));
printf("#define dsWSize %u\n",(int)(((char*)&(s->w_size))-((char*)s)));
printf("#define dsWMask %u\n",(int)(((char*)&(s->w_mask))-((char*)s)));
printf("#define dsWindow %u\n",(int)(((char*)&(s->window))-((char*)s)));
printf("#define dsPrev %u\n",(int)(((char*)&(s->prev))-((char*)s)));
printf("#define dsMatchLen %u\n",(int)(((char*)&(s->match_length))-((char*)s)));
printf("#define dsPrevMatch %u\n",(int)(((char*)&(s->prev_match))-((char*)s)));
printf("#define dsStrStart %u\n",(int)(((char*)&(s->strstart))-((char*)s)));
printf("#define dsMatchStart %u\n",(int)(((char*)&(s->match_start))-((char*)s)));
printf("#define dsLookahead %u\n",(int)(((char*)&(s->lookahead))-((char*)s)));
printf("#define dsPrevLen %u\n",(int)(((char*)&(s->prev_length))-((char*)s)));
printf("#define dsMaxChainLen %u\n",(int)(((char*)&(s->max_chain_length))-((char*)s)));
printf("#define dsGoodMatch %u\n",(int)(((char*)&(s->good_match))-((char*)s)));
printf("#define dsNiceMatch %u\n",(int)(((char*)&(s->nice_match))-((char*)s)));
}
*/
#define dsWSize 68
#define dsWMask 76
#define dsWindow 80
#define dsPrev 96
#define dsMatchLen 144
#define dsPrevMatch 148
#define dsStrStart 156
#define dsMatchStart 160
#define dsLookahead 164
#define dsPrevLen 168
#define dsMaxChainLen 172
#define dsGoodMatch 188
#define dsNiceMatch 192
#define window_size [ rcx + dsWSize]
#define WMask [ rcx + dsWMask]
#define window_ad [ rcx + dsWindow]
#define prev_ad [ rcx + dsPrev]
#define strstart [ rcx + dsStrStart]
#define match_start [ rcx + dsMatchStart]
#define Lookahead [ rcx + dsLookahead] //; 0ffffffffh on infozip
#define prev_length [ rcx + dsPrevLen]
#define max_chain_length [ rcx + dsMaxChainLen]
#define good_match [ rcx + dsGoodMatch]
#define nice_match [ rcx + dsNiceMatch]
/*
; windows:
; parameter 1 in rcx(deflate state s), param 2 in rdx (cur match)
; see http://weblogs.asp.net/oldnewthing/archive/2004/01/14/58579.aspx and
; http://msdn.microsoft.com/library/en-us/kmarch/hh/kmarch/64bitAMD_8e951dd2-ee77-4728-8702-55ce4b5dd24a.xml.asp
;
; All registers must be preserved across the call, except for
; rax, rcx, rdx, r8, r9, r10, and r11, which are scratch.
;
; gcc on macosx-linux:
; see http://www.x86-64.org/documentation/abi-0.99.pdf
; param 1 in rdi, param 2 in rsi
; rbx, rsp, rbp, r12 to r15 must be preserved
;;; Save registers that the compiler may be using, and adjust esp to
;;; make room for our stack frame.
;;; Retrieve the function arguments. r8d will hold cur_match
;;; throughout the entire function. edx will hold the pointer to the
;;; deflate_state structure during the function's setup (before
;;; entering the main loop.
; ms: parameter 1 in rcx (deflate_state* s), param 2 in edx -> r8 (cur match)
; mac: param 1 in rdi, param 2 rsi
; this clear high 32 bits of r8, which can be garbage in both r8 and rdx
*/
mov [save_rbx],rbx
mov [save_rbp],rbp
mov rcx,rdi
mov r8d,esi
mov [save_r12],r12
mov [save_r13],r13
mov [save_r14],r14
mov [save_r15],r15
//;;; uInt wmask = s->w_mask;
//;;; unsigned chain_length = s->max_chain_length;
//;;; if (s->prev_length >= s->good_match) {
//;;; chain_length >>= 2;
//;;; }
mov edi, prev_length
mov esi, good_match
mov eax, WMask
mov ebx, max_chain_length
cmp edi, esi
jl LastMatchGood
shr ebx, 2
LastMatchGood:
//;;; chainlen is decremented once beforehand so that the function can
//;;; use the sign flag instead of the zero flag for the exit test.
//;;; It is then shifted into the high word, to make room for the wmask
//;;; value, which it will always accompany.
dec ebx
shl ebx, 16
or ebx, eax
//;;; on zlib only
//;;; if ((uInt)nice_match > s->lookahead) nice_match = s->lookahead;
mov eax, nice_match
mov [chainlenwmask], ebx
mov r10d, Lookahead
cmp r10d, eax
cmovnl r10d, eax
mov [nicematch],r10d
//;;; register Bytef *scan = s->window + s->strstart;
mov r10, window_ad
mov ebp, strstart
lea r13, [r10 + rbp]
//;;; Determine how many bytes the scan ptr is off from being
//;;; dword-aligned.
mov r9,r13
neg r13
and r13,3
//;;; IPos limit = s->strstart > (IPos)MAX_DIST(s) ?
//;;; s->strstart - (IPos)MAX_DIST(s) : NIL;
mov eax, window_size
sub eax, MIN_LOOKAHEAD
xor edi,edi
sub ebp, eax
mov r11d, prev_length
cmovng ebp,edi
//;;; int best_len = s->prev_length;
//;;; Store the sum of s->window + best_len in esi locally, and in esi.
lea rsi,[r10+r11]
//;;; register ush scan_start = *(ushf*)scan;
//;;; register ush scan_end = *(ushf*)(scan+best_len-1);
//;;; Posf *prev = s->prev;
movzx r12d,word ptr [r9]
movzx ebx, word ptr [r9 + r11 - 1]
mov rdi, prev_ad
//;;; Jump into the main loop.
mov edx, [chainlenwmask]
cmp bx,word ptr [rsi + r8 - 1]
jz LookupLoopIsZero
LookupLoop1:
and r8d, edx
movzx r8d, word ptr [rdi + r8*2]
cmp r8d, ebp
jbe LeaveNow
sub edx, 0x00010000
BEFORE_JMP
js LeaveNow
AFTER_JMP
LoopEntry1:
cmp bx,word ptr [rsi + r8 - 1]
BEFORE_JMP
jz LookupLoopIsZero
AFTER_JMP
LookupLoop2:
and r8d, edx
movzx r8d, word ptr [rdi + r8*2]
cmp r8d, ebp
BEFORE_JMP
jbe LeaveNow
AFTER_JMP
sub edx, 0x00010000
BEFORE_JMP
js LeaveNow
AFTER_JMP
LoopEntry2:
cmp bx,word ptr [rsi + r8 - 1]
BEFORE_JMP
jz LookupLoopIsZero
AFTER_JMP
LookupLoop4:
and r8d, edx
movzx r8d, word ptr [rdi + r8*2]
cmp r8d, ebp
BEFORE_JMP
jbe LeaveNow
AFTER_JMP
sub edx, 0x00010000
BEFORE_JMP
js LeaveNow
AFTER_JMP
LoopEntry4:
cmp bx,word ptr [rsi + r8 - 1]
BEFORE_JMP
jnz LookupLoop1
jmp LookupLoopIsZero
AFTER_JMP
/*
;;; do {
;;; match = s->window + cur_match;
;;; if (*(ushf*)(match+best_len-1) != scan_end ||
;;; *(ushf*)match != scan_start) continue;
;;; [...]
;;; } while ((cur_match = prev[cur_match & wmask]) > limit
;;; && --chain_length != 0);
;;;
;;; Here is the inner loop of the function. The function will spend the
;;; majority of its time in this loop, and majority of that time will
;;; be spent in the first ten instructions.
;;;
;;; Within this loop:
;;; ebx = scanend
;;; r8d = curmatch
;;; edx = chainlenwmask - i.e., ((chainlen << 16) | wmask)
;;; esi = windowbestlen - i.e., (window + bestlen)
;;; edi = prev
;;; ebp = limit
*/
.balign 16
LookupLoop:
and r8d, edx
movzx r8d, word ptr [rdi + r8*2]
cmp r8d, ebp
BEFORE_JMP
jbe LeaveNow
AFTER_JMP
sub edx, 0x00010000
BEFORE_JMP
js LeaveNow
AFTER_JMP
LoopEntry:
cmp bx,word ptr [rsi + r8 - 1]
BEFORE_JMP
jnz LookupLoop1
AFTER_JMP
LookupLoopIsZero:
cmp r12w, word ptr [r10 + r8]
BEFORE_JMP
jnz LookupLoop1
AFTER_JMP
//;;; Store the current value of chainlen.
mov [chainlenwmask], edx
/*
;;; Point edi to the string under scrutiny, and esi to the string we
;;; are hoping to match it up with. In actuality, esi and edi are
;;; both pointed (MAX_MATCH_8 - scanalign) bytes ahead, and edx is
;;; initialized to -(MAX_MATCH_8 - scanalign).
*/
lea rsi,[r8+r10]
mov rdx, 0xfffffffffffffef8 //; -(MAX_MATCH_8)
lea rsi, [rsi + r13 + 0x0108] //;MAX_MATCH_8]
lea rdi, [r9 + r13 + 0x0108] //;MAX_MATCH_8]
prefetcht1 [rsi+rdx]
prefetcht1 [rdi+rdx]
/*
;;; Test the strings for equality, 8 bytes at a time. At the end,
;;; adjust rdx so that it is offset to the exact byte that mismatched.
;;;
;;; We already know at this point that the first three bytes of the
;;; strings match each other, and they can be safely passed over before
;;; starting the compare loop. So what this code does is skip over 0-3
;;; bytes, as much as necessary in order to dword-align the edi
;;; pointer. (rsi will still be misaligned three times out of four.)
;;;
;;; It should be confessed that this loop usually does not represent
;;; much of the total running time. Replacing it with a more
;;; straightforward "rep cmpsb" would not drastically degrade
;;; performance.
*/
LoopCmps:
mov rax, [rsi + rdx]
xor rax, [rdi + rdx]
jnz LeaveLoopCmps
mov rax, [rsi + rdx + 8]
xor rax, [rdi + rdx + 8]
jnz LeaveLoopCmps8
mov rax, [rsi + rdx + 8+8]
xor rax, [rdi + rdx + 8+8]
jnz LeaveLoopCmps16
add rdx,8+8+8
BEFORE_JMP
jnz LoopCmps
jmp LenMaximum
AFTER_JMP
LeaveLoopCmps16: add rdx,8
LeaveLoopCmps8: add rdx,8
LeaveLoopCmps:
test eax, 0x0000FFFF
jnz LenLower
test eax,0xffffffff
jnz LenLower32
add rdx,4
shr rax,32
or ax,ax
BEFORE_JMP
jnz LenLower
AFTER_JMP
LenLower32:
shr eax,16
add rdx,2
LenLower:
sub al, 1
adc rdx, 0
//;;; Calculate the length of the match. If it is longer than MAX_MATCH,
//;;; then automatically accept it as the best possible match and leave.
lea rax, [rdi + rdx]
sub rax, r9
cmp eax, MAX_MATCH
BEFORE_JMP
jge LenMaximum
AFTER_JMP
/*
;;; If the length of the match is not longer than the best match we
;;; have so far, then forget it and return to the lookup loop.
;///////////////////////////////////
*/
cmp eax, r11d
jg LongerMatch
lea rsi,[r10+r11]
mov rdi, prev_ad
mov edx, [chainlenwmask]
BEFORE_JMP
jmp LookupLoop
AFTER_JMP
/*
;;; s->match_start = cur_match;
;;; best_len = len;
;;; if (len >= nice_match) break;
;;; scan_end = *(ushf*)(scan+best_len-1);
*/
LongerMatch:
mov r11d, eax
mov match_start, r8d
cmp eax, [nicematch]
BEFORE_JMP
jge LeaveNow
AFTER_JMP
lea rsi,[r10+rax]
movzx ebx, word ptr [r9 + rax - 1]
mov rdi, prev_ad
mov edx, [chainlenwmask]
BEFORE_JMP
jmp LookupLoop
AFTER_JMP
//;;; Accept the current string, with the maximum possible length.
LenMaximum:
mov r11d,MAX_MATCH
mov match_start, r8d
//;;; if ((uInt)best_len <= s->lookahead) return (uInt)best_len;
//;;; return s->lookahead;
LeaveNow:
mov eax, Lookahead
cmp r11d, eax
cmovng eax, r11d
//;;; Restore the stack and return from whence we came.
// mov rsi,[save_rsi]
// mov rdi,[save_rdi]
mov rbx,[save_rbx]
mov rbp,[save_rbp]
mov r12,[save_r12]
mov r13,[save_r13]
mov r14,[save_r14]
mov r15,[save_r15]
ret 0
//; please don't remove this string !
//; Your can freely use gvmat64 in any free or commercial app
//; but it is far better don't remove the string in the binary!
// db 0dh,0ah,"asm686 with masm, optimised assembly code from Brian Raiter, written 1998, converted to amd 64 by Gilles Vollant 2005",0dh,0ah,0
match_init:
ret 0
| {
"language": "Assembly"
} |
polygon
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1.440494E+01 4.945223E+01
1.440463E+01 4.945229E+01
1.440461E+01 4.945224E+01
1.440465E+01 4.945222E+01
1.440466E+01 4.945219E+01
1.440453E+01 4.945216E+01
1.440444E+01 4.945226E+01
1.440436E+01 4.945225E+01
1.440425E+01 4.945228E+01
1.440412E+01 4.945240E+01
1.440402E+01 4.945243E+01
1.440400E+01 4.945247E+01
1.440406E+01 4.945251E+01
1.440409E+01 4.945258E+01
1.440403E+01 4.945257E+01
1.440399E+01 4.945262E+01
1.440402E+01 4.945266E+01
1.440395E+01 4.945273E+01
1.440329E+01 4.945317E+01
1.440301E+01 4.945335E+01
1.440298E+01 4.945341E+01
1.440300E+01 4.945347E+01
1.440292E+01 4.945349E+01
1.440286E+01 4.945369E+01
1.440270E+01 4.945451E+01
1.440252E+01 4.945513E+01
1.440232E+01 4.945509E+01
1.440227E+01 4.945509E+01
1.440226E+01 4.945513E+01
1.440231E+01 4.945518E+01
1.440232E+01 4.945526E+01
1.440229E+01 4.945530E+01
1.440233E+01 4.945542E+01
1.440228E+01 4.945556E+01
1.440173E+01 4.945596E+01
1.440119E+01 4.945611E+01
1.440044E+01 4.945640E+01
1.439979E+01 4.945658E+01
1.439859E+01 4.945668E+01
1.439852E+01 4.945669E+01
1.439804E+01 4.945678E+01
1.439760E+01 4.945682E+01
1.439734E+01 4.945684E+01
1.439660E+01 4.945697E+01
1.439593E+01 4.945708E+01
1.439531E+01 4.945720E+01
1.439475E+01 4.945729E+01
1.439369E+01 4.945753E+01
1.439348E+01 4.945757E+01
1.439278E+01 4.945768E+01
1.439162E+01 4.945792E+01
1.439144E+01 4.945802E+01
1.439076E+01 4.945837E+01
1.439040E+01 4.945847E+01
1.439037E+01 4.945899E+01
1.439032E+01 4.945990E+01
1.438957E+01 4.945972E+01
1.438935E+01 4.945965E+01
1.438835E+01 4.945937E+01
1.438796E+01 4.945924E+01
1.438745E+01 4.945863E+01
1.438733E+01 4.945853E+01
1.438710E+01 4.945842E+01
1.438662E+01 4.945828E+01
1.438576E+01 4.945800E+01
1.438532E+01 4.945789E+01
1.438518E+01 4.945783E+01
1.438458E+01 4.945704E+01
1.438452E+01 4.945692E+01
1.438436E+01 4.945653E+01
1.438430E+01 4.945654E+01
1.438410E+01 4.945624E+01
1.438380E+01 4.945560E+01
1.438376E+01 4.945550E+01
1.438353E+01 4.945541E+01
1.438345E+01 4.945523E+01
1.438346E+01 4.945523E+01
1.438344E+01 4.945518E+01
1.438343E+01 4.945518E+01
1.438336E+01 4.945501E+01
1.438336E+01 4.945501E+01
1.438334E+01 4.945495E+01
1.438334E+01 4.945495E+01
1.438328E+01 4.945483E+01
1.438318E+01 4.945453E+01
1.438318E+01 4.945446E+01
1.438222E+01 4.945442E+01
1.438158E+01 4.945439E+01
1.438079E+01 4.945422E+01
1.438043E+01 4.945389E+01
1.438047E+01 4.945359E+01
1.438052E+01 4.945336E+01
1.438021E+01 4.945287E+01
1.438011E+01 4.945267E+01
1.437972E+01 4.945235E+01
1.437913E+01 4.945187E+01
1.437856E+01 4.945090E+01
1.437875E+01 4.945080E+01
1.437878E+01 4.945078E+01
1.437903E+01 4.945057E+01
1.437911E+01 4.945050E+01
1.437919E+01 4.945046E+01
1.437929E+01 4.945033E+01
1.437948E+01 4.945011E+01
1.437975E+01 4.944987E+01
1.438233E+01 4.944822E+01
1.438274E+01 4.944795E+01
1.438266E+01 4.944788E+01
1.438198E+01 4.944725E+01
1.438134E+01 4.944667E+01
1.438119E+01 4.944646E+01
1.438256E+01 4.944607E+01
1.438313E+01 4.944578E+01
1.438390E+01 4.944538E+01
1.438452E+01 4.944478E+01
1.438583E+01 4.944381E+01
1.438663E+01 4.944323E+01
1.438685E+01 4.944303E+01
1.438715E+01 4.944280E+01
1.438752E+01 4.944247E+01
1.438778E+01 4.944223E+01
1.438820E+01 4.944190E+01
1.438872E+01 4.944145E+01
1.438873E+01 4.944144E+01
1.438896E+01 4.944122E+01
1.438923E+01 4.944098E+01
1.438997E+01 4.944040E+01
1.439031E+01 4.944001E+01
1.439049E+01 4.943984E+01
1.439079E+01 4.943966E+01
1.439186E+01 4.943902E+01
1.439190E+01 4.943894E+01
1.439113E+01 4.943879E+01
1.439113E+01 4.943856E+01
1.439119E+01 4.943833E+01
1.439128E+01 4.943804E+01
1.439141E+01 4.943741E+01
1.439153E+01 4.943652E+01
1.439174E+01 4.943592E+01
1.439217E+01 4.943485E+01
1.439225E+01 4.943471E+01
1.439231E+01 4.943427E+01
1.439221E+01 4.943433E+01
1.439204E+01 4.943442E+01
1.439196E+01 4.943446E+01
1.439146E+01 4.943467E+01
1.439113E+01 4.943477E+01
1.439056E+01 4.943496E+01
1.439034E+01 4.943506E+01
1.438986E+01 4.943529E+01
1.438925E+01 4.943546E+01
1.438840E+01 4.943550E+01
1.438720E+01 4.943555E+01
1.438690E+01 4.943558E+01
1.438693E+01 4.943548E+01
1.438731E+01 4.943530E+01
1.438743E+01 4.943524E+01
1.438758E+01 4.943509E+01
1.438756E+01 4.943502E+01
1.438737E+01 4.943500E+01
1.438712E+01 4.943505E+01
1.438649E+01 4.943510E+01
1.438628E+01 4.943507E+01
1.438514E+01 4.943501E+01
1.438478E+01 4.943506E+01
1.438447E+01 4.943505E+01
1.438406E+01 4.943510E+01
1.438384E+01 4.943505E+01
1.438368E+01 4.943505E+01
1.438350E+01 4.943501E+01
1.438321E+01 4.943504E+01
1.438291E+01 4.943504E+01
1.438269E+01 4.943499E+01
1.438249E+01 4.943498E+01
1.438212E+01 4.943501E+01
1.438183E+01 4.943507E+01
1.438143E+01 4.943503E+01
1.438112E+01 4.943497E+01
1.437958E+01 4.943489E+01
1.437908E+01 4.943490E+01
1.437736E+01 4.943502E+01
1.437661E+01 4.943508E+01
1.437625E+01 4.943512E+01
1.437623E+01 4.943514E+01
1.437615E+01 4.943514E+01
1.437589E+01 4.943513E+01
1.437519E+01 4.943516E+01
1.437468E+01 4.943515E+01
1.437413E+01 4.943515E+01
1.437363E+01 4.943515E+01
1.437353E+01 4.943503E+01
1.437344E+01 4.943485E+01
1.437336E+01 4.943459E+01
1.437325E+01 4.943425E+01
1.437331E+01 4.943415E+01
1.437320E+01 4.943412E+01
1.437280E+01 4.943417E+01
1.437208E+01 4.943426E+01
1.437181E+01 4.943428E+01
1.437148E+01 4.943424E+01
1.437082E+01 4.943404E+01
1.437017E+01 4.943387E+01
1.436980E+01 4.943372E+01
1.436941E+01 4.943384E+01
1.436903E+01 4.943395E+01
1.436811E+01 4.943390E+01
1.436774E+01 4.943381E+01
1.436759E+01 4.943334E+01
1.436753E+01 4.943327E+01
1.436634E+01 4.943260E+01
1.436643E+01 4.943228E+01
1.436639E+01 4.943224E+01
1.436672E+01 4.943174E+01
1.436659E+01 4.943171E+01
1.436587E+01 4.943135E+01
1.436644E+01 4.943043E+01
1.436602E+01 4.943023E+01
1.436582E+01 4.943017E+01
1.436552E+01 4.943003E+01
1.436536E+01 4.942997E+01
1.436524E+01 4.942995E+01
1.436449E+01 4.942973E+01
1.436443E+01 4.942971E+01
1.436443E+01 4.942955E+01
1.436441E+01 4.942949E+01
1.436414E+01 4.942937E+01
1.436395E+01 4.942910E+01
1.436358E+01 4.942872E+01
1.436320E+01 4.942851E+01
1.436299E+01 4.942831E+01
1.436307E+01 4.942827E+01
1.436330E+01 4.942803E+01
1.436299E+01 4.942774E+01
1.436274E+01 4.942756E+01
1.436200E+01 4.942657E+01
1.436181E+01 4.942635E+01
1.436176E+01 4.942630E+01
1.436147E+01 4.942630E+01
1.435956E+01 4.942630E+01
1.435931E+01 4.942630E+01
END
END
| {
"language": "Assembly"
} |
/*
* Copyright (C) 2010-2011 Red Hat, Inc.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library. If not, see
* <http://www.gnu.org/licenses/>.
*
*/
#pragma once
#include "security_driver.h"
extern virSecurityDriver virSecurityDriverNop;
| {
"language": "Assembly"
} |
//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
// Autogenerated by gen-libclc-test.py
// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s
#include <spirv/spirv_types.h>
// CHECK-NOT: declare {{.*}} @_Z
// CHECK-NOT: call {{[^ ]*}} bitcast
__attribute__((overloadable)) __clc_vec2_uint32_t
test___spirv_ConvertFToU_Ruint2_sat_rtp(__clc_vec2_fp32_t args_0) {
return __spirv_ConvertFToU_Ruint2_sat_rtp(args_0);
}
#ifdef cl_khr_fp64
__attribute__((overloadable)) __clc_vec2_uint32_t
test___spirv_ConvertFToU_Ruint2_sat_rtp(__clc_vec2_fp64_t args_0) {
return __spirv_ConvertFToU_Ruint2_sat_rtp(args_0);
}
#endif
#ifdef cl_khr_fp16
__attribute__((overloadable)) __clc_vec2_uint32_t
test___spirv_ConvertFToU_Ruint2_sat_rtp(__clc_vec2_fp16_t args_0) {
return __spirv_ConvertFToU_Ruint2_sat_rtp(args_0);
}
#endif
| {
"language": "Assembly"
} |
#pragma once
#ifndef CRC32_H
#define CRC32_H
static unsigned int crc32_tab[] = {
0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
};
class crc32
{
public:
static const unsigned int getCrc32(unsigned int crc, const void *buf, int size) {
const unsigned char *p;
p = (unsigned char *)buf;
crc = crc ^ ~0U;
while (size--) {
crc = crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8);
}
return crc ^ ~0U;
}
};
#endif | {
"language": "Assembly"
} |
; RUN: llvm-as < %s > %t
; RUN: llvm-nm %t | FileCheck %s
; RUN: verify-uselistorder %s
; Test for isBitcodeFile, llvm-nm must read from a file for this test.
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin9.2.2"
; CHECK: foo
define i32 @foo() {
ret i32 0
}
| {
"language": "Assembly"
} |
vs.1.1
# DYNAMIC: "DOWATERFOG" "0..1"
#include "macros.vsh"
local( $worldPos, $worldNormal, $projPos, $reflectionVector );
&AllocateRegister( \$projPos );
dp4 $projPos.x, $vPos, $cModelViewProj0
dp4 $projPos.y, $vPos, $cModelViewProj1
dp4 $projPos.z, $vPos, $cModelViewProj2
dp4 $projPos.w, $vPos, $cModelViewProj3
mov oPos, $projPos
&AllocateRegister( \$worldPos );
; garymcthack
dp4 $worldPos.z, $vPos, $cModel2
&CalcFog( $worldPos, $projPos );
&FreeRegister( \$worldPos );
&FreeRegister( \$projPos );
;------------------------------------------------------------------------------
; Texture coordinates
;------------------------------------------------------------------------------
; base texcoords
dp4 oT0.x, $vTexCoord0, $SHADER_SPECIFIC_CONST_0
dp4 oT0.y, $vTexCoord0, $SHADER_SPECIFIC_CONST_1
dp4 oT1.x, $vTexCoord0, $SHADER_SPECIFIC_CONST_2
dp4 oT1.y, $vTexCoord0, $SHADER_SPECIFIC_CONST_3
; lightmap texcoords
mov oT2, $vTexCoord1
; detail
dp4 oT3.x, $vTexCoord0, $SHADER_SPECIFIC_CONST_4
dp4 oT3.y, $vTexCoord0, $SHADER_SPECIFIC_CONST_5
; Now the basetexture/basetexture2 blend uses vertex color, so send it into the psh.
mov oD0, $vColor
&FreeRegister( \$worldPos ); # garymcthack
| {
"language": "Assembly"
} |
/*
* sim-read.S -- read interface for FT32 simulator
*
* Copyright (C) 2015 FTDI (support@ftdichip.com)
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "syscall.h"
/*
* Input:
* $r0 -- File descriptor.
* $r1 -- Buffer to be read into.
* -0x12($fp) -- Length of the buffer.
*
* Output:
* $r0 -- Length read or -1.
* errno -- Set if an error
*/
.globl _read
.type _read,@function
.weak read
.text
_read:
read:
# swi SYS_read
return
.Lend:
.size _read,.Lend-_read
| {
"language": "Assembly"
} |
# Test object with an artifically constructed type unit header to verify
# that the length field is correctly used to verify the validity of the
# type_offset field.
#
# To generate the test object:
# llvm-mc -triple x86_64-unknown-linux typeunit-header.s -filetype=obj \
# -o typeunit-header.elf-x86-64
#
# We only have an abbreviation for the type unit die which is all we need.
# Real type unit dies have quite different attributes of course, but we
# just need to demonstrate an issue with validating length, so we just give it
# a single visibility attribute.
.section .debug_abbrev,"",@progbits
.byte 0x01 # Abbrev code
.byte 0x41 # DW_TAG_type_unit
.byte 0x01 # DW_CHILDREN_yes
.byte 0x17 # DW_AT_visibility
.byte 0x0b # DW_FORM_data1
.byte 0x00 # EOM(1)
.byte 0x00 # EOM(2)
.byte 0x02 # Abbrev code
.byte 0x13 # DW_TAG_structure_type
.byte 0x00 # DW_CHILDREN_no (no members)
.byte 0x17 # DW_AT_visibility
.byte 0x0b # DW_FORM_data1
.byte 0x00 # EOM(1)
.byte 0x00 # EOM(2)
.byte 0x00 # EOM(3)
.section .debug_types,"",@progbits
# DWARF v4 Type unit header - DWARF32 format.
TU_4_32_start:
.long TU_4_32_end-TU_4_32_version # Length of Unit
TU_4_32_version:
.short 4 # DWARF version number
.long .debug_abbrev # Offset Into Abbrev. Section
.byte 8 # Address Size (in bytes)
.quad 0x0011223344556677 # Type Signature
.long TU_4_32_type-TU_4_32_start # Type offset
# The type-unit DIE, which has just a visibility attribute.
.byte 1 # Abbreviation code
.byte 1 # DW_VIS_local
# The type DIE, which also just has a one-byte visibility attribute.
TU_4_32_type:
.byte 2 # Abbreviation code
.byte 1 # DW_VIS_local
.byte 0 # NULL
.byte 0 # NULL
TU_4_32_end:
| {
"language": "Assembly"
} |