content
stringlengths 0
376M
|
|---|
#***********************************************************************
# Copyright 2022 Massachusets Institute of Technology
# SPDX short identifier: BSD-2-Clause
#
# File Name: CMakeLists.txt
# Program: Common Evaluation Platform (CEP)
# Description: CMake file
# Notes:
#************************************************************************
cmake_minimum_required(VERSION 3.8)
project(helloworld C)
set(CMAKE_C_STANDARD 11)
add_executable(helloworld helloworld.c)
target_include_directories(helloworld PRIVATE)
target_link_libraries(helloworld PRIVATE)
set(CMAKE_INSTALL_PREFIX "/usr" CACHE PATH "Standard install prefix" FORCE)
install(TARGETS helloworld RUNTIME DESTINATION bin) |
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// assumes input does not change between start going high and out_valid
module aes_128(clk, start, state, key, out, out_valid);
input clk;
input start;
input [127:0] state, key;
output [127:0] out;
output out_valid;
reg [127:0] s0, k0;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9,
k1, k2, k3, k4, k5, k6, k7, k8, k9,
k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b;
reg start_r;
always @(posedge clk)
begin
start_r <= start;
end
wire start_posedge = start & ~start_r;
reg [4:0] validCounter;
always @ (posedge clk)
begin
if(start_posedge)
begin
s0 <= state ^ key;
k0 <= key;
validCounter <= 21;
end
else if(~out_valid)
begin
validCounter <= validCounter - 1;
end
end
assign out_valid = (validCounter == 0);
expand_key_128
a1 (clk, k0, k1, k0b, 8'h1),
a2 (clk, k1, k2, k1b, 8'h2),
a3 (clk, k2, k3, k2b, 8'h4),
a4 (clk, k3, k4, k3b, 8'h8),
a5 (clk, k4, k5, k4b, 8'h10),
a6 (clk, k5, k6, k5b, 8'h20),
a7 (clk, k6, k7, k6b, 8'h40),
a8 (clk, k7, k8, k7b, 8'h80),
a9 (clk, k8, k9, k8b, 8'h1b),
a10 (clk, k9, , k9b, 8'h36);
one_round
r1 (clk, s0, k0b, s1),
r2 (clk, s1, k1b, s2),
r3 (clk, s2, k2b, s3),
r4 (clk, s3, k3b, s4),
r5 (clk, s4, k4b, s5),
r6 (clk, s5, k5b, s6),
r7 (clk, s6, k6b, s7),
r8 (clk, s7, k7b, s8),
r9 (clk, s8, k8b, s9);
final_round
rf (clk, s9, k9b, out);
endmodule
module expand_key_128(clk, in, out_1, out_2, rcon);
input clk;
input [127:0] in;
input [7:0] rcon;
output reg [127:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3,
v0, v1, v2, v3;
reg [31:0] k0a, k1a, k2a, k3a;
wire [31:0] k0b, k1b, k2b, k3b, k4a;
assign {k0, k1, k2, k3} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
assign v2 = v1 ^ k2;
assign v3 = v2 ^ k3;
always @ (posedge clk)
{k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};
S4
S4_0 (clk, {k3[23:0], k3[31:24]}, k4a);
assign k0b = k0a ^ k4a;
assign k1b = k1a ^ k4a;
assign k2b = k2a ^ k4a;
assign k3b = k3a ^ k4a;
always @ (posedge clk)
out_1 <= {k0b, k1b, k2b, k3b};
assign out_2 = {k0b, k1b, k2b, k3b};
endmodule
|
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// This is a fully unrolled implementation
module aes_192 (clk, rst, start, state, key, out, out_valid);
input clk;
input rst;
input start;
input [127:0] state;
input [191:0] key;
output [127:0] out;
output out_valid;
// Internals signals and such
reg [127:0] s0;
reg [191:0] k0;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
wire [191:0] k1, k2, k3, k4, k5, k6, k7, k8, k9, k10, k11;
wire [127:0] k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b, k10b, k11b;
reg start_r;
wire start_posedge = start & ~start_r;
reg [4:0] validCounter;
always @(posedge clk or posedge rst)
begin
if (rst)
start_r <= 1'b0;
else
start_r <= start;
end // end always
always @ (posedge clk or posedge rst)
begin
if (rst) begin
s0 <= 0;
k0 <= 0;
validCounter <= 0;
end else
if(start_posedge)
begin
s0 <= state ^ key[191:64];
k0 <= key;
validCounter <= 26;
end
else if(validCounter > 1)
begin
validCounter <= validCounter - 1;
end
end // end always
assign out_valid = (validCounter == 1);
expand_key_type_D_192 a0 (clk, rst, k0, 8'h1, k1, k0b);
expand_key_type_B_192 a1 (clk, rst, k1, k2, k1b);
expand_key_type_A_192 a2 (clk, rst, k2, 8'h2, k3, k2b);
expand_key_type_C_192 a3 (clk, rst, k3, 8'h4, k4, k3b);
expand_key_type_B_192 a4 (clk, rst, k4, k5, k4b);
expand_key_type_A_192 a5 (clk, rst, k5, 8'h8, k6, k5b);
expand_key_type_C_192 a6 (clk, rst, k6, 8'h10, k7, k6b);
expand_key_type_B_192 a7 (clk, rst, k7, k8, k7b);
expand_key_type_A_192 a8 (clk, rst, k8, 8'h20, k9, k8b);
expand_key_type_C_192 a9 (clk, rst, k9, 8'h40, k10, k9b);
expand_key_type_B_192 a10 (clk, rst, k10, k11, k10b);
expand_key_type_A_192 a11 (clk, rst, k11, 8'h80, , k11b);
one_round
r1 (clk, rst, s0, k0b, s1),
r2 (clk, rst, s1, k1b, s2),
r3 (clk, rst, s2, k2b, s3),
r4 (clk, rst, s3, k3b, s4),
r5 (clk, rst, s4, k4b, s5),
r6 (clk, rst, s5, k5b, s6),
r7 (clk, rst, s6, k6b, s7),
r8 (clk, rst, s7, k7b, s8),
r9 (clk, rst, s8, k8b, s9),
r10 (clk, rst, s9, k9b, s10),
r11 (clk, rst, s10, k10b, s11);
final_round
rf (clk, rst, s11, k11b, out);
endmodule
/* expand k0,k1,k2,k3 for every two clock cycles */
module expand_key_type_A_192 (clk, rst, in, rcon, out_1, out_2);
input clk;
input rst;
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output [127:0] out_2;
// Internal signals
wire [31:0] k0, k1, k2, k3, k4, k5, v0, v1, v2, v3;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
assign v2 = v1 ^ k2;
assign v3 = v2 ^ k3;
always @ (posedge clk or posedge rst)
begin
if (rst)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {32'd0, 32'd0, 32'd0, 32'd0, 32'd0, 32'd0};
else
{k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, v2, v3, k4, k5};
end // end always
S4 S4_0 (clk, rst, {k5[23:0], k5[31:24]}, k6a);
assign k0b = k0a ^ k6a;
assign k1b = k1a ^ k6a;
assign k2b = k2a ^ k6a;
assign k3b = k3a ^ k6a;
assign {k4b, k5b} = {k4a, k5a};
always @ (posedge clk or posedge rst)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
end // end always
assign out_2 = {k0b, k1b, k2b, k3b};
endmodule // end module expand_key_type_A_192
/* expand k2,k3,k4,k5 for every two clock cycles */
module expand_key_type_B_192 (clk, rst, in, out_1, out_2);
input clk;
input rst;
input [191:0] in;
output reg [191:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5, v2, v3, v4, v5;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v2 = k1 ^ k2;
assign v3 = v2 ^ k3;
assign v4 = v3 ^ k4;
assign v5 = v4 ^ k5;
always @ (posedge clk or posedge rst)
begin
if (rst)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {32'd0, 32'd0, 32'd0, 32'd0, 32'd0, 32'd0};
else
{k0a, k1a, k2a, k3a, k4a, k5a} <= {k0, k1, v2, v3, v4, v5};
end // end always
always @ (posedge clk or posedge rst)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0a, k1a, k2a, k3a, k4a, k5a};
end
assign out_2 = {k2a, k3a, k4a, k5a};
endmodule // end expand_key_type_B_192
/* expand k0,k1,k4,k5 for every two clock cycles */
module expand_key_type_C_192 (clk, rst, in, rcon, out_1, out_2);
input clk;
input rst;
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5, v4, v5, v0, v1;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v4 = k3 ^ k4;
assign v5 = v4 ^ k5;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
always @ (posedge clk or posedge rst)
begin
if (rst)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {32'd0, 32'd0, 32'd0, 32'd0, 32'd0, 32'd0};
else
{k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, k2, k3, v4, v5};
end
S4 S4_0 (clk, rst, {v5[23:0], v5[31:24]}, k6a);
assign k0b = k0a ^ k6a;
assign k1b = k1a ^ k6a;
assign {k2b, k3b, k4b, k5b} = {k2a, k3a, k4a, k5a};
always @ (posedge clk or posedge rst)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
end
assign out_2 = {k4b, k5b, k0b, k1b};
endmodule // end expand_key_type_C_192
/* expand k0,k1 for every two clock cycles */
module expand_key_type_D_192 (clk, rst, in, rcon, out_1, out_2);
input clk;
input rst;
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5, v0, v1;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
always @ (posedge clk or posedge rst)
begin
if (rst)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {32'd0, 32'd0, 32'd0, 32'd0, 32'd0, 32'd0};
else
{k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, k2, k3, k4, k5};
end // end always
S4 S4_0 (clk, rst, {k5[23:0], k5[31:24]}, k6a);
assign k0b = k0a ^ k6a;
assign k1b = k1a ^ k6a;
assign {k2b, k3b, k4b, k5b} = {k2a, k3a, k4a, k5a};
always @ (posedge clk or posedge rst)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
end // end always
assign out_2 = {k4b, k5b, k0b, k1b};
endmodule // end expand_key_type_D_192
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : aes_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-AES core
//
module aes_top_192(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
// As of now, no errors are generated
assign wb_err_o = 1'b0;
// Interrupt is unused
assign int_o = 1'b0;
// Internal registers
reg start, start_r;
reg [31:0] pt [0:3];
reg [31:0] key [0:5];
reg wb_stb_i_r;
wire [127:0] pt_big = {pt[0], pt[1], pt[2], pt[3]};
wire [191:0] key_big = {key[0], key[1], key[2], key[3], key[4], key[5]};
wire [127:0] ct;
wire ct_valid;
// Generate the acknowledgement signal
assign wb_ack_o = wb_stb_i_r && wb_stb_i;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i or negedge wb_rst_i)
begin
if(wb_rst_i)
begin
start <= 0;
start_r <= 0;
pt[0] <= 0;
pt[1] <= 0;
pt[2] <= 0;
pt[3] <= 0;
key[0] <= 0;
key[1] <= 0;
key[2] <= 0;
key[3] <= 0;
key[4] <= 0;
key[5] <= 0;
wb_stb_i_r <= 1'b0;
end
else begin
// Generate registered version of start (for edge detection)
start_r <= start;
// Generate a registered version of the write strobe
wb_stb_i_r <= wb_stb_i;
// Perform a write
if(wb_stb_i & wb_we_i) begin
case(wb_adr_i[5:2])
0: start <= wb_dat_i[0];
1: pt[3] <= wb_dat_i;
2: pt[2] <= wb_dat_i;
3: pt[1] <= wb_dat_i;
4: pt[0] <= wb_dat_i;
5: key[5] <= wb_dat_i;
6: key[4] <= wb_dat_i;
7: key[3] <= wb_dat_i;
8: key[2] <= wb_dat_i;
9: key[1] <= wb_dat_i;
10: key[0] <= wb_dat_i;
default:
;
endcase
end else begin // end if wb_stb_i & wb_we_i
start <= 1'b0;
end
end // end else begin
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[5:2])
1:
wb_dat_o = pt[3];
2:
wb_dat_o = pt[2];
3:
wb_dat_o = pt[1];
4:
wb_dat_o = pt[0];
5:
wb_dat_o = key[5];
6:
wb_dat_o = key[4];
7:
wb_dat_o = key[3];
8:
wb_dat_o = key[2];
9:
wb_dat_o = key[1];
10:
wb_dat_o = key[0];
11:
wb_dat_o = {31'b0, ct_valid};
12:
wb_dat_o = ct[127:96];
13:
wb_dat_o = ct[95:64];
14:
wb_dat_o = ct[63:32];
15:
wb_dat_o = ct[31:0];
default:
wb_dat_o = 32'b0;
endcase
end // always @ (*)
aes_192 aes(
.clk(wb_clk_i),
.rst(wb_rst_i),
.state(pt_big),
.key(key_big),
.start(start && ~start_r), // start on detected position edge
.out(ct),
.out_valid(ct_valid)
);
endmodule
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : aes_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-AES core
//
module aes_top_128(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
// As of now, no errors are generated
assign wb_err_o = 1'b0;
// Interrupt is unused
assign int_o = 1'b0;
// Internal registers
reg start, start_r;
reg [31:0] pt [0:3];
reg [31:0] key [0:5];
reg wb_stb_i_r;
wire [127:0] pt_big = {pt[0], pt[1], pt[2], pt[3]};
wire [191:0] key_big = {key[0], key[1], key[2], key[3], key[4], key[5]};
wire [127:0] ct;
wire ct_valid;
// Generate the acknowledgement signal
assign wb_ack_o = wb_stb_i_r && wb_stb_i;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i or negedge wb_rst_i)
begin
if(wb_rst_i)
begin
start <= 0;
start_r <= 0;
pt[0] <= 0;
pt[1] <= 0;
pt[2] <= 0;
pt[3] <= 0;
key[0] <= 0;
key[1] <= 0;
key[2] <= 0;
key[3] <= 0;
key[4] <= 0;
key[5] <= 0;
wb_stb_i_r <= 1'b0;
end
else begin
// Generate registered version of start (for edge detection)
start_r <= start;
// Generate a registered version of the write strobe
wb_stb_i_r <= wb_stb_i;
// Perform a write
if(wb_stb_i & wb_we_i) begin
case(wb_adr_i[5:2])
0: start <= wb_dat_i[0];
1: pt[3] <= wb_dat_i;
2: pt[2] <= wb_dat_i;
3: pt[1] <= wb_dat_i;
4: pt[0] <= wb_dat_i;
5: key[5] <= wb_dat_i;
6: key[4] <= wb_dat_i;
7: key[3] <= wb_dat_i;
8: key[2] <= wb_dat_i;
9: key[1] <= wb_dat_i;
10: key[0] <= wb_dat_i;
default:
;
endcase
end else begin // end if wb_stb_i & wb_we_i
start <= 1'b0;
end
end // end else begin
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[5:2])
1:
wb_dat_o = pt[3];
2:
wb_dat_o = pt[2];
3:
wb_dat_o = pt[1];
4:
wb_dat_o = pt[0];
5:
wb_dat_o = key[5];
6:
wb_dat_o = key[4];
7:
wb_dat_o = key[3];
8:
wb_dat_o = key[2];
9:
wb_dat_o = key[1];
10:
wb_dat_o = key[0];
11:
wb_dat_o = {31'b0, ct_valid};
12:
wb_dat_o = ct[127:96];
13:
wb_dat_o = ct[95:64];
14:
wb_dat_o = ct[63:32];
15:
wb_dat_o = ct[31:0];
default:
wb_dat_o = 32'b0;
endcase
end // always @ (*)
aes_128 aes(
.clk(wb_clk_i),
//.rst(1'b0),
.state(pt_big),
.key(key_big),
.start(start && wb_rst_i), // start on detected position edge
.out(ct),
.out_valid(ct_valid)
);
endmodule
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : aes_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-AES core
//
module aes_top_192(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
// As of now, no errors are generated
assign wb_err_o = 1'b0;
// Interrupt is unused
assign int_o = 1'b0;
// Internal registers
reg start, start_r;
reg [31:0] pt [0:3];
reg [31:0] key [0:5];
reg wb_stb_i_r;
wire [127:0] pt_big = {pt[0], pt[1], pt[2], pt[3]};
wire [191:0] key_big = {key[0], key[1], key[2], key[3], key[4], key[5]};
wire [127:0] ct;
wire ct_valid;
// Generate the acknowledgement signal
assign wb_ack_o = wb_stb_i_r && wb_stb_i;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i or negedge wb_rst_i)
begin
if(wb_rst_i)
begin
start <= 0;
start_r <= 0;
pt[0] <= 0;
pt[1] <= 0;
pt[2] <= 0;
pt[3] <= 0;
key[0] <= 0;
key[1] <= 0;
key[2] <= 0;
key[3] <= 0;
key[4] <= 0;
key[5] <= 0;
wb_stb_i_r <= 1'b0;
end
else begin
// Generate registered version of start (for edge detection)
start_r <= start;
// Generate a registered version of the write strobe
wb_stb_i_r <= wb_stb_i;
// Perform a write
if(wb_stb_i & wb_we_i) begin
case(wb_adr_i[5:2])
0: start <= wb_dat_i[0];
1: pt[3] <= wb_dat_i;
2: pt[2] <= wb_dat_i;
3: pt[1] <= wb_dat_i;
4: pt[0] <= wb_dat_i;
5: key[5] <= wb_dat_i;
6: key[4] <= wb_dat_i;
7: key[3] <= wb_dat_i;
8: key[2] <= wb_dat_i;
9: key[1] <= wb_dat_i;
10: key[0] <= wb_dat_i;
default:
;
endcase
end else begin // end if wb_stb_i & wb_we_i
start <= 1'b0;
end
end // end else begin
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[5:2])
1:
wb_dat_o = pt[3];
2:
wb_dat_o = pt[2];
3:
wb_dat_o = pt[1];
4:
wb_dat_o = pt[0];
5:
wb_dat_o = key[5];
6:
wb_dat_o = key[4];
7:
wb_dat_o = key[3];
8:
wb_dat_o = key[2];
9:
wb_dat_o = key[1];
10:
wb_dat_o = key[0];
11:
wb_dat_o = {31'b0, ct_valid};
12:
wb_dat_o = ct[127:96];
13:
wb_dat_o = ct[95:64];
14:
wb_dat_o = ct[63:32];
15:
wb_dat_o = ct[31:0];
default:
wb_dat_o = 32'b0;
endcase
end // always @ (*)
aes_192 aes(
.clk(wb_clk_i),
.rst(wb_rst_i),
.state(pt_big),
.key(key_big),
.start(start && ~start_r), // start on detected position edge
.out(ct),
.out_valid(ct_valid)
);
endmodule
|
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* verilator lint_off UNOPTFLAT */
/* one AES round for every two clock cycles */
module one_round (clk, rst, state_in, key, state_out);
input clk;
input rst;
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33,
k0, k1, k2, k3;
assign {k0, k1, k2, k3} = key;
assign {s0, s1, s2, s3} = state_in;
table_lookup
t0 (clk, rst, s0, p00, p01, p02, p03),
t1 (clk, rst, s1, p10, p11, p12, p13),
t2 (clk, rst, s2, p20, p21, p22, p23),
t3 (clk, rst, s3, p30, p31, p32, p33);
assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0;
assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1;
assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2;
assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3;
always @ (posedge clk)
state_out <= {z0, z1, z2, z3};
endmodule
/* AES final round for every two clock cycles */
module final_round (clk, rst, state_in, key_in, state_out);
input clk;
input rst;
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33;
assign {k0, k1, k2, k3} = key_in;
assign {s0, s1, s2, s3} = state_in;
S4
S4_1 (clk, rst, s0, {p00, p01, p02, p03}),
S4_2 (clk, rst, s1, {p10, p11, p12, p13}),
S4_3 (clk, rst, s2, {p20, p21, p22, p23}),
S4_4 (clk, rst, s3, {p30, p31, p32, p33});
assign z0 = {p00, p11, p22, p33} ^ k0;
assign z1 = {p10, p21, p32, p03} ^ k1;
assign z2 = {p20, p31, p02, p13} ^ k2;
assign z3 = {p30, p01, p12, p23} ^ k3;
always @ (posedge clk or posedge rst)
if (rst)
state_out <= 0;
else
state_out <= {z0, z1, z2, z3};
endmodule
|
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* verilator lint_off UNOPTFLAT */
module table_lookup (clk, rst, state, p0, p1, p2, p3);
input clk;
input rst;
input [31:0] state;
output [31:0] p0, p1, p2, p3;
wire [7:0] b0, b1, b2, b3;
assign {b0, b1, b2, b3} = state;
T
t0 (clk, rst, b0, {p0[23:0], p0[31:24]}),
t1 (clk, rst, b1, {p1[15:0], p1[31:16]}),
t2 (clk, rst, b2, {p2[7:0], p2[31:8]} ),
t3 (clk, rst, b3, p3);
endmodule // end table_lookup
/* substitue four bytes in a word */
module S4 (clk, rst, in, out);
input clk;
input rst;
input [31:0] in;
output [31:0] out;
S
S_0 (clk, rst, in[31:24], out[31:24]),
S_1 (clk, rst, in[23:16], out[23:16]),
S_2 (clk, rst, in[15:8], out[15:8] ),
S_3 (clk, rst, in[7:0], out[7:0] );
endmodule // end S4
/* S_box, S_box, S_box*(x+1), S_box*x */
module T (clk, rst, in, out);
input clk;
input rst;
input [7:0] in;
output [31:0] out;
S
s0 (clk, rst, in, out[31:24]);
assign out[23:16] = out[31:24];
xS
s4 (clk, rst, in, out[7:0]);
assign out[15:8] = out[23:16] ^ out[7:0];
endmodule // end T
/* S box */
module S (clk, rst, in, out);
input clk;
input rst;
input [7:0] in;
output reg [7:0] out;
always @ (posedge clk or posedge rst)
if (rst)
out <= 8'd0;
else
case (in)
8'h00: out <= 8'h63;
8'h01: out <= 8'h7c;
8'h02: out <= 8'h77;
8'h03: out <= 8'h7b;
8'h04: out <= 8'hf2;
8'h05: out <= 8'h6b;
8'h06: out <= 8'h6f;
8'h07: out <= 8'hc5;
8'h08: out <= 8'h30;
8'h09: out <= 8'h01;
8'h0a: out <= 8'h67;
8'h0b: out <= 8'h2b;
8'h0c: out <= 8'hfe;
8'h0d: out <= 8'hd7;
8'h0e: out <= 8'hab;
8'h0f: out <= 8'h76;
8'h10: out <= 8'hca;
8'h11: out <= 8'h82;
8'h12: out <= 8'hc9;
8'h13: out <= 8'h7d;
8'h14: out <= 8'hfa;
8'h15: out <= 8'h59;
8'h16: out <= 8'h47;
8'h17: out <= 8'hf0;
8'h18: out <= 8'had;
8'h19: out <= 8'hd4;
8'h1a: out <= 8'ha2;
8'h1b: out <= 8'haf;
8'h1c: out <= 8'h9c;
8'h1d: out <= 8'ha4;
8'h1e: out <= 8'h72;
8'h1f: out <= 8'hc0;
8'h20: out <= 8'hb7;
8'h21: out <= 8'hfd;
8'h22: out <= 8'h93;
8'h23: out <= 8'h26;
8'h24: out <= 8'h36;
8'h25: out <= 8'h3f;
8'h26: out <= 8'hf7;
8'h27: out <= 8'hcc;
8'h28: out <= 8'h34;
8'h29: out <= 8'ha5;
8'h2a: out <= 8'he5;
8'h2b: out <= 8'hf1;
8'h2c: out <= 8'h71;
8'h2d: out <= 8'hd8;
8'h2e: out <= 8'h31;
8'h2f: out <= 8'h15;
8'h30: out <= 8'h04;
8'h31: out <= 8'hc7;
8'h32: out <= 8'h23;
8'h33: out <= 8'hc3;
8'h34: out <= 8'h18;
8'h35: out <= 8'h96;
8'h36: out <= 8'h05;
8'h37: out <= 8'h9a;
8'h38: out <= 8'h07;
8'h39: out <= 8'h12;
8'h3a: out <= 8'h80;
8'h3b: out <= 8'he2;
8'h3c: out <= 8'heb;
8'h3d: out <= 8'h27;
8'h3e: out <= 8'hb2;
8'h3f: out <= 8'h75;
8'h40: out <= 8'h09;
8'h41: out <= 8'h83;
8'h42: out <= 8'h2c;
8'h43: out <= 8'h1a;
8'h44: out <= 8'h1b;
8'h45: out <= 8'h6e;
8'h46: out <= 8'h5a;
8'h47: out <= 8'ha0;
8'h48: out <= 8'h52;
8'h49: out <= 8'h3b;
8'h4a: out <= 8'hd6;
8'h4b: out <= 8'hb3;
8'h4c: out <= 8'h29;
8'h4d: out <= 8'he3;
8'h4e: out <= 8'h2f;
8'h4f: out <= 8'h84;
8'h50: out <= 8'h53;
8'h51: out <= 8'hd1;
8'h52: out <= 8'h00;
8'h53: out <= 8'hed;
8'h54: out <= 8'h20;
8'h55: out <= 8'hfc;
8'h56: out <= 8'hb1;
8'h57: out <= 8'h5b;
8'h58: out <= 8'h6a;
8'h59: out <= 8'hcb;
8'h5a: out <= 8'hbe;
8'h5b: out <= 8'h39;
8'h5c: out <= 8'h4a;
8'h5d: out <= 8'h4c;
8'h5e: out <= 8'h58;
8'h5f: out <= 8'hcf;
8'h60: out <= 8'hd0;
8'h61: out <= 8'hef;
8'h62: out <= 8'haa;
8'h63: out <= 8'hfb;
8'h64: out <= 8'h43;
8'h65: out <= 8'h4d;
8'h66: out <= 8'h33;
8'h67: out <= 8'h85;
8'h68: out <= 8'h45;
8'h69: out <= 8'hf9;
8'h6a: out <= 8'h02;
8'h6b: out <= 8'h7f;
8'h6c: out <= 8'h50;
8'h6d: out <= 8'h3c;
8'h6e: out <= 8'h9f;
8'h6f: out <= 8'ha8;
8'h70: out <= 8'h51;
8'h71: out <= 8'ha3;
8'h72: out <= 8'h40;
8'h73: out <= 8'h8f;
8'h74: out <= 8'h92;
8'h75: out <= 8'h9d;
8'h76: out <= 8'h38;
8'h77: out <= 8'hf5;
8'h78: out <= 8'hbc;
8'h79: out <= 8'hb6;
8'h7a: out <= 8'hda;
8'h7b: out <= 8'h21;
8'h7c: out <= 8'h10;
8'h7d: out <= 8'hff;
8'h7e: out <= 8'hf3;
8'h7f: out <= 8'hd2;
8'h80: out <= 8'hcd;
8'h81: out <= 8'h0c;
8'h82: out <= 8'h13;
8'h83: out <= 8'hec;
8'h84: out <= 8'h5f;
8'h85: out <= 8'h97;
8'h86: out <= 8'h44;
8'h87: out <= 8'h17;
8'h88: out <= 8'hc4;
8'h89: out <= 8'ha7;
8'h8a: out <= 8'h7e;
8'h8b: out <= 8'h3d;
8'h8c: out <= 8'h64;
8'h8d: out <= 8'h5d;
8'h8e: out <= 8'h19;
8'h8f: out <= 8'h73;
8'h90: out <= 8'h60;
8'h91: out <= 8'h81;
8'h92: out <= 8'h4f;
8'h93: out <= 8'hdc;
8'h94: out <= 8'h22;
8'h95: out <= 8'h2a;
8'h96: out <= 8'h90;
8'h97: out <= 8'h88;
8'h98: out <= 8'h46;
8'h99: out <= 8'hee;
8'h9a: out <= 8'hb8;
8'h9b: out <= 8'h14;
8'h9c: out <= 8'hde;
8'h9d: out <= 8'h5e;
8'h9e: out <= 8'h0b;
8'h9f: out <= 8'hdb;
8'ha0: out <= 8'he0;
8'ha1: out <= 8'h32;
8'ha2: out <= 8'h3a;
8'ha3: out <= 8'h0a;
8'ha4: out <= 8'h49;
8'ha5: out <= 8'h06;
8'ha6: out <= 8'h24;
8'ha7: out <= 8'h5c;
8'ha8: out <= 8'hc2;
8'ha9: out <= 8'hd3;
8'haa: out <= 8'hac;
8'hab: out <= 8'h62;
8'hac: out <= 8'h91;
8'had: out <= 8'h95;
8'hae: out <= 8'he4;
8'haf: out <= 8'h79;
8'hb0: out <= 8'he7;
8'hb1: out <= 8'hc8;
8'hb2: out <= 8'h37;
8'hb3: out <= 8'h6d;
8'hb4: out <= 8'h8d;
8'hb5: out <= 8'hd5;
8'hb6: out <= 8'h4e;
8'hb7: out <= 8'ha9;
8'hb8: out <= 8'h6c;
8'hb9: out <= 8'h56;
8'hba: out <= 8'hf4;
8'hbb: out <= 8'hea;
8'hbc: out <= 8'h65;
8'hbd: out <= 8'h7a;
8'hbe: out <= 8'hae;
8'hbf: out <= 8'h08;
8'hc0: out <= 8'hba;
8'hc1: out <= 8'h78;
8'hc2: out <= 8'h25;
8'hc3: out <= 8'h2e;
8'hc4: out <= 8'h1c;
8'hc5: out <= 8'ha6;
8'hc6: out <= 8'hb4;
8'hc7: out <= 8'hc6;
8'hc8: out <= 8'he8;
8'hc9: out <= 8'hdd;
8'hca: out <= 8'h74;
8'hcb: out <= 8'h1f;
8'hcc: out <= 8'h4b;
8'hcd: out <= 8'hbd;
8'hce: out <= 8'h8b;
8'hcf: out <= 8'h8a;
8'hd0: out <= 8'h70;
8'hd1: out <= 8'h3e;
8'hd2: out <= 8'hb5;
8'hd3: out <= 8'h66;
8'hd4: out <= 8'h48;
8'hd5: out <= 8'h03;
8'hd6: out <= 8'hf6;
8'hd7: out <= 8'h0e;
8'hd8: out <= 8'h61;
8'hd9: out <= 8'h35;
8'hda: out <= 8'h57;
8'hdb: out <= 8'hb9;
8'hdc: out <= 8'h86;
8'hdd: out <= 8'hc1;
8'hde: out <= 8'h1d;
8'hdf: out <= 8'h9e;
8'he0: out <= 8'he1;
8'he1: out <= 8'hf8;
8'he2: out <= 8'h98;
8'he3: out <= 8'h11;
8'he4: out <= 8'h69;
8'he5: out <= 8'hd9;
8'he6: out <= 8'h8e;
8'he7: out <= 8'h94;
8'he8: out <= 8'h9b;
8'he9: out <= 8'h1e;
8'hea: out <= 8'h87;
8'heb: out <= 8'he9;
8'hec: out <= 8'hce;
8'hed: out <= 8'h55;
8'hee: out <= 8'h28;
8'hef: out <= 8'hdf;
8'hf0: out <= 8'h8c;
8'hf1: out <= 8'ha1;
8'hf2: out <= 8'h89;
8'hf3: out <= 8'h0d;
8'hf4: out <= 8'hbf;
8'hf5: out <= 8'he6;
8'hf6: out <= 8'h42;
8'hf7: out <= 8'h68;
8'hf8: out <= 8'h41;
8'hf9: out <= 8'h99;
8'hfa: out <= 8'h2d;
8'hfb: out <= 8'h0f;
8'hfc: out <= 8'hb0;
8'hfd: out <= 8'h54;
8'hfe: out <= 8'hbb;
8'hff: out <= 8'h16;
endcase
endmodule
/* S box * x */
module xS (clk, rst, in, out);
input clk;
input rst;
input [7:0] in;
output reg [7:0] out;
always @ (posedge clk or posedge rst)
if (rst)
out <= 8'd0;
else
case (in)
8'h00: out <= 8'hc6;
8'h01: out <= 8'hf8;
8'h02: out <= 8'hee;
8'h03: out <= 8'hf6;
8'h04: out <= 8'hff;
8'h05: out <= 8'hd6;
8'h06: out <= 8'hde;
8'h07: out <= 8'h91;
8'h08: out <= 8'h60;
8'h09: out <= 8'h02;
8'h0a: out <= 8'hce;
8'h0b: out <= 8'h56;
8'h0c: out <= 8'he7;
8'h0d: out <= 8'hb5;
8'h0e: out <= 8'h4d;
8'h0f: out <= 8'hec;
8'h10: out <= 8'h8f;
8'h11: out <= 8'h1f;
8'h12: out <= 8'h89;
8'h13: out <= 8'hfa;
8'h14: out <= 8'hef;
8'h15: out <= 8'hb2;
8'h16: out <= 8'h8e;
8'h17: out <= 8'hfb;
8'h18: out <= 8'h41;
8'h19: out <= 8'hb3;
8'h1a: out <= 8'h5f;
8'h1b: out <= 8'h45;
8'h1c: out <= 8'h23;
8'h1d: out <= 8'h53;
8'h1e: out <= 8'he4;
8'h1f: out <= 8'h9b;
8'h20: out <= 8'h75;
8'h21: out <= 8'he1;
8'h22: out <= 8'h3d;
8'h23: out <= 8'h4c;
8'h24: out <= 8'h6c;
8'h25: out <= 8'h7e;
8'h26: out <= 8'hf5;
8'h27: out <= 8'h83;
8'h28: out <= 8'h68;
8'h29: out <= 8'h51;
8'h2a: out <= 8'hd1;
8'h2b: out <= 8'hf9;
8'h2c: out <= 8'he2;
8'h2d: out <= 8'hab;
8'h2e: out <= 8'h62;
8'h2f: out <= 8'h2a;
8'h30: out <= 8'h08;
8'h31: out <= 8'h95;
8'h32: out <= 8'h46;
8'h33: out <= 8'h9d;
8'h34: out <= 8'h30;
8'h35: out <= 8'h37;
8'h36: out <= 8'h0a;
8'h37: out <= 8'h2f;
8'h38: out <= 8'h0e;
8'h39: out <= 8'h24;
8'h3a: out <= 8'h1b;
8'h3b: out <= 8'hdf;
8'h3c: out <= 8'hcd;
8'h3d: out <= 8'h4e;
8'h3e: out <= 8'h7f;
8'h3f: out <= 8'hea;
8'h40: out <= 8'h12;
8'h41: out <= 8'h1d;
8'h42: out <= 8'h58;
8'h43: out <= 8'h34;
8'h44: out <= 8'h36;
8'h45: out <= 8'hdc;
8'h46: out <= 8'hb4;
8'h47: out <= 8'h5b;
8'h48: out <= 8'ha4;
8'h49: out <= 8'h76;
8'h4a: out <= 8'hb7;
8'h4b: out <= 8'h7d;
8'h4c: out <= 8'h52;
8'h4d: out <= 8'hdd;
8'h4e: out <= 8'h5e;
8'h4f: out <= 8'h13;
8'h50: out <= 8'ha6;
8'h51: out <= 8'hb9;
8'h52: out <= 8'h00;
8'h53: out <= 8'hc1;
8'h54: out <= 8'h40;
8'h55: out <= 8'he3;
8'h56: out <= 8'h79;
8'h57: out <= 8'hb6;
8'h58: out <= 8'hd4;
8'h59: out <= 8'h8d;
8'h5a: out <= 8'h67;
8'h5b: out <= 8'h72;
8'h5c: out <= 8'h94;
8'h5d: out <= 8'h98;
8'h5e: out <= 8'hb0;
8'h5f: out <= 8'h85;
8'h60: out <= 8'hbb;
8'h61: out <= 8'hc5;
8'h62: out <= 8'h4f;
8'h63: out <= 8'hed;
8'h64: out <= 8'h86;
8'h65: out <= 8'h9a;
8'h66: out <= 8'h66;
8'h67: out <= 8'h11;
8'h68: out <= 8'h8a;
8'h69: out <= 8'he9;
8'h6a: out <= 8'h04;
8'h6b: out <= 8'hfe;
8'h6c: out <= 8'ha0;
8'h6d: out <= 8'h78;
8'h6e: out <= 8'h25;
8'h6f: out <= 8'h4b;
8'h70: out <= 8'ha2;
8'h71: out <= 8'h5d;
8'h72: out <= 8'h80;
8'h73: out <= 8'h05;
8'h74: out <= 8'h3f;
8'h75: out <= 8'h21;
8'h76: out <= 8'h70;
8'h77: out <= 8'hf1;
8'h78: out <= 8'h63;
8'h79: out <= 8'h77;
8'h7a: out <= 8'haf;
8'h7b: out <= 8'h42;
8'h7c: out <= 8'h20;
8'h7d: out <= 8'he5;
8'h7e: out <= 8'hfd;
8'h7f: out <= 8'hbf;
8'h80: out <= 8'h81;
8'h81: out <= 8'h18;
8'h82: out <= 8'h26;
8'h83: out <= 8'hc3;
8'h84: out <= 8'hbe;
8'h85: out <= 8'h35;
8'h86: out <= 8'h88;
8'h87: out <= 8'h2e;
8'h88: out <= 8'h93;
8'h89: out <= 8'h55;
8'h8a: out <= 8'hfc;
8'h8b: out <= 8'h7a;
8'h8c: out <= 8'hc8;
8'h8d: out <= 8'hba;
8'h8e: out <= 8'h32;
8'h8f: out <= 8'he6;
8'h90: out <= 8'hc0;
8'h91: out <= 8'h19;
8'h92: out <= 8'h9e;
8'h93: out <= 8'ha3;
8'h94: out <= 8'h44;
8'h95: out <= 8'h54;
8'h96: out <= 8'h3b;
8'h97: out <= 8'h0b;
8'h98: out <= 8'h8c;
8'h99: out <= 8'hc7;
8'h9a: out <= 8'h6b;
8'h9b: out <= 8'h28;
8'h9c: out <= 8'ha7;
8'h9d: out <= 8'hbc;
8'h9e: out <= 8'h16;
8'h9f: out <= 8'had;
8'ha0: out <= 8'hdb;
8'ha1: out <= 8'h64;
8'ha2: out <= 8'h74;
8'ha3: out <= 8'h14;
8'ha4: out <= 8'h92;
8'ha5: out <= 8'h0c;
8'ha6: out <= 8'h48;
8'ha7: out <= 8'hb8;
8'ha8: out <= 8'h9f;
8'ha9: out <= 8'hbd;
8'haa: out <= 8'h43;
8'hab: out <= 8'hc4;
8'hac: out <= 8'h39;
8'had: out <= 8'h31;
8'hae: out <= 8'hd3;
8'haf: out <= 8'hf2;
8'hb0: out <= 8'hd5;
8'hb1: out <= 8'h8b;
8'hb2: out <= 8'h6e;
8'hb3: out <= 8'hda;
8'hb4: out <= 8'h01;
8'hb5: out <= 8'hb1;
8'hb6: out <= 8'h9c;
8'hb7: out <= 8'h49;
8'hb8: out <= 8'hd8;
8'hb9: out <= 8'hac;
8'hba: out <= 8'hf3;
8'hbb: out <= 8'hcf;
8'hbc: out <= 8'hca;
8'hbd: out <= 8'hf4;
8'hbe: out <= 8'h47;
8'hbf: out <= 8'h10;
8'hc0: out <= 8'h6f;
8'hc1: out <= 8'hf0;
8'hc2: out <= 8'h4a;
8'hc3: out <= 8'h5c;
8'hc4: out <= 8'h38;
8'hc5: out <= 8'h57;
8'hc6: out <= 8'h73;
8'hc7: out <= 8'h97;
8'hc8: out <= 8'hcb;
8'hc9: out <= 8'ha1;
8'hca: out <= 8'he8;
8'hcb: out <= 8'h3e;
8'hcc: out <= 8'h96;
8'hcd: out <= 8'h61;
8'hce: out <= 8'h0d;
8'hcf: out <= 8'h0f;
8'hd0: out <= 8'he0;
8'hd1: out <= 8'h7c;
8'hd2: out <= 8'h71;
8'hd3: out <= 8'hcc;
8'hd4: out <= 8'h90;
8'hd5: out <= 8'h06;
8'hd6: out <= 8'hf7;
8'hd7: out <= 8'h1c;
8'hd8: out <= 8'hc2;
8'hd9: out <= 8'h6a;
8'hda: out <= 8'hae;
8'hdb: out <= 8'h69;
8'hdc: out <= 8'h17;
8'hdd: out <= 8'h99;
8'hde: out <= 8'h3a;
8'hdf: out <= 8'h27;
8'he0: out <= 8'hd9;
8'he1: out <= 8'heb;
8'he2: out <= 8'h2b;
8'he3: out <= 8'h22;
8'he4: out <= 8'hd2;
8'he5: out <= 8'ha9;
8'he6: out <= 8'h07;
8'he7: out <= 8'h33;
8'he8: out <= 8'h2d;
8'he9: out <= 8'h3c;
8'hea: out <= 8'h15;
8'heb: out <= 8'hc9;
8'hec: out <= 8'h87;
8'hed: out <= 8'haa;
8'hee: out <= 8'h50;
8'hef: out <= 8'ha5;
8'hf0: out <= 8'h03;
8'hf1: out <= 8'h59;
8'hf2: out <= 8'h09;
8'hf3: out <= 8'h1a;
8'hf4: out <= 8'h65;
8'hf5: out <= 8'hd7;
8'hf6: out <= 8'h84;
8'hf7: out <= 8'hd0;
8'hf8: out <= 8'h82;
8'hf9: out <= 8'h29;
8'hfa: out <= 8'h5a;
8'hfb: out <= 8'h1e;
8'hfc: out <= 8'h7b;
8'hfd: out <= 8'ha8;
8'hfe: out <= 8'h6d;
8'hff: out <= 8'h2c;
endcase
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// CRP ////
//// DES Crypt Module ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module crp(P, R, K_sub);
/* verilator lint_off LITENDIAN */
output [1:32] P;
input [1:32] R;
input [1:48] K_sub;
wire [1:48] E;
wire [1:48] X;
wire [1:32] S;
/* verilator lint_on LITENDIAN */
assign E[1:48] = { R[32], R[1], R[2], R[3], R[4], R[5], R[4], R[5],
R[6], R[7], R[8], R[9], R[8], R[9], R[10], R[11],
R[12], R[13], R[12], R[13], R[14], R[15], R[16],
R[17], R[16], R[17], R[18], R[19], R[20], R[21],
R[20], R[21], R[22], R[23], R[24], R[25], R[24],
R[25], R[26], R[27], R[28], R[29], R[28], R[29],
R[30], R[31], R[32], R[1]};
assign X = E ^ K_sub;
sbox1 u0( .addr(X[01:06]), .dout(S[01:04]) );
sbox2 u1( .addr(X[07:12]), .dout(S[05:08]) );
sbox3 u2( .addr(X[13:18]), .dout(S[09:12]) );
sbox4 u3( .addr(X[19:24]), .dout(S[13:16]) );
sbox5 u4( .addr(X[25:30]), .dout(S[17:20]) );
sbox6 u5( .addr(X[31:36]), .dout(S[21:24]) );
sbox7 u6( .addr(X[37:42]), .dout(S[25:28]) );
sbox8 u7( .addr(X[43:48]), .dout(S[29:32]) );
assign P[1:32] = { S[16], S[7], S[20], S[21], S[29], S[12], S[28],
S[17], S[1], S[15], S[23], S[26], S[5], S[18],
S[31], S[10], S[2], S[8], S[24], S[14], S[32],
S[27], S[3], S[9], S[19], S[13], S[30], S[6],
S[22], S[11], S[4], S[25]};
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// DES ////
//// DES Top Level module ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module des3(desOut, out_valid, start, desIn, key1, key2, key3, decrypt, clk);
output reg[63:0] desOut;
output out_valid;
input start;
input [63:0] desIn;
input [55:0] key1;
input [55:0] key2;
input [55:0] key3;
input decrypt;
input clk;
/* verilator lint_off LITENDIAN */
wire [1:48] K_sub;
wire [1:64] IP, FP;
reg [1:64] FP_R;
reg [1:32] L, R;
wire [1:32] Xin;
wire [1:32] Lout;
wire [1:32] Rout;
wire [1:32] out;
/* verilator lint_on LITENDIAN */
reg [5:0] roundSel;
reg start_r;
always @(posedge clk)
begin
start_r <= start;
end
wire start_posedge = start & ~start_r;
reg [7:0] validCounter;
wire [63:0] des;
always @ (posedge clk)
begin
if(start_posedge)
begin
roundSel <= 6'h00;
end
else if(~out_valid)
begin
roundSel <= roundSel +1;
end
end
assign out_valid = (roundSel == 6'h30);
always @ (posedge clk)
begin
if(!out_valid)
begin
desOut <= des;
end
end
crp u0(
.P(out),
.R(Lout),
.K_sub(K_sub));
// Select a subkey from key.
key_sel3 u1(
.K_sub(K_sub),
.key1(key1),
.key2(key2),
.key3(key3),
.roundSel(roundSel),
.decrypt(decrypt)
);
assign Lout = (roundSel == 0) ? IP[33:64] : ((roundSel == 16) ? FP_R[33:64] : ((roundSel == 32) ? FP_R[33:64] : R));
assign Xin = (roundSel == 0) ? IP[01:32] : ((roundSel == 16) ? FP_R[01:32] : ((roundSel == 32) ? FP_R[01:32] : L));
always @(posedge clk)
FP_R <= FP;
assign Rout = Xin ^ out;
assign FP = { Rout, Lout};
always @(posedge clk)
L <= Lout;
always @(posedge clk)
R <= Rout;
// Perform initial permutation
assign IP[1:64] = {desIn[06], desIn[14], desIn[22], desIn[30], desIn[38], desIn[46],
desIn[54], desIn[62], desIn[04], desIn[12], desIn[20], desIn[28],
desIn[36], desIn[44], desIn[52], desIn[60], desIn[02], desIn[10],
desIn[18], desIn[26], desIn[34], desIn[42], desIn[50], desIn[58],
desIn[00], desIn[08], desIn[16], desIn[24], desIn[32], desIn[40],
desIn[48], desIn[56], desIn[07], desIn[15], desIn[23], desIn[31],
desIn[39], desIn[47], desIn[55], desIn[63], desIn[05], desIn[13],
desIn[21], desIn[29], desIn[37], desIn[45], desIn[53], desIn[61],
desIn[03], desIn[11], desIn[19], desIn[27], desIn[35], desIn[43],
desIn[51], desIn[59], desIn[01], desIn[09], desIn[17], desIn[25],
desIn[33], desIn[41], desIn[49], desIn[57] };
// Perform final permutation
assign des = {FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32],
FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31],
FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30],
FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29],
FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28],
FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27],
FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26],
FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] };
endmodule
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : des3_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-DES3 core
//
module des3_top #(
parameter remove_parity_bits=0)
(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg start, start_r;
reg decrypt;
reg [31:0] desIn [0:1];
reg [31:0] key [0:5];
reg wb_stb_i_r;
wire [63:0] des_in={desIn[0], desIn[1]};
wire [55:0] key_1;
wire [55:0] key_2;
wire [55:0] key_3;
wire [63:0] ct;
wire ct_valid;
// The following generate logic is to used to remove the parity bits from the key
// This was performed in the C test code that loaded vectors
genvar i;
generate if (remove_parity_bits == 1) begin
for (i = 0; i < 4; i = i + 1) begin
assign key_1[34 + i*7:28 + i*7] = key[0][i*8+1 + 6:i*8+1];
assign key_1[ 6 + i*7: i*7] = key[1][i*8+1 + 6:i*8+1];
assign key_2[34 + i*7:28 + i*7] = key[2][i*8+1 + 6:i*8+1];
assign key_2[ 6 + i*7: i*7] = key[3][i*8+1 + 6:i*8+1];
assign key_3[34 + i*7:28 + i*7] = key[4][i*8+1 + 6:i*8+1];
assign key_3[ 6 + i*7: i*7] = key[5][i*8+1 + 6:i*8+1];
end // generate for (i = 0; i < 4; i = i + 1)
end else begin
assign key_1 = {key[0][27:0], key[1][27:0]};
assign key_2 = {key[2][27:0], key[3][27:0]};
assign key_3 = {key[4][27:0], key[5][27:0]};
end // end else
endgenerate
// Generate the acknowledgement signal
assign wb_ack_o = wb_stb_i_r && wb_stb_i;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i)
begin
if(wb_rst_i)
begin
start <= 0;
start_r <= 0;
decrypt <= 0;
desIn[1] <= 0;
desIn[0] <= 0;
key[5] <= 0;
key[4] <= 0;
key[3] <= 0;
key[2] <= 0;
key[1] <= 0;
key[0] <= 0;
wb_stb_i_r <= 1'b0;
end
else begin
// Generate registered versions of start
start_r <= start;
// Generate a registered version of the write strobe
wb_stb_i_r <= wb_stb_i;
// Peform a write
if(wb_stb_i & wb_we_i) begin
case(wb_adr_i[5:2])
0:
start <= wb_dat_i[0];
1:
decrypt <= wb_dat_i[0];
2:
desIn[1]<= wb_dat_i;
3:
desIn[0]<= wb_dat_i;
4:
key[5] <= wb_dat_i;
5:
key[4] <= wb_dat_i;
6:
key[3] <= wb_dat_i;
7:
key[2] <= wb_dat_i;
8:
key[1] <= wb_dat_i;
9:
key[0] <= wb_dat_i;
default:
;
endcase
end else begin // if wb_stb_i & wb_we_i
start <= 1'b0;
end
end // else
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[5:2])
2:
wb_dat_o = desIn[1];
3:
wb_dat_o = desIn[0];
4:
wb_dat_o = key[5];
5:
wb_dat_o = key[4];
6:
wb_dat_o = key[3];
7:
wb_dat_o = key[2];
8:
wb_dat_o = key[1];
9:
wb_dat_o = key[0];
10:
wb_dat_o = {31'b0, ct_valid};
11:
wb_dat_o = ct[63:32];
12:
wb_dat_o = ct[31:0];
default:
wb_dat_o = 32'b0;
endcase
end // always @ (*)
des3 des3(
.desOut(ct),
.out_valid(ct_valid),
.start(start && ~start_r),
.desIn(des_in),
.key1(key_1),
.key2(key_2),
.key3(key_3),
.decrypt(decrypt),
.clk(wb_clk_i));
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// KEY_SEL ////
//// Select one of 16 sub-keys for round ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module key_sel3(K_sub, key1, key2, key3, roundSel, decrypt);
/* verilator lint_off LITENDIAN */
output [1:48] K_sub;
/* verilator lint_on LITENDIAN */
input [55:0] key1, key2, key3;
input [5:0] roundSel;
input decrypt;
wire decrypt_int;
reg [55:0] K;
reg [1:48] K_sub;
/* verilator lint_off LITENDIAN */
wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9;
wire [1:48] K10, K11, K12, K13, K14, K15, K16;
/* verilator lint_on LITENDIAN */
always @(roundSel or decrypt or key1 or key2 or key3)
case ({decrypt, roundSel[5:4]}) // synopsys full_case parallel_case
3'b0_00:
K = key1;
3'b0_01:
K = key2;
3'b0_10:
K = key3;
3'b1_00:
K = key3;
3'b1_01:
K = key2;
3'b1_10:
K = key1;
3'b0_11:
K = 56'b0;
3'b1_11:
K = 56'b0;
endcase
assign decrypt_int = (roundSel[5:4]==2'h1) ? !decrypt : decrypt;
always @(K1 or K2 or K3 or K4 or K5 or K6 or K7 or K8 or K9 or K10
or K11 or K12 or K13 or K14 or K15 or K16 or roundSel)
case(roundSel[3:0]) // synopsys full_case parallel_case
0:
K_sub = K1;
1:
K_sub = K2;
2:
K_sub = K3;
3:
K_sub = K4;
4:
K_sub = K5;
5:
K_sub = K6;
6:
K_sub = K7;
7:
K_sub = K8;
8:
K_sub = K9;
9:
K_sub = K10;
10:
K_sub = K11;
11:
K_sub = K12;
12:
K_sub = K13;
13:
K_sub = K14;
14:
K_sub = K15;
15:
K_sub = K16;
endcase
assign K16[1] = decrypt_int ? K[47] : K[40];
assign K16[2] = decrypt_int ? K[11] : K[4];
assign K16[3] = decrypt_int ? K[26] : K[19];
assign K16[4] = decrypt_int ? K[3] : K[53];
assign K16[5] = decrypt_int ? K[13] : K[6];
assign K16[6] = decrypt_int ? K[41] : K[34];
assign K16[7] = decrypt_int ? K[27] : K[20];
assign K16[8] = decrypt_int ? K[6] : K[24];
assign K16[9] = decrypt_int ? K[54] : K[47];
assign K16[10] = decrypt_int ? K[48] : K[41];
assign K16[11] = decrypt_int ? K[39] : K[32];
assign K16[12] = decrypt_int ? K[19] : K[12];
assign K16[13] = decrypt_int ? K[53] : K[46];
assign K16[14] = decrypt_int ? K[25] : K[18];
assign K16[15] = decrypt_int ? K[33] : K[26];
assign K16[16] = decrypt_int ? K[34] : K[27];
assign K16[17] = decrypt_int ? K[17] : K[10];
assign K16[18] = decrypt_int ? K[5] : K[55];
assign K16[19] = decrypt_int ? K[4] : K[54];
assign K16[20] = decrypt_int ? K[55] : K[48];
assign K16[21] = decrypt_int ? K[24] : K[17];
assign K16[22] = decrypt_int ? K[32] : K[25];
assign K16[23] = decrypt_int ? K[40] : K[33];
assign K16[24] = decrypt_int ? K[20] : K[13];
assign K16[25] = decrypt_int ? K[36] : K[29];
assign K16[26] = decrypt_int ? K[31] : K[51];
assign K16[27] = decrypt_int ? K[21] : K[14];
assign K16[28] = decrypt_int ? K[8] : K[1];
assign K16[29] = decrypt_int ? K[23] : K[16];
assign K16[30] = decrypt_int ? K[52] : K[45];
assign K16[31] = decrypt_int ? K[14] : K[7];
assign K16[32] = decrypt_int ? K[29] : K[22];
assign K16[33] = decrypt_int ? K[51] : K[44];
assign K16[34] = decrypt_int ? K[9] : K[2];
assign K16[35] = decrypt_int ? K[35] : K[28];
assign K16[36] = decrypt_int ? K[30] : K[23];
assign K16[37] = decrypt_int ? K[2] : K[50];
assign K16[38] = decrypt_int ? K[37] : K[30];
assign K16[39] = decrypt_int ? K[22] : K[15];
assign K16[40] = decrypt_int ? K[0] : K[52];
assign K16[41] = decrypt_int ? K[42] : K[35];
assign K16[42] = decrypt_int ? K[38] : K[31];
assign K16[43] = decrypt_int ? K[16] : K[9];
assign K16[44] = decrypt_int ? K[43] : K[36];
assign K16[45] = decrypt_int ? K[44] : K[37];
assign K16[46] = decrypt_int ? K[1] : K[49];
assign K16[47] = decrypt_int ? K[7] : K[0];
assign K16[48] = decrypt_int ? K[28] : K[21];
assign K15[1] = decrypt_int ? K[54] : K[33];
assign K15[2] = decrypt_int ? K[18] : K[54];
assign K15[3] = decrypt_int ? K[33] : K[12];
assign K15[4] = decrypt_int ? K[10] : K[46];
assign K15[5] = decrypt_int ? K[20] : K[24];
assign K15[6] = decrypt_int ? K[48] : K[27];
assign K15[7] = decrypt_int ? K[34] : K[13];
assign K15[8] = decrypt_int ? K[13] : K[17];
assign K15[9] = decrypt_int ? K[4] : K[40];
assign K15[10] = decrypt_int ? K[55] : K[34];
assign K15[11] = decrypt_int ? K[46] : K[25];
assign K15[12] = decrypt_int ? K[26] : K[5];
assign K15[13] = decrypt_int ? K[3] : K[39];
assign K15[14] = decrypt_int ? K[32] : K[11];
assign K15[15] = decrypt_int ? K[40] : K[19];
assign K15[16] = decrypt_int ? K[41] : K[20];
assign K15[17] = decrypt_int ? K[24] : K[3];
assign K15[18] = decrypt_int ? K[12] : K[48];
assign K15[19] = decrypt_int ? K[11] : K[47];
assign K15[20] = decrypt_int ? K[5] : K[41];
assign K15[21] = decrypt_int ? K[6] : K[10];
assign K15[22] = decrypt_int ? K[39] : K[18];
assign K15[23] = decrypt_int ? K[47] : K[26];
assign K15[24] = decrypt_int ? K[27] : K[6];
assign K15[25] = decrypt_int ? K[43] : K[22];
assign K15[26] = decrypt_int ? K[38] : K[44];
assign K15[27] = decrypt_int ? K[28] : K[7];
assign K15[28] = decrypt_int ? K[15] : K[49];
assign K15[29] = decrypt_int ? K[30] : K[9];
assign K15[30] = decrypt_int ? K[0] : K[38];
assign K15[31] = decrypt_int ? K[21] : K[0];
assign K15[32] = decrypt_int ? K[36] : K[15];
assign K15[33] = decrypt_int ? K[31] : K[37];
assign K15[34] = decrypt_int ? K[16] : K[50];
assign K15[35] = decrypt_int ? K[42] : K[21];
assign K15[36] = decrypt_int ? K[37] : K[16];
assign K15[37] = decrypt_int ? K[9] : K[43];
assign K15[38] = decrypt_int ? K[44] : K[23];
assign K15[39] = decrypt_int ? K[29] : K[8];
assign K15[40] = decrypt_int ? K[7] : K[45];
assign K15[41] = decrypt_int ? K[49] : K[28];
assign K15[42] = decrypt_int ? K[45] : K[51];
assign K15[43] = decrypt_int ? K[23] : K[2];
assign K15[44] = decrypt_int ? K[50] : K[29];
assign K15[45] = decrypt_int ? K[51] : K[30];
assign K15[46] = decrypt_int ? K[8] : K[42];
assign K15[47] = decrypt_int ? K[14] : K[52];
assign K15[48] = decrypt_int ? K[35] : K[14];
assign K14[1] = decrypt_int ? K[11] : K[19];
assign K14[2] = decrypt_int ? K[32] : K[40];
assign K14[3] = decrypt_int ? K[47] : K[55];
assign K14[4] = decrypt_int ? K[24] : K[32];
assign K14[5] = decrypt_int ? K[34] : K[10];
assign K14[6] = decrypt_int ? K[5] : K[13];
assign K14[7] = decrypt_int ? K[48] : K[24];
assign K14[8] = decrypt_int ? K[27] : K[3];
assign K14[9] = decrypt_int ? K[18] : K[26];
assign K14[10] = decrypt_int ? K[12] : K[20];
assign K14[11] = decrypt_int ? K[3] : K[11];
assign K14[12] = decrypt_int ? K[40] : K[48];
assign K14[13] = decrypt_int ? K[17] : K[25];
assign K14[14] = decrypt_int ? K[46] : K[54];
assign K14[15] = decrypt_int ? K[54] : K[5];
assign K14[16] = decrypt_int ? K[55] : K[6];
assign K14[17] = decrypt_int ? K[13] : K[46];
assign K14[18] = decrypt_int ? K[26] : K[34];
assign K14[19] = decrypt_int ? K[25] : K[33];
assign K14[20] = decrypt_int ? K[19] : K[27];
assign K14[21] = decrypt_int ? K[20] : K[53];
assign K14[22] = decrypt_int ? K[53] : K[4];
assign K14[23] = decrypt_int ? K[4] : K[12];
assign K14[24] = decrypt_int ? K[41] : K[17];
assign K14[25] = decrypt_int ? K[2] : K[8];
assign K14[26] = decrypt_int ? K[52] : K[30];
assign K14[27] = decrypt_int ? K[42] : K[52];
assign K14[28] = decrypt_int ? K[29] : K[35];
assign K14[29] = decrypt_int ? K[44] : K[50];
assign K14[30] = decrypt_int ? K[14] : K[51];
assign K14[31] = decrypt_int ? K[35] : K[45];
assign K14[32] = decrypt_int ? K[50] : K[1];
assign K14[33] = decrypt_int ? K[45] : K[23];
assign K14[34] = decrypt_int ? K[30] : K[36];
assign K14[35] = decrypt_int ? K[1] : K[7];
assign K14[36] = decrypt_int ? K[51] : K[2];
assign K14[37] = decrypt_int ? K[23] : K[29];
assign K14[38] = decrypt_int ? K[31] : K[9];
assign K14[39] = decrypt_int ? K[43] : K[49];
assign K14[40] = decrypt_int ? K[21] : K[31];
assign K14[41] = decrypt_int ? K[8] : K[14];
assign K14[42] = decrypt_int ? K[0] : K[37];
assign K14[43] = decrypt_int ? K[37] : K[43];
assign K14[44] = decrypt_int ? K[9] : K[15];
assign K14[45] = decrypt_int ? K[38] : K[16];
assign K14[46] = decrypt_int ? K[22] : K[28];
assign K14[47] = decrypt_int ? K[28] : K[38];
assign K14[48] = decrypt_int ? K[49] : K[0];
assign K13[1] = decrypt_int ? K[25] : K[5];
assign K13[2] = decrypt_int ? K[46] : K[26];
assign K13[3] = decrypt_int ? K[4] : K[41];
assign K13[4] = decrypt_int ? K[13] : K[18];
assign K13[5] = decrypt_int ? K[48] : K[53];
assign K13[6] = decrypt_int ? K[19] : K[24];
assign K13[7] = decrypt_int ? K[5] : K[10];
assign K13[8] = decrypt_int ? K[41] : K[46];
assign K13[9] = decrypt_int ? K[32] : K[12];
assign K13[10] = decrypt_int ? K[26] : K[6];
assign K13[11] = decrypt_int ? K[17] : K[54];
assign K13[12] = decrypt_int ? K[54] : K[34];
assign K13[13] = decrypt_int ? K[6] : K[11];
assign K13[14] = decrypt_int ? K[3] : K[40];
assign K13[15] = decrypt_int ? K[11] : K[48];
assign K13[16] = decrypt_int ? K[12] : K[17];
assign K13[17] = decrypt_int ? K[27] : K[32];
assign K13[18] = decrypt_int ? K[40] : K[20];
assign K13[19] = decrypt_int ? K[39] : K[19];
assign K13[20] = decrypt_int ? K[33] : K[13];
assign K13[21] = decrypt_int ? K[34] : K[39];
assign K13[22] = decrypt_int ? K[10] : K[47];
assign K13[23] = decrypt_int ? K[18] : K[55];
assign K13[24] = decrypt_int ? K[55] : K[3];
assign K13[25] = decrypt_int ? K[16] : K[49];
assign K13[26] = decrypt_int ? K[7] : K[16];
assign K13[27] = decrypt_int ? K[1] : K[38];
assign K13[28] = decrypt_int ? K[43] : K[21];
assign K13[29] = decrypt_int ? K[31] : K[36];
assign K13[30] = decrypt_int ? K[28] : K[37];
assign K13[31] = decrypt_int ? K[49] : K[31];
assign K13[32] = decrypt_int ? K[9] : K[42];
assign K13[33] = decrypt_int ? K[0] : K[9];
assign K13[34] = decrypt_int ? K[44] : K[22];
assign K13[35] = decrypt_int ? K[15] : K[52];
assign K13[36] = decrypt_int ? K[38] : K[43];
assign K13[37] = decrypt_int ? K[37] : K[15];
assign K13[38] = decrypt_int ? K[45] : K[50];
assign K13[39] = decrypt_int ? K[2] : K[35];
assign K13[40] = decrypt_int ? K[35] : K[44];
assign K13[41] = decrypt_int ? K[22] : K[0];
assign K13[42] = decrypt_int ? K[14] : K[23];
assign K13[43] = decrypt_int ? K[51] : K[29];
assign K13[44] = decrypt_int ? K[23] : K[1];
assign K13[45] = decrypt_int ? K[52] : K[2];
assign K13[46] = decrypt_int ? K[36] : K[14];
assign K13[47] = decrypt_int ? K[42] : K[51];
assign K13[48] = decrypt_int ? K[8] : K[45];
assign K12[1] = decrypt_int ? K[39] : K[48];
assign K12[2] = decrypt_int ? K[3] : K[12];
assign K12[3] = decrypt_int ? K[18] : K[27];
assign K12[4] = decrypt_int ? K[27] : K[4];
assign K12[5] = decrypt_int ? K[5] : K[39];
assign K12[6] = decrypt_int ? K[33] : K[10];
assign K12[7] = decrypt_int ? K[19] : K[53];
assign K12[8] = decrypt_int ? K[55] : K[32];
assign K12[9] = decrypt_int ? K[46] : K[55];
assign K12[10] = decrypt_int ? K[40] : K[17];
assign K12[11] = decrypt_int ? K[6] : K[40];
assign K12[12] = decrypt_int ? K[11] : K[20];
assign K12[13] = decrypt_int ? K[20] : K[54];
assign K12[14] = decrypt_int ? K[17] : K[26];
assign K12[15] = decrypt_int ? K[25] : K[34];
assign K12[16] = decrypt_int ? K[26] : K[3];
assign K12[17] = decrypt_int ? K[41] : K[18];
assign K12[18] = decrypt_int ? K[54] : K[6];
assign K12[19] = decrypt_int ? K[53] : K[5];
assign K12[20] = decrypt_int ? K[47] : K[24];
assign K12[21] = decrypt_int ? K[48] : K[25];
assign K12[22] = decrypt_int ? K[24] : K[33];
assign K12[23] = decrypt_int ? K[32] : K[41];
assign K12[24] = decrypt_int ? K[12] : K[46];
assign K12[25] = decrypt_int ? K[30] : K[35];
assign K12[26] = decrypt_int ? K[21] : K[2];
assign K12[27] = decrypt_int ? K[15] : K[51];
assign K12[28] = decrypt_int ? K[2] : K[7];
assign K12[29] = decrypt_int ? K[45] : K[22];
assign K12[30] = decrypt_int ? K[42] : K[23];
assign K12[31] = decrypt_int ? K[8] : K[44];
assign K12[32] = decrypt_int ? K[23] : K[28];
assign K12[33] = decrypt_int ? K[14] : K[50];
assign K12[34] = decrypt_int ? K[31] : K[8];
assign K12[35] = decrypt_int ? K[29] : K[38];
assign K12[36] = decrypt_int ? K[52] : K[29];
assign K12[37] = decrypt_int ? K[51] : K[1];
assign K12[38] = decrypt_int ? K[0] : K[36];
assign K12[39] = decrypt_int ? K[16] : K[21];
assign K12[40] = decrypt_int ? K[49] : K[30];
assign K12[41] = decrypt_int ? K[36] : K[45];
assign K12[42] = decrypt_int ? K[28] : K[9];
assign K12[43] = decrypt_int ? K[38] : K[15];
assign K12[44] = decrypt_int ? K[37] : K[42];
assign K12[45] = decrypt_int ? K[7] : K[43];
assign K12[46] = decrypt_int ? K[50] : K[0];
assign K12[47] = decrypt_int ? K[1] : K[37];
assign K12[48] = decrypt_int ? K[22] : K[31];
assign K11[1] = decrypt_int ? K[53] : K[34];
assign K11[2] = decrypt_int ? K[17] : K[55];
assign K11[3] = decrypt_int ? K[32] : K[13];
assign K11[4] = decrypt_int ? K[41] : K[47];
assign K11[5] = decrypt_int ? K[19] : K[25];
assign K11[6] = decrypt_int ? K[47] : K[53];
assign K11[7] = decrypt_int ? K[33] : K[39];
assign K11[8] = decrypt_int ? K[12] : K[18];
assign K11[9] = decrypt_int ? K[3] : K[41];
assign K11[10] = decrypt_int ? K[54] : K[3];
assign K11[11] = decrypt_int ? K[20] : K[26];
assign K11[12] = decrypt_int ? K[25] : K[6];
assign K11[13] = decrypt_int ? K[34] : K[40];
assign K11[14] = decrypt_int ? K[6] : K[12];
assign K11[15] = decrypt_int ? K[39] : K[20];
assign K11[16] = decrypt_int ? K[40] : K[46];
assign K11[17] = decrypt_int ? K[55] : K[4];
assign K11[18] = decrypt_int ? K[11] : K[17];
assign K11[19] = decrypt_int ? K[10] : K[48];
assign K11[20] = decrypt_int ? K[4] : K[10];
assign K11[21] = decrypt_int ? K[5] : K[11];
assign K11[22] = decrypt_int ? K[13] : K[19];
assign K11[23] = decrypt_int ? K[46] : K[27];
assign K11[24] = decrypt_int ? K[26] : K[32];
assign K11[25] = decrypt_int ? K[44] : K[21];
assign K11[26] = decrypt_int ? K[35] : K[43];
assign K11[27] = decrypt_int ? K[29] : K[37];
assign K11[28] = decrypt_int ? K[16] : K[52];
assign K11[29] = decrypt_int ? K[0] : K[8];
assign K11[30] = decrypt_int ? K[1] : K[9];
assign K11[31] = decrypt_int ? K[22] : K[30];
assign K11[32] = decrypt_int ? K[37] : K[14];
assign K11[33] = decrypt_int ? K[28] : K[36];
assign K11[34] = decrypt_int ? K[45] : K[49];
assign K11[35] = decrypt_int ? K[43] : K[51];
assign K11[36] = decrypt_int ? K[7] : K[15];
assign K11[37] = decrypt_int ? K[38] : K[42];
assign K11[38] = decrypt_int ? K[14] : K[22];
assign K11[39] = decrypt_int ? K[30] : K[7];
assign K11[40] = decrypt_int ? K[8] : K[16];
assign K11[41] = decrypt_int ? K[50] : K[31];
assign K11[42] = decrypt_int ? K[42] : K[50];
assign K11[43] = decrypt_int ? K[52] : K[1];
assign K11[44] = decrypt_int ? K[51] : K[28];
assign K11[45] = decrypt_int ? K[21] : K[29];
assign K11[46] = decrypt_int ? K[9] : K[45];
assign K11[47] = decrypt_int ? K[15] : K[23];
assign K11[48] = decrypt_int ? K[36] : K[44];
assign K10[1] = decrypt_int ? K[10] : K[20];
assign K10[2] = decrypt_int ? K[6] : K[41];
assign K10[3] = decrypt_int ? K[46] : K[24];
assign K10[4] = decrypt_int ? K[55] : K[33];
assign K10[5] = decrypt_int ? K[33] : K[11];
assign K10[6] = decrypt_int ? K[4] : K[39];
assign K10[7] = decrypt_int ? K[47] : K[25];
assign K10[8] = decrypt_int ? K[26] : K[4];
assign K10[9] = decrypt_int ? K[17] : K[27];
assign K10[10] = decrypt_int ? K[11] : K[46];
assign K10[11] = decrypt_int ? K[34] : K[12];
assign K10[12] = decrypt_int ? K[39] : K[17];
assign K10[13] = decrypt_int ? K[48] : K[26];
assign K10[14] = decrypt_int ? K[20] : K[55];
assign K10[15] = decrypt_int ? K[53] : K[6];
assign K10[16] = decrypt_int ? K[54] : K[32];
assign K10[17] = decrypt_int ? K[12] : K[47];
assign K10[18] = decrypt_int ? K[25] : K[3];
assign K10[19] = decrypt_int ? K[24] : K[34];
assign K10[20] = decrypt_int ? K[18] : K[53];
assign K10[21] = decrypt_int ? K[19] : K[54];
assign K10[22] = decrypt_int ? K[27] : K[5];
assign K10[23] = decrypt_int ? K[3] : K[13];
assign K10[24] = decrypt_int ? K[40] : K[18];
assign K10[25] = decrypt_int ? K[31] : K[7];
assign K10[26] = decrypt_int ? K[49] : K[29];
assign K10[27] = decrypt_int ? K[43] : K[23];
assign K10[28] = decrypt_int ? K[30] : K[38];
assign K10[29] = decrypt_int ? K[14] : K[49];
assign K10[30] = decrypt_int ? K[15] : K[50];
assign K10[31] = decrypt_int ? K[36] : K[16];
assign K10[32] = decrypt_int ? K[51] : K[0];
assign K10[33] = decrypt_int ? K[42] : K[22];
assign K10[34] = decrypt_int ? K[0] : K[35];
assign K10[35] = decrypt_int ? K[2] : K[37];
assign K10[36] = decrypt_int ? K[21] : K[1];
assign K10[37] = decrypt_int ? K[52] : K[28];
assign K10[38] = decrypt_int ? K[28] : K[8];
assign K10[39] = decrypt_int ? K[44] : K[52];
assign K10[40] = decrypt_int ? K[22] : K[2];
assign K10[41] = decrypt_int ? K[9] : K[44];
assign K10[42] = decrypt_int ? K[1] : K[36];
assign K10[43] = decrypt_int ? K[7] : K[42];
assign K10[44] = decrypt_int ? K[38] : K[14];
assign K10[45] = decrypt_int ? K[35] : K[15];
assign K10[46] = decrypt_int ? K[23] : K[31];
assign K10[47] = decrypt_int ? K[29] : K[9];
assign K10[48] = decrypt_int ? K[50] : K[30];
assign K9[1] = decrypt_int ? K[24] : K[6];
assign K9[2] = decrypt_int ? K[20] : K[27];
assign K9[3] = decrypt_int ? K[3] : K[10];
assign K9[4] = decrypt_int ? K[12] : K[19];
assign K9[5] = decrypt_int ? K[47] : K[54];
assign K9[6] = decrypt_int ? K[18] : K[25];
assign K9[7] = decrypt_int ? K[4] : K[11];
assign K9[8] = decrypt_int ? K[40] : K[47];
assign K9[9] = decrypt_int ? K[6] : K[13];
assign K9[10] = decrypt_int ? K[25] : K[32];
assign K9[11] = decrypt_int ? K[48] : K[55];
assign K9[12] = decrypt_int ? K[53] : K[3];
assign K9[13] = decrypt_int ? K[5] : K[12];
assign K9[14] = decrypt_int ? K[34] : K[41];
assign K9[15] = decrypt_int ? K[10] : K[17];
assign K9[16] = decrypt_int ? K[11] : K[18];
assign K9[17] = decrypt_int ? K[26] : K[33];
assign K9[18] = decrypt_int ? K[39] : K[46];
assign K9[19] = decrypt_int ? K[13] : K[20];
assign K9[20] = decrypt_int ? K[32] : K[39];
assign K9[21] = decrypt_int ? K[33] : K[40];
assign K9[22] = decrypt_int ? K[41] : K[48];
assign K9[23] = decrypt_int ? K[17] : K[24];
assign K9[24] = decrypt_int ? K[54] : K[4];
assign K9[25] = decrypt_int ? K[45] : K[52];
assign K9[26] = decrypt_int ? K[8] : K[15];
assign K9[27] = decrypt_int ? K[2] : K[9];
assign K9[28] = decrypt_int ? K[44] : K[51];
assign K9[29] = decrypt_int ? K[28] : K[35];
assign K9[30] = decrypt_int ? K[29] : K[36];
assign K9[31] = decrypt_int ? K[50] : K[2];
assign K9[32] = decrypt_int ? K[38] : K[45];
assign K9[33] = decrypt_int ? K[1] : K[8];
assign K9[34] = decrypt_int ? K[14] : K[21];
assign K9[35] = decrypt_int ? K[16] : K[23];
assign K9[36] = decrypt_int ? K[35] : K[42];
assign K9[37] = decrypt_int ? K[7] : K[14];
assign K9[38] = decrypt_int ? K[42] : K[49];
assign K9[39] = decrypt_int ? K[31] : K[38];
assign K9[40] = decrypt_int ? K[36] : K[43];
assign K9[41] = decrypt_int ? K[23] : K[30];
assign K9[42] = decrypt_int ? K[15] : K[22];
assign K9[43] = decrypt_int ? K[21] : K[28];
assign K9[44] = decrypt_int ? K[52] : K[0];
assign K9[45] = decrypt_int ? K[49] : K[1];
assign K9[46] = decrypt_int ? K[37] : K[44];
assign K9[47] = decrypt_int ? K[43] : K[50];
assign K9[48] = decrypt_int ? K[9] : K[16];
assign K8[1] = decrypt_int ? K[6] : K[24];
assign K8[2] = decrypt_int ? K[27] : K[20];
assign K8[3] = decrypt_int ? K[10] : K[3];
assign K8[4] = decrypt_int ? K[19] : K[12];
assign K8[5] = decrypt_int ? K[54] : K[47];
assign K8[6] = decrypt_int ? K[25] : K[18];
assign K8[7] = decrypt_int ? K[11] : K[4];
assign K8[8] = decrypt_int ? K[47] : K[40];
assign K8[9] = decrypt_int ? K[13] : K[6];
assign K8[10] = decrypt_int ? K[32] : K[25];
assign K8[11] = decrypt_int ? K[55] : K[48];
assign K8[12] = decrypt_int ? K[3] : K[53];
assign K8[13] = decrypt_int ? K[12] : K[5];
assign K8[14] = decrypt_int ? K[41] : K[34];
assign K8[15] = decrypt_int ? K[17] : K[10];
assign K8[16] = decrypt_int ? K[18] : K[11];
assign K8[17] = decrypt_int ? K[33] : K[26];
assign K8[18] = decrypt_int ? K[46] : K[39];
assign K8[19] = decrypt_int ? K[20] : K[13];
assign K8[20] = decrypt_int ? K[39] : K[32];
assign K8[21] = decrypt_int ? K[40] : K[33];
assign K8[22] = decrypt_int ? K[48] : K[41];
assign K8[23] = decrypt_int ? K[24] : K[17];
assign K8[24] = decrypt_int ? K[4] : K[54];
assign K8[25] = decrypt_int ? K[52] : K[45];
assign K8[26] = decrypt_int ? K[15] : K[8];
assign K8[27] = decrypt_int ? K[9] : K[2];
assign K8[28] = decrypt_int ? K[51] : K[44];
assign K8[29] = decrypt_int ? K[35] : K[28];
assign K8[30] = decrypt_int ? K[36] : K[29];
assign K8[31] = decrypt_int ? K[2] : K[50];
assign K8[32] = decrypt_int ? K[45] : K[38];
assign K8[33] = decrypt_int ? K[8] : K[1];
assign K8[34] = decrypt_int ? K[21] : K[14];
assign K8[35] = decrypt_int ? K[23] : K[16];
assign K8[36] = decrypt_int ? K[42] : K[35];
assign K8[37] = decrypt_int ? K[14] : K[7];
assign K8[38] = decrypt_int ? K[49] : K[42];
assign K8[39] = decrypt_int ? K[38] : K[31];
assign K8[40] = decrypt_int ? K[43] : K[36];
assign K8[41] = decrypt_int ? K[30] : K[23];
assign K8[42] = decrypt_int ? K[22] : K[15];
assign K8[43] = decrypt_int ? K[28] : K[21];
assign K8[44] = decrypt_int ? K[0] : K[52];
assign K8[45] = decrypt_int ? K[1] : K[49];
assign K8[46] = decrypt_int ? K[44] : K[37];
assign K8[47] = decrypt_int ? K[50] : K[43];
assign K8[48] = decrypt_int ? K[16] : K[9];
assign K7[1] = decrypt_int ? K[20] : K[10];
assign K7[2] = decrypt_int ? K[41] : K[6];
assign K7[3] = decrypt_int ? K[24] : K[46];
assign K7[4] = decrypt_int ? K[33] : K[55];
assign K7[5] = decrypt_int ? K[11] : K[33];
assign K7[6] = decrypt_int ? K[39] : K[4];
assign K7[7] = decrypt_int ? K[25] : K[47];
assign K7[8] = decrypt_int ? K[4] : K[26];
assign K7[9] = decrypt_int ? K[27] : K[17];
assign K7[10] = decrypt_int ? K[46] : K[11];
assign K7[11] = decrypt_int ? K[12] : K[34];
assign K7[12] = decrypt_int ? K[17] : K[39];
assign K7[13] = decrypt_int ? K[26] : K[48];
assign K7[14] = decrypt_int ? K[55] : K[20];
assign K7[15] = decrypt_int ? K[6] : K[53];
assign K7[16] = decrypt_int ? K[32] : K[54];
assign K7[17] = decrypt_int ? K[47] : K[12];
assign K7[18] = decrypt_int ? K[3] : K[25];
assign K7[19] = decrypt_int ? K[34] : K[24];
assign K7[20] = decrypt_int ? K[53] : K[18];
assign K7[21] = decrypt_int ? K[54] : K[19];
assign K7[22] = decrypt_int ? K[5] : K[27];
assign K7[23] = decrypt_int ? K[13] : K[3];
assign K7[24] = decrypt_int ? K[18] : K[40];
assign K7[25] = decrypt_int ? K[7] : K[31];
assign K7[26] = decrypt_int ? K[29] : K[49];
assign K7[27] = decrypt_int ? K[23] : K[43];
assign K7[28] = decrypt_int ? K[38] : K[30];
assign K7[29] = decrypt_int ? K[49] : K[14];
assign K7[30] = decrypt_int ? K[50] : K[15];
assign K7[31] = decrypt_int ? K[16] : K[36];
assign K7[32] = decrypt_int ? K[0] : K[51];
assign K7[33] = decrypt_int ? K[22] : K[42];
assign K7[34] = decrypt_int ? K[35] : K[0];
assign K7[35] = decrypt_int ? K[37] : K[2];
assign K7[36] = decrypt_int ? K[1] : K[21];
assign K7[37] = decrypt_int ? K[28] : K[52];
assign K7[38] = decrypt_int ? K[8] : K[28];
assign K7[39] = decrypt_int ? K[52] : K[44];
assign K7[40] = decrypt_int ? K[2] : K[22];
assign K7[41] = decrypt_int ? K[44] : K[9];
assign K7[42] = decrypt_int ? K[36] : K[1];
assign K7[43] = decrypt_int ? K[42] : K[7];
assign K7[44] = decrypt_int ? K[14] : K[38];
assign K7[45] = decrypt_int ? K[15] : K[35];
assign K7[46] = decrypt_int ? K[31] : K[23];
assign K7[47] = decrypt_int ? K[9] : K[29];
assign K7[48] = decrypt_int ? K[30] : K[50];
assign K6[1] = decrypt_int ? K[34] : K[53];
assign K6[2] = decrypt_int ? K[55] : K[17];
assign K6[3] = decrypt_int ? K[13] : K[32];
assign K6[4] = decrypt_int ? K[47] : K[41];
assign K6[5] = decrypt_int ? K[25] : K[19];
assign K6[6] = decrypt_int ? K[53] : K[47];
assign K6[7] = decrypt_int ? K[39] : K[33];
assign K6[8] = decrypt_int ? K[18] : K[12];
assign K6[9] = decrypt_int ? K[41] : K[3];
assign K6[10] = decrypt_int ? K[3] : K[54];
assign K6[11] = decrypt_int ? K[26] : K[20];
assign K6[12] = decrypt_int ? K[6] : K[25];
assign K6[13] = decrypt_int ? K[40] : K[34];
assign K6[14] = decrypt_int ? K[12] : K[6];
assign K6[15] = decrypt_int ? K[20] : K[39];
assign K6[16] = decrypt_int ? K[46] : K[40];
assign K6[17] = decrypt_int ? K[4] : K[55];
assign K6[18] = decrypt_int ? K[17] : K[11];
assign K6[19] = decrypt_int ? K[48] : K[10];
assign K6[20] = decrypt_int ? K[10] : K[4];
assign K6[21] = decrypt_int ? K[11] : K[5];
assign K6[22] = decrypt_int ? K[19] : K[13];
assign K6[23] = decrypt_int ? K[27] : K[46];
assign K6[24] = decrypt_int ? K[32] : K[26];
assign K6[25] = decrypt_int ? K[21] : K[44];
assign K6[26] = decrypt_int ? K[43] : K[35];
assign K6[27] = decrypt_int ? K[37] : K[29];
assign K6[28] = decrypt_int ? K[52] : K[16];
assign K6[29] = decrypt_int ? K[8] : K[0];
assign K6[30] = decrypt_int ? K[9] : K[1];
assign K6[31] = decrypt_int ? K[30] : K[22];
assign K6[32] = decrypt_int ? K[14] : K[37];
assign K6[33] = decrypt_int ? K[36] : K[28];
assign K6[34] = decrypt_int ? K[49] : K[45];
assign K6[35] = decrypt_int ? K[51] : K[43];
assign K6[36] = decrypt_int ? K[15] : K[7];
assign K6[37] = decrypt_int ? K[42] : K[38];
assign K6[38] = decrypt_int ? K[22] : K[14];
assign K6[39] = decrypt_int ? K[7] : K[30];
assign K6[40] = decrypt_int ? K[16] : K[8];
assign K6[41] = decrypt_int ? K[31] : K[50];
assign K6[42] = decrypt_int ? K[50] : K[42];
assign K6[43] = decrypt_int ? K[1] : K[52];
assign K6[44] = decrypt_int ? K[28] : K[51];
assign K6[45] = decrypt_int ? K[29] : K[21];
assign K6[46] = decrypt_int ? K[45] : K[9];
assign K6[47] = decrypt_int ? K[23] : K[15];
assign K6[48] = decrypt_int ? K[44] : K[36];
assign K5[1] = decrypt_int ? K[48] : K[39];
assign K5[2] = decrypt_int ? K[12] : K[3];
assign K5[3] = decrypt_int ? K[27] : K[18];
assign K5[4] = decrypt_int ? K[4] : K[27];
assign K5[5] = decrypt_int ? K[39] : K[5];
assign K5[6] = decrypt_int ? K[10] : K[33];
assign K5[7] = decrypt_int ? K[53] : K[19];
assign K5[8] = decrypt_int ? K[32] : K[55];
assign K5[9] = decrypt_int ? K[55] : K[46];
assign K5[10] = decrypt_int ? K[17] : K[40];
assign K5[11] = decrypt_int ? K[40] : K[6];
assign K5[12] = decrypt_int ? K[20] : K[11];
assign K5[13] = decrypt_int ? K[54] : K[20];
assign K5[14] = decrypt_int ? K[26] : K[17];
assign K5[15] = decrypt_int ? K[34] : K[25];
assign K5[16] = decrypt_int ? K[3] : K[26];
assign K5[17] = decrypt_int ? K[18] : K[41];
assign K5[18] = decrypt_int ? K[6] : K[54];
assign K5[19] = decrypt_int ? K[5] : K[53];
assign K5[20] = decrypt_int ? K[24] : K[47];
assign K5[21] = decrypt_int ? K[25] : K[48];
assign K5[22] = decrypt_int ? K[33] : K[24];
assign K5[23] = decrypt_int ? K[41] : K[32];
assign K5[24] = decrypt_int ? K[46] : K[12];
assign K5[25] = decrypt_int ? K[35] : K[30];
assign K5[26] = decrypt_int ? K[2] : K[21];
assign K5[27] = decrypt_int ? K[51] : K[15];
assign K5[28] = decrypt_int ? K[7] : K[2];
assign K5[29] = decrypt_int ? K[22] : K[45];
assign K5[30] = decrypt_int ? K[23] : K[42];
assign K5[31] = decrypt_int ? K[44] : K[8];
assign K5[32] = decrypt_int ? K[28] : K[23];
assign K5[33] = decrypt_int ? K[50] : K[14];
assign K5[34] = decrypt_int ? K[8] : K[31];
assign K5[35] = decrypt_int ? K[38] : K[29];
assign K5[36] = decrypt_int ? K[29] : K[52];
assign K5[37] = decrypt_int ? K[1] : K[51];
assign K5[38] = decrypt_int ? K[36] : K[0];
assign K5[39] = decrypt_int ? K[21] : K[16];
assign K5[40] = decrypt_int ? K[30] : K[49];
assign K5[41] = decrypt_int ? K[45] : K[36];
assign K5[42] = decrypt_int ? K[9] : K[28];
assign K5[43] = decrypt_int ? K[15] : K[38];
assign K5[44] = decrypt_int ? K[42] : K[37];
assign K5[45] = decrypt_int ? K[43] : K[7];
assign K5[46] = decrypt_int ? K[0] : K[50];
assign K5[47] = decrypt_int ? K[37] : K[1];
assign K5[48] = decrypt_int ? K[31] : K[22];
assign K4[1] = decrypt_int ? K[5] : K[25];
assign K4[2] = decrypt_int ? K[26] : K[46];
assign K4[3] = decrypt_int ? K[41] : K[4];
assign K4[4] = decrypt_int ? K[18] : K[13];
assign K4[5] = decrypt_int ? K[53] : K[48];
assign K4[6] = decrypt_int ? K[24] : K[19];
assign K4[7] = decrypt_int ? K[10] : K[5];
assign K4[8] = decrypt_int ? K[46] : K[41];
assign K4[9] = decrypt_int ? K[12] : K[32];
assign K4[10] = decrypt_int ? K[6] : K[26];
assign K4[11] = decrypt_int ? K[54] : K[17];
assign K4[12] = decrypt_int ? K[34] : K[54];
assign K4[13] = decrypt_int ? K[11] : K[6];
assign K4[14] = decrypt_int ? K[40] : K[3];
assign K4[15] = decrypt_int ? K[48] : K[11];
assign K4[16] = decrypt_int ? K[17] : K[12];
assign K4[17] = decrypt_int ? K[32] : K[27];
assign K4[18] = decrypt_int ? K[20] : K[40];
assign K4[19] = decrypt_int ? K[19] : K[39];
assign K4[20] = decrypt_int ? K[13] : K[33];
assign K4[21] = decrypt_int ? K[39] : K[34];
assign K4[22] = decrypt_int ? K[47] : K[10];
assign K4[23] = decrypt_int ? K[55] : K[18];
assign K4[24] = decrypt_int ? K[3] : K[55];
assign K4[25] = decrypt_int ? K[49] : K[16];
assign K4[26] = decrypt_int ? K[16] : K[7];
assign K4[27] = decrypt_int ? K[38] : K[1];
assign K4[28] = decrypt_int ? K[21] : K[43];
assign K4[29] = decrypt_int ? K[36] : K[31];
assign K4[30] = decrypt_int ? K[37] : K[28];
assign K4[31] = decrypt_int ? K[31] : K[49];
assign K4[32] = decrypt_int ? K[42] : K[9];
assign K4[33] = decrypt_int ? K[9] : K[0];
assign K4[34] = decrypt_int ? K[22] : K[44];
assign K4[35] = decrypt_int ? K[52] : K[15];
assign K4[36] = decrypt_int ? K[43] : K[38];
assign K4[37] = decrypt_int ? K[15] : K[37];
assign K4[38] = decrypt_int ? K[50] : K[45];
assign K4[39] = decrypt_int ? K[35] : K[2];
assign K4[40] = decrypt_int ? K[44] : K[35];
assign K4[41] = decrypt_int ? K[0] : K[22];
assign K4[42] = decrypt_int ? K[23] : K[14];
assign K4[43] = decrypt_int ? K[29] : K[51];
assign K4[44] = decrypt_int ? K[1] : K[23];
assign K4[45] = decrypt_int ? K[2] : K[52];
assign K4[46] = decrypt_int ? K[14] : K[36];
assign K4[47] = decrypt_int ? K[51] : K[42];
assign K4[48] = decrypt_int ? K[45] : K[8];
assign K3[1] = decrypt_int ? K[19] : K[11];
assign K3[2] = decrypt_int ? K[40] : K[32];
assign K3[3] = decrypt_int ? K[55] : K[47];
assign K3[4] = decrypt_int ? K[32] : K[24];
assign K3[5] = decrypt_int ? K[10] : K[34];
assign K3[6] = decrypt_int ? K[13] : K[5];
assign K3[7] = decrypt_int ? K[24] : K[48];
assign K3[8] = decrypt_int ? K[3] : K[27];
assign K3[9] = decrypt_int ? K[26] : K[18];
assign K3[10] = decrypt_int ? K[20] : K[12];
assign K3[11] = decrypt_int ? K[11] : K[3];
assign K3[12] = decrypt_int ? K[48] : K[40];
assign K3[13] = decrypt_int ? K[25] : K[17];
assign K3[14] = decrypt_int ? K[54] : K[46];
assign K3[15] = decrypt_int ? K[5] : K[54];
assign K3[16] = decrypt_int ? K[6] : K[55];
assign K3[17] = decrypt_int ? K[46] : K[13];
assign K3[18] = decrypt_int ? K[34] : K[26];
assign K3[19] = decrypt_int ? K[33] : K[25];
assign K3[20] = decrypt_int ? K[27] : K[19];
assign K3[21] = decrypt_int ? K[53] : K[20];
assign K3[22] = decrypt_int ? K[4] : K[53];
assign K3[23] = decrypt_int ? K[12] : K[4];
assign K3[24] = decrypt_int ? K[17] : K[41];
assign K3[25] = decrypt_int ? K[8] : K[2];
assign K3[26] = decrypt_int ? K[30] : K[52];
assign K3[27] = decrypt_int ? K[52] : K[42];
assign K3[28] = decrypt_int ? K[35] : K[29];
assign K3[29] = decrypt_int ? K[50] : K[44];
assign K3[30] = decrypt_int ? K[51] : K[14];
assign K3[31] = decrypt_int ? K[45] : K[35];
assign K3[32] = decrypt_int ? K[1] : K[50];
assign K3[33] = decrypt_int ? K[23] : K[45];
assign K3[34] = decrypt_int ? K[36] : K[30];
assign K3[35] = decrypt_int ? K[7] : K[1];
assign K3[36] = decrypt_int ? K[2] : K[51];
assign K3[37] = decrypt_int ? K[29] : K[23];
assign K3[38] = decrypt_int ? K[9] : K[31];
assign K3[39] = decrypt_int ? K[49] : K[43];
assign K3[40] = decrypt_int ? K[31] : K[21];
assign K3[41] = decrypt_int ? K[14] : K[8];
assign K3[42] = decrypt_int ? K[37] : K[0];
assign K3[43] = decrypt_int ? K[43] : K[37];
assign K3[44] = decrypt_int ? K[15] : K[9];
assign K3[45] = decrypt_int ? K[16] : K[38];
assign K3[46] = decrypt_int ? K[28] : K[22];
assign K3[47] = decrypt_int ? K[38] : K[28];
assign K3[48] = decrypt_int ? K[0] : K[49];
assign K2[1] = decrypt_int ? K[33] : K[54];
assign K2[2] = decrypt_int ? K[54] : K[18];
assign K2[3] = decrypt_int ? K[12] : K[33];
assign K2[4] = decrypt_int ? K[46] : K[10];
assign K2[5] = decrypt_int ? K[24] : K[20];
assign K2[6] = decrypt_int ? K[27] : K[48];
assign K2[7] = decrypt_int ? K[13] : K[34];
assign K2[8] = decrypt_int ? K[17] : K[13];
assign K2[9] = decrypt_int ? K[40] : K[4];
assign K2[10] = decrypt_int ? K[34] : K[55];
assign K2[11] = decrypt_int ? K[25] : K[46];
assign K2[12] = decrypt_int ? K[5] : K[26];
assign K2[13] = decrypt_int ? K[39] : K[3];
assign K2[14] = decrypt_int ? K[11] : K[32];
assign K2[15] = decrypt_int ? K[19] : K[40];
assign K2[16] = decrypt_int ? K[20] : K[41];
assign K2[17] = decrypt_int ? K[3] : K[24];
assign K2[18] = decrypt_int ? K[48] : K[12];
assign K2[19] = decrypt_int ? K[47] : K[11];
assign K2[20] = decrypt_int ? K[41] : K[5];
assign K2[21] = decrypt_int ? K[10] : K[6];
assign K2[22] = decrypt_int ? K[18] : K[39];
assign K2[23] = decrypt_int ? K[26] : K[47];
assign K2[24] = decrypt_int ? K[6] : K[27];
assign K2[25] = decrypt_int ? K[22] : K[43];
assign K2[26] = decrypt_int ? K[44] : K[38];
assign K2[27] = decrypt_int ? K[7] : K[28];
assign K2[28] = decrypt_int ? K[49] : K[15];
assign K2[29] = decrypt_int ? K[9] : K[30];
assign K2[30] = decrypt_int ? K[38] : K[0];
assign K2[31] = decrypt_int ? K[0] : K[21];
assign K2[32] = decrypt_int ? K[15] : K[36];
assign K2[33] = decrypt_int ? K[37] : K[31];
assign K2[34] = decrypt_int ? K[50] : K[16];
assign K2[35] = decrypt_int ? K[21] : K[42];
assign K2[36] = decrypt_int ? K[16] : K[37];
assign K2[37] = decrypt_int ? K[43] : K[9];
assign K2[38] = decrypt_int ? K[23] : K[44];
assign K2[39] = decrypt_int ? K[8] : K[29];
assign K2[40] = decrypt_int ? K[45] : K[7];
assign K2[41] = decrypt_int ? K[28] : K[49];
assign K2[42] = decrypt_int ? K[51] : K[45];
assign K2[43] = decrypt_int ? K[2] : K[23];
assign K2[44] = decrypt_int ? K[29] : K[50];
assign K2[45] = decrypt_int ? K[30] : K[51];
assign K2[46] = decrypt_int ? K[42] : K[8];
assign K2[47] = decrypt_int ? K[52] : K[14];
assign K2[48] = decrypt_int ? K[14] : K[35];
assign K1[1] = decrypt_int ? K[40] : K[47];
assign K1[2] = decrypt_int ? K[4] : K[11];
assign K1[3] = decrypt_int ? K[19] : K[26];
assign K1[4] = decrypt_int ? K[53] : K[3];
assign K1[5] = decrypt_int ? K[6] : K[13];
assign K1[6] = decrypt_int ? K[34] : K[41];
assign K1[7] = decrypt_int ? K[20] : K[27];
assign K1[8] = decrypt_int ? K[24] : K[6];
assign K1[9] = decrypt_int ? K[47] : K[54];
assign K1[10] = decrypt_int ? K[41] : K[48];
assign K1[11] = decrypt_int ? K[32] : K[39];
assign K1[12] = decrypt_int ? K[12] : K[19];
assign K1[13] = decrypt_int ? K[46] : K[53];
assign K1[14] = decrypt_int ? K[18] : K[25];
assign K1[15] = decrypt_int ? K[26] : K[33];
assign K1[16] = decrypt_int ? K[27] : K[34];
assign K1[17] = decrypt_int ? K[10] : K[17];
assign K1[18] = decrypt_int ? K[55] : K[5];
assign K1[19] = decrypt_int ? K[54] : K[4];
assign K1[20] = decrypt_int ? K[48] : K[55];
assign K1[21] = decrypt_int ? K[17] : K[24];
assign K1[22] = decrypt_int ? K[25] : K[32];
assign K1[23] = decrypt_int ? K[33] : K[40];
assign K1[24] = decrypt_int ? K[13] : K[20];
assign K1[25] = decrypt_int ? K[29] : K[36];
assign K1[26] = decrypt_int ? K[51] : K[31];
assign K1[27] = decrypt_int ? K[14] : K[21];
assign K1[28] = decrypt_int ? K[1] : K[8];
assign K1[29] = decrypt_int ? K[16] : K[23];
assign K1[30] = decrypt_int ? K[45] : K[52];
assign K1[31] = decrypt_int ? K[7] : K[14];
assign K1[32] = decrypt_int ? K[22] : K[29];
assign K1[33] = decrypt_int ? K[44] : K[51];
assign K1[34] = decrypt_int ? K[2] : K[9];
assign K1[35] = decrypt_int ? K[28] : K[35];
assign K1[36] = decrypt_int ? K[23] : K[30];
assign K1[37] = decrypt_int ? K[50] : K[2];
assign K1[38] = decrypt_int ? K[30] : K[37];
assign K1[39] = decrypt_int ? K[15] : K[22];
assign K1[40] = decrypt_int ? K[52] : K[0];
assign K1[41] = decrypt_int ? K[35] : K[42];
assign K1[42] = decrypt_int ? K[31] : K[38];
assign K1[43] = decrypt_int ? K[9] : K[16];
assign K1[44] = decrypt_int ? K[36] : K[43];
assign K1[45] = decrypt_int ? K[37] : K[44];
assign K1[46] = decrypt_int ? K[49] : K[1];
assign K1[47] = decrypt_int ? K[0] : K[7];
assign K1[48] = decrypt_int ? K[21] : K[28];
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module sbox1(addr, dout);
/* verilator lint_off LITENDIAN */
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
/* verilator lint_on LITENDIAN */
always @(addr)
begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0:
dout = 14;
1:
dout = 4;
2:
dout = 13;
3:
dout = 1;
4:
dout = 2;
5:
dout = 15;
6:
dout = 11;
7:
dout = 8;
8:
dout = 3;
9:
dout = 10;
10:
dout = 6;
11:
dout = 12;
12:
dout = 5;
13:
dout = 9;
14:
dout = 0;
15:
dout = 7;
16:
dout = 0;
17:
dout = 15;
18:
dout = 7;
19:
dout = 4;
20:
dout = 14;
21:
dout = 2;
22:
dout = 13;
23:
dout = 1;
24:
dout = 10;
25:
dout = 6;
26:
dout = 12;
27:
dout = 11;
28:
dout = 9;
29:
dout = 5;
30:
dout = 3;
31:
dout = 8;
32:
dout = 4;
33:
dout = 1;
34:
dout = 14;
35:
dout = 8;
36:
dout = 13;
37:
dout = 6;
38:
dout = 2;
39:
dout = 11;
40:
dout = 15;
41:
dout = 12;
42:
dout = 9;
43:
dout = 7;
44:
dout = 3;
45:
dout = 10;
46:
dout = 5;
47:
dout = 0;
48:
dout = 15;
49:
dout = 12;
50:
dout = 8;
51:
dout = 2;
52:
dout = 4;
53:
dout = 9;
54:
dout = 1;
55:
dout = 7;
56:
dout = 5;
57:
dout = 11;
58:
dout = 3;
59:
dout = 14;
60:
dout = 10;
61:
dout = 0;
62:
dout = 6;
63:
dout = 13;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module sbox2(addr, dout);
/* verilator lint_off LITENDIAN */
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
/* verilator lint_on LITENDIAN */
always @(addr)
begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0:
dout = 15;
1:
dout = 1;
2:
dout = 8;
3:
dout = 14;
4:
dout = 6;
5:
dout = 11;
6:
dout = 3;
7:
dout = 4;
8:
dout = 9;
9:
dout = 7;
10:
dout = 2;
11:
dout = 13;
12:
dout = 12;
13:
dout = 0;
14:
dout = 5;
15:
dout = 10;
16:
dout = 3;
17:
dout = 13;
18:
dout = 4;
19:
dout = 7;
20:
dout = 15;
21:
dout = 2;
22:
dout = 8;
23:
dout = 14;
24:
dout = 12;
25:
dout = 0;
26:
dout = 1;
27:
dout = 10;
28:
dout = 6;
29:
dout = 9;
30:
dout = 11;
31:
dout = 5;
32:
dout = 0;
33:
dout = 14;
34:
dout = 7;
35:
dout = 11;
36:
dout = 10;
37:
dout = 4;
38:
dout = 13;
39:
dout = 1;
40:
dout = 5;
41:
dout = 8;
42:
dout = 12;
43:
dout = 6;
44:
dout = 9;
45:
dout = 3;
46:
dout = 2;
47:
dout = 15;
48:
dout = 13;
49:
dout = 8;
50:
dout = 10;
51:
dout = 1;
52:
dout = 3;
53:
dout = 15;
54:
dout = 4;
55:
dout = 2;
56:
dout = 11;
57:
dout = 6;
58:
dout = 7;
59:
dout = 12;
60:
dout = 0;
61:
dout = 5;
62:
dout = 14;
63:
dout = 9;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module sbox3(addr, dout);
/* verilator lint_off LITENDIAN */
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
/* verilator lint_on LITENDIAN */
always @(addr)
begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0:
dout = 10;
1:
dout = 0;
2:
dout = 9;
3:
dout = 14;
4:
dout = 6;
5:
dout = 3;
6:
dout = 15;
7:
dout = 5;
8:
dout = 1;
9:
dout = 13;
10:
dout = 12;
11:
dout = 7;
12:
dout = 11;
13:
dout = 4;
14:
dout = 2;
15:
dout = 8;
16:
dout = 13;
17:
dout = 7;
18:
dout = 0;
19:
dout = 9;
20:
dout = 3;
21:
dout = 4;
22:
dout = 6;
23:
dout = 10;
24:
dout = 2;
25:
dout = 8;
26:
dout = 5;
27:
dout = 14;
28:
dout = 12;
29:
dout = 11;
30:
dout = 15;
31:
dout = 1;
32:
dout = 13;
33:
dout = 6;
34:
dout = 4;
35:
dout = 9;
36:
dout = 8;
37:
dout = 15;
38:
dout = 3;
39:
dout = 0;
40:
dout = 11;
41:
dout = 1;
42:
dout = 2;
43:
dout = 12;
44:
dout = 5;
45:
dout = 10;
46:
dout = 14;
47:
dout = 7;
48:
dout = 1;
49:
dout = 10;
50:
dout = 13;
51:
dout = 0;
52:
dout = 6;
53:
dout = 9;
54:
dout = 8;
55:
dout = 7;
56:
dout = 4;
57:
dout = 15;
58:
dout = 14;
59:
dout = 3;
60:
dout = 11;
61:
dout = 5;
62:
dout = 2;
63:
dout = 12;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module sbox4(addr, dout);
/* verilator lint_off LITENDIAN */
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
/* verilator lint_on LITENDIAN */
always @(addr)
begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0:
dout = 7;
1:
dout = 13;
2:
dout = 14;
3:
dout = 3;
4:
dout = 0;
5:
dout = 6;
6:
dout = 9;
7:
dout = 10;
8:
dout = 1;
9:
dout = 2;
10:
dout = 8;
11:
dout = 5;
12:
dout = 11;
13:
dout = 12;
14:
dout = 4;
15:
dout = 15;
16:
dout = 13;
17:
dout = 8;
18:
dout = 11;
19:
dout = 5;
20:
dout = 6;
21:
dout = 15;
22:
dout = 0;
23:
dout = 3;
24:
dout = 4;
25:
dout = 7;
26:
dout = 2;
27:
dout = 12;
28:
dout = 1;
29:
dout = 10;
30:
dout = 14;
31:
dout = 9;
32:
dout = 10;
33:
dout = 6;
34:
dout = 9;
35:
dout = 0;
36:
dout = 12;
37:
dout = 11;
38:
dout = 7;
39:
dout = 13;
40:
dout = 15;
41:
dout = 1;
42:
dout = 3;
43:
dout = 14;
44:
dout = 5;
45:
dout = 2;
46:
dout = 8;
47:
dout = 4;
48:
dout = 3;
49:
dout = 15;
50:
dout = 0;
51:
dout = 6;
52:
dout = 10;
53:
dout = 1;
54:
dout = 13;
55:
dout = 8;
56:
dout = 9;
57:
dout = 4;
58:
dout = 5;
59:
dout = 11;
60:
dout = 12;
61:
dout = 7;
62:
dout = 2;
63:
dout = 14;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module sbox5(addr, dout);
/* verilator lint_off LITENDIAN */
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
/* verilator lint_on LITENDIAN */
always @(addr)
begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0:
dout = 2;
1:
dout = 12;
2:
dout = 4;
3:
dout = 1;
4:
dout = 7;
5:
dout = 10;
6:
dout = 11;
7:
dout = 6;
8:
dout = 8;
9:
dout = 5;
10:
dout = 3;
11:
dout = 15;
12:
dout = 13;
13:
dout = 0;
14:
dout = 14;
15:
dout = 9;
16:
dout = 14;
17:
dout = 11;
18:
dout = 2;
19:
dout = 12;
20:
dout = 4;
21:
dout = 7;
22:
dout = 13;
23:
dout = 1;
24:
dout = 5;
25:
dout = 0;
26:
dout = 15;
27:
dout = 10;
28:
dout = 3;
29:
dout = 9;
30:
dout = 8;
31:
dout = 6;
32:
dout = 4;
33:
dout = 2;
34:
dout = 1;
35:
dout = 11;
36:
dout = 10;
37:
dout = 13;
38:
dout = 7;
39:
dout = 8;
40:
dout = 15;
41:
dout = 9;
42:
dout = 12;
43:
dout = 5;
44:
dout = 6;
45:
dout = 3;
46:
dout = 0;
47:
dout = 14;
48:
dout = 11;
49:
dout = 8;
50:
dout = 12;
51:
dout = 7;
52:
dout = 1;
53:
dout = 14;
54:
dout = 2;
55:
dout = 13;
56:
dout = 6;
57:
dout = 15;
58:
dout = 0;
59:
dout = 9;
60:
dout = 10;
61:
dout = 4;
62:
dout = 5;
63:
dout = 3;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module sbox6(addr, dout);
/* verilator lint_off LITENDIAN */
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
/* verilator lint_on LITENDIAN */
always @(addr)
begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0:
dout = 12;
1:
dout = 1;
2:
dout = 10;
3:
dout = 15;
4:
dout = 9;
5:
dout = 2;
6:
dout = 6;
7:
dout = 8;
8:
dout = 0;
9:
dout = 13;
10:
dout = 3;
11:
dout = 4;
12:
dout = 14;
13:
dout = 7;
14:
dout = 5;
15:
dout = 11;
16:
dout = 10;
17:
dout = 15;
18:
dout = 4;
19:
dout = 2;
20:
dout = 7;
21:
dout = 12;
22:
dout = 9;
23:
dout = 5;
24:
dout = 6;
25:
dout = 1;
26:
dout = 13;
27:
dout = 14;
28:
dout = 0;
29:
dout = 11;
30:
dout = 3;
31:
dout = 8;
32:
dout = 9;
33:
dout = 14;
34:
dout = 15;
35:
dout = 5;
36:
dout = 2;
37:
dout = 8;
38:
dout = 12;
39:
dout = 3;
40:
dout = 7;
41:
dout = 0;
42:
dout = 4;
43:
dout = 10;
44:
dout = 1;
45:
dout = 13;
46:
dout = 11;
47:
dout = 6;
48:
dout = 4;
49:
dout = 3;
50:
dout = 2;
51:
dout = 12;
52:
dout = 9;
53:
dout = 5;
54:
dout = 15;
55:
dout = 10;
56:
dout = 11;
57:
dout = 14;
58:
dout = 1;
59:
dout = 7;
60:
dout = 6;
61:
dout = 0;
62:
dout = 8;
63:
dout = 13;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module sbox7(addr, dout);
/* verilator lint_off LITENDIAN */
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
/* verilator lint_on LITENDIAN */
always @(addr)
begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0:
dout = 4;
1:
dout = 11;
2:
dout = 2;
3:
dout = 14;
4:
dout = 15;
5:
dout = 0;
6:
dout = 8;
7:
dout = 13;
8:
dout = 3;
9:
dout = 12;
10:
dout = 9;
11:
dout = 7;
12:
dout = 5;
13:
dout = 10;
14:
dout = 6;
15:
dout = 1;
16:
dout = 13;
17:
dout = 0;
18:
dout = 11;
19:
dout = 7;
20:
dout = 4;
21:
dout = 9;
22:
dout = 1;
23:
dout = 10;
24:
dout = 14;
25:
dout = 3;
26:
dout = 5;
27:
dout = 12;
28:
dout = 2;
29:
dout = 15;
30:
dout = 8;
31:
dout = 6;
32:
dout = 1;
33:
dout = 4;
34:
dout = 11;
35:
dout = 13;
36:
dout = 12;
37:
dout = 3;
38:
dout = 7;
39:
dout = 14;
40:
dout = 10;
41:
dout = 15;
42:
dout = 6;
43:
dout = 8;
44:
dout = 0;
45:
dout = 5;
46:
dout = 9;
47:
dout = 2;
48:
dout = 6;
49:
dout = 11;
50:
dout = 13;
51:
dout = 8;
52:
dout = 1;
53:
dout = 4;
54:
dout = 10;
55:
dout = 7;
56:
dout = 9;
57:
dout = 5;
58:
dout = 0;
59:
dout = 15;
60:
dout = 14;
61:
dout = 2;
62:
dout = 3;
63:
dout = 12;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module sbox8(addr, dout);
/* verilator lint_off LITENDIAN */
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
/* verilator lint_on LITENDIAN */
always @(addr)
begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0:
dout = 13;
1:
dout = 2;
2:
dout = 8;
3:
dout = 4;
4:
dout = 6;
5:
dout = 15;
6:
dout = 11;
7:
dout = 1;
8:
dout = 10;
9:
dout = 9;
10:
dout = 3;
11:
dout = 14;
12:
dout = 5;
13:
dout = 0;
14:
dout = 12;
15:
dout = 7;
16:
dout = 1;
17:
dout = 15;
18:
dout = 13;
19:
dout = 8;
20:
dout = 10;
21:
dout = 3;
22:
dout = 7;
23:
dout = 4;
24:
dout = 12;
25:
dout = 5;
26:
dout = 6;
27:
dout = 11;
28:
dout = 0;
29:
dout = 14;
30:
dout = 9;
31:
dout = 2;
32:
dout = 7;
33:
dout = 11;
34:
dout = 4;
35:
dout = 1;
36:
dout = 9;
37:
dout = 12;
38:
dout = 14;
39:
dout = 2;
40:
dout = 0;
41:
dout = 6;
42:
dout = 10;
43:
dout = 13;
44:
dout = 15;
45:
dout = 3;
46:
dout = 5;
47:
dout = 8;
48:
dout = 2;
49:
dout = 1;
50:
dout = 14;
51:
dout = 7;
52:
dout = 4;
53:
dout = 10;
54:
dout = 8;
55:
dout = 13;
56:
dout = 15;
57:
dout = 12;
58:
dout = 9;
59:
dout = 0;
60:
dout = 3;
61:
dout = 5;
62:
dout = 6;
63:
dout = 11;
endcase
end
endmodule
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : md5_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-MD5 core
//
module md5_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg startHash, startHash_r;
reg [31:0] data [15:0];
reg message_reset, message_reset_r;
wire [511:0] bigData = {data[0], data[1], data[2], data[3], data[4], data[5], data[6], data[7], data[8], data[9], data[10], data[11], data[12], data[13], data[14], data[15]};
wire [127:0] hash;
wire ready;
wire hashValid;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i)
begin
if(wb_rst_i)
begin
startHash <= 0;
startHash_r <= 0;
message_reset <= 0;
message_reset_r <= 0;
data[0] <= 0;
data[1] <= 0;
data[2] <= 0;
data[3] <= 0;
data[4] <= 0;
data[5] <= 0;
data[6] <= 0;
data[7] <= 0;
data[8] <= 0;
data[9] <= 0;
data[10] <= 0;
data[11] <= 0;
data[12] <= 0;
data[13] <= 0;
data[14] <= 0;
data[15] <= 0;
end
else begin
// Generate a registered versions of startHash and message_reset
startHash_r <= startHash;
message_reset_r <= message_reset;
// Perform a write
if(wb_stb_i & wb_we_i) begin
case(wb_adr_i[6:2])
0: startHash <= wb_dat_i[0];
1: data[15] <= wb_dat_i;
2: data[14] <= wb_dat_i;
3: data[13] <= wb_dat_i;
4: data[12] <= wb_dat_i;
5: data[11] <= wb_dat_i;
6: data[10] <= wb_dat_i;
7: data[9] <= wb_dat_i;
8: data[8] <= wb_dat_i;
9: data[7] <= wb_dat_i;
10: data[6] <= wb_dat_i;
11: data[5] <= wb_dat_i;
12: data[4] <= wb_dat_i;
13: data[3] <= wb_dat_i;
14: data[2] <= wb_dat_i;
15: data[1] <= wb_dat_i;
16: data[0] <= wb_dat_i;
22: message_reset <= wb_dat_i[0];
default:
;
endcase
end else begin // if(wb_stb_i & wb_we_i)
startHash <= 1'b0;
message_reset <= 1'b0;
end // end else
end // else
end // end always
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[6:2])
0: wb_dat_o = {31'b0, ready};
1: wb_dat_o = data[15];
2: wb_dat_o = data[14];
3: wb_dat_o = data[13];
4: wb_dat_o = data[12];
5: wb_dat_o = data[11];
6: wb_dat_o = data[10];
7: wb_dat_o = data[9];
8: wb_dat_o = data[8];
9: wb_dat_o = data[7];
10: wb_dat_o = data[6];
11: wb_dat_o = data[5];
12: wb_dat_o = data[4];
13: wb_dat_o = data[3];
14: wb_dat_o = data[2];
15: wb_dat_o = data[1];
16: wb_dat_o = data[0];
17: wb_dat_o = {31'b0, hashValid};
21: wb_dat_o = hash[127:96];
20: wb_dat_o = hash[95:64];
19: wb_dat_o = hash[63:32];
18: wb_dat_o = hash[31:0];
default:
wb_dat_o = 32'b0;
endcase
end
pancham pancham(
.clk(wb_clk_i),
.rst(wb_rst_i | (message_reset & ~message_reset_r)),
.msg_padded(bigData),
.msg_in_valid(startHash && ~startHash_r),
.msg_output(hash),
.msg_out_valid(hashValid),
.ready(ready)
);
endmodule
|
/*****************************************************************
Pancham is an MD5 compliant IP core for cryptographic
applications.
Copyright (C) 2003 Swapnajit Mittra, Project VeriPage
(Contact email: verilog_tutorial at hotmail.com
Website : http://www.angelfire.com/ca/verilog)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the
Free Software Foundation, Inc.
59 Temple Place, Suite 330
Boston, MA 02111-1307
USA
******************************************************************/
/*
* This is the main module that computes a 128-bit message
* digest from a maximum of 512-bit long input message using
* MD5 algorithm.
*
* Modified by Matthew Hicks (mdhicks@gmail.com)
* Input from 128-bit to 512-bit
* Hold valid outputs
* Carry over constants between encryptions
* Support for arbitrary size encryption
* Address some Verilator warnings
* Convert vector direction
*
*/
// ROUNDs
`define ROUND1 2'b00
`define ROUND2 2'b01
`define ROUND3 2'b10
`define ROUND4 2'b11
// T_i = 4294967296*abs(sin(i))
`define T_1 32'hd76aa478
`define T_2 32'he8c7b756
`define T_3 32'h242070db
`define T_4 32'hc1bdceee
`define T_5 32'hf57c0faf
`define T_6 32'h4787c62a
`define T_7 32'ha8304613
`define T_8 32'hfd469501
`define T_9 32'h698098d8
`define T_10 32'h8b44f7af
`define T_11 32'hffff5bb1
`define T_12 32'h895cd7be
`define T_13 32'h6b901122
`define T_14 32'hfd987193
`define T_15 32'ha679438e
`define T_16 32'h49b40821
`define T_17 32'hf61e2562
`define T_18 32'hc040b340
`define T_19 32'h265e5a51
`define T_20 32'he9b6c7aa
`define T_21 32'hd62f105d
`define T_22 32'h2441453
`define T_23 32'hd8a1e681
`define T_24 32'he7d3fbc8
`define T_25 32'h21e1cde6
`define T_26 32'hc33707d6
`define T_27 32'hf4d50d87
`define T_28 32'h455a14ed
`define T_29 32'ha9e3e905
`define T_30 32'hfcefa3f8
`define T_31 32'h676f02d9
`define T_32 32'h8d2a4c8a
`define T_33 32'hfffa3942
`define T_34 32'h8771f681
`define T_35 32'h6d9d6122
`define T_36 32'hfde5380c
`define T_37 32'ha4beea44
`define T_38 32'h4bdecfa9
`define T_39 32'hf6bb4b60
`define T_40 32'hbebfbc70
`define T_41 32'h289b7ec6
`define T_42 32'heaa127fa
`define T_43 32'hd4ef3085
`define T_44 32'h4881d05
`define T_45 32'hd9d4d039
`define T_46 32'he6db99e5
`define T_47 32'h1fa27cf8
`define T_48 32'hc4ac5665
`define T_49 32'hf4292244
`define T_50 32'h432aff97
`define T_51 32'hab9423a7
`define T_52 32'hfc93a039
`define T_53 32'h655b59c3
`define T_54 32'h8f0ccc92
`define T_55 32'hffeff47d
`define T_56 32'h85845dd1
`define T_57 32'h6fa87e4f
`define T_58 32'hfe2ce6e0
`define T_59 32'ha3014314
`define T_60 32'h4e0811a1
`define T_61 32'hf7537e82
`define T_62 32'hbd3af235
`define T_63 32'h2ad7d2bb
`define T_64 32'heb86d391
/* verilator lint_off UNOPTFLAT */
module pancham (
clk
, rst
, msg_padded
, msg_in_valid
, msg_output
, msg_out_valid
, ready
);
//--------------------------------
//
// Input/Output declarations
//
//--------------------------------
input clk; // input clock
input rst; // global rst
input [511:0] msg_padded; // input message, already padded
input msg_in_valid; // input message is valid, active high
output [127:0] msg_output; // output message, always 128 bit wide
output msg_out_valid; // if asserted, output message is valid
output ready; // the core is ready for an input message
//--------------------------------
//
// Variable declarations
//
//--------------------------------
// inputs
wire clk;
wire rst;
wire [511:0] msg_padded;
wire msg_in_valid;
// output
wire [127:0] msg_output;
reg msg_out_valid;
wire ready;
// scratch pads
reg [1:0] round;
reg [31:0] a;
reg [31:0] A;
reg [31:0] AA;
reg [31:0] next_A;
reg [31:0] b;
reg [31:0] B;
reg [31:0] BB;
reg [31:0] next_B;
reg [31:0] c;
reg [31:0] C;
reg [31:0] CC;
reg [31:0] next_C;
reg [31:0] d;
reg [31:0] D;
reg [31:0] DD;
reg [31:0] next_D;
reg [31:0] m;
reg [31:0] s;
reg [31:0] t;
reg [3:0] phase; // Counter to determine 16 phases within each round.
wire [31:0] next_a;
reg [7:0] current_state;
reg [7:0] next_state;
reg [8*11:1] ascii_state;
//--------------------------------
//
// Parameter definitions
//
//--------------------------------
parameter SALT_A = 32'h67452301;
parameter SALT_B = 32'hefcdab89;
parameter SALT_C = 32'h98badcfe;
parameter SALT_D = 32'h10325476;
parameter ONE = 72'h1;
parameter IDLE_BIT = 0;
parameter IDLE = ONE << IDLE_BIT;
parameter ROUND1_BIT = 1;
parameter ROUND1 = ONE << ROUND1_BIT;
parameter ROUND2_BIT = 2;
parameter ROUND2 = ONE << ROUND2_BIT;
parameter ROUND3_BIT = 3;
parameter ROUND3 = ONE << ROUND3_BIT;
parameter ROUND4_BIT = 4;
parameter ROUND4 = ONE << ROUND4_BIT;
parameter FINISH_OFF_BIT = 5;
parameter FINISH_OFF = ONE << FINISH_OFF_BIT;
parameter TURN_ARND_BIT = 6;
parameter TURN_ARND = ONE << TURN_ARND_BIT;
//--------------------------------
//
// Submodule instantiation
//
//--------------------------------
pancham_round ROUND (
.a (a )
, .b (b )
, .c (c )
, .d (d )
, .m (m )
, .s (s )
, .t (t )
, .round (round)
, .next_a (next_a)
);
wire [31:0] m0 = msg_padded[31:0];
wire [31:0] m1 = msg_padded[63:32];
wire [31:0] m2 = msg_padded[95:64];
wire [31:0] m3 = msg_padded[127:96];
wire [31:0] m4 = msg_padded[159:128];
wire [31:0] m5 = msg_padded[191:160];
wire [31:0] m6 = msg_padded[223:192];
wire [31:0] m7 = msg_padded[255:224];
wire [31:0] m8 = msg_padded[287:256];
wire [31:0] m9 = msg_padded[319:288];
wire [31:0] m10 = msg_padded[351:320];
wire [31:0] m11 = msg_padded[383:352];
wire [31:0] m12 = msg_padded[415:384];
wire [31:0] m13 = msg_padded[447:416];
wire [31:0] m14 = msg_padded[479:448];
wire [31:0] m15 = msg_padded[511:480];
//--------------------------------
//
// Actual code starts here
//
//--------------------------------
always @(current_state
or msg_in_valid
or A
or B
or C
or D
or phase
or msg_padded
or next_a
or AA
or BB
or CC
or DD
)
begin // {
round = `ROUND1;
next_A = A;
next_B = B;
next_C = C;
next_D = D;
a = 32'h0;
b = 32'h0;
c = 32'h0;
d = 32'h0;
m = 32'h0;
s = 32'h0;
t = 32'h0;
next_state = current_state;
case (1'b1) // synopsys full_case parallel_case
current_state[IDLE_BIT]:
begin // {
// synopsys translate_off
ascii_state = "IDLE";
// synopsys translate_on
if (msg_in_valid)
next_state = ROUND1[7:0];
end // }
//----------------------------------------------------------------
//--------------------------- ROUND 1 ----------------------------
//----------------------------------------------------------------
current_state[ROUND1_BIT]:
begin // {
// synopsys translate_off
ascii_state = "ROUND1";
// synopsys translate_on
round = `ROUND1;
case (phase)
4'b0000:
begin
a=A;
b=B;
c=C;
d=D;
m=m0;
s=32'd07;
t= `T_1;
next_A=next_a;
end
4'b0001:
begin
a=D;
b=A;
c=B;
d=C;
m=m1;
s=32'd12;
t= `T_2;
next_D=next_a;
end
4'b0010:
begin
a=C;
b=D;
c=A;
d=B;
m=m2;
s=32'd17;
t= `T_3;
next_C=next_a;
end
4'b0011:
begin
a=B;
b=C;
c=D;
d=A;
m=m3;
s=32'd22;
t= `T_4;
next_B=next_a;
end
4'b0100:
begin
a=A;
b=B;
c=C;
d=D;
m=m4;
s=32'd07;
t= `T_5;
next_A=next_a;
end
4'b0101:
begin
a=D;
b=A;
c=B;
d=C;
m=m5;
s=32'd12;
t= `T_6;
next_D=next_a;
end
4'b0110:
begin
a=C;
b=D;
c=A;
d=B;
m=m6;
s=32'd17;
t= `T_7;
next_C=next_a;
end
4'b0111:
begin
a=B;
b=C;
c=D;
d=A;
m=m7;
s=32'd22;
t= `T_8;
next_B=next_a;
end
4'b1000:
begin
a=A;
b=B;
c=C;
d=D;
m=m8;
s=32'd07;
t= `T_9;
next_A=next_a;
end
4'b1001:
begin
a=D;
b=A;
c=B;
d=C;
m=m9;
s=32'd12;
t=`T_10;
next_D=next_a;
end
4'b1010:
begin
a=C;
b=D;
c=A;
d=B;
m=m10;
s=32'd17;
t=`T_11;
next_C=next_a;
end
4'b1011:
begin
a=B;
b=C;
c=D;
d=A;
m=m11;
s=32'd22;
t=`T_12;
next_B=next_a;
end
4'b1100:
begin
a=A;
b=B;
c=C;
d=D;
m=m12;
s=32'd7;
t=`T_13;
next_A=next_a;
end
4'b1101:
begin
a=D;
b=A;
c=B;
d=C;
m=m13;
s=32'd12;
t=`T_14;
next_D=next_a;
end
4'b1110:
begin
a=C;
b=D;
c=A;
d=B;
m=m14;
s=32'd17;
t=`T_15;
next_C=next_a;
end
4'b1111:
begin
a=B;
b=C;
c=D;
d=A;
m=m15;
s=32'd22;
t=`T_16;
next_B=next_a;
end
endcase
if (phase == 4'b1111)
next_state = ROUND2[7:0];
end // }
//----------------------------------------------------------------
//--------------------------- ROUND 2 ----------------------------
//----------------------------------------------------------------
current_state[ROUND2_BIT]:
begin // {
// synopsys translate_off
ascii_state = "ROUND2";
// synopsys translate_on
round = `ROUND2;
case (phase)
4'b0000:
begin
a=A;
b=B;
c=C;
d=D;
m=m1;
s=32'd05;
t=`T_17;
next_A=next_a;
end
4'b0001:
begin
a=D;
b=A;
c=B;
d=C;
m=m6;
s=32'd09;
t=`T_18;
next_D=next_a;
end
4'b0010:
begin
a=C;
b=D;
c=A;
d=B;
m=m11;
s=32'd14;
t=`T_19;
next_C=next_a;
end
4'b0011:
begin
a=B;
b=C;
c=D;
d=A;
m=m0;
s=32'd20;
t=`T_20;
next_B=next_a;
end
4'b0100:
begin
a=A;
b=B;
c=C;
d=D;
m=m5;
s=32'd05;
t=`T_21;
next_A=next_a;
end
4'b0101:
begin
a=D;
b=A;
c=B;
d=C;
m=m10;
s=32'd09;
t=`T_22;
next_D=next_a;
end
4'b0110:
begin
a=C;
b=D;
c=A;
d=B;
m=m15;
s=32'd14;
t=`T_23;
next_C=next_a;
end
4'b0111:
begin
a=B;
b=C;
c=D;
d=A;
m=m4;
s=32'd20;
t=`T_24;
next_B=next_a;
end
4'b1000:
begin
a=A;
b=B;
c=C;
d=D;
m=m9;
s=32'd05;
t=`T_25;
next_A=next_a;
end
4'b1001:
begin
a=D;
b=A;
c=B;
d=C;
m=m14;
s=32'd9;
t=`T_26;
next_D=next_a;
end
4'b1010:
begin
a=C;
b=D;
c=A;
d=B;
m=m3;
s=32'd14;
t=`T_27;
next_C=next_a;
end
4'b1011:
begin
a=B;
b=C;
c=D;
d=A;
m=m8;
s=32'd20;
t=`T_28;
next_B=next_a;
end
4'b1100:
begin
a=A;
b=B;
c=C;
d=D;
m=m13;
s=32'd05;
t=`T_29;
next_A=next_a;
end
4'b1101:
begin
a=D;
b=A;
c=B;
d=C;
m=m2;
s=32'd09;
t=`T_30;
next_D=next_a;
end
4'b1110:
begin
a=C;
b=D;
c=A;
d=B;
m=m7;
s=32'd14;
t=`T_31;
next_C=next_a;
end
4'b1111:
begin
a=B;
b=C;
c=D;
d=A;
m=m12;
s=32'd20;
t=`T_32;
next_B=next_a;
end
endcase
if (phase == 4'b1111)
next_state = ROUND3[7:0];
end // }
//----------------------------------------------------------------
//--------------------------- ROUND 3 ----------------------------
//----------------------------------------------------------------
current_state[ROUND3_BIT]:
begin // {
// synopsys translate_off
ascii_state = "ROUND3";
// synopsys translate_on
round = `ROUND3;
case (phase)
4'b0000:
begin
a=A;
b=B;
c=C;
d=D;
m=m5;
s=32'd04;
t=`T_33;
next_A=next_a;
end
4'b0001:
begin
a=D;
b=A;
c=B;
d=C;
m=m8;
s=32'd11;
t=`T_34;
next_D=next_a;
end
4'b0010:
begin
a=C;
b=D;
c=A;
d=B;
m=m11;
s=32'd16;
t=`T_35;
next_C=next_a;
end
4'b0011:
begin
a=B;
b=C;
c=D;
d=A;
m=m14;
s=32'd23;
t=`T_36;
next_B=next_a;
end
4'b0100:
begin
a=A;
b=B;
c=C;
d=D;
m=m1;
s=32'd04;
t=`T_37;
next_A=next_a;
end
4'b0101:
begin
a=D;
b=A;
c=B;
d=C;
m=m4;
s=32'd11;
t=`T_38;
next_D=next_a;
end
4'b0110:
begin
a=C;
b=D;
c=A;
d=B;
m=m7;
s=32'd16;
t=`T_39;
next_C=next_a;
end
4'b0111:
begin
a=B;
b=C;
c=D;
d=A;
m=m10;
s=32'd23;
t=`T_40;
next_B=next_a;
end
4'b1000:
begin
a=A;
b=B;
c=C;
d=D;
m=m13;
s=32'd04;
t=`T_41;
next_A=next_a;
end
4'b1001:
begin
a=D;
b=A;
c=B;
d=C;
m=m0;
s=32'd11;
t=`T_42;
next_D=next_a;
end
4'b1010:
begin
a=C;
b=D;
c=A;
d=B;
m=m3;
s=32'd16;
t=`T_43;
next_C=next_a;
end
4'b1011:
begin
a=B;
b=C;
c=D;
d=A;
m=m6;
s=32'd23;
t=`T_44;
next_B=next_a;
end
4'b1100:
begin
a=A;
b=B;
c=C;
d=D;
m=m9;
s=32'd04;
t=`T_45;
next_A=next_a;
end
4'b1101:
begin
a=D;
b=A;
c=B;
d=C;
m=m12;
s=32'd11;
t=`T_46;
next_D=next_a;
end
4'b1110:
begin
a=C;
b=D;
c=A;
d=B;
m=m15;
s=32'd16;
t=`T_47;
next_C=next_a;
end
4'b1111:
begin
a=B;
b=C;
c=D;
d=A;
m=m2;
s=32'd23;
t=`T_48;
next_B=next_a;
end
endcase
if (phase == 4'b1111)
next_state = ROUND4[7:0];
end // }
//----------------------------------------------------------------
//--------------------------- ROUND 4 ----------------------------
//----------------------------------------------------------------
current_state[ROUND4_BIT]:
begin // {
// synopsys translate_off
ascii_state = "ROUND4";
// synopsys translate_on
round = `ROUND4;
case (phase)
4'b0000:
begin
a=A;
b=B;
c=C;
d=D;
m=m0;
s=32'd06;
t=`T_49;
next_A=next_a;
end
4'b0001:
begin
a=D;
b=A;
c=B;
d=C;
m=m7;
s=32'd10;
t=`T_50;
next_D=next_a;
end
4'b0010:
begin
a=C;
b=D;
c=A;
d=B;
m=m14;
s=32'd15;
t=`T_51;
next_C=next_a;
end
4'b0011:
begin
a=B;
b=C;
c=D;
d=A;
m=m5;
s=32'd21;
t=`T_52;
next_B=next_a;
end
4'b0100:
begin
a=A;
b=B;
c=C;
d=D;
m=m12;
s=32'd06;
t=`T_53;
next_A=next_a;
end
4'b0101:
begin
a=D;
b=A;
c=B;
d=C;
m=m3;
s=32'd10;
t=`T_54;
next_D=next_a;
end
4'b0110:
begin
a=C;
b=D;
c=A;
d=B;
m=m10;
s=32'd15;
t=`T_55;
next_C=next_a;
end
4'b0111:
begin
a=B;
b=C;
c=D;
d=A;
m=m1;
s=32'd21;
t=`T_56;
next_B=next_a;
end
4'b1000:
begin
a=A;
b=B;
c=C;
d=D;
m=m8;
s=32'd06;
t=`T_57;
next_A=next_a;
end
4'b1001:
begin
a=D;
b=A;
c=B;
d=C;
m=m15;
s=32'd10;
t=`T_58;
next_D=next_a;
end
4'b1010:
begin
a=C;
b=D;
c=A;
d=B;
m=m6;
s=32'd15;
t=`T_59;
next_C=next_a;
end
4'b1011:
begin
a=B;
b=C;
c=D;
d=A;
m=m13;
s=32'd21;
t=`T_60;
next_B=next_a;
end
4'b1100:
begin
a=A;
b=B;
c=C;
d=D;
m=m4;
s=32'd06;
t=`T_61;
next_A=next_a;
end
4'b1101:
begin
a=D;
b=A;
c=B;
d=C;
m=m11;
s=32'd10;
t=`T_62;
next_D=next_a;
end
4'b1110:
begin
a=C;
b=D;
c=A;
d=B;
m=m2;
s=32'd15;
t=`T_63;
next_C=next_a;
end
4'b1111:
begin
a=B;
b=C;
c=D;
d=A;
m=m9;
s=32'd21;
t=`T_64;
next_B=next_a;
end
endcase
if (phase == 4'b1111)
next_state = FINISH_OFF[7:0];
end // }
//----------------------------------------------------------------
current_state[FINISH_OFF_BIT]:
begin // {
// synopsys translate_off
ascii_state = "FINISH_OFF";
// synopsys translate_on
next_A = AA + A;
next_B = BB + B;
next_C = CC + C;
next_D = DD + D;
next_state = TURN_ARND[7:0];
end // }
//----------------------------------------------------------------
// One cycle for making the system to come to reset state
current_state[TURN_ARND_BIT]:
begin // {
// synopsys translate_off
ascii_state = "TURN_ARND";
// synopsys translate_on
next_state = IDLE[7:0];
end // }
endcase
end // }
//--------------------------------
//
// Flops and other combinatorial
// logic definition
//
//--------------------------------
// Outputs
assign msg_output = {{A[7:0], A[15:8], A[23:16], A[31:24]}
,{B[7:0], B[15:8], B[23:16], B[31:24]}
,{C[7:0], C[15:8], C[23:16], C[31:24]}
,{D[7:0], D[15:8], D[23:16], D[31:24]}};
always @(posedge clk)
msg_out_valid <= current_state[FINISH_OFF_BIT];
assign ready = current_state[IDLE_BIT];
// Internal scratch pads
always @(posedge clk)
if (next_state[ROUND1_BIT] && current_state[IDLE_BIT])
begin // {
AA <= A;
BB <= B;
CC <= C;
DD <= D;
end // }
// Initialize A, B, C and D and then compute them
always @(posedge clk)
if (rst )
begin // {
A <= SALT_A;
B <= SALT_B;
C <= SALT_C;
D <= SALT_D;
end // }
else
begin // {
A <= next_A;
B <= next_B;
C <= next_C;
D <= next_D;
end // }
// Determine one of the 16 phases within each round
always @(posedge clk)
if (rst)
phase <= 4'b0;
else if (next_state[ROUND1_BIT] && current_state[IDLE_BIT])
phase <= 4'b0;
else
phase <= phase + 4'b1;
// Assign current_state based on rst and the next_state
always @(posedge clk)
if (rst)
current_state <= IDLE[7:0];
else
current_state <= next_state;
endmodule
|
/*****************************************************************
Pancham is an MD5 compliant IP core for cryptographic applicati
-ons.
Copyright (C) 2003 Swapnajit Mittra, Project VeriPage
(Contact email: verilog_tutorial at hotmail.com
Website : http://www.angelfire.com/ca/verilog)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the
Free Software Foundation, Inc.
59 Temple Place, Suite 330
Boston, MA 02111-1307
USA
******************************************************************/
/*
* pancham_round performs the rounds 1-4 of the MD5 algorithm
* described in RFC1321 for a 128-bit long input message.
*
* Inputs: [abcd m[k] s abs(sin(2*pi*t/64))] as described
* in RFC1321.Also the round number (1-4).
*
* Outputs: the modified 'a' value as describes in RFC1321
* on the left hand side of the round #n equation.
*
*/
`define ROUND1 2'b00
`define ROUND2 2'b01
`define ROUND3 2'b10
`define ROUND4 2'b11
module pancham_round (
a
, b
, c
, d
, m
, s
, t
, round
, next_a
);
input [31:0] a;
input [31:0] b;
input [31:0] c;
input [31:0] d;
input [31:0] m; // Note that for a 128-bit long input message, X[k] = M[k] = m
input [31:0] s;
input [31:0] t; // t-th sample of abs(sin(i)), i = 1, 2, ..., 64
input [1:0] round; // round number (1-4).
output [31:0] next_a;
wire [31:0] a; //
wire [31:0] b;
wire [31:0] c;
wire [31:0] d;
wire [31:0] m;
wire [31:0] s;
wire [31:0] t;
wire [1:0] round;
reg [31:0] next_a;
reg [31:0] add_result;
reg [31:0] rotate_result1;
reg [31:0] rotate_result2;
always @(a
or b
or c
or d
or m
or s
or t
or round)
begin // {
case (round)
`ROUND1:
begin // {
add_result = (a + F(b,c,d) + m + t);
rotate_result1 = add_result << s;
rotate_result2 = add_result >> (32-s);
next_a = b + (rotate_result1 | rotate_result2);
end // }
`ROUND2:
begin // {
add_result = (a + G(b,c,d) + m + t);
rotate_result1 = add_result << s;
rotate_result2 = add_result >> (32-s);
next_a = b + (rotate_result1 | rotate_result2);
end // }
`ROUND3:
begin // {
add_result = (a + H(b,c,d) + m + t);
rotate_result1 = add_result << s;
rotate_result2 = add_result >> (32-s);
next_a = b + (rotate_result1 | rotate_result2);
end // }
`ROUND4:
begin // {
add_result = (a + I(b,c,d) + m + t);
rotate_result1 = add_result << s;
rotate_result2 = add_result >> (32-s);
next_a = b + (rotate_result1 | rotate_result2);
end // }
endcase
end // }
//--------------------------------
//
// Function declarations
//
//--------------------------------
// Step 4 functions F, G, H and I
function [31:0] F;
input [31:0] x, y, z;
begin // {
F = (x&y)|((~x)&z);
end // }
endfunction // }
function [31:0] G;
input [31:0] x, y, z;
begin // {
G = (x&z)|(y&(~z));
end // }
endfunction
function [31:0] H;
input [31:0] x, y, z;
begin // {
H = (x^y^z);
end // }
endfunction
function [31:0] I;
input [31:0] x, y, z;
begin // {
I = (y^(x|(~z)));
end // }
endfunction
endmodule
|
--------------------
Exponent
--------------------
000000ff
255
--------------------
Modulus
--------------------
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
13407807929942597099574024998205846127479365820592393377723561443721764030073546976801874298166903427690031858186486050853753882811946569946433649006084095
--------------------
B -> Message
--------------------
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
115792089237316195423570985008687907853269984665640564039457584007913129639935
--------------------
Result
--------------------
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffc000000000000000000000000000000000000000000000000000000000000000
3351951982485649274893506249551461531869841455148098344430890360930441007518357796178159245492869964176255792569658195217272060561976778090606433969111040
3351951982485649274893506249551461531869841455148098344430890360930441007518357796178159245492869964176255792569658195217272060561976778090606433969111040
3351951982485649274893506249551461531869841455148098344430890360930441007518357796178159245492869964176255792569658195217272060561976778090606433969111040
|
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/100ps
//------------------------------------------------------------------
// Test module.
//------------------------------------------------------------------
module tb_modexp();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// Debug output control.
parameter DEBUG = 0;
parameter VCD = 1;
// Clock defines.
localparam CLK_HALF_PERIOD = 1;
localparam CLK_PERIOD = 2 * CLK_HALF_PERIOD;
// Address defines
localparam OPERAND_WIDTH = 32;
localparam ADDRESS_WIDTH = 8;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_CYCLES_HIGH = 8'h10;
localparam ADDR_CYCLES_LOW = 8'h11;
localparam ADDR_MODULUS_LENGTH = 8'h20;
localparam ADDR_EXPONENT_LENGTH = 8'h21;
localparam ADDR_MODULUS_PTR_RST = 8'h30;
localparam ADDR_MODULUS_DATA = 8'h31;
localparam ADDR_EXPONENT_PTR_RST = 8'h40;
localparam ADDR_EXPONENT_DATA = 8'h41;
localparam ADDR_MESSAGE_PTR_RST = 8'h50;
localparam ADDR_MESSAGE_DATA = 8'h51;
localparam ADDR_RESULT_PTR_RST = 8'h60;
localparam ADDR_RESULT_DATA = 8'h61;
localparam DEFAULT_MODLENGTH = 8'h80; // 2048 bits.
localparam DEFAULT_EXPLENGTH = 8'h80;
localparam CORE_NAME0 = 32'h6d6f6465; // "mode"
localparam CORE_NAME1 = 32'h78702020; // "xp "
localparam CORE_VERSION = 32'h302e3532; // "0.52"
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg [127 : 0] result_data;
reg tb_clk;
reg tb_reset_n;
reg tb_cs;
reg tb_we;
reg [31 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
wire tb_error;
reg tb_cyc;
reg [3 : 0] tb_sel;
wire tb_ack;
wire tb_err;
wire tb_int;
reg [31 : 0] pmsg [63 : 0];
reg [31 : 0] cmsg [63 : 0];
reg [31 : 0] gmsg [63 : 0];
integer f1;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
modexp dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.cs(tb_cs),
.we(tb_we),
.address(tb_address[10:2]),
.write_data(tb_write_data),
.read_data(tb_read_data));
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut();
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
$display("");
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim();
begin
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_cs = 0;
tb_we = 0;
tb_address = 32'h00000000;
tb_write_data = 32'h00000000;
end
endtask // init_sim
//----------------------------------------------------------------
// read_word()
//
// Read a data word from the given address in the DUT.
//----------------------------------------------------------------
task read_word(input [7 : 0] address);
begin
tb_address = {22'b0,address,2'b0};
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
tb_cs = 0;
if (DEBUG)
begin
$display("*** (read_word) Reading 0x%08x from 0x%02x.", tb_read_data, address);
$display("");
end
end
endtask // read_word
//----------------------------------------------------------------
// write_word()
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [ 7 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
begin
$display("*** (write_word) Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
tb_address = {22'b0,address,2'b0};
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask // write_word
//----------------------------------------------------------------
// wait_ready()
//
// Wait until the ready flag in the core is set.
//----------------------------------------------------------------
task wait_ready();
begin
while (tb_read_data != 32'h00000001)
read_word(8'h09);
if (DEBUG)
$display("*** (wait_ready) Ready flag has been set.");
end
endtask // wait_ready
//----------------------------------------------------------------
// assertEquals
//----------------------------------------------------------------
function assertEquals(
input [31:0] expected,
input [31:0] actual
);
begin
if (expected === actual)
begin
assertEquals = 1; // success
end
else
begin
$display("*** Expected: 0x%08x, got 0x%08x", expected, actual);
assertEquals = 0; // failure
end
end
endfunction // assertEquals
//----------------------------------------------------------------
// assertSuccess
//----------------------------------------------------------------
task assertSuccess(input success);
begin
if (success !== 1)
begin
$display("*** Test -> FAILED");
error_ctr = error_ctr + 1;
end
else
$display("*** Test -> passed");
end
endtask // assertSuccess
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results();
begin
$display("");
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// exp32bit_mod2048bit_test();
//----------------------------------------------------------------
task exp32bit_mod2048bit_test();
integer i;
integer success;
reg [31 : 0] read_data;
reg [31 : 0] exp [63 : 0];
reg [31 : 0] mod [63 : 0];
reg [31 : 0] msg [63 : 0];
reg [31 : 0] res [63 : 0];
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("");
$display("Test with e = 65537 and 2048 bit modulus -- Encrypting");
$readmemh("./gen/exp", exp);
$readmemh("./gen/mod", mod);
$readmemh("./gen/msg", msg);
$readmemh("./gen/res", res);
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
write_word(ADDR_EXPONENT_DATA , exp[0]);
write_word(ADDR_MODULUS_PTR_RST, 32'h00000000);
write_word(ADDR_MODULUS_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MODULUS_DATA, mod[i]);
if(DEBUG) $display("writing: %d -> %h", i, mod[i]);
end
write_word(ADDR_MESSAGE_PTR_RST, 32'h00000000);
write_word(ADDR_MESSAGE_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MESSAGE_DATA, msg[i]);
if(DEBUG) $display("Writing: %d -> %h", i, msg[i]);
end
write_word(ADDR_EXPONENT_LENGTH, 32'h00000001);
write_word(ADDR_MODULUS_LENGTH , 32'h00000041);
// Start processing and wait for ready.
write_word(ADDR_CTRL, 32'h00000001);
wait_ready();
write_word(ADDR_RESULT_PTR_RST, 32'h00000000);
read_word(ADDR_RESULT_DATA); read_data=tb_read_data;
success=success&assertEquals(32'h00000000, read_data);
for(i=0; i<64; i=i+1) begin
read_word(ADDR_RESULT_DATA);
read_data=tb_read_data;
success=success&assertEquals(res[i], read_data);
if(DEBUG) $display("Reading: %d -> %h -> %h", i, res[i], read_data);
end
if (success !== 1)
begin
$display("*** ERROR: e65537_2048bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_2048bit_modulus success.");
end
endtask // e65537_2048bit_modulus
//----------------------------------------------------------------
// modexp_encrypt
//----------------------------------------------------------------
task modexp_encrypt();
integer i;
integer success;
reg [31 : 0] pubexp [1];
reg [31 : 0] pubmod [63 : 0];
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("");
$display("Encrypting -- exp = 65537 and 2048 bit mod");
$readmemh("./gen/pTextHEX", pmsg);
$readmemh("./gen/exponent", pubexp);
$readmemh("./gen/modulus", pubmod);
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
write_word(ADDR_EXPONENT_DATA , pubexp[0]);
if(DEBUG) $display("Writing EXP: %d %h", pubexp[0], pubexp[0]);
write_word(ADDR_MODULUS_PTR_RST, 32'h00000000);
write_word(ADDR_MODULUS_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MODULUS_DATA, pubmod[i]);
if(DEBUG) $display("Writing MOD: %d -> %h", i, pubmod[i]);
end
write_word(ADDR_MESSAGE_PTR_RST, 32'h00000000);
write_word(ADDR_MESSAGE_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MESSAGE_DATA, pmsg[i]);
if(DEBUG) $display("Writing MSG: %d -> %h", i, pmsg[i]);
end
write_word(ADDR_EXPONENT_LENGTH, 32'h00000001);
write_word(ADDR_MODULUS_LENGTH , 32'h00000041);
// Start processing and wait for ready.
write_word(ADDR_CTRL, 32'h00000001);
wait_ready();
write_word(ADDR_RESULT_PTR_RST, 32'h00000000);
read_word(ADDR_RESULT_DATA); cmsg[0]=tb_read_data;
//success=success&assertEquals(32'h00000000, cmsg[0]);
f1 = $fopen("./gen/cTextHEX", "w");
for(i=0; i<64; i=i+1) begin
read_word(ADDR_RESULT_DATA);
cmsg[i]=tb_read_data;
if(DEBUG) $display("Reading: %d -> %h ", i, cmsg[i]);
$fwrite(f1, "%h\n",cmsg[i]);
end
$fclose(f1);
assertSuccess(success);
end
endtask // e65537_2048bit_modulus
//----------------------------------------------------------------
// modexp_decrypt
//----------------------------------------------------------------
task modexp_decrypt();
integer i;
integer success;
reg [31 : 0] rdata;
reg [31 : 0] read_data;
reg [31 : 0] priexp [63 : 0];
reg [31 : 0] primod [63 : 0];
begin
$display("");
$display("*** Running -> modexp_decrypt()");
$readmemh("./gen/priExponent", priexp);
$readmemh("./gen/priModulus", primod);
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Decrypting -- 2048 bit exp and 2048 bit mod");
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
write_word(ADDR_EXPONENT_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_EXPONENT_DATA, priexp[i]);
if(DEBUG) $display("Writing EXP: %d -> %h", i, priexp[i]);
end
write_word(ADDR_MODULUS_PTR_RST, 32'h00000000);
write_word(ADDR_MODULUS_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MODULUS_DATA, primod[i]);
if(DEBUG) $display("Writing MOD: %d -> %h", i, primod[i]);
end
write_word(ADDR_MESSAGE_PTR_RST, 32'h00000000);
write_word(ADDR_MESSAGE_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MESSAGE_DATA, cmsg[i]);
if(DEBUG) $display("Writing MSG: %d -> %h", i, cmsg[i]);
end
write_word(ADDR_EXPONENT_LENGTH, 32'h00000041);
write_word(ADDR_MODULUS_LENGTH , 32'h00000041);
// Start processing and wait for ready.
write_word(ADDR_CTRL, 32'h00000001);
wait_ready();
write_word(ADDR_RESULT_PTR_RST, 32'h00000000);
read_word(ADDR_RESULT_DATA); rdata=tb_read_data;
success=success&assertEquals(32'h00000000, rdata);
f1 = $fopen("./gen/gTextHEX", "w");
for(i=0; i<64; i=i+1) begin
read_word(ADDR_RESULT_DATA);
rdata=tb_read_data;
if(DEBUG) $display("Reading: %d -> %h ", i, rdata);
$fwrite(f1, "%h\n",rdata);
success=success&assertEquals(pmsg[i], rdata);
end
$fclose(f1);
assertSuccess(success);
end
endtask // e65537_2048bit_modulus
//----------------------------------------------------------------
// modexp_32bits
//----------------------------------------------------------------
task modexp_32bits(input [31:0] Wmsg,
input [31:0] Wexp,
input [31:0] Wmod,
input [31:0] Wres);
reg [31 : 0] Rmsg;
reg [31 : 0] Rexp;
reg [31 : 0] Rmod;
reg [31 : 0] Rres;
integer success;
begin
$display("");
$display("*** Running -> modexp_32bits()");
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("*** Writing -> MES: %h EXP: %h MOD: %h", Wmsg, Wexp, Wmod);
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
write_word(ADDR_EXPONENT_DATA , Wexp);
write_word(ADDR_MODULUS_PTR_RST , 32'h00000000);
write_word(ADDR_MODULUS_DATA , Wmod);
write_word(ADDR_MESSAGE_PTR_RST , 32'h00000000);
write_word(ADDR_MESSAGE_DATA , Wmsg);
write_word(ADDR_EXPONENT_LENGTH , 32'h00000001);
write_word(ADDR_MODULUS_LENGTH , 32'h00000001);
// Start processing and wait for ready.
write_word(ADDR_CTRL , 32'h00000001);
wait_ready();
write_word(ADDR_MESSAGE_PTR_RST , 32'h00000000);
read_word(ADDR_MESSAGE_DATA);
Rmsg=tb_read_data;
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
read_word(ADDR_EXPONENT_DATA);
Rexp=tb_read_data;
write_word(ADDR_MODULUS_PTR_RST , 32'h00000000);
read_word(ADDR_MODULUS_DATA);
Rmod=tb_read_data;
write_word(ADDR_RESULT_PTR_RST , 32'h00000000);
read_word(ADDR_RESULT_DATA);
Rres=tb_read_data;
$display("*** Reading -> MES: %h EXP: %h MOD: %h RES: %h", Rmsg, Rexp, Rmod, Rres);
success=success&assertEquals(Wres, Rres);
assertSuccess(success);
end
endtask // e65537_2048bit_modulus
//----------------------------------------------------------------
// main
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : main
if(VCD) begin
$dumpfile("./iverilog/tb_modexp.vcd");
$dumpvars(0,tb_modexp);
//$dumpvars(1,tb_clk, tb_reset_n, tb_cs, tb_we, tb_address, tb_write_data, tb_read_data);
end
$display(" -= Testbench for modexp started =-");
$display(" =================================");
$display("");
init_sim();
reset_dut();
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000005, 32'h00000001); //msg^exp < mod -> 1^2 < 5
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000003, 32'h00000001); //msg^exp < mod -> 1^2 < 3
modexp_32bits(32'h00000002, 32'h00000002, 32'h00000005, 32'h00000004); //msg^exp < mod -> 2^2 < 5
modexp_32bits(32'h00000002, 32'h00000002, 32'h00000003, 32'h00000001); //msg^exp > mod -> 2^2 > 3
modexp_32bits(32'h00000004, 32'h0000000D, 32'h000001F1, 32'h000001bd); //msg^exp > mod -> 4^13 > 497
modexp_32bits(32'h01234567, 32'h89ABCDEF, 32'h11111111, 32'h0D9EF081); //msg^exp > mod -> 19088743^2309737967 > 286331153
modexp_32bits(32'h30000000, 32'hC0000000, 32'h00A00001, 32'h0000CC3F); //msg^exp > mod -> 805306368^3221225472 > 10485761 <- Passes
//modexp_32bits(32'h30000000, 32'hC0000000, 32'h00A00000, 32'h00600000); //msg^exp > mod -> 805306368^3221225472 > 10485760 <- Fails
//modexp_32bits(32'h00000002, 32'h00000003, 32'h00000001, 32'h00000000); //mod 1 <- FAILS Does not check
/*
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000002, 32'h00000001); //1 mod 2 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000003, 32'h00000001); //1 mod 3 = 1 -> 1 <- passes
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000004, 32'h00000001); //1 mod 4 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000005, 32'h00000001); //1 mod 5 = 1 -> 1 <- passes
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000006, 32'h00000001); //1 mod 6 = 1 -> 4 <- FAILS
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000002, 32'h00000000); //2 mod 2 = 0 -> passes
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000003, 32'h00000002); //2 mod 3 = 2 -> passes
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000004, 32'h00000002); //2 mod 4 = 2 -> 0 <- FAILS
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000005, 32'h00000002); //2 mod 5 = 2 -> passes
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000006, 32'h00000002); //2 mod 6 = 2 -> passes
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000002, 32'h00000001); //3 mod 2 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000003, 32'h00000000); //3 mod 3 = 0 -> 3 <- FAILS
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000004, 32'h00000003); //3 mod 4 = 3 -> 0 <- FAILS
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000005, 32'h00000003); //3 mod 5 = 3 -> passes
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000006, 32'h00000003); //3 mod 6 = 3 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000002, 32'h00000000); //4 mod 2 = 0 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000003, 32'h00000001); //4 mod 3 = 1 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000004, 32'h00000000); //4 mod 4 = 0 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000005, 32'h00000004); //4 mod 5 = 4 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000006, 32'h00000004); //4 mod 6 = 4 -> passes
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000002, 32'h00000001); //5 mod 2 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000003, 32'h00000002); //5 mod 3 = 2 -> passes
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000004, 32'h00000001); //5 mod 4 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000005, 32'h00000000); //5 mod 5 = 0 -> 5 <- FAILS
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000006, 32'h00000005); //5 mod 6 = 5 -> passes
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000002, 32'h00000000); //6 mod 2 = 0 -> passes
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000003, 32'h00000000); //6 mod 3 = 0 -> 3 <- FAILS
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000004, 32'h00000002); //6 mod 4 = 2 -> 0 <- FAILS
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000005, 32'h00000001); //6 mod 5 = 1 -> passes
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000006, 32'h00000000); //6 mod 6 = 0 -> 1 <- FAILS
*/
/*
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000002, 32'h00000000); //8^6 mod 2 = 0 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000003, 32'h00000001); //8^6 mod 3 = 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000004, 32'h00000000); //8^6 mod 4 = 0 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000005, 32'h00000004); //8^6 mod 5 = 4 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000006, 32'h00000004); //8^6 mod 6 = 4 -> 1 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000007, 32'h00000001); //8^6 mod 7 = 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000008, 32'h00000000); //8^6 mod 8 = 0 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000009, 32'h00000001); //8^6 mod 9 = 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000A, 32'h00000004); //8^6 mod 10= 4 -> 9 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000B, 32'h00000003); //8^6 mod 11= 3 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000C, 32'h00000004); //8^6 mod 12= 4 -> 5 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000D, 32'h0000000C); //8^6 mod 13= 12-> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000E, 32'h00000008); //8^6 mod 14= 8 -> 5 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000F, 32'h00000004); //8^6 mod 15= 4 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000010, 32'h00000000); //8^6 mod 16= 0 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000011, 32'h00000004); //8^6 mod 17= 4 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000012, 32'h0000000A); //8^6 mod 18= 10-> 13<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000013, 32'h00000001); //8^6 mod 19= 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000014, 32'h00000004); //8^6 mod 20= 4 -> 11<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000015, 32'h00000001); //8^6 mod 21= 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000016, 32'h0000000E); //8^6 mod 22= 14-> 1 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000017, 32'h0000000D); //8^6 mod 23= 13-> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000018, 32'h00000010); //8^6 mod 24= 16-> 9 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000019, 32'h00000013); //8^6 mod 25= 19-> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001A, 32'h0000000C); //8^6 mod 26= 12-> 19<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001B, 32'h00000001); //8^6 mod 27= 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001C, 32'h00000008); //8^6 mod 28= 8 -> 19<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001D, 32'h0000000D); //8^6 mod 29= 13-> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001E, 32'h00000004); //8^6 mod 30= 4 -> 13<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001F, 32'h00000008); //8^6 mod 31= 8 -> passes
*/
//exp32bit_mod2048bit_test();
//modexp_encrypt();
//modexp_decrypt();
display_test_results();
$display("");
$display("*** modexp simulation done. ***");
$finish;
end // main
endmodule // tb_modexp
//======================================================================
// EOF tb_modexp.v
//======================================================================
|
//======================================================================
//
// tb_modexp.v
// -----------
// Testbench modular exponentiation core.
//
//
// Author: Joachim Strombergson, Peter Magnusson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/100ps
//------------------------------------------------------------------
// Test module.
//------------------------------------------------------------------
module tb_modexp();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// Debug output control.
parameter DEBUG = 0;
parameter DEBUG_EI = 0;
parameter DEBUG_RESULT = 0;
parameter DISPLAY_TEST_CYCLES = 1;
// Clock defines.
localparam CLK_HALF_PERIOD = 1;
localparam CLK_PERIOD = 2 * CLK_HALF_PERIOD;
// The DUT address map.
localparam GENERAL_PREFIX = 4'h0;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_START_BIT = 0;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_MODULUS_LENGTH = 8'h20;
localparam ADDR_EXPONENT_LENGTH = 8'h21;
localparam ADDR_LENGTH = 8'h22;
localparam ADDR_MODULUS_PTR_RST = 8'h30;
localparam ADDR_MODULUS_DATA = 8'h31;
localparam ADDR_EXPONENT_PTR_RST = 8'h40;
localparam ADDR_EXPONENT_DATA = 8'h41;
localparam ADDR_MESSAGE_PTR_RST = 8'h50;
localparam ADDR_MESSAGE_DATA = 8'h51;
localparam ADDR_RESULT_PTR_RST = 8'h60;
localparam ADDR_RESULT_DATA = 8'h61;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] test_cycle_ctr;
reg test_cycle_ctr_rst;
reg test_cycle_ctr_inc;
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg [31 : 0] read_data;
reg [127 : 0] result_data;
reg tb_clk;
reg tb_reset_n;
reg tb_cs;
reg tb_we;
reg [11 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
wire tb_error;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
modexp dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.cs(tb_cs),
.we(tb_we),
.address(tb_address),
.write_data(tb_write_data),
.read_data(tb_read_data)
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
end
end
//----------------------------------------------------------------
// test_cycle_counter
//
// Used to measure the number of cycles it takes to perform
// a given test case.
//----------------------------------------------------------------
always @ (posedge tb_clk)
begin
if (test_cycle_ctr_rst)
test_cycle_ctr = 64'h0000000000000000;
if (test_cycle_ctr_inc)
test_cycle_ctr = test_cycle_ctr + 1;
end
//----------------------------------------------------------------
// start_test_cycle_ctr
//
// Reset and start the test cycle counter.
//----------------------------------------------------------------
task start_test_cycle_ctr();
begin
test_cycle_ctr_rst = 1;
#(CLK_PERIOD);
test_cycle_ctr_rst = 0;
test_cycle_ctr_inc = 1;
end
endtask // start_test_cycle_ctr()
//----------------------------------------------------------------
// stop_test_cycle_ctr()
//
// Stop the test cycle counter and optionally display the
// result.
//----------------------------------------------------------------
task stop_test_cycle_ctr();
begin
test_cycle_ctr_inc = 0;
#(CLK_PERIOD);
if (DISPLAY_TEST_CYCLES)
$display("*** Number of cycles performed during test: 0x%016x", test_cycle_ctr);
end
endtask // stop_test_cycle_ctr()
//----------------------------------------------------------------
// ei_monitor()
//
// Displays ei_new, the most important variable for determining
// what modexp will do (i.e. should Z=MONTPROD( Z, P, M) be
// performed
//----------------------------------------------------------------
always @*
begin : ei_monitor
if (DEBUG_EI)
if (dut.modexp_ctrl_reg == dut.CTRL_ITERATE_Z_P)
$display("loop counter %d: ei = %d", dut.loop_counter_reg, dut.ei_reg);
end
//----------------------------------------------------------------
// z_monitor()
//
// Displays the contents of the result_mem.
//----------------------------------------------------------------
always @*
begin : result_monitor
if (DEBUG_RESULT)
$display("result_mem[0][1] = %x %x",dut.result_mem.mem[0],dut.result_mem.mem[1]);
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
task dump_dut_state();
begin
$display("cycle: 0x%016x", cycle_ctr);
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
$display("cs = 0x%01x, we = 0x%01x", tb_cs, tb_we);
$display("addr = 0x%08x, read_data = 0x%08x, write_data = 0x%08x",
tb_address, tb_read_data, tb_write_data);
$display("");
$display("State:");
$display("ready_reg = 0x%01x, start_reg = 0x%01x, start_new = 0x%01x",
dut.core_inst.ready_reg, dut.start_reg, dut.start_new);
$display("residue_valid = 0x%01x", dut.core_inst.residue_valid_reg);
$display("loop_counter_reg = 0x%08x", dut.core_inst.loop_counter_reg);
$display("exponent_length_reg = 0x%02x exponent_length_m1 = 0x%02x modulus_length_reg = 0x%02x modulus_length_m1 = 0x%02x",
dut.exponent_length_reg, dut.core_inst.exponent_length_m1, dut.modulus_length_reg, dut.core_inst.modulus_length_m1);
$display("ctrl_reg = 0x%04x", dut.core_inst.modexp_ctrl_reg);
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut();
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
$display("");
end
endtask // reset_dut
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results();
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim();
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_cs = 0;
tb_we = 0;
tb_address = 8'h00;
tb_write_data = 32'h00000000;
end
endtask // init_sim
//----------------------------------------------------------------
// read_word()
//
// Read a data word from the given address in the DUT.
// the word read will be available in the global variable
// read_data.
//----------------------------------------------------------------
task read_word(input [11 : 0] address);
begin
tb_address = address;
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
read_data = tb_read_data;
tb_cs = 0;
if (DEBUG)
begin
$display("*** (read_word) Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
end
end
endtask // read_word
//----------------------------------------------------------------
// write_word()
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [11 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
begin
$display("*** (write_word) Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
tb_address = address;
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask // write_word
//----------------------------------------------------------------
// wait_ready()
//
// Wait until the ready flag in the core is set.
//----------------------------------------------------------------
task wait_ready();
begin
while (tb_read_data != 32'h00000001)
read_word({GENERAL_PREFIX, ADDR_STATUS});
if (DEBUG)
$display("*** (wait_ready) Ready flag has been set.");
end
endtask // wait_ready
//----------------------------------------------------------------
// dump_message_mem()
//
// Dump the contents of the message memory.
//----------------------------------------------------------------
task dump_message_mem();
reg [8 : 0] i;
begin
$display("Contents of the message memory:");
for (i = 0 ; i < 256 ; i = i + 8)
begin
$display("message_mem[0x%02x .. 0x%02x] = 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x",
i[7 : 0], (i[7 : 0] + 8'h07),
dut.core_inst.message_mem.mem[(i[7 : 0] + 0)], dut.core_inst.message_mem.mem[(i[7 : 0] + 1)],
dut.core_inst.message_mem.mem[(i[7 : 0] + 2)], dut.core_inst.message_mem.mem[(i[7 : 0] + 3)],
dut.core_inst.message_mem.mem[(i[7 : 0] + 4)], dut.core_inst.message_mem.mem[(i[7 : 0] + 5)],
dut.core_inst.message_mem.mem[(i[7 : 0] + 6)], dut.core_inst.message_mem.mem[(i[7 : 0] + 7)],
);
end
$display("");
end
endtask // dump_message_mem
//----------------------------------------------------------------
// dump_exponent_mem()
//
// Dump the contents of the exponent memory.
//----------------------------------------------------------------
task dump_exponent_mem();
reg [8 : 0] i;
begin
$display("Contents of the exponent memory:");
for (i = 0 ; i < 256 ; i = i + 8)
begin
$display("exponent_mem[0x%02x .. 0x%02x] = 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x",
i[7 : 0], (i[7 : 0] + 8'h07),
dut.core_inst.exponent_mem.mem[(i[7 : 0] + 0)], dut.core_inst.exponent_mem.mem[(i[7 : 0] + 1)],
dut.core_inst.exponent_mem.mem[(i[7 : 0] + 2)], dut.core_inst.exponent_mem.mem[(i[7 : 0] + 3)],
dut.core_inst.exponent_mem.mem[(i[7 : 0] + 4)], dut.core_inst.exponent_mem.mem[(i[7 : 0] + 5)],
dut.core_inst.exponent_mem.mem[(i[7 : 0] + 6)], dut.core_inst.exponent_mem.mem[(i[7 : 0] + 7)],
);
end
$display("");
end
endtask // dump_exponent_mem
//----------------------------------------------------------------
// dump_modulus_mem()
//
// Dump the contents of the modulus memory.
//----------------------------------------------------------------
task dump_modulus_mem();
reg [8 : 0] i;
begin
$display("Contents of the modulus memory:");
for (i = 0 ; i < 256 ; i = i + 8)
begin
$display("modulus_mem[0x%02x .. 0x%02x] = 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x",
i[7 : 0], (i[7 : 0] + 8'h07),
dut.core_inst.modulus_mem.mem[(i[7 : 0] + 0)], dut.core_inst.modulus_mem.mem[(i[7 : 0] + 1)],
dut.core_inst.modulus_mem.mem[(i[7 : 0] + 2)], dut.core_inst.modulus_mem.mem[(i[7 : 0] + 3)],
dut.core_inst.modulus_mem.mem[(i[7 : 0] + 4)], dut.core_inst.modulus_mem.mem[(i[7 : 0] + 5)],
dut.core_inst.modulus_mem.mem[(i[7 : 0] + 6)], dut.core_inst.modulus_mem.mem[(i[7 : 0] + 7)],
);
end
$display("");
end
endtask // dump_modulus_mem
//----------------------------------------------------------------
// dump_residue_mem()
//
// Dump the contents of the residue memory.
//----------------------------------------------------------------
task dump_residue_mem();
reg [8 : 0] i;
begin
$display("Contents of the residue memory:");
for (i = 0 ; i < 256 ; i = i + 8)
begin
$display("residue_mem[0x%02x .. 0x%02x] = 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x",
i[7 : 0], (i[7 : 0] + 8'h07),
dut.core_inst.residue_mem.mem[(i[7 : 0] + 0)], dut.core_inst.residue_mem.mem[(i[7 : 0] + 1)],
dut.core_inst.residue_mem.mem[(i[7 : 0] + 2)], dut.core_inst.residue_mem.mem[(i[7 : 0] + 3)],
dut.core_inst.residue_mem.mem[(i[7 : 0] + 4)], dut.core_inst.residue_mem.mem[(i[7 : 0] + 5)],
dut.core_inst.residue_mem.mem[(i[7 : 0] + 6)], dut.core_inst.residue_mem.mem[(i[7 : 0] + 7)],
);
end
$display("");
end
endtask // dump_residue_mem
//----------------------------------------------------------------
// dump_result_mem()
//
// Dump the contents of the result memory.
//----------------------------------------------------------------
task dump_result_mem();
reg [8 : 0] i;
begin
$display("Contents of the result memory:");
for (i = 0 ; i < 256 ; i = i + 8)
begin
$display("result_mem[0x%02x .. 0x%02x] = 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x",
i[7 : 0], (i[7 : 0] + 8'h07),
dut.core_inst.result_mem.mem[(i[7 : 0] + 0)], dut.core_inst.result_mem.mem[(i[7 : 0] + 1)],
dut.core_inst.result_mem.mem[(i[7 : 0] + 2)], dut.core_inst.result_mem.mem[(i[7 : 0] + 3)],
dut.core_inst.result_mem.mem[(i[7 : 0] + 4)], dut.core_inst.result_mem.mem[(i[7 : 0] + 5)],
dut.core_inst.result_mem.mem[(i[7 : 0] + 6)], dut.core_inst.result_mem.mem[(i[7 : 0] + 7)],
);
end
$display("");
end
endtask // dump_result_mem
//----------------------------------------------------------------
// dump_memories()
//
// Dump the contents of the memories in the dut.
//----------------------------------------------------------------
task dump_memories();
begin
dump_message_mem();
dump_exponent_mem();
dump_modulus_mem();
dump_residue_mem();
dump_result_mem();
end
endtask // dump_memories
//----------------------------------------------------------------
// tc1
//
// A first, very simple testcase where we want to do:
// c = m ** e % N with the following (decimal) test values:
// m = 3
// e = 7
// n = 11
// c = 3 ** 7 % 11 = 9
//----------------------------------------------------------------
task tc1();
reg [31 : 0] read_data;
begin
tc_ctr = tc_ctr + 1;
$display("TC1: Trying to calculate 3**7 mod 11 = 9");
// Write 3 to message memory.
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000003);
// Write 7 to exponent memory and set length to one word.
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000007);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
// Write 11 to modulus memory and set length to one word.
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h0000000b);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000001);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
// Read out result word and check result.
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA});
read_data = tb_read_data;
if (read_data == 32'h00000009)
begin
$display("*** TC1 successful.");
$display("");
end
else
begin
$display("*** ERROR: TC1 NOT successful.");
$display("Expected: 0x09, got 0x%08x", read_data);
error_ctr = error_ctr + 1;
dump_memories();
end
end
endtask // tc1
//----------------------------------------------------------------
// tc2
//
// c = m ** e % N with the following (decimal) test values:
// m = 251
// e = 251
// n = 257
// c = 251 ** 251 % 257 = 183
//----------------------------------------------------------------
task tc2();
reg [31 : 0] read_data;
begin
tc_ctr = tc_ctr + 1;
$display("TC2: Trying to calculate 251**251 mod 257 = 183");
// Write 13 to message memory.
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h000000fb);
// Write 11 to exponent memory and set length to one word.
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h000000fb);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
// Write 7 to modulus memory and set length to one word.
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000101);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000001);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
// Read out result word and check result.
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA});
read_data = tb_read_data;
if (read_data == 32'h000000b7)
begin
$display("*** TC2 successful.");
$display("");
end
else
begin
$display("*** ERROR: TC2 NOT successful.");
$display("Expected: 0x000000b7, got 0x%08x", read_data);
error_ctr = error_ctr + 1;
end
end
endtask // tc2
//----------------------------------------------------------------
// tc3
//
// c = m ** e % N with the following (decimal) test values:
// m = 0x81
// e = 0x41
// n = 0x87
// c = 0x81 ** 0x41 % 0x87 = 0x36
//----------------------------------------------------------------
task tc3();
reg [31 : 0] read_data;
begin
tc_ctr = tc_ctr + 1;
$display("TC3: Trying to calculate 0x81 ** 0x41 mod 0x87 = 0x36");
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000081);
// Write 11 to exponent memory and set length to one word.
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000041);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
// Write 7 to modulus memory and set length to one word.
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000087);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000001);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
// Read out result word and check result.
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA});
read_data = tb_read_data;
if (read_data == 32'h00000036)
begin
$display("*** TC3 successful.");
$display("");
end
else
begin
$display("*** ERROR: TC3 NOT successful.");
$display("Expected: 0x06, got 0x%08x", read_data);
error_ctr = error_ctr + 1;
end
end
endtask // tc3
//----------------------------------------------------------------
// assertEquals
//----------------------------------------------------------------
function assertEquals(
input [31:0] expected,
input [31:0] actual
);
begin
if (expected === actual)
begin
assertEquals = 1; // success
end
else
begin
$display("Expected: 0x%08x, got 0x%08x", expected, actual);
assertEquals = 0; // failure
end
end
endfunction // assertEquals
integer success;
//----------------------------------------------------------------
// autogenerated_BASIC_33bit()
//
// Task that tests modexp with 33 bit oprerands.
//----------------------------------------------------------------
task autogenerated_BASIC_33bit();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("autogenerated_BASIC_33bit: 00000001946473e1 ** h000000010e85e74f mod 0000000170754797 ");
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h946473e1);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h0e85e74f);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h70754797);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000002);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000002);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7761ed4f, read_data);
if (success !== 1)
begin
$display("*** ERROR: autogenerated_BASIC_33bit was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** autogenerated_BASIC_33bit success.");
end
endtask // autogenerated_BASIC_33bit
//----------------------------------------------------------------
// autogenerated_BASIC_128bit()
//
// Task that tests modexp with 128 bit operands.
//----------------------------------------------------------------
task autogenerated_BASIC_128bit();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("autogenerated_BASIC_128bit");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h3285c343);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h2acbcb0f);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h4d023228);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h2ecc73db);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h29462882);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h12caa2d5);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb80e1c66);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h1006807f);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h267d2f2e);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h51c216a7);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hda752ead);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h48d22d89);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000004);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000005);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0ddc404d, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h91600596, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7425a8d8, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha066ca56, read_data);
if (success !== 1)
begin
$display("*** ERROR: autogenerated_BASIC_128bit was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** autogenerated_BASIC_128bit success.");
end
endtask // autogenerated_BASIC_128bit
//----------------------------------------------------------------
// e64bit_64bit_modulus()
//----------------------------------------------------------------
task e64bit_64bit_modulus();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with 64 bit exponent and 64 bit modulus.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h12345678);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h97543211);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hfeababab);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hdeadbeef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffee);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hbeefbeef);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000002);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000003);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'he52c5b9f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h85de87eb, read_data);
if (success !== 1)
begin
$display("*** ERROR: 64 bit exponent and 64 bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** 64 bit exponent and 64 bit modulus success.");
end
endtask // e64bit_64bit_modulus
//----------------------------------------------------------------
// e65537_64bit_modulus()
//----------------------------------------------------------------
task e65537_64bit_modulus();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with e = 65537 and 64 bit modulus.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hf077656f);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h3bf9e69b);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb6684dc3);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h79a5824b);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000003);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h132d8e17, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hdd4d85a4, read_data);
if (success !== 1)
begin
$display("*** ERROR: e65537_64bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_64bit_modulus success.");
end
endtask // e65537_64bit_modulus
//----------------------------------------------------------------
// e65537_64bit_modulus_elength()
//----------------------------------------------------------------
task e65537_64bit_modulus_elength();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with e = 65537 and 64 bit modulus, explicit exponent length.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hf077656f);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h3bf9e69b);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb6684dc3);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h79a5824b);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000003);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h132d8e17, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hdd4d85a4, read_data);
if (success !== 1)
begin
$display("*** ERROR: e65537_64bit_modulus with explicit elength was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_64bit_modulus success.");
end
endtask // e65537_64bit_modulus_elength
//----------------------------------------------------------------
// e65537_128bit_modulus()
//----------------------------------------------------------------
task e65537_128bit_modulus();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with e = 65537 and 128 bit modulus.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hf5e8eee0);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hc06b048a);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h964b2105);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h2c36ad6b);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h956e61b3);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h27997bc4);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h94e7e5c9);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb53585cf);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000005);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h9c6d322c, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h25ab8bd3, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4aa80100, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf0f3a02c, read_data);
if (success !== 1)
begin
$display("*** ERROR: e65537_128bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_128bit_modulus success.");
end
endtask // e65537_128bit_modulus
//----------------------------------------------------------------
// e65537_256bit_modulus()
//
// Task that tests modexp with small exponent and 256 bit modulus.
//----------------------------------------------------------------
task e65537_256bit_modulus();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with e = 65537 and 256 bit modulus.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hf169d36e);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hbe2ce61d);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hc2e87809);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h4fed15c3);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h7c70eac5);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'ha123e643);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h299b36d2);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h788e583b);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hf169d36e);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hbe2ce61d);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hc2e87809);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h4fed15c3);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h7c70eac5);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'ha123e643);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h299b36d2);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h788e583a);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000009);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf169d36e, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hbe2ce61d, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hc2e87809, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4fed15c3, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7c70eac5, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha123e643, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h299b36d2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h788e583a, read_data);
if (success !== 1)
begin
$display("*** ERROR: e65537_256bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_256bit_modulus success.");
end
endtask // e65537_256bit_modulus
//----------------------------------------------------------------
// e65537_1024bit_modulus()
//
// Task that tests modexp with small exponent and
// 2048 bit modulus.
//----------------------------------------------------------------
task e65537_1024bit_modulus();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with e = 65537 and 1024 bit modulus.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000021);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
if (success !== 1)
begin
$display("*** ERROR: e65537_1024bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_1024bit_modulus success.");
end
endtask // e65537_1024bit_modulus
//----------------------------------------------------------------
// e65537_1536bit_modulus()
//
// Task that tests modexp with small exponent and
// 1536 bit modulus.
//----------------------------------------------------------------
task e65537_1536bit_modulus();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with e = 65537 and 1536 bit modulus.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000031);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
if (success !== 1)
begin
$display("*** ERROR: e65537_1536bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_1536bit_modulus success.");
end
endtask // e65537_1536bit_modulus
//----------------------------------------------------------------
// e65537_1664bit_modulus()
//
// Task that tests modexp with small exponent and
// 1664 bit modulus.
//----------------------------------------------------------------
task e65537_1664bit_modulus();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with e = 65537 and 1664 bit modulus.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000035);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
if (success !== 1)
begin
$display("*** ERROR: e65537_1664bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_1664it_modulus success.");
end
endtask // e65537_1664bit_modulus
//----------------------------------------------------------------
// e65537_2048bit_modulus()
//
// Task that tests modexp with small exponent and
// 2048 bit modulus.
//----------------------------------------------------------------
task e65537_2048bit_modulus();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with e = 65537 and 2048 bit modulus.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000041);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
if (success !== 1)
begin
$display("*** ERROR: e65537_2048bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_2048bit_modulus success.");
end
endtask // e65537_2048bit_modulus
//----------------------------------------------------------------
// rob_dec_1024()
//
// Task that tests modexp with 1024 bit decipher/sign with
// real RSA key operands.
//----------------------------------------------------------------
task rob_dec_1024();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Desipher/Sign Test with Rob 1024 bit operands.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h3ff26c9e);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h32685b93);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h66570228);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hf0603c4e);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h04a717c1);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h8038b116);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'heb48325e);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hcada992a);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h920bb241);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h5aee4afe);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'he2a37e87);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hb35b9519);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hb335775d);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h989553e9);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h1326f46e);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h2cdf6b7b);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h84aabfa9);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hef24c600);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hb56872ad);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h5edb9041);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'he8ecd7f8);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h535133fb);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hdefc92c7);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h42384226);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h7d40e5f5);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hc91bd745);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h9578e460);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hfc858374);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h3172bed3);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h73b6957c);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hc0d6a68e);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h33156a61);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h0001ffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00303130);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h0d060960);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h86480165);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h03040201);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h05000420);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h8e36fc9a);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'ha31724c3);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h2416263c);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h0366a175);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hfabbb92b);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h741ca649);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h6107074d);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h0343b597);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hd075ec0a);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h95048ef8);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hcaa69073);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h8d9d58e9);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h1764b437);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h50b58cad);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h8a6e3199);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h135f80ee);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h84eb2bde);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h58d38ee3);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h5825e91e);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hafdeb1ba);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'ha15a160b);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h0057c47c);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hc7765e31);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h868a3e15);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h5ee57cef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hb008c4dd);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h6a0a89ee);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h98a4ee9c);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h971a07de);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h61e5b0d3);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hcf70e1cd);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hc6a0de5b);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h451f2fb9);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hdb995196);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h9f2f884b);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h4b09749a);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'he6c4ddbe);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h7ee61f79);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h265c6adf);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hb16b3015);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000021);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000021);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h06339a64, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h367db02a, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf41158cc, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h95e76049, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4519c165, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h111184be, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'he41d8ee2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2ae5f5d1, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h1da7f962, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hac93ac88, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h915eee13, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha3350c22, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf0dfa62e, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hfdfc2b62, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h29f26e27, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hbebdc84e, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4746df79, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7b387ad2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h13423c9f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h98e8a146, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hff486b6c, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h1a85414e, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h73117121, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hb700e547, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hab4e07b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h21b988b8, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h24dd77c2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h046b0a20, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hcddb986a, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hac75c2f2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hb044ed59, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hea565879, read_data);
if (success !== 1)
begin
$display("*** ERROR: rob_dec_1024 was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** rob_dec_1024 success.");
end
endtask // rob_dec_1024
//----------------------------------------------------------------
// rob_enc_1024()
//
// Task that tests modexp with 1024 bit encipher/verify with
// real RSA key operands.
//----------------------------------------------------------------
task rob_enc_1024();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Encipher/Verify Test with Rob 1024 bit operands.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h06339a64);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h367db02a);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hf41158cc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h95e76049);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h4519c165);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h111184be);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'he41d8ee2);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h2ae5f5d1);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h1da7f962);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hac93ac88);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h915eee13);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'ha3350c22);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hf0dfa62e);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hfdfc2b62);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h29f26e27);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hbebdc84e);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h4746df79);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h7b387ad2);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h13423c9f);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h98e8a146);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hff486b6c);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h1a85414e);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h73117121);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb700e547);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hab4e07b2);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h21b988b8);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h24dd77c2);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h046b0a20);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hcddb986a);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hac75c2f2);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb044ed59);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hea565879);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hd075ec0a);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h95048ef8);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hcaa69073);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h8d9d58e9);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h1764b437);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h50b58cad);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h8a6e3199);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h135f80ee);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h84eb2bde);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h58d38ee3);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h5825e91e);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hafdeb1ba);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'ha15a160b);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h0057c47c);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hc7765e31);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h868a3e15);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h5ee57cef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hb008c4dd);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h6a0a89ee);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h98a4ee9c);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h971a07de);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h61e5b0d3);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hcf70e1cd);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hc6a0de5b);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h451f2fb9);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hdb995196);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h9f2f884b);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h4b09749a);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'he6c4ddbe);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h7ee61f79);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h265c6adf);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hb16b3015);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000021);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000021);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0001ffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00303130, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0d060960, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h86480165, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h03040201, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h05000420, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h8e36fc9a, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha31724c3, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2416263c, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0366a175, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hfabbb92b, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h741ca649, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h6107074d, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0343b597, read_data);
if (success !== 1)
begin
$display("*** ERROR: rob_enc_1024 was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** rob_enc_1024 success.");
end
endtask // rob_enc_1024
//----------------------------------------------------------------
// main
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : main
$display(" -= Testbench for modexp started =-");
$display(" =================================");
$display("");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
// tc1();
// tc2();
// tc3();
// autogenerated_BASIC_33bit();
// autogenerated_BASIC_128bit();
// e64bit_64bit_modulus();
// e65537_64bit_modulus();
// e65537_64bit_modulus_elength();
// e65537_128bit_modulus();
// e65537_256bit_modulus();
// e65537_1024bit_modulus();
// e65537_1536bit_modulus();
// e65537_1664bit_modulus();
e65537_2048bit_modulus();
// rob_dec_1024();
// rob_enc_1024();
display_test_results();
$display("");
$display("*** modexp simulation done. ***");
$finish;
end // main
endmodule // tb_modexp
//======================================================================
// EOF tb_modexp.v
//======================================================================
|
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/100ps
//------------------------------------------------------------------
// Test module.
//------------------------------------------------------------------
module tb_top();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// Debug output control.
parameter DEBUG = 0;
parameter VCD = 1;
// Clock defines.
localparam CLK_HALF_PERIOD = 1;
localparam CLK_PERIOD = 2 * CLK_HALF_PERIOD;
// Address defines
localparam OPERAND_WIDTH = 32;
localparam ADDRESS_WIDTH = 8;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_CYCLES_HIGH = 8'h10;
localparam ADDR_CYCLES_LOW = 8'h11;
localparam ADDR_MODULUS_LENGTH = 8'h20;
localparam ADDR_EXPONENT_LENGTH = 8'h21;
localparam ADDR_MODULUS_PTR_RST = 8'h30;
localparam ADDR_MODULUS_DATA = 8'h31;
localparam ADDR_EXPONENT_PTR_RST = 8'h40;
localparam ADDR_EXPONENT_DATA = 8'h41;
localparam ADDR_MESSAGE_PTR_RST = 8'h50;
localparam ADDR_MESSAGE_DATA = 8'h51;
localparam ADDR_RESULT_PTR_RST = 8'h60;
localparam ADDR_RESULT_DATA = 8'h61;
localparam DEFAULT_MODLENGTH = 8'h80; // 2048 bits.
localparam DEFAULT_EXPLENGTH = 8'h80;
localparam CORE_NAME0 = 32'h6d6f6465; // "mode"
localparam CORE_NAME1 = 32'h78702020; // "xp "
localparam CORE_VERSION = 32'h302e3532; // "0.52"
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg [127 : 0] result_data;
reg tb_clk;
reg tb_reset;
reg tb_cs;
reg tb_we;
reg [31 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
wire tb_error;
reg tb_cyc;
reg [3 : 0] tb_sel;
wire tb_ack;
wire tb_err;
wire tb_int;
reg [31 : 0] pmsg [63 : 0];
reg [31 : 0] cmsg [63 : 0];
reg [31 : 0] gmsg [63 : 0];
integer f1;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
modexp_top dut(
.wb_adr_i(tb_address),
.wb_cyc_i(tb_cyc),//
.wb_dat_i(tb_write_data),
.wb_sel_i(tb_sel),//
.wb_stb_i(tb_cs),
.wb_we_i(tb_we),
.wb_ack_o(tb_ack),//
.wb_err_o(tb_err),//
.wb_dat_o(tb_read_data),
.wb_clk_i(tb_clk),
.wb_rst_i(tb_reset),
.int_o(tb_int)//
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut();
begin
$display("*** Toggle reset.");
tb_reset = 1;
#(2 * CLK_PERIOD);
tb_reset = 0;
$display("");
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim();
begin
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset = 0;
tb_cs = 0;
tb_we = 0;
tb_address = 32'h00000000;
tb_write_data = 32'h00000000;
end
endtask // init_sim
//----------------------------------------------------------------
// read_word()
//
// Read a data word from the given address in the DUT.
//----------------------------------------------------------------
task read_word(input [7 : 0] address);
begin
tb_address = {22'b0,address,2'b0};
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
tb_cs = 0;
if (DEBUG)
begin
$display("*** (read_word) Reading 0x%08x from 0x%02x.", tb_read_data, address);
$display("");
end
end
endtask // read_word
//----------------------------------------------------------------
// write_word()
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [ 7 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
begin
$display("*** (write_word) Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
tb_address = {22'b0,address,2'b0};
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask // write_word
//----------------------------------------------------------------
// wait_ready()
//
// Wait until the ready flag in the core is set.
//----------------------------------------------------------------
task wait_ready();
begin
while (tb_read_data != 32'h00000001)
read_word(8'h09);
if (DEBUG)
$display("*** (wait_ready) Ready flag has been set.");
end
endtask // wait_ready
//----------------------------------------------------------------
// assertEquals
//----------------------------------------------------------------
function assertEquals(
input [31:0] expected,
input [31:0] actual
);
begin
if (expected === actual)
begin
assertEquals = 1; // success
end
else
begin
$display("*** Expected: 0x%08x, got 0x%08x", expected, actual);
assertEquals = 0; // failure
end
end
endfunction // assertEquals
//----------------------------------------------------------------
// assertSuccess
//----------------------------------------------------------------
task assertSuccess(input success);
begin
if (success !== 1)
begin
$display("*** Test -> FAILED");
error_ctr = error_ctr + 1;
end
else
$display("*** Test -> passed");
end
endtask // assertSuccess
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results();
begin
$display("");
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// exp32bit_mod2048bit_test
//----------------------------------------------------------------
task exp32bit_mod2048bit_test();
integer i;
integer success;
reg [31 : 0] read_data;
reg [31 : 0] exp [63 : 0];
reg [31 : 0] mod [63 : 0];
reg [31 : 0] msg [63 : 0];
reg [31 : 0] res [63 : 0];
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("");
$display("Test with e = 65537 and 2048 bit modulus -- Encrypting");
$readmemh("./gen/exp", exp);
$readmemh("./gen/mod", mod);
$readmemh("./gen/msg", msg);
$readmemh("./gen/res", res);
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
write_word(ADDR_EXPONENT_DATA , exp[0]);
write_word(ADDR_MODULUS_PTR_RST, 32'h00000000);
write_word(ADDR_MODULUS_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MODULUS_DATA, mod[i]);
if(DEBUG) $display("writing: %d -> %h", i, mod[i]);
end
write_word(ADDR_MESSAGE_PTR_RST, 32'h00000000);
write_word(ADDR_MESSAGE_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MESSAGE_DATA, msg[i]);
if(DEBUG) $display("Writing: %d -> %h", i, msg[i]);
end
write_word(ADDR_EXPONENT_LENGTH, 32'h00000001);
write_word(ADDR_MODULUS_LENGTH , 32'h00000041);
// Start processing and wait for ready.
write_word(ADDR_CTRL, 32'h00000001);
wait_ready();
write_word(ADDR_RESULT_PTR_RST, 32'h00000000);
read_word(ADDR_RESULT_DATA); read_data=tb_read_data;
success=success&assertEquals(32'h00000000, read_data);
for(i=0; i<64; i=i+1) begin
read_word(ADDR_RESULT_DATA);
read_data=tb_read_data;
success=success&assertEquals(res[i], read_data);
if(DEBUG) $display("Reading: %d -> %h -> %h", i, res[i], read_data);
end
if (success !== 1)
begin
$display("*** ERROR: e65537_2048bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_2048bit_modulus success.");
end
endtask // exp32bit_mod2048bit_test
//----------------------------------------------------------------
// modexp_encrypt
//----------------------------------------------------------------
task modexp_encrypt();
integer i;
integer success;
reg [31 : 0] pubexp [1];
reg [31 : 0] pubmod [63 : 0];
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("");
$display("Encrypting -- exp = 65537 and 2048 bit mod");
$readmemh("./gen/pTextHEX", pmsg);
$readmemh("./gen/exponent", pubexp);
$readmemh("./gen/modulus", pubmod);
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
write_word(ADDR_EXPONENT_DATA , pubexp[0]);
if(DEBUG) $display("Writing EXP: %d %h", pubexp[0], pubexp[0]);
write_word(ADDR_MODULUS_PTR_RST, 32'h00000000);
write_word(ADDR_MODULUS_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MODULUS_DATA, pubmod[i]);
if(DEBUG) $display("Writing MOD: %d -> %h", i, pubmod[i]);
end
write_word(ADDR_MESSAGE_PTR_RST, 32'h00000000);
write_word(ADDR_MESSAGE_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MESSAGE_DATA, pmsg[i]);
if(DEBUG) $display("Writing MSG: %d -> %h", i, pmsg[i]);
end
write_word(ADDR_EXPONENT_LENGTH, 32'h00000001);
write_word(ADDR_MODULUS_LENGTH , 32'h00000041);
// Start processing and wait for ready.
write_word(ADDR_CTRL, 32'h00000001);
wait_ready();
write_word(ADDR_RESULT_PTR_RST, 32'h00000000);
read_word(ADDR_RESULT_DATA); cmsg[0]=tb_read_data;
//success=success&assertEquals(32'h00000000, cmsg[0]);
f1 = $fopen("./gen/cTextHEX", "w");
for(i=0; i<64; i=i+1) begin
read_word(ADDR_RESULT_DATA);
cmsg[i]=tb_read_data;
if(DEBUG) $display("Reading: %d -> %h ", i, cmsg[i]);
$fwrite(f1, "%h\n",cmsg[i]);
end
$fclose(f1);
assertSuccess(success);
end
endtask // modexp_encrypt
//----------------------------------------------------------------
// modexp_decrypt
//----------------------------------------------------------------
task modexp_decrypt();
integer i;
integer success;
reg [31 : 0] rdata;
reg [31 : 0] read_data;
reg [31 : 0] priexp [63 : 0];
reg [31 : 0] primod [63 : 0];
begin
$display("");
$display("*** Running -> modexp_decrypt()");
$readmemh("./gen/priExponent", priexp);
$readmemh("./gen/priModulus", primod);
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Decrypting -- 2048 bit exp and 2048 bit mod");
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
write_word(ADDR_EXPONENT_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_EXPONENT_DATA, priexp[i]);
if(DEBUG) $display("Writing EXP: %d -> %h", i, priexp[i]);
end
write_word(ADDR_MODULUS_PTR_RST, 32'h00000000);
write_word(ADDR_MODULUS_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MODULUS_DATA, primod[i]);
if(DEBUG) $display("Writing MOD: %d -> %h", i, primod[i]);
end
write_word(ADDR_MESSAGE_PTR_RST, 32'h00000000);
write_word(ADDR_MESSAGE_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MESSAGE_DATA, cmsg[i]);
if(DEBUG) $display("Writing MSG: %d -> %h", i, cmsg[i]);
end
write_word(ADDR_EXPONENT_LENGTH, 32'h00000041);
write_word(ADDR_MODULUS_LENGTH , 32'h00000041);
// Start processing and wait for ready.
write_word(ADDR_CTRL, 32'h00000001);
wait_ready();
write_word(ADDR_RESULT_PTR_RST, 32'h00000000);
read_word(ADDR_RESULT_DATA); rdata=tb_read_data;
success=success&assertEquals(32'h00000000, rdata);
f1 = $fopen("./gen/gTextHEX", "w");
for(i=0; i<64; i=i+1) begin
read_word(ADDR_RESULT_DATA);
rdata=tb_read_data;
if(DEBUG) $display("Reading: %d -> %h ", i, rdata);
$fwrite(f1, "%h\n",rdata);
success=success&assertEquals(pmsg[i], rdata);
end
$fclose(f1);
assertSuccess(success);
end
endtask // modexp_decrypt
//----------------------------------------------------------------
// modexp_32bits
//----------------------------------------------------------------
task modexp_32bits(input [31:0] Wmsg,
input [31:0] Wexp,
input [31:0] Wmod,
input [31:0] Wres);
reg [31 : 0] Rmsg;
reg [31 : 0] Rexp;
reg [31 : 0] Rmod;
reg [31 : 0] Rres;
integer success;
begin
$display("");
$display("*** Running -> modexp_32bits()");
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("*** Writing -> MES: %h EXP: %h MOD: %h", Wmsg, Wexp, Wmod);
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
write_word(ADDR_EXPONENT_DATA , Wexp);
write_word(ADDR_MODULUS_PTR_RST , 32'h00000000);
write_word(ADDR_MODULUS_DATA , Wmod);
write_word(ADDR_MESSAGE_PTR_RST , 32'h00000000);
write_word(ADDR_MESSAGE_DATA , Wmsg);
write_word(ADDR_EXPONENT_LENGTH , 32'h00000001);
write_word(ADDR_MODULUS_LENGTH , 32'h00000001);
// Start processing and wait for ready.
write_word(ADDR_CTRL , 32'h00000001);
wait_ready();
write_word(ADDR_MESSAGE_PTR_RST , 32'h00000000);
read_word(ADDR_MESSAGE_DATA);
Rmsg=tb_read_data;
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
read_word(ADDR_EXPONENT_DATA);
Rexp=tb_read_data;
write_word(ADDR_MODULUS_PTR_RST , 32'h00000000);
read_word(ADDR_MODULUS_DATA);
Rmod=tb_read_data;
write_word(ADDR_RESULT_PTR_RST , 32'h00000000);
read_word(ADDR_RESULT_DATA);
Rres=tb_read_data;
$display("*** Reading -> MES: %h EXP: %h MOD: %h RES: %h", Rmsg, Rexp, Rmod, Rres);
success=success&assertEquals(Wres, Rres);
assertSuccess(success);
end
endtask // modexp_32bits
//----------------------------------------------------------------
// main
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : main
if(VCD) begin
$dumpfile("./iverilog/tb_top.vcd");
$dumpvars(0,tb_top);
//$dumpvars(1,tb_clk, tb_reset, tb_cs, tb_we, tb_address, tb_write_data, tb_read_data);
end
$display(" -= Testbench for modexp started =-");
$display(" =================================");
$display("");
init_sim();
reset_dut();
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000005, 32'h00000001); //msg^exp < mod -> 1^2 < 5
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000003, 32'h00000001); //msg^exp < mod -> 1^2 < 3
modexp_32bits(32'h00000002, 32'h00000002, 32'h00000005, 32'h00000004); //msg^exp < mod -> 2^2 < 5
modexp_32bits(32'h00000002, 32'h00000002, 32'h00000003, 32'h00000001); //msg^exp > mod -> 2^2 > 3
modexp_32bits(32'h00000004, 32'h0000000D, 32'h000001F1, 32'h000001bd); //msg^exp > mod -> 4^13 > 497
modexp_32bits(32'h01234567, 32'h89ABCDEF, 32'h11111111, 32'h0D9EF081); //msg^exp > mod -> 19088743^2309737967 > 286331153
modexp_32bits(32'h30000000, 32'hC0000000, 32'h00A00001, 32'h0000CC3F); //msg^exp > mod -> 805306368^3221225472 > 10485761 <- Passes
//modexp_32bits(32'h30000000, 32'hC0000000, 32'h00A00000, 32'h00600000); //msg^exp > mod -> 805306368^3221225472 > 10485760 <- Fails
//modexp_32bits(32'h00000002, 32'h00000003, 32'h00000001, 32'h00000000); //mod 1 <- FAILS Does not check
/*
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000002, 32'h00000001); //1 mod 2 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000003, 32'h00000001); //1 mod 3 = 1 -> 1 <- passes
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000004, 32'h00000001); //1 mod 4 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000005, 32'h00000001); //1 mod 5 = 1 -> 1 <- passes
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000006, 32'h00000001); //1 mod 6 = 1 -> 4 <- FAILS
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000002, 32'h00000000); //2 mod 2 = 0 -> passes
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000003, 32'h00000002); //2 mod 3 = 2 -> passes
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000004, 32'h00000002); //2 mod 4 = 2 -> 0 <- FAILS
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000005, 32'h00000002); //2 mod 5 = 2 -> passes
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000006, 32'h00000002); //2 mod 6 = 2 -> passes
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000002, 32'h00000001); //3 mod 2 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000003, 32'h00000000); //3 mod 3 = 0 -> 3 <- FAILS
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000004, 32'h00000003); //3 mod 4 = 3 -> 0 <- FAILS
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000005, 32'h00000003); //3 mod 5 = 3 -> passes
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000006, 32'h00000003); //3 mod 6 = 3 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000002, 32'h00000000); //4 mod 2 = 0 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000003, 32'h00000001); //4 mod 3 = 1 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000004, 32'h00000000); //4 mod 4 = 0 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000005, 32'h00000004); //4 mod 5 = 4 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000006, 32'h00000004); //4 mod 6 = 4 -> passes
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000002, 32'h00000001); //5 mod 2 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000003, 32'h00000002); //5 mod 3 = 2 -> passes
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000004, 32'h00000001); //5 mod 4 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000005, 32'h00000000); //5 mod 5 = 0 -> 5 <- FAILS
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000006, 32'h00000005); //5 mod 6 = 5 -> passes
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000002, 32'h00000000); //6 mod 2 = 0 -> passes
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000003, 32'h00000000); //6 mod 3 = 0 -> 3 <- FAILS
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000004, 32'h00000002); //6 mod 4 = 2 -> 0 <- FAILS
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000005, 32'h00000001); //6 mod 5 = 1 -> passes
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000006, 32'h00000000); //6 mod 6 = 0 -> 1 <- FAILS
*/
/*
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000002, 32'h00000000); //8^6 mod 2 = 0 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000003, 32'h00000001); //8^6 mod 3 = 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000004, 32'h00000000); //8^6 mod 4 = 0 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000005, 32'h00000004); //8^6 mod 5 = 4 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000006, 32'h00000004); //8^6 mod 6 = 4 -> 1 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000007, 32'h00000001); //8^6 mod 7 = 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000008, 32'h00000000); //8^6 mod 8 = 0 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000009, 32'h00000001); //8^6 mod 9 = 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000A, 32'h00000004); //8^6 mod 10= 4 -> 9 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000B, 32'h00000003); //8^6 mod 11= 3 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000C, 32'h00000004); //8^6 mod 12= 4 -> 5 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000D, 32'h0000000C); //8^6 mod 13= 12-> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000E, 32'h00000008); //8^6 mod 14= 8 -> 5 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000F, 32'h00000004); //8^6 mod 15= 4 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000010, 32'h00000000); //8^6 mod 16= 0 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000011, 32'h00000004); //8^6 mod 17= 4 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000012, 32'h0000000A); //8^6 mod 18= 10-> 13<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000013, 32'h00000001); //8^6 mod 19= 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000014, 32'h00000004); //8^6 mod 20= 4 -> 11<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000015, 32'h00000001); //8^6 mod 21= 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000016, 32'h0000000E); //8^6 mod 22= 14-> 1 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000017, 32'h0000000D); //8^6 mod 23= 13-> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000018, 32'h00000010); //8^6 mod 24= 16-> 9 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000019, 32'h00000013); //8^6 mod 25= 19-> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001A, 32'h0000000C); //8^6 mod 26= 12-> 19<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001B, 32'h00000001); //8^6 mod 27= 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001C, 32'h00000008); //8^6 mod 28= 8 -> 19<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001D, 32'h0000000D); //8^6 mod 29= 13-> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001E, 32'h00000004); //8^6 mod 30= 4 -> 13<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001F, 32'h00000008); //8^6 mod 31= 8 -> passes
*/
//exp32bit_mod2048bit_test();
//modexp_encrypt();
//modexp_decrypt();
display_test_results();
$display("");
$display("*** modexp simulation done. ***");
$finish;
end // main
endmodule // tb_modexp
//======================================================================
// EOF tb_modexp.v
//======================================================================
|
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Defines of the Core ////
//// ////
//// Known problems (limits): ////
//// None ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - gorban@opencores.org ////
//// - Jacob Gorban ////
//// - Igor Mohor (igorm@opencores.org) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Timescale define
`timescale 1ns/10ps
|
//======================================================================
//
// adder.v
// -------
// Adder with separate carry in and carry out. Used in the montprod
// amd residue modules of the modexp core.
//
//
// Author: Peter Magnusson, Joachim Strömbergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module adder #(parameter OPW = 32)
(
input [(OPW - 1) : 0] a,
input [(OPW - 1) : 0] b,
input carry_in,
output wire [(OPW - 1) : 0] sum,
output wire carry_out
);
reg [(OPW) : 0] adder_result;
assign sum = adder_result[(OPW - 1) : 0];
assign carry_out = adder_result[(OPW)];
always @*
begin
adder_result = {1'b0, a} + {1'b0, b} + {{OPW{1'b0}}, carry_in};
end
endmodule // adder
//======================================================================
// EOF adder.v
//======================================================================
|
//======================================================================
//
// blockmem1rw1.v
// --------------
// Synchronous block memory with one read and one write port.
// The data size is the same for both read and write operations.
//
// The memory is used in the modexp core.
//
// paremeter OPW is operand word width in bits.
// parameter ADW is address width in bits.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem1r1w #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire [(ADW - 1) : 0] read_addr,
output wire [(OPW - 1) : 0] read_data,
input wire wr,
input wire [(ADW - 1) : 0] write_addr,
input wire [(OPW - 1) : 0] write_data
);
reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data;
assign read_data = tmp_read_data;
always @ (posedge clk)
begin : reg_mem
if (wr)
mem[write_addr] <= write_data;
tmp_read_data <= mem[read_addr];
end
endmodule // blockmem1r1w
//======================================================================
// EOF blockmem1r1w.v
//======================================================================
|
//======================================================================
//
// blockmem2r1w.v
// --------------
// Synchronous block memory with two read ports and one write port.
// The data size is the same for both read and write operations.
//
// The memory is used in the modexp core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem2r1w #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire [(ADW - 1) : 0] read_addr0,
output wire [(OPW - 1) : 0] read_data0,
input wire [(ADW - 1) : 0] read_addr1,
output wire [(OPW - 1) : 0] read_data1,
input wire wr,
input wire [(ADW - 1) : 0] write_addr,
input wire [(OPW - 1) : 0] write_data
);
reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data0;
reg [(OPW - 1) : 0] tmp_read_data1;
assign read_data0 = tmp_read_data0;
assign read_data1 = tmp_read_data1;
always @ (posedge clk)
begin : reg_mem
if (wr)
mem[write_addr] <= write_data;
tmp_read_data0 <= mem[read_addr0];
tmp_read_data1 <= mem[read_addr1];
end
endmodule // blockmem2r1w
//======================================================================
// EOF blockmem2r1w.v
//======================================================================
|
//======================================================================
//
// blockmem2r1wptr.v
// -----------------
// Synchronous block memory with two read ports and one write port.
// For port 1 the address is implicit and instead given by the
// internal pointer. The pointer is automatically increased
// when the cs signal is set. The pointer is reset to zero when
// the rst signal is asserted.
//
//
// NOTE: This memory needs to be rebuilt if interface 0 is changed
// to use bigger operand widths and fewer words than interface 1.
// This adaption is NOT automatic.
//
//
// The memory is used in the modexp core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem2r1wptr #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire reset_n,
input wire [(ADW - 1) : 0] read_addr0,
output wire [(OPW - 1) : 0] read_data0,
output wire [31 : 0] read_data1,
input wire rst,
input wire cs,
input wire wr,
input wire [31 : 0] write_data
);
//----------------------------------------------------------------
// Memories and regs including update variables and write enable.
//----------------------------------------------------------------
reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data0;
reg [31 : 0] tmp_read_data1;
reg [7 : 0] ptr_reg;
reg [7 : 0] ptr_new;
reg ptr_we;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data0 = tmp_read_data0;
assign read_data1 = tmp_read_data1;
//----------------------------------------------------------------
// mem_update
//
// Clocked update of memory This should cause
// the memory to be implemented as a block memory.
//----------------------------------------------------------------
always @ (posedge clk)
begin : mem_update
if (wr)
mem[ptr_reg] <= write_data;
tmp_read_data0 <= mem[read_addr0];
tmp_read_data1 <= mem[ptr_reg];
end
//----------------------------------------------------------------
// ptr_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : ptr_update
if (!reset_n)
ptr_reg <= 8'h00;
else
if (ptr_we)
ptr_reg <= ptr_new;
end
//----------------------------------------------------------------
// ptr_logic
//----------------------------------------------------------------
always @*
begin : ptr_logic
ptr_new = 8'h00;
ptr_we = 1'b0;
if (rst)
begin
ptr_new = 8'h00;
ptr_we = 1'b1;
end
if (cs)
begin
ptr_new = ptr_reg + 1'b1;
ptr_we = 1'b1;
end
end
endmodule // blockmem2r1wptr
//======================================================================
// EOF blockmem2r1wptr.v
//======================================================================
|
//======================================================================
//
// blockmem2r1wptr.v
// -----------------
// Synchronous block memory with two read ports and one write port.
// For port 1 the address is implicit and instead given by the
// internal pointer. But write address is explicitly given.
//
// The memory is used in the modexp core.
//
//
// NOTE: This memory needs to be rebuilt if interface 0 is changed
// to use bigger operand widths and fewer words than interface 1.
// This adaption is NOT automatic.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem2rptr1w #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire reset_n,
input wire [(ADW - 1) : 0] read_addr0,
output wire [(OPW - 1) : 0] read_data0,
output wire [31 : 0] read_data1,
input wire rst,
input wire cs,
input wire wr,
input wire [07 : 0] write_addr,
input wire [31 : 0] write_data
);
//----------------------------------------------------------------
// Memories and regs including update variables and write enable.
//----------------------------------------------------------------
reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data0;
reg [31 : 0] tmp_read_data1;
reg [7 : 0] ptr_reg;
reg [7 : 0] ptr_new;
reg ptr_we;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data0 = tmp_read_data0;
assign read_data1 = tmp_read_data1;
//----------------------------------------------------------------
// mem_update
//
// Clocked update of memory This should cause
// the memory to be implemented as a block memory.
//----------------------------------------------------------------
always @ (posedge clk)
begin : mem_update
if (wr)
mem[write_addr] <= write_data;
tmp_read_data0 <= mem[read_addr0];
tmp_read_data1 <= mem[ptr_reg];
end
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_mem_update
if (!reset_n)
ptr_reg <= 8'h00;
else
if (ptr_we)
ptr_reg <= ptr_new;
end
//----------------------------------------------------------------
// ptr_logic
//----------------------------------------------------------------
always @*
begin : ptr_logic
ptr_new = 8'h00;
ptr_we = 1'b0;
if (rst)
begin
ptr_new = 8'h00;
ptr_we = 1'b1;
end
if (cs)
begin
ptr_new = ptr_reg + 1'b1;
ptr_we = 1'b1;
end
end
endmodule // blockmem2r1wptr
//======================================================================
// EOF blockmem2r1wptr.v
//======================================================================
|
//======================================================================
//
// modexp.v
// --------
// Top level wrapper for the modula exponentiation core. The core
// is used to implement public key algorithms such as RSA,
// DH, ElGamal etc.
//
// The core calculates the following function:
//
// C = M ** e mod N
//
// M is a message with a length of n bits
// e is the exponent with a length of m bits
// N is the modulus with a length of n bits
//
// n can be 32 and up to and including 8192 bits in steps
// of 32 bits.
// m can be one and up to and including 8192 bits in steps
// of 32 bits.
//
// The core has a 32-bit memory like interface, but provides
// status signals to inform the system that a given operation
// has is done. Additionally, any errors will also be asserted.
//
//
// Author: Joachim Strombergson, Peter Magnusson
// Copyright (c) 2015, NORDUnet A/S
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
//======================================================================
module modexp(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [ 7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// The operand width is the internal operand width in bits.
// The address width is the size of the address space used. This
// value must be balances with OPERAND_WIDTH to allow a total
// of 8192 bits of data. OPERAND_WIDTH * (ADDRESS_WIDTH ** 2)
// is the formula. Note that the API data with is always 32 bits.
localparam OPERAND_WIDTH = 32;
localparam ADDRESS_WIDTH = 8;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_CYCLES_HIGH = 8'h10;
localparam ADDR_CYCLES_LOW = 8'h11;
localparam ADDR_MODULUS_LENGTH = 8'h20;
localparam ADDR_EXPONENT_LENGTH = 8'h21;
localparam ADDR_MODULUS_PTR_RST = 8'h30;
localparam ADDR_MODULUS_DATA = 8'h31;
localparam ADDR_EXPONENT_PTR_RST = 8'h40;
localparam ADDR_EXPONENT_DATA = 8'h41;
localparam ADDR_MESSAGE_PTR_RST = 8'h50;
localparam ADDR_MESSAGE_DATA = 8'h51;
localparam ADDR_RESULT_PTR_RST = 8'h60;
localparam ADDR_RESULT_DATA = 8'h61;
localparam DEFAULT_MODLENGTH = 8'h80; // 2048 bits.
localparam DEFAULT_EXPLENGTH = 8'h80;
localparam CORE_NAME0 = 32'h6d6f6465; // "mode"
localparam CORE_NAME1 = 32'h78702020; // "xp "
localparam CORE_VERSION = 32'h302e3532; // "0.52"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [07 : 0] exponent_length_reg;
reg [07 : 0] exponent_length_new;
reg exponent_length_we;
reg [07 : 0] modulus_length_reg;
reg [07 : 0] modulus_length_new;
reg modulus_length_we;
reg start_reg;
reg start_new;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg exponent_mem_api_rst;
reg exponent_mem_api_cs;
reg exponent_mem_api_wr;
wire [31 : 0] exponent_mem_api_read_data;
reg modulus_mem_api_rst;
reg modulus_mem_api_cs;
reg modulus_mem_api_wr;
wire [31 : 0] modulus_mem_api_read_data;
reg message_mem_api_rst;
reg message_mem_api_cs;
reg message_mem_api_wr;
wire [31 : 0] message_mem_api_read_data;
reg result_mem_api_rst;
reg result_mem_api_cs;
wire [31 : 0] result_mem_api_read_data;
wire ready;
wire [63 : 0] cycles;
reg [31 : 0] tmp_read_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
modexp_core #(.OPW(OPERAND_WIDTH), .ADW(ADDRESS_WIDTH))
core_inst(
.clk(clk),
.reset_n(reset_n),
.start(start_reg),
.ready(ready),
.exponent_length(exponent_length_reg),
.modulus_length(modulus_length_reg),
.cycles(cycles),
.exponent_mem_api_cs(exponent_mem_api_cs),
.exponent_mem_api_wr(exponent_mem_api_wr),
.exponent_mem_api_rst(exponent_mem_api_rst),
.exponent_mem_api_write_data(write_data),
.exponent_mem_api_read_data(exponent_mem_api_read_data),
.modulus_mem_api_cs(modulus_mem_api_cs),
.modulus_mem_api_wr(modulus_mem_api_wr),
.modulus_mem_api_rst(modulus_mem_api_rst),
.modulus_mem_api_write_data(write_data),
.modulus_mem_api_read_data(modulus_mem_api_read_data),
.message_mem_api_cs(message_mem_api_cs),
.message_mem_api_wr(message_mem_api_wr),
.message_mem_api_rst(message_mem_api_rst),
.message_mem_api_write_data(write_data),
.message_mem_api_read_data(message_mem_api_read_data),
.result_mem_api_cs(result_mem_api_cs),
.result_mem_api_rst(result_mem_api_rst),
.result_mem_api_read_data(result_mem_api_read_data)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
start_reg <= 1'b0;
exponent_length_reg <= DEFAULT_EXPLENGTH;
modulus_length_reg <= DEFAULT_MODLENGTH;
end
else
begin
start_reg <= start_new;
if (exponent_length_we)
begin
exponent_length_reg <= write_data[7 : 0];
end
if (modulus_length_we)
begin
modulus_length_reg <= write_data[7 : 0];
end
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
modulus_length_we = 1'b0;
exponent_length_we = 1'b0;
start_new = 1'b0;
modulus_mem_api_rst = 1'b0;
modulus_mem_api_cs = 1'b0;
modulus_mem_api_wr = 1'b0;
exponent_mem_api_rst = 1'b0;
exponent_mem_api_cs = 1'b0;
exponent_mem_api_wr = 1'b0;
message_mem_api_rst = 1'b0;
message_mem_api_cs = 1'b0;
message_mem_api_wr = 1'b0;
result_mem_api_rst = 1'b0;
result_mem_api_cs = 1'b0;
tmp_read_data = 32'h00000000;
if (cs)
begin
if (we)
begin
case (address)
ADDR_CTRL:
begin
start_new = write_data[0];
end
ADDR_MODULUS_LENGTH:
begin
modulus_length_we = 1'b1;
end
ADDR_EXPONENT_LENGTH:
begin
exponent_length_we = 1'b1;
end
ADDR_MODULUS_PTR_RST:
begin
modulus_mem_api_rst = 1'b1;
end
ADDR_MODULUS_DATA:
begin
modulus_mem_api_cs = 1'b1;
modulus_mem_api_wr = 1'b1;
end
ADDR_EXPONENT_PTR_RST:
begin
exponent_mem_api_rst = 1'b1;
end
ADDR_EXPONENT_DATA:
begin
exponent_mem_api_cs = 1'b1;
exponent_mem_api_wr = 1'b1;
end
ADDR_MESSAGE_PTR_RST:
begin
message_mem_api_rst = 1'b1;
end
ADDR_MESSAGE_DATA:
begin
message_mem_api_cs = 1'b1;
message_mem_api_wr = 1'b1;
end
ADDR_RESULT_PTR_RST:
begin
result_mem_api_rst = 1'b1;
end
default:
begin
end
endcase // case (address[7 : 0])
end // if (we)
else
begin
case (address)
ADDR_NAME0:
tmp_read_data = CORE_NAME0;
ADDR_NAME1:
tmp_read_data = CORE_NAME1;
ADDR_VERSION:
tmp_read_data = CORE_VERSION;
ADDR_CTRL:
tmp_read_data = {31'h00000000, start_reg};
ADDR_STATUS:
tmp_read_data = {31'h00000000, ready};
ADDR_CYCLES_HIGH:
tmp_read_data = cycles[63 : 32];
ADDR_CYCLES_LOW:
tmp_read_data = cycles[31 : 0];
ADDR_MODULUS_LENGTH:
tmp_read_data = {24'h000000, modulus_length_reg};
ADDR_EXPONENT_LENGTH:
tmp_read_data = {24'h000000, exponent_length_reg};
ADDR_MODULUS_DATA:
begin
modulus_mem_api_cs = 1'b1;
tmp_read_data = modulus_mem_api_read_data;
end
ADDR_EXPONENT_DATA:
begin
exponent_mem_api_cs = 1'b1;
tmp_read_data = exponent_mem_api_read_data;
end
ADDR_MESSAGE_DATA:
begin
message_mem_api_cs = 1'b1;
tmp_read_data = message_mem_api_read_data;
end
ADDR_RESULT_DATA:
begin
result_mem_api_cs = 1'b1;
tmp_read_data = result_mem_api_read_data;
end
default:
begin
end
endcase // case (address)
end // else: !if(we)
end // if (cs)
end // block: api
endmodule // modexp
//======================================================================
// EOF modexp.v
//======================================================================
|
//======================================================================
//
// modexp_core.v
// -------------
// Modular exponentiation core for implementing public key algorithms
// such as RSA, DH, ElGamal etc.
//
// The core calculates the following function:
//
// C = M ** e mod N
//
// M is a message with a length of n bits
// e is the exponent with a length of m bits
// N is the modulus with a length of n bits
//
// n can be 32 and up to and including 8192 bits in steps
// of 32 bits.
// m can be one and up to and including 8192 bits in steps
// of 32 bits.
//
// The core has access ports for the exponent, modulus, message and
// result memories.
//
//
// Author: Joachim Strombergson, Peter Magnusson
// Copyright (c) 2015, NORDUnet A/S
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
//======================================================================
module modexp_core #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire reset_n,
input wire start,
output wire ready,
input wire [07 : 0] exponent_length,
input wire [07 : 0] modulus_length,
output wire [63 : 0] cycles,
input wire exponent_mem_api_cs,
input wire exponent_mem_api_wr,
input wire exponent_mem_api_rst,
input wire [31 : 0] exponent_mem_api_write_data,
output wire [31 : 0] exponent_mem_api_read_data,
input wire modulus_mem_api_cs,
input wire modulus_mem_api_wr,
input wire modulus_mem_api_rst,
input wire [31 : 0] modulus_mem_api_write_data,
output wire [31 : 0] modulus_mem_api_read_data,
input wire message_mem_api_cs,
input wire message_mem_api_wr,
input wire message_mem_api_rst,
input wire [31 : 0] message_mem_api_write_data,
output wire [31 : 0] message_mem_api_read_data,
input wire result_mem_api_cs,
input wire result_mem_api_rst,
output wire [31 : 0] result_mem_api_read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam MONTPROD_SELECT_ONE_NR = 3'h0;
localparam MONTPROD_SELECT_X_NR = 3'h1;
localparam MONTPROD_SELECT_Z_P = 3'h2;
localparam MONTPROD_SELECT_P_P = 3'h3;
localparam MONTPROD_SELECT_Z_ONE = 3'h4;
localparam MONTPROD_DEST_Z = 2'b00;
localparam MONTPROD_DEST_P = 2'b01;
localparam MONTPROD_DEST_NOWHERE = 2'b10;
localparam CTRL_IDLE = 4'h0;
localparam CTRL_RESIDUE = 4'h1;
localparam CTRL_CALCULATE_Z0 = 4'h2;
localparam CTRL_CALCULATE_P0 = 4'h3;
localparam CTRL_ITERATE = 4'h4;
localparam CTRL_ITERATE_Z_P = 4'h5;
localparam CTRL_ITERATE_P_P = 4'h6;
localparam CTRL_ITERATE_END = 4'h7;
localparam CTRL_CALCULATE_ZN = 4'h8;
localparam CTRL_DONE = 4'h9;
//for rsa, c=M^65537 etc, there is no need to slow down to hide the exponent
localparam EXPONATION_MODE_SECRET_SECURE = 1'b0;
localparam EXPONATION_MODE_PUBLIC_FAST = 1'b1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg ready_reg;
reg ready_new;
reg ready_we;
reg [2 : 0] montprod_select_reg;
reg [2 : 0] montprod_select_new;
reg montprod_select_we;
reg [1 : 0] montprod_dest_reg;
reg [1 : 0] montprod_dest_new;
reg montprod_dest_we;
reg [3 : 0] modexp_ctrl_reg;
reg [3 : 0] modexp_ctrl_new;
reg modexp_ctrl_we;
reg [31 : 0] one_reg;
reg [31 : 0] one_new;
reg [31 : 0] b_one_reg;
reg [31 : 0] b_one_new;
reg [12 : 0] loop_counter_reg;
reg [12 : 0] loop_counter_new;
reg loop_counter_we;
reg [07 : 0] E_word_index;
reg [04 : 0] E_bit_index;
reg last_iteration;
reg ei_reg;
reg ei_new;
reg ei_we;
reg exponation_mode_reg;
reg exponation_mode_new;
reg exponation_mode_we;
reg [31 : 0] cycle_ctr_low_reg;
reg [31 : 0] cycle_ctr_low_new;
reg cycle_ctr_low_we;
reg [31 : 0] cycle_ctr_high_reg;
reg [31 : 0] cycle_ctr_high_new;
reg cycle_ctr_high_we;
reg cycle_ctr_state_reg;
reg cycle_ctr_state_new;
reg cycle_ctr_state_we;
reg cycle_ctr_start;
reg cycle_ctr_stop;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [07 : 0] modulus_mem_int_rd_addr;
wire [31 : 0] modulus_mem_int_rd_data;
reg [07 : 0] message_mem_int_rd_addr;
wire [31 : 0] message_mem_int_rd_data;
reg [07 : 0] exponent_mem_int_rd_addr;
wire [31 : 0] exponent_mem_int_rd_data;
reg [07 : 0] result_mem_int_rd_addr;
wire [31 : 0] result_mem_int_rd_data;
reg [07 : 0] result_mem_int_wr_addr;
reg [31 : 0] result_mem_int_wr_data;
reg result_mem_int_we;
reg [07 : 0] p_mem_rd0_addr;
wire [31 : 0] p_mem_rd0_data;
reg [07 : 0] p_mem_rd1_addr;
wire [31 : 0] p_mem_rd1_data;
reg [07 : 0] p_mem_wr_addr;
reg [31 : 0] p_mem_wr_data;
reg p_mem_we;
reg [31 : 0] tmp_read_data;
reg montprod_calc;
wire montprod_ready;
reg [07 : 0] montprod_length;
wire [07 : 0] montprod_opa_addr;
reg [31 : 0] montprod_opa_data;
wire [07 : 0] montprod_opb_addr;
reg [31 : 0] montprod_opb_data;
wire [07 : 0] montprod_opm_addr;
reg [31 : 0] montprod_opm_data;
wire [07 : 0] montprod_result_addr;
wire [31 : 0] montprod_result_data;
wire montprod_result_we;
reg residue_calculate;
wire residue_ready;
reg [14 : 0] residue_nn;
reg [07 : 0] residue_length;
wire [07 : 0] residue_opa_rd_addr;
wire [31 : 0] residue_opa_rd_data;
wire [07 : 0] residue_opa_wr_addr;
wire [31 : 0] residue_opa_wr_data;
wire residue_opa_wr_we;
wire [07 : 0] residue_opm_addr;
reg [31 : 0] residue_opm_data;
reg [07 : 0] residue_mem_montprod_read_addr;
wire [31 : 0] residue_mem_montprod_read_data;
reg residue_valid_reg;
reg residue_valid_new;
reg residue_valid_int_validated;
wire [7 : 0] modulus_length_m1;
wire [7 : 0] exponent_length_m1;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_reg;
assign cycles = {cycle_ctr_high_reg, cycle_ctr_low_reg};
assign modulus_length_m1 = modulus_length - 8'h1;
assign exponent_length_m1 = exponent_length - 8'h1;
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
montprod #(.OPW(OPW), .ADW(ADW))
montprod_inst(
.clk(clk),
.reset_n(reset_n),
.calculate(montprod_calc),
.ready(montprod_ready),
.length(montprod_length),
.opa_addr(montprod_opa_addr),
.opa_data(montprod_opa_data),
.opb_addr(montprod_opb_addr),
.opb_data(montprod_opb_data),
.opm_addr(montprod_opm_addr),
.opm_data(montprod_opm_data),
.result_addr(montprod_result_addr),
.result_data(montprod_result_data),
.result_we(montprod_result_we)
);
residue #(.OPW(OPW), .ADW(ADW))
residue_inst(
.clk(clk),
.reset_n(reset_n),
.calculate(residue_calculate),
.ready(residue_ready),
.nn(residue_nn),
.length(residue_length),
.opa_rd_addr(residue_opa_rd_addr),
.opa_rd_data(residue_opa_rd_data),
.opa_wr_addr(residue_opa_wr_addr),
.opa_wr_data(residue_opa_wr_data),
.opa_wr_we(residue_opa_wr_we),
.opm_addr(residue_opm_addr),
.opm_data(residue_opm_data)
);
blockmem2r1w #(.OPW(OPW), .ADW(ADW))
residue_mem(
.clk(clk),
.read_addr0(residue_opa_rd_addr),
.read_data0(residue_opa_rd_data),
.read_addr1(residue_mem_montprod_read_addr),
.read_data1(residue_mem_montprod_read_data),
.wr(residue_opa_wr_we),
.write_addr(residue_opa_wr_addr),
.write_data(residue_opa_wr_data)
);
blockmem2r1w #(.OPW(OPW), .ADW(ADW))
p_mem(
.clk(clk),
.read_addr0(p_mem_rd0_addr),
.read_data0(p_mem_rd0_data),
.read_addr1(p_mem_rd1_addr),
.read_data1(p_mem_rd1_data),
.wr(p_mem_we),
.write_addr(p_mem_wr_addr),
.write_data(p_mem_wr_data)
);
blockmem2r1wptr #(.OPW(OPW), .ADW(ADW))
exponent_mem(
.clk(clk),
.reset_n(reset_n),
.read_addr0(exponent_mem_int_rd_addr),
.read_data0(exponent_mem_int_rd_data),
.read_data1(exponent_mem_api_read_data),
.rst(exponent_mem_api_rst),
.cs(exponent_mem_api_cs),
.wr(exponent_mem_api_wr),
.write_data(exponent_mem_api_write_data)
);
blockmem2r1wptr #(.OPW(OPW), .ADW(ADW))
modulus_mem(
.clk(clk),
.reset_n(reset_n),
.read_addr0(modulus_mem_int_rd_addr),
.read_data0(modulus_mem_int_rd_data),
.read_data1(modulus_mem_api_read_data),
.rst(modulus_mem_api_rst),
.cs(modulus_mem_api_cs),
.wr(modulus_mem_api_wr),
.write_data(modulus_mem_api_write_data)
);
blockmem2r1wptr #(.OPW(OPW), .ADW(ADW))
message_mem(
.clk(clk),
.reset_n(reset_n),
.read_addr0(message_mem_int_rd_addr),
.read_data0(message_mem_int_rd_data),
.read_data1(message_mem_api_read_data),
.rst(message_mem_api_rst),
.cs(message_mem_api_cs),
.wr(message_mem_api_wr),
.write_data(message_mem_api_write_data)
);
blockmem2rptr1w #(.OPW(OPW), .ADW(ADW))
result_mem(
.clk(clk),
.reset_n(reset_n),
.read_addr0(result_mem_int_rd_addr[7 : 0]),
.read_data0(result_mem_int_rd_data),
.read_data1(result_mem_api_read_data),
.rst(result_mem_api_rst),
.cs(result_mem_api_cs),
.wr(result_mem_int_we),
.write_addr(result_mem_int_wr_addr),
.write_data(result_mem_int_wr_data)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
ready_reg <= 1'b1;
montprod_select_reg <= MONTPROD_SELECT_ONE_NR;
montprod_dest_reg <= MONTPROD_DEST_NOWHERE;
modexp_ctrl_reg <= CTRL_IDLE;
one_reg <= 32'h0;
b_one_reg <= 32'h0;
loop_counter_reg <= 13'b0;
ei_reg <= 1'b0;
residue_valid_reg <= 1'b0;
exponation_mode_reg <= EXPONATION_MODE_SECRET_SECURE;
cycle_ctr_low_reg <= 32'h00000000;
cycle_ctr_high_reg <= 32'h00000000;
cycle_ctr_state_reg <= 1'b0;
end
else
begin
one_reg <= one_new;
b_one_reg <= b_one_new;
residue_valid_reg <= residue_valid_new;
if (ready_we)
ready_reg <= ready_new;
if (montprod_select_we)
montprod_select_reg <= montprod_select_new;
if (montprod_dest_we)
montprod_dest_reg <= montprod_dest_new;
if (loop_counter_we)
loop_counter_reg <= loop_counter_new;
if (ei_we)
ei_reg <= ei_new;
if (exponation_mode_we)
exponation_mode_reg <= exponation_mode_new;
if (cycle_ctr_low_we)
cycle_ctr_low_reg <= cycle_ctr_low_new;
if (cycle_ctr_high_we)
cycle_ctr_high_reg <= cycle_ctr_high_new;
if (cycle_ctr_state_we)
cycle_ctr_state_reg <= cycle_ctr_state_new;
if (modexp_ctrl_we)
modexp_ctrl_reg <= modexp_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// cycle_ctr
//
// Implementation of the cycle counter
//----------------------------------------------------------------
always @*
begin : cycle_ctr
cycle_ctr_low_new = 32'h00000000;
cycle_ctr_low_we = 1'b0;
cycle_ctr_high_new = 32'h00000000;
cycle_ctr_high_we = 1'b0;
cycle_ctr_state_new = 1'b0;
cycle_ctr_state_we = 1'b0;
if (cycle_ctr_start)
begin
cycle_ctr_low_new = 32'h00000000;
cycle_ctr_low_we = 1'b1;
cycle_ctr_high_new = 32'h00000000;
cycle_ctr_high_we = 1'b1;
cycle_ctr_state_new = 1'b1;
cycle_ctr_state_we = 1'b1;
end
if (cycle_ctr_stop)
begin
cycle_ctr_state_new = 1'b0;
cycle_ctr_state_we = 1'b1;
end
if (cycle_ctr_state_reg)
begin
cycle_ctr_low_new = cycle_ctr_low_reg + 1'b1;
cycle_ctr_low_we = 1'b1;
if (cycle_ctr_low_new == 32'h00000000)
begin
cycle_ctr_high_new = cycle_ctr_high_reg + 1'b1;
cycle_ctr_high_we = 1'b1;
end
end
end // cycle_ctr
//----------------------------------------------------------------
// one
//
// generates the big integer one ( 00... 01 )
//----------------------------------------------------------------
always @*
begin : one_process
one_new = 32'h00000000;
b_one_new = 32'h00000000;
if (montprod_opa_addr == modulus_length_m1)
one_new = 32'h00000001;
if (montprod_opb_addr == modulus_length_m1)
b_one_new = 32'h00000001;
end
//----------------------------------------------------------------
// Read mux for modulus. Needed since it is being
// addressed by two sources.
//----------------------------------------------------------------
always @*
begin : modulus_mem_reader_process
if (modexp_ctrl_reg == CTRL_RESIDUE)
modulus_mem_int_rd_addr = residue_opm_addr;
else
modulus_mem_int_rd_addr = montprod_opm_addr;
end
//----------------------------------------------------------------
// Feeds residue calculator.
//----------------------------------------------------------------
always @*
begin : residue_process
//N*2, N=length*32, *32 = shl5, *64 = shl6
residue_nn = { 1'b0, modulus_length, 6'h0 };
residue_length = modulus_length;
residue_opm_data = modulus_mem_int_rd_data;
end
//----------------------------------------------------------------
// Detects if modulus has been updated and we need to
// recalculate the residue
// and we need residue is valid or not.
//----------------------------------------------------------------
always @*
begin : residue_valid_process
residue_valid_new = residue_valid_reg;
if (modulus_mem_api_cs & modulus_mem_api_wr)
residue_valid_new = 1'b0;
else if ( residue_valid_int_validated == 1'b1)
residue_valid_new = 1'b1;
end
//----------------------------------------------------------------
// montprod_op_select
//
// Select operands used during montprod calculations depending
// on what operation we want to do.
//----------------------------------------------------------------
always @*
begin : montprod_op_select
montprod_length = modulus_length;
result_mem_int_rd_addr = montprod_opa_addr;
message_mem_int_rd_addr = montprod_opa_addr;
p_mem_rd0_addr = montprod_opa_addr;
residue_mem_montprod_read_addr = montprod_opb_addr;
p_mem_rd1_addr = montprod_opb_addr;
montprod_opm_data = modulus_mem_int_rd_data;
case (montprod_select_reg)
MONTPROD_SELECT_ONE_NR:
begin
montprod_opa_data = one_reg;
montprod_opb_data = residue_mem_montprod_read_data;
end
MONTPROD_SELECT_X_NR:
begin
montprod_opa_data = message_mem_int_rd_data;
montprod_opb_data = residue_mem_montprod_read_data;
end
MONTPROD_SELECT_Z_P:
begin
montprod_opa_data = result_mem_int_rd_data;
montprod_opb_data = p_mem_rd1_data;
end
MONTPROD_SELECT_P_P:
begin
montprod_opa_data = p_mem_rd0_data;
montprod_opb_data = p_mem_rd1_data;
end
MONTPROD_SELECT_Z_ONE:
begin
montprod_opa_data = result_mem_int_rd_data;
montprod_opb_data = b_one_reg;
end
default:
begin
montprod_opa_data = 32'h00000000;
montprod_opb_data = 32'h00000000;
end
endcase // case (montprod_selcect_reg)
end
//----------------------------------------------------------------
// memory write mux
//
// Direct memory write signals to correct memory.
//----------------------------------------------------------------
always @*
begin : memory_write_process
result_mem_int_wr_addr = montprod_result_addr;
result_mem_int_wr_data = montprod_result_data;
result_mem_int_we = 1'b0;
p_mem_wr_addr = montprod_result_addr;
p_mem_wr_data = montprod_result_data;
p_mem_we = 1'b0;
case (montprod_dest_reg)
MONTPROD_DEST_Z:
result_mem_int_we = montprod_result_we;
MONTPROD_DEST_P:
p_mem_we = montprod_result_we;
default:
begin
end
endcase
// inhibit Z=Z*P when ei = 0
if (modexp_ctrl_reg == CTRL_ITERATE_Z_P)
result_mem_int_we = result_mem_int_we & ei_reg;
end
//----------------------------------------------------------------
// loop_counter
//
// Calculate the loop counter and related variables.
//----------------------------------------------------------------
always @*
begin : loop_counters_process
loop_counter_new = 13'b0;
loop_counter_we = 1'b0;
if (loop_counter_reg == {exponent_length_m1, 5'b11111})
last_iteration = 1'b1;
else
last_iteration = 1'b0;
case (modexp_ctrl_reg)
CTRL_CALCULATE_P0:
begin
loop_counter_new = 13'b0;
loop_counter_we = 1'b1;
end
CTRL_ITERATE_END:
begin
loop_counter_new = loop_counter_reg + 1'b1;
loop_counter_we = 1'b1;
end
default:
begin
end
endcase
end
//----------------------------------------------------------------
// exponent
//
// Reads the exponent.
//----------------------------------------------------------------
always @*
begin : exponent_process
// Accessing new instead of reg - pick up update at
// CTRL_ITERATE_NEW to remove a pipeline stall.
E_word_index = exponent_length_m1 - loop_counter_new[ 12 : 5 ];
E_bit_index = loop_counter_reg[ 04 : 0 ];
exponent_mem_int_rd_addr = E_word_index;
ei_new = exponent_mem_int_rd_data[ E_bit_index ];
if (modexp_ctrl_reg == CTRL_ITERATE)
ei_we = 1'b1;
else
ei_we = 1'b0;
end
//----------------------------------------------------------------
// modexp_ctrl
//
// Control FSM logic needed to perform the modexp operation.
//----------------------------------------------------------------
always @*
begin
ready_new = 1'b0;
ready_we = 1'b0;
montprod_select_new = MONTPROD_SELECT_ONE_NR;
montprod_select_we = 0;
montprod_dest_new = MONTPROD_DEST_NOWHERE;
montprod_dest_we = 0;
montprod_calc = 0;
modexp_ctrl_new = CTRL_IDLE;
modexp_ctrl_we = 1'b0;
cycle_ctr_start = 1'b0;
cycle_ctr_stop = 1'b0;
residue_calculate = 1'b0;
residue_valid_int_validated = 1'b0;
case (modexp_ctrl_reg)
CTRL_IDLE:
begin
if (start)
begin
ready_new = 1'b0;
ready_we = 1'b1;
cycle_ctr_start = 1'b1;
if (residue_valid_reg)
begin
//residue has alrady been calculated, start with MONTPROD( 1, Nr, MODULUS )
montprod_select_new = MONTPROD_SELECT_ONE_NR;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_Z;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_CALCULATE_Z0;
modexp_ctrl_we = 1;
end
else
begin
//modulus has been written and residue (Nr) must be calculated
modexp_ctrl_new = CTRL_RESIDUE;
modexp_ctrl_we = 1;
residue_calculate = 1'b1;
end
end
end
CTRL_RESIDUE:
begin
if (residue_ready)
begin
montprod_select_new = MONTPROD_SELECT_ONE_NR;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_Z;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_CALCULATE_Z0;
modexp_ctrl_we = 1;
residue_valid_int_validated = 1'b1; //update registers telling residue is valid
end
end
CTRL_CALCULATE_Z0:
begin
if (montprod_ready)
begin
montprod_select_new = MONTPROD_SELECT_X_NR;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_P;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_CALCULATE_P0;
modexp_ctrl_we = 1;
end
end
CTRL_CALCULATE_P0:
begin
if (montprod_ready == 1'b1)
begin
modexp_ctrl_new = CTRL_ITERATE;
modexp_ctrl_we = 1;
end
end
CTRL_ITERATE:
begin
montprod_select_new = MONTPROD_SELECT_Z_P;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_Z;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_ITERATE_Z_P;
modexp_ctrl_we = 1;
if (ei_new == 1'b0 && exponation_mode_reg == EXPONATION_MODE_PUBLIC_FAST)
begin
//Skip the fake montgomery calculation, exponation_mode_reg optimizing for speed not blinding.
montprod_select_new = MONTPROD_SELECT_P_P;
montprod_dest_new = MONTPROD_DEST_P;
modexp_ctrl_new = CTRL_ITERATE_P_P;
end
end
CTRL_ITERATE_Z_P:
if (montprod_ready)
begin
montprod_select_new = MONTPROD_SELECT_P_P;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_P;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_ITERATE_P_P;
modexp_ctrl_we = 1;
end
CTRL_ITERATE_P_P:
if (montprod_ready == 1'b1)
begin
modexp_ctrl_new = CTRL_ITERATE_END;
modexp_ctrl_we = 1;
end
CTRL_ITERATE_END:
begin
if (!last_iteration)
begin
modexp_ctrl_new = CTRL_ITERATE;
modexp_ctrl_we = 1;
end
else
begin
montprod_select_new = MONTPROD_SELECT_Z_ONE;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_Z;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_CALCULATE_ZN;
modexp_ctrl_we = 1;
end
end
CTRL_CALCULATE_ZN:
begin
if (montprod_ready)
begin
modexp_ctrl_new = CTRL_DONE;
modexp_ctrl_we = 1;
end
end
CTRL_DONE:
begin
cycle_ctr_stop = 1'b1;
ready_new = 1'b1;
ready_we = 1'b1;
modexp_ctrl_new = CTRL_IDLE;
modexp_ctrl_we = 1;
end
default:
begin
end
endcase // case (modexp_ctrl_reg)
end
endmodule // modexp_core
//======================================================================
// EOF modexp_core.v
//======================================================================
|
module rsa_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i; //Address
input wb_cyc_i; //bus cycle
input [dw-1:0] wb_dat_i; //Data IN
input [3:0] wb_sel_i; //Select Input Array
input wb_stb_i; //Chip Select
input wb_we_i; //Write Or Read Enabled
output wb_ack_o; //Acknowledge
output wb_err_o; //Error
output reg [dw-1:0] wb_dat_o; //Data OUT
output int_o; //Interrupt
input wb_clk_i; //Clk
input wb_rst_i; //Reset
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
wire reset_n=!wb_rst_i;
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// The operand width is the internal operand width in bits.
// The address width is the size of the address space used. This
// value must be balances with OPERAND_WIDTH to allow a total
// of 8192 bits of data. OPERAND_WIDTH * (ADDRESS_WIDTH ** 2)
// is the formula. Note that the API data with is always 32 bits.
localparam OPERAND_WIDTH = 32;
localparam ADDRESS_WIDTH = 8;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_CYCLES_HIGH = 8'h10;
localparam ADDR_CYCLES_LOW = 8'h11;
localparam ADDR_MODULUS_LENGTH = 8'h20;
localparam ADDR_EXPONENT_LENGTH = 8'h21;
localparam ADDR_MODULUS_PTR_RST = 8'h30;
localparam ADDR_MODULUS_DATA = 8'h31;
localparam ADDR_EXPONENT_PTR_RST = 8'h40;
localparam ADDR_EXPONENT_DATA = 8'h41;
localparam ADDR_MESSAGE_PTR_RST = 8'h50;
localparam ADDR_MESSAGE_DATA = 8'h51;
localparam ADDR_RESULT_PTR_RST = 8'h60;
localparam ADDR_RESULT_DATA = 8'h61;
localparam DEFAULT_MODLENGTH = 8'h80; // 2048 bits.
localparam DEFAULT_EXPLENGTH = 8'h80;
localparam CORE_NAME0 = 32'h6d6f6465; // "mode"
localparam CORE_NAME1 = 32'h78702020; // "xp "
localparam CORE_VERSION = 32'h302e3532; // "0.52"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [07 : 0] exponent_length_reg;
reg [07 : 0] exponent_length_new;
reg exponent_length_we;
reg [07 : 0] modulus_length_reg;
reg [07 : 0] modulus_length_new;
reg modulus_length_we;
reg start_reg;
reg start_new;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg exponent_mem_api_rst;
reg exponent_mem_api_cs;
reg exponent_mem_api_wr;
wire [31 : 0] exponent_mem_api_read_data;
reg modulus_mem_api_rst;
reg modulus_mem_api_cs;
reg modulus_mem_api_wr;
wire [31 : 0] modulus_mem_api_read_data;
reg message_mem_api_rst;
reg message_mem_api_cs;
reg message_mem_api_wr;
wire [31 : 0] message_mem_api_read_data;
reg result_mem_api_rst;
reg result_mem_api_cs;
wire [31 : 0] result_mem_api_read_data;
wire ready;
wire [63 : 0] cycles;
//reg [31 : 0] wb_dat_o;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
//assign wb_dat_o = wb_dat_o;
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
modexp_core #(.OPW(OPERAND_WIDTH), .ADW(ADDRESS_WIDTH))
core_inst(
.clk(wb_clk_i),
.reset_n(reset_n),
.start(start_reg),
.ready(ready),
.exponent_length(exponent_length_reg),
.modulus_length(modulus_length_reg),
.cycles(cycles),
.exponent_mem_api_cs(exponent_mem_api_cs),
.exponent_mem_api_wr(exponent_mem_api_wr),
.exponent_mem_api_rst(exponent_mem_api_rst),
.exponent_mem_api_write_data(wb_dat_i),
.exponent_mem_api_read_data(exponent_mem_api_read_data),
.modulus_mem_api_cs(modulus_mem_api_cs),
.modulus_mem_api_wr(modulus_mem_api_wr),
.modulus_mem_api_rst(modulus_mem_api_rst),
.modulus_mem_api_write_data(wb_dat_i),
.modulus_mem_api_read_data(modulus_mem_api_read_data),
.message_mem_api_cs(message_mem_api_cs),
.message_mem_api_wr(message_mem_api_wr),
.message_mem_api_rst(message_mem_api_rst),
.message_mem_api_write_data(wb_dat_i),
.message_mem_api_read_data(message_mem_api_read_data),
.result_mem_api_cs(result_mem_api_cs),
.result_mem_api_rst(result_mem_api_rst),
.result_mem_api_read_data(result_mem_api_read_data)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge wb_clk_i or negedge reset_n)
begin
if (!reset_n)
begin
start_reg <= 1'b0;
exponent_length_reg <= DEFAULT_EXPLENGTH;
modulus_length_reg <= DEFAULT_MODLENGTH;
end
else
begin
start_reg <= start_new;
if (exponent_length_we)
begin
exponent_length_reg <= wb_dat_i[7 : 0];
end
if (modulus_length_we)
begin
modulus_length_reg <= wb_dat_i[7 : 0];
end
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
modulus_length_we = 1'b0;
exponent_length_we = 1'b0;
start_new = 1'b0;
modulus_mem_api_rst = 1'b0;
modulus_mem_api_cs = 1'b0;
modulus_mem_api_wr = 1'b0;
exponent_mem_api_rst = 1'b0;
exponent_mem_api_cs = 1'b0;
exponent_mem_api_wr = 1'b0;
message_mem_api_rst = 1'b0;
message_mem_api_cs = 1'b0;
message_mem_api_wr = 1'b0;
result_mem_api_rst = 1'b0;
result_mem_api_cs = 1'b0;
wb_dat_o = 32'h00000000;
if (wb_stb_i)
begin
if (wb_we_i)
begin
case (wb_adr_i[9:2])
ADDR_CTRL:
begin
start_new = wb_dat_i[0];
end
ADDR_MODULUS_LENGTH:
begin
modulus_length_we = 1'b1;
end
ADDR_EXPONENT_LENGTH:
begin
exponent_length_we = 1'b1;
end
ADDR_MODULUS_PTR_RST:
begin
modulus_mem_api_rst = 1'b1;
end
ADDR_MODULUS_DATA:
begin
modulus_mem_api_cs = 1'b1;
modulus_mem_api_wr = 1'b1;
end
ADDR_EXPONENT_PTR_RST:
begin
exponent_mem_api_rst = 1'b1;
end
ADDR_EXPONENT_DATA:
begin
exponent_mem_api_cs = 1'b1;
exponent_mem_api_wr = 1'b1;
end
ADDR_MESSAGE_PTR_RST:
begin
message_mem_api_rst = 1'b1;
end
ADDR_MESSAGE_DATA:
begin
message_mem_api_cs = 1'b1;
message_mem_api_wr = 1'b1;
end
ADDR_RESULT_PTR_RST:
begin
result_mem_api_rst = 1'b1;
end
default:
begin
end
endcase // case (wb_adr_i[7 : 0])
end // if (wb_we_i)
else
begin
case (wb_adr_i[9:2])
ADDR_NAME0:
wb_dat_o = CORE_NAME0;
ADDR_NAME1:
wb_dat_o = CORE_NAME1;
ADDR_VERSION:
wb_dat_o = CORE_VERSION;
ADDR_CTRL:
wb_dat_o = {31'h00000000, start_reg};
ADDR_STATUS:
wb_dat_o = {31'h00000000, ready};
ADDR_CYCLES_HIGH:
wb_dat_o = cycles[63 : 32];
ADDR_CYCLES_LOW:
wb_dat_o = cycles[31 : 0];
ADDR_MODULUS_LENGTH:
wb_dat_o = {24'h000000, modulus_length_reg};
ADDR_EXPONENT_LENGTH:
wb_dat_o = {24'h000000, exponent_length_reg};
ADDR_MODULUS_DATA:
begin
modulus_mem_api_cs = 1'b1;
wb_dat_o = modulus_mem_api_read_data;
end
ADDR_EXPONENT_DATA:
begin
exponent_mem_api_cs = 1'b1;
wb_dat_o = exponent_mem_api_read_data;
end
ADDR_MESSAGE_DATA:
begin
message_mem_api_cs = 1'b1;
wb_dat_o = message_mem_api_read_data;
end
ADDR_RESULT_DATA:
begin
result_mem_api_cs = 1'b1;
wb_dat_o = result_mem_api_read_data;
end
default:
begin
end
endcase // case (wb_adr_i)
end // else: !if(wb_we_i)
end // if (wb_stb_i)
end // block: api
endmodule // modexp
//======================================================================
// EOF modexp_top.v
//======================================================================
|
//======================================================================
//
// montprod.v
// ---------
// Montgomery product calculator for the modular exponentiantion core.
//
// parameter OPW is operand word width in bits.
// parameter ADW is address width in bits.
//
//
// Author: Peter Magnusson, Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module montprod #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire reset_n,
input wire calculate,
output wire ready,
input wire [(ADW - 1) : 0] length,
output wire [(ADW - 1) : 0] opa_addr,
input wire [(OPW - 1) : 0] opa_data,
output wire [(ADW - 1) : 0] opb_addr,
input wire [(OPW - 1) : 0] opb_data,
output wire [(ADW - 1) : 0] opm_addr,
input wire [(OPW - 1) : 0] opm_data,
output wire [(ADW - 1) : 0] result_addr,
output wire [(OPW - 1) : 0] result_data,
output wire result_we
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam CTRL_IDLE = 4'h0;
localparam CTRL_LOOP_ITER = 4'h1;
localparam CTRL_LOOP_BQ = 4'h2;
localparam CTRL_CALC_ADD = 4'h3;
localparam CTRL_STALLPIPE_ADD = 4'h4;
localparam CTRL_CALC_SDIV2 = 4'h5;
localparam CTRL_STALLPIPE_SDIV2 = 4'h6;
localparam CTRL_L_STALLPIPE_ES = 4'h7;
localparam CTRL_EMIT_S = 4'h8;
localparam SMUX_ZERO = 2'h0;
localparam SMUX_ADD = 2'h1;
localparam SMUX_SHR = 2'h2;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg ready_reg;
reg ready_new;
reg ready_we;
reg [3 : 0] montprod_ctrl_reg;
reg [3 : 0] montprod_ctrl_new;
reg montprod_ctrl_we;
reg [1 : 0] s_mux_new;
reg [1 : 0] s_mux_reg;
reg s_mem_we_reg;
reg s_mem_we_new;
reg [(ADW - 1) : 0] s_mem_read_addr_reg;
reg q_new;
reg q_reg;
reg b_new;
reg b_reg;
reg bq_we;
reg [12 : 0] loop_ctr_reg;
reg [12 : 0] loop_ctr_new;
reg loop_ctr_we;
reg loop_ctr_set;
reg loop_ctr_dec;
reg [(13 - ADW - 1) : 0] b_bit_index_reg;
reg [(13 - ADW - 1) : 0] b_bit_index_new;
reg b_bit_index_we;
reg [(ADW - 1) : 0] word_index_reg;
reg [(ADW - 1) : 0] word_index_new;
reg word_index_we;
reg [(ADW - 1) : 0] word_index_prev_reg;
reg reset_word_index_lsw;
reg reset_word_index_msw;
reg inc_word_index;
reg dec_word_index;
reg add_carry_in_sa_reg;
reg add_carry_in_sa_new;
reg add_carry_in_sm_reg;
reg add_carry_in_sm_new;
reg shr_carry_in_reg;
reg shr_carry_in_new;
reg first_iteration_reg;
reg first_iteration_new;
reg first_iteration_we;
reg test_reg;
reg test_new;
reg [(OPW - 2) : 0] shr_data_out_reg;
reg shr_carry_out_reg;
reg shr_carry_out_new;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [(OPW - 1) : 0] add_result_sa;
wire add_carry_out_sa;
wire [(OPW - 1) : 0] add_result_sm;
wire add_carry_out_sm;
reg [(ADW - 1) : 0] b_word_index; //loop counter as a word index
/* verilator lint_off UNOPTFLAT */
reg [(OPW - 1) : 0] shr_data_in;
/* verilator lint_on UNOPTFLAT */
wire shr_carry_out;
wire [(OPW - 1) : 0] shr_data_out;
reg [(ADW - 1) : 0] tmp_opa_addr;
reg tmp_result_we;
reg [(ADW - 1) : 0] s_mem_read_addr;
wire [(OPW - 1) : 0] s_mem_read_data;
reg [(ADW - 1) : 0] s_mem_write_addr;
reg [(OPW - 1) : 0] s_mem_write_data;
reg [(OPW - 1) : 0] tmp_s_mem_write_data;
reg [(OPW - 1) : 0] sa_adder_data_in;
/* verilator lint_off UNOPTFLAT */
reg [(OPW - 1) : 0] muxed_s_mem_read_data;
/* verilator lint_on UNOPTFLAT */
reg [(OPW - 1) : 0] shifted_s_mem_write_data;
wire [(ADW - 1) : 0] length_m1;
// Temporary debug wires.
reg [1 : 0] state_trace;
reg [1 : 0] mux_trace;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign length_m1 = length - 1'b1;
assign opa_addr = tmp_opa_addr;
assign opb_addr = b_word_index;
assign opm_addr = word_index_reg;
assign result_addr = word_index_prev_reg;
assign result_data = s_mem_read_data;
assign result_we = tmp_result_we;
assign ready = ready_reg;
//----------------------------------------------------------------
// Instantions
//----------------------------------------------------------------
blockmem1r1w #(.OPW(OPW), .ADW(ADW)) s_mem(
.clk(clk),
.read_addr(s_mem_read_addr),
.read_data(s_mem_read_data),
.wr(s_mem_we_reg),
.write_addr(s_mem_write_addr),
.write_data(s_mem_write_data)
);
adder #(.OPW(OPW)) s_adder_sm(
.a(muxed_s_mem_read_data),
.b(opm_data),
.carry_in(add_carry_in_sm_reg),
.sum(add_result_sm),
.carry_out(add_carry_out_sm)
);
adder #(.OPW(OPW)) s_adder_sa(
.a(sa_adder_data_in),
.b(opa_data),
.carry_in(add_carry_in_sa_reg),
.sum(add_result_sa),
.carry_out(add_carry_out_sa)
);
shr #(.OPW(OPW)) shifter(
.a(shr_data_in),
.carry_in(shr_carry_in_reg),
.adiv2(shr_data_out),
.carry_out(shr_carry_out)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
test_reg <= 1'b1;
ready_reg <= 1'b1;
loop_ctr_reg <= 13'h0;
word_index_reg <= {ADW{1'b0}};
word_index_prev_reg <= {ADW{1'b0}};
add_carry_in_sa_reg <= 1'b0;
add_carry_in_sm_reg <= 1'b0;
shr_data_out_reg <= {(OPW - 1){1'b0}};
shr_carry_in_reg <= 1'b0;
b_reg <= 1'b0;
q_reg <= 1'b0;
s_mux_reg <= SMUX_ZERO;
s_mem_we_reg <= 1'b0;
s_mem_read_addr_reg <= {ADW{1'b0}};
b_bit_index_reg <= {(13 - ADW){1'b0}};
first_iteration_reg <= 1'b0;
montprod_ctrl_reg <= CTRL_IDLE;
end
else
begin
test_reg <= test_new;
s_mem_read_addr_reg <= s_mem_read_addr;
s_mem_we_reg <= s_mem_we_new;
s_mux_reg <= s_mux_new;
word_index_prev_reg <= word_index_reg;
shr_carry_in_reg <= shr_carry_in_new;
add_carry_in_sa_reg <= add_carry_in_sa_new;
add_carry_in_sm_reg <= add_carry_in_sm_new;
shr_data_out_reg <= shr_data_out[(OPW - 2) : 0];
if (word_index_we)
word_index_reg <= word_index_new;
if (first_iteration_we)
first_iteration_reg <= first_iteration_new;
if (b_bit_index_we)
b_bit_index_reg <= b_bit_index_new;
if (bq_we)
begin
b_reg <= b_new;
q_reg <= q_new;
end
if (ready_we)
ready_reg <= ready_new;
if (loop_ctr_we)
loop_ctr_reg <= loop_ctr_new;
if (montprod_ctrl_we)
begin
montprod_ctrl_reg <= montprod_ctrl_new;
end
end
end // reg_update
//----------------------------------------------------------------
// s_logic
//
// Logic to calculate S memory updates including address
// and write enable. This is the main montprod datapath.
//----------------------------------------------------------------
always @*
begin : s_logic
shr_carry_in_new = 1'b0;
muxed_s_mem_read_data = {OPW{1'b0}};
sa_adder_data_in = {OPW{1'b0}};
add_carry_in_sa_new = 1'b0;
add_carry_in_sm_new = 1'b0;
s_mem_read_addr = word_index_reg;
s_mem_write_addr = s_mem_read_addr_reg;
s_mem_write_data = {OPW{1'b0}};
s_mem_we_new = 1'b0;
state_trace = 0;
mux_trace = 0;
tmp_s_mem_write_data = {OPW{1'b0}};
test_new = 1'b0;
case (montprod_ctrl_reg)
CTRL_LOOP_ITER:
begin
s_mem_read_addr = length_m1;
end
CTRL_CALC_ADD:
begin
//s = (s + q*M + b*A) >>> 1;, if(b==1) S+= A. Takes (1..length) cycles.
s_mem_we_new = b_reg | q_reg | first_iteration_reg;
state_trace = 1;
test_new = 1'b1;
end
CTRL_CALC_SDIV2:
begin
//s = (s + q*M + b*A) >>> 1; s>>=1. Takes (1..length) cycles.
s_mem_we_new = 1'b1;
end
default:
begin
end
endcase
case (s_mux_reg)
SMUX_ADD:
begin
mux_trace = 1;
if (first_iteration_reg)
muxed_s_mem_read_data = {OPW{1'b0}};
else
muxed_s_mem_read_data = s_mem_read_data;
if (q_reg)
sa_adder_data_in = add_result_sm;
else
sa_adder_data_in = muxed_s_mem_read_data;
if (b_reg)
tmp_s_mem_write_data = add_result_sa;
else if (q_reg)
tmp_s_mem_write_data = add_result_sm;
else if (first_iteration_reg)
tmp_s_mem_write_data = {OPW{1'b0}};
s_mem_write_data = tmp_s_mem_write_data;
add_carry_in_sa_new = add_carry_out_sa;
add_carry_in_sm_new = add_carry_out_sm;
// Experimental integration of shift in add.
shr_data_in = tmp_s_mem_write_data;
shifted_s_mem_write_data = {shr_carry_out, shr_data_out_reg};
end
SMUX_SHR:
begin
shr_data_in = s_mem_read_data;
s_mem_write_data = shr_data_out;
shr_carry_in_new = shr_carry_out;
end
default:
begin
end
endcase
end // s_logic
//----------------------------------------------------------------
// bq
//
// Extract b and q bits.
// b: current bit of B used.
// q = (s - b * A) & 1
// update the b bit and word indices based on loop counter.
//----------------------------------------------------------------
always @*
begin : bq
b_new = opb_data[b_bit_index_reg];
if (first_iteration_reg)
q_new = 1'b0 ^ (opa_data[0] & b_new);
else
q_new = s_mem_read_data[0] ^ (opa_data[0] & b_new);
// B_bit_index = 5'h1f - loop_counter[4:0];
b_bit_index_new = ((2**(13 - ADW)) - 1'b1) - loop_ctr_reg[(13 - ADW - 1) : 0];
b_word_index = loop_ctr_reg[12 : (13 - ADW)];
end // bq
//----------------------------------------------------------------
// word_index
//
// Logic that implements the word index used to drive
// addresses for operands.
//----------------------------------------------------------------
always @*
begin : word_index
word_index_new = {ADW{1'b0}};
word_index_we = 1'b0;
if (reset_word_index_lsw)
begin
word_index_new = length_m1;
word_index_we = 1'b1;
end
if (reset_word_index_msw)
begin
word_index_new = {ADW{1'b0}};
word_index_we = 1'b1;
end
if (inc_word_index)
begin
word_index_new = word_index_reg + 1'b1;
word_index_we = 1'b1;
end
if (dec_word_index)
begin
word_index_new = word_index_reg - 1'b1;
word_index_we = 1'b1;
end
end // word_index
//----------------------------------------------------------------
// loop_ctr
// Logic for updating the loop counter.
//----------------------------------------------------------------
always @*
begin : loop_ctr
loop_ctr_new = 13'h0;
loop_ctr_we = 1'b0;
if (loop_ctr_set)
begin
loop_ctr_new = {length, {(13 - ADW){1'b0}}} - 1'b1;
loop_ctr_we = 1'b1;
end
if (loop_ctr_dec)
begin
loop_ctr_new = loop_ctr_reg - 1'b1;
loop_ctr_we = 1'b1;
end
end
//----------------------------------------------------------------
// montprod_ctrl
//
// Control FSM for the montgomery product calculator.
//----------------------------------------------------------------
always @*
begin : montprod_ctrl
ready_new = 1'b0;
ready_we = 1'b0;
loop_ctr_set = 1'b0;
loop_ctr_dec = 1'b0;
b_bit_index_we = 1'b0;
bq_we = 1'b0;
s_mux_new = SMUX_ZERO;
dec_word_index = 1'b0;
inc_word_index = 1'b0;
reset_word_index_lsw = 1'b0;
reset_word_index_msw = 1'b0;
first_iteration_new = 1'b0;
first_iteration_we = 1'b0;
tmp_opa_addr = word_index_reg;
tmp_result_we = 1'b0;
montprod_ctrl_new = CTRL_IDLE;
montprod_ctrl_we = 1'b0;
case (montprod_ctrl_reg)
CTRL_IDLE:
begin
if (calculate)
begin
first_iteration_new = 1'b1;
first_iteration_we = 1'b1;
ready_new = 1'b0;
ready_we = 1'b1;
reset_word_index_lsw = 1'b1;
loop_ctr_set = 1'b1;
montprod_ctrl_new = CTRL_LOOP_ITER;
montprod_ctrl_we = 1'b1;
end
end
//calculate q = (s - b * A) & 1;.
// Also abort loop if done.
CTRL_LOOP_ITER:
begin
tmp_opa_addr = length_m1;
b_bit_index_we = 1'b1;
montprod_ctrl_new = CTRL_LOOP_BQ;
montprod_ctrl_we = 1'b1;
end
CTRL_LOOP_BQ:
begin
reset_word_index_lsw = 1'b1;
bq_we = 1'b1;
montprod_ctrl_new = CTRL_CALC_ADD;
montprod_ctrl_we = 1'b1;
end
CTRL_CALC_ADD:
begin
s_mux_new = SMUX_ADD;
if (word_index_reg == 0)
begin
reset_word_index_lsw = 1'b1;
montprod_ctrl_new = CTRL_STALLPIPE_ADD;
montprod_ctrl_we = 1'b1;
end
else
begin
dec_word_index = 1'b1;
end
end
CTRL_STALLPIPE_ADD:
begin
first_iteration_new = 1'b0;
first_iteration_we = 1'b1;
reset_word_index_msw = 1'b1;
montprod_ctrl_new = CTRL_CALC_SDIV2;
montprod_ctrl_we = 1'b1;
end
CTRL_CALC_SDIV2:
begin
s_mux_new = SMUX_SHR;
if (word_index_reg == length_m1)
begin
montprod_ctrl_new = CTRL_STALLPIPE_SDIV2;
montprod_ctrl_we = 1'b1;
end
else
inc_word_index = 1'b1;
end
CTRL_STALLPIPE_SDIV2:
begin
loop_ctr_dec = 1'b1;
montprod_ctrl_new = CTRL_LOOP_ITER;
montprod_ctrl_we = 1'b1;
reset_word_index_lsw = 1'b1;
if (loop_ctr_reg == 0)
begin
montprod_ctrl_new = CTRL_L_STALLPIPE_ES;
montprod_ctrl_we = 1'b1;
end
end
CTRL_L_STALLPIPE_ES:
begin
montprod_ctrl_new = CTRL_EMIT_S;
montprod_ctrl_we = 1'b1;
end
CTRL_EMIT_S:
begin
dec_word_index = 1'b1;
tmp_result_we = 1'b1;
if (word_index_prev_reg == 0)
begin
ready_new = 1'b1;
ready_we = 1'b1;
montprod_ctrl_new = CTRL_IDLE;
montprod_ctrl_we = 1'b1;
end
end
default:
begin
end
endcase // case (montprod_ctrl_reg)
end // montprod_ctrl
endmodule // montprod
//======================================================================
// EOF montprod.v
//======================================================================
|
//======================================================================
//
// residue.v
// ---------
// Modulus 2**2N residue calculator for montgomery calculations.
//
// m_residue_2_2N_array( N, M, Nr)
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
// for (int i = 0; i < 2 * N; i++)
// Nr = Nr shift left 1
// if (Nr less than M) continue;
// Nr = Nr - M
// return Nr
//
//
//
// Author: Peter Magnusson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module residue #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire reset_n,
input wire calculate,
output wire ready,
input wire [14 : 0] nn, //MAX(2*N)=8192*2 (14 bit)
input wire [(ADW - 1) : 0] length,
output wire [(ADW - 1) : 0] opa_rd_addr,
input wire [(OPW - 1) : 0] opa_rd_data,
output wire [(ADW - 1) : 0] opa_wr_addr,
output wire [(OPW - 1) : 0] opa_wr_data,
output wire opa_wr_we,
output wire [(ADW - 1) : 0] opm_addr,
input wire [(OPW - 1) : 0] opm_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam CTRL_IDLE = 4'h0;
localparam CTRL_INIT = 4'h1;
localparam CTRL_INIT_STALL = 4'h2;
localparam CTRL_SHL = 4'h3;
localparam CTRL_SHL_STALL = 4'h4;
localparam CTRL_COMPARE = 4'h5;
localparam CTRL_COMPARE_STALL = 4'h6;
localparam CTRL_SUB = 4'h7;
localparam CTRL_SUB_STALL = 4'h8;
localparam CTRL_LOOP = 4'h9;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [(ADW - 1) : 0] opa_rd_addr_reg;
reg [(ADW - 1) : 0] opa_wr_addr_reg;
reg [(OPW - 1) : 0] opa_wr_data_reg;
reg opa_wr_we_reg;
reg [(ADW - 1) : 0] opm_addr_reg;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [03 : 0] residue_ctrl_reg;
reg [03 : 0] residue_ctrl_new;
reg residue_ctrl_we;
reg reset_word_index;
reg reset_n_counter;
reg [14 : 0] loop_counter_1_to_nn_reg; //for i = 1 to nn (2*N)
reg [14 : 0] loop_counter_1_to_nn_new;
reg loop_counter_1_to_nn_we;
reg [14 : 0] nn_reg;
reg nn_we;
reg [(ADW - 1) : 0] length_m1_reg;
reg [(ADW - 1) : 0] length_m1_new;
reg length_m1_we;
reg [(ADW - 1) : 0] word_index_reg;
reg [(ADW - 1) : 0] word_index_new;
reg word_index_we;
reg [(OPW - 1) : 0] one_data;
wire [(OPW - 1) : 0] sub_data;
wire [(OPW - 1) : 0] shl_data;
reg sub_carry_in_new;
reg sub_carry_in_reg;
wire sub_carry_out;
reg shl_carry_in_new;
reg shl_carry_in_reg;
wire shl_carry_out;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign opa_rd_addr = opa_rd_addr_reg;
assign opa_wr_addr = opa_wr_addr_reg;
assign opa_wr_data = opa_wr_data_reg;
assign opa_wr_we = opa_wr_we_reg;
assign opm_addr = opm_addr_reg;
assign ready = ready_reg;
//----------------------------------------------------------------
// Instantions
//----------------------------------------------------------------
adder #(.OPW(OPW)) add_inst(
.a(opa_rd_data),
.b( ~ opm_data),
.carry_in(sub_carry_in_reg),
.sum(sub_data),
.carry_out(sub_carry_out)
);
shl #(.OPW(OPW)) shl_inst(
.a(opa_rd_data),
.carry_in(shl_carry_in_reg),
.amul2(shl_data),
.carry_out(shl_carry_out)
);
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
residue_ctrl_reg <= CTRL_IDLE;
word_index_reg <= {ADW{1'b1}};
length_m1_reg <= {ADW{1'b1}};
nn_reg <= 15'h0;
loop_counter_1_to_nn_reg <= 15'h0;
ready_reg <= 1'b1;
sub_carry_in_reg <= 1'b0;
shl_carry_in_reg <= 1'b0;
end
else
begin
if (residue_ctrl_we)
residue_ctrl_reg <= residue_ctrl_new;
if (word_index_we)
word_index_reg <= word_index_new;
if (length_m1_we)
length_m1_reg <= length_m1_new;
if (nn_we)
nn_reg <= nn;
if (loop_counter_1_to_nn_we)
loop_counter_1_to_nn_reg <= loop_counter_1_to_nn_new;
if (ready_we)
ready_reg <= ready_new;
sub_carry_in_reg <= sub_carry_in_new;
shl_carry_in_reg <= shl_carry_in_new;
end
end // reg_update
//----------------------------------------------------------------
// loop counter process. implements for (int i = 0; i < 2 * N; i++)
//
// m_residue_2_2N_array( N, M, Nr)
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
// for (int i = 0; i < 2 * N; i++)
// Nr = Nr shift left 1
// if (Nr less than M) continue;
// Nr = Nr - M
// return Nr
//
//----------------------------------------------------------------
always @*
begin : process_1_to_2n
loop_counter_1_to_nn_new = loop_counter_1_to_nn_reg + 15'h1;
loop_counter_1_to_nn_we = 1'b0;
if (reset_n_counter)
begin
loop_counter_1_to_nn_new = 15'h1;
loop_counter_1_to_nn_we = 1'b1;
end
if (residue_ctrl_reg == CTRL_LOOP)
loop_counter_1_to_nn_we = 1'b1;
end
//----------------------------------------------------------------
// implements looping over words in a multiword operation
//----------------------------------------------------------------
always @*
begin : word_index_process
word_index_new = word_index_reg - 1'b1;
word_index_we = 1'b1;
if (reset_word_index)
word_index_new = length_m1_reg;
if (residue_ctrl_reg == CTRL_IDLE)
//reduce a pipeline stage with early read
word_index_new = length_m1_new;
end
//----------------------------------------------------------------
// writer process. implements:
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
// Nr = Nr shift left 1
// Nr = Nr - M
//
// m_residue_2_2N_array( N, M, Nr)
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
// for (int i = 0; i < 2 * N; i++)
// Nr = Nr shift left 1
// if (Nr less than M) continue;
// Nr = Nr - M
// return Nr
//----------------------------------------------------------------
always @*
begin : writer_process
opa_wr_addr_reg = word_index_reg;
case (residue_ctrl_reg)
CTRL_INIT:
begin
opa_wr_data_reg = one_data;
opa_wr_we_reg = 1'b1;
end
CTRL_SUB:
begin
opa_wr_data_reg = sub_data;
opa_wr_we_reg = 1'b1;
end
CTRL_SHL:
begin
opa_wr_data_reg = shl_data;
opa_wr_we_reg = 1'b1;
end
default:
begin
opa_wr_data_reg = 32'h0;
opa_wr_we_reg = 1'b0;
end
endcase
end
//----------------------------------------------------------------
// reader process. reads from new value because it occurs one
// cycle earlier than the writer.
//----------------------------------------------------------------
always @*
begin : reader_process
opa_rd_addr_reg = word_index_new;
opm_addr_reg = word_index_new;
end
//----------------------------------------------------------------
// carry process. "Ripple carry awesomeness!"
//----------------------------------------------------------------
always @*
begin : carry_process
case (residue_ctrl_reg)
CTRL_COMPARE:
sub_carry_in_new = sub_carry_out;
CTRL_SUB:
sub_carry_in_new = sub_carry_out;
default:
sub_carry_in_new = 1'b1;
endcase
case (residue_ctrl_reg)
CTRL_SHL:
shl_carry_in_new = shl_carry_out;
default:
shl_carry_in_new = 1'b0;
endcase
end
//----------------------------------------------------------------
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
//----------------------------------------------------------------
always @*
begin : one_process
one_data = 32'h0;
if (residue_ctrl_reg == CTRL_INIT)
if (word_index_reg == length_m1_reg)
one_data = {{(OPW - 1){1'b0}}, 1'b1};
end
//----------------------------------------------------------------
// residue_ctrl
//
// Control FSM for residue
//----------------------------------------------------------------
always @*
begin : residue_ctrl
ready_new = 1'b0;
ready_we = 1'b0;
reset_word_index = 1'b0;
reset_n_counter = 1'b0;
length_m1_new = length - 1'b1;
length_m1_we = 1'b0;
nn_we = 1'b0;
residue_ctrl_new = CTRL_IDLE;
residue_ctrl_we = 1'b0;
case (residue_ctrl_reg)
CTRL_IDLE:
if (calculate)
begin
ready_new = 1'b0;
ready_we = 1'b1;
reset_word_index = 1'b1;
length_m1_we = 1'b1;
nn_we = 1'b1;
residue_ctrl_new = CTRL_INIT;
residue_ctrl_we = 1'b1;
end
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
CTRL_INIT:
if (word_index_reg == 0)
begin
residue_ctrl_new = CTRL_INIT_STALL;
residue_ctrl_we = 1'b1;
end
CTRL_INIT_STALL:
begin
reset_word_index = 1'b1;
reset_n_counter = 1'b1;
residue_ctrl_new = CTRL_SHL;
residue_ctrl_we = 1'b1;
end
// Nr = Nr shift left 1
CTRL_SHL:
begin
if (word_index_reg == 0)
begin
residue_ctrl_new = CTRL_SHL_STALL;
residue_ctrl_we = 1'b1;
end
end
CTRL_SHL_STALL:
begin
reset_word_index = 1'b1;
residue_ctrl_new = CTRL_COMPARE;
residue_ctrl_we = 1'b1;
end
//if (Nr less than M) continue
CTRL_COMPARE:
if (word_index_reg == 0)
begin
residue_ctrl_new = CTRL_COMPARE_STALL;
residue_ctrl_we = 1'b1;
end
CTRL_COMPARE_STALL:
begin
reset_word_index = 1'b1;
residue_ctrl_we = 1'b1;
if (sub_carry_in_reg == 1'b1)
//TODO: Bug! detect CF to detect less than, but no detect ZF to detect equal to.
residue_ctrl_new = CTRL_SUB;
else
residue_ctrl_new = CTRL_LOOP;
end
//Nr = Nr - M
CTRL_SUB:
if (word_index_reg == 0)
begin
residue_ctrl_new = CTRL_SUB_STALL;
residue_ctrl_we = 1'b1;
end
CTRL_SUB_STALL:
begin
residue_ctrl_new = CTRL_LOOP;
residue_ctrl_we = 1'b1;
end
//for (int i = 0; i < 2 * N; i++)
CTRL_LOOP:
begin
if (loop_counter_1_to_nn_reg == nn_reg)
begin
ready_new = 1'b1;
ready_we = 1'b1;
residue_ctrl_new = CTRL_IDLE;
residue_ctrl_we = 1'b1;
end
else
begin
reset_word_index = 1'b1;
residue_ctrl_new = CTRL_SHL;
residue_ctrl_we = 1'b1;
end
end
default:
begin
end
endcase
end
endmodule // residue
//======================================================================
// EOF residue.v
//======================================================================
|
module rsa_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i; //Address
input wb_cyc_i; //bus cycle
input [dw-1:0] wb_dat_i; //Data IN
input [3:0] wb_sel_i; //Select Input Array
input wb_stb_i; //Chip Select
input wb_we_i; //Write Or Read Enabled
output wb_ack_o; //Acknowledge
output wb_err_o; //Error
output reg [dw-1:0] wb_dat_o; //Data OUT
output int_o; //Interrupt
input wb_clk_i; //Clk
input wb_rst_i; //Reset
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
wire reset_n=!wb_rst_i;
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// The operand width is the internal operand width in bits.
// The address width is the size of the address space used. This
// value must be balances with OPERAND_WIDTH to allow a total
// of 8192 bits of data. OPERAND_WIDTH * (ADDRESS_WIDTH ** 2)
// is the formula. Note that the API data with is always 32 bits.
localparam OPERAND_WIDTH = 32;
localparam ADDRESS_WIDTH = 8;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_CYCLES_HIGH = 8'h10;
localparam ADDR_CYCLES_LOW = 8'h11;
localparam ADDR_MODULUS_LENGTH = 8'h20;
localparam ADDR_EXPONENT_LENGTH = 8'h21;
localparam ADDR_MODULUS_PTR_RST = 8'h30;
localparam ADDR_MODULUS_DATA = 8'h31;
localparam ADDR_EXPONENT_PTR_RST = 8'h40;
localparam ADDR_EXPONENT_DATA = 8'h41;
localparam ADDR_MESSAGE_PTR_RST = 8'h50;
localparam ADDR_MESSAGE_DATA = 8'h51;
localparam ADDR_RESULT_PTR_RST = 8'h60;
localparam ADDR_RESULT_DATA = 8'h61;
localparam DEFAULT_MODLENGTH = 8'h80; // 2048 bits.
localparam DEFAULT_EXPLENGTH = 8'h80;
localparam CORE_NAME0 = 32'h6d6f6465; // "mode"
localparam CORE_NAME1 = 32'h78702020; // "xp "
localparam CORE_VERSION = 32'h302e3532; // "0.52"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [07 : 0] exponent_length_reg;
reg [07 : 0] exponent_length_new;
reg exponent_length_we;
reg [07 : 0] modulus_length_reg;
reg [07 : 0] modulus_length_new;
reg modulus_length_we;
reg start_reg;
reg start_new;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg exponent_mem_api_rst;
reg exponent_mem_api_cs;
reg exponent_mem_api_wr;
wire [31 : 0] exponent_mem_api_read_data;
reg modulus_mem_api_rst;
reg modulus_mem_api_cs;
reg modulus_mem_api_wr;
wire [31 : 0] modulus_mem_api_read_data;
reg message_mem_api_rst;
reg message_mem_api_cs;
reg message_mem_api_wr;
wire [31 : 0] message_mem_api_read_data;
reg result_mem_api_rst;
reg result_mem_api_cs;
wire [31 : 0] result_mem_api_read_data;
wire ready;
wire [63 : 0] cycles;
//reg [31 : 0] wb_dat_o;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
//assign wb_dat_o = wb_dat_o;
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
modexp_core #(.OPW(OPERAND_WIDTH), .ADW(ADDRESS_WIDTH))
core_inst(
.clk(wb_clk_i),
.reset_n(reset_n),
.start(start_reg),
.ready(ready),
.exponent_length(exponent_length_reg),
.modulus_length(modulus_length_reg),
.cycles(cycles),
.exponent_mem_api_cs(exponent_mem_api_cs),
.exponent_mem_api_wr(exponent_mem_api_wr),
.exponent_mem_api_rst(exponent_mem_api_rst),
.exponent_mem_api_write_data(wb_dat_i),
.exponent_mem_api_read_data(exponent_mem_api_read_data),
.modulus_mem_api_cs(modulus_mem_api_cs),
.modulus_mem_api_wr(modulus_mem_api_wr),
.modulus_mem_api_rst(modulus_mem_api_rst),
.modulus_mem_api_write_data(wb_dat_i),
.modulus_mem_api_read_data(modulus_mem_api_read_data),
.message_mem_api_cs(message_mem_api_cs),
.message_mem_api_wr(message_mem_api_wr),
.message_mem_api_rst(message_mem_api_rst),
.message_mem_api_write_data(wb_dat_i),
.message_mem_api_read_data(message_mem_api_read_data),
.result_mem_api_cs(result_mem_api_cs),
.result_mem_api_rst(result_mem_api_rst),
.result_mem_api_read_data(result_mem_api_read_data)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge wb_clk_i or negedge reset_n)
begin
if (!reset_n)
begin
start_reg <= 1'b0;
exponent_length_reg <= DEFAULT_EXPLENGTH;
modulus_length_reg <= DEFAULT_MODLENGTH;
end
else
begin
start_reg <= start_new;
if (exponent_length_we)
begin
exponent_length_reg <= wb_dat_i[7 : 0];
end
if (modulus_length_we)
begin
modulus_length_reg <= wb_dat_i[7 : 0];
end
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
modulus_length_we = 1'b0;
exponent_length_we = 1'b0;
start_new = 1'b0;
modulus_mem_api_rst = 1'b0;
modulus_mem_api_cs = 1'b0;
modulus_mem_api_wr = 1'b0;
exponent_mem_api_rst = 1'b0;
exponent_mem_api_cs = 1'b0;
exponent_mem_api_wr = 1'b0;
message_mem_api_rst = 1'b0;
message_mem_api_cs = 1'b0;
message_mem_api_wr = 1'b0;
result_mem_api_rst = 1'b0;
result_mem_api_cs = 1'b0;
wb_dat_o = 32'h00000000;
if (wb_stb_i)
begin
if (wb_we_i)
begin
case (wb_adr_i[9:2])
ADDR_CTRL:
begin
start_new = wb_dat_i[0];
end
ADDR_MODULUS_LENGTH:
begin
modulus_length_we = 1'b1;
end
ADDR_EXPONENT_LENGTH:
begin
exponent_length_we = 1'b1;
end
ADDR_MODULUS_PTR_RST:
begin
modulus_mem_api_rst = 1'b1;
end
ADDR_MODULUS_DATA:
begin
modulus_mem_api_cs = 1'b1;
modulus_mem_api_wr = 1'b1;
end
ADDR_EXPONENT_PTR_RST:
begin
exponent_mem_api_rst = 1'b1;
end
ADDR_EXPONENT_DATA:
begin
exponent_mem_api_cs = 1'b1;
exponent_mem_api_wr = 1'b1;
end
ADDR_MESSAGE_PTR_RST:
begin
message_mem_api_rst = 1'b1;
end
ADDR_MESSAGE_DATA:
begin
message_mem_api_cs = 1'b1;
message_mem_api_wr = 1'b1;
end
ADDR_RESULT_PTR_RST:
begin
result_mem_api_rst = 1'b1;
end
default:
begin
end
endcase // case (wb_adr_i[7 : 0])
end // if (wb_we_i)
else
begin
case (wb_adr_i[9:2])
ADDR_NAME0:
wb_dat_o = CORE_NAME0;
ADDR_NAME1:
wb_dat_o = CORE_NAME1;
ADDR_VERSION:
wb_dat_o = CORE_VERSION;
ADDR_CTRL:
wb_dat_o = {31'h00000000, start_reg};
ADDR_STATUS:
wb_dat_o = {31'h00000000, ready};
ADDR_CYCLES_HIGH:
wb_dat_o = cycles[63 : 32];
ADDR_CYCLES_LOW:
wb_dat_o = cycles[31 : 0];
ADDR_MODULUS_LENGTH:
wb_dat_o = {24'h000000, modulus_length_reg};
ADDR_EXPONENT_LENGTH:
wb_dat_o = {24'h000000, exponent_length_reg};
ADDR_MODULUS_DATA:
begin
modulus_mem_api_cs = 1'b1;
wb_dat_o = modulus_mem_api_read_data;
end
ADDR_EXPONENT_DATA:
begin
exponent_mem_api_cs = 1'b1;
wb_dat_o = exponent_mem_api_read_data;
end
ADDR_MESSAGE_DATA:
begin
message_mem_api_cs = 1'b1;
wb_dat_o = message_mem_api_read_data;
end
ADDR_RESULT_DATA:
begin
result_mem_api_cs = 1'b1;
wb_dat_o = result_mem_api_read_data;
end
default:
begin
end
endcase // case (wb_adr_i)
end // else: !if(wb_we_i)
end // if (wb_stb_i)
end // block: api
endmodule // modexp
//======================================================================
// EOF modexp_top.v
//======================================================================
|
//======================================================================
//
// shl.v
// -----
// One bit left shift of words with carry in and carry out. Used in
// the residue module of the modexp core.
//
//
// Author: Peter Magnusson, Joachim Strömbergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module shl #(parameter OPW = 32)
(
input wire [(OPW - 1) : 0] a,
input wire carry_in,
output wire [(OPW - 1) : 0] amul2,
output wire carry_out
);
assign amul2 = {a[(OPW - 2) : 0], carry_in};
assign carry_out = a[(OPW - 1)];
endmodule // shl
//======================================================================
// EOF shl.v
//======================================================================
|
//======================================================================
//
// shr32.v
// -------
// One bit right shift with carry in and carry out.
// Used in the montprod module of the modexp core.
//
//
// Author: Peter Magnusson, Joachim Strömbergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module shr #(parameter OPW = 32)
(
input wire [(OPW - 1) : 0] a,
input wire carry_in,
output wire [(OPW - 1) : 0] adiv2,
output wire carry_out
);
assign adiv2 = {carry_in, a[(OPW - 1) : 1]};
assign carry_out = a[0];
endmodule // shr
//======================================================================
// EOF shr.v
//======================================================================
|
//======================================================================
//
// sha256_core.v
// -------------
// Verilog 2001 implementation of the SHA-256 hash function.
// This is the internal core with wide interfaces.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
// Modified by Matthew Hicks:
// Convert to synchronous, positive level reset
// Fix at 256-bit mode
module sha256(
input wire clk,
input wire rst,
input wire init,
input wire next,
input wire [511 : 0] block,
output wire ready,
output wire [255 : 0] digest,
output wire digest_valid
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter SHA256_H0_0 = 32'h6a09e667;
parameter SHA256_H0_1 = 32'hbb67ae85;
parameter SHA256_H0_2 = 32'h3c6ef372;
parameter SHA256_H0_3 = 32'ha54ff53a;
parameter SHA256_H0_4 = 32'h510e527f;
parameter SHA256_H0_5 = 32'h9b05688c;
parameter SHA256_H0_6 = 32'h1f83d9ab;
parameter SHA256_H0_7 = 32'h5be0cd19;
parameter SHA256_ROUNDS = 63;
parameter CTRL_IDLE = 0;
parameter CTRL_ROUNDS = 1;
parameter CTRL_DONE = 2;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] a_reg;
reg [31 : 0] a_new;
reg [31 : 0] b_reg;
reg [31 : 0] b_new;
reg [31 : 0] c_reg;
reg [31 : 0] c_new;
reg [31 : 0] d_reg;
reg [31 : 0] d_new;
reg [31 : 0] e_reg;
reg [31 : 0] e_new;
reg [31 : 0] f_reg;
reg [31 : 0] f_new;
reg [31 : 0] g_reg;
reg [31 : 0] g_new;
reg [31 : 0] h_reg;
reg [31 : 0] h_new;
reg a_h_we;
reg [31 : 0] H0_reg;
reg [31 : 0] H0_new;
reg [31 : 0] H1_reg;
reg [31 : 0] H1_new;
reg [31 : 0] H2_reg;
reg [31 : 0] H2_new;
reg [31 : 0] H3_reg;
reg [31 : 0] H3_new;
reg [31 : 0] H4_reg;
reg [31 : 0] H4_new;
reg [31 : 0] H5_reg;
reg [31 : 0] H5_new;
reg [31 : 0] H6_reg;
reg [31 : 0] H6_new;
reg [31 : 0] H7_reg;
reg [31 : 0] H7_new;
reg H_we;
reg [5 : 0] t_ctr_reg;
reg [5 : 0] t_ctr_new;
reg t_ctr_we;
reg t_ctr_inc;
reg t_ctr_rst;
reg digest_valid_reg;
reg digest_valid_new;
reg digest_valid_we;
reg [1 : 0] sha256_ctrl_reg;
reg [1 : 0] sha256_ctrl_new;
reg sha256_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg digest_init;
reg digest_update;
reg state_init;
reg state_update;
reg first_block;
reg ready_flag;
reg [31 : 0] t1;
reg [31 : 0] t2;
wire [31 : 0] k_data;
reg w_init;
reg w_next;
wire [31 : 0] w_data;
//----------------------------------------------------------------
// Module instantiantions.
//----------------------------------------------------------------
sha256_k_constants k_constants_inst(
.addr(t_ctr_reg),
.K(k_data)
);
sha256_w_mem w_mem_inst(
.clk(clk),
.rst(rst),
.block(block),
.init(w_init),
.next(w_next),
.w(w_data)
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_flag;
assign digest = {H0_reg, H1_reg, H2_reg, H3_reg,
H4_reg, H5_reg, H6_reg, H7_reg};
assign digest_valid = digest_valid_reg;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
if (rst)
begin
a_reg <= 32'h0;
b_reg <= 32'h0;
c_reg <= 32'h0;
d_reg <= 32'h0;
e_reg <= 32'h0;
f_reg <= 32'h0;
g_reg <= 32'h0;
h_reg <= 32'h0;
H0_reg <= 32'h0;
H1_reg <= 32'h0;
H2_reg <= 32'h0;
H3_reg <= 32'h0;
H4_reg <= 32'h0;
H5_reg <= 32'h0;
H6_reg <= 32'h0;
H7_reg <= 32'h0;
digest_valid_reg <= 0;
t_ctr_reg <= 6'h0;
sha256_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (a_h_we)
begin
a_reg <= a_new;
b_reg <= b_new;
c_reg <= c_new;
d_reg <= d_new;
e_reg <= e_new;
f_reg <= f_new;
g_reg <= g_new;
h_reg <= h_new;
end
if (H_we)
begin
H0_reg <= H0_new;
H1_reg <= H1_new;
H2_reg <= H2_new;
H3_reg <= H3_new;
H4_reg <= H4_new;
H5_reg <= H5_new;
H6_reg <= H6_new;
H7_reg <= H7_new;
end
if (t_ctr_we)
t_ctr_reg <= t_ctr_new;
if (digest_valid_we)
digest_valid_reg <= digest_valid_new;
if (sha256_ctrl_we)
sha256_ctrl_reg <= sha256_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// digest_logic
//
// The logic needed to init as well as update the digest.
//----------------------------------------------------------------
always @*
begin : digest_logic
H0_new = 32'h0;
H1_new = 32'h0;
H2_new = 32'h0;
H3_new = 32'h0;
H4_new = 32'h0;
H5_new = 32'h0;
H6_new = 32'h0;
H7_new = 32'h0;
H_we = 0;
if (digest_init)
begin
H_we = 1;
H0_new = SHA256_H0_0;
H1_new = SHA256_H0_1;
H2_new = SHA256_H0_2;
H3_new = SHA256_H0_3;
H4_new = SHA256_H0_4;
H5_new = SHA256_H0_5;
H6_new = SHA256_H0_6;
H7_new = SHA256_H0_7;
end
if (digest_update)
begin
H0_new = H0_reg + a_reg;
H1_new = H1_reg + b_reg;
H2_new = H2_reg + c_reg;
H3_new = H3_reg + d_reg;
H4_new = H4_reg + e_reg;
H5_new = H5_reg + f_reg;
H6_new = H6_reg + g_reg;
H7_new = H7_reg + h_reg;
H_we = 1;
end
end // digest_logic
//----------------------------------------------------------------
// t1_logic
//
// The logic for the T1 function.
//----------------------------------------------------------------
always @*
begin : t1_logic
reg [31 : 0] sum1;
reg [31 : 0] ch;
sum1 = {e_reg[5 : 0], e_reg[31 : 6]} ^
{e_reg[10 : 0], e_reg[31 : 11]} ^
{e_reg[24 : 0], e_reg[31 : 25]};
ch = (e_reg & f_reg) ^ ((~e_reg) & g_reg);
t1 = h_reg + sum1 + ch + w_data + k_data;
end // t1_logic
//----------------------------------------------------------------
// t2_logic
//
// The logic for the T2 function
//----------------------------------------------------------------
always @*
begin : t2_logic
reg [31 : 0] sum0;
reg [31 : 0] maj;
sum0 = {a_reg[1 : 0], a_reg[31 : 2]} ^
{a_reg[12 : 0], a_reg[31 : 13]} ^
{a_reg[21 : 0], a_reg[31 : 22]};
maj = (a_reg & b_reg) ^ (a_reg & c_reg) ^ (b_reg & c_reg);
t2 = sum0 + maj;
end // t2_logic
//----------------------------------------------------------------
// state_logic
//
// The logic needed to init as well as update the state during
// round processing.
//----------------------------------------------------------------
always @*
begin : state_logic
a_new = 32'h0;
b_new = 32'h0;
c_new = 32'h0;
d_new = 32'h0;
e_new = 32'h0;
f_new = 32'h0;
g_new = 32'h0;
h_new = 32'h0;
a_h_we = 0;
if (state_init)
begin
a_h_we = 1;
if (first_block)
begin
a_new = SHA256_H0_0;
b_new = SHA256_H0_1;
c_new = SHA256_H0_2;
d_new = SHA256_H0_3;
e_new = SHA256_H0_4;
f_new = SHA256_H0_5;
g_new = SHA256_H0_6;
h_new = SHA256_H0_7;
end
else
begin
a_new = H0_reg;
b_new = H1_reg;
c_new = H2_reg;
d_new = H3_reg;
e_new = H4_reg;
f_new = H5_reg;
g_new = H6_reg;
h_new = H7_reg;
end
end
if (state_update)
begin
a_new = t1 + t2;
b_new = a_reg;
c_new = b_reg;
d_new = c_reg;
e_new = d_reg + t1;
f_new = e_reg;
g_new = f_reg;
h_new = g_reg;
a_h_we = 1;
end
end // state_logic
//----------------------------------------------------------------
// t_ctr
//
// Update logic for the round counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : t_ctr
t_ctr_new = 0;
t_ctr_we = 0;
if (t_ctr_rst)
begin
t_ctr_new = 0;
t_ctr_we = 1;
end
if (t_ctr_inc)
begin
t_ctr_new = t_ctr_reg + 1'b1;
t_ctr_we = 1;
end
end // t_ctr
//----------------------------------------------------------------
// sha256_ctrl_fsm
//
// Logic for the state machine controlling the core behaviour.
//----------------------------------------------------------------
always @*
begin : sha256_ctrl_fsm
digest_init = 0;
digest_update = 0;
state_init = 0;
state_update = 0;
first_block = 0;
ready_flag = 0;
w_init = 0;
w_next = 0;
t_ctr_inc = 0;
t_ctr_rst = 0;
digest_valid_new = 0;
digest_valid_we = 0;
sha256_ctrl_new = CTRL_IDLE;
sha256_ctrl_we = 0;
case (sha256_ctrl_reg)
CTRL_IDLE:
begin
ready_flag = 1;
if (init)
begin
digest_init = 1;
w_init = 1;
state_init = 1;
first_block = 1;
t_ctr_rst = 1;
digest_valid_new = 0;
digest_valid_we = 1;
sha256_ctrl_new = CTRL_ROUNDS;
sha256_ctrl_we = 1;
end
if (next)
begin
t_ctr_rst = 1;
w_init = 1;
state_init = 1;
digest_valid_new = 0;
digest_valid_we = 1;
sha256_ctrl_new = CTRL_ROUNDS;
sha256_ctrl_we = 1;
end
end
CTRL_ROUNDS:
begin
w_next = 1;
state_update = 1;
t_ctr_inc = 1;
if (t_ctr_reg == SHA256_ROUNDS)
begin
sha256_ctrl_new = CTRL_DONE;
sha256_ctrl_we = 1;
end
end
CTRL_DONE:
begin
digest_update = 1;
digest_valid_new = 1;
digest_valid_we = 1;
sha256_ctrl_new = CTRL_IDLE;
sha256_ctrl_we = 1;
end
endcase // case (sha256_ctrl_reg)
end // sha256_ctrl_fsm
endmodule // sha256_core
//======================================================================
// EOF sha256_core.v
//======================================================================
|
//======================================================================
//
// sha256_k_constants.v
// --------------------
// The table K with constants in the SHA-256 hash function.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module sha256_k_constants(
input wire [5 : 0] addr,
output wire [31 : 0] K
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_K;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign K = tmp_K;
//----------------------------------------------------------------
// addr_mux
//----------------------------------------------------------------
always @*
begin : addr_mux
case(addr)
00:
tmp_K = 32'h428a2f98;
01:
tmp_K = 32'h71374491;
02:
tmp_K = 32'hb5c0fbcf;
03:
tmp_K = 32'he9b5dba5;
04:
tmp_K = 32'h3956c25b;
05:
tmp_K = 32'h59f111f1;
06:
tmp_K = 32'h923f82a4;
07:
tmp_K = 32'hab1c5ed5;
08:
tmp_K = 32'hd807aa98;
09:
tmp_K = 32'h12835b01;
10:
tmp_K = 32'h243185be;
11:
tmp_K = 32'h550c7dc3;
12:
tmp_K = 32'h72be5d74;
13:
tmp_K = 32'h80deb1fe;
14:
tmp_K = 32'h9bdc06a7;
15:
tmp_K = 32'hc19bf174;
16:
tmp_K = 32'he49b69c1;
17:
tmp_K = 32'hefbe4786;
18:
tmp_K = 32'h0fc19dc6;
19:
tmp_K = 32'h240ca1cc;
20:
tmp_K = 32'h2de92c6f;
21:
tmp_K = 32'h4a7484aa;
22:
tmp_K = 32'h5cb0a9dc;
23:
tmp_K = 32'h76f988da;
24:
tmp_K = 32'h983e5152;
25:
tmp_K = 32'ha831c66d;
26:
tmp_K = 32'hb00327c8;
27:
tmp_K = 32'hbf597fc7;
28:
tmp_K = 32'hc6e00bf3;
29:
tmp_K = 32'hd5a79147;
30:
tmp_K = 32'h06ca6351;
31:
tmp_K = 32'h14292967;
32:
tmp_K = 32'h27b70a85;
33:
tmp_K = 32'h2e1b2138;
34:
tmp_K = 32'h4d2c6dfc;
35:
tmp_K = 32'h53380d13;
36:
tmp_K = 32'h650a7354;
37:
tmp_K = 32'h766a0abb;
38:
tmp_K = 32'h81c2c92e;
39:
tmp_K = 32'h92722c85;
40:
tmp_K = 32'ha2bfe8a1;
41:
tmp_K = 32'ha81a664b;
42:
tmp_K = 32'hc24b8b70;
43:
tmp_K = 32'hc76c51a3;
44:
tmp_K = 32'hd192e819;
45:
tmp_K = 32'hd6990624;
46:
tmp_K = 32'hf40e3585;
47:
tmp_K = 32'h106aa070;
48:
tmp_K = 32'h19a4c116;
49:
tmp_K = 32'h1e376c08;
50:
tmp_K = 32'h2748774c;
51:
tmp_K = 32'h34b0bcb5;
52:
tmp_K = 32'h391c0cb3;
53:
tmp_K = 32'h4ed8aa4a;
54:
tmp_K = 32'h5b9cca4f;
55:
tmp_K = 32'h682e6ff3;
56:
tmp_K = 32'h748f82ee;
57:
tmp_K = 32'h78a5636f;
58:
tmp_K = 32'h84c87814;
59:
tmp_K = 32'h8cc70208;
60:
tmp_K = 32'h90befffa;
61:
tmp_K = 32'ha4506ceb;
62:
tmp_K = 32'hbef9a3f7;
63:
tmp_K = 32'hc67178f2;
endcase // case (addr)
end // block: addr_mux
endmodule // sha256_k_constants
//======================================================================
// sha256_k_constants.v
//======================================================================
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : sha256_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-SHA256 core
//
module sha256_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg startHash, startHash_r;
reg newMessage, newMessage_r;
reg [31:0] data [0:15];
wire [511:0] bigData = {data[15], data[14], data[13], data[12], data[11], data[10], data[9], data[8], data[7], data[6], data[5], data[4], data[3], data[2], data[1], data[0]};
wire [255:0] hash;
wire ready;
wire hashValid;
// Implement SHA256 I/O memory map interface
// Write side
always @(posedge wb_clk_i)
begin
if(wb_rst_i)
begin
startHash <= 0;
startHash_r <= 0;
newMessage <= 0;
newMessage_r <= 0;
data[0] <= 0;
data[1] <= 0;
data[2] <= 0;
data[3] <= 0;
data[4] <= 0;
data[5] <= 0;
data[6] <= 0;
data[7] <= 0;
data[8] <= 0;
data[9] <= 0;
data[10] <= 0;
data[11] <= 0;
data[12] <= 0;
data[13] <= 0;
data[14] <= 0;
data[15] <= 0;
end
else begin
// Generate a registered versions of startHash and newMessage
startHash_r <= startHash;
newMessage_r <= newMessage;
// Perform a write
if(wb_stb_i & wb_we_i) begin
case(wb_adr_i[6:2])
0: begin
startHash <= wb_dat_i[0];
newMessage <= wb_dat_i[1];
end
1: data[0] <= wb_dat_i;
2: data[1] <= wb_dat_i;
3: data[2] <= wb_dat_i;
4: data[3] <= wb_dat_i;
5: data[4] <= wb_dat_i;
6: data[5] <= wb_dat_i;
7: data[6] <= wb_dat_i;
8: data[7] <= wb_dat_i;
9: data[8] <= wb_dat_i;
10: data[9] <= wb_dat_i;
11: data[10] <= wb_dat_i;
12: data[11] <= wb_dat_i;
13: data[12] <= wb_dat_i;
14: data[13] <= wb_dat_i;
15: data[14] <= wb_dat_i;
16: data[15] <= wb_dat_i;
default:
;
endcase
end else begin
startHash <= 1'b0;
newMessage <= 1'b0;
end // end else
end
end // end always
// Implement SHA256 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[6:2])
0: wb_dat_o = {31'b0, ready};
1: wb_dat_o = data[0];
2: wb_dat_o = data[1];
3: wb_dat_o = data[2];
4: wb_dat_o = data[3];
5: wb_dat_o = data[4];
6: wb_dat_o = data[5];
7: wb_dat_o = data[6];
8: wb_dat_o = data[7];
9: wb_dat_o = data[8];
10: wb_dat_o = data[9];
11: wb_dat_o = data[10];
12: wb_dat_o = data[11];
13: wb_dat_o = data[12];
14: wb_dat_o = data[13];
15: wb_dat_o = data[14];
16: wb_dat_o = data[15];
17: wb_dat_o = {31'b0, hashValid};
18: wb_dat_o = hash[31:0];
19: wb_dat_o = hash[63:32];
20: wb_dat_o = hash[95:64];
21: wb_dat_o = hash[127:96];
22: wb_dat_o = hash[159:128];
23: wb_dat_o = hash[191:160];
24: wb_dat_o = hash[223:192];
25: wb_dat_o = hash[255:224];
default:
wb_dat_o = 32'b0;
endcase
end
sha256 sha256(
.clk(wb_clk_i),
.rst(wb_rst_i),
.init(startHash && ~startHash_r),
.next(newMessage && ~newMessage_r),
.block(bigData),
.digest(hash),
.digest_valid(hashValid),
.ready(ready)
);
endmodule
|
//======================================================================
//
// sha256_w_mem_regs.v
// -------------------
// The W memory. This version uses 16 32-bit registers as a sliding
// window to generate the 64 words.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module sha256_w_mem(
input wire clk,
input wire rst,
input wire [511 : 0] block,
input wire init,
input wire next,
output wire [31 : 0] w
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter CTRL_IDLE = 0;
parameter CTRL_UPDATE = 1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] w_mem [0 : 15];
reg [31 : 0] w_mem00_new;
reg [31 : 0] w_mem01_new;
reg [31 : 0] w_mem02_new;
reg [31 : 0] w_mem03_new;
reg [31 : 0] w_mem04_new;
reg [31 : 0] w_mem05_new;
reg [31 : 0] w_mem06_new;
reg [31 : 0] w_mem07_new;
reg [31 : 0] w_mem08_new;
reg [31 : 0] w_mem09_new;
reg [31 : 0] w_mem10_new;
reg [31 : 0] w_mem11_new;
reg [31 : 0] w_mem12_new;
reg [31 : 0] w_mem13_new;
reg [31 : 0] w_mem14_new;
reg [31 : 0] w_mem15_new;
reg w_mem_we;
reg [5 : 0] w_ctr_reg;
reg [5 : 0] w_ctr_new;
reg w_ctr_we;
reg w_ctr_inc;
reg w_ctr_rst;
reg [1 : 0] sha256_w_mem_ctrl_reg;
reg [1 : 0] sha256_w_mem_ctrl_new;
reg sha256_w_mem_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] w_tmp;
reg [31 : 0] w_new;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign w = w_tmp;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
if (rst)
begin
w_mem[00] <= 32'h0;
w_mem[01] <= 32'h0;
w_mem[02] <= 32'h0;
w_mem[03] <= 32'h0;
w_mem[04] <= 32'h0;
w_mem[05] <= 32'h0;
w_mem[06] <= 32'h0;
w_mem[07] <= 32'h0;
w_mem[08] <= 32'h0;
w_mem[09] <= 32'h0;
w_mem[10] <= 32'h0;
w_mem[11] <= 32'h0;
w_mem[12] <= 32'h0;
w_mem[13] <= 32'h0;
w_mem[14] <= 32'h0;
w_mem[15] <= 32'h0;
w_ctr_reg <= 6'h00;
sha256_w_mem_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (w_mem_we)
begin
w_mem[00] <= w_mem00_new;
w_mem[01] <= w_mem01_new;
w_mem[02] <= w_mem02_new;
w_mem[03] <= w_mem03_new;
w_mem[04] <= w_mem04_new;
w_mem[05] <= w_mem05_new;
w_mem[06] <= w_mem06_new;
w_mem[07] <= w_mem07_new;
w_mem[08] <= w_mem08_new;
w_mem[09] <= w_mem09_new;
w_mem[10] <= w_mem10_new;
w_mem[11] <= w_mem11_new;
w_mem[12] <= w_mem12_new;
w_mem[13] <= w_mem13_new;
w_mem[14] <= w_mem14_new;
w_mem[15] <= w_mem15_new;
end
if (w_ctr_we)
w_ctr_reg <= w_ctr_new;
if (sha256_w_mem_ctrl_we)
sha256_w_mem_ctrl_reg <= sha256_w_mem_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// select_w
//
// Mux for the external read operation. This is where we exract
// the W variable.
//----------------------------------------------------------------
always @*
begin : select_w
if (w_ctr_reg < 16)
begin
w_tmp = w_mem[w_ctr_reg[3 : 0]];
end
else
begin
w_tmp = w_new;
end
end // select_w
//----------------------------------------------------------------
// w_new_logic
//
// Logic that calculates the next value to be inserted into
// the sliding window of the memory.
//----------------------------------------------------------------
always @*
begin : w_mem_update_logic
reg [31 : 0] w_0;
reg [31 : 0] w_1;
reg [31 : 0] w_9;
reg [31 : 0] w_14;
reg [31 : 0] d0;
reg [31 : 0] d1;
w_mem00_new = 32'h0;
w_mem01_new = 32'h0;
w_mem02_new = 32'h0;
w_mem03_new = 32'h0;
w_mem04_new = 32'h0;
w_mem05_new = 32'h0;
w_mem06_new = 32'h0;
w_mem07_new = 32'h0;
w_mem08_new = 32'h0;
w_mem09_new = 32'h0;
w_mem10_new = 32'h0;
w_mem11_new = 32'h0;
w_mem12_new = 32'h0;
w_mem13_new = 32'h0;
w_mem14_new = 32'h0;
w_mem15_new = 32'h0;
w_mem_we = 0;
w_0 = w_mem[0];
w_1 = w_mem[1];
w_9 = w_mem[9];
w_14 = w_mem[14];
d0 = {w_1[6 : 0], w_1[31 : 7]} ^
{w_1[17 : 0], w_1[31 : 18]} ^
{3'b000, w_1[31 : 3]};
d1 = {w_14[16 : 0], w_14[31 : 17]} ^
{w_14[18 : 0], w_14[31 : 19]} ^
{10'b0000000000, w_14[31 : 10]};
w_new = d1 + w_9 + d0 + w_0;
if (init)
begin
w_mem00_new = block[511 : 480];
w_mem01_new = block[479 : 448];
w_mem02_new = block[447 : 416];
w_mem03_new = block[415 : 384];
w_mem04_new = block[383 : 352];
w_mem05_new = block[351 : 320];
w_mem06_new = block[319 : 288];
w_mem07_new = block[287 : 256];
w_mem08_new = block[255 : 224];
w_mem09_new = block[223 : 192];
w_mem10_new = block[191 : 160];
w_mem11_new = block[159 : 128];
w_mem12_new = block[127 : 96];
w_mem13_new = block[95 : 64];
w_mem14_new = block[63 : 32];
w_mem15_new = block[31 : 0];
w_mem_we = 1;
end
else if (w_ctr_reg > 15)
begin
w_mem00_new = w_mem[01];
w_mem01_new = w_mem[02];
w_mem02_new = w_mem[03];
w_mem03_new = w_mem[04];
w_mem04_new = w_mem[05];
w_mem05_new = w_mem[06];
w_mem06_new = w_mem[07];
w_mem07_new = w_mem[08];
w_mem08_new = w_mem[09];
w_mem09_new = w_mem[10];
w_mem10_new = w_mem[11];
w_mem11_new = w_mem[12];
w_mem12_new = w_mem[13];
w_mem13_new = w_mem[14];
w_mem14_new = w_mem[15];
w_mem15_new = w_new;
w_mem_we = 1;
end
end // w_mem_update_logic
//----------------------------------------------------------------
// w_ctr
// W schedule adress counter. Counts from 0x10 to 0x3f and
// is used to expand the block into words.
//----------------------------------------------------------------
always @*
begin : w_ctr
w_ctr_new = 0;
w_ctr_we = 0;
if (w_ctr_rst)
begin
w_ctr_new = 6'h00;
w_ctr_we = 1;
end
if (w_ctr_inc)
begin
w_ctr_new = w_ctr_reg + 6'h01;
w_ctr_we = 1;
end
end // w_ctr
//----------------------------------------------------------------
// sha256_w_mem_fsm
// Logic for the w shedule FSM.
//----------------------------------------------------------------
always @*
begin : sha256_w_mem_fsm
w_ctr_rst = 0;
w_ctr_inc = 0;
sha256_w_mem_ctrl_new = CTRL_IDLE;
sha256_w_mem_ctrl_we = 0;
case (sha256_w_mem_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
w_ctr_rst = 1;
sha256_w_mem_ctrl_new = CTRL_UPDATE;
sha256_w_mem_ctrl_we = 1;
end
end
CTRL_UPDATE:
begin
if (next)
begin
w_ctr_inc = 1;
end
if (w_ctr_reg == 6'h3f)
begin
sha256_w_mem_ctrl_new = CTRL_IDLE;
sha256_w_mem_ctrl_we = 1;
end
end
endcase // case (sha256_ctrl_reg)
end // sha256_ctrl_fsm
endmodule // sha256_w_mem
//======================================================================
// sha256_w_mem.v
//======================================================================
|
/* Copyright (c) 2012-2013 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* ============================================================================
*
* Global defines for the whole debug system
*
* Author(s):
* Philipp Wagner <philipp.wagner@tum.de>
*/
/*
* Width of a timestamp provided by the Global Timestamp Provider (GTP)
* The timestamp increments every clock cycle of the fastest clock in the system
* and should be big enough to be unique until the data reaches the host PC.
* Note: Changing this parameter requires changes in the flit packaging
* logic as well (e.g. in itm_dbgnoc_if.v)!
* TODO: We still need to find a proper width for this timestamp
*/
`define DBG_TIMESTAMP_WIDTH 32
/*
* Delay in clock cycles between a local (outgoing) and a remote (incoming)
* trigger event.
*
* This delays all trace data for the given number of cycles before deciding
* if it should be used or not, e.g. if the trigger matches or not.
* Consider a simple example with one register between CTM and the debug module
* on both directions:
* ITM generates trigger event -> 1 T delay -> CTM (comb.) -> 1 T delay ->
* ITM registers incoming trigger event
* This means only after two cycles it's clear if the captured data should be
* used. So we delay the capatured data for two cycles by using a shift register
* and make sure to delay all trigger signals by this same (fixed) time as well
* before we decide to use the data or not.
*
* Make this buffer as big as the longest latency between the CTM and a debug
* module, and make sure to delay all internally generated triggers by this
* time as well.
*/
`define DBG_TRIGGER_DELAY 2
/*
* Router addresses of predefined modules
*/
// Address of the external interface, connecting the Debug NoC to the host PC
`define DBG_NOC_ADDR_EXTERNALIF 5'd0
// Address of the Trace Controller Module (TCM)
`define DBG_NOC_ADDR_TCM 5'd1
// Begin of the dynamic address range
`define DBG_NOC_ADDR_DYN_START 5'd2
// note: the max. address is 2^DBG_NOC_PH_DEST_WIDTH-1, currently set to 31
// register read request
`define DBG_NOC_CLASS_REG_READ_REQ 3'b000
// register read response
`define DBG_NOC_CLASS_REG_READ_RESP 3'b001
// register write request
`define DBG_NOC_CLASS_REG_WRITE_REQ 3'b010
// software trace data (from STM)
`define DBG_NOC_CLASS_SOFT_TRACE_DATA 3'b011
// instruction trace data (from ITM)
`define DBG_NOC_CLASS_TRACE_DATA 3'b100
// network router statistics (from NRM)
`define DBG_NOC_CLASS_NRM_DATA 3'b101
// encapsulated lisnoc32 packets
`define DBG_NOC_CLASS_NCM 3'b111
/*
* Maximum length of packets (number of flits, including the header flit) that
* can be sent from the Debug NoC to the USB interface.
*
* The currently used protocol requires a limit like this (even though the
* size is arbitrary, it only defines a FIFO depth).
* XXX: Enhance the Debug Noc -> USB protocol to remove this restriction.
*/
`define MAX_DBGNOC_TO_USB_PACKET_LENGTH 32
/*
* This is the execution traceport in a single signal
*
* Bit 102: enable
* Bit 101-70: program counter
* Bit 69-38: instruction
* Bit 37: writeback enable
* Bit 36-32: writeback register
* Bit 31-0: writeback data
*/
`define DEBUG_TRACE_EXEC_WIDTH 103
`define DEBUG_TRACE_EXEC_ENABLE_MSB 102
`define DEBUG_TRACE_EXEC_ENABLE_LSB 102
`define DEBUG_TRACE_EXEC_PC_MSB 101
`define DEBUG_TRACE_EXEC_PC_LSB 70
`define DEBUG_TRACE_EXEC_INSN_MSB 69
`define DEBUG_TRACE_EXEC_INSN_LSB 38
`define DEBUG_TRACE_EXEC_WBEN_MSB 37
`define DEBUG_TRACE_EXEC_WBEN_LSB 37
`define DEBUG_TRACE_EXEC_WBREG_MSB 36
`define DEBUG_TRACE_EXEC_WBREG_LSB 32
`define DEBUG_TRACE_EXEC_WBDATA_MSB 31
`define DEBUG_TRACE_EXEC_WBDATA_LSB 0
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Wei Song <ws327@cam.ac.uk>
// Stefan Wallentowitz <stefan@wallentowitz.de>
import dii_package::dii_flit;
module debug_ring
#(parameter PORTS = 1,
parameter BUFFER_SIZE = 4,
parameter SUBNET_BITS = 6,
parameter LOCAL_SUBNET = 0)
(input clk, rst,
input [PORTS-1:0][15:0] id_map,
input dii_flit [PORTS-1:0] dii_in, output [PORTS-1:0] dii_in_ready,
output dii_flit [PORTS-1:0] dii_out, input [PORTS-1:0] dii_out_ready
);
dii_flit [1:0][1:0] ext_port;
logic [1:0][1:0] ext_port_ready;
debug_ring_expand
#(.PORTS(PORTS), .BUFFER_SIZE(BUFFER_SIZE))
ring (
.*,
.ext_in ( ext_port[0] ),
.ext_in_ready ( ext_port_ready[0] ),
.ext_out ( ext_port[1] ),
.ext_out_ready ( ext_port_ready[1] )
);
// empty input for chain 0
assign ext_port[0][0].valid = 1'b0;
// connect the ends of chain 0 & 1
assign ext_port[0][1] = ext_port[1][0];
assign ext_port_ready[1][0] = ext_port_ready[0][1];
// dump chain 1
assign ext_port_ready[1][1] = 1'b1;
endmodule // debug_ring
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Wei Song <ws327@cam.ac.uk>
// Stefan Wallentowitz <stefan@wallentowitz.de>
import dii_package::dii_flit;
module debug_ring_expand
#(parameter PORTS = 1,
parameter BUFFER_SIZE = 4)
(input clk, rst,
input [PORTS-1:0][15:0] id_map,
input dii_flit [PORTS-1:0] dii_in, output [PORTS-1:0] dii_in_ready,
output dii_flit [PORTS-1:0] dii_out, input [PORTS-1:0] dii_out_ready,
input dii_flit [1:0] ext_in, output [1:0] ext_in_ready, // extension input ports
output dii_flit [1:0] ext_out, input [1:0] ext_out_ready // extension output ports
);
genvar i;
dii_flit [1:0][PORTS:0] chain;
logic [1:0][PORTS:0] chain_ready;
generate
for(i=0; i<PORTS; i++) begin : gen_router
ring_router
#(.BUFFER_SIZE(BUFFER_SIZE))
u_router(
.*,
.id ( id_map[i] ),
.ring_in0 ( chain[0][i] ),
.ring_in0_ready ( chain_ready[0][i] ),
.ring_in1 ( chain[1][i] ),
.ring_in1_ready ( chain_ready[1][i] ),
.ring_out0 ( chain[0][i+1] ),
.ring_out0_ready ( chain_ready[0][i+1] ),
.ring_out1 ( chain[1][i+1] ),
.ring_out1_ready ( chain_ready[1][i+1] ),
.local_in ( dii_in[i] ),
.local_in_ready ( dii_in_ready[i] ),
.local_out ( dii_out[i] ),
.local_out_ready ( dii_out_ready[i] )
);
end // for (i=0; i<PORTS, i++)
endgenerate
// the expanded ports
generate
for(i=0; i<2; i++) begin
assign chain[i][0] = ext_in[i];
assign ext_in_ready[i] = chain_ready[i][0];
assign ext_out[i] = chain[i][PORTS];
assign chain_ready[i][PORTS] = ext_out_ready[i];
end
endgenerate
endmodule // debug_ring_expand
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Wei Song <ws327@cam.ac.uk>
// Stefan Wallentowitz <stefan@wallentowitz.de>
import dii_package::dii_flit;
import dii_package::dii_flit_assemble;
module dii_buffer
#(
parameter BUF_SIZE = 4, // length of the buffer
parameter FULLPACKET = 0
)
(
input clk, rst,
output logic [$clog2(BUF_SIZE):0] packet_size,
input dii_flit flit_in,
output flit_in_ready,
output dii_flit flit_out,
input flit_out_ready
);
localparam ID_W = $clog2(BUF_SIZE); // the width of the index
// internal shift register
dii_flit [BUF_SIZE-1:0] data;
reg [ID_W:0] rp; // read pointer
logic reg_out_valid; // local output valid
logic flit_in_fire, flit_out_fire;
assign flit_in_ready = (rp != BUF_SIZE - 1) || !reg_out_valid;
assign flit_in_fire = flit_in.valid && flit_in_ready;
assign flit_out_fire = flit_out.valid && flit_out_ready;
always_ff @(posedge clk)
if(rst)
reg_out_valid <= 0;
else if(flit_in.valid)
reg_out_valid <= 1;
else if(flit_out_fire && rp == 0)
reg_out_valid <= 0;
always_ff @(posedge clk)
if(rst)
rp <= 0;
else if(flit_in_fire && !flit_out_fire && reg_out_valid)
rp <= rp + 1;
else if(flit_out_fire && !flit_in_fire && rp != 0)
rp <= rp - 1;
always @(posedge clk)
if(flit_in_fire)
data <= {data, flit_in};
generate // SRL does not allow parallel read
if(FULLPACKET != 0) begin
logic [BUF_SIZE-1:0] data_last_buf, data_last_shifted;
always_ff @(posedge clk)
if(rst)
data_last_buf <= 0;
else if(flit_in_fire)
data_last_buf <= {data_last_buf, flit_in.last && flit_in.valid};
// extra logic to get the packet size in a stable manner
assign data_last_shifted = data_last_buf << BUF_SIZE - 1 - rp;
function logic [ID_W:0] find_first_one(input logic [BUF_SIZE-1:0] data);
automatic int i;
for(i=BUF_SIZE-1; i>=0; i--)
if(data[i]) return i;
return BUF_SIZE;
endfunction // size_count
assign packet_size = BUF_SIZE - find_first_one(data_last_shifted);
always_comb begin
flit_out = data[rp];
flit_out.valid = reg_out_valid && |data_last_shifted;
end
end else begin // if (FULLPACKET)
assign packet_size = 0;
always_comb begin
flit_out = data[rp];
flit_out.valid = reg_out_valid;
end
end
endgenerate
endmodule // dii_buffer
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Wei Song <ws327@cam.ac.uk>
// Stefan Wallentowitz <stefan@wallentowitz.de>
package dii_package;
typedef struct packed unsigned {
logic valid;
logic last;
logic [15:0] data;
} dii_flit;
function dii_flit
dii_flit_assemble(
input logic m_valid,
input logic m_last,
input logic [15:0] m_data
);
return dii_flit'{m_valid, m_last, m_data};
endfunction
endpackage // dii_package
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Wei Song <ws327@cam.ac.uk>
// Stefan Wallentowitz <stefan@wallentowitz.de>
interface dii_channel_flat
#(parameter N = 'x);
logic [N*16-1:0] data;
logic [N-1:0] first;
logic [N-1:0] last;
logic [N-1:0] valid;
logic [N-1:0] ready;
endinterface // dii_channel_flat
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Stefan Wallentowitz <stefan@wallentowitz.de>
package opensocdebug;
typedef struct packed {
logic [31:0] insn;
logic [31:0] pc;
logic jb;
logic jal;
logic jr;
logic [31:0] jbtarget;
logic valid;
logic [31:0] wbdata;
logic [4:0] wbreg;
logic wben;
} mor1kx_trace_exec;
endpackage // opensocdebug
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Wei Song <ws327@cam.ac.uk>
// Stefan Wallentowitz <stefan@wallentowitz.de>
module osd_fifo
#(parameter WIDTH = 'x,
parameter DEPTH = 'x)
(
input clk,
input rst,
input [WIDTH-1:0] in_data,
input in_valid,
output in_ready,
output [WIDTH-1:0] out_data,
output out_valid,
input out_ready
);
// Signals for fifo
reg [WIDTH-1:0] fifo_data [0:DEPTH-1]; //actual fifo
reg [WIDTH-1:0] nxt_fifo_data [0:DEPTH-1];
reg [DEPTH:0] fifo_write_ptr;
wire pop;
wire push;
assign pop = out_valid & out_ready;
assign push = in_valid & in_ready;
assign out_data = fifo_data[0];
assign out_valid = !fifo_write_ptr[0];
assign in_ready = !fifo_write_ptr[DEPTH];
always @(posedge clk) begin
if (rst) begin
fifo_write_ptr <= {{DEPTH{1'b0}},1'b1};
end else if (push & !pop) begin
fifo_write_ptr <= fifo_write_ptr << 1;
end else if (!push & pop) begin
fifo_write_ptr <= fifo_write_ptr >> 1;
end
end
always @(*) begin : shift_register_comb
integer i;
for (i=0;i<DEPTH;i=i+1) begin
if (pop) begin
if (push & fifo_write_ptr[i+1]) begin
nxt_fifo_data[i] = in_data;
end else if (i<DEPTH-1) begin
nxt_fifo_data[i] = fifo_data[i+1];
end else begin
nxt_fifo_data[i] = fifo_data[i];
end
end else if (push & fifo_write_ptr[i]) begin
nxt_fifo_data[i] = in_data;
end else begin
nxt_fifo_data[i] = fifo_data[i];
end
end
end
always @(posedge clk) begin : shift_register_seq
integer i;
for (i=0;i<DEPTH;i=i+1) begin
fifo_data[i] <= nxt_fifo_data[i];
end
end
endmodule // noc_fifo
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Stefan Wallentowitz <stefan@wallentowitz.de>
import dii_package::dii_flit;
module osd_mam
#(parameter DATA_WIDTH = 16, // data width in bits, must be multiple of 16
parameter ADDR_WIDTH = 32, // address width in bits
parameter MAX_PKT_LEN = 'x,
parameter REGIONS = 1,
parameter MEM_SIZE0 = 'x,
parameter BASE_ADDR0 = 'x,
parameter MEM_SIZE1 = 'x,
parameter BASE_ADDR1 = 'x,
parameter MEM_SIZE2 = 'x,
parameter BASE_ADDR2 = 'x,
parameter MEM_SIZE3 = 'x,
parameter BASE_ADDR3 = 'x,
parameter MEM_SIZE4 = 'x,
parameter BASE_ADDR4 = 'x,
parameter MEM_SIZE5 = 'x,
parameter BASE_ADDR5 = 'x,
parameter MEM_SIZE6 = 'x,
parameter BASE_ADDR6 = 'x,
parameter MEM_SIZE7 = 'x,
parameter BASE_ADDR7 = 'x,
parameter ENDIAN = 1 // 0 little-endian, 1 big-endian
)
(
input clk, rst,
input dii_flit debug_in, output debug_in_ready,
output dii_flit debug_out, input debug_out_ready,
input [15:0] id,
output reg req_valid, // Start a new memory access request
input req_ready, // Acknowledge the new memory access request
output reg req_we, // 0: Read, 1: Write
output reg [ADDR_WIDTH-1:0] req_addr, // Request base address
output reg req_burst, // 0 for single beat access, 1 for incremental burst
output reg [12:0] req_beats, // Burst length in number of words
output reg req_sync, // Request a synchronous access
output reg write_valid, // Next write data is valid
output reg [DATA_WIDTH-1:0] write_data, // Write data
output reg [DATA_WIDTH/8-1:0] write_strb, // Byte strobe if req_burst==0
input write_ready, // Acknowledge this data item
input write_complete, // Signal completion if sync access
input read_valid, // Next read data is valid
input [DATA_WIDTH-1:0] read_data, // Read data
output reg read_ready // Acknowledge this data item
);
initial begin
assert(DATA_WIDTH[2:0] == 0)
else $fatal(1, "datawidth of MAM read/write port must be times of bytes!");
end
function logic [DATA_WIDTH-1:0] endian_conv(input logic [DATA_WIDTH-1:0] din);
int i;
// should be "static int", but unsupported by Verilator currently, see
// https://www.veripool.org/issues/546-Verilator-Support-static-inside-task
int total = DATA_WIDTH/8;
for(i=0; i<total; i++)
endian_conv[i*8 +: 8] = din[(total-i-1)*8 +: 8];
endfunction // endian_conv
logic [DATA_WIDTH-1:0] read_data_m, write_data_m;
assign read_data_m = ENDIAN ? read_data : endian_conv(read_data);
assign write_data = ENDIAN ? write_data_m : endian_conv(write_data_m);
logic reg_request;
logic reg_write;
logic [15:0] reg_addr;
logic [1:0] reg_size;
logic [15:0] reg_wdata;
logic reg_ack;
logic reg_err;
logic [15:0] reg_rdata;
logic stall;
dii_flit dp_out, dp_in;
logic dp_out_ready, dp_in_ready;
osd_regaccess_layer
#(.MOD_VENDOR(16'h1), .MOD_TYPE(16'h3), .MOD_VERSION(16'h0),
.MOD_EVENT_DEST_DEFAULT(16'h0), .MAX_REG_SIZE(16), .CAN_STALL(0))
u_regaccess(.*,
.event_dest (),
.module_in (dp_out),
.module_in_ready (dp_out_ready),
.module_out (dp_in),
.module_out_ready (dp_in_ready));
assign reg_ack = 1'b1;
logic [63:0] base_addr [8];
assign base_addr[0] = 64'(BASE_ADDR0);
assign base_addr[1] = 64'(BASE_ADDR1);
assign base_addr[2] = 64'(BASE_ADDR2);
assign base_addr[3] = 64'(BASE_ADDR3);
assign base_addr[4] = 64'(BASE_ADDR4);
assign base_addr[5] = 64'(BASE_ADDR5);
assign base_addr[6] = 64'(BASE_ADDR6);
assign base_addr[7] = 64'(BASE_ADDR7);
logic [63:0] mem_size [8];
assign mem_size[0] = 64'(MEM_SIZE0);
assign mem_size[1] = 64'(MEM_SIZE1);
assign mem_size[2] = 64'(MEM_SIZE2);
assign mem_size[3] = 64'(MEM_SIZE3);
assign mem_size[4] = 64'(MEM_SIZE4);
assign mem_size[5] = 64'(MEM_SIZE5);
assign mem_size[6] = 64'(MEM_SIZE6);
assign mem_size[7] = 64'(MEM_SIZE7);
always_comb begin
reg_err = 1'b0;
reg_rdata = 16'hx;
if (reg_addr[15:7] == 9'h4) // 0x200
case (reg_addr)
16'h200: reg_rdata = 16'(DATA_WIDTH);
16'h201: reg_rdata = 16'(ADDR_WIDTH);
16'h202: reg_rdata = 16'(REGIONS);
default: reg_err = 1'b1;
endcase
else if (reg_addr[15:7] == 9'h5) // 0x280-0x300
if (reg_addr[3])
reg_err = 1'b1;
else if (reg_addr[6:4] > REGIONS)
reg_err = 1'b1;
else if (reg_addr[2] == 0) // addr
case (reg_addr[1:0])
0: reg_rdata = base_addr[reg_addr[6:4]][15:0];
1: reg_rdata = base_addr[reg_addr[6:4]][31:16];
2: reg_rdata = base_addr[reg_addr[6:4]][47:32];
3: reg_rdata = base_addr[reg_addr[6:4]][63:48];
endcase // case (reg_addr[1:0])
else
case (reg_addr[1:0])
0: reg_rdata = mem_size[reg_addr[6:4]][15:0];
1: reg_rdata = mem_size[reg_addr[6:4]][31:16];
2: reg_rdata = mem_size[reg_addr[6:4]][47:32];
3: reg_rdata = mem_size[reg_addr[6:4]][63:48];
endcase // case (reg_addr[1:0])
end
enum {
STATE_INACTIVE, STATE_DI_SRC, STATE_DI_FLAGS, STATE_HDR, STATE_ADDR,
STATE_REQUEST, STATE_WRITE_PACKET, STATE_WRITE, STATE_WRITE_WAIT,
STATE_READ_PACKET, STATE_READ, STATE_READ_WAIT, STATE_WRITE_SINGLE,
STATE_WRITE_SINGLE_WAIT, STATE_SYNC_WAIT, STATE_SYNC_PACKET
} state, nxt_state;
// The counter is used to count flits
reg [$clog2(MAX_PKT_LEN)-1:0] counter;
logic [$clog2(MAX_PKT_LEN)-1:0] nxt_counter;
// This counter is used to count words (that can span packets)
localparam WCOUNTER_WIDTH = (DATA_WIDTH == 16) ? 1 : $clog2(DATA_WIDTH);
reg [WCOUNTER_WIDTH-1:0] wcounter;
logic [WCOUNTER_WIDTH-1:0] nxt_wcounter;
// Stores whether we are inside a packet
reg in_packet;
logic nxt_in_packet;
// Stores whether the last address flit is the last flit in a packet
// Decides whether to go to STATE_WRITE or STATE_WRITE_PACKET
reg is_last_flit;
logic nxt_is_last_flit;
// Combinational part of interface
logic [12:0] nxt_req_beats;
logic nxt_req_we;
logic nxt_req_burst;
logic nxt_req_sync;
logic [ADDR_WIDTH-1:0] nxt_req_addr;
logic [DATA_WIDTH/8-1:0] nxt_write_strb;
reg [DATA_WIDTH-1:0] write_data_reg;
logic [DATA_WIDTH-1:0] nxt_write_data_reg;
logic [15:0] req_di_src;
logic [15:0] nxt_req_di_src;
// This is the number of (16 bit) words needed to form an address
localparam ADDR_WORDS = ADDR_WIDTH >> 4;
always_ff @(posedge clk) begin
if (rst) begin
state <= STATE_INACTIVE;
end else begin
state <= nxt_state;
end
req_beats <= nxt_req_beats;
req_we <= nxt_req_we;
req_burst <= nxt_req_burst;
req_addr <= nxt_req_addr;
req_sync <= nxt_req_sync;
req_di_src <= nxt_req_di_src;
counter <= nxt_counter;
write_data_reg <= nxt_write_data_reg;
wcounter <= nxt_wcounter;
in_packet <= nxt_in_packet;
is_last_flit <= nxt_is_last_flit;
write_strb <= nxt_write_strb;
end
integer i;
always_comb begin
nxt_state = state;
nxt_counter = counter;
nxt_req_beats = req_beats;
nxt_write_data_reg = write_data_reg;
nxt_wcounter = wcounter;
nxt_in_packet = in_packet;
nxt_is_last_flit = is_last_flit;
nxt_write_strb = write_strb;
nxt_req_we = req_we;
nxt_req_burst = req_burst;
nxt_req_sync = req_sync;
nxt_req_addr = req_addr;
nxt_req_di_src = req_di_src;
dp_in_ready = 0;
dp_out.valid = 0;
dp_out.data = 16'hx;
dp_out.last = 0;
req_valid = 0;
write_valid = 0;
write_data_m = write_data_reg;
read_ready = 0;
case (state)
STATE_INACTIVE: begin
dp_in_ready = 1;
if (dp_in.valid) begin
nxt_state = STATE_DI_SRC;
end
end
STATE_DI_SRC: begin
dp_in_ready = 1;
nxt_req_di_src = dp_in.data;
if (dp_in.valid) begin
nxt_state = STATE_DI_FLAGS;
end
end
STATE_DI_FLAGS: begin
dp_in_ready = 1;
if (dp_in.valid) begin
nxt_state = STATE_HDR;
end
end
STATE_HDR: begin
dp_in_ready = 1;
nxt_req_we = dp_in.data[15];
nxt_req_burst = dp_in.data[14];
nxt_req_sync = dp_in.data[13];
nxt_write_strb = dp_in.data[DATA_WIDTH/8-1:0];
if (nxt_req_burst)
nxt_req_beats = {5'h0, dp_in.data[7:0]};
else
nxt_req_beats = 13'h1;
if (dp_in.valid) begin
nxt_state = STATE_ADDR;
nxt_counter = 0;
end
end
STATE_ADDR: begin
dp_in_ready = 1;
nxt_req_addr[ADDR_WIDTH - counter*16 - 1 -: 16] = dp_in.data;
if (dp_in.valid) begin
nxt_counter = counter + 1;
if (counter == ADDR_WORDS - 1) begin
nxt_is_last_flit = dp_in.last;
nxt_state = STATE_REQUEST;
end
end
end
STATE_REQUEST: begin
req_valid = 1;
if (req_ready) begin
nxt_is_last_flit = 0;
if (req_we) begin
if (req_burst) begin
if (is_last_flit) begin
nxt_state = STATE_WRITE_PACKET;
end else begin
nxt_state = STATE_WRITE;
end
end else begin
nxt_state = STATE_WRITE_SINGLE;
end
end else begin
nxt_state = STATE_READ_PACKET;
end
nxt_wcounter = 0;
nxt_counter = 0;
nxt_in_packet = 0;
end
end
STATE_WRITE_PACKET: begin
dp_in_ready = 1;
if (dp_in.valid) begin
nxt_counter = counter + 1;
if (counter == 2) begin
nxt_state = STATE_WRITE;
end
end
end
STATE_WRITE: begin
nxt_write_data_reg[(DATA_WIDTH/16-wcounter)*16-1 -: 16] = dp_in.data;
write_data_m[(DATA_WIDTH/16-wcounter)*16-1 -: 16] = dp_in.data;
dp_in_ready = 1;
if (dp_in.valid) begin
nxt_wcounter = wcounter + 1;
if (wcounter == DATA_WIDTH/16 - 1) begin
write_valid = 1;
if (!write_ready) begin
nxt_state = STATE_WRITE_WAIT;
nxt_in_packet = !dp_in.last;
end else begin
nxt_req_beats = req_beats - 1;
if (req_beats == 1) begin
if (!req_sync) begin
nxt_state = STATE_INACTIVE;
end else begin
if (!write_complete) begin
nxt_state = STATE_SYNC_WAIT;
end else begin
nxt_state = STATE_SYNC_PACKET;
nxt_counter = 0;
end
end
end else if (dp_in.last) begin
nxt_counter = 0;
nxt_state = STATE_WRITE_PACKET;
end
end
nxt_wcounter = 0;
end else begin
if (dp_in.last) begin
nxt_counter = 0;
nxt_state = STATE_WRITE_PACKET;
end
end
end
end // case: STATE_WRITE
STATE_WRITE_WAIT: begin
write_valid = 1;
if (write_ready) begin
nxt_req_beats = req_beats - 1;
if (req_beats == 1) begin
if (!req_sync) begin
nxt_state = STATE_INACTIVE;
end else begin
if (!write_complete) begin
nxt_state = STATE_SYNC_WAIT;
end else begin
nxt_state = STATE_SYNC_PACKET;
nxt_counter = 0;
end
end
end else begin
if (in_packet) begin
nxt_state = STATE_WRITE;
end else begin
nxt_counter = 0;
nxt_state = STATE_WRITE_PACKET;
end
end
end
end // case: STATE_WRITE_WAIT
STATE_WRITE_SINGLE: begin
nxt_write_data_reg[(DATA_WIDTH/16-wcounter)*16-1 -: 16] = dp_in.data;
write_data_m[(DATA_WIDTH/16-wcounter)*16-1 -: 16] = dp_in.data;
dp_in_ready = 1;
if (dp_in.valid) begin
nxt_wcounter = wcounter + 1;
if (wcounter == DATA_WIDTH/16 - 1) begin
write_valid = 1;
if (!write_ready) begin
nxt_state = STATE_WRITE_SINGLE_WAIT;
end else begin
if (!req_sync) begin
nxt_state = STATE_INACTIVE;
end else begin
if (!write_complete) begin
nxt_state = STATE_SYNC_WAIT;
end else begin
nxt_state = STATE_SYNC_PACKET;
nxt_counter = 0;
end
end
end
end
end
end
STATE_WRITE_SINGLE_WAIT: begin
write_valid = 1;
if (write_ready) begin
if (!req_sync) begin
nxt_state = STATE_INACTIVE;
end else begin
if (!write_complete) begin
nxt_state = STATE_SYNC_WAIT;
end else begin
nxt_state = STATE_SYNC_PACKET;
nxt_counter = 0;
end
end
end
end
STATE_SYNC_WAIT: begin
if (write_complete) begin
nxt_state = STATE_SYNC_PACKET;
end
end
STATE_SYNC_PACKET: begin
dp_out.valid = 1;
if (counter == 0) begin
// DI DEST
dp_out.data = req_di_src;
end else if (counter == 1) begin
// DI SRC
dp_out.data = id;
end else begin
// DI FLAGS
dp_out.data[15:14] = 2'b10; // FLAGS.TYPE = EVENT
dp_out.data[13:10] = 4'b0000; // FLAGS.TYPE_SUB = 0
dp_out.data[9:0] = 10'h0; // reserved
dp_out.last = 1;
end
if (dp_out_ready) begin
nxt_counter = counter + 1;
if (counter == 2) begin
nxt_state = STATE_INACTIVE;
end
end
end
STATE_READ_PACKET: begin
dp_out.valid = 1;
if (counter == 0) begin
// DI DEST
dp_out.data = req_di_src;
end else if (counter == 1) begin
// DI SRC
dp_out.data = id;
end else begin
// DI FLAGS
dp_out.data[15:14] = 2'b10; // FLAGS.TYPE = EVENT
dp_out.data[13:10] = 4'b0000; // FLAGS.TYPE_SUB = 0
dp_out.data[9:0] = 10'h0; // reserved
end
if (dp_out_ready) begin
nxt_counter = counter + 1;
if (counter == 2) begin
nxt_state = STATE_READ;
end
end
end // case: STATE_READ_PACKET
STATE_READ: begin
if (read_valid) begin
dp_out.valid = 1;
dp_out.last = (counter == MAX_PKT_LEN - 2) ||
((wcounter == DATA_WIDTH/16 - 1) && (req_beats == 1));
dp_out.data = read_data_m[(DATA_WIDTH/16-wcounter)*16-1 -: 16];
if (dp_out_ready) begin
nxt_wcounter = wcounter + 1;
if (wcounter == DATA_WIDTH/16-1) begin
nxt_req_beats = req_beats - 1;
nxt_wcounter = 0;
read_ready = 1;
if (req_beats == 1) begin
nxt_state = STATE_INACTIVE;
end else begin
if (counter == MAX_PKT_LEN - 2) begin
nxt_state = STATE_READ_PACKET;
nxt_counter = 0;
end else begin
nxt_counter = counter + 1;
end
end
end else begin
if (counter == MAX_PKT_LEN - 2) begin
nxt_state = STATE_READ_PACKET;
nxt_counter = 0;
end else begin
nxt_counter = counter + 1;
end
end
end
end
end
endcase
end
endmodule // osd_dem_uart
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Nico Gutmann <nicolai.gutmann@gmail.com>
import dii_package::dii_flit;
module osd_mam_wb
#(parameter DATA_WIDTH = 16, // in bits, must be multiple of 16
parameter ADDR_WIDTH = 32,
parameter MAX_PKT_LEN = 'x,
parameter REGIONS = 1,
parameter MEM_SIZE0 = 'x,
parameter BASE_ADDR0 = 'x,
parameter MEM_SIZE1 = 'x,
parameter BASE_ADDR1 = 'x,
parameter MEM_SIZE2 = 'x,
parameter BASE_ADDR2 = 'x,
parameter MEM_SIZE3 = 'x,
parameter BASE_ADDR3 = 'x,
parameter MEM_SIZE4 = 'x,
parameter BASE_ADDR4 = 'x,
parameter MEM_SIZE5 = 'x,
parameter BASE_ADDR5 = 'x,
parameter MEM_SIZE6 = 'x,
parameter BASE_ADDR6 = 'x,
parameter MEM_SIZE7 = 'x,
parameter BASE_ADDR7 = 'x,
//Byte select width
localparam SW = (DATA_WIDTH == 32) ? 4 :
(DATA_WIDTH == 16) ? 2 :
(DATA_WIDTH == 8) ? 1 : 'hx
) (
input clk_i, rst_i,
input dii_flit debug_in, output debug_in_ready,
output dii_flit debug_out, input debug_out_ready,
input [15:0] id,
output stb_o,
output cyc_o,
input ack_i,
output we_o,
output [ADDR_WIDTH-1:0] addr_o,
output [DATA_WIDTH-1:0] dat_o,
input [DATA_WIDTH-1:0] dat_i,
output [2:0] cti_o,
output [1:0] bte_o,
output [SW-1:0] sel_o
);
logic req_valid;
logic req_ready;
logic req_we;
logic [ADDR_WIDTH-1:0] req_addr;
logic req_burst;
logic [13:0] req_beats;
logic req_sync;
logic write_valid;
logic [DATA_WIDTH-1:0] write_data;
logic [DATA_WIDTH/8-1:0] write_strb;
logic write_ready;
logic write_complete;
logic read_valid;
logic [DATA_WIDTH-1:0] read_data;
logic read_ready;
osd_mam
#(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH),
.MAX_PKT_LEN(MAX_PKT_LEN), .REGIONS(REGIONS),
.BASE_ADDR0(BASE_ADDR0), .MEM_SIZE0(MEM_SIZE0),
.BASE_ADDR1(BASE_ADDR1), .MEM_SIZE1(MEM_SIZE1),
.BASE_ADDR2(BASE_ADDR2), .MEM_SIZE2(MEM_SIZE2),
.BASE_ADDR3(BASE_ADDR3), .MEM_SIZE3(MEM_SIZE3),
.BASE_ADDR4(BASE_ADDR4), .MEM_SIZE4(MEM_SIZE4),
.BASE_ADDR5(BASE_ADDR5), .MEM_SIZE5(MEM_SIZE5),
.BASE_ADDR6(BASE_ADDR6), .MEM_SIZE6(MEM_SIZE6),
.BASE_ADDR7(BASE_ADDR7), .MEM_SIZE7(MEM_SIZE7))
u_mam(.*,
.clk(clk_i),
.rst(rst_i));
assign write_complete = 1'b1;
osd_mam_wb_if
#(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH))
u_mam_wb_if(.*);
endmodule
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Nico Gutmann <nicolai.gutmann@gmail.com>
module osd_mam_wb_if
#(parameter DATA_WIDTH = 16, // in bits, must be multiple of 16
parameter ADDR_WIDTH = 32,
//Byte select width
localparam SW = (DATA_WIDTH == 32) ? 4 :
(DATA_WIDTH == 16) ? 2 :
(DATA_WIDTH == 8) ? 1 : 'hx
)
(
input clk_i, rst_i,
input req_valid, // Start a new memory access request
output reg req_ready, // Acknowledge the new memory access request
input req_we, // 0: Read, 1: Write
input [ADDR_WIDTH-1:0] req_addr, // Request base address
input req_burst, // 0 for single beat access, 1 for incremental burst
input [13:0] req_beats, // Burst length in number of words
input write_valid, // Next write data is valid
input [DATA_WIDTH-1:0] write_data, // Write data
input [DATA_WIDTH/8-1:0] write_strb, // Byte strobe if req_burst==0
output reg write_ready, // Acknowledge this data item
output reg read_valid, // Next read data is valid
output reg [DATA_WIDTH-1:0] read_data, // Read data
input read_ready, // Acknowledge this data item
output reg stb_o,
output cyc_o,
input ack_i,
output reg we_o,
output reg [ADDR_WIDTH-1:0] addr_o,
output reg [DATA_WIDTH-1:0] dat_o,
input [DATA_WIDTH-1:0] dat_i,
output reg [2:0] cti_o,
output reg [1:0] bte_o,
output reg [SW-1:0] sel_o
);
enum { STATE_IDLE, STATE_WRITE_LAST, STATE_WRITE_LAST_WAIT,
STATE_WRITE, STATE_WRITE_WAIT, STATE_READ,
STATE_READ_WAIT } state, nxt_state;
logic nxt_we_o;
logic [2:0] nxt_cti_o;
logic [1:0] nxt_bte_o;
reg [DATA_WIDTH-1:0] read_data_reg;
logic [DATA_WIDTH-1:0] nxt_read_data_reg;
reg [DATA_WIDTH-1:0] dat_o_reg;
logic [DATA_WIDTH-1:0] nxt_dat_o_reg;
logic [ADDR_WIDTH-1:0] nxt_addr_o;
reg [13:0] beats;
logic [13:0] nxt_beats;
//registers
always_ff @(posedge clk_i) begin
if (rst_i) begin
state <= STATE_IDLE;
end else begin
state <= nxt_state;
end
we_o <= nxt_we_o;
cti_o <= nxt_cti_o;
bte_o <= nxt_bte_o;
read_data_reg <= nxt_read_data_reg;
dat_o_reg <= nxt_dat_o_reg;
addr_o <= nxt_addr_o;
beats <= nxt_beats;
end
assign cyc_o = stb_o;
//state & output logic
always_comb begin
nxt_state = state;
nxt_we_o = we_o;
nxt_cti_o = cti_o;
nxt_bte_o = 2'b0;
nxt_read_data_reg = read_data_reg;
nxt_dat_o_reg = dat_o_reg;
nxt_addr_o = addr_o;
nxt_beats = beats;
sel_o = '{default:'1};
stb_o = 0;
req_ready = 0;
write_ready = 0;
read_valid = 0;
dat_o = dat_o_reg;
read_data = read_data_reg;
case (state)
STATE_IDLE: begin
req_ready = 1;
nxt_beats = req_beats;
nxt_addr_o = req_addr;
if (req_valid) begin
if (req_we) begin
nxt_we_o = 1;
if (req_burst) begin
if (nxt_beats == 1) begin
nxt_cti_o = 3'b111;
if (write_valid) begin
nxt_state = STATE_WRITE_LAST;
nxt_dat_o_reg = write_data;
end else begin
nxt_state = STATE_WRITE_LAST_WAIT;
end
end else begin
nxt_cti_o = 3'b010;
nxt_bte_o = 2'b00;
if (write_valid) begin
nxt_state = STATE_WRITE;
nxt_dat_o_reg = write_data;
end else begin
nxt_state = STATE_WRITE_WAIT;
end
end
end else begin // !req_burst
nxt_cti_o = 3'b111;
if (write_valid) begin
nxt_state = STATE_WRITE_LAST;
nxt_dat_o_reg = write_data;
end else begin
nxt_state = STATE_WRITE_LAST_WAIT;
end
end // if (req_burst)
end else begin // req_we == 0
nxt_we_o = 0;
nxt_state = STATE_READ;
if (req_burst) begin
if (nxt_beats == 1) begin
nxt_cti_o = 3'b111;
end else begin
nxt_cti_o = 3'b010;
end
end else begin // !req_burst
nxt_cti_o = 3'b111;
end // if (req_burst)
end // if (req_we)
end // if (req_valid)
end //STATE_IDLE
STATE_WRITE_LAST_WAIT: begin
write_ready = 1;
if (write_valid) begin
nxt_state = STATE_WRITE_LAST;
nxt_dat_o_reg = write_data;
end
end //STATE_WRITE_LAST_WAIT
STATE_WRITE_LAST: begin
stb_o = 1;
if (ack_i) begin
nxt_state = STATE_IDLE;
nxt_cti_o = 3'b000;
end
end //STATE_WRITE_LAST
STATE_WRITE_WAIT: begin
write_ready = 1;
if (write_valid) begin
nxt_state = STATE_WRITE;
nxt_dat_o_reg = write_data;
nxt_beats = beats - 1;
end
end //STATE_WRITE_WAIT
STATE_WRITE: begin
stb_o = 1;
if (ack_i) begin
write_ready = 1;
nxt_addr_o = addr_o + DATA_WIDTH/8;
if (beats == 1) begin
nxt_cti_o=3'b111;
if (write_valid) begin
nxt_state = STATE_WRITE_LAST;
nxt_dat_o_reg = write_data;
end else begin
nxt_state = STATE_WRITE_LAST_WAIT;
end
end else begin // beats != 1
if (write_valid) begin
nxt_state = STATE_WRITE;
nxt_dat_o_reg = write_data;
nxt_beats = beats - 1;
end else begin
nxt_state = STATE_WRITE_WAIT;
end
end // if (beats == 1)
end // if (ack_i)
end // STATE_WRITE
STATE_READ: begin
stb_o = 1;
if (ack_i) begin
nxt_read_data_reg = dat_i;
nxt_beats = beats - 1;
nxt_addr_o = addr_o + DATA_WIDTH/8;
nxt_state = STATE_READ_WAIT;
end
end
STATE_READ_WAIT: begin
read_valid = 1;
if (read_ready) begin
if (beats == 1) begin
nxt_cti_o = 3'b111;
end
if (beats == 0) begin
nxt_state = STATE_IDLE;
end else begin
nxt_state = STATE_READ;
end
end
end //STATE_READ_WAIT
endcase// Case (state)
end // always_comb
endmodule
|
// Copyright 2016-2017 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Philipp Wagner <philipp.wagner@tum.de>
// Stefan Wallentowitz <stefan@wallentowitz.de>
import dii_package::dii_flit;
/**
* Module: osd_regaccess
*
* Handle register accesses to a debug modules. Accesses to the base registers
* (0x0000 - 0x01ff) are answered directly by this module, all other accesses
* are available on the reg_* ports to be handled by the debug module itself.
*/
module osd_regaccess
#(parameter MOD_VENDOR = 'x, // module vendor
parameter MOD_TYPE = 'x, // module type
parameter MOD_VERSION = 'x, // module version
parameter MOD_EVENT_DEST_DEFAULT = 'x, // default event destination
parameter CAN_STALL = 0,
parameter MAX_REG_SIZE = 16)
(input clk, rst,
input [15:0] id,
input dii_flit debug_in, output logic debug_in_ready,
output dii_flit debug_out, input debug_out_ready,
output reg reg_request,
output reg_write,
output [15:0] reg_addr,
output [1:0] reg_size,
output [15:0] reg_wdata,
input reg_ack,
input reg_err,
input [15:0] reg_rdata,
output [15:0] event_dest,
output stall);
localparam ACCESS_SIZE_16 = 2'b00;
localparam ACCESS_SIZE_32 = 2'b01;
localparam ACCESS_SIZE_64 = 2'b10;
localparam ACCESS_SIZE_128 = 2'b11;
// base register addresses
localparam REG_MOD_VENDOR = 16'h0;
localparam REG_MOD_TYPE = 16'h1;
localparam REG_MOD_VERSION = 16'h2;
localparam REG_MOD_CS = 16'h3;
localparam REG_MOD_CS_ACTIVE = 0;
localparam REG_MOD_EVENT_DEST = 16'h4;
// Registers
reg mod_cs_active;
logic nxt_mod_cs_active;
reg [15:0] mod_event_dest;
reg [15:0] nxt_mod_event_dest;
assign stall = CAN_STALL ? ~mod_cs_active : 1'b0;
assign event_dest = mod_event_dest;
// State machine
enum {
STATE_IDLE, STATE_REQ_HDR_SRC, STATE_REQ_HDR_FLAGS, STATE_ADDR,
STATE_WRITE, STATE_RESP_HDR_DEST, STATE_RESP_HDR_SRC,
STATE_RESP_HDR_FLAGS, STATE_RESP_VALUE, STATE_DROP, STATE_EXT_START,
STATE_EXT_WAIT
} state, nxt_state;
// Local request/response data
reg req_write;
reg [1:0] req_size;
reg [15:0] req_addr;
reg [MAX_REG_SIZE-1:0] reqresp_value;
reg [15:0] resp_dest;
reg resp_error;
logic nxt_req_write;
logic [1:0] nxt_req_size;
logic [15:0] nxt_req_addr;
logic [MAX_REG_SIZE-1:0] nxt_reqresp_value;
logic [15:0] nxt_resp_dest;
logic nxt_resp_error;
logic reg_addr_is_ext;
logic [8:0] reg_addr_internal;
// handle the base addresses 0x0000 - 0x01ff as "internal"
assign reg_addr_is_ext = (debug_in.data[15:9] != 0);
assign reg_addr_internal = debug_in.data[8:0];
assign reg_write = req_write;
assign reg_addr = req_addr;
assign reg_size = req_size;
assign reg_wdata = reqresp_value;
always @(posedge clk) begin
if (rst) begin
state <= STATE_IDLE;
mod_cs_active <= 0;
mod_event_dest <= 16'(MOD_EVENT_DEST_DEFAULT);
end else begin
state <= nxt_state;
mod_cs_active <= nxt_mod_cs_active;
mod_event_dest <= nxt_mod_event_dest;
end
resp_dest <= nxt_resp_dest;
reqresp_value <= nxt_reqresp_value;
resp_error <= nxt_resp_error;
req_write <= nxt_req_write;
req_size <= nxt_req_size;
req_addr <= nxt_req_addr;
end
always @(*) begin
nxt_state = state;
nxt_req_write = req_write;
nxt_req_size = req_size;
nxt_req_addr = req_addr;
nxt_resp_dest = resp_dest;
nxt_reqresp_value = reqresp_value;
nxt_resp_error = resp_error;
nxt_mod_cs_active = mod_cs_active;
nxt_mod_event_dest = mod_event_dest;
debug_in_ready = 0;
debug_out = 0;
reg_request = 0;
case (state)
STATE_IDLE: begin
debug_in_ready = 1;
if (debug_in.valid) begin
nxt_state = STATE_REQ_HDR_SRC;
end
end
STATE_REQ_HDR_SRC: begin
debug_in_ready = 1;
nxt_resp_dest = debug_in.data[15:0];
nxt_resp_error = 0;
nxt_state = STATE_REQ_HDR_FLAGS;
end
STATE_REQ_HDR_FLAGS: begin
debug_in_ready = 1;
nxt_req_write = debug_in.data[12];
nxt_req_size = debug_in.data[11:10];
if (debug_in.valid) begin
if (|debug_in.data[15:14]) begin
nxt_state = STATE_DROP;
end else begin
nxt_state = STATE_ADDR;
end
end
end
STATE_ADDR: begin
debug_in_ready = 1;
if (reg_addr_is_ext) begin
nxt_req_addr = debug_in.data;
if (debug_in.valid) begin
if (req_write)
nxt_state = STATE_WRITE;
else
nxt_state = STATE_EXT_START;
end
end else begin
if (req_write) begin
// LOCAL WRITE
if (req_size != ACCESS_SIZE_16) begin
// XXX: only 16 bit writes are supported right now
nxt_resp_error = 1;
end else begin
nxt_req_addr = debug_in.data;
case (debug_in.data)
REG_MOD_EVENT_DEST: nxt_resp_error = 0;
REG_MOD_CS: nxt_resp_error = 0;
default: nxt_resp_error = 1;
endcase // case (debug_in.data)
end
end else begin // if (nxt_req_write)
// LOCAL READ
case (debug_in.data)
REG_MOD_VENDOR: nxt_reqresp_value = 16'(MOD_VENDOR);
REG_MOD_TYPE: nxt_reqresp_value = 16'(MOD_TYPE);
REG_MOD_VERSION: nxt_reqresp_value = 16'(MOD_VERSION);
REG_MOD_CS: nxt_reqresp_value = {15'h0, ~stall};
REG_MOD_EVENT_DEST: nxt_reqresp_value = mod_event_dest;
default: nxt_resp_error = 1;
endcase // case (debug_in.data)
end
if (debug_in.valid) begin
if (req_write) begin
if (debug_in.last) begin
nxt_resp_error = 1;
nxt_state = STATE_RESP_HDR_DEST;
end else if (nxt_resp_error) begin
nxt_state = STATE_RESP_HDR_DEST;
end else begin
nxt_state = STATE_WRITE;
end
end else begin
if (debug_in.last) begin
nxt_state = STATE_RESP_HDR_DEST;
end else begin
nxt_state = STATE_DROP;
end
end
end
end
end // case: STATE_ADDR
STATE_WRITE: begin
debug_in_ready = 1;
if (debug_in.valid) begin
nxt_reqresp_value = debug_in.data;
if (req_addr[15:9] != 0) begin
if (debug_in.last)
nxt_state = STATE_EXT_START;
else
nxt_state = STATE_DROP;
end else begin
case (req_addr)
REG_MOD_CS: begin
nxt_mod_cs_active = debug_in.data[REG_MOD_CS_ACTIVE];
nxt_resp_error = 0;
end
REG_MOD_EVENT_DEST: begin
nxt_mod_event_dest = debug_in.data;
nxt_resp_error = 0;
end
endcase // case (req_addr)
if (debug_in.last) begin
nxt_state = STATE_RESP_HDR_DEST;
end else begin
nxt_state = STATE_DROP;
end
end
end
end
STATE_RESP_HDR_DEST: begin
debug_out.valid = 1;
debug_out.data = resp_dest;
if (debug_out_ready) begin
nxt_state = STATE_RESP_HDR_SRC;
end
end
STATE_RESP_HDR_SRC: begin
debug_out.valid = 1;
debug_out.data = id;
if (debug_out_ready) begin
nxt_state = STATE_RESP_HDR_FLAGS;
end
end
STATE_RESP_HDR_FLAGS: begin
debug_out.valid = 1;
debug_out.data[9:0] = 10'h0; // reserved
debug_out.data[15:14] = 2'b00; // TYPE == REG
// TYPE_SUB
if (req_write) begin
if (resp_error) begin
debug_out.data[13:10] = 4'b1111; // RESP_WRITE_REG_ERROR
end else begin
debug_out.data[13:10] = 4'b1110; // RESP_WRITE_REG_SUCCESS
end
end else begin
if (resp_error) begin
debug_out.data[13:10] = 4'b1100; // RESP_READ_REG_ERROR
end else begin
debug_out.data[13:10] = {2'b10, req_size}; // RESP_READ_REG_SUCCESS_*
end
end
debug_out.last = resp_error | req_write;
if (debug_out_ready) begin
if (req_write) begin
nxt_state = STATE_IDLE;
end else begin
nxt_state = STATE_RESP_VALUE;
end
end
end
STATE_RESP_VALUE: begin
debug_out.valid = 1;
debug_out.data = reqresp_value[15:0];
debug_out.last = 1;
if (debug_out_ready) begin
nxt_state = STATE_IDLE;
end
end
STATE_EXT_START: begin
reg_request = 1;
if (reg_ack | reg_err) begin
nxt_reqresp_value = reg_rdata;
nxt_resp_error = reg_err;
nxt_state = STATE_RESP_HDR_DEST;
end
end
STATE_DROP: begin
debug_in_ready = 1;
if (debug_in.valid & debug_in.last) begin
nxt_state = STATE_IDLE;
end
end
endcase // case (state)
end
endmodule
|
// Copyright 2016-2017 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Philipp Wagner <philipp.wagner@tum.de>
import dii_package::dii_flit;
/**
* Debug Interconnect Register Access Demultiplexer
*
* This module splits an incoming DI link depending on the packet type.
* Register access packets (FLAGS.TYPE = REG) are forwarded to the out_reg
* output ports, all other packets are forwarded to the out_bypass ports.
*
* The latency between the in and the out port is 3 cycles.
*/
module osd_regaccess_demux
(input clk, input rst,
input dii_flit in, output logic in_ready,
output dii_flit out_reg, input out_reg_ready,
output dii_flit out_bypass, input out_bypass_ready);
typedef struct packed {
logic [15:0] data;
logic last;
logic valid;
} bufdata;
bufdata buf_reg[3];
logic [2:0] buf_reg_is_regaccess;
logic [2:0] buf_reg_is_bypass;
logic do_tag, mark_bypass, mark_regaccess;
assign do_tag = buf_reg[2].valid & buf_reg[1].valid & buf_reg[0].valid &
(!buf_reg_is_regaccess[2] & !buf_reg_is_bypass[2]) &
(!buf_reg_is_regaccess[1] & !buf_reg_is_bypass[1]) &
(!buf_reg_is_regaccess[0] & !buf_reg_is_bypass[0]);
assign mark_bypass = do_tag & (buf_reg[0].data[15:14] != 2'b00);
assign mark_regaccess = do_tag & (buf_reg[0].data[15:14] == 2'b00);
logic pkg_is_bypass, pkg_is_regaccess;
always_ff @(posedge clk) begin
if (rst) begin
pkg_is_bypass <= 0;
pkg_is_regaccess <= 0;
end else begin
pkg_is_bypass <= (pkg_is_bypass | mark_bypass)
& !(in.last & in.valid & in_ready)
& !(buf_reg[0].last & buf_reg[0].valid);
pkg_is_regaccess <= (pkg_is_regaccess | mark_regaccess)
& !(in.last & in.valid & in_ready)
& !(buf_reg[0].last & buf_reg[0].valid);
end
end
logic keep_1, keep_2;
assign keep_1 = !do_tag & buf_reg[1].valid
& !(buf_reg_is_bypass[1] | buf_reg_is_regaccess[1]) & keep_2;
assign keep_2 = !do_tag & buf_reg[2].valid
& !(buf_reg_is_bypass[2] | buf_reg_is_regaccess[2]);
always_ff @(posedge clk) begin
if (rst) begin
buf_reg[0].valid <= 0;
buf_reg_is_regaccess[0] <= 0;
buf_reg_is_bypass[0] <= 0;
buf_reg[1].valid <= 0;
buf_reg_is_regaccess[1] <= 0;
buf_reg_is_bypass[1] <= 0;
buf_reg[2].valid <= 0;
buf_reg_is_regaccess[2] <= 0;
buf_reg_is_bypass[2] <= 0;
end else begin
if (in_ready) begin
buf_reg[0].data <= in.data;
buf_reg[0].last <= in.last;
buf_reg[0].valid <= in.valid & in_ready;
if (buf_reg[0].valid & !buf_reg[0].last) begin
buf_reg_is_regaccess[0] <= pkg_is_regaccess | mark_regaccess;
buf_reg_is_bypass[0] <= pkg_is_bypass | mark_bypass;
end else begin
buf_reg_is_regaccess[0] <= pkg_is_regaccess;
buf_reg_is_bypass[0] <= pkg_is_bypass;
end
if (!keep_1) begin
buf_reg[1] <= buf_reg[0];
buf_reg_is_regaccess[1] <= buf_reg_is_regaccess[0] | mark_regaccess;
buf_reg_is_bypass[1] <= buf_reg_is_bypass[0] | mark_bypass;
end else begin
buf_reg_is_regaccess[1] <= buf_reg_is_regaccess[1] | mark_regaccess;
buf_reg_is_bypass[1] <= buf_reg_is_bypass[1] | mark_bypass;
end
if (!keep_2) begin
buf_reg[2] <= buf_reg[1];
buf_reg_is_regaccess[2] <= buf_reg_is_regaccess[1] | mark_regaccess;
buf_reg_is_bypass[2] <= buf_reg_is_bypass[1] | mark_bypass;
end else begin
buf_reg_is_regaccess[2] <= buf_reg_is_regaccess[2] | mark_regaccess;
buf_reg_is_bypass[2] <= buf_reg_is_bypass[2] | mark_bypass;
end
end
end
end
// Output data
assign out_reg.data = buf_reg[2].data;
assign out_reg.last = buf_reg[2].last;
assign out_reg.valid = buf_reg[2].valid
& (buf_reg_is_regaccess[2] | mark_regaccess);
assign out_bypass.data = buf_reg[2].data;
assign out_bypass.last = buf_reg[2].last;
assign out_bypass.valid = buf_reg[2].valid
& (buf_reg_is_bypass[2] | mark_bypass);
logic no_buf_entry_is_tagged;
assign no_buf_entry_is_tagged = ~do_tag & ~(|buf_reg_is_regaccess | |buf_reg_is_bypass);
assign in_ready = (out_bypass_ready & out_reg_ready) |
(out_bypass_ready & (buf_reg_is_bypass[2] | mark_bypass)) |
(out_reg_ready & (buf_reg_is_regaccess[2] | mark_regaccess)) |
no_buf_entry_is_tagged;
endmodule // osd_regaccess_demux
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Stefan Wallentowitz <stefan@wallentowitz.de>
import dii_package::dii_flit;
/**
* Register access layer
*
* This module handles all debug register accesses in a debug link and leaves
* all other packet types to be handled by user logic.
*/
module osd_regaccess_layer
#(parameter MOD_VENDOR = 'x,
parameter MOD_TYPE = 'x,
parameter MOD_VERSION = 'x,
parameter MOD_EVENT_DEST_DEFAULT = 0,
parameter CAN_STALL = 0,
parameter MAX_REG_SIZE = 16)
(input clk, rst,
input [15:0] id,
input dii_flit debug_in, output logic debug_in_ready,
output dii_flit debug_out, input debug_out_ready,
output dii_flit module_out, input module_out_ready,
input dii_flit module_in, output module_in_ready,
output reg reg_request,
output reg_write,
output [15:0] reg_addr,
output [1:0] reg_size,
output [15:0] reg_wdata,
input reg_ack,
input reg_err,
input [15:0] reg_rdata,
output [15:0] event_dest, // DI address of the event destination
output stall);
dii_flit regaccess_in, regaccess_out;
logic regaccess_in_ready, regaccess_out_ready;
osd_regaccess
#(.MOD_VENDOR(MOD_VENDOR),
.MOD_TYPE(MOD_TYPE),
.MOD_EVENT_DEST_DEFAULT(MOD_EVENT_DEST_DEFAULT),
.MOD_VERSION(MOD_VERSION),
.CAN_STALL(CAN_STALL),
.MAX_REG_SIZE(MAX_REG_SIZE))
u_regaccess
(.*,
.event_dest (event_dest),
.debug_in (regaccess_in),
.debug_in_ready (regaccess_in_ready),
.debug_out (regaccess_out),
.debug_out_ready (regaccess_out_ready));
// Ingress path demux
osd_regaccess_demux
u_demux(.*,
.in (debug_in),
.in_ready (debug_in_ready),
.out_reg (regaccess_in),
.out_reg_ready (regaccess_in_ready),
.out_bypass (module_out),
.out_bypass_ready (module_out_ready));
// Egress path mux
ring_router_mux
u_mux(.*,
.in_local (module_in),
.in_local_ready (module_in_ready),
.in_ring (regaccess_out),
.in_ring_ready (regaccess_out_ready),
.out_mux (debug_out),
.out_mux_ready (debug_out_ready));
endmodule
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Stefan Wallentowitz <stefan@wallentowitz.de>
import dii_package::dii_flit;
module ring_router
#(parameter BUFFER_SIZE=4)
(
input clk, rst,
input [15:0] id,
input dii_flit ring_in0, output ring_in0_ready,
input dii_flit ring_in1, output ring_in1_ready,
output dii_flit ring_out0, input ring_out0_ready,
output dii_flit ring_out1, input ring_out1_ready,
input dii_flit local_in, output local_in_ready,
output dii_flit local_out, input local_out_ready
);
dii_flit ring_fwd0; logic ring_fwd0_ready;
dii_flit ring_fwd1; logic ring_fwd1_ready;
dii_flit ring_local0; logic ring_local0_ready;
dii_flit ring_local1; logic ring_local1_ready;
dii_flit ring_muxed; logic ring_muxed_ready;
ring_router_demux
u_demux0(.*,
.in_ring ( ring_in0 ),
.in_ring_ready ( ring_in0_ready ),
.out_local ( ring_local0 ),
.out_local_ready ( ring_local0_ready ),
.out_ring ( ring_fwd0 ),
.out_ring_ready ( ring_fwd0_ready )
);
ring_router_demux
u_demux1(.*,
.in_ring ( ring_in1 ),
.in_ring_ready ( ring_in1_ready ),
.out_local ( ring_local1 ),
.out_local_ready ( ring_local1_ready ),
.out_ring ( ring_fwd1 ),
.out_ring_ready ( ring_fwd1_ready )
);
ring_router_mux_rr
u_mux_local(.*,
.in0 ( ring_local0 ),
.in0_ready ( ring_local0_ready ),
.in1 ( ring_local1 ),
.in1_ready ( ring_local1_ready ),
.out_mux ( local_out ),
.out_mux_ready ( local_out_ready )
);
ring_router_mux
u_mux_ring0(.*,
.in_ring ( ring_fwd0 ),
.in_ring_ready ( ring_fwd0_ready ),
.in_local ( local_in ),
.in_local_ready ( local_in_ready ),
.out_mux ( ring_muxed ),
.out_mux_ready ( ring_muxed_ready )
);
dii_buffer
#(.BUF_SIZE(BUFFER_SIZE))
u_buffer0(.*,
.packet_size ( ),
.flit_in ( ring_muxed ),
.flit_in_ready ( ring_muxed_ready ),
.flit_out ( ring_out0 ),
.flit_out_ready ( ring_out0_ready )
);
dii_buffer
#(.BUF_SIZE(BUFFER_SIZE))
u_buffer1(.*,
.packet_size ( ),
.flit_in ( ring_fwd1 ),
.flit_in_ready ( ring_fwd1_ready ),
.flit_out ( ring_out1 ),
.flit_out_ready ( ring_out1_ready )
);
endmodule
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Stefan Wallentowitz <stefan@wallentowitz.de>
import dii_package::dii_flit;
module ring_router_demux
(
input clk, rst,
input [15:0] id,
input dii_flit in_ring, output in_ring_ready,
output dii_flit out_local, input out_local_ready,
output dii_flit out_ring, input out_ring_ready
);
assign out_local.data = in_ring.data;
assign out_local.last = in_ring.last;
assign out_ring.data = in_ring.data;
assign out_ring.last = in_ring.last;
reg worm;
reg worm_local;
logic is_local;
assign is_local = (in_ring.data[15:0] == id);
always_ff @(posedge clk) begin
if (rst) begin
worm <= 0;
worm_local <= 1'bx;
end else begin
if (!worm) begin
worm_local <= is_local;
if (in_ring_ready & in_ring.valid & !in_ring.last) begin
worm <= 1;
end
end else begin
if (in_ring_ready & in_ring.valid & in_ring.last) begin
worm <= 0;
end
end
end
end
logic switch_local;
assign switch_local = worm ? worm_local : is_local;
assign out_ring.valid = !switch_local & in_ring.valid;
assign out_local.valid = switch_local & in_ring.valid;
assign in_ring_ready = switch_local ? out_local_ready : out_ring_ready;
endmodule // ring_router_demux
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Philipp Wagner <philipp.wagner@tum.de>
// Stefan Wallentowitz <stefan@wallentowitz.de>
import dii_package::dii_flit;
/**
* Ring NoC Router with gateway functionality
*
* This module has similar functionality as the ring_router module, but adds
* an additional port "ext". On this port all traffic to subnets outside of the
* LOCAL_SUBNET are forwarded.
*/
module ring_router_gateway
#(
parameter BUFFER_SIZE = 4,
parameter SUBNET_BITS = 6,
parameter LOCAL_SUBNET = 0
)(
input clk, rst,
input [15:0] id,
input dii_flit ring_in0, output ring_in0_ready,
input dii_flit ring_in1, output ring_in1_ready,
output dii_flit ring_out0, input ring_out0_ready,
output dii_flit ring_out1, input ring_out1_ready,
input dii_flit local_in, output local_in_ready,
output dii_flit local_out, input local_out_ready,
input dii_flit ext_in, output ext_in_ready,
output dii_flit ext_out, input ext_out_ready
);
dii_flit ring_fwd0; logic ring_fwd0_ready;
dii_flit ring_fwd1; logic ring_fwd1_ready;
dii_flit ring_local0; logic ring_local0_ready;
dii_flit ring_local1; logic ring_local1_ready;
dii_flit ring_ext0; logic ring_ext0_ready;
dii_flit ring_ext1; logic ring_ext1_ready;
dii_flit ring_muxed; logic ring_muxed_ready;
ring_router_gateway_demux
u_demux0(.*,
.in_ring ( ring_in0 ),
.in_ring_ready ( ring_in0_ready ),
.out_local ( ring_local0 ),
.out_local_ready ( ring_local0_ready ),
.out_ring ( ring_fwd0 ),
.out_ring_ready ( ring_fwd0_ready ),
.out_ext ( ring_ext0 ),
.out_ext_ready ( ring_ext0_ready )
);
ring_router_gateway_demux
u_demux1(.*,
.in_ring ( ring_in1 ),
.in_ring_ready ( ring_in1_ready ),
.out_local ( ring_local1 ),
.out_local_ready ( ring_local1_ready ),
.out_ring ( ring_fwd1 ),
.out_ring_ready ( ring_fwd1_ready ),
.out_ext ( ring_ext1 ),
.out_ext_ready ( ring_ext1_ready )
);
ring_router_mux_rr
u_mux_local(.*,
.in0 ( ring_local0 ),
.in0_ready ( ring_local0_ready ),
.in1 ( ring_local1 ),
.in1_ready ( ring_local1_ready ),
.out_mux ( local_out ),
.out_mux_ready ( local_out_ready )
);
ring_router_mux_rr
u_mux_ext(.*,
.in0 ( ring_ext0 ),
.in0_ready ( ring_ext0_ready ),
.in1 ( ring_ext1 ),
.in1_ready ( ring_ext1_ready ),
.out_mux ( ext_out ),
.out_mux_ready ( ext_out_ready )
);
ring_router_gateway_mux
u_mux_ring0(.*,
.in_ring ( ring_fwd0 ),
.in_ring_ready ( ring_fwd0_ready ),
.in_local ( local_in ),
.in_local_ready ( local_in_ready ),
.in_ext ( ext_in ),
.in_ext_ready ( ext_in_ready ),
.out_mux ( ring_muxed ),
.out_mux_ready ( ring_muxed_ready )
);
dii_buffer
#(.BUF_SIZE(BUFFER_SIZE))
u_buffer0(.*,
.packet_size ( ),
.flit_in ( ring_muxed ),
.flit_in_ready ( ring_muxed_ready ),
.flit_out ( ring_out0 ),
.flit_out_ready ( ring_out0_ready )
);
dii_buffer
#(.BUF_SIZE(BUFFER_SIZE))
u_buffer1(.*,
.packet_size ( ),
.flit_in ( ring_fwd1 ),
.flit_in_ready ( ring_fwd1_ready ),
.flit_out ( ring_out1 ),
.flit_out_ready ( ring_out1_ready )
);
endmodule
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Philipp Wagner <philipp.wagner@tum.de>
// Stefan Wallentowitz <stefan@wallentowitz.de>
import dii_package::dii_flit;
module ring_router_gateway_demux
#(
parameter SUBNET_BITS = 6,
parameter LOCAL_SUBNET = 0
)(
input clk, rst,
input [15:0] id,
input dii_flit in_ring, output reg in_ring_ready,
output dii_flit out_local, input out_local_ready,
output dii_flit out_ext, input out_ext_ready,
output dii_flit out_ring, input out_ring_ready
);
assign out_local.data = in_ring.data;
assign out_local.last = in_ring.last;
assign out_ext.data = in_ring.data;
assign out_ext.last = in_ring.last;
assign out_ring.data = in_ring.data;
assign out_ring.last = in_ring.last;
reg worm;
reg worm_local;
reg worm_ext;
logic is_local;
logic is_ext;
assign is_local = (in_ring.data[15:0] == id);
assign is_ext = (in_ring.data[15:16-SUBNET_BITS] != LOCAL_SUBNET);
always_ff @(posedge clk) begin
if (rst) begin
worm <= 0;
worm_local <= 1'bx;
worm_ext <= 1'bx;
end else begin
if (!worm) begin
worm_local <= is_local;
worm_ext <= is_ext;
if (in_ring_ready & in_ring.valid & !in_ring.last) begin
worm <= 1;
end
end else begin
if (in_ring_ready & in_ring.valid & in_ring.last) begin
worm <= 0;
end
end
end
end
logic switch_local;
logic switch_ext;
assign switch_local = worm ? worm_local : is_local;
assign switch_ext = worm ? worm_ext : is_ext;
always_comb begin
out_local.valid = 1'b0;
out_ext.valid = 1'b0;
out_ring.valid = 1'b0;
in_ring_ready = 1'b0;
if (switch_local) begin
out_local.valid = in_ring.valid;
in_ring_ready = out_local_ready;
end else if (switch_ext) begin
out_ext.valid = in_ring.valid;
in_ring_ready = out_ext_ready;
end else begin
out_ring.valid = in_ring.valid;
in_ring_ready = out_ring_ready;
end
end
endmodule // ring_router_demux
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Philipp Wagner <philipp.wagner@tum.de>
// Stefan Wallentowitz <stefan@wallentowitz.de>
import dii_package::dii_flit;
module ring_router_gateway_mux
(
input clk, rst,
input dii_flit in_ring, output logic in_ring_ready,
input dii_flit in_local, output logic in_local_ready,
input dii_flit in_ext, output logic in_ext_ready,
output dii_flit out_mux, input out_mux_ready
);
enum { NOWORM, WORM_LOCAL, WORM_EXT, WORM_RING } state, nxt_state;
always_ff @(posedge clk) begin
if (rst) begin
state <= NOWORM;
end else begin
state <= nxt_state;
end
end
always_comb begin
nxt_state = state;
out_mux.valid = 0;
out_mux.data = 'x;
out_mux.last = 'x;
in_ring_ready = 0;
in_local_ready = 0;
in_ext_ready = 0;
case (state)
NOWORM: begin
if (in_ring.valid) begin
in_ring_ready = out_mux_ready;
out_mux = in_ring;
out_mux.valid = 1'b1;
if (!in_ring.last) begin
nxt_state = WORM_RING;
end
end else if (in_local.valid) begin
in_local_ready = out_mux_ready;
out_mux = in_local;
out_mux.valid = 1'b1;
if (!in_local.last) begin
nxt_state = WORM_LOCAL;
end
end else if (in_ext.valid) begin
in_ext_ready = out_mux_ready;
out_mux = in_ext;
out_mux.valid = 1'b1;
if (!in_ext.last) begin
nxt_state = WORM_EXT;
end
end
end // case: NOWORM
WORM_RING: begin
in_ring_ready = out_mux_ready;
out_mux.valid = in_ring.valid;
out_mux.last = in_ring.last;
out_mux.data = in_ring.data;
if (out_mux.last & out_mux.valid & out_mux_ready) begin
nxt_state = NOWORM;
end
end
WORM_LOCAL: begin
in_local_ready = out_mux_ready;
out_mux.valid = in_local.valid;
out_mux.last = in_local.last;
out_mux.data = in_local.data;
if (out_mux.last & out_mux.valid & out_mux_ready) begin
nxt_state = NOWORM;
end
end
WORM_EXT: begin
in_ext_ready = out_mux_ready;
out_mux.valid = in_ext.valid;
out_mux.last = in_ext.last;
out_mux.data = in_ext.data;
if (out_mux.last & out_mux.valid & out_mux_ready) begin
nxt_state = NOWORM;
end
end
endcase // case (state)
end
endmodule
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Stefan Wallentowitz <stefan@wallentowitz.de>
import dii_package::dii_flit;
module ring_router_mux
(
input clk, rst,
input dii_flit in_ring, output logic in_ring_ready,
input dii_flit in_local, output logic in_local_ready,
output dii_flit out_mux, input out_mux_ready
);
enum { NOWORM, WORM_LOCAL, WORM_RING } state, nxt_state;
always_ff @(posedge clk) begin
if (rst) begin
state <= NOWORM;
end else begin
state <= nxt_state;
end
end
always_comb begin
nxt_state = state;
out_mux.valid = 0;
out_mux.data = 'x;
out_mux.last = 'x;
in_ring_ready = 0;
in_local_ready = 0;
case (state)
NOWORM: begin
if (in_ring.valid) begin
in_ring_ready = out_mux_ready;
out_mux = in_ring;
out_mux.valid = 1'b1;
if (!in_ring.last) begin
nxt_state = WORM_RING;
end
end else if (in_local.valid) begin
in_local_ready = out_mux_ready;
out_mux = in_local;
out_mux.valid = 1'b1;
if (!in_local.last) begin
nxt_state = WORM_LOCAL;
end
end // if (in_local.valid)
end // case: NOWORM
WORM_RING: begin
in_ring_ready = out_mux_ready;
out_mux.valid = in_ring.valid;
out_mux.last = in_ring.last;
out_mux.data = in_ring.data;
if (out_mux.last & out_mux.valid & out_mux_ready) begin
nxt_state = NOWORM;
end
end
WORM_LOCAL: begin
in_local_ready = out_mux_ready;
out_mux.valid = in_local.valid;
out_mux.last = in_local.last;
out_mux.data = in_local.data;
if (out_mux.last & out_mux.valid & out_mux_ready) begin
nxt_state = NOWORM;
end
end
endcase // case (state)
end
endmodule // ring_router_mux
|
// Copyright 2016 by the authors
//
// Copyright and related rights are licensed under the Solderpad
// Hardware License, Version 0.51 (the "License"); you may not use
// this file except in compliance with the License. You may obtain a
// copy of the License at http://solderpad.org/licenses/SHL-0.51.
// Unless required by applicable law or agreed to in writing,
// software, hardware and materials distributed under this License is
// distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the
// License.
//
// Authors:
// Stefan Wallentowitz <stefan@wallentowitz.de>
import dii_package::dii_flit;
module ring_router_mux_rr
(
input clk, rst,
input dii_flit in0, output logic in0_ready,
input dii_flit in1, output logic in1_ready,
output dii_flit out_mux, input out_mux_ready
);
enum { NOWORM0, NOWORM1, WORM0, WORM1 } state, nxt_state;
always_ff @(posedge clk) begin
if (rst) begin
state <= NOWORM0;
end else begin
state <= nxt_state;
end
end
always_comb begin
nxt_state = state;
out_mux.valid = 0;
out_mux.data = 'x;
out_mux.last = 'x;
in0_ready = 0;
in1_ready = 0;
case (state)
NOWORM0: begin
if (in0.valid) begin
in0_ready = out_mux_ready;
out_mux = in0;
out_mux.valid = 1;
if (!in0.last) begin
nxt_state = WORM0;
end
end else if (in1.valid) begin
in1_ready = out_mux_ready;
out_mux = in1;
out_mux.valid = 1;
if (!in1.last) begin
nxt_state = WORM1;
end
end
end
NOWORM1: begin
if (in1.valid) begin
in1_ready = out_mux_ready;
out_mux = in1;
out_mux.valid = 1;
if (!in1.last) begin
nxt_state = WORM1;
end
end else if (in0.valid) begin
in0_ready = out_mux_ready;
out_mux = in0;
out_mux.valid = 1;
if (!in0.last) begin
nxt_state = WORM0;
end
end
end
WORM0: begin
in0_ready = out_mux_ready;
out_mux = in0;
if (out_mux.last & out_mux.valid & out_mux_ready) begin
nxt_state = NOWORM1;
end
end
WORM1: begin
in1_ready = out_mux_ready;
out_mux = in1;
if (out_mux.last & out_mux.valid & out_mux_ready) begin
nxt_state = NOWORM0;
end
end
endcase // case (state)
end
endmodule // ring_router_mux
|
/*
* This source file contains a Verilog description of an IP core
* automatically generated by the SPIRAL HDL Generator.
*
* This product includes a hardware design developed by Carnegie Mellon University.
*
* Copyright (c) 2005-2011 by Peter A. Milder for the SPIRAL Project,
* Carnegie Mellon University
*
* For more information, see the SPIRAL project website at:
* http://www.spiral.net
*
* This design is provided for internal, non-commercial research use only
* and is not for redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
// Input/output stream: 2 complex words per cycle
// Throughput: one transform every 32 cycles
// Latency: 332 cycles
// Resources required:
// 20 multipliers (16 x 16 bit)
// 34 adders (16 x 16 bit)
// 4 RAMs (16 words, 32 bits per word)
// 4 RAMs (8 words, 32 bits per word)
// 12 RAMs (64 words, 32 bits per word)
// 4 RAMs (32 words, 32 bits per word)
// 2 ROMs (32 words, 16 bits per word)
// 2 ROMs (8 words, 16 bits per word)
// 12 ROMs (32 words, 5 bits per word)
// 2 ROMs (16 words, 16 bits per word)
// Generated on Tue Sep 04 00:43:02 EDT 2018
// Latency: 332 clock cycles
// Throughput: 1 transform every 32 cycles
// We use an interleaved complex data format. X0 represents the
// real portion of the first input, and X1 represents the imaginary
// portion. The X variables are system inputs and the Y variables
// are system outputs.
// The design uses a system of flag signals to indicate the
// beginning of the input and output data streams. The 'next'
// input (asserted high), is used to instruct the system that the
// input stream will begin on the following cycle.
// This system has a 'gap' of 32 cycles. This means that
// 32 cycles must elapse between the beginning of the input
// vectors.
// The output signal 'next_out' (also asserted high) indicates
// that the output vector will begin streaming out of the system
// on the following cycle.
// The system has a latency of 332 cycles. This means that
// the 'next_out' will be asserted 332 cycles after the user
// asserts 'next'.
// The simple testbench below will demonstrate the timing for loading
// and unloading data vectors.
// The system reset signal is asserted high.
// Please note: when simulating floating point code, you must include
// Xilinx's DSP slice simulation module.
// Latency: 332
// Gap: 32
// module_name_is:dft_top
module dft_top(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [15:0] t0_0;
wire [15:0] t0_1;
wire [15:0] t0_2;
wire [15:0] t0_3;
wire next_0;
wire [15:0] t1_0;
wire [15:0] t1_1;
wire [15:0] t1_2;
wire [15:0] t1_3;
wire next_1;
wire [15:0] t2_0;
wire [15:0] t2_1;
wire [15:0] t2_2;
wire [15:0] t2_3;
wire next_2;
wire [15:0] t3_0;
wire [15:0] t3_1;
wire [15:0] t3_2;
wire [15:0] t3_3;
wire next_3;
wire [15:0] t4_0;
wire [15:0] t4_1;
wire [15:0] t4_2;
wire [15:0] t4_3;
wire next_4;
wire [15:0] t5_0;
wire [15:0] t5_1;
wire [15:0] t5_2;
wire [15:0] t5_3;
wire next_5;
wire [15:0] t6_0;
wire [15:0] t6_1;
wire [15:0] t6_2;
wire [15:0] t6_3;
wire next_6;
wire [15:0] t7_0;
wire [15:0] t7_1;
wire [15:0] t7_2;
wire [15:0] t7_3;
wire next_7;
wire [15:0] t8_0;
wire [15:0] t8_1;
wire [15:0] t8_2;
wire [15:0] t8_3;
wire next_8;
wire [15:0] t9_0;
wire [15:0] t9_1;
wire [15:0] t9_2;
wire [15:0] t9_3;
wire next_9;
wire [15:0] t10_0;
wire [15:0] t10_1;
wire [15:0] t10_2;
wire [15:0] t10_3;
wire next_10;
wire [15:0] t11_0;
wire [15:0] t11_1;
wire [15:0] t11_2;
wire [15:0] t11_3;
wire next_11;
wire [15:0] t12_0;
wire [15:0] t12_1;
wire [15:0] t12_2;
wire [15:0] t12_3;
wire next_12;
wire [15:0] t13_0;
wire [15:0] t13_1;
wire [15:0] t13_2;
wire [15:0] t13_3;
wire next_13;
wire [15:0] t14_0;
wire [15:0] t14_1;
wire [15:0] t14_2;
wire [15:0] t14_3;
wire next_14;
wire [15:0] t15_0;
wire [15:0] t15_1;
wire [15:0] t15_2;
wire [15:0] t15_3;
wire next_15;
wire [15:0] t16_0;
wire [15:0] t16_1;
wire [15:0] t16_2;
wire [15:0] t16_3;
wire next_16;
wire [15:0] t17_0;
wire [15:0] t17_1;
wire [15:0] t17_2;
wire [15:0] t17_3;
wire next_17;
wire [15:0] t18_0;
wire [15:0] t18_1;
wire [15:0] t18_2;
wire [15:0] t18_3;
wire next_18;
assign t0_0 = X0;
assign Y0 = t18_0;
assign t0_1 = X1;
assign Y1 = t18_1;
assign t0_2 = X2;
assign Y2 = t18_2;
assign t0_3 = X3;
assign Y3 = t18_3;
assign next_0 = next;
assign next_out = next_18;
// latency=68, gap=32
rc82445 stage0(.clk(clk), .reset(reset), .next(next_0), .next_out(next_1),
.X0(t0_0), .Y0(t1_0),
.X1(t0_1), .Y1(t1_1),
.X2(t0_2), .Y2(t1_2),
.X3(t0_3), .Y3(t1_3));
// latency=2, gap=32
codeBlock82447 stage1(.clk(clk), .reset(reset), .next_in(next_1), .next_out(next_2),
.X0_in(t1_0), .Y0(t2_0),
.X1_in(t1_1), .Y1(t2_1),
.X2_in(t1_2), .Y2(t2_2),
.X3_in(t1_3), .Y3(t2_3));
// latency=8, gap=32
rc82529 stage2(.clk(clk), .reset(reset), .next(next_2), .next_out(next_3),
.X0(t2_0), .Y0(t3_0),
.X1(t2_1), .Y1(t3_1),
.X2(t2_2), .Y2(t3_2),
.X3(t2_3), .Y3(t3_3));
// latency=8, gap=32
DirSum_82710 stage3(.next(next_3), .clk(clk), .reset(reset), .next_out(next_4),
.X0(t3_0), .Y0(t4_0),
.X1(t3_1), .Y1(t4_1),
.X2(t3_2), .Y2(t4_2),
.X3(t3_3), .Y3(t4_3));
// latency=2, gap=32
codeBlock82713 stage4(.clk(clk), .reset(reset), .next_in(next_4), .next_out(next_5),
.X0_in(t4_0), .Y0(t5_0),
.X1_in(t4_1), .Y1(t5_1),
.X2_in(t4_2), .Y2(t5_2),
.X3_in(t4_3), .Y3(t5_3));
// latency=12, gap=32
rc82795 stage5(.clk(clk), .reset(reset), .next(next_5), .next_out(next_6),
.X0(t5_0), .Y0(t6_0),
.X1(t5_1), .Y1(t6_1),
.X2(t5_2), .Y2(t6_2),
.X3(t5_3), .Y3(t6_3));
// latency=8, gap=32
DirSum_82984 stage6(.next(next_6), .clk(clk), .reset(reset), .next_out(next_7),
.X0(t6_0), .Y0(t7_0),
.X1(t6_1), .Y1(t7_1),
.X2(t6_2), .Y2(t7_2),
.X3(t6_3), .Y3(t7_3));
// latency=2, gap=32
codeBlock82987 stage7(.clk(clk), .reset(reset), .next_in(next_7), .next_out(next_8),
.X0_in(t7_0), .Y0(t8_0),
.X1_in(t7_1), .Y1(t8_1),
.X2_in(t7_2), .Y2(t8_2),
.X3_in(t7_3), .Y3(t8_3));
// latency=20, gap=32
rc83069 stage8(.clk(clk), .reset(reset), .next(next_8), .next_out(next_9),
.X0(t8_0), .Y0(t9_0),
.X1(t8_1), .Y1(t9_1),
.X2(t8_2), .Y2(t9_2),
.X3(t8_3), .Y3(t9_3));
// latency=8, gap=32
DirSum_83274 stage9(.next(next_9), .clk(clk), .reset(reset), .next_out(next_10),
.X0(t9_0), .Y0(t10_0),
.X1(t9_1), .Y1(t10_1),
.X2(t9_2), .Y2(t10_2),
.X3(t9_3), .Y3(t10_3));
// latency=2, gap=32
codeBlock83277 stage10(.clk(clk), .reset(reset), .next_in(next_10), .next_out(next_11),
.X0_in(t10_0), .Y0(t11_0),
.X1_in(t10_1), .Y1(t11_1),
.X2_in(t10_2), .Y2(t11_2),
.X3_in(t10_3), .Y3(t11_3));
// latency=36, gap=32
rc83359 stage11(.clk(clk), .reset(reset), .next(next_11), .next_out(next_12),
.X0(t11_0), .Y0(t12_0),
.X1(t11_1), .Y1(t12_1),
.X2(t11_2), .Y2(t12_2),
.X3(t11_3), .Y3(t12_3));
// latency=8, gap=32
DirSum_83596 stage12(.next(next_12), .clk(clk), .reset(reset), .next_out(next_13),
.X0(t12_0), .Y0(t13_0),
.X1(t12_1), .Y1(t13_1),
.X2(t12_2), .Y2(t13_2),
.X3(t12_3), .Y3(t13_3));
// latency=2, gap=32
codeBlock83599 stage13(.clk(clk), .reset(reset), .next_in(next_13), .next_out(next_14),
.X0_in(t13_0), .Y0(t14_0),
.X1_in(t13_1), .Y1(t14_1),
.X2_in(t13_2), .Y2(t14_2),
.X3_in(t13_3), .Y3(t14_3));
// latency=68, gap=32
rc83681 stage14(.clk(clk), .reset(reset), .next(next_14), .next_out(next_15),
.X0(t14_0), .Y0(t15_0),
.X1(t14_1), .Y1(t15_1),
.X2(t14_2), .Y2(t15_2),
.X3(t14_3), .Y3(t15_3));
// latency=8, gap=32
DirSum_83981 stage15(.next(next_15), .clk(clk), .reset(reset), .next_out(next_16),
.X0(t15_0), .Y0(t16_0),
.X1(t15_1), .Y1(t16_1),
.X2(t15_2), .Y2(t16_2),
.X3(t15_3), .Y3(t16_3));
// latency=2, gap=32
codeBlock83984 stage16(.clk(clk), .reset(reset), .next_in(next_16), .next_out(next_17),
.X0_in(t16_0), .Y0(t17_0),
.X1_in(t16_1), .Y1(t17_1),
.X2_in(t16_2), .Y2(t17_2),
.X3_in(t16_3), .Y3(t17_3));
// latency=68, gap=32
rc84066 stage17(.clk(clk), .reset(reset), .next(next_17), .next_out(next_18),
.X0(t17_0), .Y0(t18_0),
.X1(t17_1), .Y1(t18_1),
.X2(t17_2), .Y2(t18_2),
.X3(t17_3), .Y3(t18_3));
endmodule
// Latency: 68
// Gap: 32
module rc82445(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm82443 instPerm85011(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet82443(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm82443(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter addrbits = 5;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm0;
assign tm0 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85016(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85017(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(31, 5) nextReg_85028(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85029(.X(next2), .Y(next3), .clk(clk));
nextReg #(32, 5) nextReg_85032(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85033(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(31, 1) shiftFIFO_85036(.X(tm0), .Y(tm0_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85039(.X(tm0_d), .Y(tm0_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 5) shiftFIFO_85044(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm0_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 16;
{1'd0, 5'd1}: s1rd0 <= 24;
{1'd0, 5'd2}: s1rd0 <= 20;
{1'd0, 5'd3}: s1rd0 <= 28;
{1'd0, 5'd4}: s1rd0 <= 18;
{1'd0, 5'd5}: s1rd0 <= 26;
{1'd0, 5'd6}: s1rd0 <= 22;
{1'd0, 5'd7}: s1rd0 <= 30;
{1'd0, 5'd8}: s1rd0 <= 17;
{1'd0, 5'd9}: s1rd0 <= 25;
{1'd0, 5'd10}: s1rd0 <= 21;
{1'd0, 5'd11}: s1rd0 <= 29;
{1'd0, 5'd12}: s1rd0 <= 19;
{1'd0, 5'd13}: s1rd0 <= 27;
{1'd0, 5'd14}: s1rd0 <= 23;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 8;
{1'd0, 5'd18}: s1rd0 <= 4;
{1'd0, 5'd19}: s1rd0 <= 12;
{1'd0, 5'd20}: s1rd0 <= 2;
{1'd0, 5'd21}: s1rd0 <= 10;
{1'd0, 5'd22}: s1rd0 <= 6;
{1'd0, 5'd23}: s1rd0 <= 14;
{1'd0, 5'd24}: s1rd0 <= 1;
{1'd0, 5'd25}: s1rd0 <= 9;
{1'd0, 5'd26}: s1rd0 <= 5;
{1'd0, 5'd27}: s1rd0 <= 13;
{1'd0, 5'd28}: s1rd0 <= 3;
{1'd0, 5'd29}: s1rd0 <= 11;
{1'd0, 5'd30}: s1rd0 <= 7;
{1'd0, 5'd31}: s1rd0 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm0_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 8;
{1'd0, 5'd2}: s1rd1 <= 4;
{1'd0, 5'd3}: s1rd1 <= 12;
{1'd0, 5'd4}: s1rd1 <= 2;
{1'd0, 5'd5}: s1rd1 <= 10;
{1'd0, 5'd6}: s1rd1 <= 6;
{1'd0, 5'd7}: s1rd1 <= 14;
{1'd0, 5'd8}: s1rd1 <= 1;
{1'd0, 5'd9}: s1rd1 <= 9;
{1'd0, 5'd10}: s1rd1 <= 5;
{1'd0, 5'd11}: s1rd1 <= 13;
{1'd0, 5'd12}: s1rd1 <= 3;
{1'd0, 5'd13}: s1rd1 <= 11;
{1'd0, 5'd14}: s1rd1 <= 7;
{1'd0, 5'd15}: s1rd1 <= 15;
{1'd0, 5'd16}: s1rd1 <= 16;
{1'd0, 5'd17}: s1rd1 <= 24;
{1'd0, 5'd18}: s1rd1 <= 20;
{1'd0, 5'd19}: s1rd1 <= 28;
{1'd0, 5'd20}: s1rd1 <= 18;
{1'd0, 5'd21}: s1rd1 <= 26;
{1'd0, 5'd22}: s1rd1 <= 22;
{1'd0, 5'd23}: s1rd1 <= 30;
{1'd0, 5'd24}: s1rd1 <= 17;
{1'd0, 5'd25}: s1rd1 <= 25;
{1'd0, 5'd26}: s1rd1 <= 21;
{1'd0, 5'd27}: s1rd1 <= 29;
{1'd0, 5'd28}: s1rd1 <= 19;
{1'd0, 5'd29}: s1rd1 <= 27;
{1'd0, 5'd30}: s1rd1 <= 23;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet82443 sw(tm0_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm0_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm0_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
module memMod(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is block
reg [width-1:0] mem[depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule
module memMod_dist(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is distributed
reg [width-1:0] mem[depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule
module shiftRegFIFO(X, Y, clk);
parameter depth=1, width=1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @ (posedge clk) begin
for(index=1;index<depth;index=index+1) begin
mem[index] <= mem[index-1];
end
mem[0]<=X;
end
endmodule
module nextReg(X, Y, reset, clk);
parameter depth=2, logDepth=1;
output Y;
input X;
input clk, reset;
reg [logDepth:0] count;
reg active;
assign Y = (count == depth) ? 1 : 0;
always @ (posedge clk) begin
if (reset == 1) begin
count <= 0;
active <= 0;
end
else if (X == 1) begin
active <= 1;
count <= 1;
end
else if (count == depth) begin
count <= 0;
active <= 0;
end
else if (active)
count <= count+1;
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock82447(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85051(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a309;
wire signed [15:0] a310;
wire signed [15:0] a311;
wire signed [15:0] a312;
wire signed [15:0] t141;
wire signed [15:0] t142;
wire signed [15:0] t143;
wire signed [15:0] t144;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a309 = X0;
assign a310 = X2;
assign a311 = X1;
assign a312 = X3;
assign Y0 = t141;
assign Y1 = t142;
assign Y2 = t143;
assign Y3 = t144;
addfxp #(16, 1) add82459(.a(a309), .b(a310), .clk(clk), .q(t141)); // 0
addfxp #(16, 1) add82474(.a(a311), .b(a312), .clk(clk), .q(t142)); // 0
subfxp #(16, 1) sub82489(.a(a309), .b(a310), .clk(clk), .q(t143)); // 0
subfxp #(16, 1) sub82504(.a(a311), .b(a312), .clk(clk), .q(t144)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 8
// Gap: 2
module rc82529(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm82527 instPerm85052(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet82527(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [0:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
1'd0: control <= 1'b1;
1'd1: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 8
// Gap: 2
module perm82527(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 2;
parameter addrbits = 1;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm1;
assign tm1 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85057(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85058(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
shiftRegFIFO #(1, 1) shiftFIFO_85067(.X(next), .Y(next2), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85068(.X(next2), .Y(next3), .clk(clk));
shiftRegFIFO #(2, 1) shiftFIFO_85069(.X(next3), .Y(next4), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85070(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85073(.X(tm1), .Y(tm1_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85076(.X(tm1_d), .Y(tm1_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 1) shiftFIFO_85081(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm1_d, s1rdloc})
{1'd0, 1'd0}: s1rd0 <= 1;
{1'd0, 1'd1}: s1rd0 <= 0;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm1_d, s1rdloc})
{1'd0, 1'd0}: s1rd1 <= 0;
{1'd0, 1'd1}: s1rd1 <= 1;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet82527 sw(tm1_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm1_dd, writeCycle})
{1'd0, 1'd0}: s2wr0 <= 1;
{1'd0, 1'd1}: s2wr0 <= 0;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm1_dd, writeCycle})
{1'd0, 1'd0}: s2wr1 <= 0;
{1'd0, 1'd1}: s2wr1 <= 1;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 2
module DirSum_82710(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [0:0] i5;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i5 <= 0;
end
else begin
if (next == 1)
i5 <= 0;
else if (i5 == 1)
i5 <= 0;
else
i5 <= i5 + 1;
end
end
codeBlock82532 codeBlockIsnt85082(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i5_in(i5),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D18_82700(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h0;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D20_82708(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hc000;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock82532(clk, reset, next_in, next_out,
i5_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [0:0] i5_in;
reg [0:0] i5;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_85085(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a293;
wire signed [15:0] a282;
wire signed [15:0] a296;
wire signed [15:0] a286;
wire signed [15:0] a297;
wire signed [15:0] a298;
reg signed [15:0] tm137;
reg signed [15:0] tm141;
reg signed [15:0] tm153;
reg signed [15:0] tm160;
reg signed [15:0] tm138;
reg signed [15:0] tm142;
reg signed [15:0] tm154;
reg signed [15:0] tm161;
wire signed [15:0] tm4;
wire signed [15:0] a287;
wire signed [15:0] tm5;
wire signed [15:0] a289;
reg signed [15:0] tm139;
reg signed [15:0] tm143;
reg signed [15:0] tm155;
reg signed [15:0] tm162;
reg signed [15:0] tm31;
reg signed [15:0] tm32;
reg signed [15:0] tm140;
reg signed [15:0] tm144;
reg signed [15:0] tm156;
reg signed [15:0] tm163;
reg signed [15:0] tm157;
reg signed [15:0] tm164;
wire signed [15:0] a288;
wire signed [15:0] a290;
wire signed [15:0] a291;
wire signed [15:0] a292;
reg signed [15:0] tm158;
reg signed [15:0] tm165;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm159;
reg signed [15:0] tm166;
assign a293 = X0;
assign a282 = a293;
assign a296 = X1;
assign a286 = a296;
assign a297 = X2;
assign a298 = X3;
assign a287 = tm4;
assign a289 = tm5;
assign Y0 = tm159;
assign Y1 = tm166;
D18_82700 instD18inst0_82700(.addr(i5[0:0]), .out(tm4), .clk(clk));
D20_82708 instD20inst0_82708(.addr(i5[0:0]), .out(tm5), .clk(clk));
multfix #(16, 2) m82631(.a(tm31), .b(tm140), .clk(clk), .q_sc(a288), .q_unsc(), .rst(reset));
multfix #(16, 2) m82653(.a(tm32), .b(tm144), .clk(clk), .q_sc(a290), .q_unsc(), .rst(reset));
multfix #(16, 2) m82671(.a(tm32), .b(tm140), .clk(clk), .q_sc(a291), .q_unsc(), .rst(reset));
multfix #(16, 2) m82682(.a(tm31), .b(tm144), .clk(clk), .q_sc(a292), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub82660(.a(a288), .b(a290), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add82689(.a(a291), .b(a292), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm31 <= 0;
tm140 <= 0;
tm32 <= 0;
tm144 <= 0;
tm32 <= 0;
tm140 <= 0;
tm31 <= 0;
tm144 <= 0;
end
else begin
i5 <= i5_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm137 <= a297;
tm141 <= a298;
tm153 <= a282;
tm160 <= a286;
tm138 <= tm137;
tm142 <= tm141;
tm154 <= tm153;
tm161 <= tm160;
tm139 <= tm138;
tm143 <= tm142;
tm155 <= tm154;
tm162 <= tm161;
tm31 <= a287;
tm32 <= a289;
tm140 <= tm139;
tm144 <= tm143;
tm156 <= tm155;
tm163 <= tm162;
tm157 <= tm156;
tm164 <= tm163;
tm158 <= tm157;
tm165 <= tm164;
tm159 <= tm158;
tm166 <= tm165;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock82713(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85088(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a249;
wire signed [15:0] a250;
wire signed [15:0] a251;
wire signed [15:0] a252;
wire signed [15:0] t117;
wire signed [15:0] t118;
wire signed [15:0] t119;
wire signed [15:0] t120;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a249 = X0;
assign a250 = X2;
assign a251 = X1;
assign a252 = X3;
assign Y0 = t117;
assign Y1 = t118;
assign Y2 = t119;
assign Y3 = t120;
addfxp #(16, 1) add82725(.a(a249), .b(a250), .clk(clk), .q(t117)); // 0
addfxp #(16, 1) add82740(.a(a251), .b(a252), .clk(clk), .q(t118)); // 0
subfxp #(16, 1) sub82755(.a(a249), .b(a250), .clk(clk), .q(t119)); // 0
subfxp #(16, 1) sub82770(.a(a251), .b(a252), .clk(clk), .q(t120)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 12
// Gap: 4
module rc82795(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm82793 instPerm85089(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet82793(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [1:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
2'd0: control <= 1'b1;
2'd1: control <= 1'b1;
2'd2: control <= 1'b0;
2'd3: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 12
// Gap: 4
module perm82793(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 4;
parameter addrbits = 2;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm6;
assign tm6 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85094(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85095(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
shiftRegFIFO #(3, 1) shiftFIFO_85104(.X(next), .Y(next2), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85105(.X(next2), .Y(next3), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85106(.X(next3), .Y(next4), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85107(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85110(.X(tm6), .Y(tm6_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85113(.X(tm6_d), .Y(tm6_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 2) shiftFIFO_85118(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm6_d, s1rdloc})
{1'd0, 2'd0}: s1rd0 <= 2;
{1'd0, 2'd1}: s1rd0 <= 3;
{1'd0, 2'd2}: s1rd0 <= 0;
{1'd0, 2'd3}: s1rd0 <= 1;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm6_d, s1rdloc})
{1'd0, 2'd0}: s1rd1 <= 0;
{1'd0, 2'd1}: s1rd1 <= 1;
{1'd0, 2'd2}: s1rd1 <= 2;
{1'd0, 2'd3}: s1rd1 <= 3;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet82793 sw(tm6_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm6_dd, writeCycle})
{1'd0, 2'd0}: s2wr0 <= 2;
{1'd0, 2'd1}: s2wr0 <= 3;
{1'd0, 2'd2}: s2wr0 <= 0;
{1'd0, 2'd3}: s2wr0 <= 1;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm6_dd, writeCycle})
{1'd0, 2'd0}: s2wr1 <= 0;
{1'd0, 2'd1}: s2wr1 <= 1;
{1'd0, 2'd2}: s2wr1 <= 2;
{1'd0, 2'd3}: s2wr1 <= 3;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 4
module DirSum_82984(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [1:0] i4;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i4 <= 0;
end
else begin
if (next == 1)
i4 <= 0;
else if (i4 == 3)
i4 <= 0;
else
i4 <= i4 + 1;
end
end
codeBlock82798 codeBlockIsnt85119(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i4_in(i4),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D14_82970(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h2d41;
2: out3 <= 16'h0;
3: out3 <= 16'hd2bf;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D16_82982(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hd2bf;
2: out3 <= 16'hc000;
3: out3 <= 16'hd2bf;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock82798(clk, reset, next_in, next_out,
i4_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [1:0] i4_in;
reg [1:0] i4;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_85122(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a233;
wire signed [15:0] a222;
wire signed [15:0] a236;
wire signed [15:0] a226;
wire signed [15:0] a237;
wire signed [15:0] a238;
reg signed [15:0] tm167;
reg signed [15:0] tm171;
reg signed [15:0] tm183;
reg signed [15:0] tm190;
reg signed [15:0] tm168;
reg signed [15:0] tm172;
reg signed [15:0] tm184;
reg signed [15:0] tm191;
wire signed [15:0] tm9;
wire signed [15:0] a227;
wire signed [15:0] tm10;
wire signed [15:0] a229;
reg signed [15:0] tm169;
reg signed [15:0] tm173;
reg signed [15:0] tm185;
reg signed [15:0] tm192;
reg signed [15:0] tm39;
reg signed [15:0] tm40;
reg signed [15:0] tm170;
reg signed [15:0] tm174;
reg signed [15:0] tm186;
reg signed [15:0] tm193;
reg signed [15:0] tm187;
reg signed [15:0] tm194;
wire signed [15:0] a228;
wire signed [15:0] a230;
wire signed [15:0] a231;
wire signed [15:0] a232;
reg signed [15:0] tm188;
reg signed [15:0] tm195;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm189;
reg signed [15:0] tm196;
assign a233 = X0;
assign a222 = a233;
assign a236 = X1;
assign a226 = a236;
assign a237 = X2;
assign a238 = X3;
assign a227 = tm9;
assign a229 = tm10;
assign Y0 = tm189;
assign Y1 = tm196;
D14_82970 instD14inst0_82970(.addr(i4[1:0]), .out(tm9), .clk(clk));
D16_82982 instD16inst0_82982(.addr(i4[1:0]), .out(tm10), .clk(clk));
multfix #(16, 2) m82897(.a(tm39), .b(tm170), .clk(clk), .q_sc(a228), .q_unsc(), .rst(reset));
multfix #(16, 2) m82919(.a(tm40), .b(tm174), .clk(clk), .q_sc(a230), .q_unsc(), .rst(reset));
multfix #(16, 2) m82937(.a(tm40), .b(tm170), .clk(clk), .q_sc(a231), .q_unsc(), .rst(reset));
multfix #(16, 2) m82948(.a(tm39), .b(tm174), .clk(clk), .q_sc(a232), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub82926(.a(a228), .b(a230), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add82955(.a(a231), .b(a232), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm39 <= 0;
tm170 <= 0;
tm40 <= 0;
tm174 <= 0;
tm40 <= 0;
tm170 <= 0;
tm39 <= 0;
tm174 <= 0;
end
else begin
i4 <= i4_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm167 <= a237;
tm171 <= a238;
tm183 <= a222;
tm190 <= a226;
tm168 <= tm167;
tm172 <= tm171;
tm184 <= tm183;
tm191 <= tm190;
tm169 <= tm168;
tm173 <= tm172;
tm185 <= tm184;
tm192 <= tm191;
tm39 <= a227;
tm40 <= a229;
tm170 <= tm169;
tm174 <= tm173;
tm186 <= tm185;
tm193 <= tm192;
tm187 <= tm186;
tm194 <= tm193;
tm188 <= tm187;
tm195 <= tm194;
tm189 <= tm188;
tm196 <= tm195;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock82987(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85125(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a189;
wire signed [15:0] a190;
wire signed [15:0] a191;
wire signed [15:0] a192;
wire signed [15:0] t93;
wire signed [15:0] t94;
wire signed [15:0] t95;
wire signed [15:0] t96;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a189 = X0;
assign a190 = X2;
assign a191 = X1;
assign a192 = X3;
assign Y0 = t93;
assign Y1 = t94;
assign Y2 = t95;
assign Y3 = t96;
addfxp #(16, 1) add82999(.a(a189), .b(a190), .clk(clk), .q(t93)); // 0
addfxp #(16, 1) add83014(.a(a191), .b(a192), .clk(clk), .q(t94)); // 0
subfxp #(16, 1) sub83029(.a(a189), .b(a190), .clk(clk), .q(t95)); // 0
subfxp #(16, 1) sub83044(.a(a191), .b(a192), .clk(clk), .q(t96)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 20
// Gap: 8
module rc83069(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm83067 instPerm85126(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet83067(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [2:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
3'd0: control <= 1'b1;
3'd1: control <= 1'b1;
3'd2: control <= 1'b1;
3'd3: control <= 1'b1;
3'd4: control <= 1'b0;
3'd5: control <= 1'b0;
3'd6: control <= 1'b0;
3'd7: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 20
// Gap: 8
module perm83067(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 8;
parameter addrbits = 3;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm11;
assign tm11 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85131(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85132(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
shiftRegFIFO #(7, 1) shiftFIFO_85141(.X(next), .Y(next2), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85142(.X(next2), .Y(next3), .clk(clk));
shiftRegFIFO #(8, 1) shiftFIFO_85143(.X(next3), .Y(next4), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85144(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(7, 1) shiftFIFO_85147(.X(tm11), .Y(tm11_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85150(.X(tm11_d), .Y(tm11_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 3) shiftFIFO_85155(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm11_d, s1rdloc})
{1'd0, 3'd0}: s1rd0 <= 4;
{1'd0, 3'd1}: s1rd0 <= 5;
{1'd0, 3'd2}: s1rd0 <= 6;
{1'd0, 3'd3}: s1rd0 <= 7;
{1'd0, 3'd4}: s1rd0 <= 0;
{1'd0, 3'd5}: s1rd0 <= 1;
{1'd0, 3'd6}: s1rd0 <= 2;
{1'd0, 3'd7}: s1rd0 <= 3;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm11_d, s1rdloc})
{1'd0, 3'd0}: s1rd1 <= 0;
{1'd0, 3'd1}: s1rd1 <= 1;
{1'd0, 3'd2}: s1rd1 <= 2;
{1'd0, 3'd3}: s1rd1 <= 3;
{1'd0, 3'd4}: s1rd1 <= 4;
{1'd0, 3'd5}: s1rd1 <= 5;
{1'd0, 3'd6}: s1rd1 <= 6;
{1'd0, 3'd7}: s1rd1 <= 7;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet83067 sw(tm11_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm11_dd, writeCycle})
{1'd0, 3'd0}: s2wr0 <= 4;
{1'd0, 3'd1}: s2wr0 <= 5;
{1'd0, 3'd2}: s2wr0 <= 6;
{1'd0, 3'd3}: s2wr0 <= 7;
{1'd0, 3'd4}: s2wr0 <= 0;
{1'd0, 3'd5}: s2wr0 <= 1;
{1'd0, 3'd6}: s2wr0 <= 2;
{1'd0, 3'd7}: s2wr0 <= 3;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm11_dd, writeCycle})
{1'd0, 3'd0}: s2wr1 <= 0;
{1'd0, 3'd1}: s2wr1 <= 1;
{1'd0, 3'd2}: s2wr1 <= 2;
{1'd0, 3'd3}: s2wr1 <= 3;
{1'd0, 3'd4}: s2wr1 <= 4;
{1'd0, 3'd5}: s2wr1 <= 5;
{1'd0, 3'd6}: s2wr1 <= 6;
{1'd0, 3'd7}: s2wr1 <= 7;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 8
module DirSum_83274(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [2:0] i3;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i3 <= 0;
end
else begin
if (next == 1)
i3 <= 0;
else if (i3 == 7)
i3 <= 0;
else
i3 <= i3 + 1;
end
end
codeBlock83072 codeBlockIsnt85156(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i3_in(i3),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D10_83252(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [2:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3b21;
2: out3 <= 16'h2d41;
3: out3 <= 16'h187e;
4: out3 <= 16'h0;
5: out3 <= 16'he782;
6: out3 <= 16'hd2bf;
7: out3 <= 16'hc4df;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D12_83272(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [2:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'he782;
2: out3 <= 16'hd2bf;
3: out3 <= 16'hc4df;
4: out3 <= 16'hc000;
5: out3 <= 16'hc4df;
6: out3 <= 16'hd2bf;
7: out3 <= 16'he782;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock83072(clk, reset, next_in, next_out,
i3_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [2:0] i3_in;
reg [2:0] i3;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_85159(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a173;
wire signed [15:0] a162;
wire signed [15:0] a176;
wire signed [15:0] a166;
wire signed [15:0] a177;
wire signed [15:0] a178;
reg signed [15:0] tm197;
reg signed [15:0] tm201;
reg signed [15:0] tm213;
reg signed [15:0] tm220;
reg signed [15:0] tm198;
reg signed [15:0] tm202;
reg signed [15:0] tm214;
reg signed [15:0] tm221;
wire signed [15:0] tm14;
wire signed [15:0] a167;
wire signed [15:0] tm15;
wire signed [15:0] a169;
reg signed [15:0] tm199;
reg signed [15:0] tm203;
reg signed [15:0] tm215;
reg signed [15:0] tm222;
reg signed [15:0] tm47;
reg signed [15:0] tm48;
reg signed [15:0] tm200;
reg signed [15:0] tm204;
reg signed [15:0] tm216;
reg signed [15:0] tm223;
reg signed [15:0] tm217;
reg signed [15:0] tm224;
wire signed [15:0] a168;
wire signed [15:0] a170;
wire signed [15:0] a171;
wire signed [15:0] a172;
reg signed [15:0] tm218;
reg signed [15:0] tm225;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm219;
reg signed [15:0] tm226;
assign a173 = X0;
assign a162 = a173;
assign a176 = X1;
assign a166 = a176;
assign a177 = X2;
assign a178 = X3;
assign a167 = tm14;
assign a169 = tm15;
assign Y0 = tm219;
assign Y1 = tm226;
D10_83252 instD10inst0_83252(.addr(i3[2:0]), .out(tm14), .clk(clk));
D12_83272 instD12inst0_83272(.addr(i3[2:0]), .out(tm15), .clk(clk));
multfix #(16, 2) m83171(.a(tm47), .b(tm200), .clk(clk), .q_sc(a168), .q_unsc(), .rst(reset));
multfix #(16, 2) m83193(.a(tm48), .b(tm204), .clk(clk), .q_sc(a170), .q_unsc(), .rst(reset));
multfix #(16, 2) m83211(.a(tm48), .b(tm200), .clk(clk), .q_sc(a171), .q_unsc(), .rst(reset));
multfix #(16, 2) m83222(.a(tm47), .b(tm204), .clk(clk), .q_sc(a172), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub83200(.a(a168), .b(a170), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add83229(.a(a171), .b(a172), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm47 <= 0;
tm200 <= 0;
tm48 <= 0;
tm204 <= 0;
tm48 <= 0;
tm200 <= 0;
tm47 <= 0;
tm204 <= 0;
end
else begin
i3 <= i3_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm197 <= a177;
tm201 <= a178;
tm213 <= a162;
tm220 <= a166;
tm198 <= tm197;
tm202 <= tm201;
tm214 <= tm213;
tm221 <= tm220;
tm199 <= tm198;
tm203 <= tm202;
tm215 <= tm214;
tm222 <= tm221;
tm47 <= a167;
tm48 <= a169;
tm200 <= tm199;
tm204 <= tm203;
tm216 <= tm215;
tm223 <= tm222;
tm217 <= tm216;
tm224 <= tm223;
tm218 <= tm217;
tm225 <= tm224;
tm219 <= tm218;
tm226 <= tm225;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock83277(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85162(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a129;
wire signed [15:0] a130;
wire signed [15:0] a131;
wire signed [15:0] a132;
wire signed [15:0] t69;
wire signed [15:0] t70;
wire signed [15:0] t71;
wire signed [15:0] t72;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a129 = X0;
assign a130 = X2;
assign a131 = X1;
assign a132 = X3;
assign Y0 = t69;
assign Y1 = t70;
assign Y2 = t71;
assign Y3 = t72;
addfxp #(16, 1) add83289(.a(a129), .b(a130), .clk(clk), .q(t69)); // 0
addfxp #(16, 1) add83304(.a(a131), .b(a132), .clk(clk), .q(t70)); // 0
subfxp #(16, 1) sub83319(.a(a129), .b(a130), .clk(clk), .q(t71)); // 0
subfxp #(16, 1) sub83334(.a(a131), .b(a132), .clk(clk), .q(t72)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 36
// Gap: 16
module rc83359(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm83357 instPerm85163(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet83357(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [3:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
4'd0: control <= 1'b1;
4'd1: control <= 1'b1;
4'd2: control <= 1'b1;
4'd3: control <= 1'b1;
4'd4: control <= 1'b1;
4'd5: control <= 1'b1;
4'd6: control <= 1'b1;
4'd7: control <= 1'b1;
4'd8: control <= 1'b0;
4'd9: control <= 1'b0;
4'd10: control <= 1'b0;
4'd11: control <= 1'b0;
4'd12: control <= 1'b0;
4'd13: control <= 1'b0;
4'd14: control <= 1'b0;
4'd15: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 36
// Gap: 16
module perm83357(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 16;
parameter addrbits = 4;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm16;
assign tm16 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85168(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85169(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(15, 4) nextReg_85180(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85181(.X(next2), .Y(next3), .clk(clk));
nextReg #(16, 4) nextReg_85184(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85185(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(15, 1) shiftFIFO_85188(.X(tm16), .Y(tm16_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85191(.X(tm16_d), .Y(tm16_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 4) shiftFIFO_85196(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm16_d, s1rdloc})
{1'd0, 4'd0}: s1rd0 <= 8;
{1'd0, 4'd1}: s1rd0 <= 9;
{1'd0, 4'd2}: s1rd0 <= 10;
{1'd0, 4'd3}: s1rd0 <= 11;
{1'd0, 4'd4}: s1rd0 <= 12;
{1'd0, 4'd5}: s1rd0 <= 13;
{1'd0, 4'd6}: s1rd0 <= 14;
{1'd0, 4'd7}: s1rd0 <= 15;
{1'd0, 4'd8}: s1rd0 <= 0;
{1'd0, 4'd9}: s1rd0 <= 1;
{1'd0, 4'd10}: s1rd0 <= 2;
{1'd0, 4'd11}: s1rd0 <= 3;
{1'd0, 4'd12}: s1rd0 <= 4;
{1'd0, 4'd13}: s1rd0 <= 5;
{1'd0, 4'd14}: s1rd0 <= 6;
{1'd0, 4'd15}: s1rd0 <= 7;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm16_d, s1rdloc})
{1'd0, 4'd0}: s1rd1 <= 0;
{1'd0, 4'd1}: s1rd1 <= 1;
{1'd0, 4'd2}: s1rd1 <= 2;
{1'd0, 4'd3}: s1rd1 <= 3;
{1'd0, 4'd4}: s1rd1 <= 4;
{1'd0, 4'd5}: s1rd1 <= 5;
{1'd0, 4'd6}: s1rd1 <= 6;
{1'd0, 4'd7}: s1rd1 <= 7;
{1'd0, 4'd8}: s1rd1 <= 8;
{1'd0, 4'd9}: s1rd1 <= 9;
{1'd0, 4'd10}: s1rd1 <= 10;
{1'd0, 4'd11}: s1rd1 <= 11;
{1'd0, 4'd12}: s1rd1 <= 12;
{1'd0, 4'd13}: s1rd1 <= 13;
{1'd0, 4'd14}: s1rd1 <= 14;
{1'd0, 4'd15}: s1rd1 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet83357 sw(tm16_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm16_dd, writeCycle})
{1'd0, 4'd0}: s2wr0 <= 8;
{1'd0, 4'd1}: s2wr0 <= 9;
{1'd0, 4'd2}: s2wr0 <= 10;
{1'd0, 4'd3}: s2wr0 <= 11;
{1'd0, 4'd4}: s2wr0 <= 12;
{1'd0, 4'd5}: s2wr0 <= 13;
{1'd0, 4'd6}: s2wr0 <= 14;
{1'd0, 4'd7}: s2wr0 <= 15;
{1'd0, 4'd8}: s2wr0 <= 0;
{1'd0, 4'd9}: s2wr0 <= 1;
{1'd0, 4'd10}: s2wr0 <= 2;
{1'd0, 4'd11}: s2wr0 <= 3;
{1'd0, 4'd12}: s2wr0 <= 4;
{1'd0, 4'd13}: s2wr0 <= 5;
{1'd0, 4'd14}: s2wr0 <= 6;
{1'd0, 4'd15}: s2wr0 <= 7;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm16_dd, writeCycle})
{1'd0, 4'd0}: s2wr1 <= 0;
{1'd0, 4'd1}: s2wr1 <= 1;
{1'd0, 4'd2}: s2wr1 <= 2;
{1'd0, 4'd3}: s2wr1 <= 3;
{1'd0, 4'd4}: s2wr1 <= 4;
{1'd0, 4'd5}: s2wr1 <= 5;
{1'd0, 4'd6}: s2wr1 <= 6;
{1'd0, 4'd7}: s2wr1 <= 7;
{1'd0, 4'd8}: s2wr1 <= 8;
{1'd0, 4'd9}: s2wr1 <= 9;
{1'd0, 4'd10}: s2wr1 <= 10;
{1'd0, 4'd11}: s2wr1 <= 11;
{1'd0, 4'd12}: s2wr1 <= 12;
{1'd0, 4'd13}: s2wr1 <= 13;
{1'd0, 4'd14}: s2wr1 <= 14;
{1'd0, 4'd15}: s2wr1 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 16
module DirSum_83596(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [3:0] i2;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i2 <= 0;
end
else begin
if (next == 1)
i2 <= 0;
else if (i2 == 15)
i2 <= 0;
else
i2 <= i2 + 1;
end
end
codeBlock83362 codeBlockIsnt85201(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i2_in(i2),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D6_83558(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3ec5;
2: out3 <= 16'h3b21;
3: out3 <= 16'h3537;
4: out3 <= 16'h2d41;
5: out3 <= 16'h238e;
6: out3 <= 16'h187e;
7: out3 <= 16'hc7c;
8: out3 <= 16'h0;
9: out3 <= 16'hf384;
10: out3 <= 16'he782;
11: out3 <= 16'hdc72;
12: out3 <= 16'hd2bf;
13: out3 <= 16'hcac9;
14: out3 <= 16'hc4df;
15: out3 <= 16'hc13b;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D8_83594(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hf384;
2: out3 <= 16'he782;
3: out3 <= 16'hdc72;
4: out3 <= 16'hd2bf;
5: out3 <= 16'hcac9;
6: out3 <= 16'hc4df;
7: out3 <= 16'hc13b;
8: out3 <= 16'hc000;
9: out3 <= 16'hc13b;
10: out3 <= 16'hc4df;
11: out3 <= 16'hcac9;
12: out3 <= 16'hd2bf;
13: out3 <= 16'hdc72;
14: out3 <= 16'he782;
15: out3 <= 16'hf384;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock83362(clk, reset, next_in, next_out,
i2_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [3:0] i2_in;
reg [3:0] i2;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_85204(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a113;
wire signed [15:0] a102;
wire signed [15:0] a116;
wire signed [15:0] a106;
wire signed [15:0] a117;
wire signed [15:0] a118;
reg signed [15:0] tm227;
reg signed [15:0] tm231;
reg signed [15:0] tm243;
reg signed [15:0] tm250;
reg signed [15:0] tm228;
reg signed [15:0] tm232;
reg signed [15:0] tm244;
reg signed [15:0] tm251;
wire signed [15:0] tm19;
wire signed [15:0] a107;
wire signed [15:0] tm20;
wire signed [15:0] a109;
reg signed [15:0] tm229;
reg signed [15:0] tm233;
reg signed [15:0] tm245;
reg signed [15:0] tm252;
reg signed [15:0] tm55;
reg signed [15:0] tm56;
reg signed [15:0] tm230;
reg signed [15:0] tm234;
reg signed [15:0] tm246;
reg signed [15:0] tm253;
reg signed [15:0] tm247;
reg signed [15:0] tm254;
wire signed [15:0] a108;
wire signed [15:0] a110;
wire signed [15:0] a111;
wire signed [15:0] a112;
reg signed [15:0] tm248;
reg signed [15:0] tm255;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm249;
reg signed [15:0] tm256;
assign a113 = X0;
assign a102 = a113;
assign a116 = X1;
assign a106 = a116;
assign a117 = X2;
assign a118 = X3;
assign a107 = tm19;
assign a109 = tm20;
assign Y0 = tm249;
assign Y1 = tm256;
D6_83558 instD6inst0_83558(.addr(i2[3:0]), .out(tm19), .clk(clk));
D8_83594 instD8inst0_83594(.addr(i2[3:0]), .out(tm20), .clk(clk));
multfix #(16, 2) m83461(.a(tm55), .b(tm230), .clk(clk), .q_sc(a108), .q_unsc(), .rst(reset));
multfix #(16, 2) m83483(.a(tm56), .b(tm234), .clk(clk), .q_sc(a110), .q_unsc(), .rst(reset));
multfix #(16, 2) m83501(.a(tm56), .b(tm230), .clk(clk), .q_sc(a111), .q_unsc(), .rst(reset));
multfix #(16, 2) m83512(.a(tm55), .b(tm234), .clk(clk), .q_sc(a112), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub83490(.a(a108), .b(a110), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add83519(.a(a111), .b(a112), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm55 <= 0;
tm230 <= 0;
tm56 <= 0;
tm234 <= 0;
tm56 <= 0;
tm230 <= 0;
tm55 <= 0;
tm234 <= 0;
end
else begin
i2 <= i2_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm227 <= a117;
tm231 <= a118;
tm243 <= a102;
tm250 <= a106;
tm228 <= tm227;
tm232 <= tm231;
tm244 <= tm243;
tm251 <= tm250;
tm229 <= tm228;
tm233 <= tm232;
tm245 <= tm244;
tm252 <= tm251;
tm55 <= a107;
tm56 <= a109;
tm230 <= tm229;
tm234 <= tm233;
tm246 <= tm245;
tm253 <= tm252;
tm247 <= tm246;
tm254 <= tm253;
tm248 <= tm247;
tm255 <= tm254;
tm249 <= tm248;
tm256 <= tm255;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock83599(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85207(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a69;
wire signed [15:0] a70;
wire signed [15:0] a71;
wire signed [15:0] a72;
wire signed [15:0] t45;
wire signed [15:0] t46;
wire signed [15:0] t47;
wire signed [15:0] t48;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a69 = X0;
assign a70 = X2;
assign a71 = X1;
assign a72 = X3;
assign Y0 = t45;
assign Y1 = t46;
assign Y2 = t47;
assign Y3 = t48;
addfxp #(16, 1) add83611(.a(a69), .b(a70), .clk(clk), .q(t45)); // 0
addfxp #(16, 1) add83626(.a(a71), .b(a72), .clk(clk), .q(t46)); // 0
subfxp #(16, 1) sub83641(.a(a69), .b(a70), .clk(clk), .q(t47)); // 0
subfxp #(16, 1) sub83656(.a(a71), .b(a72), .clk(clk), .q(t48)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 68
// Gap: 32
module rc83681(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm83679 instPerm85208(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet83679(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm83679(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter addrbits = 5;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm21;
assign tm21 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85213(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85214(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(31, 5) nextReg_85225(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85226(.X(next2), .Y(next3), .clk(clk));
nextReg #(32, 5) nextReg_85229(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85230(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(31, 1) shiftFIFO_85233(.X(tm21), .Y(tm21_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85236(.X(tm21_d), .Y(tm21_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 5) shiftFIFO_85241(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm21_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 16;
{1'd0, 5'd1}: s1rd0 <= 17;
{1'd0, 5'd2}: s1rd0 <= 18;
{1'd0, 5'd3}: s1rd0 <= 19;
{1'd0, 5'd4}: s1rd0 <= 20;
{1'd0, 5'd5}: s1rd0 <= 21;
{1'd0, 5'd6}: s1rd0 <= 22;
{1'd0, 5'd7}: s1rd0 <= 23;
{1'd0, 5'd8}: s1rd0 <= 24;
{1'd0, 5'd9}: s1rd0 <= 25;
{1'd0, 5'd10}: s1rd0 <= 26;
{1'd0, 5'd11}: s1rd0 <= 27;
{1'd0, 5'd12}: s1rd0 <= 28;
{1'd0, 5'd13}: s1rd0 <= 29;
{1'd0, 5'd14}: s1rd0 <= 30;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 1;
{1'd0, 5'd18}: s1rd0 <= 2;
{1'd0, 5'd19}: s1rd0 <= 3;
{1'd0, 5'd20}: s1rd0 <= 4;
{1'd0, 5'd21}: s1rd0 <= 5;
{1'd0, 5'd22}: s1rd0 <= 6;
{1'd0, 5'd23}: s1rd0 <= 7;
{1'd0, 5'd24}: s1rd0 <= 8;
{1'd0, 5'd25}: s1rd0 <= 9;
{1'd0, 5'd26}: s1rd0 <= 10;
{1'd0, 5'd27}: s1rd0 <= 11;
{1'd0, 5'd28}: s1rd0 <= 12;
{1'd0, 5'd29}: s1rd0 <= 13;
{1'd0, 5'd30}: s1rd0 <= 14;
{1'd0, 5'd31}: s1rd0 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm21_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 1;
{1'd0, 5'd2}: s1rd1 <= 2;
{1'd0, 5'd3}: s1rd1 <= 3;
{1'd0, 5'd4}: s1rd1 <= 4;
{1'd0, 5'd5}: s1rd1 <= 5;
{1'd0, 5'd6}: s1rd1 <= 6;
{1'd0, 5'd7}: s1rd1 <= 7;
{1'd0, 5'd8}: s1rd1 <= 8;
{1'd0, 5'd9}: s1rd1 <= 9;
{1'd0, 5'd10}: s1rd1 <= 10;
{1'd0, 5'd11}: s1rd1 <= 11;
{1'd0, 5'd12}: s1rd1 <= 12;
{1'd0, 5'd13}: s1rd1 <= 13;
{1'd0, 5'd14}: s1rd1 <= 14;
{1'd0, 5'd15}: s1rd1 <= 15;
{1'd0, 5'd16}: s1rd1 <= 16;
{1'd0, 5'd17}: s1rd1 <= 17;
{1'd0, 5'd18}: s1rd1 <= 18;
{1'd0, 5'd19}: s1rd1 <= 19;
{1'd0, 5'd20}: s1rd1 <= 20;
{1'd0, 5'd21}: s1rd1 <= 21;
{1'd0, 5'd22}: s1rd1 <= 22;
{1'd0, 5'd23}: s1rd1 <= 23;
{1'd0, 5'd24}: s1rd1 <= 24;
{1'd0, 5'd25}: s1rd1 <= 25;
{1'd0, 5'd26}: s1rd1 <= 26;
{1'd0, 5'd27}: s1rd1 <= 27;
{1'd0, 5'd28}: s1rd1 <= 28;
{1'd0, 5'd29}: s1rd1 <= 29;
{1'd0, 5'd30}: s1rd1 <= 30;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet83679 sw(tm21_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm21_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm21_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 32
module DirSum_83981(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [4:0] i1;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i1 <= 0;
end
else begin
if (next == 1)
i1 <= 0;
else if (i1 == 31)
i1 <= 0;
else
i1 <= i1 + 1;
end
end
codeBlock83683 codeBlockIsnt85246(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i1_in(i1),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D2_83911(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [4:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3fb1;
2: out3 <= 16'h3ec5;
3: out3 <= 16'h3d3f;
4: out3 <= 16'h3b21;
5: out3 <= 16'h3871;
6: out3 <= 16'h3537;
7: out3 <= 16'h3179;
8: out3 <= 16'h2d41;
9: out3 <= 16'h289a;
10: out3 <= 16'h238e;
11: out3 <= 16'h1e2b;
12: out3 <= 16'h187e;
13: out3 <= 16'h1294;
14: out3 <= 16'hc7c;
15: out3 <= 16'h646;
16: out3 <= 16'h0;
17: out3 <= 16'hf9ba;
18: out3 <= 16'hf384;
19: out3 <= 16'hed6c;
20: out3 <= 16'he782;
21: out3 <= 16'he1d5;
22: out3 <= 16'hdc72;
23: out3 <= 16'hd766;
24: out3 <= 16'hd2bf;
25: out3 <= 16'hce87;
26: out3 <= 16'hcac9;
27: out3 <= 16'hc78f;
28: out3 <= 16'hc4df;
29: out3 <= 16'hc2c1;
30: out3 <= 16'hc13b;
31: out3 <= 16'hc04f;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D4_83979(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [4:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hf9ba;
2: out3 <= 16'hf384;
3: out3 <= 16'hed6c;
4: out3 <= 16'he782;
5: out3 <= 16'he1d5;
6: out3 <= 16'hdc72;
7: out3 <= 16'hd766;
8: out3 <= 16'hd2bf;
9: out3 <= 16'hce87;
10: out3 <= 16'hcac9;
11: out3 <= 16'hc78f;
12: out3 <= 16'hc4df;
13: out3 <= 16'hc2c1;
14: out3 <= 16'hc13b;
15: out3 <= 16'hc04f;
16: out3 <= 16'hc000;
17: out3 <= 16'hc04f;
18: out3 <= 16'hc13b;
19: out3 <= 16'hc2c1;
20: out3 <= 16'hc4df;
21: out3 <= 16'hc78f;
22: out3 <= 16'hcac9;
23: out3 <= 16'hce87;
24: out3 <= 16'hd2bf;
25: out3 <= 16'hd766;
26: out3 <= 16'hdc72;
27: out3 <= 16'he1d5;
28: out3 <= 16'he782;
29: out3 <= 16'hed6c;
30: out3 <= 16'hf384;
31: out3 <= 16'hf9ba;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock83683(clk, reset, next_in, next_out,
i1_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [4:0] i1_in;
reg [4:0] i1;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_85249(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a53;
wire signed [15:0] a42;
wire signed [15:0] a56;
wire signed [15:0] a46;
wire signed [15:0] a57;
wire signed [15:0] a58;
reg signed [15:0] tm257;
reg signed [15:0] tm261;
reg signed [15:0] tm273;
reg signed [15:0] tm280;
reg signed [15:0] tm258;
reg signed [15:0] tm262;
reg signed [15:0] tm274;
reg signed [15:0] tm281;
wire signed [15:0] tm24;
wire signed [15:0] a47;
wire signed [15:0] tm25;
wire signed [15:0] a49;
reg signed [15:0] tm259;
reg signed [15:0] tm263;
reg signed [15:0] tm275;
reg signed [15:0] tm282;
reg signed [15:0] tm63;
reg signed [15:0] tm64;
reg signed [15:0] tm260;
reg signed [15:0] tm264;
reg signed [15:0] tm276;
reg signed [15:0] tm283;
reg signed [15:0] tm277;
reg signed [15:0] tm284;
wire signed [15:0] a48;
wire signed [15:0] a50;
wire signed [15:0] a51;
wire signed [15:0] a52;
reg signed [15:0] tm278;
reg signed [15:0] tm285;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm279;
reg signed [15:0] tm286;
assign a53 = X0;
assign a42 = a53;
assign a56 = X1;
assign a46 = a56;
assign a57 = X2;
assign a58 = X3;
assign a47 = tm24;
assign a49 = tm25;
assign Y0 = tm279;
assign Y1 = tm286;
D2_83911 instD2inst0_83911(.addr(i1[4:0]), .out(tm24), .clk(clk));
D4_83979 instD4inst0_83979(.addr(i1[4:0]), .out(tm25), .clk(clk));
multfix #(16, 2) m83782(.a(tm63), .b(tm260), .clk(clk), .q_sc(a48), .q_unsc(), .rst(reset));
multfix #(16, 2) m83804(.a(tm64), .b(tm264), .clk(clk), .q_sc(a50), .q_unsc(), .rst(reset));
multfix #(16, 2) m83822(.a(tm64), .b(tm260), .clk(clk), .q_sc(a51), .q_unsc(), .rst(reset));
multfix #(16, 2) m83833(.a(tm63), .b(tm264), .clk(clk), .q_sc(a52), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub83811(.a(a48), .b(a50), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add83840(.a(a51), .b(a52), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm63 <= 0;
tm260 <= 0;
tm64 <= 0;
tm264 <= 0;
tm64 <= 0;
tm260 <= 0;
tm63 <= 0;
tm264 <= 0;
end
else begin
i1 <= i1_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm257 <= a57;
tm261 <= a58;
tm273 <= a42;
tm280 <= a46;
tm258 <= tm257;
tm262 <= tm261;
tm274 <= tm273;
tm281 <= tm280;
tm259 <= tm258;
tm263 <= tm262;
tm275 <= tm274;
tm282 <= tm281;
tm63 <= a47;
tm64 <= a49;
tm260 <= tm259;
tm264 <= tm263;
tm276 <= tm275;
tm283 <= tm282;
tm277 <= tm276;
tm284 <= tm283;
tm278 <= tm277;
tm285 <= tm284;
tm279 <= tm278;
tm286 <= tm285;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock83984(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85252(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a9;
wire signed [15:0] a10;
wire signed [15:0] a11;
wire signed [15:0] a12;
wire signed [15:0] t21;
wire signed [15:0] t22;
wire signed [15:0] t23;
wire signed [15:0] t24;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a9 = X0;
assign a10 = X2;
assign a11 = X1;
assign a12 = X3;
assign Y0 = t21;
assign Y1 = t22;
assign Y2 = t23;
assign Y3 = t24;
addfxp #(16, 1) add83996(.a(a9), .b(a10), .clk(clk), .q(t21)); // 0
addfxp #(16, 1) add84011(.a(a11), .b(a12), .clk(clk), .q(t22)); // 0
subfxp #(16, 1) sub84026(.a(a9), .b(a10), .clk(clk), .q(t23)); // 0
subfxp #(16, 1) sub84041(.a(a11), .b(a12), .clk(clk), .q(t24)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 68
// Gap: 32
module rc84066(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm84064 instPerm85253(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet84064(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm84064(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter addrbits = 5;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm26;
assign tm26 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85258(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85259(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(31, 5) nextReg_85270(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85271(.X(next2), .Y(next3), .clk(clk));
nextReg #(32, 5) nextReg_85274(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85275(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(31, 1) shiftFIFO_85278(.X(tm26), .Y(tm26_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85281(.X(tm26_d), .Y(tm26_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 5) shiftFIFO_85286(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm26_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 1;
{1'd0, 5'd1}: s1rd0 <= 3;
{1'd0, 5'd2}: s1rd0 <= 5;
{1'd0, 5'd3}: s1rd0 <= 7;
{1'd0, 5'd4}: s1rd0 <= 9;
{1'd0, 5'd5}: s1rd0 <= 11;
{1'd0, 5'd6}: s1rd0 <= 13;
{1'd0, 5'd7}: s1rd0 <= 15;
{1'd0, 5'd8}: s1rd0 <= 17;
{1'd0, 5'd9}: s1rd0 <= 19;
{1'd0, 5'd10}: s1rd0 <= 21;
{1'd0, 5'd11}: s1rd0 <= 23;
{1'd0, 5'd12}: s1rd0 <= 25;
{1'd0, 5'd13}: s1rd0 <= 27;
{1'd0, 5'd14}: s1rd0 <= 29;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 2;
{1'd0, 5'd18}: s1rd0 <= 4;
{1'd0, 5'd19}: s1rd0 <= 6;
{1'd0, 5'd20}: s1rd0 <= 8;
{1'd0, 5'd21}: s1rd0 <= 10;
{1'd0, 5'd22}: s1rd0 <= 12;
{1'd0, 5'd23}: s1rd0 <= 14;
{1'd0, 5'd24}: s1rd0 <= 16;
{1'd0, 5'd25}: s1rd0 <= 18;
{1'd0, 5'd26}: s1rd0 <= 20;
{1'd0, 5'd27}: s1rd0 <= 22;
{1'd0, 5'd28}: s1rd0 <= 24;
{1'd0, 5'd29}: s1rd0 <= 26;
{1'd0, 5'd30}: s1rd0 <= 28;
{1'd0, 5'd31}: s1rd0 <= 30;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm26_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 2;
{1'd0, 5'd2}: s1rd1 <= 4;
{1'd0, 5'd3}: s1rd1 <= 6;
{1'd0, 5'd4}: s1rd1 <= 8;
{1'd0, 5'd5}: s1rd1 <= 10;
{1'd0, 5'd6}: s1rd1 <= 12;
{1'd0, 5'd7}: s1rd1 <= 14;
{1'd0, 5'd8}: s1rd1 <= 16;
{1'd0, 5'd9}: s1rd1 <= 18;
{1'd0, 5'd10}: s1rd1 <= 20;
{1'd0, 5'd11}: s1rd1 <= 22;
{1'd0, 5'd12}: s1rd1 <= 24;
{1'd0, 5'd13}: s1rd1 <= 26;
{1'd0, 5'd14}: s1rd1 <= 28;
{1'd0, 5'd15}: s1rd1 <= 30;
{1'd0, 5'd16}: s1rd1 <= 1;
{1'd0, 5'd17}: s1rd1 <= 3;
{1'd0, 5'd18}: s1rd1 <= 5;
{1'd0, 5'd19}: s1rd1 <= 7;
{1'd0, 5'd20}: s1rd1 <= 9;
{1'd0, 5'd21}: s1rd1 <= 11;
{1'd0, 5'd22}: s1rd1 <= 13;
{1'd0, 5'd23}: s1rd1 <= 15;
{1'd0, 5'd24}: s1rd1 <= 17;
{1'd0, 5'd25}: s1rd1 <= 19;
{1'd0, 5'd26}: s1rd1 <= 21;
{1'd0, 5'd27}: s1rd1 <= 23;
{1'd0, 5'd28}: s1rd1 <= 25;
{1'd0, 5'd29}: s1rd1 <= 27;
{1'd0, 5'd30}: s1rd1 <= 29;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet84064 sw(tm26_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm26_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm26_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
module multfix(clk, rst, a, b, q_sc, q_unsc);
parameter WIDTH=35, CYCLES=6;
input signed [WIDTH-1:0] a,b;
output [WIDTH-1:0] q_sc;
output [WIDTH-1:0] q_unsc;
input clk, rst;
reg signed [2*WIDTH-1:0] q[CYCLES-1:0];
wire signed [2*WIDTH-1:0] res;
integer i;
assign res = q[CYCLES-1];
assign q_unsc = res[WIDTH-1:0];
assign q_sc = {res[2*WIDTH-1], res[2*WIDTH-4:WIDTH-2]};
always @(posedge clk) begin
q[0] <= a * b;
for (i = 1; i < CYCLES; i=i+1) begin
q[i] <= q[i-1];
end
end
endmodule
module addfxp(a, b, q, clk);
parameter width = 16, cycles=1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a+b;
for (i=1; i < cycles; i = i+1)
res[i] <= res[i-1];
end
endmodule
module subfxp(a, b, q, clk);
parameter width = 16, cycles=1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a-b;
for (i=1; i < cycles; i = i+1)
res[i] <= res[i-1];
end
endmodule |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : dft_top_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-DFT core
//
module dft_top_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg next;
reg [63:0] dataX [0:31];
reg [63:0] dataY [0:31];
reg [5:0] xSel;
reg [5:0] ySel;
wire [63:0] dataIn, dataOut, dataR_Out;
reg [63:0] data_In_data, data_In_addr, data_Out_addr;
reg data_valid, data_In_write;
wire next_out, next_posedge;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i)
begin
if(wb_rst_i)
begin
next <= 0;
data_In_write <= 0;
data_In_addr <= 0;
data_In_data[31:0] <= 0;
data_In_data[63:32]<= 0;
end
else if(wb_stb_i & wb_we_i)
case(wb_adr_i[5:2])
0:
next <= wb_dat_i[0];
1:
data_In_write <= wb_dat_i[0];
2:
data_In_addr <= wb_dat_i;
3:
data_In_data[31:0] <= wb_dat_i;
4:
data_In_data[63:32]<= wb_dat_i;
5:
data_Out_addr <= wb_dat_i;
default:
;
endcase
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[5:2])
0:
wb_dat_o = {31'b0, next};
1:
wb_dat_o = {31'b0, data_In_write};
2:
wb_dat_o = data_In_addr;
3:
wb_dat_o = data_In_data[31:0];
4:
wb_dat_o = data_In_data[63:32];
5:
wb_dat_o = data_Out_addr;
6:
wb_dat_o = dataR_Out[31:0];
7:
wb_dat_o = dataR_Out[63:32];
8:
wb_dat_o = {31'b0, data_valid};
default:
wb_dat_o = 32'b0;
endcase
end // always @ (*)
dft_top dft_top(
.clk(wb_clk_i),
.reset(wb_rst_i),
.next(next_posedge),
.next_out(next_out),
.X0(dataIn[15:0]),
.X1(dataIn[31:16]),
.X2(dataIn[47:32]),
.X3(dataIn[63:48]),
.Y0(dataOut[15:0]),
.Y1(dataOut[31:16]),
.Y2(dataOut[47:32]),
.Y3(dataOut[63:48]));
reg data_In_write_r;
always @(posedge wb_clk_i)
begin
data_In_write_r <= data_In_write;
end
wire data_In_write_posedge = data_In_write & ~data_In_write_r;
always @ (posedge wb_clk_i)
begin
if(data_In_write_posedge)
begin
dataX[data_In_addr] <= data_In_data;
end
end
assign dataR_Out=dataY[data_Out_addr];
reg next_r;
always @(posedge wb_clk_i)
begin
next_r <= next;
end
assign next_posedge = next & ~next_r;
always @ (posedge wb_clk_i)
begin
if(next_posedge)
begin
xSel <= 6'h00;
end
else if(xSel<6'b100000)
begin
xSel <= xSel +1;
end
end
assign dataIn = dataX[xSel];
reg next_out_r;
always @(posedge wb_clk_i)
begin
next_out_r <= next_out;
end
wire next_out_posedge = next_out & ~next_out_r;
always @ (posedge wb_clk_i)
begin
if(next_out_posedge)
begin
ySel <= 6'h00;
end
else if(ySel<6'b100000)
begin
ySel <= ySel +1;
dataY[ySel] = dataOut;
end
end
always @ (posedge wb_clk_i)
begin
if(next_posedge)
begin
data_valid <= 0;
end
else if(next_out_posedge)
begin
data_valid <= 1;
end
end
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral IIR Filter Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./iirGen.pl -A 256 0 378 0 179 0 32 0 2 0 0 0 -B 0 -4 22 -68 136 -191 191 -136 68 -22 4 0 -moduleName FIR_filter -fractionalBits 8 -bitWidth 32 -inData inData -inReg -outReg -outData outData -clk clk -reset reset -reset_edge negedge -filterForm 1 -debug -outFile ../outputs/filter_1536037053.v */
/* Warning: zero-valued filter taps have been optimized away. */
module FIR_filter (
inData,
clk,
outData,
reset
);
// Port mode declarations:
input [31:0] inData;
input clk;
output [31:0] outData;
input reset;
//registerIn
reg [31:0] inData_in;
always@(posedge clk or negedge reset) begin
if(~reset) begin
inData_in <= 32'h00000000;
end else begin
inData_in <= inData;
end
end
//registerOut
reg [31:0] outData;
wire [31:0] outData_in;
always@(posedge clk or negedge reset) begin
if(~reset) begin
outData <= 32'h00000000;
end else begin
outData <= outData_in;
end
end
wire [31:0] leftOut, rightOut;
FIR_filter_firBlock_left my_FIR_filter_firBlock_left(
.X(inData_in),
.Y(leftOut),
.clk(clk),
.reset(reset)
);
FIR_filter_firBlock_right my_FIR_filter_firBlock_right(
.X(outData_in),
.Y(rightOut),
.clk(clk),
.reset(reset)
);
assign outData_in = leftOut + rightOut; // adder(32)
//FIR_filter area estimate = 113925.875962894;
endmodule //FIR_filter
module FIR_filter_firBlock_left_MultiplyBlock (
X,
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11
);
// Port mode declarations:
input signed [31:0] X;
output signed [31:0]
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11;
wire [31:0] Y [0:10];
assign Y1 = Y[0];
assign Y2 = Y[1];
assign Y3 = Y[2];
assign Y4 = Y[3];
assign Y5 = Y[4];
assign Y6 = Y[5];
assign Y7 = Y[6];
assign Y8 = Y[7];
assign Y9 = Y[8];
assign Y10 = Y[9];
assign Y11 = Y[10];
//Multipliers:
wire signed [39:0]
w1,
w0,
w16,
w17,
w4,
w3,
w8,
w11,
w192,
w191,
w22,
w22_,
w68,
w136,
w136_,
w191_,
w68_,
w4_;
assign w1 = X;
assign w0 = 0;
assign w11 = w3 + w8; //2195.42405790882 = adderArea(3,34)
assign w136 = w17 << 3; //shl(3,39)
assign w136_ = -1 * w136; //1669.85284613971 = negArea(3,39)
assign w16 = w1 << 4; //shl(4,35)
assign w17 = w1 + w16; //2195.42405790882 = adderArea(4,35)
assign w191 = w192 - w1; //2561.32791574853 = subArea(6,39)
assign w191_ = -1 * w191; //1809.56165059559 = negArea(0,39)
assign w192 = w3 << 6; //shl(6,39)
assign w22 = w11 << 1; //shl(1,36)
assign w22_ = -1 * w22; //1623.28324465441 = negArea(1,36)
assign w3 = w4 - w1; //2408.3135227603 = subArea(2,33)
assign w4 = w1 << 2; //shl(2,33)
assign w4_ = -1 * w4; //1437.00483871323 = negArea(2,33)
assign w68 = w17 << 2; //shl(2,38)
assign w68_ = -1 * w68; //1669.85284613971 = negArea(2,38)
assign w8 = w1 << 3; //shl(3,34)
assign Y[0] = w4[39:8]; //BitwidthUsed(0, 25)
assign Y[1] = w22_[39:8]; //BitwidthUsed(0, 28)
assign Y[2] = w68[39:8]; //BitwidthUsed(0, 30)
assign Y[3] = w136_[39:8]; //BitwidthUsed(0, 31)
assign Y[4] = w191[39:8]; //BitwidthUsed(0, 31)
assign Y[5] = w191_[39:8]; //BitwidthUsed(0, 31)
assign Y[6] = w136[39:8]; //BitwidthUsed(0, 31)
assign Y[7] = w68_[39:8]; //BitwidthUsed(0, 30)
assign Y[8] = w22[39:8]; //BitwidthUsed(0, 28)
assign Y[9] = w4_[39:8]; //BitwidthUsed(0, 25)
assign Y[10] = w0[39:8]; //BitwidthUsed(none)
//FIR_filter_firBlock_left_MultiplyBlock area estimate = 17570.0449805691;
endmodule //FIR_filter_firBlock_left_MultiplyBlock
module FIR_filter_firBlock_left (
X,
clk,
Y,
reset
);
// Port mode declarations:
input [31:0] X;
input clk;
output [31:0] Y;
input reset;
//registerOut
reg [31:0] Y;
wire [31:0] Y_in;
always@(posedge clk or negedge reset) begin
if(~reset) begin
Y <= 32'h00000000;
end else begin
Y <= Y_in;
end
end
wire [31:0] multProducts [0:10];
FIR_filter_firBlock_left_MultiplyBlock my_FIR_filter_firBlock_left_MultiplyBlock(
.X(X),
.Y1(multProducts[0]),
.Y2(multProducts[1]),
.Y3(multProducts[2]),
.Y4(multProducts[3]),
.Y5(multProducts[4]),
.Y6(multProducts[5]),
.Y7(multProducts[6]),
.Y8(multProducts[7]),
.Y9(multProducts[8]),
.Y10(multProducts[9]),
.Y11(multProducts[10])
);
reg [31:0] firStep[0:9];
always@(posedge clk or negedge reset) begin
if(~reset) begin
firStep[0] <= 32'h00000000;
firStep[1] <= 32'h00000000;
firStep[2] <= 32'h00000000;
firStep[3] <= 32'h00000000;
firStep[4] <= 32'h00000000;
firStep[5] <= 32'h00000000;
firStep[6] <= 32'h00000000;
firStep[7] <= 32'h00000000;
firStep[8] <= 32'h00000000;
firStep[9] <= 32'h00000000;
end
else begin
firStep[0] <= multProducts[0]; // 2448.23046908235 = flop(0, 31)
firStep[1] <= firStep[0] + multProducts[1]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[2] <= firStep[1] + multProducts[2]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[3] <= firStep[2] + multProducts[3]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[4] <= firStep[3] + multProducts[4]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[5] <= firStep[4] + multProducts[5]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[6] <= firStep[5] + multProducts[6]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[7] <= firStep[6] + multProducts[7]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[8] <= firStep[7] + multProducts[8]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[9] <= firStep[8] + multProducts[9]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
end
end
assign Y_in = firStep[9]+ multProducts[10];// 0 = adder(none)
//FIR_filter_firBlock_left area estimate = 64259.3966616544;
endmodule //FIR_filter_firBlock_left
/* Warning: zero-valued filter taps have been optimized away. */
module FIR_filter_firBlock_right_MultiplyBlock (
X,
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8
);
// Port mode declarations:
input signed [31:0] X;
output signed [31:0]
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8;
wire [31:0] Y [0:7];
assign Y1 = Y[0];
assign Y2 = Y[1];
assign Y3 = Y[2];
assign Y4 = Y[3];
assign Y5 = Y[4];
assign Y6 = Y[5];
assign Y7 = Y[6];
assign Y8 = Y[7];
//Multipliers:
wire signed [39:0]
w1,
w0,
w4,
w3,
w192,
w189,
w5,
w10,
w179,
w2,
w2_,
w32,
w32_,
w179_,
w378,
w378_;
assign w1 = X;
assign w0 = 0;
assign w10 = w5 << 1; //shl(1,35)
assign w179 = w189 - w10; //2943.86389821912 = subArea(1,39)
assign w179_ = -1 * w179; //1809.56165059559 = negArea(0,39)
assign w189 = w192 - w3; //2484.82071925441 = subArea(6,38)
assign w192 = w3 << 6; //shl(6,38)
assign w2 = w1 << 1; //shl(1,32)
assign w2_ = -1 * w2; //1437.00483871323 = negArea(1,32)
assign w3 = w4 - w1; //2331.80632626618 = subArea(2,32)
assign w32 = w1 << 5; //shl(5,36)
assign w32_ = -1 * w32; //1437.00483871323 = negArea(5,36)
assign w378 = w189 << 1; //shl(1,39)
assign w378_ = -1 * w378; //1762.99204911029 = negArea(1,39)
assign w4 = w1 << 2; //shl(2,32)
assign w5 = w1 + w4; //2195.42405790882 = adderArea(2,33)
assign Y[0] = w2_[39:8]; //BitwidthUsed(0, 24)
assign Y[1] = w0[39:8]; //BitwidthUsed(none)
assign Y[2] = w32_[39:8]; //BitwidthUsed(0, 28)
assign Y[3] = w0[39:8]; //BitwidthUsed(none)
assign Y[4] = w179_[39:8]; //BitwidthUsed(0, 31)
assign Y[5] = w0[39:8]; //BitwidthUsed(none)
assign Y[6] = w378_[39:8]; //BitwidthUsed(0, 31)
assign Y[7] = w0[39:8]; //BitwidthUsed(none)
//FIR_filter_firBlock_right_MultiplyBlock area estimate = 16402.4783787809;
endmodule //FIR_filter_firBlock_right_MultiplyBlock
module FIR_filter_firBlock_right (
X,
clk,
Y,
reset
);
// Port mode declarations:
input [31:0] X;
input clk;
output [31:0] Y;
input reset;
//registerOut
reg [31:0] Y;
wire [31:0] Y_in;
always@(posedge clk or negedge reset) begin
if(~reset) begin
Y <= 32'h00000000;
end else begin
Y <= Y_in;
end
end
wire [31:0] multProducts [0:7];
FIR_filter_firBlock_right_MultiplyBlock my_FIR_filter_firBlock_right_MultiplyBlock(
.X(X),
.Y1(multProducts[0]),
.Y2(multProducts[1]),
.Y3(multProducts[2]),
.Y4(multProducts[3]),
.Y5(multProducts[4]),
.Y6(multProducts[5]),
.Y7(multProducts[6]),
.Y8(multProducts[7])
);
reg [31:0] firStep[0:6];
always@(posedge clk or negedge reset) begin
if(~reset) begin
firStep[0] <= 32'h00000000;
firStep[1] <= 32'h00000000;
firStep[2] <= 32'h00000000;
firStep[3] <= 32'h00000000;
firStep[4] <= 32'h00000000;
firStep[5] <= 32'h00000000;
firStep[6] <= 32'h00000000;
end
else begin
firStep[0] <= multProducts[0]; // 2448.23046908235 = flop(0, 31)
firStep[1] <= firStep[0] + multProducts[1]; // 2448.23046908235 = flop(0, 31) + adder(none)
firStep[2] <= firStep[1] + multProducts[2]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[3] <= firStep[2] + multProducts[3]; // 2448.23046908235 = flop(0, 31) + adder(none)
firStep[4] <= firStep[3] + multProducts[4]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[5] <= firStep[4] + multProducts[5]; // 2448.23046908235 = flop(0, 31) + adder(none)
firStep[6] <= firStep[5] + multProducts[6]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
end
end
assign Y_in = firStep[6]+ multProducts[7];// 0 = adder(none)
//FIR_filter_firBlock_right area estimate = 42574.5943051662;
endmodule //FIR_filter_firBlock_right
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : fir_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-FIR core
//
module fir_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg next;
reg [31:0] dataX [0:31];
reg [31:0] dataY [0:31];
reg [5:0] xSel=6'b0;
reg [5:0] ySel=6'b0;
reg [5:0] count;
wire [31:0] dataIn, dataOut, data_Out;
reg [31:0] data_In_data, data_In_addr, data_Out_addr;
reg data_valid, data_In_write;
wire next_out;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i)
begin
if(wb_rst_i)
begin
next <= 0;
data_In_write <= 0;
data_In_addr <= 0;
data_In_data <= 0;
end
else if(wb_stb_i & wb_we_i)
case(wb_adr_i[5:2])
0:
next <= wb_dat_i[0];
1:
data_In_write <= wb_dat_i[0];
2:
data_In_addr <= wb_dat_i;
3:
data_In_data <= wb_dat_i;
4:
data_Out_addr <= wb_dat_i;
default:
;
endcase
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[5:2])
0:
wb_dat_o = {31'b0, next};
1:
wb_dat_o = {31'b0, data_In_write};
2:
wb_dat_o = data_In_addr;
3:
wb_dat_o = data_In_data;
4:
wb_dat_o = data_Out_addr;
5:
wb_dat_o = data_Out;
6:
wb_dat_o = {31'b0, data_valid};
default:
wb_dat_o = 32'b0;
endcase
end // always @ (*)
FIR_filter FIR_filter(
.clk(wb_clk_i),
.reset(~wb_rst_i),
.inData(dataIn),
.outData(dataOut));
reg data_In_write_r;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
data_In_write_r <= 0;
else
data_In_write_r <= data_In_write;
end
wire data_In_write_posedge = data_In_write & ~data_In_write_r;
reg [15:0] i;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
for (i = 0; i < 32; i = i + 1)
dataX[i] <= 0;
else
dataX[data_In_addr] <= data_In_data;
end
assign data_Out = dataY[data_Out_addr];
reg next_r;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
next_r <= 0;
else
next_r <= next;
end
wire next_posedge = next & ~next_r;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
xSel <= 0;
else if(next_posedge)
xSel <= 6'h00;
else if(xSel<6'b100000)
xSel <= xSel + 1;
end
assign dataIn = (xSel<6'b100000) ? dataX[xSel] : 32'b0;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
count <= 0;
else if(next_posedge)
begin
count <= 6'h00;
end
else if(xSel<4'b1010)
begin
count <= count +1;
end
end
assign next_out = (count == 4'b1000);
reg next_out_r;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
next_out_r <= 0;
else
next_out_r <= next_out;
end
wire next_out_posedge = next_out & ~next_out_r;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i) begin
ySel <= 0;
for (i = 0; i < 32; i = i + 1)
dataY[i] <= 0;
end else if(next_out_posedge)
begin
ySel <= 6'h00;
end
else if(ySel<6'b100000)
begin
ySel <= ySel +1;
dataY[ySel] = dataOut;
end
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
data_valid <= 0;
else if(next_posedge)
begin
data_valid <= 0;
end
else if(next_out_posedge)
begin
data_valid <= 1;
end
end
endmodule
|
/*
* This source file contains a Verilog description of an IP core
* automatically generated by the SPIRAL HDL Generator.
*
* This product includes a hardware design developed by Carnegie Mellon University.
*
* Copyright (c) 2005-2011 by Peter A. Milder for the SPIRAL Project,
* Carnegie Mellon University
*
* For more information, see the SPIRAL project website at:
* http://www.spiral.net
*
* This design is provided for internal, non-commercial research use only
* and is not for redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
// Input/output stream: 2 complex words per cycle
// Throughput: one transform every 32 cycles
// Latency: 332 cycles
// Resources required:
// 20 multipliers (16 x 16 bit)
// 34 adders (16 x 16 bit)
// 4 RAMs (16 words, 32 bits per word)
// 4 RAMs (8 words, 32 bits per word)
// 12 RAMs (64 words, 32 bits per word)
// 4 RAMs (32 words, 32 bits per word)
// 2 ROMs (32 words, 16 bits per word)
// 2 ROMs (8 words, 16 bits per word)
// 12 ROMs (32 words, 5 bits per word)
// 2 ROMs (16 words, 16 bits per word)
// Generated on Tue Sep 04 00:36:47 EDT 2018
// Latency: 332 clock cycles
// Throughput: 1 transform every 32 cycles
// We use an interleaved complex data format. X0 represents the
// real portion of the first input, and X1 represents the imaginary
// portion. The X variables are system inputs and the Y variables
// are system outputs.
// The design uses a system of flag signals to indicate the
// beginning of the input and output data streams. The 'next'
// input (asserted high), is used to instruct the system that the
// input stream will begin on the following cycle.
// This system has a 'gap' of 32 cycles. This means that
// 32 cycles must elapse between the beginning of the input
// vectors.
// The output signal 'next_out' (also asserted high) indicates
// that the output vector will begin streaming out of the system
// on the following cycle.
// The system has a latency of 332 cycles. This means that
// the 'next_out' will be asserted 332 cycles after the user
// asserts 'next'.
// The simple testbench below will demonstrate the timing for loading
// and unloading data vectors.
// The system reset signal is asserted high.
// Please note: when simulating floating point code, you must include
// Xilinx's DSP slice simulation module.
// Latency: 332
// Gap: 32
// module_name_is:dft_top
module idft_top(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [15:0] t0_0;
wire [15:0] t0_1;
wire [15:0] t0_2;
wire [15:0] t0_3;
wire next_0;
wire [15:0] t1_0;
wire [15:0] t1_1;
wire [15:0] t1_2;
wire [15:0] t1_3;
wire next_1;
wire [15:0] t2_0;
wire [15:0] t2_1;
wire [15:0] t2_2;
wire [15:0] t2_3;
wire next_2;
wire [15:0] t3_0;
wire [15:0] t3_1;
wire [15:0] t3_2;
wire [15:0] t3_3;
wire next_3;
wire [15:0] t4_0;
wire [15:0] t4_1;
wire [15:0] t4_2;
wire [15:0] t4_3;
wire next_4;
wire [15:0] t5_0;
wire [15:0] t5_1;
wire [15:0] t5_2;
wire [15:0] t5_3;
wire next_5;
wire [15:0] t6_0;
wire [15:0] t6_1;
wire [15:0] t6_2;
wire [15:0] t6_3;
wire next_6;
wire [15:0] t7_0;
wire [15:0] t7_1;
wire [15:0] t7_2;
wire [15:0] t7_3;
wire next_7;
wire [15:0] t8_0;
wire [15:0] t8_1;
wire [15:0] t8_2;
wire [15:0] t8_3;
wire next_8;
wire [15:0] t9_0;
wire [15:0] t9_1;
wire [15:0] t9_2;
wire [15:0] t9_3;
wire next_9;
wire [15:0] t10_0;
wire [15:0] t10_1;
wire [15:0] t10_2;
wire [15:0] t10_3;
wire next_10;
wire [15:0] t11_0;
wire [15:0] t11_1;
wire [15:0] t11_2;
wire [15:0] t11_3;
wire next_11;
wire [15:0] t12_0;
wire [15:0] t12_1;
wire [15:0] t12_2;
wire [15:0] t12_3;
wire next_12;
wire [15:0] t13_0;
wire [15:0] t13_1;
wire [15:0] t13_2;
wire [15:0] t13_3;
wire next_13;
wire [15:0] t14_0;
wire [15:0] t14_1;
wire [15:0] t14_2;
wire [15:0] t14_3;
wire next_14;
wire [15:0] t15_0;
wire [15:0] t15_1;
wire [15:0] t15_2;
wire [15:0] t15_3;
wire next_15;
wire [15:0] t16_0;
wire [15:0] t16_1;
wire [15:0] t16_2;
wire [15:0] t16_3;
wire next_16;
wire [15:0] t17_0;
wire [15:0] t17_1;
wire [15:0] t17_2;
wire [15:0] t17_3;
wire next_17;
wire [15:0] t18_0;
wire [15:0] t18_1;
wire [15:0] t18_2;
wire [15:0] t18_3;
wire next_18;
assign t0_0 = X0;
assign Y0 = t18_0;
assign t0_1 = X1;
assign Y1 = t18_1;
assign t0_2 = X2;
assign Y2 = t18_2;
assign t0_3 = X3;
assign Y3 = t18_3;
assign next_0 = next;
assign next_out = next_18;
// latency=68, gap=32
rc7079 stage0(.clk(clk), .reset(reset), .next(next_0), .next_out(next_1),
.X0(t0_0), .Y0(t1_0),
.X1(t0_1), .Y1(t1_1),
.X2(t0_2), .Y2(t1_2),
.X3(t0_3), .Y3(t1_3));
// latency=2, gap=32
codeBlock7081 stage1(.clk(clk), .reset(reset), .next_in(next_1), .next_out(next_2),
.X0_in(t1_0), .Y0(t2_0),
.X1_in(t1_1), .Y1(t2_1),
.X2_in(t1_2), .Y2(t2_2),
.X3_in(t1_3), .Y3(t2_3));
// latency=8, gap=32
rc7163 stage2(.clk(clk), .reset(reset), .next(next_2), .next_out(next_3),
.X0(t2_0), .Y0(t3_0),
.X1(t2_1), .Y1(t3_1),
.X2(t2_2), .Y2(t3_2),
.X3(t2_3), .Y3(t3_3));
// latency=8, gap=32
DirSum_7344 stage3(.next(next_3), .clk(clk), .reset(reset), .next_out(next_4),
.X0(t3_0), .Y0(t4_0),
.X1(t3_1), .Y1(t4_1),
.X2(t3_2), .Y2(t4_2),
.X3(t3_3), .Y3(t4_3));
// latency=2, gap=32
codeBlock7347 stage4(.clk(clk), .reset(reset), .next_in(next_4), .next_out(next_5),
.X0_in(t4_0), .Y0(t5_0),
.X1_in(t4_1), .Y1(t5_1),
.X2_in(t4_2), .Y2(t5_2),
.X3_in(t4_3), .Y3(t5_3));
// latency=12, gap=32
rc7429 stage5(.clk(clk), .reset(reset), .next(next_5), .next_out(next_6),
.X0(t5_0), .Y0(t6_0),
.X1(t5_1), .Y1(t6_1),
.X2(t5_2), .Y2(t6_2),
.X3(t5_3), .Y3(t6_3));
// latency=8, gap=32
DirSum_7618 stage6(.next(next_6), .clk(clk), .reset(reset), .next_out(next_7),
.X0(t6_0), .Y0(t7_0),
.X1(t6_1), .Y1(t7_1),
.X2(t6_2), .Y2(t7_2),
.X3(t6_3), .Y3(t7_3));
// latency=2, gap=32
codeBlock7621 stage7(.clk(clk), .reset(reset), .next_in(next_7), .next_out(next_8),
.X0_in(t7_0), .Y0(t8_0),
.X1_in(t7_1), .Y1(t8_1),
.X2_in(t7_2), .Y2(t8_2),
.X3_in(t7_3), .Y3(t8_3));
// latency=20, gap=32
rc7703 stage8(.clk(clk), .reset(reset), .next(next_8), .next_out(next_9),
.X0(t8_0), .Y0(t9_0),
.X1(t8_1), .Y1(t9_1),
.X2(t8_2), .Y2(t9_2),
.X3(t8_3), .Y3(t9_3));
// latency=8, gap=32
DirSum_7908 stage9(.next(next_9), .clk(clk), .reset(reset), .next_out(next_10),
.X0(t9_0), .Y0(t10_0),
.X1(t9_1), .Y1(t10_1),
.X2(t9_2), .Y2(t10_2),
.X3(t9_3), .Y3(t10_3));
// latency=2, gap=32
codeBlock7911 stage10(.clk(clk), .reset(reset), .next_in(next_10), .next_out(next_11),
.X0_in(t10_0), .Y0(t11_0),
.X1_in(t10_1), .Y1(t11_1),
.X2_in(t10_2), .Y2(t11_2),
.X3_in(t10_3), .Y3(t11_3));
// latency=36, gap=32
rc7993 stage11(.clk(clk), .reset(reset), .next(next_11), .next_out(next_12),
.X0(t11_0), .Y0(t12_0),
.X1(t11_1), .Y1(t12_1),
.X2(t11_2), .Y2(t12_2),
.X3(t11_3), .Y3(t12_3));
// latency=8, gap=32
DirSum_8230 stage12(.next(next_12), .clk(clk), .reset(reset), .next_out(next_13),
.X0(t12_0), .Y0(t13_0),
.X1(t12_1), .Y1(t13_1),
.X2(t12_2), .Y2(t13_2),
.X3(t12_3), .Y3(t13_3));
// latency=2, gap=32
codeBlock8233 stage13(.clk(clk), .reset(reset), .next_in(next_13), .next_out(next_14),
.X0_in(t13_0), .Y0(t14_0),
.X1_in(t13_1), .Y1(t14_1),
.X2_in(t13_2), .Y2(t14_2),
.X3_in(t13_3), .Y3(t14_3));
// latency=68, gap=32
rc8315 stage14(.clk(clk), .reset(reset), .next(next_14), .next_out(next_15),
.X0(t14_0), .Y0(t15_0),
.X1(t14_1), .Y1(t15_1),
.X2(t14_2), .Y2(t15_2),
.X3(t14_3), .Y3(t15_3));
// latency=8, gap=32
DirSum_8615 stage15(.next(next_15), .clk(clk), .reset(reset), .next_out(next_16),
.X0(t15_0), .Y0(t16_0),
.X1(t15_1), .Y1(t16_1),
.X2(t15_2), .Y2(t16_2),
.X3(t15_3), .Y3(t16_3));
// latency=2, gap=32
codeBlock8618 stage16(.clk(clk), .reset(reset), .next_in(next_16), .next_out(next_17),
.X0_in(t16_0), .Y0(t17_0),
.X1_in(t16_1), .Y1(t17_1),
.X2_in(t16_2), .Y2(t17_2),
.X3_in(t16_3), .Y3(t17_3));
// latency=68, gap=32
rc8700 stage17(.clk(clk), .reset(reset), .next(next_17), .next_out(next_18),
.X0(t17_0), .Y0(t18_0),
.X1(t17_1), .Y1(t18_1),
.X2(t17_2), .Y2(t18_2),
.X3(t17_3), .Y3(t18_3));
endmodule
// Latency: 68
// Gap: 32
module rc7079(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm7077 instPerm9645(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet7077(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm7077(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter addrbits = 5;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm0;
assign tm0 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_9650(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9651(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(31, 5) nextReg_9662(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_9663(.X(next2), .Y(next3), .clk(clk));
nextReg #(32, 5) nextReg_9666(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9667(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(31, 1) shiftFIFO_9670(.X(tm0), .Y(tm0_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_9673(.X(tm0_d), .Y(tm0_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 5) shiftFIFO_9678(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm0_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 16;
{1'd0, 5'd1}: s1rd0 <= 24;
{1'd0, 5'd2}: s1rd0 <= 20;
{1'd0, 5'd3}: s1rd0 <= 28;
{1'd0, 5'd4}: s1rd0 <= 18;
{1'd0, 5'd5}: s1rd0 <= 26;
{1'd0, 5'd6}: s1rd0 <= 22;
{1'd0, 5'd7}: s1rd0 <= 30;
{1'd0, 5'd8}: s1rd0 <= 17;
{1'd0, 5'd9}: s1rd0 <= 25;
{1'd0, 5'd10}: s1rd0 <= 21;
{1'd0, 5'd11}: s1rd0 <= 29;
{1'd0, 5'd12}: s1rd0 <= 19;
{1'd0, 5'd13}: s1rd0 <= 27;
{1'd0, 5'd14}: s1rd0 <= 23;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 8;
{1'd0, 5'd18}: s1rd0 <= 4;
{1'd0, 5'd19}: s1rd0 <= 12;
{1'd0, 5'd20}: s1rd0 <= 2;
{1'd0, 5'd21}: s1rd0 <= 10;
{1'd0, 5'd22}: s1rd0 <= 6;
{1'd0, 5'd23}: s1rd0 <= 14;
{1'd0, 5'd24}: s1rd0 <= 1;
{1'd0, 5'd25}: s1rd0 <= 9;
{1'd0, 5'd26}: s1rd0 <= 5;
{1'd0, 5'd27}: s1rd0 <= 13;
{1'd0, 5'd28}: s1rd0 <= 3;
{1'd0, 5'd29}: s1rd0 <= 11;
{1'd0, 5'd30}: s1rd0 <= 7;
{1'd0, 5'd31}: s1rd0 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm0_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 8;
{1'd0, 5'd2}: s1rd1 <= 4;
{1'd0, 5'd3}: s1rd1 <= 12;
{1'd0, 5'd4}: s1rd1 <= 2;
{1'd0, 5'd5}: s1rd1 <= 10;
{1'd0, 5'd6}: s1rd1 <= 6;
{1'd0, 5'd7}: s1rd1 <= 14;
{1'd0, 5'd8}: s1rd1 <= 1;
{1'd0, 5'd9}: s1rd1 <= 9;
{1'd0, 5'd10}: s1rd1 <= 5;
{1'd0, 5'd11}: s1rd1 <= 13;
{1'd0, 5'd12}: s1rd1 <= 3;
{1'd0, 5'd13}: s1rd1 <= 11;
{1'd0, 5'd14}: s1rd1 <= 7;
{1'd0, 5'd15}: s1rd1 <= 15;
{1'd0, 5'd16}: s1rd1 <= 16;
{1'd0, 5'd17}: s1rd1 <= 24;
{1'd0, 5'd18}: s1rd1 <= 20;
{1'd0, 5'd19}: s1rd1 <= 28;
{1'd0, 5'd20}: s1rd1 <= 18;
{1'd0, 5'd21}: s1rd1 <= 26;
{1'd0, 5'd22}: s1rd1 <= 22;
{1'd0, 5'd23}: s1rd1 <= 30;
{1'd0, 5'd24}: s1rd1 <= 17;
{1'd0, 5'd25}: s1rd1 <= 25;
{1'd0, 5'd26}: s1rd1 <= 21;
{1'd0, 5'd27}: s1rd1 <= 29;
{1'd0, 5'd28}: s1rd1 <= 19;
{1'd0, 5'd29}: s1rd1 <= 27;
{1'd0, 5'd30}: s1rd1 <= 23;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet7077 sw(tm0_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm0_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm0_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
module memMod(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is block
reg [width-1:0] mem[depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule
module memMod_dist(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is distributed
reg [width-1:0] mem[depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule
module shiftRegFIFO(X, Y, clk);
parameter depth=1, width=1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @ (posedge clk) begin
for(index=1;index<depth;index=index+1) begin
mem[index] <= mem[index-1];
end
mem[0]<=X;
end
endmodule
module nextReg(X, Y, reset, clk);
parameter depth=2, logDepth=1;
output Y;
input X;
input clk, reset;
reg [logDepth:0] count;
reg active;
assign Y = (count == depth) ? 1 : 0;
always @ (posedge clk) begin
if (reset == 1) begin
count <= 0;
active <= 0;
end
else if (X == 1) begin
active <= 1;
count <= 1;
end
else if (count == depth) begin
count <= 0;
active <= 0;
end
else if (active)
count <= count+1;
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock7081(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_9685(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a309;
wire signed [15:0] a310;
wire signed [15:0] a311;
wire signed [15:0] a312;
wire signed [15:0] t141;
wire signed [15:0] t142;
wire signed [15:0] t143;
wire signed [15:0] t144;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a309 = X0;
assign a310 = X2;
assign a311 = X1;
assign a312 = X3;
assign Y0 = t141;
assign Y1 = t142;
assign Y2 = t143;
assign Y3 = t144;
addfxp #(16, 1) add7093(.a(a309), .b(a310), .clk(clk), .q(t141)); // 0
addfxp #(16, 1) add7108(.a(a311), .b(a312), .clk(clk), .q(t142)); // 0
subfxp #(16, 1) sub7123(.a(a309), .b(a310), .clk(clk), .q(t143)); // 0
subfxp #(16, 1) sub7138(.a(a311), .b(a312), .clk(clk), .q(t144)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 8
// Gap: 2
module rc7163(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm7161 instPerm9686(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet7161(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [0:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
1'd0: control <= 1'b1;
1'd1: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 8
// Gap: 2
module perm7161(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 2;
parameter addrbits = 1;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm1;
assign tm1 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_9691(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9692(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
shiftRegFIFO #(1, 1) shiftFIFO_9701(.X(next), .Y(next2), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_9702(.X(next2), .Y(next3), .clk(clk));
shiftRegFIFO #(2, 1) shiftFIFO_9703(.X(next3), .Y(next4), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9704(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9707(.X(tm1), .Y(tm1_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_9710(.X(tm1_d), .Y(tm1_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 1) shiftFIFO_9715(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm1_d, s1rdloc})
{1'd0, 1'd0}: s1rd0 <= 1;
{1'd0, 1'd1}: s1rd0 <= 0;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm1_d, s1rdloc})
{1'd0, 1'd0}: s1rd1 <= 0;
{1'd0, 1'd1}: s1rd1 <= 1;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet7161 sw(tm1_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm1_dd, writeCycle})
{1'd0, 1'd0}: s2wr0 <= 1;
{1'd0, 1'd1}: s2wr0 <= 0;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm1_dd, writeCycle})
{1'd0, 1'd0}: s2wr1 <= 0;
{1'd0, 1'd1}: s2wr1 <= 1;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 2
module DirSum_7344(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [0:0] i5;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i5 <= 0;
end
else begin
if (next == 1)
i5 <= 0;
else if (i5 == 1)
i5 <= 0;
else
i5 <= i5 + 1;
end
end
codeBlock7166 codeBlockIsnt9716(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i5_in(i5),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D18_7334(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h0;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D20_7342(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'h4000;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock7166(clk, reset, next_in, next_out,
i5_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [0:0] i5_in;
reg [0:0] i5;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_9719(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a293;
wire signed [15:0] a282;
wire signed [15:0] a296;
wire signed [15:0] a286;
wire signed [15:0] a297;
wire signed [15:0] a298;
reg signed [15:0] tm137;
reg signed [15:0] tm141;
reg signed [15:0] tm153;
reg signed [15:0] tm160;
reg signed [15:0] tm138;
reg signed [15:0] tm142;
reg signed [15:0] tm154;
reg signed [15:0] tm161;
wire signed [15:0] tm4;
wire signed [15:0] a287;
wire signed [15:0] tm5;
wire signed [15:0] a289;
reg signed [15:0] tm139;
reg signed [15:0] tm143;
reg signed [15:0] tm155;
reg signed [15:0] tm162;
reg signed [15:0] tm31;
reg signed [15:0] tm32;
reg signed [15:0] tm140;
reg signed [15:0] tm144;
reg signed [15:0] tm156;
reg signed [15:0] tm163;
reg signed [15:0] tm157;
reg signed [15:0] tm164;
wire signed [15:0] a288;
wire signed [15:0] a290;
wire signed [15:0] a291;
wire signed [15:0] a292;
reg signed [15:0] tm158;
reg signed [15:0] tm165;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm159;
reg signed [15:0] tm166;
assign a293 = X0;
assign a282 = a293;
assign a296 = X1;
assign a286 = a296;
assign a297 = X2;
assign a298 = X3;
assign a287 = tm4;
assign a289 = tm5;
assign Y0 = tm159;
assign Y1 = tm166;
D18_7334 instD18inst0_7334(.addr(i5[0:0]), .out(tm4), .clk(clk));
D20_7342 instD20inst0_7342(.addr(i5[0:0]), .out(tm5), .clk(clk));
multfix #(16, 2) m7265(.a(tm31), .b(tm140), .clk(clk), .q_sc(a288), .q_unsc(), .rst(reset));
multfix #(16, 2) m7287(.a(tm32), .b(tm144), .clk(clk), .q_sc(a290), .q_unsc(), .rst(reset));
multfix #(16, 2) m7305(.a(tm32), .b(tm140), .clk(clk), .q_sc(a291), .q_unsc(), .rst(reset));
multfix #(16, 2) m7316(.a(tm31), .b(tm144), .clk(clk), .q_sc(a292), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub7294(.a(a288), .b(a290), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add7323(.a(a291), .b(a292), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm31 <= 0;
tm140 <= 0;
tm32 <= 0;
tm144 <= 0;
tm32 <= 0;
tm140 <= 0;
tm31 <= 0;
tm144 <= 0;
end
else begin
i5 <= i5_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm137 <= a297;
tm141 <= a298;
tm153 <= a282;
tm160 <= a286;
tm138 <= tm137;
tm142 <= tm141;
tm154 <= tm153;
tm161 <= tm160;
tm139 <= tm138;
tm143 <= tm142;
tm155 <= tm154;
tm162 <= tm161;
tm31 <= a287;
tm32 <= a289;
tm140 <= tm139;
tm144 <= tm143;
tm156 <= tm155;
tm163 <= tm162;
tm157 <= tm156;
tm164 <= tm163;
tm158 <= tm157;
tm165 <= tm164;
tm159 <= tm158;
tm166 <= tm165;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock7347(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_9722(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a249;
wire signed [15:0] a250;
wire signed [15:0] a251;
wire signed [15:0] a252;
wire signed [15:0] t117;
wire signed [15:0] t118;
wire signed [15:0] t119;
wire signed [15:0] t120;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a249 = X0;
assign a250 = X2;
assign a251 = X1;
assign a252 = X3;
assign Y0 = t117;
assign Y1 = t118;
assign Y2 = t119;
assign Y3 = t120;
addfxp #(16, 1) add7359(.a(a249), .b(a250), .clk(clk), .q(t117)); // 0
addfxp #(16, 1) add7374(.a(a251), .b(a252), .clk(clk), .q(t118)); // 0
subfxp #(16, 1) sub7389(.a(a249), .b(a250), .clk(clk), .q(t119)); // 0
subfxp #(16, 1) sub7404(.a(a251), .b(a252), .clk(clk), .q(t120)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 12
// Gap: 4
module rc7429(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm7427 instPerm9723(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet7427(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [1:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
2'd0: control <= 1'b1;
2'd1: control <= 1'b1;
2'd2: control <= 1'b0;
2'd3: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 12
// Gap: 4
module perm7427(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 4;
parameter addrbits = 2;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm6;
assign tm6 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_9728(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9729(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
shiftRegFIFO #(3, 1) shiftFIFO_9738(.X(next), .Y(next2), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_9739(.X(next2), .Y(next3), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_9740(.X(next3), .Y(next4), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9741(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_9744(.X(tm6), .Y(tm6_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_9747(.X(tm6_d), .Y(tm6_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 2) shiftFIFO_9752(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm6_d, s1rdloc})
{1'd0, 2'd0}: s1rd0 <= 2;
{1'd0, 2'd1}: s1rd0 <= 3;
{1'd0, 2'd2}: s1rd0 <= 0;
{1'd0, 2'd3}: s1rd0 <= 1;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm6_d, s1rdloc})
{1'd0, 2'd0}: s1rd1 <= 0;
{1'd0, 2'd1}: s1rd1 <= 1;
{1'd0, 2'd2}: s1rd1 <= 2;
{1'd0, 2'd3}: s1rd1 <= 3;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet7427 sw(tm6_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm6_dd, writeCycle})
{1'd0, 2'd0}: s2wr0 <= 2;
{1'd0, 2'd1}: s2wr0 <= 3;
{1'd0, 2'd2}: s2wr0 <= 0;
{1'd0, 2'd3}: s2wr0 <= 1;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm6_dd, writeCycle})
{1'd0, 2'd0}: s2wr1 <= 0;
{1'd0, 2'd1}: s2wr1 <= 1;
{1'd0, 2'd2}: s2wr1 <= 2;
{1'd0, 2'd3}: s2wr1 <= 3;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 4
module DirSum_7618(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [1:0] i4;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i4 <= 0;
end
else begin
if (next == 1)
i4 <= 0;
else if (i4 == 3)
i4 <= 0;
else
i4 <= i4 + 1;
end
end
codeBlock7432 codeBlockIsnt9753(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i4_in(i4),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D14_7604(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h2d41;
2: out3 <= 16'h0;
3: out3 <= 16'hd2bf;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D16_7616(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'h2d41;
2: out3 <= 16'h4000;
3: out3 <= 16'h2d41;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock7432(clk, reset, next_in, next_out,
i4_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [1:0] i4_in;
reg [1:0] i4;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_9756(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a233;
wire signed [15:0] a222;
wire signed [15:0] a236;
wire signed [15:0] a226;
wire signed [15:0] a237;
wire signed [15:0] a238;
reg signed [15:0] tm167;
reg signed [15:0] tm171;
reg signed [15:0] tm183;
reg signed [15:0] tm190;
reg signed [15:0] tm168;
reg signed [15:0] tm172;
reg signed [15:0] tm184;
reg signed [15:0] tm191;
wire signed [15:0] tm9;
wire signed [15:0] a227;
wire signed [15:0] tm10;
wire signed [15:0] a229;
reg signed [15:0] tm169;
reg signed [15:0] tm173;
reg signed [15:0] tm185;
reg signed [15:0] tm192;
reg signed [15:0] tm39;
reg signed [15:0] tm40;
reg signed [15:0] tm170;
reg signed [15:0] tm174;
reg signed [15:0] tm186;
reg signed [15:0] tm193;
reg signed [15:0] tm187;
reg signed [15:0] tm194;
wire signed [15:0] a228;
wire signed [15:0] a230;
wire signed [15:0] a231;
wire signed [15:0] a232;
reg signed [15:0] tm188;
reg signed [15:0] tm195;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm189;
reg signed [15:0] tm196;
assign a233 = X0;
assign a222 = a233;
assign a236 = X1;
assign a226 = a236;
assign a237 = X2;
assign a238 = X3;
assign a227 = tm9;
assign a229 = tm10;
assign Y0 = tm189;
assign Y1 = tm196;
D14_7604 instD14inst0_7604(.addr(i4[1:0]), .out(tm9), .clk(clk));
D16_7616 instD16inst0_7616(.addr(i4[1:0]), .out(tm10), .clk(clk));
multfix #(16, 2) m7531(.a(tm39), .b(tm170), .clk(clk), .q_sc(a228), .q_unsc(), .rst(reset));
multfix #(16, 2) m7553(.a(tm40), .b(tm174), .clk(clk), .q_sc(a230), .q_unsc(), .rst(reset));
multfix #(16, 2) m7571(.a(tm40), .b(tm170), .clk(clk), .q_sc(a231), .q_unsc(), .rst(reset));
multfix #(16, 2) m7582(.a(tm39), .b(tm174), .clk(clk), .q_sc(a232), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub7560(.a(a228), .b(a230), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add7589(.a(a231), .b(a232), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm39 <= 0;
tm170 <= 0;
tm40 <= 0;
tm174 <= 0;
tm40 <= 0;
tm170 <= 0;
tm39 <= 0;
tm174 <= 0;
end
else begin
i4 <= i4_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm167 <= a237;
tm171 <= a238;
tm183 <= a222;
tm190 <= a226;
tm168 <= tm167;
tm172 <= tm171;
tm184 <= tm183;
tm191 <= tm190;
tm169 <= tm168;
tm173 <= tm172;
tm185 <= tm184;
tm192 <= tm191;
tm39 <= a227;
tm40 <= a229;
tm170 <= tm169;
tm174 <= tm173;
tm186 <= tm185;
tm193 <= tm192;
tm187 <= tm186;
tm194 <= tm193;
tm188 <= tm187;
tm195 <= tm194;
tm189 <= tm188;
tm196 <= tm195;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock7621(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_9759(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a189;
wire signed [15:0] a190;
wire signed [15:0] a191;
wire signed [15:0] a192;
wire signed [15:0] t93;
wire signed [15:0] t94;
wire signed [15:0] t95;
wire signed [15:0] t96;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a189 = X0;
assign a190 = X2;
assign a191 = X1;
assign a192 = X3;
assign Y0 = t93;
assign Y1 = t94;
assign Y2 = t95;
assign Y3 = t96;
addfxp #(16, 1) add7633(.a(a189), .b(a190), .clk(clk), .q(t93)); // 0
addfxp #(16, 1) add7648(.a(a191), .b(a192), .clk(clk), .q(t94)); // 0
subfxp #(16, 1) sub7663(.a(a189), .b(a190), .clk(clk), .q(t95)); // 0
subfxp #(16, 1) sub7678(.a(a191), .b(a192), .clk(clk), .q(t96)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 20
// Gap: 8
module rc7703(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm7701 instPerm9760(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet7701(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [2:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
3'd0: control <= 1'b1;
3'd1: control <= 1'b1;
3'd2: control <= 1'b1;
3'd3: control <= 1'b1;
3'd4: control <= 1'b0;
3'd5: control <= 1'b0;
3'd6: control <= 1'b0;
3'd7: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 20
// Gap: 8
module perm7701(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 8;
parameter addrbits = 3;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm11;
assign tm11 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_9765(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9766(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
shiftRegFIFO #(7, 1) shiftFIFO_9775(.X(next), .Y(next2), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_9776(.X(next2), .Y(next3), .clk(clk));
shiftRegFIFO #(8, 1) shiftFIFO_9777(.X(next3), .Y(next4), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9778(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(7, 1) shiftFIFO_9781(.X(tm11), .Y(tm11_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_9784(.X(tm11_d), .Y(tm11_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 3) shiftFIFO_9789(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm11_d, s1rdloc})
{1'd0, 3'd0}: s1rd0 <= 4;
{1'd0, 3'd1}: s1rd0 <= 5;
{1'd0, 3'd2}: s1rd0 <= 6;
{1'd0, 3'd3}: s1rd0 <= 7;
{1'd0, 3'd4}: s1rd0 <= 0;
{1'd0, 3'd5}: s1rd0 <= 1;
{1'd0, 3'd6}: s1rd0 <= 2;
{1'd0, 3'd7}: s1rd0 <= 3;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm11_d, s1rdloc})
{1'd0, 3'd0}: s1rd1 <= 0;
{1'd0, 3'd1}: s1rd1 <= 1;
{1'd0, 3'd2}: s1rd1 <= 2;
{1'd0, 3'd3}: s1rd1 <= 3;
{1'd0, 3'd4}: s1rd1 <= 4;
{1'd0, 3'd5}: s1rd1 <= 5;
{1'd0, 3'd6}: s1rd1 <= 6;
{1'd0, 3'd7}: s1rd1 <= 7;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet7701 sw(tm11_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm11_dd, writeCycle})
{1'd0, 3'd0}: s2wr0 <= 4;
{1'd0, 3'd1}: s2wr0 <= 5;
{1'd0, 3'd2}: s2wr0 <= 6;
{1'd0, 3'd3}: s2wr0 <= 7;
{1'd0, 3'd4}: s2wr0 <= 0;
{1'd0, 3'd5}: s2wr0 <= 1;
{1'd0, 3'd6}: s2wr0 <= 2;
{1'd0, 3'd7}: s2wr0 <= 3;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm11_dd, writeCycle})
{1'd0, 3'd0}: s2wr1 <= 0;
{1'd0, 3'd1}: s2wr1 <= 1;
{1'd0, 3'd2}: s2wr1 <= 2;
{1'd0, 3'd3}: s2wr1 <= 3;
{1'd0, 3'd4}: s2wr1 <= 4;
{1'd0, 3'd5}: s2wr1 <= 5;
{1'd0, 3'd6}: s2wr1 <= 6;
{1'd0, 3'd7}: s2wr1 <= 7;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 8
module DirSum_7908(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [2:0] i3;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i3 <= 0;
end
else begin
if (next == 1)
i3 <= 0;
else if (i3 == 7)
i3 <= 0;
else
i3 <= i3 + 1;
end
end
codeBlock7706 codeBlockIsnt9790(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i3_in(i3),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D10_7886(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [2:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3b21;
2: out3 <= 16'h2d41;
3: out3 <= 16'h187e;
4: out3 <= 16'h0;
5: out3 <= 16'he782;
6: out3 <= 16'hd2bf;
7: out3 <= 16'hc4df;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D12_7906(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [2:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'h187e;
2: out3 <= 16'h2d41;
3: out3 <= 16'h3b21;
4: out3 <= 16'h4000;
5: out3 <= 16'h3b21;
6: out3 <= 16'h2d41;
7: out3 <= 16'h187e;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock7706(clk, reset, next_in, next_out,
i3_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [2:0] i3_in;
reg [2:0] i3;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_9793(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a173;
wire signed [15:0] a162;
wire signed [15:0] a176;
wire signed [15:0] a166;
wire signed [15:0] a177;
wire signed [15:0] a178;
reg signed [15:0] tm197;
reg signed [15:0] tm201;
reg signed [15:0] tm213;
reg signed [15:0] tm220;
reg signed [15:0] tm198;
reg signed [15:0] tm202;
reg signed [15:0] tm214;
reg signed [15:0] tm221;
wire signed [15:0] tm14;
wire signed [15:0] a167;
wire signed [15:0] tm15;
wire signed [15:0] a169;
reg signed [15:0] tm199;
reg signed [15:0] tm203;
reg signed [15:0] tm215;
reg signed [15:0] tm222;
reg signed [15:0] tm47;
reg signed [15:0] tm48;
reg signed [15:0] tm200;
reg signed [15:0] tm204;
reg signed [15:0] tm216;
reg signed [15:0] tm223;
reg signed [15:0] tm217;
reg signed [15:0] tm224;
wire signed [15:0] a168;
wire signed [15:0] a170;
wire signed [15:0] a171;
wire signed [15:0] a172;
reg signed [15:0] tm218;
reg signed [15:0] tm225;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm219;
reg signed [15:0] tm226;
assign a173 = X0;
assign a162 = a173;
assign a176 = X1;
assign a166 = a176;
assign a177 = X2;
assign a178 = X3;
assign a167 = tm14;
assign a169 = tm15;
assign Y0 = tm219;
assign Y1 = tm226;
D10_7886 instD10inst0_7886(.addr(i3[2:0]), .out(tm14), .clk(clk));
D12_7906 instD12inst0_7906(.addr(i3[2:0]), .out(tm15), .clk(clk));
multfix #(16, 2) m7805(.a(tm47), .b(tm200), .clk(clk), .q_sc(a168), .q_unsc(), .rst(reset));
multfix #(16, 2) m7827(.a(tm48), .b(tm204), .clk(clk), .q_sc(a170), .q_unsc(), .rst(reset));
multfix #(16, 2) m7845(.a(tm48), .b(tm200), .clk(clk), .q_sc(a171), .q_unsc(), .rst(reset));
multfix #(16, 2) m7856(.a(tm47), .b(tm204), .clk(clk), .q_sc(a172), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub7834(.a(a168), .b(a170), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add7863(.a(a171), .b(a172), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm47 <= 0;
tm200 <= 0;
tm48 <= 0;
tm204 <= 0;
tm48 <= 0;
tm200 <= 0;
tm47 <= 0;
tm204 <= 0;
end
else begin
i3 <= i3_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm197 <= a177;
tm201 <= a178;
tm213 <= a162;
tm220 <= a166;
tm198 <= tm197;
tm202 <= tm201;
tm214 <= tm213;
tm221 <= tm220;
tm199 <= tm198;
tm203 <= tm202;
tm215 <= tm214;
tm222 <= tm221;
tm47 <= a167;
tm48 <= a169;
tm200 <= tm199;
tm204 <= tm203;
tm216 <= tm215;
tm223 <= tm222;
tm217 <= tm216;
tm224 <= tm223;
tm218 <= tm217;
tm225 <= tm224;
tm219 <= tm218;
tm226 <= tm225;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock7911(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_9796(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a129;
wire signed [15:0] a130;
wire signed [15:0] a131;
wire signed [15:0] a132;
wire signed [15:0] t69;
wire signed [15:0] t70;
wire signed [15:0] t71;
wire signed [15:0] t72;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a129 = X0;
assign a130 = X2;
assign a131 = X1;
assign a132 = X3;
assign Y0 = t69;
assign Y1 = t70;
assign Y2 = t71;
assign Y3 = t72;
addfxp #(16, 1) add7923(.a(a129), .b(a130), .clk(clk), .q(t69)); // 0
addfxp #(16, 1) add7938(.a(a131), .b(a132), .clk(clk), .q(t70)); // 0
subfxp #(16, 1) sub7953(.a(a129), .b(a130), .clk(clk), .q(t71)); // 0
subfxp #(16, 1) sub7968(.a(a131), .b(a132), .clk(clk), .q(t72)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 36
// Gap: 16
module rc7993(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm7991 instPerm9797(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet7991(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [3:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
4'd0: control <= 1'b1;
4'd1: control <= 1'b1;
4'd2: control <= 1'b1;
4'd3: control <= 1'b1;
4'd4: control <= 1'b1;
4'd5: control <= 1'b1;
4'd6: control <= 1'b1;
4'd7: control <= 1'b1;
4'd8: control <= 1'b0;
4'd9: control <= 1'b0;
4'd10: control <= 1'b0;
4'd11: control <= 1'b0;
4'd12: control <= 1'b0;
4'd13: control <= 1'b0;
4'd14: control <= 1'b0;
4'd15: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 36
// Gap: 16
module perm7991(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 16;
parameter addrbits = 4;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm16;
assign tm16 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_9802(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9803(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(15, 4) nextReg_9814(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_9815(.X(next2), .Y(next3), .clk(clk));
nextReg #(16, 4) nextReg_9818(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9819(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(15, 1) shiftFIFO_9822(.X(tm16), .Y(tm16_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_9825(.X(tm16_d), .Y(tm16_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 4) shiftFIFO_9830(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm16_d, s1rdloc})
{1'd0, 4'd0}: s1rd0 <= 8;
{1'd0, 4'd1}: s1rd0 <= 9;
{1'd0, 4'd2}: s1rd0 <= 10;
{1'd0, 4'd3}: s1rd0 <= 11;
{1'd0, 4'd4}: s1rd0 <= 12;
{1'd0, 4'd5}: s1rd0 <= 13;
{1'd0, 4'd6}: s1rd0 <= 14;
{1'd0, 4'd7}: s1rd0 <= 15;
{1'd0, 4'd8}: s1rd0 <= 0;
{1'd0, 4'd9}: s1rd0 <= 1;
{1'd0, 4'd10}: s1rd0 <= 2;
{1'd0, 4'd11}: s1rd0 <= 3;
{1'd0, 4'd12}: s1rd0 <= 4;
{1'd0, 4'd13}: s1rd0 <= 5;
{1'd0, 4'd14}: s1rd0 <= 6;
{1'd0, 4'd15}: s1rd0 <= 7;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm16_d, s1rdloc})
{1'd0, 4'd0}: s1rd1 <= 0;
{1'd0, 4'd1}: s1rd1 <= 1;
{1'd0, 4'd2}: s1rd1 <= 2;
{1'd0, 4'd3}: s1rd1 <= 3;
{1'd0, 4'd4}: s1rd1 <= 4;
{1'd0, 4'd5}: s1rd1 <= 5;
{1'd0, 4'd6}: s1rd1 <= 6;
{1'd0, 4'd7}: s1rd1 <= 7;
{1'd0, 4'd8}: s1rd1 <= 8;
{1'd0, 4'd9}: s1rd1 <= 9;
{1'd0, 4'd10}: s1rd1 <= 10;
{1'd0, 4'd11}: s1rd1 <= 11;
{1'd0, 4'd12}: s1rd1 <= 12;
{1'd0, 4'd13}: s1rd1 <= 13;
{1'd0, 4'd14}: s1rd1 <= 14;
{1'd0, 4'd15}: s1rd1 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet7991 sw(tm16_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm16_dd, writeCycle})
{1'd0, 4'd0}: s2wr0 <= 8;
{1'd0, 4'd1}: s2wr0 <= 9;
{1'd0, 4'd2}: s2wr0 <= 10;
{1'd0, 4'd3}: s2wr0 <= 11;
{1'd0, 4'd4}: s2wr0 <= 12;
{1'd0, 4'd5}: s2wr0 <= 13;
{1'd0, 4'd6}: s2wr0 <= 14;
{1'd0, 4'd7}: s2wr0 <= 15;
{1'd0, 4'd8}: s2wr0 <= 0;
{1'd0, 4'd9}: s2wr0 <= 1;
{1'd0, 4'd10}: s2wr0 <= 2;
{1'd0, 4'd11}: s2wr0 <= 3;
{1'd0, 4'd12}: s2wr0 <= 4;
{1'd0, 4'd13}: s2wr0 <= 5;
{1'd0, 4'd14}: s2wr0 <= 6;
{1'd0, 4'd15}: s2wr0 <= 7;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm16_dd, writeCycle})
{1'd0, 4'd0}: s2wr1 <= 0;
{1'd0, 4'd1}: s2wr1 <= 1;
{1'd0, 4'd2}: s2wr1 <= 2;
{1'd0, 4'd3}: s2wr1 <= 3;
{1'd0, 4'd4}: s2wr1 <= 4;
{1'd0, 4'd5}: s2wr1 <= 5;
{1'd0, 4'd6}: s2wr1 <= 6;
{1'd0, 4'd7}: s2wr1 <= 7;
{1'd0, 4'd8}: s2wr1 <= 8;
{1'd0, 4'd9}: s2wr1 <= 9;
{1'd0, 4'd10}: s2wr1 <= 10;
{1'd0, 4'd11}: s2wr1 <= 11;
{1'd0, 4'd12}: s2wr1 <= 12;
{1'd0, 4'd13}: s2wr1 <= 13;
{1'd0, 4'd14}: s2wr1 <= 14;
{1'd0, 4'd15}: s2wr1 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 16
module DirSum_8230(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [3:0] i2;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i2 <= 0;
end
else begin
if (next == 1)
i2 <= 0;
else if (i2 == 15)
i2 <= 0;
else
i2 <= i2 + 1;
end
end
codeBlock7996 codeBlockIsnt9835(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i2_in(i2),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D6_8192(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3ec5;
2: out3 <= 16'h3b21;
3: out3 <= 16'h3537;
4: out3 <= 16'h2d41;
5: out3 <= 16'h238e;
6: out3 <= 16'h187e;
7: out3 <= 16'hc7c;
8: out3 <= 16'h0;
9: out3 <= 16'hf384;
10: out3 <= 16'he782;
11: out3 <= 16'hdc72;
12: out3 <= 16'hd2bf;
13: out3 <= 16'hcac9;
14: out3 <= 16'hc4df;
15: out3 <= 16'hc13b;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D8_8228(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hc7c;
2: out3 <= 16'h187e;
3: out3 <= 16'h238e;
4: out3 <= 16'h2d41;
5: out3 <= 16'h3537;
6: out3 <= 16'h3b21;
7: out3 <= 16'h3ec5;
8: out3 <= 16'h4000;
9: out3 <= 16'h3ec5;
10: out3 <= 16'h3b21;
11: out3 <= 16'h3537;
12: out3 <= 16'h2d41;
13: out3 <= 16'h238e;
14: out3 <= 16'h187e;
15: out3 <= 16'hc7c;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock7996(clk, reset, next_in, next_out,
i2_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [3:0] i2_in;
reg [3:0] i2;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_9838(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a113;
wire signed [15:0] a102;
wire signed [15:0] a116;
wire signed [15:0] a106;
wire signed [15:0] a117;
wire signed [15:0] a118;
reg signed [15:0] tm227;
reg signed [15:0] tm231;
reg signed [15:0] tm243;
reg signed [15:0] tm250;
reg signed [15:0] tm228;
reg signed [15:0] tm232;
reg signed [15:0] tm244;
reg signed [15:0] tm251;
wire signed [15:0] tm19;
wire signed [15:0] a107;
wire signed [15:0] tm20;
wire signed [15:0] a109;
reg signed [15:0] tm229;
reg signed [15:0] tm233;
reg signed [15:0] tm245;
reg signed [15:0] tm252;
reg signed [15:0] tm55;
reg signed [15:0] tm56;
reg signed [15:0] tm230;
reg signed [15:0] tm234;
reg signed [15:0] tm246;
reg signed [15:0] tm253;
reg signed [15:0] tm247;
reg signed [15:0] tm254;
wire signed [15:0] a108;
wire signed [15:0] a110;
wire signed [15:0] a111;
wire signed [15:0] a112;
reg signed [15:0] tm248;
reg signed [15:0] tm255;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm249;
reg signed [15:0] tm256;
assign a113 = X0;
assign a102 = a113;
assign a116 = X1;
assign a106 = a116;
assign a117 = X2;
assign a118 = X3;
assign a107 = tm19;
assign a109 = tm20;
assign Y0 = tm249;
assign Y1 = tm256;
D6_8192 instD6inst0_8192(.addr(i2[3:0]), .out(tm19), .clk(clk));
D8_8228 instD8inst0_8228(.addr(i2[3:0]), .out(tm20), .clk(clk));
multfix #(16, 2) m8095(.a(tm55), .b(tm230), .clk(clk), .q_sc(a108), .q_unsc(), .rst(reset));
multfix #(16, 2) m8117(.a(tm56), .b(tm234), .clk(clk), .q_sc(a110), .q_unsc(), .rst(reset));
multfix #(16, 2) m8135(.a(tm56), .b(tm230), .clk(clk), .q_sc(a111), .q_unsc(), .rst(reset));
multfix #(16, 2) m8146(.a(tm55), .b(tm234), .clk(clk), .q_sc(a112), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub8124(.a(a108), .b(a110), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add8153(.a(a111), .b(a112), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm55 <= 0;
tm230 <= 0;
tm56 <= 0;
tm234 <= 0;
tm56 <= 0;
tm230 <= 0;
tm55 <= 0;
tm234 <= 0;
end
else begin
i2 <= i2_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm227 <= a117;
tm231 <= a118;
tm243 <= a102;
tm250 <= a106;
tm228 <= tm227;
tm232 <= tm231;
tm244 <= tm243;
tm251 <= tm250;
tm229 <= tm228;
tm233 <= tm232;
tm245 <= tm244;
tm252 <= tm251;
tm55 <= a107;
tm56 <= a109;
tm230 <= tm229;
tm234 <= tm233;
tm246 <= tm245;
tm253 <= tm252;
tm247 <= tm246;
tm254 <= tm253;
tm248 <= tm247;
tm255 <= tm254;
tm249 <= tm248;
tm256 <= tm255;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock8233(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_9841(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a69;
wire signed [15:0] a70;
wire signed [15:0] a71;
wire signed [15:0] a72;
wire signed [15:0] t45;
wire signed [15:0] t46;
wire signed [15:0] t47;
wire signed [15:0] t48;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a69 = X0;
assign a70 = X2;
assign a71 = X1;
assign a72 = X3;
assign Y0 = t45;
assign Y1 = t46;
assign Y2 = t47;
assign Y3 = t48;
addfxp #(16, 1) add8245(.a(a69), .b(a70), .clk(clk), .q(t45)); // 0
addfxp #(16, 1) add8260(.a(a71), .b(a72), .clk(clk), .q(t46)); // 0
subfxp #(16, 1) sub8275(.a(a69), .b(a70), .clk(clk), .q(t47)); // 0
subfxp #(16, 1) sub8290(.a(a71), .b(a72), .clk(clk), .q(t48)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 68
// Gap: 32
module rc8315(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm8313 instPerm9842(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet8313(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm8313(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter addrbits = 5;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm21;
assign tm21 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_9847(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9848(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(31, 5) nextReg_9859(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_9860(.X(next2), .Y(next3), .clk(clk));
nextReg #(32, 5) nextReg_9863(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9864(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(31, 1) shiftFIFO_9867(.X(tm21), .Y(tm21_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_9870(.X(tm21_d), .Y(tm21_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 5) shiftFIFO_9875(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm21_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 16;
{1'd0, 5'd1}: s1rd0 <= 17;
{1'd0, 5'd2}: s1rd0 <= 18;
{1'd0, 5'd3}: s1rd0 <= 19;
{1'd0, 5'd4}: s1rd0 <= 20;
{1'd0, 5'd5}: s1rd0 <= 21;
{1'd0, 5'd6}: s1rd0 <= 22;
{1'd0, 5'd7}: s1rd0 <= 23;
{1'd0, 5'd8}: s1rd0 <= 24;
{1'd0, 5'd9}: s1rd0 <= 25;
{1'd0, 5'd10}: s1rd0 <= 26;
{1'd0, 5'd11}: s1rd0 <= 27;
{1'd0, 5'd12}: s1rd0 <= 28;
{1'd0, 5'd13}: s1rd0 <= 29;
{1'd0, 5'd14}: s1rd0 <= 30;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 1;
{1'd0, 5'd18}: s1rd0 <= 2;
{1'd0, 5'd19}: s1rd0 <= 3;
{1'd0, 5'd20}: s1rd0 <= 4;
{1'd0, 5'd21}: s1rd0 <= 5;
{1'd0, 5'd22}: s1rd0 <= 6;
{1'd0, 5'd23}: s1rd0 <= 7;
{1'd0, 5'd24}: s1rd0 <= 8;
{1'd0, 5'd25}: s1rd0 <= 9;
{1'd0, 5'd26}: s1rd0 <= 10;
{1'd0, 5'd27}: s1rd0 <= 11;
{1'd0, 5'd28}: s1rd0 <= 12;
{1'd0, 5'd29}: s1rd0 <= 13;
{1'd0, 5'd30}: s1rd0 <= 14;
{1'd0, 5'd31}: s1rd0 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm21_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 1;
{1'd0, 5'd2}: s1rd1 <= 2;
{1'd0, 5'd3}: s1rd1 <= 3;
{1'd0, 5'd4}: s1rd1 <= 4;
{1'd0, 5'd5}: s1rd1 <= 5;
{1'd0, 5'd6}: s1rd1 <= 6;
{1'd0, 5'd7}: s1rd1 <= 7;
{1'd0, 5'd8}: s1rd1 <= 8;
{1'd0, 5'd9}: s1rd1 <= 9;
{1'd0, 5'd10}: s1rd1 <= 10;
{1'd0, 5'd11}: s1rd1 <= 11;
{1'd0, 5'd12}: s1rd1 <= 12;
{1'd0, 5'd13}: s1rd1 <= 13;
{1'd0, 5'd14}: s1rd1 <= 14;
{1'd0, 5'd15}: s1rd1 <= 15;
{1'd0, 5'd16}: s1rd1 <= 16;
{1'd0, 5'd17}: s1rd1 <= 17;
{1'd0, 5'd18}: s1rd1 <= 18;
{1'd0, 5'd19}: s1rd1 <= 19;
{1'd0, 5'd20}: s1rd1 <= 20;
{1'd0, 5'd21}: s1rd1 <= 21;
{1'd0, 5'd22}: s1rd1 <= 22;
{1'd0, 5'd23}: s1rd1 <= 23;
{1'd0, 5'd24}: s1rd1 <= 24;
{1'd0, 5'd25}: s1rd1 <= 25;
{1'd0, 5'd26}: s1rd1 <= 26;
{1'd0, 5'd27}: s1rd1 <= 27;
{1'd0, 5'd28}: s1rd1 <= 28;
{1'd0, 5'd29}: s1rd1 <= 29;
{1'd0, 5'd30}: s1rd1 <= 30;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet8313 sw(tm21_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm21_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm21_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 32
module DirSum_8615(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [4:0] i1;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i1 <= 0;
end
else begin
if (next == 1)
i1 <= 0;
else if (i1 == 31)
i1 <= 0;
else
i1 <= i1 + 1;
end
end
codeBlock8317 codeBlockIsnt9880(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i1_in(i1),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D2_8545(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [4:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3fb1;
2: out3 <= 16'h3ec5;
3: out3 <= 16'h3d3f;
4: out3 <= 16'h3b21;
5: out3 <= 16'h3871;
6: out3 <= 16'h3537;
7: out3 <= 16'h3179;
8: out3 <= 16'h2d41;
9: out3 <= 16'h289a;
10: out3 <= 16'h238e;
11: out3 <= 16'h1e2b;
12: out3 <= 16'h187e;
13: out3 <= 16'h1294;
14: out3 <= 16'hc7c;
15: out3 <= 16'h646;
16: out3 <= 16'h0;
17: out3 <= 16'hf9ba;
18: out3 <= 16'hf384;
19: out3 <= 16'hed6c;
20: out3 <= 16'he782;
21: out3 <= 16'he1d5;
22: out3 <= 16'hdc72;
23: out3 <= 16'hd766;
24: out3 <= 16'hd2bf;
25: out3 <= 16'hce87;
26: out3 <= 16'hcac9;
27: out3 <= 16'hc78f;
28: out3 <= 16'hc4df;
29: out3 <= 16'hc2c1;
30: out3 <= 16'hc13b;
31: out3 <= 16'hc04f;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D4_8613(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [4:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'h646;
2: out3 <= 16'hc7c;
3: out3 <= 16'h1294;
4: out3 <= 16'h187e;
5: out3 <= 16'h1e2b;
6: out3 <= 16'h238e;
7: out3 <= 16'h289a;
8: out3 <= 16'h2d41;
9: out3 <= 16'h3179;
10: out3 <= 16'h3537;
11: out3 <= 16'h3871;
12: out3 <= 16'h3b21;
13: out3 <= 16'h3d3f;
14: out3 <= 16'h3ec5;
15: out3 <= 16'h3fb1;
16: out3 <= 16'h4000;
17: out3 <= 16'h3fb1;
18: out3 <= 16'h3ec5;
19: out3 <= 16'h3d3f;
20: out3 <= 16'h3b21;
21: out3 <= 16'h3871;
22: out3 <= 16'h3537;
23: out3 <= 16'h3179;
24: out3 <= 16'h2d41;
25: out3 <= 16'h289a;
26: out3 <= 16'h238e;
27: out3 <= 16'h1e2b;
28: out3 <= 16'h187e;
29: out3 <= 16'h1294;
30: out3 <= 16'hc7c;
31: out3 <= 16'h646;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock8317(clk, reset, next_in, next_out,
i1_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [4:0] i1_in;
reg [4:0] i1;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_9883(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a53;
wire signed [15:0] a42;
wire signed [15:0] a56;
wire signed [15:0] a46;
wire signed [15:0] a57;
wire signed [15:0] a58;
reg signed [15:0] tm257;
reg signed [15:0] tm261;
reg signed [15:0] tm273;
reg signed [15:0] tm280;
reg signed [15:0] tm258;
reg signed [15:0] tm262;
reg signed [15:0] tm274;
reg signed [15:0] tm281;
wire signed [15:0] tm24;
wire signed [15:0] a47;
wire signed [15:0] tm25;
wire signed [15:0] a49;
reg signed [15:0] tm259;
reg signed [15:0] tm263;
reg signed [15:0] tm275;
reg signed [15:0] tm282;
reg signed [15:0] tm63;
reg signed [15:0] tm64;
reg signed [15:0] tm260;
reg signed [15:0] tm264;
reg signed [15:0] tm276;
reg signed [15:0] tm283;
reg signed [15:0] tm277;
reg signed [15:0] tm284;
wire signed [15:0] a48;
wire signed [15:0] a50;
wire signed [15:0] a51;
wire signed [15:0] a52;
reg signed [15:0] tm278;
reg signed [15:0] tm285;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm279;
reg signed [15:0] tm286;
assign a53 = X0;
assign a42 = a53;
assign a56 = X1;
assign a46 = a56;
assign a57 = X2;
assign a58 = X3;
assign a47 = tm24;
assign a49 = tm25;
assign Y0 = tm279;
assign Y1 = tm286;
D2_8545 instD2inst0_8545(.addr(i1[4:0]), .out(tm24), .clk(clk));
D4_8613 instD4inst0_8613(.addr(i1[4:0]), .out(tm25), .clk(clk));
multfix #(16, 2) m8416(.a(tm63), .b(tm260), .clk(clk), .q_sc(a48), .q_unsc(), .rst(reset));
multfix #(16, 2) m8438(.a(tm64), .b(tm264), .clk(clk), .q_sc(a50), .q_unsc(), .rst(reset));
multfix #(16, 2) m8456(.a(tm64), .b(tm260), .clk(clk), .q_sc(a51), .q_unsc(), .rst(reset));
multfix #(16, 2) m8467(.a(tm63), .b(tm264), .clk(clk), .q_sc(a52), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub8445(.a(a48), .b(a50), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add8474(.a(a51), .b(a52), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm63 <= 0;
tm260 <= 0;
tm64 <= 0;
tm264 <= 0;
tm64 <= 0;
tm260 <= 0;
tm63 <= 0;
tm264 <= 0;
end
else begin
i1 <= i1_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm257 <= a57;
tm261 <= a58;
tm273 <= a42;
tm280 <= a46;
tm258 <= tm257;
tm262 <= tm261;
tm274 <= tm273;
tm281 <= tm280;
tm259 <= tm258;
tm263 <= tm262;
tm275 <= tm274;
tm282 <= tm281;
tm63 <= a47;
tm64 <= a49;
tm260 <= tm259;
tm264 <= tm263;
tm276 <= tm275;
tm283 <= tm282;
tm277 <= tm276;
tm284 <= tm283;
tm278 <= tm277;
tm285 <= tm284;
tm279 <= tm278;
tm286 <= tm285;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock8618(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_9886(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a9;
wire signed [15:0] a10;
wire signed [15:0] a11;
wire signed [15:0] a12;
wire signed [15:0] t21;
wire signed [15:0] t22;
wire signed [15:0] t23;
wire signed [15:0] t24;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a9 = X0;
assign a10 = X2;
assign a11 = X1;
assign a12 = X3;
assign Y0 = t21;
assign Y1 = t22;
assign Y2 = t23;
assign Y3 = t24;
addfxp #(16, 1) add8630(.a(a9), .b(a10), .clk(clk), .q(t21)); // 0
addfxp #(16, 1) add8645(.a(a11), .b(a12), .clk(clk), .q(t22)); // 0
subfxp #(16, 1) sub8660(.a(a9), .b(a10), .clk(clk), .q(t23)); // 0
subfxp #(16, 1) sub8675(.a(a11), .b(a12), .clk(clk), .q(t24)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 68
// Gap: 32
module rc8700(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm8698 instPerm9887(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet8698(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm8698(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter addrbits = 5;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm26;
assign tm26 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_9892(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9893(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(31, 5) nextReg_9904(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_9905(.X(next2), .Y(next3), .clk(clk));
nextReg #(32, 5) nextReg_9908(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_9909(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(31, 1) shiftFIFO_9912(.X(tm26), .Y(tm26_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_9915(.X(tm26_d), .Y(tm26_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 5) shiftFIFO_9920(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm26_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 1;
{1'd0, 5'd1}: s1rd0 <= 3;
{1'd0, 5'd2}: s1rd0 <= 5;
{1'd0, 5'd3}: s1rd0 <= 7;
{1'd0, 5'd4}: s1rd0 <= 9;
{1'd0, 5'd5}: s1rd0 <= 11;
{1'd0, 5'd6}: s1rd0 <= 13;
{1'd0, 5'd7}: s1rd0 <= 15;
{1'd0, 5'd8}: s1rd0 <= 17;
{1'd0, 5'd9}: s1rd0 <= 19;
{1'd0, 5'd10}: s1rd0 <= 21;
{1'd0, 5'd11}: s1rd0 <= 23;
{1'd0, 5'd12}: s1rd0 <= 25;
{1'd0, 5'd13}: s1rd0 <= 27;
{1'd0, 5'd14}: s1rd0 <= 29;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 2;
{1'd0, 5'd18}: s1rd0 <= 4;
{1'd0, 5'd19}: s1rd0 <= 6;
{1'd0, 5'd20}: s1rd0 <= 8;
{1'd0, 5'd21}: s1rd0 <= 10;
{1'd0, 5'd22}: s1rd0 <= 12;
{1'd0, 5'd23}: s1rd0 <= 14;
{1'd0, 5'd24}: s1rd0 <= 16;
{1'd0, 5'd25}: s1rd0 <= 18;
{1'd0, 5'd26}: s1rd0 <= 20;
{1'd0, 5'd27}: s1rd0 <= 22;
{1'd0, 5'd28}: s1rd0 <= 24;
{1'd0, 5'd29}: s1rd0 <= 26;
{1'd0, 5'd30}: s1rd0 <= 28;
{1'd0, 5'd31}: s1rd0 <= 30;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm26_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 2;
{1'd0, 5'd2}: s1rd1 <= 4;
{1'd0, 5'd3}: s1rd1 <= 6;
{1'd0, 5'd4}: s1rd1 <= 8;
{1'd0, 5'd5}: s1rd1 <= 10;
{1'd0, 5'd6}: s1rd1 <= 12;
{1'd0, 5'd7}: s1rd1 <= 14;
{1'd0, 5'd8}: s1rd1 <= 16;
{1'd0, 5'd9}: s1rd1 <= 18;
{1'd0, 5'd10}: s1rd1 <= 20;
{1'd0, 5'd11}: s1rd1 <= 22;
{1'd0, 5'd12}: s1rd1 <= 24;
{1'd0, 5'd13}: s1rd1 <= 26;
{1'd0, 5'd14}: s1rd1 <= 28;
{1'd0, 5'd15}: s1rd1 <= 30;
{1'd0, 5'd16}: s1rd1 <= 1;
{1'd0, 5'd17}: s1rd1 <= 3;
{1'd0, 5'd18}: s1rd1 <= 5;
{1'd0, 5'd19}: s1rd1 <= 7;
{1'd0, 5'd20}: s1rd1 <= 9;
{1'd0, 5'd21}: s1rd1 <= 11;
{1'd0, 5'd22}: s1rd1 <= 13;
{1'd0, 5'd23}: s1rd1 <= 15;
{1'd0, 5'd24}: s1rd1 <= 17;
{1'd0, 5'd25}: s1rd1 <= 19;
{1'd0, 5'd26}: s1rd1 <= 21;
{1'd0, 5'd27}: s1rd1 <= 23;
{1'd0, 5'd28}: s1rd1 <= 25;
{1'd0, 5'd29}: s1rd1 <= 27;
{1'd0, 5'd30}: s1rd1 <= 29;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet8698 sw(tm26_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm26_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm26_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
module multfix(clk, rst, a, b, q_sc, q_unsc);
parameter WIDTH=35, CYCLES=6;
input signed [WIDTH-1:0] a,b;
output [WIDTH-1:0] q_sc;
output [WIDTH-1:0] q_unsc;
input clk, rst;
reg signed [2*WIDTH-1:0] q[CYCLES-1:0];
wire signed [2*WIDTH-1:0] res;
integer i;
assign res = q[CYCLES-1];
assign q_unsc = res[WIDTH-1:0];
assign q_sc = {res[2*WIDTH-1], res[2*WIDTH-4:WIDTH-2]};
always @(posedge clk) begin
q[0] <= a * b;
for (i = 1; i < CYCLES; i=i+1) begin
q[i] <= q[i-1];
end
end
endmodule
module addfxp(a, b, q, clk);
parameter width = 16, cycles=1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a+b;
for (i=1; i < cycles; i = i+1)
res[i] <= res[i-1];
end
endmodule
module subfxp(a, b, q, clk);
parameter width = 16, cycles=1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a-b;
for (i=1; i < cycles; i = i+1)
res[i] <= res[i-1];
end
endmodule |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : idft_top_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-IDFT core
//
module idft_top_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg next;
reg [63:0] dataX [0:31];
reg [63:0] dataY [0:31];
reg [5:0] xSel;
reg [5:0] ySel;
wire [63:0] dataIn, dataOut, dataR_Out;
reg [63:0] data_In_data, data_In_addr, data_Out_addr;
reg data_valid, data_In_write;
wire next_out, next_posedge;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i)
begin
if(wb_rst_i)
begin
next <= 0;
data_In_write <= 0;
data_In_addr <= 0;
data_In_data[31:0] <= 0;
data_In_data[63:32]<= 0;
end
else if(wb_stb_i & wb_we_i)
case(wb_adr_i[5:2])
0:
next <= wb_dat_i[0];
1:
data_In_write <= wb_dat_i[0];
2:
data_In_addr <= wb_dat_i;
3:
data_In_data[31:0] <= wb_dat_i;
4:
data_In_data[63:32]<= wb_dat_i;
5:
data_Out_addr <= wb_dat_i;
default:
;
endcase
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[5:2])
0:
wb_dat_o = {31'b0, next};
1:
wb_dat_o = {31'b0, data_In_write};
2:
wb_dat_o = data_In_addr;
3:
wb_dat_o = data_In_data[31:0];
4:
wb_dat_o = data_In_data[63:32];
5:
wb_dat_o = data_Out_addr;
6:
wb_dat_o = dataR_Out[31:0];
7:
wb_dat_o = dataR_Out[63:32];
8:
wb_dat_o = {31'b0, data_valid};
default:
wb_dat_o = 32'b0;
endcase
end // always @ (*)
idft_top idft_top(
.clk(wb_clk_i),
.reset(wb_rst_i),
.next(next_posedge),
.next_out(next_out),
.X0(dataIn[15:0]),
.X1(dataIn[31:16]),
.X2(dataIn[47:32]),
.X3(dataIn[63:48]),
.Y0(dataOut[15:0]),
.Y1(dataOut[31:16]),
.Y2(dataOut[47:32]),
.Y3(dataOut[63:48]));
reg data_In_write_r;
always @(posedge wb_clk_i)
begin
data_In_write_r <= data_In_write;
end
wire data_In_write_posedge = data_In_write & ~data_In_write_r;
always @ (posedge wb_clk_i)
begin
if(data_In_write_posedge)
begin
dataX[data_In_addr] <= data_In_data;
end
end
assign dataR_Out=dataY[data_Out_addr];
reg next_r;
always @(posedge wb_clk_i)
begin
next_r <= next;
end
assign next_posedge = next & ~next_r;
always @ (posedge wb_clk_i)
begin
if(next_posedge)
begin
xSel <= 6'h00;
end
else if(xSel<6'b100000)
begin
xSel <= xSel +1;
end
end
assign dataIn = dataX[xSel];
reg next_out_r;
always @(posedge wb_clk_i)
begin
next_out_r <= next_out;
end
wire next_out_posedge = next_out & ~next_out_r;
always @ (posedge wb_clk_i)
begin
if(next_out_posedge)
begin
ySel <= 6'h00;
end
else if(ySel<6'b100000)
begin
ySel <= ySel +1;
dataY[ySel] = dataOut;
end
end
always @ (posedge wb_clk_i)
begin
if(next_posedge)
begin
data_valid <= 0;
end
else if(next_out_posedge)
begin
data_valid <= 1;
end
end
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral IIR Filter Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./iirGen.pl -A 256 0 378 0 179 0 32 0 2 0 0 0 -B 0 4 22 68 136 191 191 136 68 22 4 0 -moduleName IIR_filter -fractionalBits 8 -bitWidth 32 -inData inData -inReg -outReg -outData outData -clk clk -reset reset -reset_edge negedge -filterForm 1 -debug -outFile ../outputs/filter_1536036361.v */
/* Warning: zero-valued filter taps have been optimized away. */
module IIR_filter_firBlock_left_MultiplyBlock (
X,
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11
);
// Port mode declarations:
input signed [31:0] X;
output signed [31:0]
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8,
Y9,
Y10,
Y11;
wire [31:0] Y [0:10];
assign Y1 = Y[0];
assign Y2 = Y[1];
assign Y3 = Y[2];
assign Y4 = Y[3];
assign Y5 = Y[4];
assign Y6 = Y[5];
assign Y7 = Y[6];
assign Y8 = Y[7];
assign Y9 = Y[8];
assign Y10 = Y[9];
assign Y11 = Y[10];
//Multipliers:
wire signed [39:0]
w1,
w0,
w16,
w17,
w4,
w3,
w8,
w11,
w192,
w191,
w22,
w68,
w136;
assign w1 = X;
assign w0 = 0;
assign w11 = w3 + w8; //2195.42405790882 = adderArea(3,34)
assign w136 = w17 << 3; //shl(3,39)
assign w16 = w1 << 4; //shl(4,35)
assign w17 = w1 + w16; //2195.42405790882 = adderArea(4,35)
assign w191 = w192 - w1; //2561.32791574853 = subArea(6,39)
assign w192 = w3 << 6; //shl(6,39)
assign w22 = w11 << 1; //shl(1,36)
assign w3 = w4 - w1; //2408.3135227603 = subArea(2,33)
assign w4 = w1 << 2; //shl(2,33)
assign w68 = w17 << 2; //shl(2,38)
assign w8 = w1 << 3; //shl(3,34)
assign Y[0] = w4[39:8]; //BitwidthUsed(0, 25)
assign Y[1] = w22[39:8]; //BitwidthUsed(0, 28)
assign Y[2] = w68[39:8]; //BitwidthUsed(0, 30)
assign Y[3] = w136[39:8]; //BitwidthUsed(0, 31)
assign Y[4] = w191[39:8]; //BitwidthUsed(0, 31)
assign Y[5] = w191[39:8]; //BitwidthUsed(0, 31)
assign Y[6] = w136[39:8]; //BitwidthUsed(0, 31)
assign Y[7] = w68[39:8]; //BitwidthUsed(0, 30)
assign Y[8] = w22[39:8]; //BitwidthUsed(0, 28)
assign Y[9] = w4[39:8]; //BitwidthUsed(0, 25)
assign Y[10] = w0[39:8]; //BitwidthUsed(none)
//IIR_filter_firBlock_left_MultiplyBlock area estimate = 9360.48955432647;
endmodule //IIR_filter_firBlock_left_MultiplyBlock
module IIR_filter_firBlock_left (
X,
clk,
Y,
reset
);
// Port mode declarations:
input [31:0] X;
input clk;
output [31:0] Y;
input reset;
//registerOut
reg [31:0] Y;
wire [31:0] Y_in;
always@(posedge clk or negedge reset) begin
if(~reset) begin
Y <= 32'h00000000;
end else begin
Y <= Y_in;
end
end
wire [31:0] multProducts [0:10];
IIR_filter_firBlock_left_MultiplyBlock my_IIR_filter_firBlock_left_MultiplyBlock(
.X(X),
.Y1(multProducts[0]),
.Y2(multProducts[1]),
.Y3(multProducts[2]),
.Y4(multProducts[3]),
.Y5(multProducts[4]),
.Y6(multProducts[5]),
.Y7(multProducts[6]),
.Y8(multProducts[7]),
.Y9(multProducts[8]),
.Y10(multProducts[9]),
.Y11(multProducts[10])
);
reg [31:0] firStep[0:9];
always@(posedge clk or negedge reset) begin
if(~reset) begin
firStep[0] <= 32'h00000000;
firStep[1] <= 32'h00000000;
firStep[2] <= 32'h00000000;
firStep[3] <= 32'h00000000;
firStep[4] <= 32'h00000000;
firStep[5] <= 32'h00000000;
firStep[6] <= 32'h00000000;
firStep[7] <= 32'h00000000;
firStep[8] <= 32'h00000000;
firStep[9] <= 32'h00000000;
end
else begin
firStep[0] <= multProducts[0]; // 2448.23046908235 = flop(0, 31)
firStep[1] <= firStep[0] + multProducts[1]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[2] <= firStep[1] + multProducts[2]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[3] <= firStep[2] + multProducts[3]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[4] <= firStep[3] + multProducts[4]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[5] <= firStep[4] + multProducts[5]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[6] <= firStep[5] + multProducts[6]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[7] <= firStep[6] + multProducts[7]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[8] <= firStep[7] + multProducts[8]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[9] <= firStep[8] + multProducts[9]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
end
end
assign Y_in = firStep[9]+ multProducts[10];// 0 = adder(none)
//IIR_filter_firBlock_left area estimate = 56049.8412354117;
endmodule //IIR_filter_firBlock_left
/* Warning: zero-valued filter taps have been optimized away. */
module IIR_filter_firBlock_right_MultiplyBlock (
X,
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8
);
// Port mode declarations:
input signed [31:0] X;
output signed [31:0]
Y1,
Y2,
Y3,
Y4,
Y5,
Y6,
Y7,
Y8;
wire [31:0] Y [0:7];
assign Y1 = Y[0];
assign Y2 = Y[1];
assign Y3 = Y[2];
assign Y4 = Y[3];
assign Y5 = Y[4];
assign Y6 = Y[5];
assign Y7 = Y[6];
assign Y8 = Y[7];
//Multipliers:
wire signed [39:0]
w1,
w0,
w4,
w3,
w192,
w189,
w5,
w10,
w179,
w2,
w2_,
w32,
w32_,
w179_,
w378,
w378_;
assign w1 = X;
assign w0 = 0;
assign w10 = w5 << 1; //shl(1,35)
assign w179 = w189 - w10; //2943.86389821912 = subArea(1,39)
assign w179_ = -1 * w179; //1809.56165059559 = negArea(0,39)
assign w189 = w192 - w3; //2484.82071925441 = subArea(6,38)
assign w192 = w3 << 6; //shl(6,38)
assign w2 = w1 << 1; //shl(1,32)
assign w2_ = -1 * w2; //1437.00483871323 = negArea(1,32)
assign w3 = w4 - w1; //2331.80632626618 = subArea(2,32)
assign w32 = w1 << 5; //shl(5,36)
assign w32_ = -1 * w32; //1437.00483871323 = negArea(5,36)
assign w378 = w189 << 1; //shl(1,39)
assign w378_ = -1 * w378; //1762.99204911029 = negArea(1,39)
assign w4 = w1 << 2; //shl(2,32)
assign w5 = w1 + w4; //2195.42405790882 = adderArea(2,33)
assign Y[0] = w2_[39:8]; //BitwidthUsed(0, 24)
assign Y[1] = w0[39:8]; //BitwidthUsed(none)
assign Y[2] = w32_[39:8]; //BitwidthUsed(0, 28)
assign Y[3] = w0[39:8]; //BitwidthUsed(none)
assign Y[4] = w179_[39:8]; //BitwidthUsed(0, 31)
assign Y[5] = w0[39:8]; //BitwidthUsed(none)
assign Y[6] = w378_[39:8]; //BitwidthUsed(0, 31)
assign Y[7] = w0[39:8]; //BitwidthUsed(none)
//IIR_filter_firBlock_right_MultiplyBlock area estimate = 16402.4783787809;
endmodule //IIR_filter_firBlock_right_MultiplyBlock
module IIR_filter_firBlock_right (
X,
clk,
Y,
reset
);
// Port mode declarations:
input [31:0] X;
input clk;
output [31:0] Y;
input reset;
//registerOut
reg [31:0] Y;
wire [31:0] Y_in;
always@(posedge clk or negedge reset) begin
if(~reset) begin
Y <= 32'h00000000;
end else begin
Y <= Y_in;
end
end
wire [31:0] multProducts [0:7];
IIR_filter_firBlock_right_MultiplyBlock my_IIR_filter_firBlock_right_MultiplyBlock(
.X(X),
.Y1(multProducts[0]),
.Y2(multProducts[1]),
.Y3(multProducts[2]),
.Y4(multProducts[3]),
.Y5(multProducts[4]),
.Y6(multProducts[5]),
.Y7(multProducts[6]),
.Y8(multProducts[7])
);
reg [31:0] firStep[0:6];
always@(posedge clk or negedge reset) begin
if(~reset) begin
firStep[0] <= 32'h00000000;
firStep[1] <= 32'h00000000;
firStep[2] <= 32'h00000000;
firStep[3] <= 32'h00000000;
firStep[4] <= 32'h00000000;
firStep[5] <= 32'h00000000;
firStep[6] <= 32'h00000000;
end
else begin
firStep[0] <= multProducts[0]; // 2448.23046908235 = flop(0, 31)
firStep[1] <= firStep[0] + multProducts[1]; // 2448.23046908235 = flop(0, 31) + adder(none)
firStep[2] <= firStep[1] + multProducts[2]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[3] <= firStep[2] + multProducts[3]; // 2448.23046908235 = flop(0, 31) + adder(none)
firStep[4] <= firStep[3] + multProducts[4]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
firStep[5] <= firStep[4] + multProducts[5]; // 2448.23046908235 = flop(0, 31) + adder(none)
firStep[6] <= firStep[5] + multProducts[6]; // 4643.65452699117 = flop(0, 31) + adder(0, 31)
end
end
assign Y_in = firStep[6]+ multProducts[7];// 0 = adder(none)
//IIR_filter_firBlock_right area estimate = 42574.5943051662;
endmodule //IIR_filter_firBlock_right
module IIR_filter (
inData,
clk,
outData,
reset
);
// Port mode declarations:
input [31:0] inData;
input clk;
output [31:0] outData;
input reset;
//registerIn
reg [31:0] inData_in;
always@(posedge clk or negedge reset) begin
if(~reset) begin
inData_in <= 32'h00000000;
end else begin
inData_in <= inData;
end
end
//registerOut
reg [31:0] outData;
wire [31:0] outData_in;
always@(posedge clk or negedge reset) begin
if(~reset) begin
outData <= 32'h00000000;
end else begin
outData <= outData_in;
end
end
wire [31:0] leftOut, rightOut;
IIR_filter_firBlock_left my_IIR_filter_firBlock_left(
.X(inData_in),
.Y(leftOut),
.clk(clk),
.reset(reset)
);
IIR_filter_firBlock_right my_IIR_filter_firBlock_right(
.X(outData_in),
.Y(rightOut),
.clk(clk),
.reset(reset)
);
assign outData_in = leftOut + rightOut; // adder(32)
//IIR_filter area estimate = 105716.320536651;
endmodule //IIR_filter
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : iir_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-IIR core
//
module iir_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg next;
reg [31:0] dataX [0:31];
reg [31:0] dataY [0:31];
reg [5:0] xSel=6'b0;
reg [5:0] ySel=6'b0;
reg [5:0] count;
wire [31:0] dataIn, dataOut, data_Out;
reg [31:0] data_In_data, data_In_addr, data_Out_addr;
reg data_valid, data_In_write;
wire next_out;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i)
begin
if(wb_rst_i)
begin
next <= 0;
data_In_write <= 0;
data_In_addr <= 0;
data_In_data <= 0;
end
else if(wb_stb_i & wb_we_i)
case(wb_adr_i[5:2])
0:
next <= wb_dat_i[0];
1:
data_In_write <= wb_dat_i[0];
2:
data_In_addr <= wb_dat_i;
3:
data_In_data <= wb_dat_i;
4:
data_Out_addr <= wb_dat_i;
default:
;
endcase
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[5:2])
0:
wb_dat_o = {31'b0, next};
1:
wb_dat_o = {31'b0, data_In_write};
2:
wb_dat_o = data_In_addr;
3:
wb_dat_o = data_In_data;
4:
wb_dat_o = data_Out_addr;
5:
wb_dat_o = data_Out;
6:
wb_dat_o = {31'b0, data_valid};
default:
wb_dat_o = 32'b0;
endcase
end // always @ (*)
IIR_filter IIR_filter(
.clk(wb_clk_i),
.reset(~wb_rst_i),
.inData(dataIn),
.outData(dataOut));
reg data_In_write_r;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
data_In_write_r <= 0;
else
data_In_write_r <= data_In_write;
end
wire data_In_write_posedge = data_In_write & ~data_In_write_r;
reg [15:0] i;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
for (i = 0; i < 32; i = i + 1)
dataX[i] <= 0;
else
dataX[data_In_addr] <= data_In_data;
end
assign data_Out = dataY[data_Out_addr];
reg next_r;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
next_r <= 0;
else
next_r <= next;
end
wire next_posedge = next & ~next_r;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
xSel <= 0;
else if(next_posedge)
xSel <= 6'h00;
else if(xSel<6'b100000)
xSel <= xSel + 1;
end
assign dataIn = (xSel<6'b100000) ? dataX[xSel] : 32'b0;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
count <= 0;
else if(next_posedge)
begin
count <= 6'h00;
end
else if(xSel<4'b1010)
begin
count <= count +1;
end
end
assign next_out = (count == 4'b1000);
reg next_out_r;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
next_out_r <= 0;
else
next_out_r <= next_out;
end
wire next_out_posedge = next_out & ~next_out_r;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i) begin
ySel <= 0;
for (i = 0; i < 32; i = i + 1)
dataY[i] <= 0;
end else if(next_out_posedge)
begin
ySel <= 6'h00;
end
else if(ySel<6'b100000)
begin
ySel <= ySel +1;
dataY[ySel] = dataOut;
end
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
data_valid <= 0;
else if(next_posedge)
begin
data_valid <= 0;
end
else if(next_out_posedge)
begin
data_valid <= 1;
end
end
endmodule
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : iir_top_axi4lite.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides an axi4-lite wrapper for the wishbone based-IIR core
//
module iir_top_axi4lite (
// Clock & Reset
input logic clk_i,
input logic rst_ni,
// AXI4-Lite Slave Interface
AXI_LITE.in slave
);
// AES wishbone slave wires
wire wb_clk;
wire wb_rst;
wire [slave.AXI_ADDR_WIDTH - 1:0] wbs_d_iir_adr_i;
wire [slave.AXI_DATA_WIDTH - 1:0] wbs_d_iir_dat_i;
wire [3:0] wbs_d_iir_sel_i;
wire wbs_d_iir_we_i;
wire wbs_d_iir_cyc_i;
wire wbs_d_iir_stb_i;
wire [slave.AXI_DATA_WIDTH - 1:0] wbs_d_iir_dat_o;
wire wbs_d_iir_ack_o;
wire wbs_d_iir_err_o;
// Instantiate the AXI4Lite to Wishbone bridge
bonfire_axi4l2wb #(
.ADRWIDTH (slave.AXI_ADDR_WIDTH),
.FAST_READ_TERM (1'd0)
) bonfire_axi4l2wb_inst (
.S_AXI_ACLK (clk_i),
.S_AXI_ARESETN (rst_ni),
.S_AXI_AWADDR (slave.aw_addr),
.S_AXI_AWVALID (slave.aw_valid),
.S_AXI_AWREADY (slave.aw_ready),
.S_AXI_WDATA (slave.w_data),
.S_AXI_WSTRB (slave.w_strb),
.S_AXI_WVALID (slave.w_valid),
.S_AXI_WREADY (slave.w_ready),
.S_AXI_ARADDR (slave.ar_addr),
.S_AXI_ARVALID (slave.ar_valid),
.S_AXI_ARREADY (slave.ar_ready),
.S_AXI_RDATA (slave.r_data),
.S_AXI_RRESP (slave.r_resp),
.S_AXI_RVALID (slave.r_valid),
.S_AXI_RREADY (slave.r_ready),
.S_AXI_BRESP (slave.b_resp),
.S_AXI_BVALID (slave.b_valid),
.S_AXI_BREADY (slave.b_ready),
.wb_clk_o (wb_clk),
.wb_rst_o (wb_rst),
.wb_addr_o (wbs_d_iir_adr_i),
.wb_dat_o (wbs_d_iir_dat_i),
.wb_we_o (wbs_d_iir_we_i),
.wb_sel_o (wbs_d_iir_sel_i),
.wb_stb_o (wbs_d_iir_stb_i),
.wb_cyc_o (wbs_d_iir_cyc_i),
.wb_dat_i (wbs_d_iir_dat_o),
.wb_ack_i (wbs_d_iir_ack_o)
);
// Instantiate the wishbone-based DFT Core
iir_top iir_top_inst (
// Wishbone Slave interface
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_dat_i (wbs_d_iir_dat_i),
.wb_adr_i (wbs_d_iir_adr_i),
.wb_sel_i (wbs_d_iir_sel_i[3:0]),
.wb_we_i (wbs_d_iir_we_i),
.wb_cyc_i (wbs_d_iir_cyc_i),
.wb_stb_i (wbs_d_iir_stb_i),
.wb_dat_o (wbs_d_iir_dat_o),
.wb_err_o (),
.wb_ack_o (wbs_d_iir_ack_o),
// Processor interrupt
.int_o ()
);
endmodule // end aes_top_axi4lite
|
//////////////////////////////////////////////////////////////////////////////////
// Description: Generate 1023 chip sequence for SV PRN number prn_num.
// First chip on chip_out after reset.
// Asserting enb will advance to next chip.
//
//////////////////////////////////////////////////////////////////////////////////
module cacode(
input clk,
input rst,
input [5:0] prn_num,
input enb,
output reg chip_out
);
reg [10:1] g1, g2;
reg chip;
always @ (posedge clk)
if (rst) begin
g1 <= 10'b1111111111;
g2 <= 10'b1111111111;
end
else
if (enb) begin
g1[10:1] <= {g1[9:1], g1[3] ^ g1[10]};
g2[10:1] <= {g2[9:1], g2[2] ^ g2[3] ^ g2[6] ^ g2[8] ^ g2[9] ^ g2[10]};
end
always @(*)
begin
case (prn_num)
6'd1 : chip <= g1[10] ^ g2[2] ^ g2[6];
6'd2 : chip <= g1[10] ^ g2[3] ^ g2[7];
6'd3 : chip <= g1[10] ^ g2[4] ^ g2[8];
6'd4 : chip <= g1[10] ^ g2[5] ^ g2[9];
6'd5 : chip <= g1[10] ^ g2[1] ^ g2[9];
6'd6 : chip <= g1[10] ^ g2[2] ^ g2[10];
6'd7 : chip <= g1[10] ^ g2[1] ^ g2[8];
6'd8 : chip <= g1[10] ^ g2[2] ^ g2[9];
6'd9 : chip <= g1[10] ^ g2[3] ^ g2[10];
6'd10: chip <= g1[10] ^ g2[2] ^ g2[3];
6'd11: chip <= g1[10] ^ g2[3] ^ g2[4];
6'd12: chip <= g1[10] ^ g2[5] ^ g2[6];
6'd13: chip <= g1[10] ^ g2[6] ^ g2[7];
6'd14: chip <= g1[10] ^ g2[7] ^ g2[8];
6'd15: chip <= g1[10] ^ g2[8] ^ g2[9];
6'd16: chip <= g1[10] ^ g2[9] ^ g2[10];
6'd17: chip <= g1[10] ^ g2[1] ^ g2[4];
6'd18: chip <= g1[10] ^ g2[2] ^ g2[5];
6'd19: chip <= g1[10] ^ g2[3] ^ g2[6];
6'd20: chip <= g1[10] ^ g2[4] ^ g2[7];
6'd21: chip <= g1[10] ^ g2[5] ^ g2[8];
6'd22: chip <= g1[10] ^ g2[6] ^ g2[9];
6'd23: chip <= g1[10] ^ g2[1] ^ g2[3];
6'd24: chip <= g1[10] ^ g2[4] ^ g2[6];
6'd25: chip <= g1[10] ^ g2[5] ^ g2[7];
6'd26: chip <= g1[10] ^ g2[6] ^ g2[8];
6'd27: chip <= g1[10] ^ g2[7] ^ g2[9];
6'd28: chip <= g1[10] ^ g2[8] ^ g2[10];
6'd29: chip <= g1[10] ^ g2[1] ^ g2[6];
6'd30: chip <= g1[10] ^ g2[2] ^ g2[7];
6'd31: chip <= g1[10] ^ g2[3] ^ g2[8];
6'd32: chip <= g1[10] ^ g2[4] ^ g2[9];
6'd33: chip <= g1[10] ^ g2[5] ^ g2[10];
6'd34: chip <= g1[10] ^ g2[4] ^ g2[10];
6'd35: chip <= g1[10] ^ g2[1] ^ g2[7];
6'd36: chip <= g1[10] ^ g2[2] ^ g2[8];
6'd37: chip <= g1[10] ^ g2[4] ^ g2[10];
//
default: chip <= 1'b0; //invalid prn_num
endcase
end
// reclock for timing
always @ (posedge clk)
chip_out <= chip;
endmodule
|
module cacode_test (chip);
output chip;
reg clk = 0;
reg rst = 0;
reg [5:0] prn_num = 1;
reg enb = 0;
always
#10 clk <= ~clk;
initial begin
#1;
repeat (32) @(negedge clk)
rst <= 0;
repeat (32) @(negedge clk)
rst <= 1;
repeat (32) @(negedge clk)
rst <= 0;
end
initial begin
#1;
repeat (100) @(negedge clk)
enb <= 0;
repeat (1200) @(negedge clk)
enb <= 1;
repeat (100) @(negedge clk)
enb <= 0;
end
cacode dut(clk, rst, prn_num, enb, chip);
endmodule
|
// From the GPS transmitter's perspective
module gps(
sys_clk_50,
sync_rst_in,
sv_num,
startRound,
ca_code,
p_code,
l_code,
l_code_valid
);
input sys_clk_50;
input sync_rst_in;
input [5:0] sv_num;
input startRound;
output reg [12:0] ca_code;
output [127:0] p_code;
output [127:0] l_code;
output l_code_valid;
// Generate the clocks for the C/A code and P-code generators
// Assumes 200 MHz input clock
wire gps_clk_fast;
wire gps_clk_slow;
wire gps_clk_rst;
gps_clkgen gps_clk(
sys_clk_50,
sync_rst_in,
gps_clk_fast,
gps_clk_slow,
gps_clk_rst
);
// Combine SoC and clkgen resets
wire rst_combined = sync_rst_in | gps_clk_rst;
// Look for rising edge of start
reg startRound_r;
wire startRoundPosEdge = ~startRound_r & startRound;
always @(posedge gps_clk_fast)begin
if(rst_combined)begin
startRound_r <= 0;
end
else begin
startRound_r <= startRound;
end
end
// Control code generators
reg code_gen_en;
reg [3:0] ca_bit_count;
reg [7:0] p_bit_count;
always @(posedge gps_clk_fast)begin
if(rst_combined | startRoundPosEdge)begin
code_gen_en <= startRoundPosEdge;
end
else if(p_bit_count == 8'd128 && ca_bit_count == 4'd13)begin
code_gen_en <= 1'b0;
end
end
// Generate C/A code
wire ca_code_bit;
cacode ca(
gps_clk_slow,
rst_combined,
sv_num,
code_gen_en,
ca_code_bit
);
// Deal with clock differences by using code gen edge for slow clock
reg code_gen_en_r;
wire codeGenPosEdge = ~code_gen_en_r & code_gen_en;
always @(posedge gps_clk_slow)begin
if(rst_combined)begin
code_gen_en_r <= 0;
end
else begin
code_gen_en_r <= code_gen_en;
end
end
// Save 13 ca-code bits
always @(posedge gps_clk_slow)begin
if(rst_combined | codeGenPosEdge)begin
ca_bit_count <= 0;
end
else begin
if(ca_bit_count < 4'd13)begin
ca_bit_count <= ca_bit_count + 1;
ca_code <= {ca_code[11:0], ca_code_bit};
end
end
end
// Generate P-code
wire p_code_bit;
pcode p(
gps_clk_fast,
rst_combined,
code_gen_en,
sv_num,
p_code_bit
);
// Save 128 p-code bits, encrypt and send as l_code
reg [127:0] p_pt;
always @(posedge gps_clk_fast)begin
if(rst_combined | startRoundPosEdge)begin
p_bit_count <= 0;
end
else begin
if(p_bit_count < 8'd128)begin
p_bit_count <= p_bit_count + 1;
p_pt <= {p_pt [126:0], p_code_bit};
end
end
end
assign p_code = p_pt;
reg encrypt;
always @(posedge gps_clk_fast)begin
encrypt <= 0;
if(p_bit_count == 8'd127)
encrypt <= 1'b1;
end
aes_192 aes (
gps_clk_fast,
encrypt,
p_pt,
192'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
l_code,
l_code_valid
);
endmodule
|
/*
*
* Clock generation for GPS modules
* 10.23 MHz for P-code and 1.023 MHz for C/A code
*
*/
module gps_clkgen (
sys_clk_50,
sync_rst_in,
gps_clk_fast,
gps_clk_slow,
gps_rst
);
input sys_clk_50;
input sync_rst_in;
output gps_clk_fast;
output gps_clk_slow;
output gps_rst;
`ifdef SYNTHESIS
wire clk_fb;
wire clk_out0_prebufg, clk_out0;
wire locked_int;
MMCME2_ADV
#(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (16.750),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (81.875),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (20.000))
mmcm_adv_inst (
.CLKFBOUT (clk_fb),
.CLKOUT0 (clk_out0),
.CLKFBIN (clk_fb),
.CLKIN1 (sys_clk_50),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DWE (1'b0),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.LOCKED (locked_int),
.PWRDWN (1'b0),
.RST (1'b0)
);
// BUFG gps_clk_fast_buf (
// .O (clk_out0),
// .I (clk_out0_prebufg));
assign gps_clk_fast = clk_out0;
assign gps_rst = sync_rst_in | ~locked_int;
// Generate slow clock using CE
BUFGCE gps_clk_slow_buf(
.O (gps_clk_slow),
.CE (enable_slow_clk),
.I (clk_out0_prebufg)
);
reg [2:0] count = 3'h0;
reg enable_slow_clk;
always @(posedge clk_out0) begin
enable_slow_clk <= 1'b0;
if(count == 3'h4) begin
count <= 3'h0;
enable_slow_clk <= 1'b1;
end
else begin
count <= count + 3'h1;
end
end
`else
assign gps_clk_fast = sys_clk_50;
reg [2:0] count = 3'h0;
reg gps_clk_slow_r = 1'b0;
always @(posedge gps_clk_fast) begin
if(count == 3'h4) begin
count <= 3'h0;
gps_clk_slow_r <= ~gps_clk_slow_r;
end
else begin
count <= count + 3'h1;
end
end
assign gps_clk_slow = gps_clk_slow_r;
assign gps_rst = sync_rst_in;
`endif
endmodule // gps_clkgen
|
module gps_clkgen_test (fast, slow, rst);
output fast, slow, rst;
reg clk = 0;
always
#10 clk <= ~clk;
reg rst_o = 0;
initial begin
#1;
repeat (32) @(negedge clk)
rst_o <= 0;
repeat (32) @(negedge clk)
rst_o <= 1;
repeat (32) @(negedge clk)
rst_o <= 0;
end
gps_clkgen dut(clk, ~clk, rst_o, fast, slow, rst);
endmodule
|
module gps_test ();
reg clk = 0;
always
#10 clk <= ~clk;
reg start = 0;
reg rst_o = 0;
initial begin
#1;
repeat (32) @(negedge clk)
rst_o <= 0;
repeat (32) @(negedge clk)
rst_o <= 1;
repeat (32) @(negedge clk)
rst_o <= 0;
repeat (32) @(negedge clk)
start <= 1;
end
wire [12:0] ca_code;
wire [127:0] p_code, l_code;
wire l_code_valid;
gps gps(clk,~clk,rst_o,6'd12,start,ca_code,p_code,l_code,l_code_valid);
endmodule
|
module gps_top (
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg genNext;
wire [12:0] ca_code;
wire [127:0] p_code;
wire [127:0] l_code;
wire codes_valid;
// Implement GPS I/O memory map interface
// Write side
always @(posedge wb_clk_i) begin
if(wb_rst_i) begin
genNext <= 0;
end
else if(wb_stb_i & wb_we_i)
case(wb_adr_i[5:2])
0: genNext <= wb_dat_i[0];
default: ;
endcase
end // always @ (posedge wb_clk_i)
// Implement GPS I/O memory map interface
// Read side
always @(*) begin
case(wb_adr_i[5:2])
0: wb_dat_o = {31'b0, codes_valid};
1: wb_dat_o = {19'b0, ca_code};
2: wb_dat_o = p_code[31:0];
3: wb_dat_o = p_code[63:32];
4: wb_dat_o = p_code[95:64];
5: wb_dat_o = p_code[127:96];
6: wb_dat_o = l_code[31:0];
7: wb_dat_o = l_code[63:32];
8: wb_dat_o = l_code[95:64];
9: wb_dat_o = l_code[127:96];
default: wb_dat_o = 32'b0;
endcase
end // always @ (*)
gps gps(
wb_clk_i,
wb_rst_i,
6'd12,
genNext,
ca_code,
p_code,
l_code,
codes_valid
);
endmodule
|
module pcode(
clk, rst, en, sat,
preg
);
parameter SAT_WIDTH = 6;
parameter SREG_WIDTH = 37;
parameter XREG_WIDTH = 12;
//parameter PREG_WIDTH = 32;
parameter ini_x1a=12'b001001001000;
parameter ini_x1b=12'b010101010100;
parameter ini_x2a=12'b100100100101;
parameter ini_x2b=12'b010101010100;
input clk;
input rst;
input en;
input [ SAT_WIDTH-1:0] sat;
`ifdef PREG_WIDTH
output reg [PREG_WIDTH-1:0] preg;
`else
output reg preg;
`endif
reg[XREG_WIDTH-1:0] x1a;
reg[XREG_WIDTH-1:0] x1b;
reg[XREG_WIDTH-1:0] x2a;
reg[XREG_WIDTH-1:0] x2b;
reg[SREG_WIDTH-1:0] sreg;
wire x1a_rst, x1b_rst, x2a_rst, x2b_rst;
wire x1a_cnt_d, x1b_cnt_d, x2a_cnt_d, x2b_cnt_d, x_cnt_d, z_cnt_eow, z_cnt_sow;
reg[XREG_WIDTH-1:0] x1a_cnt, x1b_cnt, x2a_cnt, x2b_cnt;
reg[SAT_WIDTH-1:0] x_cnt;
reg[18:0] z_cnt;
reg x1b_en, x2a_en, x2b_en;
wire x1b_res, x2a_res, x2b_res;
wire x1b_halt, x2a_halt, x2b_halt;
//////////////////////////////////////////
//Control Signals
//////////////////////////////////////////
assign x1b_res = x1a_cnt_d & x1a_rst;
assign x1b_halt= x1b_cnt_d & x1b_rst;
assign x2a_res = z_cnt_sow|x_cnt_d;
assign x2a_halt= (z_cnt_eow|x2a_cnt_d) & x2a_rst;
assign x2b_res = x2a_res;
assign x2b_halt= (z_cnt_eow|x2b_cnt_d) & x2b_rst;
//////////////////////////////////////////
//Clock Control Signals
//////////////////////////////////////////
always @(posedge clk) begin
if(rst)
x1b_en<=1;
else if(en) begin
if(x1b_halt)
x1b_en<=0;
else if(x1b_res)
x1b_en<=1;
end
end
always @(posedge clk) begin
if(rst)
x2a_en<=1;
else if(en) begin
if(x2a_halt)
x2a_en<=0;
else if(x2a_res)
x2a_en<=1;
end
end
always @(posedge clk) begin
if(rst)
x2b_en<=1;
else if(en) begin
if(x2b_halt)
x2b_en<=0;
else if(x2b_res)
x2b_en<=1;
end
end
//////////////////////////////////////////
//Decoders
//////////////////////////////////////////
assign x1a_rst = (x1a==12'd4092) ? 1:0;
assign x1b_rst = (x1b==12'd4093) ? 1:0;
assign x2a_rst = (x2a==12'd4092) ? 1:0;
assign x2b_rst = (x2b==12'd4093) ? 1:0;
//////////////////////////////////////////
//Counters
//////////////////////////////////////////
assign x1a_cnt_d = (x1a_cnt==12'd3750) ? 1:0;
assign x1b_cnt_d = (x1b_cnt==12'd3749) ? 1:0;
assign x2a_cnt_d = (x2a_cnt==12'd3750) ? 1:0;
assign x2b_cnt_d = (x2b_cnt==12'd3749) ? 1:0;
assign x_cnt_d = (x_cnt ==6'd37) ? 1:0;
assign z_cnt_sow = ((z_cnt ==19'd000000)& x1b_res==1) ? 1:0;
assign z_cnt_eow = ((z_cnt ==19'd403200)& x1b_res==1) ? 1:0;
always @(posedge clk) begin
if(rst)
x1a_cnt <=0;
else if(en & x1a_rst) begin
if(x1a_cnt < 12'd3750)
x1a_cnt <= x1a_cnt+1;
else
x1a_cnt <= 12'd0;
end
end
always @(posedge clk) begin
if(rst)
x1b_cnt <=0;
else if(en &x1b_rst) begin
if(x1b_cnt < 12'd3749)
x1b_cnt <= x1b_cnt+1;
else
x1b_cnt <= 12'd0;
end
end
always @(posedge clk) begin
if(rst)
x2a_cnt<=0;
else if(en &x2a_rst) begin
if(x2a_cnt < 12'd3750)
x2a_cnt <= x2a_cnt+1;
else
x2a_cnt <=12'd0;
end
end
always @(posedge clk) begin
if(rst)
x2b_cnt <=0;
else if(en &x2b_rst) begin
if(x2b_cnt < 12'd3749)
x2b_cnt <= x2b_cnt+1;
else
x2b_cnt <=12'd0;
end
end
always @(posedge clk) begin
if(rst)
x_cnt<=0;
else if(en & x2a_res & x2a_cnt_d) begin
if(x_cnt < 6'd37)
x_cnt <= x_cnt+1;
else
x_cnt <=19'd0;
end
end
always @(posedge clk) begin
if(rst)
z_cnt<=0;
else if(en & x1b_res) begin
if(z_cnt < 19'd403200)
z_cnt <= z_cnt+1;
else
z_cnt <=19'd0;
end
end
//////////////////////////////////////////
//4 shift registers
//////////////////////////////////////////
always @(posedge clk) begin
if(rst|x1a_rst)
x1a<=ini_x1a;
else if(en)
x1a<={x1a[XREG_WIDTH-2:0],x1a[5]^x1a[7]^x1a[10]^x1a[11]};
end
always @(posedge clk) begin
if(rst|x1b_rst)
x1b<=ini_x1b;
else if (en & x1b_en)
x1b<={x1b[XREG_WIDTH-2:0],x1b[0]^x1b[1]^x1b[4]^x1b[7]^x1b[8]^x1b[9]^x1b[10]^x1b[11]};
end
always @(posedge clk) begin
if(rst|x2a_rst)
x2a<=ini_x2a;
else if (en & x2a_en)
x2a<={x2a[XREG_WIDTH-2:0],x2a[0]^x2a[2]^x2a[3]^x2a[4]^x2a[6]^x2a[7]^x2a[8]^x2a[9]^x2a[10]^x2a[11]};
end
always @(posedge clk) begin
if(rst|x2b_rst)
x2b<=ini_x2b;
else if (en & x2b_en)
x2b<={x2b[XREG_WIDTH-2:0],x2b[1]^x2b[2]^x2b[3]^x2b[7]^x2b[8]^x2b[11]};
end
//Output
always @(posedge clk) begin
if(rst)
sreg<=32'b0;
else if(en)
sreg<={sreg[SREG_WIDTH-2:0],(x2a[XREG_WIDTH-1]^x2b[XREG_WIDTH-1])};
end
always @(posedge clk) begin
if(rst)
`ifdef PREG_WIDTH
preg<=32'b0;
`else
preg<=1'b0;
`endif
else if(en)
`ifdef PREG_WIDTH
preg<={preg[PREG_WIDTH-2:0],(x1a[XREG_WIDTH-1]^x1b[XREG_WIDTH-1])^sreg[sat]};
`else
preg<={(x1a[XREG_WIDTH-1]^x1b[XREG_WIDTH-1])^sreg[sat]};
`endif
end
endmodule
|
# GPS code generator
Generates three codes used for GPS signal correlation (from the perspective of a space vehicle): C/A-code, P-code, and a secure form of P-code that we call L-code. The combination of the P-code generator and the L-code is meant to serve as a surrogate for the M-code generator found in modern secure GPS systems. The goal of this core is to provide reference implementations for items that a GPS designer would like to protect from an untrusted manufacturer; it is not a fully-functional GPS unit.
## Protected secrets:
* Length of P-code generator
* Position of taps for P-code generator
* Initial value used by P-code generator
* Symmetric key used for creating L-code
## References
* https://www.mitre.org/publications/technical-papers/overview-of-the-gps-m-code-signal
* https://natronics.github.io/blag/2014/gps-prn/
* https://github.com/kristianpaul/gnsssdr/blob/master/ARM_FPGA_PROJECTS/Xilinx_ISE_14.1_namuru_project_for_async_memory_bus/code_gen.v
* http://www.ohio.edu/people/starzykj/network/research/Papers/Recent%20conferences/Pcode_Generator_FPGA_FPLA2002.pdf
* https://etd.ohiolink.edu/!etd.send_file?accession=ohiou1177700503&disposition=inline
* https://www.navcen.uscg.gov/pubs/gps/icd200/ICD200Cw1234.pdf
* https://www.google.com/patents/US5068872
* http://www.google.com.pg/patents/US5202694
* https://www.google.com/patents/US6567042
|
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/100ps
//------------------------------------------------------------------
// Test module.
//------------------------------------------------------------------
module tb_pcode();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// Debug output control.
parameter DEBUG = 0;
parameter VCD = 1;
// Clock defines.
localparam CLK_HALF_PERIOD = 1;
localparam CLK_PERIOD = 2 * CLK_HALF_PERIOD;
localparam SAT_WIDTH = 6;
localparam SREG_WIDTH = 37;
localparam XREG_WIDTH = 12;
//localparam PREG_WIDTH = 32;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_rst;
reg tb_en;
reg [ SAT_WIDTH-1:0] tb_sat;
reg [XREG_WIDTH-1:0] tb_x1a;
reg [XREG_WIDTH-1:0] tb_x1b;
reg [XREG_WIDTH-1:0] tb_x2a;
reg [XREG_WIDTH-1:0] tb_x2b;
`ifdef PREG_WIDTH
wire [PREG_WIDTH-1:0]tb_preg;
`else
wire tb_preg;
`endif
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
pcode dut(
.clk(tb_clk),
.rst(tb_rst),
.en(tb_en),
.sat(tb_sat),
.preg(tb_preg)
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// rst_dut()
//
// Toggle rst to put the DUT into a well known state.
//----------------------------------------------------------------
task rst_dut();
begin
$display("*** Toggle rst.");
tb_rst = 1;
#(2 * CLK_PERIOD);
tb_rst = 0;
$display("");
end
endtask // rst_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim();
begin
tb_clk = 0;
tb_rst = 0;
tb_en = 0;
tb_sat = 6'b000000;
end
endtask // init_sim
//----------------------------------------------------------------
// timing_verification
//----------------------------------------------------------------
task timing_verification();
begin
tb_rst=1;
#(2*CLK_PERIOD);
tb_rst=0;
tb_en = 1;
#(1000*CLK_PERIOD);
tb_en = 0;
#(1000*CLK_PERIOD);
tb_en = 1;
#(1000*CLK_PERIOD);
#(100000*CLK_PERIOD);
/*
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
#(100000*CLK_PERIOD);
*/
end
endtask // timing_verification
//----------------------------------------------------------------
// main
//----------------------------------------------------------------
initial
begin : main
if(VCD) begin
$dumpfile("./iverilog/tb_pcode.vcd");
$dumpvars(0,tb_pcode);
//$dumpvars(1,tb_clk, tb_rst, tb_cs, tb_we, tb_address, tb_write_data, tb_read_data);
end
$display(" -= Testbench for pcode started =-");
$display(" =================================");
$display("");
init_sim();
rst_dut();
timing_verification();
$display("");
$display("*** pcode simulation done. ***");
$finish;
end // main
endmodule // tb_modexp
//======================================================================
// EOF tb_modexp.v
//======================================================================
|
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Defines of the Core ////
//// ////
//// Known problems (limits): ////
//// None ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - gorban@opencores.org ////
//// - Jacob Gorban ////
//// - Igor Mohor (igorm@opencores.org) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Timescale define
`timescale 1ns/10ps
|
/* Copyright (c) 2016-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* ============================================================================
*
* Configuration struct
*
* This is the static configuration struct. It contains all global configuration
* settings and is propagated through the hierarchy.
*
* There are two struct: The base_config_t struct contains all configuration
* settings. It is used to setup the system. The config_t struct contains some
* extra settings, which are derived from the base settings. You can call the
* function derive_config to convert a base_config_t struct into a config_t.
*
* When you add a base variable you need to add it at three positions:
*
* - In base_config_t
* - In config_t
* - The copy operation in derive_config
*
* If it is a derived setting, you only need to add it to the latter two.
*
* Author(s):
* Stefan Wallentowitz <stefan@wallentowitz.de>
*/
package optimsoc_config;
import optimsoc_functions::*;
typedef enum { EXTERNAL, PLAIN } lmem_style_t;
typedef struct packed {
// System configuration
integer NUMTILES;
integer NUMCTS;
logic [63:0][15:0] CTLIST;
integer CORES_PER_TILE;
integer GMEM_SIZE;
integer GMEM_TILE;
// NoC-related configuration
logic NOC_ENABLE_VCHANNELS;
// Tile configuration
integer LMEM_SIZE;
lmem_style_t LMEM_STYLE;
logic ENABLE_BOOTROM;
integer BOOTROM_SIZE;
logic ENABLE_DM;
integer DM_BASE;
integer DM_SIZE;
logic ENABLE_PGAS;
integer PGAS_BASE;
integer PGAS_SIZE;
// Network adapter configuration
logic NA_ENABLE_MPSIMPLE;
logic NA_ENABLE_DMA;
logic NA_DMA_GENIRQ;
integer NA_DMA_ENTRIES;
// Debug configuration
logic USE_DEBUG;
logic DEBUG_STM;
logic DEBUG_CTM;
integer DEBUG_SUBNET_BITS;
integer DEBUG_LOCAL_SUBNET;
integer DEBUG_ROUTER_BUFFER_SIZE;
integer DEBUG_MAX_PKT_LEN;
} base_config_t;
typedef struct packed {
// System configuration
integer NUMTILES;
integer NUMCTS;
logic [63:0][15:0] CTLIST;
integer CORES_PER_TILE;
integer GMEM_SIZE;
integer GMEM_TILE;
// -> derived
integer TOTAL_NUM_CORES;
// NoC-related configuration
logic NOC_ENABLE_VCHANNELS;
// -> derived
integer NOC_FLIT_WIDTH;
integer NOC_CHANNELS;
// Tile configuration
integer LMEM_SIZE;
lmem_style_t LMEM_STYLE;
logic ENABLE_BOOTROM;
integer BOOTROM_SIZE;
logic ENABLE_DM;
integer DM_BASE;
integer DM_SIZE;
logic ENABLE_PGAS;
integer DM_RANGE_WIDTH;
integer DM_RANGE_MATCH;
integer PGAS_BASE;
integer PGAS_SIZE;
integer PGAS_RANGE_WIDTH;
integer PGAS_RANGE_MATCH;
// Network adapter configuration
logic NA_ENABLE_MPSIMPLE;
logic NA_ENABLE_DMA;
logic NA_DMA_GENIRQ;
integer NA_DMA_ENTRIES;
// Debug configuration
logic USE_DEBUG;
logic DEBUG_STM;
logic DEBUG_CTM;
integer DEBUG_SUBNET_BITS;
integer DEBUG_LOCAL_SUBNET;
integer DEBUG_ROUTER_BUFFER_SIZE;
integer DEBUG_MAX_PKT_LEN;
// -> derived
integer DEBUG_MODS_PER_CORE;
integer DEBUG_MODS_PER_TILE;
integer DEBUG_NUM_MODS;
} config_t;
function config_t derive_config(base_config_t conf);
// Copy the basic parameters
derive_config.NUMTILES = conf.NUMTILES;
derive_config.NUMCTS = conf.NUMCTS;
derive_config.CTLIST = conf.CTLIST;
derive_config.CORES_PER_TILE = conf.CORES_PER_TILE;
derive_config.GMEM_SIZE = conf.GMEM_SIZE;
derive_config.GMEM_TILE = conf.GMEM_TILE;
derive_config.NOC_ENABLE_VCHANNELS = conf.NOC_ENABLE_VCHANNELS;
derive_config.LMEM_SIZE = conf.LMEM_SIZE;
derive_config.LMEM_STYLE = conf.LMEM_STYLE;
derive_config.ENABLE_BOOTROM = conf.ENABLE_BOOTROM;
derive_config.BOOTROM_SIZE = conf.BOOTROM_SIZE;
derive_config.ENABLE_DM = conf.ENABLE_DM;
derive_config.DM_BASE = conf.DM_BASE;
derive_config.DM_SIZE = conf.DM_SIZE;
derive_config.ENABLE_PGAS = conf.ENABLE_PGAS;
derive_config.PGAS_BASE = conf.PGAS_BASE;
derive_config.PGAS_SIZE = conf.PGAS_SIZE;
derive_config.NA_ENABLE_MPSIMPLE = conf.NA_ENABLE_MPSIMPLE;
derive_config.NA_ENABLE_DMA = conf.NA_ENABLE_DMA;
derive_config.NA_DMA_GENIRQ = conf.NA_DMA_GENIRQ;
derive_config.NA_DMA_ENTRIES = conf.NA_DMA_ENTRIES;
derive_config.USE_DEBUG = conf.USE_DEBUG;
derive_config.DEBUG_STM = conf.DEBUG_STM;
derive_config.DEBUG_CTM = conf.DEBUG_CTM;
derive_config.DEBUG_SUBNET_BITS = conf.DEBUG_SUBNET_BITS;
derive_config.DEBUG_LOCAL_SUBNET = conf.DEBUG_LOCAL_SUBNET;
derive_config.DEBUG_ROUTER_BUFFER_SIZE = conf.DEBUG_ROUTER_BUFFER_SIZE;
derive_config.DEBUG_MAX_PKT_LEN = conf.DEBUG_MAX_PKT_LEN;
// Derive the other parameters
derive_config.TOTAL_NUM_CORES = conf.NUMCTS * conf.CORES_PER_TILE;
derive_config.DM_RANGE_WIDTH = conf.ENABLE_DM ? 32-clog2_width(conf.DM_SIZE) : 1;
derive_config.DM_RANGE_MATCH = conf.DM_BASE >> (32-derive_config.DM_RANGE_WIDTH);
derive_config.PGAS_RANGE_WIDTH = conf.ENABLE_PGAS ? 32-clog2_width(conf.PGAS_SIZE) : 1;
derive_config.PGAS_RANGE_MATCH = conf.PGAS_BASE >> (32-derive_config.PGAS_RANGE_WIDTH);
derive_config.DEBUG_MODS_PER_CORE = (int'(conf.DEBUG_STM) + int'(conf.DEBUG_CTM)) * int'(conf.USE_DEBUG);
derive_config.DEBUG_MODS_PER_TILE = conf.USE_DEBUG *
(1 /* MAM */
+ derive_config.DEBUG_MODS_PER_CORE * conf.CORES_PER_TILE);
derive_config.DEBUG_NUM_MODS = conf.USE_DEBUG *
(1 /* SCM */
+ conf.NUMCTS * derive_config.DEBUG_MODS_PER_TILE);
// Those are supposed to be variables, but are constant at least for now
derive_config.NOC_CHANNELS = 2;
derive_config.NOC_FLIT_WIDTH = 32;
endfunction // DERIVE_CONFIG
endpackage // optimsoc
|
/* Copyright (c) 2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Constants
*
* Author(s):
* Stefan Wallentowitz <stefan@wallentowitz.de>
*/
package optimsoc_constants;
// Maximum packet length
localparam NOC_MAX_LEN = 32;
// NoC packet header
// Mandatory fields
localparam NOC_DEST_MSB = 31;
localparam NOC_DEST_LSB = 27;
localparam NOC_CLASS_MSB = 26;
localparam NOC_CLASS_LSB = 24;
localparam NOC_SRC_MSB = 23;
localparam NOC_SRC_LSB = 19;
// Classes
localparam NOC_CLASS_LSU = 3'h2;
// NoC LSU
localparam NOC_LSU_MSGTYPE_MSB = 18;
localparam NOC_LSU_MSGTYPE_LSB = 16;
localparam NOC_LSU_MSGTYPE_READREQ = 3'h0;
localparam NOC_LSU_SIZE_IDX = 15;
localparam NOC_LSU_SIZE_SINGLE = 0;
localparam NOC_LSU_SIZE_BURST = 1;
endpackage // constants
|
/* Copyright (c) 2013 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* System-wide definitions for an OpTiMSoC system instance.
*
* Author(s):
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*/
// Number of virtual channels
`define VCHANNELS 3
// Assign virtual channels to services
`define VCHANNEL_LSU_REQ 'x
`define VCHANNEL_LSU_RESP 'x
`define VCHANNEL_DMA_REQ 0
`define VCHANNEL_DMA_RESP 1
`define VCHANNEL_MPSIMPLE 2
`define OPTIMSOC_XDIM 2
`define OPTIMSOC_YDIM 2
`define OPTIMSOC_SRAM_IMPLEMENTATION "PLAIN"
`define OPTIMSOC_SRAM_VALIDATE_ADDRESS 1
|
/* Copyright (c) 2013-2018 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* ============================================================================
*
* Utility functions
*
* Author(s):
* Philipp Wagner <philipp.wagner@tum.de>
* Stefan Wallentowitz <stefan@wallentowitz.de>
*/
package optimsoc_functions;
/**
* Math function: $clog2 as specified in Verilog-2005
*
* clog2 = 0 for value == 0
* ceil(log2(value)) for value >= 1
*
* This implementation is a synthesizable variant of the $clog2 function as
* specified in the Verilog-2005 standard (IEEE 1364-2005).
*
* To quote the standard:
* The system function $clog2 shall return the ceiling of the log
* base 2 of the argument (the log rounded up to an integer
* value). The argument can be an integer or an arbitrary sized
* vector value. The argument shall be treated as an unsigned
* value, and an argument value of 0 shall produce a result of 0.
*/
function automatic integer clog2;
input integer value;
begin
value = value - 1;
for (clog2 = 0; value > 0; clog2 = clog2 + 1) begin
value = value >> 1;
end
end
endfunction
/**
* Math function: enhanced clog2 function
*
* 0 for value == 0
* clog2_width = 1 for value == 1
* ceil(log2(value)) for value > 1
*
*
* This function is a variant of the clog2() function, which returns 1 if the
* input value is 1. In all other cases it behaves exactly like clog2().
* This is useful to define registers which are wide enough to contain
* "value" values.
*
* Example 1:
* parameter ITEMS = 1;
* localparam ITEMS_WIDTH = clog2_width(ITEMS); // 1
* reg [ITEMS_WIDTH-1:0] item_register; // items_register is now [0:0]
*
* Example 2:
* parameter ITEMS = 64;
* localparam ITEMS_WIDTH = clog2_width(ITEMS); // 6
* reg [ITEMS_WIDTH-1:0] item_register; // items_register is now [5:0]
*
* Note: I if you want to store the number "value" inside a
* register, you need a register with size clog2(value + 1), since
* you also need to store the number 0.
*
* Example 3:
* reg [clog2_width(64) - 1 : 0] store_64_items; // width is [5:0]
* reg [clog2_width(64 + 1) - 1 : 0] store_number_64; // width is [6:0]
*/
function automatic integer clog2_width;
input integer value;
begin
if (value == 1) begin
clog2_width = 1;
end else begin
clog2_width = clog2(value);
end
end
endfunction
function automatic [23:0] index2string;
input integer index;
integer hundreds;
integer tens;
integer ones;
begin
hundreds = index / 100;
tens = (index - (hundreds * 100)) / 10;
ones = (index - (hundreds * 100) - (tens * 10));
index2string[23:16] = hundreds[7:0] + 8'd48;
index2string[15:8] = tens[7:0] + 8'd48;
index2string[7:0] = ones[7:0] + 8'd48;
end
endfunction
endpackage // functions
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a round-robin arbiter for N participants, which is a
* parameter. The arbiter itself contains no register but is purely
* combinational which allows for various use cases. It simply
* calculates the next grant (nxt_gnt) based on the current grant
* (gnt) and the requests (req).
*
* That means, the gnt should in general be a register and especially
* there must be no combinational path from nxt_gnt to gnt!
*
* The normal usage is something like registering the gnt from
* nxt_gnt. Furthermore it is important that the gnt has an initial
* value which also must be one hot!
*
* Author(s):
* Stefan Wallentowitz <stefan@wallentowitz.de>
*/
module arb_rr
#(parameter N = 2)
(
input [N-1:0] req,
input en,
input [N-1:0] gnt,
output [N-1:0] nxt_gnt
);
// At a first glance, the computation of the nxt_gnt signal looks
// strange, but the principle is easy:
//
// * For each participant we compute a mask of width N. Based on
// the current gnt signal the mask contains a 1 at the position
// of other participants that will be served in round robin
// before the participant in case they request it.
//
// * The mask is 0 on all positions for the participant "left" of
// the currently granted participant as no other has precedence
// over this one. The mask has all one except the participant
// itself for the currently arbitrated participant.
//
// * From the mask and the request the nxt_gnt is calculated,
// roughly said as: if there is no other participant which has a
// higher precedence that also requests, the participant gets
// granted.
//
// Example 1:
// req = 1010
// gnt = 1000
// nxt_gnt = 0010
//
// mask[0] = 0000
// mask[1] = 0001
// mask[2] = 0011
// mask[3] = 0111
//
// Example 2:
// req = 1010
// gnt = 0100
// nxt_gnt = 1000
//
// mask[0] = 1000
// mask[1] = 1001
// mask[2] = 1011
// mask[3] = 0000
// Mask net
reg [N-1:0] mask [0:N-1];
// Calculate the mask
always @(*) begin : calc_mask
integer i,j;
for (i=0;i<N;i=i+1) begin
// Initialize mask as 0
mask[i] = {N{1'b0}};
// All participants to the "right" up to the current grant
// holder have precendence and therefore a 1 in the mask.
// First check if the next right from us has the grant.
// Afterwards the mask is calculated iteratively based on
// this.
if(i>0)
// For i=N:1 the next right is i-1
mask[i][i-1] = ~gnt[i-1];
else
// For i=0 the next right is N-1
mask[i][N-1] = ~gnt[N-1];
// Now the mask contains a 1 when the next right to us is not
// the grant holder. If it is the grant holder that means,
// that we are the next served (if necessary) as no other has
// higher precendence, which is then calculated in the
// following by filling up 1s up to the grant holder. To stop
// filling up there and not fill up any after this is
// iterative by always checking if the one before was not
// before the grant holder.
for (j=2;j<N;j=j+1) begin
if (i-j>=0)
mask[i][i-j] = mask[i][i-j+1] & ~gnt[i-j];
else if(i-j+1>=0)
mask[i][i-j+N] = mask[i][i-j+1] & ~gnt[i-j+N];
else
mask[i][i-j+N] = mask[i][i-j+N+1] & ~gnt[i-j+N];
end
end
end // always @ (*)
// Calculate the nxt_gnt
genvar k;
generate
for (k=0;k<N;k=k+1) begin : gen_nxt_gnt
// (mask[k] & req) masks all requests with higher precendence
// Example 1: 0: 0000 1: 0000 2: 0010 3: 0010
// Example 2: 0: 1000 1: 1000 2: 1010 3: 0000
//
// ~|(mask[k] & req) is there is none of them
// Example 1: 0: 1 1: 1 2: 0 3: 0
// Example 2: 1: 0 1: 0 2: 0 3: 1
//
// One might expect at this point that there was only one of
// them that matches, but this is guaranteed by the last part
// that is checking if this one has a request itself. In
// example 1, k=0 does not have a request, if it had, the
// result of the previous calculation would be 0 for k=1.
// Therefore: (~|(mask[k] & req) & req[k]) selects the next one.
// Example 1: 0: 0 1: 1 2: 0 3: 0
// Example 2: 0: 0 1: 0 2: 0 3: 1
//
// This is already the result. (0010 and 1000). Nevertheless,
// it is necessary to capture the case of no request at all
// (~|req). In that case, nxt_gnt would be 0, what iself
// leads to a problem in the next cycle (always grants).
// Therefore the current gnt is hold in case of no request by
// (~|req & gnt[k]).
//
// Finally, we only arbitrate when enable is set.
assign nxt_gnt[k] = en ? (~|(mask[k] & req) & req[k]) | (~|req & gnt[k])
: gnt[k];
end
endgenerate
endmodule // arb_rr
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* Generic round robin arbiter.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*
*/
module lisnoc_arb_rr(/*AUTOARG*/
// Outputs
nxt_gnt,
// Inputs
req, gnt
);
parameter N = 2;
input [N-1:0] req;
input [N-1:0] gnt;
output [N-1:0] nxt_gnt;
reg [N-1:0] mask [0:N-1];
integer i,j;
always @(*) begin
for (i=0;i<N;i=i+1) begin
mask[i] = {N{1'b0}};
if(i>0)
mask[i][i-1] = ~gnt[i-1];
else
mask[i][N-1] = ~gnt[N-1];
for (j=2;j<N;j=j+1) begin
if (i-j>=0)
mask[i][i-j] = mask[i][i-j+1] & ~gnt[i-j];
else if(i-j+1>=0)
mask[i][i-j+N] = mask[i][i-j+1] & ~gnt[i-j+N];
else
mask[i][i-j+N] = mask[i][i-j+N+1] & ~gnt[i-j+N];
end
end
end // always @ (*)
genvar k;
generate
for (k=0;k<N;k=k+1) begin
assign nxt_gnt[k] = (~|(mask[k] & req) & req[k]) | (~|req & gnt[k]);
end
endgenerate
endmodule // lisnoc_arb_rr
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is the toplevel file of the DMA controller.
*
* Author(s):
* Michael Tempelmeier <michael.tempelmeier@tum.de>
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*/
`include "lisnoc_dma_def.vh"
module lisnoc_dma(/*AUTOARG*/
// Outputs
noc_in_req_ready, noc_in_resp_ready, noc_out_req_flit,
noc_out_req_valid, noc_out_resp_flit, noc_out_resp_valid,
wb_if_dat_o, wb_if_ack_o, wb_if_err_o, wb_if_rty_o, wb_adr_o,
wb_dat_o, wb_cyc_o, wb_stb_o, wb_sel_o, wb_we_o, wb_cab_o,
wb_cti_o, wb_bte_o, irq,
// Inputs
clk, rst, noc_in_req_flit, noc_in_req_valid, noc_in_resp_flit,
noc_in_resp_valid, noc_out_req_ready, noc_out_resp_ready,
wb_if_adr_i, wb_if_dat_i, wb_if_cyc_i, wb_if_stb_i, wb_if_we_i,
wb_dat_i, wb_ack_i
);
parameter table_entries = 4;
localparam table_entries_ptrwidth = $clog2(table_entries);
parameter tileid = 0;
parameter noc_packet_size = 16;
parameter generate_interrupt = 1;
input clk;
input rst;
input [`FLIT_WIDTH-1:0] noc_in_req_flit;
input noc_in_req_valid;
output noc_in_req_ready;
input [`FLIT_WIDTH-1:0] noc_in_resp_flit;
input noc_in_resp_valid;
output noc_in_resp_ready;
output [`FLIT_WIDTH-1:0] noc_out_req_flit;
output noc_out_req_valid;
input noc_out_req_ready;
output [`FLIT_WIDTH-1:0] noc_out_resp_flit;
output noc_out_resp_valid;
input noc_out_resp_ready;
input [31:0] wb_if_adr_i;
input [31:0] wb_if_dat_i;
input wb_if_cyc_i;
input wb_if_stb_i;
input wb_if_we_i;
output [31:0] wb_if_dat_o;
output wb_if_ack_o;
output wb_if_err_o;
output wb_if_rty_o;
output reg [31:0] wb_adr_o;
output reg [31:0] wb_dat_o;
output reg wb_cyc_o;
output reg wb_stb_o;
output reg [3:0] wb_sel_o;
output reg wb_we_o;
output wb_cab_o;
output reg [2:0] wb_cti_o;
output reg [1:0] wb_bte_o;
input [31:0] wb_dat_i;
input wb_ack_i;
output [table_entries-1:0] irq;
assign wb_if_err_o = 1'b0;
assign wb_if_rty_o = 1'b0;
wire [31:0] wb_req_adr_o;
wire [31:0] wb_req_dat_o;
wire wb_req_cyc_o;
wire wb_req_stb_o;
wire wb_req_we_o;
wire [3:0] wb_req_sel_o;
wire [2:0] wb_req_cti_o;
wire [1:0] wb_req_bte_o;
reg [31:0] wb_req_dat_i;
reg wb_req_ack_i;
wire [31:0] wb_resp_adr_o;
wire [31:0] wb_resp_dat_o;
wire wb_resp_cyc_o;
wire wb_resp_stb_o;
wire wb_resp_we_o;
wire [3:0] wb_resp_sel_o;
wire [2:0] wb_resp_cti_o;
wire [1:0] wb_resp_bte_o;
reg [31:0] wb_resp_dat_i;
reg wb_resp_ack_i;
wire [31:0] wb_target_adr_o;
wire [31:0] wb_target_dat_o;
wire wb_target_cyc_o;
wire wb_target_stb_o;
wire wb_target_we_o;
wire [2:0] wb_target_cti_o;
wire [1:0] wb_target_bte_o;
reg [31:0] wb_target_dat_i;
reg wb_target_ack_i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire ctrl_done_en; // From ctrl_initiator of lisnoc_dma_initiator.v
wire [table_entries_ptrwidth-1:0] ctrl_done_pos;// From ctrl_initiator of lisnoc_dma_initiator.v
wire [table_entries_ptrwidth-1:0] ctrl_read_pos;// From ctrl_initiator of lisnoc_dma_initiator.v
wire [`DMA_REQUEST_WIDTH-1:0] ctrl_read_req; // From request_table of lisnoc_dma_request_table.v
wire [table_entries-1:0] done; // From request_table of lisnoc_dma_request_table.v
wire if_valid_en; // From wbinterface of lisnoc_dma_wbinterface.v
wire [table_entries_ptrwidth-1:0] if_valid_pos;// From wbinterface of lisnoc_dma_wbinterface.v
wire if_valid_set; // From wbinterface of lisnoc_dma_wbinterface.v
wire if_validrd_en; // From wbinterface of lisnoc_dma_wbinterface.v
wire if_write_en; // From wbinterface of lisnoc_dma_wbinterface.v
wire [table_entries_ptrwidth-1:0] if_write_pos;// From wbinterface of lisnoc_dma_wbinterface.v
wire [`DMA_REQUEST_WIDTH-1:0] if_write_req; // From wbinterface of lisnoc_dma_wbinterface.v
wire [`DMA_REQMASK_WIDTH-1:0] if_write_select;// From wbinterface of lisnoc_dma_wbinterface.v
wire [table_entries-1:0] valid; // From request_table of lisnoc_dma_request_table.v
wire [3:0] wb_target_sel_o; // From target of lisnoc_dma_target.v
// End of automatics
wire [table_entries_ptrwidth-1:0] ctrl_out_read_pos;
wire [table_entries_ptrwidth-1:0] ctrl_in_read_pos;
wire [table_entries_ptrwidth-1:0] ctrl_write_pos;
assign ctrl_out_read_pos = 0;
assign ctrl_in_read_pos = 0;
assign ctrl_write_pos = 0;
lisnoc_dma_wbinterface
#(.tileid(tileid))
wbinterface(/*AUTOINST*/
// Outputs
.wb_if_dat_o (wb_if_dat_o[31:0]),
.wb_if_ack_o (wb_if_ack_o),
.if_write_req (if_write_req[`DMA_REQUEST_WIDTH-1:0]),
.if_write_pos (if_write_pos[table_entries_ptrwidth-1:0]),
.if_write_select (if_write_select[`DMA_REQMASK_WIDTH-1:0]),
.if_write_en (if_write_en),
.if_valid_pos (if_valid_pos[table_entries_ptrwidth-1:0]),
.if_valid_set (if_valid_set),
.if_valid_en (if_valid_en),
.if_validrd_en (if_validrd_en),
// Inputs
.clk (clk),
.rst (rst),
.wb_if_adr_i (wb_if_adr_i[31:0]),
.wb_if_dat_i (wb_if_dat_i[31:0]),
.wb_if_cyc_i (wb_if_cyc_i),
.wb_if_stb_i (wb_if_stb_i),
.wb_if_we_i (wb_if_we_i),
.done (done[table_entries-1:0]));
lisnoc_dma_request_table
#(.generate_interrupt(generate_interrupt))
request_table(/*AUTOINST*/
// Outputs
.ctrl_read_req (ctrl_read_req[`DMA_REQUEST_WIDTH-1:0]),
.valid (valid[table_entries-1:0]),
.done (done[table_entries-1:0]),
.irq (irq[table_entries-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.if_write_req (if_write_req[`DMA_REQUEST_WIDTH-1:0]),
.if_write_pos (if_write_pos[table_entries_ptrwidth-1:0]),
.if_write_select (if_write_select[`DMA_REQMASK_WIDTH-1:0]),
.if_write_en (if_write_en),
.if_valid_pos (if_valid_pos[table_entries_ptrwidth-1:0]),
.if_valid_set (if_valid_set),
.if_valid_en (if_valid_en),
.if_validrd_en (if_validrd_en),
.ctrl_read_pos (ctrl_read_pos[table_entries_ptrwidth-1:0]),
.ctrl_done_pos (ctrl_done_pos[table_entries_ptrwidth-1:0]),
.ctrl_done_en (ctrl_done_en));
/* lisnoc_dma_initiator AUTO_TEMPLATE(
.noc_out_\(.*\) (noc_out_req_\1[]),
.noc_in_\(.*\) (noc_in_resp_\1[]),
); */
lisnoc_dma_initiator
#(.tileid(tileid))
ctrl_initiator(/*AUTOINST*/
// Outputs
.ctrl_read_pos (ctrl_read_pos[table_entries_ptrwidth-1:0]),
.ctrl_done_pos (ctrl_done_pos[table_entries_ptrwidth-1:0]),
.ctrl_done_en (ctrl_done_en),
.noc_out_flit (noc_out_req_flit[`FLIT_WIDTH-1:0]), // Templated
.noc_out_valid (noc_out_req_valid), // Templated
.noc_in_ready (noc_in_resp_ready), // Templated
.wb_req_cyc_o (wb_req_cyc_o),
.wb_req_stb_o (wb_req_stb_o),
.wb_req_we_o (wb_req_we_o),
.wb_req_dat_o (wb_req_dat_o[31:0]),
.wb_req_adr_o (wb_req_adr_o[31:0]),
.wb_req_cti_o (wb_req_cti_o[2:0]),
.wb_req_bte_o (wb_req_bte_o[1:0]),
.wb_req_sel_o (wb_req_sel_o[3:0]),
.wb_resp_cyc_o (wb_resp_cyc_o),
.wb_resp_stb_o (wb_resp_stb_o),
.wb_resp_we_o (wb_resp_we_o),
.wb_resp_dat_o (wb_resp_dat_o[31:0]),
.wb_resp_adr_o (wb_resp_adr_o[31:0]),
.wb_resp_cti_o (wb_resp_cti_o[2:0]),
.wb_resp_bte_o (wb_resp_bte_o[1:0]),
.wb_resp_sel_o (wb_resp_sel_o[3:0]),
// Inputs
.clk (clk),
.rst (rst),
.ctrl_read_req (ctrl_read_req[`DMA_REQUEST_WIDTH-1:0]),
.valid (valid[table_entries-1:0]),
.noc_out_ready (noc_out_req_ready), // Templated
.noc_in_flit (noc_in_resp_flit[`FLIT_WIDTH-1:0]), // Templated
.noc_in_valid (noc_in_resp_valid), // Templated
.wb_req_ack_i (wb_req_ack_i),
.wb_req_dat_i (wb_req_dat_i[31:0]),
.wb_resp_ack_i (wb_resp_ack_i),
.wb_resp_dat_i (wb_resp_dat_i[31:0]));
/* lisnoc_dma_target AUTO_TEMPLATE(
.noc_out_\(.*\) (noc_out_resp_\1[]),
.noc_in_\(.*\) (noc_in_req_\1[]),
.wb_\(.*\) (wb_target_\1[]),
); */
lisnoc_dma_target
#(.tileid(tileid),.noc_packet_size(noc_packet_size))
target(/*AUTOINST*/
// Outputs
.noc_out_flit (noc_out_resp_flit[`FLIT_WIDTH-1:0]), // Templated
.noc_out_valid (noc_out_resp_valid), // Templated
.noc_in_ready (noc_in_req_ready), // Templated
.wb_cyc_o (wb_target_cyc_o), // Templated
.wb_stb_o (wb_target_stb_o), // Templated
.wb_we_o (wb_target_we_o), // Templated
.wb_dat_o (wb_target_dat_o[31:0]), // Templated
.wb_adr_o (wb_target_adr_o[31:0]), // Templated
.wb_sel_o (wb_target_sel_o[3:0]), // Templated
.wb_cti_o (wb_target_cti_o[2:0]), // Templated
.wb_bte_o (wb_target_bte_o[1:0]), // Templated
// Inputs
.clk (clk),
.rst (rst),
.noc_out_ready (noc_out_resp_ready), // Templated
.noc_in_flit (noc_in_req_flit[`FLIT_WIDTH-1:0]), // Templated
.noc_in_valid (noc_in_req_valid), // Templated
.wb_ack_i (wb_target_ack_i), // Templated
.wb_dat_i (wb_target_dat_i[31:0])); // Templated
localparam wb_arb_req = 2'b00, wb_arb_resp = 2'b01, wb_arb_target = 2'b10;
reg [1:0] wb_arb;
reg [1:0] nxt_wb_arb;
always @(posedge clk) begin
if (rst) begin
wb_arb <= wb_arb_target;
end else begin
wb_arb <= nxt_wb_arb;
end
end
wire wb_arb_active;
assign wb_arb_active = ((wb_arb == wb_arb_req) & wb_req_cyc_o) |
((wb_arb == wb_arb_resp) & wb_resp_cyc_o) |
((wb_arb == wb_arb_target) & wb_target_cyc_o);
always @(*) begin
if (wb_arb_active) begin
nxt_wb_arb = wb_arb;
end else begin
if (wb_target_cyc_o) begin
nxt_wb_arb = wb_arb_target;
end else if (wb_resp_cyc_o) begin
nxt_wb_arb = wb_arb_resp;
end else if (wb_req_cyc_o) begin
nxt_wb_arb = wb_arb_req;
end else begin
nxt_wb_arb = wb_arb_target;
end
end
end
assign wb_cab_o = 1'b0;
always @(*) begin
if (wb_arb == wb_arb_target) begin
wb_adr_o = wb_target_adr_o;
wb_dat_o = wb_target_dat_o;
wb_cyc_o = wb_target_cyc_o;
wb_stb_o = wb_target_stb_o;
wb_sel_o = wb_target_sel_o;
wb_we_o = wb_target_we_o;
wb_bte_o = wb_target_bte_o;
wb_cti_o = wb_target_cti_o;
wb_target_ack_i = wb_ack_i;
wb_target_dat_i = wb_dat_i;
wb_req_ack_i = 1'b0;
wb_req_dat_i = 32'hx;
wb_resp_ack_i = 1'b0;
wb_resp_dat_i = 32'hx;
end else if (wb_arb == wb_arb_resp) begin
wb_adr_o = wb_resp_adr_o;
wb_dat_o = wb_resp_dat_o;
wb_cyc_o = wb_resp_cyc_o;
wb_stb_o = wb_resp_stb_o;
wb_sel_o = wb_resp_sel_o;
wb_we_o = wb_resp_we_o;
wb_bte_o = wb_resp_bte_o;
wb_cti_o = wb_resp_cti_o;
wb_resp_ack_i = wb_ack_i;
wb_resp_dat_i = wb_dat_i;
wb_req_ack_i = 1'b0;
wb_req_dat_i = 32'hx;
wb_target_ack_i = 1'b0;
wb_target_dat_i = 32'hx;
end else if (wb_arb == wb_arb_req) begin
wb_adr_o = wb_req_adr_o;
wb_dat_o = wb_req_dat_o;
wb_cyc_o = wb_req_cyc_o;
wb_stb_o = wb_req_stb_o;
wb_sel_o = wb_req_sel_o;
wb_we_o = wb_req_we_o;
wb_bte_o = wb_req_bte_o;
wb_cti_o = wb_req_cti_o;
wb_req_ack_i = wb_ack_i;
wb_req_dat_i = wb_dat_i;
wb_resp_ack_i = 1'b0;
wb_resp_dat_i = 32'hx;
wb_target_ack_i = 1'b0;
wb_target_dat_i = 32'hx;
end else begin // if (wb_arb == wb_arb_req)
wb_adr_o = 32'h0;
wb_dat_o = 32'h0;
wb_cyc_o = 1'b0;
wb_stb_o = 1'b0;
wb_sel_o = 4'h0;
wb_we_o = 1'b0;
wb_bte_o = 2'b00;
wb_cti_o = 3'b000;
wb_req_ack_i = 1'b0;
wb_req_dat_i = 32'hx;
wb_resp_ack_i = 1'b0;
wb_resp_dat_i = 32'hx;
wb_target_ack_i = 1'b0;
wb_target_dat_i = 32'hx;
end
end
endmodule // lisnoc_dma
`include "lisnoc_dma_undef.vh"
|
`include "lisnoc_def.vh"
`define FLIT_WIDTH 34
// Type of flit
// The coding is chosen, so that
// type[0] signals that this is the first flit of a packet
// type[1] signals that this is the last flit of a packet
`define FLIT_TYPE_MSB (`FLIT_WIDTH - 1)
`define FLIT_TYPE_WIDTH 2
`define FLIT_TYPE_LSB (`FLIT_TYPE_MSB - `FLIT_TYPE_WIDTH + 1)
// This is the flit content size
`define FLIT_CONTENT_WIDTH 32
`define FLIT_CONTENT_MSB 31
`define FLIT_CONTENT_LSB 0
// The following fields are only valid for header flits
`define FLIT_DEST_WIDTH 5
// destination address field of header flit
`define FLIT_DEST_MSB `FLIT_CONTENT_MSB
`define FLIT_DEST_LSB `FLIT_DEST_MSB - `FLIT_DEST_WIDTH + 1
// packet type field of header flit
`define PACKET_CLASS_MSB (`FLIT_DEST_LSB - 1)
`define PACKET_CLASS_WIDTH 3
`define PACKET_CLASS_LSB (`PACKET_CLASS_MSB - `PACKET_CLASS_WIDTH + 1)
`define PACKET_CLASS_DMA 3'b010
// source address field of header flit
`define SOURCE_MSB 23
`define SOURCE_WIDTH 5
`define SOURCE_LSB 19
// packet id field of header flit
`define PACKET_ID_MSB 18
`define PACKET_ID_WIDTH 4
`define PACKET_ID_LSB 15
`define PACKET_TYPE_MSB 14
`define PACKET_TYPE_WIDTH 2
`define PACKET_TYPE_LSB 13
`define PACKET_TYPE_L2R_REQ 2'b00
`define PACKET_TYPE_R2L_REQ 2'b01
`define PACKET_TYPE_L2R_RESP 2'b10
`define PACKET_TYPE_R2L_RESP 2'b11
`define PACKET_REQ_LAST 12
`define PACKET_RESP_LAST 12
`define SIZE_MSB 31
`define SIZE_WIDTH 32
`define SIZE_LSB 0
`define DMA_REQUEST_WIDTH 103
`define DMA_REQFIELD_LADDR_WIDTH 32
`define DMA_REQFIELD_SIZE_WIDTH 32
`define DMA_REQFIELD_RTILE_WIDTH 5
`define DMA_REQFIELD_RADDR_WIDTH 32
`define DMA_REQFIELD_LADDR_MSB 102
`define DMA_REQFIELD_LADDR_LSB 70
`define DMA_REQFIELD_SIZE_MSB 69
`define DMA_REQFIELD_SIZE_LSB 38
`define DMA_REQFIELD_RTILE_MSB 37
`define DMA_REQFIELD_RTILE_LSB 33
`define DMA_REQFIELD_RADDR_MSB 32
`define DMA_REQFIELD_RADDR_LSB 1
`define DMA_REQFIELD_DIR 0
`define DMA_REQUEST_INVALID 1'b0
`define DMA_REQUEST_VALID 1'b1
`define DMA_REQUEST_L2R 1'b0
`define DMA_REQUEST_R2L 1'b1
`define DMA_REQMASK_WIDTH 5
`define DMA_REQMASK_LADDR 0
`define DMA_REQMASK_SIZE 1
`define DMA_REQMASK_RTILE 2
`define DMA_REQMASK_RADDR 3
`define DMA_REQMASK_DIR 4
`define DMA_RESPFIELD_SIZE_WIDTH 14
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* The module behaving as initiator in DMA transfers.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*
*/
`include "lisnoc_def.vh"
`include "lisnoc_dma_def.vh"
module lisnoc_dma_initiator (/*AUTOARG*/
// Outputs
ctrl_read_pos, ctrl_done_pos, ctrl_done_en, noc_out_flit,
noc_out_valid, noc_in_ready, wb_req_cyc_o, wb_req_stb_o,
wb_req_we_o, wb_req_dat_o, wb_req_adr_o, wb_req_cti_o,
wb_req_bte_o, wb_req_sel_o, wb_resp_cyc_o, wb_resp_stb_o,
wb_resp_we_o, wb_resp_dat_o, wb_resp_adr_o, wb_resp_cti_o,
wb_resp_bte_o, wb_resp_sel_o,
// Inputs
clk, rst, ctrl_read_req, valid, noc_out_ready, noc_in_flit,
noc_in_valid, wb_req_ack_i, wb_req_dat_i, wb_resp_ack_i,
wb_resp_dat_i
);
//parameters
parameter table_entries = 4;
localparam table_entries_ptrwidth = $clog2(table_entries);
parameter tileid = 0;
parameter noc_packet_size = 16;
input clk;
input rst;
// Control read (request) interface
output [table_entries_ptrwidth-1:0] ctrl_read_pos;
input [`DMA_REQUEST_WIDTH-1:0] ctrl_read_req;
output [table_entries_ptrwidth-1:0] ctrl_done_pos;
output ctrl_done_en;
input [table_entries-1:0] valid;
// NOC-Interface
output [`FLIT_WIDTH-1:0] noc_out_flit;
output noc_out_valid;
input noc_out_ready;
input [`FLIT_WIDTH-1:0] noc_in_flit;
input noc_in_valid;
output noc_in_ready;
// Wishbone interface for L2R data fetch
input wb_req_ack_i;
output wb_req_cyc_o, wb_req_stb_o;
output wb_req_we_o;
input [31:0] wb_req_dat_i;
output [31:0] wb_req_dat_o;
output [31:0] wb_req_adr_o;
output [2:0] wb_req_cti_o;
output [1:0] wb_req_bte_o;
output [3:0] wb_req_sel_o;
// Wishbone interface for L2R data fetch
input wb_resp_ack_i;
output wb_resp_cyc_o, wb_resp_stb_o;
output wb_resp_we_o;
input [31:0] wb_resp_dat_i;
output [31:0] wb_resp_dat_o;
output [31:0] wb_resp_adr_o;
output [2:0] wb_resp_cti_o;
output [1:0] wb_resp_bte_o;
output [3:0] wb_resp_sel_o;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] req_data; // From u_wbreq of lisnoc_dma_initiator_wbreq.v
wire req_data_ready; // From u_nocreq of lisnoc_dma_initiator_nocreq.v
wire req_data_valid; // From u_wbreq of lisnoc_dma_initiator_wbreq.v
wire req_is_l2r; // From u_nocreq of lisnoc_dma_initiator_nocreq.v
wire [31:0] req_laddr; // From u_nocreq of lisnoc_dma_initiator_nocreq.v
wire [`DMA_REQFIELD_SIZE_WIDTH-3:0] req_size;// From u_nocreq of lisnoc_dma_initiator_nocreq.v
wire req_start; // From u_nocreq of lisnoc_dma_initiator_nocreq.v
// End of automatics
lisnoc_dma_initiator_wbreq
u_wbreq(/*AUTOINST*/
// Outputs
.wb_req_cyc_o (wb_req_cyc_o),
.wb_req_stb_o (wb_req_stb_o),
.wb_req_we_o (wb_req_we_o),
.wb_req_dat_o (wb_req_dat_o[31:0]),
.wb_req_adr_o (wb_req_adr_o[31:0]),
.wb_req_cti_o (wb_req_cti_o[2:0]),
.wb_req_bte_o (wb_req_bte_o[1:0]),
.wb_req_sel_o (wb_req_sel_o[3:0]),
.req_data_valid (req_data_valid),
.req_data (req_data[31:0]),
// Inputs
.clk (clk),
.rst (rst),
.wb_req_ack_i (wb_req_ack_i),
.wb_req_dat_i (wb_req_dat_i[31:0]),
.req_start (req_start),
.req_is_l2r (req_is_l2r),
.req_size (req_size[`DMA_REQFIELD_SIZE_WIDTH-3:0]),
.req_laddr (req_laddr[31:0]),
.req_data_ready (req_data_ready));
lisnoc_dma_initiator_nocreq
#(.tileid(tileid),.noc_packet_size(noc_packet_size))
u_nocreq(/*AUTOINST*/
// Outputs
.noc_out_flit (noc_out_flit[`FLIT_WIDTH-1:0]),
.noc_out_valid (noc_out_valid),
.ctrl_read_pos (ctrl_read_pos[table_entries_ptrwidth-1:0]),
.req_start (req_start),
.req_laddr (req_laddr[31:0]),
.req_data_ready (req_data_ready),
.req_is_l2r (req_is_l2r),
.req_size (req_size[`DMA_REQFIELD_SIZE_WIDTH-3:0]),
// Inputs
.clk (clk),
.rst (rst),
.noc_out_ready (noc_out_ready),
.ctrl_read_req (ctrl_read_req[`DMA_REQUEST_WIDTH-1:0]),
.valid (valid[table_entries-1:0]),
.ctrl_done_pos (ctrl_done_pos[table_entries_ptrwidth-1:0]),
.ctrl_done_en (ctrl_done_en),
.req_data_valid (req_data_valid),
.req_data (req_data[31:0]));
/* lisnoc_dma_initiator_nocresp AUTO_TEMPLATE(
.wb_\(.*\) (wb_resp_\1[]),
); */
lisnoc_dma_initiator_nocresp
#(.noc_packet_size(noc_packet_size))
u_nocresp(/*AUTOINST*/
// Outputs
.noc_in_ready (noc_in_ready),
.wb_cyc_o (wb_resp_cyc_o), // Templated
.wb_stb_o (wb_resp_stb_o), // Templated
.wb_we_o (wb_resp_we_o), // Templated
.wb_dat_o (wb_resp_dat_o[31:0]), // Templated
.wb_adr_o (wb_resp_adr_o[31:0]), // Templated
.wb_cti_o (wb_resp_cti_o[2:0]), // Templated
.wb_bte_o (wb_resp_bte_o[1:0]), // Templated
.wb_sel_o (wb_resp_sel_o[3:0]), // Templated
.ctrl_done_pos (ctrl_done_pos[table_entries_ptrwidth-1:0]),
.ctrl_done_en (ctrl_done_en),
// Inputs
.clk (clk),
.rst (rst),
.noc_in_flit (noc_in_flit[`FLIT_WIDTH-1:0]),
.noc_in_valid (noc_in_valid),
.wb_ack_i (wb_resp_ack_i), // Templated
.wb_dat_i (wb_resp_dat_i[31:0])); // Templated
endmodule // lisnoc_dma_ctrl_req
`include "lisnoc_undef.vh"
`include "lisnoc_dma_undef.vh"
// Local Variables:
// verilog-library-directories:("." "../" "../infrastructure")
// verilog-auto-inst-param-value: t
// End:
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This modules generates the requests for DMA transfers.
*
* Author(s):
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*
*/
`include "lisnoc_def.vh"
`include "lisnoc_dma_def.vh"
module lisnoc_dma_initiator_nocreq (/*AUTOARG*/
// Outputs
noc_out_flit, noc_out_valid, ctrl_read_pos, req_start, req_laddr,
req_data_ready, req_is_l2r, req_size,
// Inputs
clk, rst, noc_out_ready, ctrl_read_req, valid, ctrl_done_pos,
ctrl_done_en, req_data_valid, req_data
);
parameter table_entries = 4;
localparam table_entries_ptrwidth = $clog2(table_entries);
parameter tileid = 0;
parameter noc_packet_size = 16; // flits per packet
input clk, rst;
// NOC-Interface
output reg [`FLIT_WIDTH-1:0] noc_out_flit;
output reg noc_out_valid;
input noc_out_ready;
// Control read (request) interface
output reg [table_entries_ptrwidth-1:0] ctrl_read_pos;
input [`DMA_REQUEST_WIDTH-1:0] ctrl_read_req;
input [table_entries-1:0] valid;
// Feedback from response path
input [table_entries_ptrwidth-1:0] ctrl_done_pos;
input ctrl_done_en;
// Interface to wishbone request
output reg req_start;
output [31:0] req_laddr;
input req_data_valid;
output reg req_data_ready;
input [31:0] req_data;
output req_is_l2r;
output [`DMA_REQFIELD_SIZE_WIDTH-3:0] req_size;
//
// NOC request
//
localparam NOC_REQ_WIDTH = 4;
localparam NOC_REQ_IDLE = 4'b0000;
localparam NOC_REQ_L2R_GENHDR = 4'b0001;
localparam NOC_REQ_L2R_GENADDR = 4'b0010;
localparam NOC_REQ_L2R_DATA = 4'b0011;
localparam NOC_REQ_L2R_WAITDATA = 4'b0100;
localparam NOC_REQ_R2L_GENHDR = 4'b0101;
localparam NOC_REQ_R2L_GENSIZE = 4'b1000;
localparam NOC_REQ_R2L_GENRADDR = 4'b0110;
localparam NOC_REQ_R2L_GENLADDR = 4'b0111;
// State logic
reg [NOC_REQ_WIDTH-1:0] noc_req_state;
reg [NOC_REQ_WIDTH-1:0] nxt_noc_req_state;
// Counter for payload flits/words in request
reg [`DMA_REQFIELD_SIZE_WIDTH-1:0] noc_req_counter;
reg [`DMA_REQFIELD_SIZE_WIDTH-1:0] nxt_noc_req_counter;
// Current packet payload flit/word counter
reg [4:0] noc_req_packet_count;
reg [4:0] nxt_noc_req_packet_count;
// Current packet total number of flits/words
reg [4:0] noc_req_packet_size;
reg [4:0] nxt_noc_req_packet_size;
/*
* Table entry selection logic
*
* The request table signals all open requests on the 'valid' bit vector.
* The selection logic arbitrates among those entries to determine the
* request to be handled next.
*
* The arbitration is not done for all entries marked as valid but only
* for those, that are additionally not marked in the open_responses
* bit vector.
*
* The selection signals only change after a transfer is started.
*/
// Selects the next entry from the table
reg [table_entries-1:0] select; // current grant of arbiter
wire [table_entries-1:0] nxt_select; // next grant of arbiter
// Store open responses: table entry valid is not sufficient, as
// current requests would be selected
reg [table_entries-1:0] open_responses;
reg [table_entries-1:0] nxt_open_responses;
wire [table_entries-1:0] requests;
assign requests = valid & ~open_responses & {table_entries{(noc_req_state == NOC_REQ_IDLE)}};
/* lisnoc_arb_rr AUTO_TEMPLATE(
.nxt_gnt (nxt_select),
.gnt (select),
.req (requests),
); */
// Round robin (rr) arbiter
lisnoc_arb_rr
#(.N(table_entries))
u_select(/*AUTOINST*/
// Outputs
.nxt_gnt (nxt_select), // Templated
// Inputs
.req (requests), // Templated
.gnt (select)); // Templated
// register next select to select
always @(posedge clk) begin
if (rst) begin
select <= 0;
end else begin
select <= nxt_select;
end
end
// Convert (one hot) select bit vector to binary
always @(*) begin : readpos_onehottobinary
integer d;
ctrl_read_pos = 0;
for (d=0;d<table_entries;d=d+1)
if (select[d])
ctrl_read_pos = ctrl_read_pos | d;
end
/*
*
* Request generation
*
*/
wire nxt_req_start;
// This is a pulse that signals the start of a request to the wishbone and noc
// part of the request generation.
assign nxt_req_start = // start when any is valid and not already in progress
(|(valid & ~open_responses) &
// and we are not currently generating a request (pulse)
(noc_req_state == NOC_REQ_IDLE));
// Convenience wires
wire [`DMA_REQFIELD_RTILE_WIDTH-1:0] req_rtile;
wire [31:0] req_raddr;
assign req_is_l2r = (ctrl_read_req[`DMA_REQFIELD_DIR] == `DMA_REQUEST_L2R);
assign req_laddr = ctrl_read_req[`DMA_REQFIELD_LADDR_MSB:`DMA_REQFIELD_LADDR_LSB];
assign req_size = ctrl_read_req[`DMA_REQFIELD_SIZE_MSB:`DMA_REQFIELD_SIZE_LSB];
assign req_rtile = ctrl_read_req[`DMA_REQFIELD_RTILE_MSB:`DMA_REQFIELD_RTILE_LSB];
assign req_raddr = ctrl_read_req[`DMA_REQFIELD_RADDR_MSB:`DMA_REQFIELD_RADDR_LSB];
//
// NoC side request generation
//
// next state logic, counters, control signals
always @(*) begin
// Default is not generating flits
noc_out_valid = 1'b0;
noc_out_flit = 34'h0;
// Only pop when successfull transfer
req_data_ready = 1'b0;
// Counters stay old value
nxt_noc_req_counter = noc_req_counter;
nxt_noc_req_packet_count = noc_req_packet_count;
nxt_noc_req_packet_size = noc_req_packet_size;
// Open response only changes when request generated
nxt_open_responses = open_responses;
case(noc_req_state)
NOC_REQ_IDLE: begin
// Idle'ing
if (req_start)
// A valid request exists, that is not open
if (req_is_l2r)
// L2R
nxt_noc_req_state = NOC_REQ_L2R_GENHDR;
else
// R2L
nxt_noc_req_state = NOC_REQ_R2L_GENHDR;
else
// wait for request
nxt_noc_req_state = NOC_REQ_IDLE;
// Reset counter
nxt_noc_req_counter = 0;
end
NOC_REQ_L2R_GENHDR: begin
noc_out_valid = 1'b1;
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_HEADER;
noc_out_flit[`FLIT_DEST_MSB:`FLIT_DEST_LSB] = req_rtile;
noc_out_flit[`PACKET_CLASS_MSB:`PACKET_CLASS_LSB] = `PACKET_CLASS_DMA;
noc_out_flit[`PACKET_ID_MSB:`PACKET_ID_LSB] = ctrl_read_pos;
noc_out_flit[`SOURCE_MSB:`SOURCE_LSB] = tileid;
noc_out_flit[`PACKET_TYPE_MSB:`PACKET_TYPE_LSB] = `PACKET_TYPE_L2R_REQ;
if ((noc_req_counter + (noc_packet_size-2)) < req_size) begin
// This is not the last packet in the request (noc_packet_size-2)
noc_out_flit[`SIZE_MSB:`SIZE_LSB] = noc_packet_size-2;
noc_out_flit[`PACKET_REQ_LAST] = 1'b0;
nxt_noc_req_packet_size = noc_packet_size-2;
// count is the current transfer number
nxt_noc_req_packet_count = 5'd1;
end else begin
// This is the last packet in the request
noc_out_flit[`SIZE_MSB:`SIZE_LSB] = req_size - noc_req_counter;
noc_out_flit[`PACKET_REQ_LAST] = 1'b1;
nxt_noc_req_packet_size = req_size - noc_req_counter;
// count is the current transfer number
nxt_noc_req_packet_count = 5'd1;
end // else: !if((noc_req_counter + (noc_packet_size-2)) < req_size)
// change to next state if successful
if (noc_out_ready)
nxt_noc_req_state = NOC_REQ_L2R_GENADDR;
else
nxt_noc_req_state = NOC_REQ_L2R_GENHDR;
end // case: NOC_REQ_GENHDR
NOC_REQ_L2R_GENADDR: begin
noc_out_valid = 1'b1;
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_PAYLOAD;
noc_out_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB] = req_raddr + (noc_req_counter << 2);
if (noc_out_ready) begin
nxt_noc_req_state = NOC_REQ_L2R_DATA;
end else begin
nxt_noc_req_state = NOC_REQ_L2R_GENADDR;
end
end
NOC_REQ_L2R_DATA: begin
// transfer data to noc if available
noc_out_valid = req_data_valid;
// Signal last flit for this transfer
if (noc_req_packet_count==noc_req_packet_size) begin
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_LAST;
end else begin
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_PAYLOAD;
end
noc_out_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB] = req_data;
if (noc_out_ready & noc_out_valid) begin
// transfer was successful
// signal to data fifo
req_data_ready = 1'b1;
// increment the counter for this packet
nxt_noc_req_packet_count = noc_req_packet_count + 1;
if (noc_req_packet_count == noc_req_packet_size) begin
// This was the last flit in this packet
if (noc_req_packet_count+noc_req_counter == req_size) begin
// .. and the last flit for the request
// keep open_responses and "add" currently selected request to it
nxt_open_responses = open_responses | select;
// back to IDLE
nxt_noc_req_state = NOC_REQ_IDLE;
end else begin
// .. and other packets to transfer
// Start with next header
nxt_noc_req_state = NOC_REQ_L2R_GENHDR;
// add the current counter to overall counter
nxt_noc_req_counter = noc_req_counter + noc_req_packet_count;
end
end else begin // if (noc_req_packet_count == noc_req_packet_size)
// we transfered a flit inside the packet
nxt_noc_req_state = NOC_REQ_L2R_DATA;
end
end else begin // if (noc_out_ready & noc_out_valid)
// no success
nxt_noc_req_state = NOC_REQ_L2R_DATA;
end
end // case: NOC_REQ_L2R_DATA
NOC_REQ_R2L_GENHDR: begin
noc_out_valid = 1'b1;
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_HEADER;
noc_out_flit[`FLIT_DEST_MSB:`FLIT_DEST_LSB] = req_rtile;
noc_out_flit[`PACKET_CLASS_MSB:`PACKET_CLASS_LSB] = `PACKET_CLASS_DMA;
noc_out_flit[`PACKET_ID_MSB:`PACKET_ID_LSB] = ctrl_read_pos;
noc_out_flit[`SOURCE_MSB:`SOURCE_LSB] = tileid;
noc_out_flit[`PACKET_TYPE_MSB:`PACKET_TYPE_LSB] = `PACKET_TYPE_R2L_REQ;
noc_out_flit[11:0] = 0;
// There's only one packet needed for the request
noc_out_flit[`PACKET_REQ_LAST] = 1'b1;
// change to next state if successful
if (noc_out_ready)
nxt_noc_req_state = NOC_REQ_R2L_GENSIZE;
else
nxt_noc_req_state = NOC_REQ_R2L_GENHDR;
end // case: NOC_REQ_GENHDR
NOC_REQ_R2L_GENSIZE: begin
noc_out_valid = 1'b1;
noc_out_flit[`SIZE_MSB:`SIZE_LSB] = req_size;
// change to next state if successful
if (noc_out_ready)
nxt_noc_req_state = NOC_REQ_R2L_GENRADDR;
else
nxt_noc_req_state = NOC_REQ_R2L_GENSIZE;
end // case: NOC_REQ_R2L_GENSIZE
NOC_REQ_R2L_GENRADDR: begin
noc_out_valid = 1'b1;
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_PAYLOAD;
noc_out_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB] = ctrl_read_req[`DMA_REQFIELD_RADDR_MSB:`DMA_REQFIELD_RADDR_LSB];
if (noc_out_ready) begin
// keep open_responses and "add" currently selected request to it
nxt_noc_req_state = NOC_REQ_R2L_GENLADDR;
end else begin
nxt_noc_req_state = NOC_REQ_R2L_GENRADDR;
end
end // case: NOC_REQ_R2L_GENRADDR
NOC_REQ_R2L_GENLADDR: begin
noc_out_valid = 1'b1;
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_LAST;
noc_out_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB] = ctrl_read_req[`DMA_REQFIELD_LADDR_MSB:`DMA_REQFIELD_LADDR_LSB];
if (noc_out_ready) begin
// keep open_responses and "add" currently selected request to it
nxt_open_responses = open_responses | select;
nxt_noc_req_state = NOC_REQ_IDLE;
end else begin
nxt_noc_req_state = NOC_REQ_R2L_GENLADDR;
end
end // case: NOC_REQ_R2L_GENLADDR
default: begin
nxt_noc_req_state = NOC_REQ_IDLE;
end
endcase // case (noc_req_state)
// Process done information from response
if (ctrl_done_en) begin
nxt_open_responses[ctrl_done_pos] = 1'b0;
end
end
// sequential part of NoC interface
always @(posedge clk) begin
if (rst) begin
noc_req_state <= NOC_REQ_IDLE;
noc_req_counter <= 0;
noc_req_packet_size <= 5'h0;
noc_req_packet_count <= 5'h0;
open_responses <= 0;
req_start <= 1'b0;
end else begin
noc_req_counter <= nxt_noc_req_counter;
noc_req_packet_size <= nxt_noc_req_packet_size;
noc_req_packet_count <= nxt_noc_req_packet_count;
noc_req_state <= nxt_noc_req_state;
open_responses <= nxt_open_responses;
req_start <= nxt_req_start;
end
end
endmodule // lisnoc_dma_initiator_noc_req
`include "lisnoc_undef.vh"
`include "lisnoc_dma_undef.vh"
// Local Variables:
// verilog-library-directories:("." "../" "../infrastructure")
// verilog-auto-inst-param-value: t
// End:
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This module processes the responses of DMA requests.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*
*/
`include "lisnoc_def.vh"
`include "lisnoc_dma_def.vh"
module lisnoc_dma_initiator_nocresp(/*AUTOARG*/
// Outputs
noc_in_ready, wb_cyc_o, wb_stb_o, wb_we_o, wb_dat_o, wb_adr_o,
wb_cti_o, wb_bte_o, wb_sel_o, ctrl_done_pos, ctrl_done_en,
// Inputs
clk, rst, noc_in_flit, noc_in_valid, wb_ack_i, wb_dat_i
);
//parameters
parameter flit_width = `FLIT_WIDTH;
parameter table_entries = 4;
localparam table_entries_ptrwidth = $clog2(table_entries);
parameter noc_packet_size = 16;
localparam STATE_WIDTH = 2;
localparam STATE_IDLE = 2'b00;
localparam STATE_GET_ADDR = 2'b01;
localparam STATE_DATA = 2'b10;
localparam STATE_GET_SIZE = 2'b11;
input clk, rst;
input [`FLIT_WIDTH-1:0] noc_in_flit;
input noc_in_valid;
output noc_in_ready;
// Wishbone interface for L2R data fetch
input wb_ack_i;
output reg wb_cyc_o, wb_stb_o;
output reg wb_we_o;
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
output [31:0] wb_adr_o;
output reg [2:0] wb_cti_o;
output reg [1:0] wb_bte_o;
output [3:0] wb_sel_o;
output reg [table_entries_ptrwidth-1:0] ctrl_done_pos;
output reg ctrl_done_en;
// State registers and next state logic
reg [STATE_WIDTH-1:0] state;
reg [STATE_WIDTH-1:0] nxt_state;
reg [31:0] resp_address;
reg [31:0] nxt_resp_address;
reg last_packet_of_response;
reg nxt_last_packet_of_response;
reg [table_entries_ptrwidth-1:0] resp_id;
reg [table_entries_ptrwidth-1:0] nxt_resp_id;
// There is a buffer between the NoC input and the wishbone
// handling by the state machine. Those are the connection signals
// from buffer to wishbone
wire [`FLIT_WIDTH-1:0] buf_flit;
wire buf_valid;
reg buf_ready;
/* lisnoc_packet_buffer AUTO_TEMPLATE(
.in_\(.*\) (noc_in_\1[]),
.out_size (),
.out_\(.*\) (buf_\1[]),
); */
lisnoc_packet_buffer
#(.fifo_depth(noc_packet_size))
u_buf(/*AUTOINST*/
// Outputs
.in_ready (noc_in_ready), // Templated
.out_flit (buf_flit[flit_width-1:0]), // Templated
.out_valid (buf_valid), // Templated
.out_size (), // Templated
// Inputs
.clk (clk),
.rst (rst),
.in_flit (noc_in_flit[flit_width-1:0]), // Templated
.in_valid (noc_in_valid), // Templated
.out_ready (buf_ready)); // Templated
// Is this the last flit of a packet?
wire buf_last_flit;
assign buf_last_flit = (buf_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB]==`FLIT_TYPE_LAST) |
(buf_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB]==`FLIT_TYPE_SINGLE);
assign wb_adr_o = resp_address; //alias
assign wb_dat_o = buf_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB];
// We only do word transfers
assign wb_sel_o = 4'hf;
// Next state, wishbone combinatorial signals and counting
always @(*) begin
// Signal defaults
wb_stb_o = 1'b0;
wb_cyc_o = 1'b0;
wb_we_o = 1'b0;
wb_bte_o = 2'b00;
wb_cti_o = 3'b000;
ctrl_done_en = 1'b0;
ctrl_done_pos = 0;
// Default values are old values
nxt_resp_id = resp_id;
nxt_resp_address = resp_address;
nxt_last_packet_of_response = last_packet_of_response;
buf_ready = 1'b0;
case (state)
STATE_IDLE: begin
buf_ready = 1'b1;
if (buf_valid) begin
nxt_resp_id = buf_flit[`PACKET_ID_MSB:`PACKET_ID_LSB];
nxt_last_packet_of_response = buf_flit[`PACKET_RESP_LAST];
if (buf_flit[`PACKET_TYPE_MSB:`PACKET_TYPE_LSB] == `PACKET_TYPE_L2R_RESP) begin
nxt_state = STATE_IDLE;
ctrl_done_en = 1'b1;
ctrl_done_pos = nxt_resp_id;
end else if(buf_flit[`PACKET_TYPE_MSB:`PACKET_TYPE_LSB] == `PACKET_TYPE_R2L_RESP) begin
nxt_state = STATE_GET_SIZE;
end else begin
// now we have a problem...
// must not happen
nxt_state = STATE_IDLE;
end
end else begin // if (buf_valid)
nxt_state = STATE_IDLE;
end
end
STATE_GET_SIZE: begin
buf_ready = 1'b1;
nxt_state = STATE_GET_ADDR;
end
STATE_GET_ADDR: begin
buf_ready = 1'b1;
nxt_resp_address = buf_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB];
nxt_state = STATE_DATA;
end
STATE_DATA: begin
if (buf_last_flit) begin
wb_cti_o = 3'b111;
end else begin
wb_cti_o = 3'b010;
end
wb_bte_o = 2'b00;
wb_cyc_o = 1'b1;
wb_stb_o = 1'b1;
wb_we_o = 1'b1;
if (wb_ack_i) begin
nxt_resp_address = resp_address + 4;
buf_ready = 1'b1;
if (buf_last_flit) begin
nxt_state = STATE_IDLE;
if (last_packet_of_response) begin
ctrl_done_en = 1'b1;
ctrl_done_pos = resp_id;
end
end else begin
nxt_state = STATE_DATA;
end
end else begin
buf_ready = 1'b0;
nxt_state = STATE_DATA;
end
end
default: begin
nxt_state = STATE_IDLE;
end
endcase // case (state)
end // always @ (*)
always @(posedge clk) begin
if (rst) begin
state <= STATE_IDLE;
resp_address <= 0;
last_packet_of_response <= 0;
resp_id <= 0;
end else begin
state <= nxt_state;
resp_address <= nxt_resp_address;
last_packet_of_response <= nxt_last_packet_of_response;
resp_id <= nxt_resp_id;
end
end
endmodule // lisnoc_dma_initiator_nocresp
`include "lisnoc_undef.vh"
`include "lisnoc_dma_undef.vh"
// Local Variables:
// verilog-library-directories:("." "../" "../infrastructure")
// verilog-auto-inst-param-value: t
// End:
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* The wishbone master of the initiator.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*
*/
`include "lisnoc_def.vh"
`include "lisnoc_dma_def.vh"
module lisnoc_dma_initiator_wbreq(/*AUTOARG*/
// Outputs
wb_req_cyc_o, wb_req_stb_o, wb_req_we_o, wb_req_dat_o,
wb_req_adr_o, wb_req_cti_o, wb_req_bte_o, wb_req_sel_o,
req_data_valid, req_data,
// Inputs
clk, rst, wb_req_ack_i, wb_req_dat_i, req_start, req_is_l2r,
req_size, req_laddr, req_data_ready
);
input clk, rst;
input wb_req_ack_i;
output reg wb_req_cyc_o, wb_req_stb_o;
output wb_req_we_o;
input [31:0] wb_req_dat_i;
output [31:0] wb_req_dat_o;
output reg [31:0] wb_req_adr_o;
output reg [2:0] wb_req_cti_o;
output [1:0] wb_req_bte_o;
output [3:0] wb_req_sel_o;
input req_start;
input req_is_l2r;
input [`DMA_REQFIELD_SIZE_WIDTH-3:0] req_size;
input [31:0] req_laddr;
output req_data_valid;
output [31:0] req_data;
input req_data_ready;
//
// Wishbone state machine
//
`define WB_REQ_WIDTH 2
`define WB_REQ_IDLE 2'b00
`define WB_REQ_DATA 2'b01
`define WB_REQ_WAIT 2'b10
// State logic
reg [`WB_REQ_WIDTH-1:0] wb_req_state;
reg [`WB_REQ_WIDTH-1:0] nxt_wb_req_state;
// Counter for the state machine for loaded words
reg [`DMA_REQFIELD_SIZE_WIDTH-3:0] wb_req_count;
reg [`DMA_REQFIELD_SIZE_WIDTH-3:0] nxt_wb_req_count;
/*
* The wishbone data fetch and the NoC interface are seperated by a FIFO.
* This FIFO relaxes problems with bursts and their termination and decouples
* the timing of the NoC side and the wishbone side (in terms of termination).
*/
// The intermediate store a FIFO of three elements
//
// There should be no combinatorial path from input to output, so
// that it takes one cycle before the wishbone interface knows
// about back pressure from the NoC. Additionally, the wishbone
// interface needs one extra cycle for burst termination. The data
// should be stored and not discarded. Finally, there is one
// element in the FIFO that is the normal timing decoupling.
reg [31:0] data_fifo [0:2]; // data storage
wire data_fifo_pop; // NoC pops
reg data_fifo_push; // WB pushes
wire [31:0] data_fifo_out; // Current first element
wire [31:0] data_fifo_in; // Push element
// Shift register for current position (4th bit is full mark)
reg [3:0] data_fifo_pos;
wire data_fifo_empty; // FIFO empty
wire data_fifo_ready; // FIFO accepts new elements
// Connect the fifo signals to the ports
assign data_fifo_pop = req_data_ready;
assign req_data_valid = ~data_fifo_empty;
assign req_data = data_fifo_out;
assign data_fifo_empty = data_fifo_pos[0]; // Empty when pushing to first one
assign data_fifo_out = data_fifo[0]; // First element is out
// FIFO is not ready when back-pressure would result in discarded data,
// that is, we need one store element (high-water).
assign data_fifo_ready = ~|data_fifo_pos[3:2];
// FIFO position pointer logic
always @(posedge clk) begin
if (rst) begin
data_fifo_pos <= 4'b001;
end else begin
if (data_fifo_push & ~data_fifo_pop) begin
// push and no pop
data_fifo_pos <= data_fifo_pos << 1;
end else if (~data_fifo_push & data_fifo_pop) begin
// pop and no push
data_fifo_pos <= data_fifo_pos >> 1;
end else begin
// * no push or pop or
// * both push and pop
data_fifo_pos <= data_fifo_pos;
end
end
end
// FIFO data shifting logic
always @(posedge clk) begin : data_fifo_shift
integer i;
// Iterate all fifo elements, starting from lowest
for (i=0;i<3;i=i+1) begin
if (data_fifo_pop) begin
// when popping data..
if (data_fifo_push & data_fifo_pos[i+1])
// .. and we also push this cycle, we need to check
// whether the pointer was on the next one
data_fifo[i] <= data_fifo_in;
else if (i<2)
// .. otherwise shift if not last
data_fifo[i] <= data_fifo[i+1];
else
// the last stays static
data_fifo[i] <= data_fifo[i];
end else if (data_fifo_push & data_fifo_pos[i]) begin
// when pushing only and this is the current write
// position
data_fifo[i] <= data_fifo_in;
end else begin
// else just keep
data_fifo[i] <= data_fifo[i];
end
end
end
//
// Wishbone interface logic
//
// Statically zero (this interface reads)
assign wb_req_dat_o = 32'h0000_0000;
assign wb_req_we_o = 1'b0;
// We only support full (aligned) word transfers
assign wb_req_sel_o = 4'b1111;
// We only need linear bursts
assign wb_req_bte_o = 2'b00;
// The input to the fifo is the data from the bus
assign data_fifo_in = wb_req_dat_i;
// Next state, wishbone combinatorial signals and counting
always @(*) begin
// Signal defaults
nxt_wb_req_count = wb_req_count;
wb_req_stb_o = 1'b0;
wb_req_cyc_o = 1'b0;
data_fifo_push = 1'b0;
wb_req_adr_o = 32'hx;
wb_req_cti_o = 3'b000;
case (wb_req_state)
`WB_REQ_IDLE: begin
// We are idle'ing
// Always reset counter
nxt_wb_req_count = 0;
if (req_start & req_is_l2r)
// start when new request is handled and it is a L2R
// request. Direct transition to data fetching from bus,
// as the FIFO is always empty at this point.
nxt_wb_req_state = `WB_REQ_DATA;
else
// otherwise keep idle'ing
nxt_wb_req_state = `WB_REQ_IDLE;
end
`WB_REQ_DATA: begin
// We get data from the bus
// Signal cycle and strobe. We do bursts, but don't insert
// wait states, so both of them are always equal.
wb_req_stb_o = 1'b1;
wb_req_cyc_o = 1'b1;
// The address is the base address plus the counter
// Counter counts words, not bytes
wb_req_adr_o = req_laddr + (wb_req_count << 2);
if (~data_fifo_ready | (wb_req_count==req_size-1)) begin
// If fifo gets full next cycle, do cycle termination
wb_req_cti_o = 3'b111;
end else begin
// As long as we can also store the _next_ element in
// the fifo, signal we are in an incrementing burst
wb_req_cti_o = 3'b010;
end
if (wb_req_ack_i) begin
// When this request was successfull..
// increment word counter
nxt_wb_req_count = wb_req_count + 1;
// signal push to data fifo
data_fifo_push = 1'b1;
if (wb_req_count==req_size-1)
// This was the last word
nxt_wb_req_state = `WB_REQ_IDLE;
else if (data_fifo_ready)
// when FIFO can still get data, we stay here
nxt_wb_req_state = `WB_REQ_DATA;
else
// .. otherwise we wait for FIFO to become ready
nxt_wb_req_state = `WB_REQ_WAIT;
end else begin // if (wb_req_ack_i)
// ..otherwise we still wait for the acknowledgement
nxt_wb_req_state = `WB_REQ_DATA;
end
end
`WB_REQ_WAIT: begin
// Waiting for FIFO to accept new data
if (data_fifo_ready)
// FIFO ready, restart burst
nxt_wb_req_state = `WB_REQ_DATA;
else
// wait
nxt_wb_req_state = `WB_REQ_WAIT;
end
default: begin
nxt_wb_req_state = `WB_REQ_IDLE;
end
endcase
end
// Sequential part of the state machine
always @(posedge clk) begin
if (rst) begin
wb_req_state <= `WB_REQ_IDLE;
wb_req_count <= 0;
end else begin
wb_req_state <= nxt_wb_req_state;
wb_req_count <= nxt_wb_req_count;
end
end
endmodule // lisnoc_dma_initiator_wbreq
`include "lisnoc_dma_undef.vh"
// Local Variables:
// verilog-library-directories:("../" "../infrastructure")
// verilog-auto-inst-param-value: t
// End:
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* DMA transfer table
* The DMA transfer table holds all requests and their corresponding
* life-cycle between the interface and the control handler. To save
* ports on the memory, each the request and status are dual ported,
* so that the interface can't read back the values. The only
* exception is the valid signal, that is a dedicated register for
* each request. All request valid signals are also provided in an
* output.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*
*/
`include "lisnoc_dma_def.vh"
module lisnoc_dma_request_table(/*AUTOARG*/
// Outputs
ctrl_read_req, valid, done, irq,
// Inputs
clk, rst, if_write_req, if_write_pos, if_write_select, if_write_en,
if_valid_pos, if_valid_set, if_valid_en, if_validrd_en,
ctrl_read_pos, ctrl_done_pos, ctrl_done_en
);
parameter table_entries = 4;
localparam table_entries_ptrwidth = $clog2(table_entries);
parameter generate_interrupt = 1;
input clk, rst;
// Interface write (request) interface
input [`DMA_REQUEST_WIDTH-1:0] if_write_req;
input [table_entries_ptrwidth-1:0] if_write_pos;
input [`DMA_REQMASK_WIDTH-1:0] if_write_select;
input if_write_en;
input [table_entries_ptrwidth-1:0] if_valid_pos;
input if_valid_set;
input if_valid_en;
input if_validrd_en;
// Control read (request) interface
output [`DMA_REQUEST_WIDTH-1:0] ctrl_read_req;
input [table_entries_ptrwidth-1:0] ctrl_read_pos;
// Control write (status) interface
input [table_entries_ptrwidth-1:0] ctrl_done_pos;
input ctrl_done_en;
// All valid bits of the entries
output [table_entries-1:0] valid;
output [table_entries-1:0] done;
output [table_entries-1:0] irq;
// The storage of the requests ..
reg [`DMA_REQUEST_WIDTH-1:0] transfer_request_table[0:table_entries-1];
reg [table_entries-1:0] transfer_valid;
reg [table_entries-1:0] transfer_done;
wire [`DMA_REQUEST_WIDTH-1:0] if_write_mask;
assign if_write_mask[`DMA_REQFIELD_LADDR_MSB:`DMA_REQFIELD_LADDR_LSB] = {`DMA_REQFIELD_LADDR_WIDTH{if_write_select[`DMA_REQMASK_LADDR]}};
assign if_write_mask[`DMA_REQFIELD_SIZE_MSB:`DMA_REQFIELD_SIZE_LSB] = {`DMA_REQFIELD_SIZE_WIDTH{if_write_select[`DMA_REQMASK_SIZE]}};
assign if_write_mask[`DMA_REQFIELD_RTILE_MSB:`DMA_REQFIELD_RTILE_LSB] = {`DMA_REQFIELD_RTILE_WIDTH{if_write_select[`DMA_REQMASK_RTILE]}};
assign if_write_mask[`DMA_REQFIELD_RADDR_MSB:`DMA_REQFIELD_RADDR_LSB] = {`DMA_REQFIELD_RADDR_WIDTH{if_write_select[`DMA_REQMASK_RADDR]}};
assign if_write_mask[`DMA_REQFIELD_DIR] = if_write_select[`DMA_REQMASK_DIR];
// Write to the request table
always @(posedge clk) begin : proc_request_table
integer i;
if (rst) begin : reset
//reset
for (i = 0; i < table_entries; i = i+1) begin
{ transfer_valid[i], transfer_done[i] } <= 2'b00;
end //for
end else begin
if (if_write_en) begin
transfer_request_table[if_write_pos] <= (~if_write_mask & transfer_request_table[if_write_pos]) | (if_write_mask & if_write_req);
end
for (i = 0; i<table_entries; i=i+1 ) begin
if (if_valid_en && (if_valid_pos == i)) begin
// Start transfer
transfer_valid[i] <= if_valid_set;
transfer_done[i] <= 1'b0;
end else if (if_validrd_en && (if_valid_pos==i) && (transfer_done[i])) begin
// Check transfer and was done
transfer_done[i] <= 1'b0;
transfer_valid[i] <= 1'b0;
end else if (ctrl_done_en && (ctrl_done_pos==i)) begin
// Transfer is finished
transfer_done[i] <= 1'b1;
end
end
end
end
// Read interface to the request table
assign ctrl_read_req = transfer_request_table[ctrl_read_pos];
// Combine the valid and done bits to one signal
genvar i;
generate
for (i=0;i<table_entries;i=i+1) begin
assign valid[i] = transfer_valid[i] & ~transfer_done[i];
assign done[i] = transfer_done[i];
end
endgenerate
// The interrupt is set when any request is valid and done
assign irq = (transfer_valid & transfer_done) & {(table_entries){1'b1}};
endmodule // dma_transfer_table
// Local Variables:
// verilog-typedef-regexp:"_t$"
// End:
|
/* Copyright (c) 2015 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* The module behaving as target in DMA transfers.
*
* (c) 2011-2013 by the author(s)
*
* Author(s):
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*
*/
`include "lisnoc_def.vh"
`include "lisnoc_dma_def.vh"
module lisnoc_dma_target (/*AUTOARG*/
// Outputs
noc_out_flit, noc_out_valid, noc_in_ready, wb_cyc_o, wb_stb_o,
wb_we_o, wb_dat_o, wb_adr_o, wb_sel_o, wb_cti_o, wb_bte_o,
// Inputs
clk, rst, noc_out_ready, noc_in_flit, noc_in_valid, wb_ack_i,
wb_dat_i
);
parameter flit_width = `FLIT_WIDTH;
localparam STATE_WIDTH = 4;
localparam STATE_IDLE = 4'b0000;
localparam STATE_L2R_GETADDR = 4'b0001;
localparam STATE_L2R_DATA = 4'b0010;
localparam STATE_L2R_SENDRESP = 4'b0011;
localparam STATE_R2L_GETLADDR = 4'b0100;
localparam STATE_R2L_GETRADDR = 4'b0101;
localparam STATE_R2L_GENHDR = 4'b0110;
localparam STATE_R2L_GENADDR = 4'b0111;
localparam STATE_R2L_DATA = 4'b1000;
//TODO: set nxt_wb_waiting = 1'b0 in certain states like idle, or genheader.
// Not important since we just loose one cycle in the worst case
parameter table_entries = 4;
localparam table_entries_ptrwidth = $clog2(table_entries);
parameter tileid = 0;
parameter noc_packet_size = 16;
input clk;
input rst;
// NOC-Interface
output reg [`FLIT_WIDTH-1:0] noc_out_flit;
output reg noc_out_valid;
input noc_out_ready;
input [`FLIT_WIDTH-1:0] noc_in_flit;
input noc_in_valid;
output noc_in_ready;
// Wishbone interface for L2R data store
input wb_ack_i;
output reg wb_cyc_o, wb_stb_o, wb_we_o;
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
output [31:0] wb_adr_o;
output [3:0] wb_sel_o;
output reg [2:0] wb_cti_o;
output reg [1:0] wb_bte_o;
// There is a buffer between the NoC input and the wishbone
// handling by the state machine. Those are the connection signals
// from buffer to wishbone
wire [`FLIT_WIDTH-1:0] buf_flit;
wire buf_valid;
reg buf_ready;
/*
* One FSM that handles the flow from the input
* buffer to the wishbone interface
*/
// FSM state
reg [STATE_WIDTH-1:0] state;
reg [STATE_WIDTH-1:0] nxt_state;
//FSM hidden state
reg wb_waiting;
reg nxt_wb_waiting;
// Store request parameters: address, last packet and source
reg [31:0] src_address;
reg [31:0] nxt_src_address;
reg [31:0] address;
reg [31:0] nxt_address;
reg end_of_request;
reg nxt_end_of_request;
reg [`SOURCE_WIDTH-1:0] src_tile;
reg [`SOURCE_WIDTH-1:0] nxt_src_tile;
reg [`PACKET_ID_WIDTH-1:0] packet_id;
reg [`PACKET_ID_WIDTH-1:0] nxt_packet_id;
// Counter for flits/words in request
reg [`SIZE_WIDTH-1:0] noc_resp_wcounter;
reg [`SIZE_WIDTH-1:0] nxt_noc_resp_wcounter;
// Current packet flit/word counter
reg [4:0] noc_resp_packet_wcount;
reg [4:0] nxt_noc_resp_packet_wcount;
// Current packet total number of flits/words
reg [4:0] noc_resp_packet_wsize;
reg [4:0] nxt_noc_resp_packet_wsize;
// TODO: correct define!
reg [`DMA_REQFIELD_SIZE_WIDTH-3:0] resp_wsize;
reg [`DMA_REQFIELD_SIZE_WIDTH-3:0] nxt_resp_wsize;
reg [`DMA_RESPFIELD_SIZE_WIDTH-3:0] wb_resp_count;
reg [`DMA_RESPFIELD_SIZE_WIDTH-3:0] nxt_wb_resp_count;
//FIFO-Stuff
wire data_fifo_valid;
reg [31:0] data_fifo [0:2]; // data storage
reg data_fifo_pop; // NOC pushes
reg data_fifo_push; // WB pops
wire [31:0] data_fifo_out; // Current first element
wire [31:0] data_fifo_in; // Push element
// Shift register for current position (4th bit is full mark)
reg [3:0] data_fifo_pos;
wire data_fifo_empty; // FIFO empty
wire data_fifo_ready; // FIFO accepts new elements
//
// Input buffer that stores flits until we have one complete packet
//
/* lisnoc_packet_buffer AUTO_TEMPLATE(
.in_\(.*\) (noc_in_\1[]),
.out_size (),
.out_\(.*\) (buf_\1[]),
); */
lisnoc_packet_buffer
#(.fifo_depth(noc_packet_size))
u_buf(/*AUTOINST*/
// Outputs
.in_ready (noc_in_ready), // Templated
.out_flit (buf_flit[flit_width-1:0]), // Templated
.out_valid (buf_valid), // Templated
.out_size (), // Templated
// Inputs
.clk (clk),
.rst (rst),
.in_flit (noc_in_flit[flit_width-1:0]), // Templated
.in_valid (noc_in_valid), // Templated
.out_ready (buf_ready)); // Templated
// Is this the last flit of a packet?
wire buf_last_flit;
assign buf_last_flit = (buf_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB]==`FLIT_TYPE_LAST) |
(buf_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB]==`FLIT_TYPE_SINGLE);
// The intermediate store a FIFO of three elements
//
// There should be no combinatorial path from input to output, so
// that it takes one cycle before the wishbone interface knows
// about back pressure from the NoC. Additionally, the wishbone
// interface needs one extra cycle for burst termination. The data
// should be stored and not discarded. Finally, there is one
// element in the FIFO that is the normal timing decoupling.
// Connect the fifo signals to the ports
// assign data_fifo_pop = resp_data_ready;
assign data_fifo_valid = ~data_fifo_empty;
assign data_fifo_empty = data_fifo_pos[0]; // Empty when pushing to first one
assign data_fifo_ready = ~|data_fifo_pos[3:2]; //equal to not full
assign data_fifo_in = wb_dat_i;
assign data_fifo_out = data_fifo[0]; // First element is out
// FIFO position pointer logic
always @(posedge clk) begin
if (rst) begin
data_fifo_pos <= 4'b001;
end else begin
if (data_fifo_push & ~data_fifo_pop) begin
// push and no pop
data_fifo_pos <= data_fifo_pos << 1;
end else if (~data_fifo_push & data_fifo_pop) begin
// pop and no push
data_fifo_pos <= data_fifo_pos >> 1;
end else begin
// * no push or pop or
// * both push and pop
data_fifo_pos <= data_fifo_pos;
end
end
end
// FIFO data shifting logic
always @(posedge clk) begin : data_fifo_shift
integer i;
// Iterate all fifo elements, starting from lowest
for (i=0;i<3;i=i+1) begin
if (data_fifo_pop) begin
// when popping data..
if (data_fifo_push & data_fifo_pos[i+1])
// .. and we also push this cycle, we need to check
// whether the pointer was on the next one
data_fifo[i] <= data_fifo_in;
else if (i<2)
// .. otherwise shift if not last
data_fifo[i] <= data_fifo[i+1];
else
// the last stays static
data_fifo[i] <= data_fifo[i];
end else if (data_fifo_push & data_fifo_pos[i]) begin
// when pushing only and this is the current write
// position
data_fifo[i] <= data_fifo_in;
end else begin
// else just keep
data_fifo[i] <= data_fifo[i];
end
end
end
// Wishbone signal generation
// We only do word transfers
assign wb_sel_o = 4'hf;
// The data of the payload flits
assign wb_dat_o = buf_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB];
// Assign stored (and incremented) address to wishbone interface
assign wb_adr_o = address;
//FSM
// Next state, counting, control signals
always @(*) begin
// Default values are old values
nxt_address = address;
nxt_resp_wsize = resp_wsize;
nxt_end_of_request = end_of_request;
nxt_src_address = src_address;
nxt_src_tile = src_tile;
nxt_end_of_request = end_of_request;
nxt_packet_id = packet_id;
nxt_wb_resp_count = wb_resp_count;
nxt_noc_resp_packet_wcount = noc_resp_packet_wcount;
nxt_noc_resp_packet_wsize = noc_resp_packet_wsize;
nxt_wb_waiting = wb_waiting;
nxt_noc_resp_wcounter = noc_resp_wcounter;
// Default control signals
wb_cyc_o = 1'b0;
wb_stb_o = 1'b0;
wb_we_o = 1'b0;
wb_bte_o = 2'b00;
wb_cti_o = 3'b000;
noc_out_valid = 1'b0;
noc_out_flit = 34'h0;
data_fifo_push = 1'b0;
data_fifo_pop = 1'b0;
buf_ready = 1'b0;
case (state)
STATE_IDLE: begin
buf_ready= 1'b1;
nxt_end_of_request = buf_flit[`PACKET_REQ_LAST];
nxt_src_tile = buf_flit[`SOURCE_MSB:`SOURCE_LSB];
nxt_resp_wsize = buf_flit[`SIZE_MSB:`SIZE_LSB];
nxt_packet_id = buf_flit[`PACKET_ID_MSB:`PACKET_ID_LSB];
nxt_noc_resp_wcounter = 0;
nxt_wb_resp_count = 1;
if (buf_valid) begin
if (buf_flit[`PACKET_TYPE_MSB:`PACKET_TYPE_LSB] == `PACKET_TYPE_L2R_REQ) begin
nxt_state = STATE_L2R_GETADDR;
end else if(buf_flit[`PACKET_TYPE_MSB:`PACKET_TYPE_LSB] == `PACKET_TYPE_R2L_REQ) begin
nxt_state = STATE_R2L_GETLADDR;
end else begin
// now we have a problem...
// must not happen
nxt_state = STATE_IDLE;
end
end else begin
nxt_state = STATE_IDLE;
end
end // case: STATE_IDLE
//L2R-handling
STATE_L2R_GETADDR: begin
buf_ready = 1'b1;
nxt_address = buf_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB];
if (buf_valid) begin
nxt_state = STATE_L2R_DATA;
end else begin
nxt_state = STATE_L2R_GETADDR;
end
end
STATE_L2R_DATA: begin
if (buf_last_flit)
wb_cti_o = 3'b111;
else
wb_cti_o = 3'b010;
wb_cyc_o = 1'b1;
wb_stb_o = 1'b1;
wb_we_o = 1'b1;
if (wb_ack_i) begin
nxt_address = address + 4;
buf_ready = 1'b1;
if (buf_last_flit) begin
if (end_of_request) begin
nxt_state = STATE_L2R_SENDRESP;
end else begin
nxt_state = STATE_IDLE;
end
end else begin
nxt_state = STATE_L2R_DATA;
end
end else begin
buf_ready = 1'b0;
nxt_state = STATE_L2R_DATA;
end
end // case: STATE_L2R_DATA
STATE_L2R_SENDRESP: begin
noc_out_valid = 1'b1;
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_SINGLE;
noc_out_flit[`FLIT_DEST_MSB:`FLIT_DEST_LSB] = src_tile;
noc_out_flit[`PACKET_CLASS_MSB:`PACKET_CLASS_LSB] = `PACKET_CLASS_DMA;
noc_out_flit[`PACKET_ID_MSB:`PACKET_ID_LSB] = packet_id;
noc_out_flit[`PACKET_TYPE_MSB:`PACKET_TYPE_LSB] = `PACKET_TYPE_L2R_RESP;
if (noc_out_ready) begin
nxt_state = STATE_IDLE;
end else begin
nxt_state = STATE_L2R_SENDRESP;
end
end // case: STATE_L2R_SENDRESP
//R2L handling
STATE_R2L_GETLADDR: begin
buf_ready = 1'b1;
nxt_address = buf_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB];
if (buf_valid) begin
nxt_state = STATE_R2L_GETRADDR;
end else begin
nxt_state = STATE_R2L_GETLADDR;
end
end
STATE_R2L_GETRADDR: begin
buf_ready = 1'b1;
nxt_src_address = buf_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB];
if (buf_valid) begin
nxt_state = STATE_R2L_GENHDR;
end else begin
nxt_state = STATE_R2L_GETRADDR;
end
end
STATE_R2L_GENHDR: begin
noc_out_valid = 1'b1;
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_HEADER;
noc_out_flit[`FLIT_DEST_MSB:`FLIT_DEST_LSB] = src_tile;
noc_out_flit[`PACKET_CLASS_MSB:`PACKET_CLASS_LSB] = `PACKET_CLASS_DMA;
noc_out_flit[`PACKET_ID_MSB:`PACKET_ID_LSB] = packet_id;
noc_out_flit[`SOURCE_MSB:`SOURCE_LSB] = tileid;
noc_out_flit[`PACKET_TYPE_MSB:`PACKET_TYPE_LSB] = `PACKET_TYPE_R2L_RESP;
if ((noc_resp_wcounter + (noc_packet_size -2)) < resp_wsize) begin
// This is not the last packet in the respuest ((noc_packet_size -2) words*4 bytes=120)
// Only (noc_packet_size -2) flits are availabel for the payload,
// because we need a header-flit and an address-flit, too.
noc_out_flit[`SIZE_MSB:`SIZE_LSB] = 7'd120;
noc_out_flit[`PACKET_RESP_LAST] = 1'b0;
nxt_noc_resp_packet_wsize = noc_packet_size -2;
// count is the current transfer number
nxt_noc_resp_packet_wcount = 5'd1;
end else begin
// This is the last packet in the respuest
noc_out_flit[`SIZE_MSB:`SIZE_LSB] = resp_wsize - noc_resp_wcounter;
noc_out_flit[`PACKET_RESP_LAST] = 1'b1;
nxt_noc_resp_packet_wsize = resp_wsize - noc_resp_wcounter;
// count is the current transfer number
nxt_noc_resp_packet_wcount = 5'd1;
end // else: !if((noc_resp_wcounter + (noc_packet_size -2)) < resp_wsize)
// change to next state if successful
if (noc_out_ready)
nxt_state = STATE_R2L_GENADDR;
else
nxt_state = STATE_R2L_GENHDR;
end // case: STATE_R2L_GENHDR
STATE_R2L_GENADDR: begin
noc_out_valid = 1'b1;
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_PAYLOAD;
noc_out_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB] = src_address + (noc_resp_wcounter << 2);
if (noc_out_ready) begin
nxt_state = STATE_R2L_DATA;
end else begin
nxt_state = STATE_R2L_GENADDR;
end
end // case: `NOC_RESP_R2L_GENADDR
STATE_R2L_DATA: begin
// NOC-handling
// transfer data to noc if available
noc_out_valid = data_fifo_valid;
noc_out_flit[`FLIT_CONTENT_MSB:`FLIT_CONTENT_LSB] = data_fifo_out;
//TODO: Rearange ifs
if (noc_resp_packet_wcount==noc_resp_packet_wsize) begin
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_LAST;
if (noc_out_valid & noc_out_ready) begin
data_fifo_pop = 1'b1;
if ((noc_resp_wcounter + (noc_packet_size -2)) < resp_wsize) begin
// Only (noc_packet_size -2) flits are availabel for the payload,
// because we need a header-flit and an address-flit, too.
//this was not the last packet of the response
nxt_state = STATE_R2L_GENHDR;
nxt_noc_resp_wcounter = noc_resp_wcounter + noc_resp_packet_wcount;
end else begin
//this is the last packet of the response
nxt_state = STATE_IDLE;
end
end else begin
nxt_state = STATE_R2L_DATA;
end
end else begin //not LAST
noc_out_flit[`FLIT_TYPE_MSB:`FLIT_TYPE_LSB] = `FLIT_TYPE_PAYLOAD;
if (noc_out_valid & noc_out_ready) begin
data_fifo_pop = 1'b1;
nxt_noc_resp_packet_wcount = noc_resp_packet_wcount + 1;
end
nxt_state = STATE_R2L_DATA;
end
//FIFO-handling
if (wb_waiting) begin //hidden state
//don't get data from the bus
wb_stb_o = 1'b0;
wb_cyc_o = 1'b0;
data_fifo_push = 1'b0;
if (data_fifo_ready) begin
nxt_wb_waiting = 1'b0;
end else begin
nxt_wb_waiting = 1'b1;
end
end else begin //not wb_waiting
// Signal cycle and strobe. We do bursts, but don't insert
// wait states, so both of them are always equal.
if ((noc_resp_packet_wcount==noc_resp_packet_wsize) & noc_out_valid & noc_out_ready) begin
wb_stb_o = 1'b0;
wb_cyc_o = 1'b0;
end else begin
wb_stb_o = 1'b1;
wb_cyc_o = 1'b1;
end
// TODO: why not generate address from the base address + counter<<2?
if (~data_fifo_ready | (wb_resp_count==resp_wsize)) begin
wb_cti_o = 3'b111;
end else begin
wb_cti_o = 3'b111;
end
if (wb_ack_i) begin
// When this was successfull..
if (~data_fifo_ready | (wb_resp_count==resp_wsize)) begin
nxt_wb_waiting = 1'b1;
end else begin
nxt_wb_waiting = 1'b0;
end
nxt_wb_resp_count = wb_resp_count + 1;
nxt_address = address + 4;
data_fifo_push = 1'b1;
end else begin
// ..otherwise we still wait for the acknowledgement
nxt_wb_resp_count = wb_resp_count;
nxt_address = address;
data_fifo_push = 1'b0;
nxt_wb_waiting = 1'b0;
end
end // else: !if(wb_waiting)
end // case: STATE_R2L_DATA
default: begin
nxt_state = STATE_IDLE;
end
endcase // case (state)
end
always @(posedge clk) begin
if (rst) begin
state <= STATE_IDLE;
address <= 32'h0;
end_of_request <= 1'b0;
src_tile <= 0;
resp_wsize <= 0;
packet_id <= 0;
src_address <= 0;
noc_resp_wcounter <= 0;
noc_resp_packet_wsize <= 5'h0;
noc_resp_packet_wcount <= 5'h0;
noc_resp_packet_wcount <= 0;
wb_resp_count <= 0;
wb_waiting <= 0;
end else begin
state <= nxt_state;
address <= nxt_address;
end_of_request <= nxt_end_of_request;
src_tile <= nxt_src_tile;
resp_wsize <= nxt_resp_wsize;
packet_id <= nxt_packet_id;
src_address <= nxt_src_address;
noc_resp_wcounter <= nxt_noc_resp_wcounter;
noc_resp_packet_wsize <= nxt_noc_resp_packet_wsize;
noc_resp_packet_wcount <= nxt_noc_resp_packet_wcount;
wb_resp_count <= nxt_wb_resp_count;
wb_waiting <= nxt_wb_waiting;
end
end
endmodule // lisnoc_dma_target
// Local Variables:
// verilog-library-directories:("../infrastructure")
// verilog-auto-inst-param-value: t
// End:
|