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//////////////////////////////////////////////////////////////////////
//// ////
//// uart_top.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core top level. ////
//// ////
//// Known problems (limits): ////
//// Note that transmitter and receiver instances are inside ////
//// the uart_regs.v file. ////
//// ////
//// To Do: ////
//// Nothing so far. ////
//// ////
//// Author(s): ////
//// - gorban@opencores.org ////
//// - Jacob Gorban ////
//// - Igor Mohor (igorm@opencores.org) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.18 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.17 2001/12/19 08:40:03 mohor
// Warnings fixed (unused signals removed).
//
// Revision 1.16 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.15 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.14 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.13 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.12 2001/08/25 15:46:19 gorban
// Modified port names again
//
// Revision 1.11 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.10 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_top (
wb_clk_i,
// Wishbone signals
wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_err_o, wb_ack_o, wb_sel_i,
int_o, // interrupt request
// UART signals
// serial input/output
stx_pad_o, srx_pad_i,
// modem signals
rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
`ifdef UART_HAS_BAUDRATE_OUTPUT
, baud_o
`endif
);
parameter SIM = 0;
parameter debug = 0;
input wb_clk_i;
// WISHBONE interface
input wb_rst_i;
input [2:0] wb_adr_i;
input [7:0] wb_dat_i;
output [7:0] wb_dat_o;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
output wb_err_o;
output wb_ack_o;
output int_o;
// UART signals
input srx_pad_i;
output stx_pad_o;
output rts_pad_o;
input cts_pad_i;
output dtr_pad_o;
input dsr_pad_i;
input ri_pad_i;
input dcd_pad_i;
// optional baudrate output
`ifdef UART_HAS_BAUDRATE_OUTPUT
output baud_o;
`endif
wire stx_pad_o;
wire rts_pad_o;
wire dtr_pad_o;
wire [2:0] wb_adr_i;
wire [7:0] wb_dat_i;
wire [7:0] wb_dat_o;
wire [7:0] wb_dat8_i; // 8-bit internal data input
wire [7:0] wb_dat8_o; // 8-bit internal data output
wire [3:0] wb_sel_i; // WISHBONE select signal
wire [2:0] wb_adr_int;
wire we_o; // Write enable for registers
wire re_o; // Read enable for registers
//
// MODULE INSTANCES
//
assign wb_err_o = 1'b0;
//// WISHBONE interface module
uart_wb uart_wb_inst (
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_dat8_i(wb_dat8_i),
.wb_dat8_o(wb_dat8_o),
.wb_dat32_o(32'b0),
.wb_sel_i(4'b0),
.wb_we_i( wb_we_i ),
.wb_stb_i( wb_stb_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_ack_o( wb_ack_o ),
.wb_adr_i(wb_adr_i),
.wb_adr_int(wb_adr_int),
.we_o( we_o ),
.re_o(re_o)
);
// Registers
uart_regs #(.SIM (SIM)) uart_regs_inst (
.clk( wb_clk_i ),
.wb_rst_i( wb_rst_i ),
.wb_addr_i( wb_adr_int ),
.wb_dat_i( wb_dat8_i ),
.wb_dat_o( wb_dat8_o ),
.wb_we_i( we_o ),
.wb_re_i(re_o),
.modem_inputs( {cts_pad_i, dsr_pad_i,
ri_pad_i, dcd_pad_i} ),
.stx_pad_o( stx_pad_o ),
.srx_pad_i( srx_pad_i ),
.rts_pad_o( rts_pad_o ),
.dtr_pad_o( dtr_pad_o ),
.int_o( int_o )
`ifdef UART_HAS_BAUDRATE_OUTPUT
, .baud_o(baud_o)
`endif
);
initial
begin
if(debug) begin
`ifdef UART_HAS_BAUDRATE_OUTPUT
$display("(%m) UART INFO: Has baudrate output\n");
`else
$display("(%m) UART INFO: Doesn't have baudrate output\n");
`endif
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_transmitter.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core transmitter logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - gorban@opencores.org ////
//// - Jacob Gorban ////
//// - Igor Mohor (igorm@opencores.org) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.18 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2002/01/08 11:29:40 mohor
// tf_pop was too wide. Now it is only 1 clk cycle width.
//
// Revision 1.15 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.14 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.13 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.12 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.11 2001/10/29 17:00:46 gorban
// fixed parity sending and tx_fifo resets over- and underrun
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.6 2001/06/23 11:21:48 gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5 2001/06/02 14:28:14 gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:49 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.1 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_transmitter
#(parameter SIM = 0)
(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
input clk;
input wb_rst_i;
input [7:0] lcr;
input tf_push;
input [7:0] wb_dat_i;
input enable;
input tx_reset;
input lsr_mask; //reset of fifo
output stx_pad_o;
output [2:0] tstate;
output [`UART_FIFO_COUNTER_W-1:0] tf_count;
reg [2:0] tstate;
reg [4:0] counter;
reg [2:0] bit_counter; // counts the bits to be sent
reg [6:0] shift_out; // output shift register
reg stx_o_tmp;
reg parity_xor; // parity of the word
reg tf_pop;
reg bit_out;
// TX FIFO instance
//
// Transmitter FIFO signals
wire [`UART_FIFO_WIDTH-1:0] tf_data_in;
wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
wire tf_push;
wire tf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
assign tf_data_in = wb_dat_i;
uart_tfifo fifo_tx( // error bit signal is not used in transmitter FIFO
.clk( clk ),
.wb_rst_i( wb_rst_i ),
.data_in( tf_data_in ),
.data_out( tf_data_out ),
.push( tf_push ),
.pop( tf_pop ),
.overrun( tf_overrun ),
.count( tf_count ),
.fifo_reset( tx_reset ),
.reset_status(lsr_mask)
);
// TRANSMITTER FINAL STATE MACHINE
localparam s_idle = 3'd0;
localparam s_send_start = 3'd1;
localparam s_send_byte = 3'd2;
localparam s_send_parity = 3'd3;
localparam s_send_stop = 3'd4;
localparam s_pop_byte = 3'd5;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
tstate <= s_idle;
stx_o_tmp <= 1'b1;
counter <= 5'b0;
shift_out <= 7'b0;
bit_out <= 1'b0;
parity_xor <= 1'b0;
tf_pop <= 1'b0;
bit_counter <= 3'b0;
end
else
if (enable | SIM)
begin
case (tstate)
s_idle : if (~|tf_count) // if tf_count==0
begin
tstate <= s_idle;
stx_o_tmp <= 1'b1;
end
else
begin
tf_pop <= 1'b0;
stx_o_tmp <= 1'b1;
tstate <= s_pop_byte;
end
s_pop_byte : begin
tf_pop <= 1'b1;
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
2'b00 : begin
bit_counter <= 3'b100;
parity_xor <= ^tf_data_out[4:0];
end
2'b01 : begin
bit_counter <= 3'b101;
parity_xor <= ^tf_data_out[5:0];
end
2'b10 : begin
bit_counter <= 3'b110;
parity_xor <= ^tf_data_out[6:0];
end
2'b11 : begin
bit_counter <= 3'b111;
parity_xor <= ^tf_data_out[7:0];
end
endcase
{shift_out[6:0], bit_out} <= tf_data_out;
tstate <= s_send_start;
end
s_send_start : begin
tf_pop <= 1'b0;
if (~|counter)
counter <= 5'b01111;
else
if (counter == 5'b00001)
begin
counter <= 0;
tstate <= s_send_byte;
end
else
counter <= counter - 5'd1;
stx_o_tmp <= 1'b0;
if (SIM) begin
tstate <= s_idle;
$write("%c", tf_data_out);
$fflush(32'h80000001);
end
end
s_send_byte : begin
if (~|counter)
counter <= 5'b01111;
else
if (counter == 5'b00001)
begin
if (bit_counter > 3'b0)
begin
bit_counter <= bit_counter - 3'd1;
{shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]};
tstate <= s_send_byte;
end
else // end of byte
if (~lcr[`UART_LC_PE])
begin
tstate <= s_send_stop;
end
else
begin
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
2'b00: bit_out <= ~parity_xor;
2'b01: bit_out <= 1'b1;
2'b10: bit_out <= parity_xor;
2'b11: bit_out <= 1'b0;
endcase
tstate <= s_send_parity;
end
counter <= 0;
end
else
counter <= counter - 5'd1;
stx_o_tmp <= bit_out; // set output pin
end
s_send_parity : begin
if (~|counter)
counter <= 5'b01111;
else
if (counter == 5'b00001)
begin
counter <= 5'd0;
tstate <= s_send_stop;
end
else
counter <= counter - 5'd1;
stx_o_tmp <= bit_out;
end
s_send_stop : begin
if (~|counter)
begin
casez ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
3'b0??: counter <= 5'b01101; // 1 stop bit ok igor
3'b100: counter <= 5'b10101; // 1.5 stop bit
default: counter <= 5'b11101; // 2 stop bits
endcase
end
else
if (counter == 5'b00001)
begin
counter <= 0;
tstate <= s_idle;
end
else
counter <= counter - 5'd1;
stx_o_tmp <= 1'b1;
end
default : // should never get here
tstate <= s_idle;
endcase
end // end if enable
else
tf_pop <= 1'b0; // tf_pop must be 1 cycle width
end // transmitter logic
assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_wb.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core WISHBONE interface. ////
//// ////
//// Known problems (limits): ////
//// Inserts one wait state on all transfers. ////
//// Note affected signals and the way they are affected. ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - gorban@opencores.org ////
//// - Jacob Gorban ////
//// - Igor Mohor (igorm@opencores.org) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.16 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.15 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.12 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.11 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.10 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.9 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.8 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/21 19:12:01 gorban
// Corrected some Linter messages.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:13+02 jacob
// Initial revision
//
//
// UART core WISHBONE interface
//
// Author: Jacob Gorban (jacob.gorban@flextronicssemi.com)
// Company: Flextronics Semiconductor
//
`include "uart_defines.v"
module uart_wb (clk, wb_rst_i,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
we_o, re_o // Write and read enable output for the core
);
input clk;
// WISHBONE interface
input wb_rst_i;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
input [2:0] wb_adr_i; //WISHBONE address line
input [7:0] wb_dat_i; //input WISHBONE bus
output [7:0] wb_dat_o;
reg [7:0] wb_dat_o;
wire [7:0] wb_dat_i;
reg [7:0] wb_dat_is;
output [2:0] wb_adr_int; // internal signal for address bus
input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
output [7:0] wb_dat8_i;
input [31:0] wb_dat32_o; // 32 bit data output (for debug interface)
output wb_ack_o;
output we_o;
output re_o;
wire we_o;
reg wb_ack_o;
reg [7:0] wb_dat8_i;
wire [7:0] wb_dat8_o;
wire [2:0] wb_adr_int; // internal signal for address bus
reg [2:0] wb_adr_is;
reg wb_we_is;
reg wb_cyc_is;
reg wb_stb_is;
wire [3:0] wb_sel_i;
reg wre ;// timing control signal for write or read enable
// wb_ack_o FSM
reg [1:0] wbstate;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
wb_ack_o <= 1'b0;
wbstate <= 0;
wre <= 1'b1;
end else
case (wbstate)
0: begin
if (wb_stb_is & wb_cyc_is) begin
wre <= 0;
wbstate <= 1;
wb_ack_o <= 1;
end else begin
wre <= 1;
wb_ack_o <= 0;
end
end
1: begin
wb_ack_o <= 0;
wbstate <= 2;
wre <= 0;
end
2: begin
wb_ack_o <= 0;
wbstate <= 3;
wre <= 0;
end
3: begin
wb_ack_o <= 0;
wbstate <= 0;
wre <= 1;
end
endcase
assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers
assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers
// Sample input signals
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
wb_adr_is <= 0;
wb_we_is <= 0;
wb_cyc_is <= 0;
wb_stb_is <= 0;
wb_dat_is <= 0;
end else begin
wb_adr_is <= wb_adr_i;
wb_we_is <= wb_we_i;
wb_cyc_is <= wb_cyc_i;
wb_stb_is <= wb_stb_i;
wb_dat_is <= wb_dat_i;
end
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
wb_dat_o <= 0;
else
wb_dat_o <= wb_dat8_o;
always @(wb_dat_is)
wb_dat8_i = wb_dat_is;
assign wb_adr_int = wb_adr_is;
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a generic wishbone bus (B3). The number of masters and
* slaves are configurable. Ten slaves can be connected with a
* configurable memory map.
*
* Instantiation example:
* wb_bus_b3
* #(.DATA_WIDTH(32), .ADDR_WIDTH(32),
* .MASTERS(4), .SLAVES(2),
* .S0_RANGE_WIDTH(1), .S0_RANGE_MATCH(1'b0),
* .S1_RANGE_WIDTH(4), .S1_RANGE_MATCH(4'he))
* bus(.clk_i(clk), rst_i(rst),
* .m_adr_i({m_adr_i[3],..,m_adr_i[0]},
* ...
* );
*
* DATA_WIDTH and ADDR_WIDTH are defined in bits. DATA_WIDTH must be
* full bytes (i.e., multiple of 8)!
*
* The ports are flattened. That means, that all masters share the bus
* signal ports. With four masters and a data width of 32 bit the
* m_cyc_i port is 4 bit wide and the m_dat_i is 128 (=4*32) bit wide.
* The signals are arranged from right to left, meaning the m_dat_i is
* defined as [DATA_WIDTH*MASTERS-1:0] and each port m is assigned to
* [(m+1)*DATA_WIDTH-1:m*DATA_WIDTH].
*
* The memory map is defined with the S?_RANGE_WIDTH and
* S?_RANGE_MATCH parameters. The WIDTH sets the number of most
* significant bits (i.e., those from the left) that are relevant to
* define the memory range. The MATCH accordingly sets the value of
* those bits of the address that define the memory range.
*
* Example (32 bit addresses):
* Slave 0: 0x00000000-0x7fffffff
* Slave 1: 0x80000000-0xbfffffff
* Slave 2: 0xe0000000-0xe0ffffff
*
* Slave 0 is defined by the uppermost bit, which is 0 for this
* address range. Slave 1 is defined by the uppermost two bit, that
* are 10 for the memory range. Slave 2 is defined by 8 bit which are
* e0 for the memory range.
*
* This results in:
* S0_RANGE_WIDTH(1), S0_RANGE_MATCH(1'b0)
* S1_RANGE_WIDTH(2), S1_RANGE_MATCH(2'b10)
* S2_RANGE_WIDTH(8), S2_RANGE_MATCH(8'he0)
*
* Author(s):
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*/
module wb_bus_b3
#(
/* User parameters */
// Set the number of masters and slaves
parameter MASTERS = 2,
parameter SLAVES = 1,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = 1,
parameter S0_RANGE_WIDTH = 1,
parameter S0_RANGE_MATCH = 1'b0,
parameter S1_ENABLE = 1,
parameter S1_RANGE_WIDTH = 1,
parameter S1_RANGE_MATCH = 1'b0,
parameter S2_ENABLE = 1,
parameter S2_RANGE_WIDTH = 1,
parameter S2_RANGE_MATCH = 1'b0,
parameter S3_ENABLE = 1,
parameter S3_RANGE_WIDTH = 1,
parameter S3_RANGE_MATCH = 1'b0,
parameter S4_ENABLE = 1,
parameter S4_RANGE_WIDTH = 1,
parameter S4_RANGE_MATCH = 1'b0,
parameter S5_ENABLE = 1,
parameter S5_RANGE_WIDTH = 1,
parameter S5_RANGE_MATCH = 1'b0,
parameter S6_ENABLE = 1,
parameter S6_RANGE_WIDTH = 1,
parameter S6_RANGE_MATCH = 1'b0,
parameter S7_ENABLE = 1,
parameter S7_RANGE_WIDTH = 1,
parameter S7_RANGE_MATCH = 1'b0,
parameter S8_ENABLE = 1,
parameter S8_RANGE_WIDTH = 1,
parameter S8_RANGE_MATCH = 1'b0,
parameter S9_ENABLE = 1,
parameter S9_RANGE_WIDTH = 1,
parameter S9_RANGE_MATCH = 1'b0,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3
)
(
/* Ports */
input clk_i,
input rst_i,
input [ADDR_WIDTH*MASTERS-1:0] m_adr_i,
input [DATA_WIDTH*MASTERS-1:0] m_dat_i,
input [MASTERS-1:0] m_cyc_i,
input [MASTERS-1:0] m_stb_i,
input [SEL_WIDTH*MASTERS-1:0] m_sel_i,
input [MASTERS-1:0] m_we_i,
input [MASTERS*3-1:0] m_cti_i,
input [MASTERS*2-1:0] m_bte_i,
output [DATA_WIDTH*MASTERS-1:0] m_dat_o,
output [MASTERS-1:0] m_ack_o,
output [MASTERS-1:0] m_err_o,
output [MASTERS-1:0] m_rty_o,
output [ADDR_WIDTH*SLAVES-1:0] s_adr_o,
output [DATA_WIDTH*SLAVES-1:0] s_dat_o,
output [SLAVES-1:0] s_cyc_o,
output [SLAVES-1:0] s_stb_o,
output [SEL_WIDTH*SLAVES-1:0] s_sel_o,
output [SLAVES-1:0] s_we_o,
output [SLAVES*3-1:0] s_cti_o,
output [SLAVES*2-1:0] s_bte_o,
input [DATA_WIDTH*SLAVES-1:0] s_dat_i,
input [SLAVES-1:0] s_ack_i,
input [SLAVES-1:0] s_err_i,
input [SLAVES-1:0] s_rty_i,
// The snoop port forwards all write accesses on their success for
// one cycle.
output [DATA_WIDTH-1:0] snoop_adr_o,
output snoop_en_o,
input bus_hold,
output bus_hold_ack
);
wire [ADDR_WIDTH-1:0] bus_adr;
wire [DATA_WIDTH-1:0] bus_wdat;
wire bus_cyc;
wire bus_stb;
wire [SEL_WIDTH-1:0] bus_sel;
wire bus_we;
wire [2:0] bus_cti;
wire [1:0] bus_bte;
wire [DATA_WIDTH-1:0] bus_rdat;
wire bus_ack;
wire bus_err;
wire bus_rty;
/* wb_mux AUTO_TEMPLATE(
.s_dat_o (bus_wdat),
.s_dat_i (bus_rdat),
.s_\(.*\)_o (bus_\1),
.s_\(.*\)_i (bus_\1),
); */
wb_mux
#(.MASTERS(MASTERS), .ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH))
u_mux(/*AUTOINST*/
// Outputs
.m_dat_o (m_dat_o[DATA_WIDTH*MASTERS-1:0]),
.m_ack_o (m_ack_o[MASTERS-1:0]),
.m_err_o (m_err_o[MASTERS-1:0]),
.m_rty_o (m_rty_o[MASTERS-1:0]),
.s_adr_o (bus_adr), // Templated
.s_dat_o (bus_wdat), // Templated
.s_cyc_o (bus_cyc), // Templated
.s_stb_o (bus_stb), // Templated
.s_sel_o (bus_sel), // Templated
.s_we_o (bus_we), // Templated
.s_cti_o (bus_cti), // Templated
.s_bte_o (bus_bte), // Templated
.bus_hold_ack (bus_hold_ack),
// Inputs
.clk_i (clk_i),
.rst_i (rst_i),
.m_adr_i (m_adr_i[ADDR_WIDTH*MASTERS-1:0]),
.m_dat_i (m_dat_i[DATA_WIDTH*MASTERS-1:0]),
.m_cyc_i (m_cyc_i[MASTERS-1:0]),
.m_stb_i (m_stb_i[MASTERS-1:0]),
.m_sel_i (m_sel_i[SEL_WIDTH*MASTERS-1:0]),
.m_we_i (m_we_i[MASTERS-1:0]),
.m_cti_i (m_cti_i[MASTERS*3-1:0]),
.m_bte_i (m_bte_i[MASTERS*2-1:0]),
.s_dat_i (bus_rdat), // Templated
.s_ack_i (bus_ack), // Templated
.s_err_i (bus_err), // Templated
.s_rty_i (bus_rty), // Templated
.bus_hold (bus_hold));
/* wb_decode AUTO_TEMPLATE(
.m_dat_o (bus_rdat),
.m_dat_i (bus_wdat),
.m_\(.*\)_i (bus_\1),
.m_\(.*\)_o (bus_\1),
); */
wb_decode
#(.SLAVES(SLAVES), .ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.S0_ENABLE(S0_ENABLE),
.S0_RANGE_WIDTH(S0_RANGE_WIDTH), .S0_RANGE_MATCH(S0_RANGE_MATCH),
.S1_ENABLE(S1_ENABLE),
.S1_RANGE_WIDTH(S1_RANGE_WIDTH), .S1_RANGE_MATCH(S1_RANGE_MATCH),
.S2_ENABLE(S2_ENABLE),
.S2_RANGE_WIDTH(S2_RANGE_WIDTH), .S2_RANGE_MATCH(S2_RANGE_MATCH),
.S3_ENABLE(S3_ENABLE),
.S3_RANGE_WIDTH(S3_RANGE_WIDTH), .S3_RANGE_MATCH(S3_RANGE_MATCH),
.S4_ENABLE(S4_ENABLE),
.S4_RANGE_WIDTH(S4_RANGE_WIDTH), .S4_RANGE_MATCH(S4_RANGE_MATCH),
.S5_ENABLE(S5_ENABLE),
.S5_RANGE_WIDTH(S5_RANGE_WIDTH), .S5_RANGE_MATCH(S5_RANGE_MATCH),
.S6_ENABLE(S6_ENABLE),
.S6_RANGE_WIDTH(S6_RANGE_WIDTH), .S6_RANGE_MATCH(S6_RANGE_MATCH),
.S7_ENABLE(S7_ENABLE),
.S7_RANGE_WIDTH(S7_RANGE_WIDTH), .S7_RANGE_MATCH(S7_RANGE_MATCH),
.S8_ENABLE(S8_ENABLE),
.S8_RANGE_WIDTH(S8_RANGE_WIDTH), .S8_RANGE_MATCH(S8_RANGE_MATCH),
.S9_ENABLE(S9_ENABLE),
.S9_RANGE_WIDTH(S9_RANGE_WIDTH), .S9_RANGE_MATCH(S9_RANGE_MATCH))
u_decode(/*AUTOINST*/
// Outputs
.m_dat_o (bus_rdat), // Templated
.m_ack_o (bus_ack), // Templated
.m_err_o (bus_err), // Templated
.m_rty_o (bus_rty), // Templated
.s_adr_o (s_adr_o[ADDR_WIDTH*SLAVES-1:0]),
.s_dat_o (s_dat_o[DATA_WIDTH*SLAVES-1:0]),
.s_cyc_o (s_cyc_o[SLAVES-1:0]),
.s_stb_o (s_stb_o[SLAVES-1:0]),
.s_sel_o (s_sel_o[SEL_WIDTH*SLAVES-1:0]),
.s_we_o (s_we_o[SLAVES-1:0]),
.s_cti_o (s_cti_o[SLAVES*3-1:0]),
.s_bte_o (s_bte_o[SLAVES*2-1:0]),
// Inputs
.clk_i (clk_i),
.rst_i (rst_i),
.m_adr_i (bus_adr), // Templated
.m_dat_i (bus_wdat), // Templated
.m_cyc_i (bus_cyc), // Templated
.m_stb_i (bus_stb), // Templated
.m_sel_i (bus_sel), // Templated
.m_we_i (bus_we), // Templated
.m_cti_i (bus_cti), // Templated
.m_bte_i (bus_bte), // Templated
.s_dat_i (s_dat_i[DATA_WIDTH*SLAVES-1:0]),
.s_ack_i (s_ack_i[SLAVES-1:0]),
.s_err_i (s_err_i[SLAVES-1:0]),
.s_rty_i (s_rty_i[SLAVES-1:0]));
// Snoop address comes direct from master bus
assign snoop_adr_o = bus_adr;
// Snoop on acknowledge and write. Mask with strobe to be sure
// there actually is a something happing and no dangling signals
// and always ack'ing slaves.
assign snoop_en_o = bus_ack & bus_stb & bus_we;
endmodule // wb_bus_b3
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a generic slave selector for the Wishbone bus (B3). The
* number of slaves is configurable and up to ten slaves can be
* connected with a configurable memory map.
*
* Instantiation example:
* wb_sselect
* #(.DATA_WIDTH(32), .ADDR_WIDTH(32),
* .SLAVES(2),
* .S0_ENABLE (1), .S0_RANGE_WIDTH(1), .S0_RANGE_MATCH(1'b0),
* .S1_ENABLE (1), .S1_RANGE_WIDTH(4), .S1_RANGE_MATCH(4'he))
* sselect(.clk_i(clk), rst_i(rst),
* .s_adr_o({m_adr_o[3],..,m_adr_o[0]},
* ...
* );
*
* DATA_WIDTH and ADDR_WIDTH are defined in bits. DATA_WIDTH must be
* full bytes (i.e., multiple of 8)!
*
* The ports are flattened. That means, that all slaves share the bus
* signal ports. With four slaves and a data width of 32 bit the
* s_cyc_o port is 4 bit wide and the s_dat_o is 128 (=4*32) bit wide.
* The signals are arranged from right to left, meaning the s_dat_o is
* defined as [DATA_WIDTH*SLAVES-1:0] and each port s is assigned to
* [(s+1)*DATA_WIDTH-1:s*DATA_WIDTH].
*
* The memory map is defined with the S?_RANGE_WIDTH and
* S?_RANGE_MATCH parameters. The WIDTH sets the number of most
* significant bits (i.e., those from the left) that are relevant to
* define the memory range. The MATCH accordingly sets the value of
* those bits of the address that define the memory range.
*
* Example (32 bit addresses):
* Slave 0: 0x00000000-0x7fffffff
* Slave 1: 0x80000000-0xbfffffff
* Slave 2: 0xe0000000-0xe0ffffff
*
* Slave 0 is defined by the uppermost bit, which is 0 for this
* address range. Slave 1 is defined by the uppermost two bit, that
* are 10 for the memory range. Slave 2 is defined by 8 bit which are
* e0 for the memory range.
*
* This results in:
* S0_RANGE_WIDTH(1), S0_RANGE_MATCH(1'b0)
* S1_RANGE_WIDTH(2), S1_RANGE_MATCH(2'b10)
* S2_RANGE_WIDTH(8), S2_RANGE_MATCH(8'he0)
*
*
* Finally, the slaves can be individually masked to ease
* instantiation using the Sx_ENABLE parameter. By defaults all slaves
* are enabled (and selected as long as x < SLAVES).
*
* Author(s):
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*/
import noc_soc_config::*;
import noc_soc_functions::*;
module wb_decode
#(
/* User parameters */
// Set the number of slaves
parameter SLAVES = 10,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = CONFIG.ENABLE_S0,
parameter S0_RANGE_WIDTH = CONFIG.S0_RANGE_WIDTH,
parameter S0_RANGE_MATCH = CONFIG.S0_RANGE_MATCH,
parameter S1_ENABLE = CONFIG.ENABLE_S1,
parameter S1_RANGE_WIDTH = CONFIG.S1_RANGE_WIDTH,
parameter S1_RANGE_MATCH = CONFIG.S1_RANGE_MATCH,
parameter S2_ENABLE = CONFIG.ENABLE_S2,
parameter S2_RANGE_WIDTH = CONFIG.S2_RANGE_WIDTH,
parameter S2_RANGE_MATCH = CONFIG.S2_RANGE_MATCH,
parameter S3_ENABLE = CONFIG.ENABLE_S3,
parameter S3_RANGE_WIDTH = CONFIG.S3_RANGE_WIDTH,
parameter S3_RANGE_MATCH = CONFIG.S3_RANGE_MATCH,
parameter S4_ENABLE = CONFIG.ENABLE_S4,
parameter S4_RANGE_WIDTH = CONFIG.S4_RANGE_WIDTH,
parameter S4_RANGE_MATCH = CONFIG.S4_RANGE_MATCH,
parameter S5_ENABLE = CONFIG.ENABLE_S5,
parameter S5_RANGE_WIDTH = CONFIG.S5_RANGE_WIDTH,
parameter S5_RANGE_MATCH = CONFIG.S5_RANGE_MATCH,
parameter S6_ENABLE = CONFIG.ENABLE_S6,
parameter S6_RANGE_WIDTH = CONFIG.S6_RANGE_WIDTH,
parameter S6_RANGE_MATCH = CONFIG.S6_RANGE_MATCH,
parameter S7_ENABLE = CONFIG.ENABLE_S7,
parameter S7_RANGE_WIDTH = CONFIG.S7_RANGE_WIDTH,
parameter S7_RANGE_MATCH = CONFIG.S7_RANGE_MATCH,
parameter S8_ENABLE = CONFIG.ENABLE_S8,
parameter S8_RANGE_WIDTH = CONFIG.S8_RANGE_WIDTH,
parameter S8_RANGE_MATCH = CONFIG.S8_RANGE_MATCH,
parameter S9_ENABLE = CONFIG.ENABLE_S9,
parameter S9_RANGE_WIDTH = CONFIG.S9_RANGE_WIDTH,
parameter S9_RANGE_MATCH = CONFIG.S9_RANGE_MATCH
)
(
/* Ports */
input clk_i,
input rst_i,
input [ADDR_WIDTH-1:0] m_adr_i,
input [DATA_WIDTH-1:0] m_dat_i,
input m_cyc_i,
input m_stb_i,
input [SEL_WIDTH-1:0] m_sel_i,
input m_we_i,
input [2:0] m_cti_i,
input [1:0] m_bte_i,
output reg [DATA_WIDTH-1:0] m_dat_o,
output m_ack_o,
output m_err_o,
output m_rty_o,
output reg [ADDR_WIDTH*SLAVES-1:0] s_adr_o,
output reg [DATA_WIDTH*SLAVES-1:0] s_dat_o,
output reg [SLAVES-1:0] s_cyc_o,
output reg [SLAVES-1:0] s_stb_o,
output reg [SEL_WIDTH*SLAVES-1:0] s_sel_o,
output reg [SLAVES-1:0] s_we_o,
output reg [SLAVES*3-1:0] s_cti_o,
output reg [SLAVES*2-1:0] s_bte_o,
input [DATA_WIDTH*SLAVES-1:0] s_dat_i,
input [SLAVES-1:0] s_ack_i,
input [SLAVES-1:0] s_err_i,
input [SLAVES-1:0] s_rty_i
);
wire [SLAVES-1:0] s_select;
// Generate the slave select signals based on the master bus
// address and the memory range parameters
generate
if (SLAVES > 0)
assign s_select[0] = S0_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S0_RANGE_WIDTH] == S0_RANGE_MATCH[S0_RANGE_WIDTH-1:0]);
if (SLAVES > 1)
assign s_select[1] = S1_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S1_RANGE_WIDTH] == S1_RANGE_MATCH[S1_RANGE_WIDTH-1:0]);
if (SLAVES > 2)
assign s_select[2] = S2_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S2_RANGE_WIDTH] == S2_RANGE_MATCH[S2_RANGE_WIDTH-1:0]);
if (SLAVES > 3)
assign s_select[3] = S3_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S3_RANGE_WIDTH] == S3_RANGE_MATCH[S3_RANGE_WIDTH-1:0]);
if (SLAVES > 4)
assign s_select[4] = S4_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S4_RANGE_WIDTH] == S4_RANGE_MATCH[S4_RANGE_WIDTH-1:0]);
if (SLAVES > 5)
assign s_select[5] = S5_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S5_RANGE_WIDTH] == S5_RANGE_MATCH[S5_RANGE_WIDTH-1:0]);
if (SLAVES > 6)
assign s_select[6] = S6_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S6_RANGE_WIDTH] == S6_RANGE_MATCH[S6_RANGE_WIDTH-1:0]);
if (SLAVES > 7)
assign s_select[7] = S7_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S7_RANGE_WIDTH] == S7_RANGE_MATCH[S7_RANGE_WIDTH-1:0]);
if (SLAVES > 8)
assign s_select[8] = S8_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S8_RANGE_WIDTH] == S8_RANGE_MATCH[S8_RANGE_WIDTH-1:0]);
if (SLAVES > 9)
assign s_select[9] = S9_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S9_RANGE_WIDTH] == S9_RANGE_MATCH[S9_RANGE_WIDTH-1:0]);
endgenerate
// If two s_select are high or none, we might have an bus error
wire bus_error;
assign bus_error = ~^s_select;
reg m_ack, m_err, m_rty;
// Mux the slave bus based on the slave select signal (one hot!)
always @(*) begin : bus_s_mux
integer i;
m_dat_o = {DATA_WIDTH{1'b0}};
m_ack = 1'b0;
m_err = 1'b0;
m_rty = 1'b0;
for (i = 0; i < SLAVES; i = i + 1) begin
s_adr_o[i*ADDR_WIDTH +: ADDR_WIDTH] = m_adr_i;
s_dat_o[i*DATA_WIDTH +: DATA_WIDTH] = m_dat_i;
s_sel_o[i*SEL_WIDTH +: SEL_WIDTH] = m_sel_i;
s_we_o[i] = m_we_i;
s_cti_o[i*3 +: 3] = m_cti_i;
s_bte_o[i*2 +: 2] = m_bte_i;
s_cyc_o[i] = m_cyc_i & s_select[i];
s_stb_o[i] = m_stb_i & s_select[i];
if (s_select[i]) begin
m_dat_o = s_dat_i[i*DATA_WIDTH +: DATA_WIDTH];
m_ack = s_ack_i[i];
m_err = s_err_i[i];
m_rty = s_rty_i[i];
end
end
end
assign m_ack_o = m_ack & !bus_error;
assign m_err_o = m_err | bus_error;
assign m_rty_o = m_rty & !bus_error;
endmodule // wb_sselect
|
/* Copyright (c) 2013 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a round-robin arbiter for N participants, which is a
* parameter. The arbiter itself contains no register but is purely
* combinational which allows for various use cases. It simply
* calculates the next grant (nxt_gnt) based on the current grant
* (gnt) and the requests (req).
*
* That means, the gnt should in general be a register and especially
* there must be no combinational path from nxt_gnt to gnt!
*
* The normal usage is something like registering the gnt from
* nxt_gnt. Furthermore it is important that the gnt has an initial
* value which also must be one hot!
*
* Author(s):
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*/
import noc_soc_config::*;
import noc_soc_functions::*;
module wb_interconnect_arb_rr(/*AUTOARG*/
// Outputs
nxt_gnt,
// Inputs
req, gnt
);
/* User parameters */
// Number of participants
parameter N = 2;
/* Ports */
// Request
input [N-1:0] req;
// Current grant
input [N-1:0] gnt;
// Next grant
output [N-1:0] nxt_gnt;
// Sanity check
// synthesis translate_off
//always @(*)
// if (~^gnt)
// $fatal("signal <gnt> must always be one hot!");
// synthesis translate_on
// At a first glance, the computation of the nxt_gnt signal looks
// strange, but the principle is easy:
//
// * For each participant we compute a mask of width N. Based on
// the current gnt signal the mask contains a 1 at the position
// of other participants that will be served in round robin
// before the participant in case they request it.
//
// * The mask is 0 on all positions for the participant "left" of
// the currently granted participant as no other has precedence
// over this one. The mask has all one except the participant
// itself for the currently arbitrated participant.
//
// * From the mask and the request the nxt_gnt is calculated,
// roughly said as: if there is no other participant which has a
// higher precedence that also requests, the participant gets
// granted.
//
// Example 1:
// req = 1010
// gnt = 1000
// nxt_gnt = 0010
//
// mask[0] = 0000
// mask[1] = 0001
// mask[2] = 0011
// mask[3] = 0111
//
// Example 2:
// req = 1010
// gnt = 0100
// nxt_gnt = 1000
//
// mask[0] = 1000
// mask[1] = 1001
// mask[2] = 1011
// mask[3] = 0000
// Mask net
reg [N-1:0] mask [0:N-1];
// Calculate the mask
always @(*) begin : calc_mask
integer i,j;
for (i=0;i<N;i=i+1) begin
// Initialize mask as 0
mask[i] = {N{1'b0}};
// All participants to the "right" up to the current grant
// holder have precendence and therefore a 1 in the mask.
// First check if the next right from us has the grant.
// Afterwards the mask is calculated iteratively based on
// this.
if(i>0)
// For i=N:1 the next right is i-1
mask[i][i-1] = ~gnt[i-1];
else
// For i=0 the next right is N-1
mask[i][N-1] = ~gnt[N-1];
// Now the mask contains a 1 when the next right to us is not
// the grant holder. If it is the grant holder that means,
// that we are the next served (if necessary) as no other has
// higher precendence, which is then calculated in the
// following by filling up 1s up to the grant holder. To stop
// filling up there and not fill up any after this is
// iterative by always checking if the one before was not
// before the grant holder.
for (j=2;j<N;j=j+1) begin
if (i-j>=0)
mask[i][i-j] = mask[i][i-j+1] & ~gnt[i-j];
else if(i-j+1>=0)
mask[i][i-j+N] = mask[i][i-j+1] & ~gnt[i-j+N];
else
mask[i][i-j+N] = mask[i][i-j+N+1] & ~gnt[i-j+N];
end
end
end // always @ (*)
// Calculate the nxt_gnt
genvar k;
generate
for (k=0;k<N;k=k+1) begin : gen_nxt_gnt
// (mask[k] & req) masks all requests with higher precendence
// Example 1: 0: 0000 1: 0000 2: 0010 3: 0010
// Example 2: 0: 1000 1: 1000 2: 1010 3: 0000
//
// ~|(mask[k] & req) is there is none of them
// Example 1: 0: 1 1: 1 2: 0 3: 0
// Example 2: 1: 0 1: 0 2: 0 3: 1
//
// One might expect at this point that there was only one of
// them that matches, but this is guaranteed by the last part
// that is checking if this one has a request itself. In
// example 1, k=0 does not have a request, if it had, the
// result of the previous calculation would be 0 for k=1.
// Therefore: (~|(mask[k] & req) & req[k]) selects the next one.
// Example 1: 0: 0 1: 1 2: 0 3: 0
// Example 2: 0: 0 1: 0 2: 0 3: 1
//
// This is already the result. (0010 and 1000). Nevertheless,
// it is necessary to capture the case of no request at all
// (~|req). In that case, nxt_gnt would be 0, what iself
// leads to a problem in the next cycle (always grants).
// Therefore the current gnt is hold in case of no request by
// (~|req & gnt[k]).
assign nxt_gnt[k] = (~|(mask[k] & req) & req[k]) | (~|req & gnt[k]);
end
endgenerate
endmodule // wb_interconnect_arb_rr
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a generic wishbone bus multiplexer (B3). The number of
* masters is configurable.
*
* DATA_WIDTH and ADDR_WIDTH are defined in bits. DATA_WIDTH must be
* full bytes (i.e., multiple of 8)!
*
* The ports are flattened. That means, that all masters share the bus
* signal ports. With four masters and a data width of 32 bit the
* m_cyc_i port is 4 bit wide and the m_dat_i is 128 (=4*32) bit wide.
* The signals are arranged from right to left, meaning the m_dat_i is
* defined as [DATA_WIDTH*MASTERS-1:0] and each port m is assigned to
* [(m+1)*DATA_WIDTH-1:m*DATA_WIDTH].
*
* Author(s):
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*/
// TODO: * check bus hold signal correctness
import noc_soc_config::*;
import noc_soc_functions::*;
module wb_mux
#(
/* User parameters */
// Set the number of slaves
parameter MASTERS = 1,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3
)
(
/* Ports */
input clk_i,
input rst_i,
input [ADDR_WIDTH*MASTERS-1:0] m_adr_i,
input [DATA_WIDTH*MASTERS-1:0] m_dat_i,
input [MASTERS-1:0] m_cyc_i,
input [MASTERS-1:0] m_stb_i,
input [SEL_WIDTH*MASTERS-1:0] m_sel_i,
input [MASTERS-1:0] m_we_i,
input [MASTERS*3-1:0] m_cti_i,
input [MASTERS*2-1:0] m_bte_i,
output reg [DATA_WIDTH*MASTERS-1:0] m_dat_o,
output reg [MASTERS-1:0] m_ack_o,
output reg [MASTERS-1:0] m_err_o,
output reg [MASTERS-1:0] m_rty_o,
output reg [ADDR_WIDTH-1:0] s_adr_o,
output reg [DATA_WIDTH-1:0] s_dat_o,
output reg s_cyc_o,
output reg s_stb_o,
output reg [SEL_WIDTH-1:0] s_sel_o,
output reg s_we_o,
output reg [2:0] s_cti_o,
output reg [1:0] s_bte_o,
input [DATA_WIDTH-1:0] s_dat_i,
input s_ack_i,
input s_err_i,
input s_rty_i,
input bus_hold,
output reg bus_hold_ack
);
// The granted master is one hot encoded
wire [MASTERS-1:0] grant;
// The granted master from previous cycle (register)
reg [MASTERS-1:0] prev_grant;
// This is a net that masks the actual requests. The arbiter
// selects a different master each cycle. Therefore we need to
// actively control the return of the bus arbitration. That means
// as long as the granted master still holds is cycle signal, we
// mask out all other requests (be setting the requests to grant).
// When the cycle signal is released, we set the request to all
// masters cycle signals.
reg [MASTERS-1:0] m_req;
// This is the arbitration net from round robin
wire [MASTERS-1:0] arb_grant;
reg [MASTERS-1:0] prev_arb_grant;
// It is masked with the bus_hold_ack to hold back the arbitration
// as long as the bus is held
assign grant = arb_grant & {MASTERS{!bus_hold_ack}};
always @(*) begin
if (|(m_cyc_i & prev_grant)) begin
// The bus is not released this cycle
m_req = prev_grant;
bus_hold_ack = 1'b0;
end else begin
m_req = m_cyc_i;
bus_hold_ack = bus_hold;
end
end
// We register the grant signal. This is needed nevertheless for
// fair arbitration (round robin)
always @(posedge clk_i) begin
if (rst_i) begin
prev_arb_grant <= {{MASTERS-1{1'b0}},1'b1};
prev_grant <= {{MASTERS-1{1'b0}},1'b1};
end else begin
prev_arb_grant <= arb_grant;
prev_grant <= grant;
end
end
/* wb_interconnect_arb_rr AUTO_TEMPLATE(
.gnt (prev_arb_grant),
.nxt_gnt (arb_grant),
.req (m_req),
); */
wb_interconnect_arb_rr
#(.N(MASTERS))
u_arbiter(/*AUTOINST*/
// Outputs
.nxt_gnt (arb_grant), // Templated
// Inputs
.req (m_req), // Templated
.gnt (prev_arb_grant)); // Templated
// Mux the bus based on the grant signal which must be one hot!
always @(*) begin : bus_m_mux
integer i;
s_adr_o = {ADDR_WIDTH{1'bx}};
s_dat_o = {DATA_WIDTH{1'bx}};
s_sel_o = {SEL_WIDTH{1'bx}};
s_we_o = 1'bx;
s_cti_o = 3'bx;
s_bte_o = 2'bx;
s_cyc_o = 1'b0;
s_stb_o = 1'b0;
for (i = 0; i < MASTERS; i = i + 1) begin
m_dat_o[i*DATA_WIDTH +: DATA_WIDTH] = s_dat_i;
m_ack_o[i] = grant[i] & s_ack_i;
m_err_o[i] = grant[i] & s_err_i;
m_rty_o[i] = grant[i] & s_rty_i;
if (grant[i]) begin
s_adr_o = m_adr_i[(i+1)*ADDR_WIDTH-1 -: ADDR_WIDTH];
s_dat_o = m_dat_i[(i+1)*DATA_WIDTH-1 -: DATA_WIDTH];
s_sel_o = m_sel_i[(i+1)*SEL_WIDTH-1 -: SEL_WIDTH];
s_we_o = m_we_i[i];
s_cti_o = m_cti_i[(i+1)*3-1 -: 3];
s_bte_o = m_bte_i[(i+1)*2-1 -: 2];
s_cyc_o = m_cyc_i[i];
s_stb_o = m_stb_i[i];
end
end
end
endmodule // wb_sselect
|
`timescale 1ns/1ps
module AEStopwrapper(MASRST, clk, mode, rst, kld, ld, done, key, text_in, text_out, Pause, WSI, WRSTN, SelectWIR, ShiftWR, CaptureWR, WSO, DWR, DO, DAD, SPCREQ, SPCDIS, MRST, DBus, Sel, TP1, TPE1);
input clk, rst, mode, ld, kld, MASRST;
output done;
input SPCREQ;
input SPCDIS;
input [127:0] key;
input [127:0] text_in;
output [127:0] text_out;
input Pause; // my input
input WSI, WRSTN, SelectWIR, ShiftWR, CaptureWR;
output WSO;
input MRST;
input [31:0] DBus;
input [1:0] Sel;
output [31:0] TP1;
output TPE1;
// only functional inputs/outputs are in wrapper boundary
wire [127:0] text_out1;
wire [127:0] text_inA;
wire [127:0] keyA;
wire [127:0] text_outA;
wire Scan_en, Hold_en_incell, Hold_en_outcell;
wire test_din, test_dout;
wire Bypass_d, Bypass_q;
wire WIR_din, WIR_2_q, WIR_1_q, WIR_dout;
wire [382:0] CTI; // first input, key, and finally output
wire CK; // scan clock here equal to functional clock
// first method of replicating
// Debug - SPC interface and storage
wire [7:0] EV;
wire [31:0] Val;
reg [31:0] tempbuff[0:3];
reg [1:0] cru;
always @(posedge clk)
begin
if (MASRST == 1'b1)
begin
tempbuff[0] <= 'd0;
tempbuff[1] <= 'd0;
tempbuff[2] <= 'd0;
tempbuff[3] <= 'd0;
cru <= 'd0;
end
else if ((EV[7:0] > 'd0) || (cru > 2'b0))
begin
cru <= cru + 2'b1;
tempbuff[3] <= tempbuff[2];
tempbuff[2] <= tempbuff[1];
tempbuff[1] <= tempbuff[0];
tempbuff[0] <= Val;
end
else
begin
cru <= 2'b0;
// needs to store tempbuff to wait for SPCREQ
end
end
reg [7:0] EV2;
always @(posedge clk)
begin
EV2 <= EV;
end
// SPCREQ is SPC asking for info and SPCDIS is disabling the AES fully
// first the design
// generating EN inside
reg EN;
reg cert;
wire [31:0] w01, w02, w03, w04;
assign text_outA = EN? text_out1:128'b0;
aes_encoder_decoder AES(.clk(clk && Pause && cert), .mode(mode),.rst(rst && SPCDIS), .kld(kld),.ld(ld), .done(done), .key(keyA), .text_in(text_inA),
.text_out(text_out1), .w01(w01), .w02(w02), .w03(w03), .w04(w04));
debug_AES A0 (clk, MRST, mode, ld, Pause, done, keyA, text_inA, text_out1, DBus, Sel, EV, Val, TP1, TPE1, w01, w02, w03, w04);
////added signals to interface with security policy controller THE SECURITY
//WRAPPER
///**********************************************************///
output reg DWR;
output reg [31:0]DO, DAD;
reg ld1;
reg rst1;
reg Pause1;
reg resultcheck;
// logic for writing new info into the SPC Controller data cache
always @(posedge clk)
begin
ld1 <= ld;
rst1 <= rst;
Pause1 <= Pause;
end
reg [3:0] counter2;
reg [3:0] state;
reg [127:0] buff[0:3];
always @(posedge clk)
begin
if (((ld1 == 1'b1) && (ld == 1'b0) && (rst == 1'b1)&& (Pause == 1'b1) && (cert == 1'b1))||(counter2 == 4'd11))
begin
counter2 <= 4'd0;
end
else if ((counter2 < 4'd12) && (Pause == 1'b1) && (cert == 1'b1) && (rst && SPCDIS == 1'b1) && (ld == 1'b0)) // from the loading of b in the counter field
begin
counter2 <= counter2 + 4'd1;
end
end
/// the certification
always @(posedge clk)
begin
if (MASRST == 1'b1)
begin
cert <= 1'b1;
end
else if ((ld1 == 1'b1) && (ld == 1'b0) && (rst == 1'b1)&& (Pause == 1'b1))
begin
cert <= 1'b0;
end
else if (resultcheck == 1'b1) // verifying if the key meets randomness criteria (local implementation , doesnot have to send to SPC)
begin
cert <= 1'b1;
end
end
// random result check logic (very simple now)
//
always @(posedge clk)
begin
if (cert == 1'b0)
begin
// if ((keyA[127:64] == keyA[63:0]) && !((buff[2*(pastcount-1)] == keyA))) // verify the multiplication
if (!(keyA[127:64] == keyA[63:0]))
begin
resultcheck = 1'b1;
end
else
begin
resultcheck = 1'b0;
end
end
end
/// The past values storage
reg [1:0] pastcount;
always @(*)
begin
if ((ld1 == 1'b1) && (ld == 1'b0) && (rst == 1'b1)&& (Pause == 1'b1))
begin
pastcount = pastcount + 2'd1;
end
else if (MASRST == 1'b1)
begin
pastcount = 2'd0;
end
end // need to incorporate a MASTER RESET signifying boot FROM SYTEM CONTROLLER
// what about the buffer
always @(pastcount) // should ideally be always @(pastcount)
//begin
//if ((ld1 == 1'b1) && (ld == 1'b0) && (rst == 1'b1)&& (Pause == 1'b1)) // start of operation
begin
if (pastcount > 2'd0)
begin
buff[2*pastcount-1] <= text_inA;
buff[2*pastcount] <= keyA;
end
//end
end // need to incorporate a MASTER RESET FROM SYTEM CONTROLLER
// the enable control
always @(posedge clk)
begin
if ((WRSTN == 1'b1) && (ShiftWR == 1'b0)) // normal mode (can be in other terms as well)
begin
if (done == 1'b1)
begin
EN <= 1'b1;
end
else
begin
EN <= 1'b0;
end
end
else
begin
EN <= 1'b1; // test modes where every text_out needs to be seen
end
end
// now the control state machine
//
always @(posedge clk)
begin
if (MASRST == 1'b1)
begin
state <= 4'd0;
end
else if ((WRSTN == 1'b1) && (ShiftWR == 1'b0)) // normal mode (CHECK THIS)
begin
if ((ld1 == 1'b1) && (ld == 1'b0) && (rst == 1'b1)&& (Pause == 1'b1))
begin
state <= 4'd1;
end
else if (counter2 == 4'd1)
begin
state <= 4'd2; // perhaps telling if key and/or plaintext is same as last time (to prevent any chance of replay attack (NONCE)) as well as sending result of certofocation
end
//else if ((counter2 == 4'd11) // end of operation
else if (done == 1'b1)
begin
state <= 4'd3;
end
else if ((Pause1 == 1'b1) && (Pause == 1'b0))
begin
state <= 4'd4;
end
else if ((Pause1 == 1'b0) && (Pause == 1'b1))
begin
state <= 4'd5;
end
else if (SPCREQ == 1'b1) // need to add this
begin
state <= 4'd14;
end
else if (EV > 8'd0)
begin
state <= 4'd7;
end
else
begin
state <= 4'd6;
end
end
else //////// TEST MODE
begin
state <= 4'd0;
// if ((ld1 == 1'b1) && (ld == 1'b0) && (rst == 1'b1)&& (Pause == 1'b1))
//begin
// state <= 4'd7;
//end
//else if (counter2 == 4'd1)
//begin
// state <= 4'd8; // perhaps telling if key and/or plaintext is same as last time (to prevent any chance of replay attack (NONCE)) as well as sending result of certofocation
//end
////else if ((counter2 == 4'd11) // end of operation
//else if (done == 1'b1)
//begin
// state <= 4'd9;
//end
//else if ((Pause1 == 1'b1) && (Pause == 1'b0))
//begin
// state <= 4'd10;
//end
//else if ((Pause1 == 1'b0) && (Pause == 1'b1))
//begin
// state <= 4'd11;
//end
//else if (SPCREQ == 1'b1) // need to add this
//begin
// state <= 4'd12;
//end
//else
//begin
// state <= 4'd13;
//end
end
end
always @(state)
begin
//if ((SPCDIS && cert) == 1'b1) // an addition (CAN REMOVE THE DWR ADDITIONS LATER)
//begin
case(state)
4'd0: begin
DWR = 1'b0;
DAD = 32'd0;
DO = 32'd0;
end
4'd1: begin
DWR = 1'b1;
DAD = 32'd80;
DO = {mode, 27'b0, state};
end
4'd2: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {resultcheck, 27'b0, state};
end
4'd3: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {28'b0, state};
end
4'd4: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {counter2, 24'd0, state};
end
4'd5: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {28'd0, state};
end
4'd6: begin
DWR = 1'b0;
DAD = DAD;
DO = 32'd0;
end
4'd7: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {counter2, 16'd0, EV2, state};
end
//4'd8: begin
// DWR = (1'b1 && cert && SPCDIS);
// DAD = DAD + 32'd1;
// DO = {resultcheck, 27'b0, state};
// end
//4'd9: begin
// DWR = (1'b1 && cert && SPCDIS);
// DAD = DAD + 32'd1;
// DO = {28'b0, state};
// end
//4'd10: begin
// DWR = (1'b1 && cert && SPCDIS);
// DAD = DAD + 32'd1;
// DO = {counter2, 24'd0, state};
// end
//4'd11: begin
// DWR = (1'b1 && cert && SPCDIS);
// DAD = DAD + 32'd1;
// DO = {28'd0, state};
// end
//4'd12: begin
// DWR = (1'b1 && cert && SPCDIS);
// DAD = DAD + 32'd1;
// DO = {text_out1[15:0], counter2, 8'b0, state};
// end
//4'd13: begin
// DWR = 1'b0;
// DAD = DAD;
// DO = 32'd0;
// end
4'd14: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {text_out1[15:0], counter2, 8'b0, state};
end
// fill in the rest of the stuff
endcase
//end
end
///**********************************************************///
// all the boundary scan stuff
assign CK = (clk && Pause && SPCDIS);
assign Scan_en = (WRSTN==1'b1) ? ShiftWR : 1'b0;
assign Hold_en_incell = (WRSTN==1'b1) ? 1'b0 : (({WIR_2_q, WIR_1_q, WIR_dout}==3'b010) ? (~CaptureWR) : 1); //WIR==3'b010 EXTEST
assign Hold_en_outcell = (WRSTN==1'b1) ? 1'b0 : (({WIR_2_q, WIR_1_q, WIR_dout}==3'b100) ? 1 : (~CaptureWR)); //WIR==3'b100 INTEST
assign test_din = (WRSTN==1'b1 && Scan_en==1'b1 && SelectWIR==1'b0 && {WIR_2_q, WIR_1_q, WIR_dout}!=3'b001) ? WSI : 1'b0;
assign Bypass_d = (WRSTN==1'b1 && Scan_en==1'b1 && SelectWIR==1'b0 && {WIR_2_q, WIR_1_q, WIR_dout}==3'b001) ? WSI : 1'b0; //WIR==3'b001 BYPASS
assign WIR_din = (WRSTN==1'b1 && Scan_en==1'b1 && SelectWIR==1'b1) ? WSI : 1'b0; //WIR==3'b001 BYPASS
assign WSO = (~WRSTN) ? 1'b0 : (SelectWIR ? WIR_dout : (({WIR_2_q, WIR_1_q, WIR_dout}==3'b001) ? Bypass_q : test_dout));
//Bypass Register
dff dff_bypass(.CK(CK), .Q(Bypass_q), .D(Bypass_d));
//WIR
dff dff_WIR_2(.CK(CK), .Q(WIR_2_q), .D(WIR_din));
dff dff_WIR_1(.CK(CK), .Q(WIR_1_q), .D(WIR_2_q));
dff dff_WIR_0(.CK(CK), .Q(WIR_dout), .D(WIR_1_q));
//Input Wrapper Boundary Register
WBC WBC_I1(.clk(CK), .CTI(test_din), .CFI(text_in[0]), .Scan_en(Scan_en), .Hold_en(Hold_en_incell), .CTO(CTI[0]), .CFO(text_inA[0]));
// second method of replicating
genvar i;
generate
for (i = 0; i<127; i=i+1)
begin
WBC WBC_I(.clk(CK), .CTI(CTI[i]), .CFI(text_in[i+1]), .Scan_en(Scan_en), .Hold_en(Hold_en_incell), .CTO(CTI[i+1]), .CFO(text_inA[i+1]));
end
endgenerate
//genvar i;
generate
for (i = 0; i<128; i=i+1)
begin
WBC WBC_K(.clk(CK), .CTI(CTI[i+127]), .CFI(key[i]), .Scan_en(Scan_en), .Hold_en(Hold_en_incell), .CTO(CTI[i+1+127]), .CFO(keyA[i]));
end
endgenerate
//genvar i;
generate
for (i = 0; i<127; i=i+1)
begin
WBC WBC_O(.clk(CK), .CTI(CTI[i +255]), .CFI(text_outA[i]), .Scan_en(Scan_en), .Hold_en(Hold_en_outcell), .CTO(CTI[i+1 +255]), .CFO(text_out[i]));
end
endgenerate
WBC WBC_O1(.clk(CK), .CTI(CTI[382]), .CFI(text_outA[127]), .Scan_en(Scan_en), .Hold_en(Hold_en_outcell), .CTO(test_dout), .CFO(text_out[127]));
endmodule
// D flip-flop
module dff (CK,Q,D);
input CK,D;
output Q;
reg Q ;
always @(posedge CK)
Q <=D;
endmodule
// 2:1 MUX
module MUX (sel, in0, in1, out);
input sel, in0, in1;
output out;
assign out = sel? in1 : in0;
endmodule
// Wrapper boundary cell
module WBC (clk, CTI, CFI, Scan_en, Hold_en, CTO, CFO);
input clk, CTI, CFI, Scan_en, Hold_en;
output CTO, CFO;
wire DIN;
MUX MUX_in(.sel(Scan_en), .in0(CFO), .in1(CTI), .out(DIN));
MUX MUX_out(.sel(Hold_en), .in0(CFI), .in1(CTO), .out(CFO));
dff dff_1(.CK(clk), .Q(CTO), .D(DIN));
endmodule
|
// AES cipher/decipher unit
// Controlled by the "mode" signal
// "mode = 1 => cipher, mode = 0, => decipher
//`include "timescale.v"
// the top-level module
`timescale 1ns/1ps
module aes_encoder_decoder(clk, mode, rst, kld, ld, done, key, text_in, text_out, w01, w02, w03, w04);
input clk, rst, mode;
input ld;
input kld;
output done;
input [127:0] key;
input [127:0] text_in;
output [127:0] text_out;
output [31:0] w01, w02, w03, w04;
//input EN; // my input
// my additions HEHEHEHE
//wire [127:0] text_out1;
// Local clocks that control the mode of operation
wire clk_cipher, clk_decipher;
// Wires at the output MUX
wire [127:0] text_out_cipher;
wire [127:0] text_out_decipher;
wire done_cipher, done_decipher;
assign clk_cipher = clk & mode ;
assign clk_decipher = clk & (~mode) ;
// my additon
//assign text_out = EN? text_out1:128'b0;
// Multiplex the outputs
assign text_out = mode? text_out_cipher: text_out_decipher;
assign done = mode? done_cipher: done_decipher ;
// Intantiate the cipher
aes_cipher_top cipher ( .clk(clk_cipher),
.rst(rst),
.ld(ld),
.done(done_cipher),
.key(key),
.text_in(text_in),
.text_out(text_out_cipher), .w01(w01), .w02(w02), .w03(w03), .w04(w04));
// Intantiate the decipher
aes_inv_cipher_top decipher ( .clk(clk_decipher),
.rst(rst),
.kld(kld),
.ld(ld),
.done(done_decipher),
.key(key),
.text_in(text_in),
.text_out(text_out_decipher));
endmodule
// The "cipher" module
module aes_cipher_top(clk, rst, ld, done, key, text_in, text_out, w01, w02, w03, w04 );
input clk, rst;
input ld;
output done;
input [127:0] key;
input [127:0] text_in;
output [127:0] text_out;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
output [31:0] w01, w02, w03, w04;
wire [31:0] w0, w1, w2, w3;
reg [127:0] text_in_r;
reg [127:0] text_out;
reg [7:0] sa00, sa01, sa02, sa03;
reg [7:0] sa10, sa11, sa12, sa13;
reg [7:0] sa20, sa21, sa22, sa23;
reg [7:0] sa30, sa31, sa32, sa33;
wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next;
wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next;
wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next;
wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next;
wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub;
wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub;
wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub;
wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub;
wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr;
wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr;
wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr;
wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr;
wire [7:0] sa00_mc, sa01_mc, sa02_mc, sa03_mc;
wire [7:0] sa10_mc, sa11_mc, sa12_mc, sa13_mc;
wire [7:0] sa20_mc, sa21_mc, sa22_mc, sa23_mc;
wire [7:0] sa30_mc, sa31_mc, sa32_mc, sa33_mc;
reg done, ld_r;
reg [3:0] dcnt;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign w01 = w0;
assign w02 = w1;
assign w03 = w2;
assign w04 = w3;
always @(posedge clk)
if(!rst) dcnt <= #1 4'h0;
else
if(ld) dcnt <= #1 4'hb;
else
if(|dcnt) dcnt <= #1 dcnt - 4'h1;
always @(posedge clk) done <= #1 !(|dcnt[3:1]) & dcnt[0] & !ld;
always @(posedge clk) if(ld) text_in_r <= #1 text_in;
always @(posedge clk) ld_r <= #1 ld;
////////////////////////////////////////////////////////////////////
//
// Initial Permutation (AddRoundKey)
//
always @(posedge clk) sa33 <= #1 ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_next;
always @(posedge clk) sa23 <= #1 ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_next;
always @(posedge clk) sa13 <= #1 ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_next;
always @(posedge clk) sa03 <= #1 ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_next;
always @(posedge clk) sa32 <= #1 ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_next;
always @(posedge clk) sa22 <= #1 ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_next;
always @(posedge clk) sa12 <= #1 ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_next;
always @(posedge clk) sa02 <= #1 ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_next;
always @(posedge clk) sa31 <= #1 ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_next;
always @(posedge clk) sa21 <= #1 ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_next;
always @(posedge clk) sa11 <= #1 ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_next;
always @(posedge clk) sa01 <= #1 ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_next;
always @(posedge clk) sa30 <= #1 ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_next;
always @(posedge clk) sa20 <= #1 ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_next;
always @(posedge clk) sa10 <= #1 ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_next;
always @(posedge clk) sa00 <= #1 ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_next;
////////////////////////////////////////////////////////////////////
//
// Round Permutations
//
assign sa00_sr = sa00_sub;
assign sa01_sr = sa01_sub;
assign sa02_sr = sa02_sub;
assign sa03_sr = sa03_sub;
assign sa10_sr = sa11_sub;
assign sa11_sr = sa12_sub;
assign sa12_sr = sa13_sub;
assign sa13_sr = sa10_sub;
assign sa20_sr = sa22_sub;
assign sa21_sr = sa23_sub;
assign sa22_sr = sa20_sub;
assign sa23_sr = sa21_sub;
assign sa30_sr = sa33_sub;
assign sa31_sr = sa30_sub;
assign sa32_sr = sa31_sub;
assign sa33_sr = sa32_sub;
assign {sa00_mc, sa10_mc, sa20_mc, sa30_mc} = mix_col(sa00_sr,sa10_sr,sa20_sr,sa30_sr);
assign {sa01_mc, sa11_mc, sa21_mc, sa31_mc} = mix_col(sa01_sr,sa11_sr,sa21_sr,sa31_sr);
assign {sa02_mc, sa12_mc, sa22_mc, sa32_mc} = mix_col(sa02_sr,sa12_sr,sa22_sr,sa32_sr);
assign {sa03_mc, sa13_mc, sa23_mc, sa33_mc} = mix_col(sa03_sr,sa13_sr,sa23_sr,sa33_sr);
assign sa00_next = sa00_mc ^ w0[31:24];
assign sa01_next = sa01_mc ^ w1[31:24];
assign sa02_next = sa02_mc ^ w2[31:24];
assign sa03_next = sa03_mc ^ w3[31:24];
assign sa10_next = sa10_mc ^ w0[23:16];
assign sa11_next = sa11_mc ^ w1[23:16];
assign sa12_next = sa12_mc ^ w2[23:16];
assign sa13_next = sa13_mc ^ w3[23:16];
assign sa20_next = sa20_mc ^ w0[15:08];
assign sa21_next = sa21_mc ^ w1[15:08];
assign sa22_next = sa22_mc ^ w2[15:08];
assign sa23_next = sa23_mc ^ w3[15:08];
assign sa30_next = sa30_mc ^ w0[07:00];
assign sa31_next = sa31_mc ^ w1[07:00];
assign sa32_next = sa32_mc ^ w2[07:00];
assign sa33_next = sa33_mc ^ w3[07:00];
////////////////////////////////////////////////////////////////////
//
// Final text output
//
always @(posedge clk) text_out[127:120] <= #1 sa00_sr ^ w0[31:24];
always @(posedge clk) text_out[095:088] <= #1 sa01_sr ^ w1[31:24];
always @(posedge clk) text_out[063:056] <= #1 sa02_sr ^ w2[31:24];
always @(posedge clk) text_out[031:024] <= #1 sa03_sr ^ w3[31:24];
always @(posedge clk) text_out[119:112] <= #1 sa10_sr ^ w0[23:16];
always @(posedge clk) text_out[087:080] <= #1 sa11_sr ^ w1[23:16];
always @(posedge clk) text_out[055:048] <= #1 sa12_sr ^ w2[23:16];
always @(posedge clk) text_out[023:016] <= #1 sa13_sr ^ w3[23:16];
always @(posedge clk) text_out[111:104] <= #1 sa20_sr ^ w0[15:08];
always @(posedge clk) text_out[079:072] <= #1 sa21_sr ^ w1[15:08];
always @(posedge clk) text_out[047:040] <= #1 sa22_sr ^ w2[15:08];
always @(posedge clk) text_out[015:008] <= #1 sa23_sr ^ w3[15:08];
always @(posedge clk) text_out[103:096] <= #1 sa30_sr ^ w0[07:00];
always @(posedge clk) text_out[071:064] <= #1 sa31_sr ^ w1[07:00];
always @(posedge clk) text_out[039:032] <= #1 sa32_sr ^ w2[07:00];
always @(posedge clk) text_out[007:000] <= #1 sa33_sr ^ w3[07:00];
////////////////////////////////////////////////////////////////////
//
// Generic Functions
//
function [31:0] mix_col;
input [7:0] s0,s1,s2,s3;
reg [7:0] s0_o,s1_o,s2_o,s3_o;
begin
mix_col[31:24]=xtime(s0)^xtime(s1)^s1^s2^s3;
mix_col[23:16]=s0^xtime(s1)^xtime(s2)^s2^s3;
mix_col[15:08]=s0^s1^xtime(s2)^xtime(s3)^s3;
mix_col[07:00]=xtime(s0)^s0^s1^s2^xtime(s3);
end
endfunction
function [7:0] xtime;
input [7:0] b; xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}});
endfunction
////////////////////////////////////////////////////////////////////
//
// Modules
//s
aes_key_expand_128 u0(
.clk( clk ),
.kld( ld ),
.key( key ),
.wo_0( w0 ),
.wo_1( w1 ),
.wo_2( w2 ),
.wo_3( w3 ));
aes_sbox us00( .a( sa00 ), .d( sa00_sub ));
aes_sbox us01( .a( sa01 ), .d( sa01_sub ));
aes_sbox us02( .a( sa02 ), .d( sa02_sub ));
aes_sbox us03( .a( sa03 ), .d( sa03_sub ));
aes_sbox us10( .a( sa10 ), .d( sa10_sub ));
aes_sbox us11( .a( sa11 ), .d( sa11_sub ));
aes_sbox us12( .a( sa12 ), .d( sa12_sub ));
aes_sbox us13( .a( sa13 ), .d( sa13_sub ));
aes_sbox us20( .a( sa20 ), .d( sa20_sub ));
aes_sbox us21( .a( sa21 ), .d( sa21_sub ));
aes_sbox us22( .a( sa22 ), .d( sa22_sub ));
aes_sbox us23( .a( sa23 ), .d( sa23_sub ));
aes_sbox us30( .a( sa30 ), .d( sa30_sub ));
aes_sbox us31( .a( sa31 ), .d( sa31_sub ));
aes_sbox us32( .a( sa32 ), .d( sa32_sub ));
aes_sbox us33( .a( sa33 ), .d( sa33_sub ));
endmodule
// The "decipher" module
module aes_inv_cipher_top(clk, rst, kld, ld, done, key, text_in, text_out );
input clk, rst;
input kld, ld;
output done;
input [127:0] key;
input [127:0] text_in;
output [127:0] text_out;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire [31:0] wk0, wk1, wk2, wk3;
reg [31:0] w0, w1, w2, w3;
reg [127:0] text_in_r;
reg [127:0] text_out;
reg [7:0] sa00, sa01, sa02, sa03;
reg [7:0] sa10, sa11, sa12, sa13;
reg [7:0] sa20, sa21, sa22, sa23;
reg [7:0] sa30, sa31, sa32, sa33;
wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next;
wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next;
wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next;
wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next;
wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub;
wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub;
wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub;
wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub;
wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr;
wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr;
wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr;
wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr;
wire [7:0] sa00_ark, sa01_ark, sa02_ark, sa03_ark;
wire [7:0] sa10_ark, sa11_ark, sa12_ark, sa13_ark;
wire [7:0] sa20_ark, sa21_ark, sa22_ark, sa23_ark;
wire [7:0] sa30_ark, sa31_ark, sa32_ark, sa33_ark;
reg ld_r, go, done;
reg [3:0] dcnt;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk)
if(!rst) dcnt <= #1 4'h0;
else
if(done) dcnt <= #1 4'h0;
else
if(ld) dcnt <= #1 4'h1;
else
if(go) dcnt <= #1 dcnt + 4'h1;
always @(posedge clk) done <= #1 (dcnt==4'hb) & !ld;
always @(posedge clk)
if(!rst) go <= #1 1'b0;
else
if(ld) go <= #1 1'b1;
else
if(done) go <= #1 1'b0;
always @(posedge clk) if(ld) text_in_r <= #1 text_in;
always @(posedge clk) ld_r <= #1 ld;
////////////////////////////////////////////////////////////////////
//
// Initial Permutation
//
always @(posedge clk) sa33 <= #1 ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_next;
always @(posedge clk) sa23 <= #1 ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_next;
always @(posedge clk) sa13 <= #1 ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_next;
always @(posedge clk) sa03 <= #1 ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_next;
always @(posedge clk) sa32 <= #1 ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_next;
always @(posedge clk) sa22 <= #1 ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_next;
always @(posedge clk) sa12 <= #1 ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_next;
always @(posedge clk) sa02 <= #1 ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_next;
always @(posedge clk) sa31 <= #1 ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_next;
always @(posedge clk) sa21 <= #1 ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_next;
always @(posedge clk) sa11 <= #1 ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_next;
always @(posedge clk) sa01 <= #1 ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_next;
always @(posedge clk) sa30 <= #1 ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_next;
always @(posedge clk) sa20 <= #1 ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_next;
always @(posedge clk) sa10 <= #1 ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_next;
always @(posedge clk) sa00 <= #1 ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_next;
////////////////////////////////////////////////////////////////////
//
// Round Permutations
//
assign sa00_sr = sa00;
assign sa01_sr = sa01;
assign sa02_sr = sa02;
assign sa03_sr = sa03;
assign sa10_sr = sa13;
assign sa11_sr = sa10;
assign sa12_sr = sa11;
assign sa13_sr = sa12;
assign sa20_sr = sa22;
assign sa21_sr = sa23;
assign sa22_sr = sa20;
assign sa23_sr = sa21;
assign sa30_sr = sa31;
assign sa31_sr = sa32;
assign sa32_sr = sa33;
assign sa33_sr = sa30;
assign sa00_ark = sa00_sub ^ w0[31:24];
assign sa01_ark = sa01_sub ^ w1[31:24];
assign sa02_ark = sa02_sub ^ w2[31:24];
assign sa03_ark = sa03_sub ^ w3[31:24];
assign sa10_ark = sa10_sub ^ w0[23:16];
assign sa11_ark = sa11_sub ^ w1[23:16];
assign sa12_ark = sa12_sub ^ w2[23:16];
assign sa13_ark = sa13_sub ^ w3[23:16];
assign sa20_ark = sa20_sub ^ w0[15:08];
assign sa21_ark = sa21_sub ^ w1[15:08];
assign sa22_ark = sa22_sub ^ w2[15:08];
assign sa23_ark = sa23_sub ^ w3[15:08];
assign sa30_ark = sa30_sub ^ w0[07:00];
assign sa31_ark = sa31_sub ^ w1[07:00];
assign sa32_ark = sa32_sub ^ w2[07:00];
assign sa33_ark = sa33_sub ^ w3[07:00];
assign {sa00_next, sa10_next, sa20_next, sa30_next} = inv_mix_col(sa00_ark,sa10_ark,sa20_ark,sa30_ark);
assign {sa01_next, sa11_next, sa21_next, sa31_next} = inv_mix_col(sa01_ark,sa11_ark,sa21_ark,sa31_ark);
assign {sa02_next, sa12_next, sa22_next, sa32_next} = inv_mix_col(sa02_ark,sa12_ark,sa22_ark,sa32_ark);
assign {sa03_next, sa13_next, sa23_next, sa33_next} = inv_mix_col(sa03_ark,sa13_ark,sa23_ark,sa33_ark);
////////////////////////////////////////////////////////////////////
//
// Final Text Output
//
always @(posedge clk) text_out[127:120] <= #1 sa00_ark;
always @(posedge clk) text_out[095:088] <= #1 sa01_ark;
always @(posedge clk) text_out[063:056] <= #1 sa02_ark;
always @(posedge clk) text_out[031:024] <= #1 sa03_ark;
always @(posedge clk) text_out[119:112] <= #1 sa10_ark;
always @(posedge clk) text_out[087:080] <= #1 sa11_ark;
always @(posedge clk) text_out[055:048] <= #1 sa12_ark;
always @(posedge clk) text_out[023:016] <= #1 sa13_ark;
always @(posedge clk) text_out[111:104] <= #1 sa20_ark;
always @(posedge clk) text_out[079:072] <= #1 sa21_ark;
always @(posedge clk) text_out[047:040] <= #1 sa22_ark;
always @(posedge clk) text_out[015:008] <= #1 sa23_ark;
always @(posedge clk) text_out[103:096] <= #1 sa30_ark;
always @(posedge clk) text_out[071:064] <= #1 sa31_ark;
always @(posedge clk) text_out[039:032] <= #1 sa32_ark;
always @(posedge clk) text_out[007:000] <= #1 sa33_ark;
////////////////////////////////////////////////////////////////////
//
// Generic Functions
//
function [31:0] inv_mix_col;
input [7:0] s0,s1,s2,s3;
begin
inv_mix_col[31:24]=pmul_e(s0)^pmul_b(s1)^pmul_d(s2)^pmul_9(s3);
inv_mix_col[23:16]=pmul_9(s0)^pmul_e(s1)^pmul_b(s2)^pmul_d(s3);
inv_mix_col[15:08]=pmul_d(s0)^pmul_9(s1)^pmul_e(s2)^pmul_b(s3);
inv_mix_col[07:00]=pmul_b(s0)^pmul_d(s1)^pmul_9(s2)^pmul_e(s3);
end
endfunction
// Some synthesis tools don't like xtime being called recursevly ...
function [7:0] pmul_e;
input [7:0] b;
reg [7:0] two,four,eight;
begin
two=xtime(b);four=xtime(two);eight=xtime(four);pmul_e=eight^four^two;
end
endfunction
function [7:0] pmul_9;
input [7:0] b;
reg [7:0] two,four,eight;
begin
two=xtime(b);four=xtime(two);eight=xtime(four);pmul_9=eight^b;
end
endfunction
function [7:0] pmul_d;
input [7:0] b;
reg [7:0] two,four,eight;
begin
two=xtime(b);four=xtime(two);eight=xtime(four);pmul_d=eight^four^b;
end
endfunction
function [7:0] pmul_b;
input [7:0] b;
reg [7:0] two,four,eight;
begin
two=xtime(b);four=xtime(two);eight=xtime(four);pmul_b=eight^two^b;
end
endfunction
function [7:0] xtime;
input [7:0] b;xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}});
endfunction
////////////////////////////////////////////////////////////////////
//
// Key Buffer
//
reg [127:0] kb[10:0];
reg [3:0] kcnt;
reg kdone;
reg kb_ld;
always @(posedge clk)
if(!rst) kcnt <= #1 4'ha;
else
if(kld) kcnt <= #1 4'ha;
else
if(kb_ld) kcnt <= #1 kcnt - 4'h1;
always @(posedge clk)
if(!rst) kb_ld <= #1 1'b0;
else
if(kld) kb_ld <= #1 1'b1;
else
if(kcnt==4'h0) kb_ld <= #1 1'b0;
always @(posedge clk) kdone <= #1 (kcnt==4'h0) & !kld;
always @(posedge clk) if(kb_ld) kb[kcnt] <= #1 {wk3, wk2, wk1, wk0};
always @(posedge clk) {w3, w2, w1, w0} <= #1 kb[dcnt];
////////////////////////////////////////////////////////////////////
//
// Modules
//
aes_key_expand_128 u0(
.clk( clk ),
.kld( kld ),
.key( key ),
.wo_0( wk0 ),
.wo_1( wk1 ),
.wo_2( wk2 ),
.wo_3( wk3 ));
aes_inv_sbox us00( .a( sa00_sr ), .d( sa00_sub ));
aes_inv_sbox us01( .a( sa01_sr ), .d( sa01_sub ));
aes_inv_sbox us02( .a( sa02_sr ), .d( sa02_sub ));
aes_inv_sbox us03( .a( sa03_sr ), .d( sa03_sub ));
aes_inv_sbox us10( .a( sa10_sr ), .d( sa10_sub ));
aes_inv_sbox us11( .a( sa11_sr ), .d( sa11_sub ));
aes_inv_sbox us12( .a( sa12_sr ), .d( sa12_sub ));
aes_inv_sbox us13( .a( sa13_sr ), .d( sa13_sub ));
aes_inv_sbox us20( .a( sa20_sr ), .d( sa20_sub ));
aes_inv_sbox us21( .a( sa21_sr ), .d( sa21_sub ));
aes_inv_sbox us22( .a( sa22_sr ), .d( sa22_sub ));
aes_inv_sbox us23( .a( sa23_sr ), .d( sa23_sub ));
aes_inv_sbox us30( .a( sa30_sr ), .d( sa30_sub ));
aes_inv_sbox us31( .a( sa31_sr ), .d( sa31_sub ));
aes_inv_sbox us32( .a( sa32_sr ), .d( sa32_sub ));
aes_inv_sbox us33( .a( sa33_sr ), .d( sa33_sub ));
endmodule
// The "SBOX" module
// ROM
module aes_sbox(a,d);
input [7:0] a;
output [7:0] d;
reg [7:0] d;
always @(a)
case(a) // synopsys full_case parallel_case
8'h00: d=8'h63;
8'h01: d=8'h7c;
8'h02: d=8'h77;
8'h03: d=8'h7b;
8'h04: d=8'hf2;
8'h05: d=8'h6b;
8'h06: d=8'h6f;
8'h07: d=8'hc5;
8'h08: d=8'h30;
8'h09: d=8'h01;
8'h0a: d=8'h67;
8'h0b: d=8'h2b;
8'h0c: d=8'hfe;
8'h0d: d=8'hd7;
8'h0e: d=8'hab;
8'h0f: d=8'h76;
8'h10: d=8'hca;
8'h11: d=8'h82;
8'h12: d=8'hc9;
8'h13: d=8'h7d;
8'h14: d=8'hfa;
8'h15: d=8'h59;
8'h16: d=8'h47;
8'h17: d=8'hf0;
8'h18: d=8'had;
8'h19: d=8'hd4;
8'h1a: d=8'ha2;
8'h1b: d=8'haf;
8'h1c: d=8'h9c;
8'h1d: d=8'ha4;
8'h1e: d=8'h72;
8'h1f: d=8'hc0;
8'h20: d=8'hb7;
8'h21: d=8'hfd;
8'h22: d=8'h93;
8'h23: d=8'h26;
8'h24: d=8'h36;
8'h25: d=8'h3f;
8'h26: d=8'hf7;
8'h27: d=8'hcc;
8'h28: d=8'h34;
8'h29: d=8'ha5;
8'h2a: d=8'he5;
8'h2b: d=8'hf1;
8'h2c: d=8'h71;
8'h2d: d=8'hd8;
8'h2e: d=8'h31;
8'h2f: d=8'h15;
8'h30: d=8'h04;
8'h31: d=8'hc7;
8'h32: d=8'h23;
8'h33: d=8'hc3;
8'h34: d=8'h18;
8'h35: d=8'h96;
8'h36: d=8'h05;
8'h37: d=8'h9a;
8'h38: d=8'h07;
8'h39: d=8'h12;
8'h3a: d=8'h80;
8'h3b: d=8'he2;
8'h3c: d=8'heb;
8'h3d: d=8'h27;
8'h3e: d=8'hb2;
8'h3f: d=8'h75;
8'h40: d=8'h09;
8'h41: d=8'h83;
8'h42: d=8'h2c;
8'h43: d=8'h1a;
8'h44: d=8'h1b;
8'h45: d=8'h6e;
8'h46: d=8'h5a;
8'h47: d=8'ha0;
8'h48: d=8'h52;
8'h49: d=8'h3b;
8'h4a: d=8'hd6;
8'h4b: d=8'hb3;
8'h4c: d=8'h29;
8'h4d: d=8'he3;
8'h4e: d=8'h2f;
8'h4f: d=8'h84;
8'h50: d=8'h53;
8'h51: d=8'hd1;
8'h52: d=8'h00;
8'h53: d=8'hed;
8'h54: d=8'h20;
8'h55: d=8'hfc;
8'h56: d=8'hb1;
8'h57: d=8'h5b;
8'h58: d=8'h6a;
8'h59: d=8'hcb;
8'h5a: d=8'hbe;
8'h5b: d=8'h39;
8'h5c: d=8'h4a;
8'h5d: d=8'h4c;
8'h5e: d=8'h58;
8'h5f: d=8'hcf;
8'h60: d=8'hd0;
8'h61: d=8'hef;
8'h62: d=8'haa;
8'h63: d=8'hfb;
8'h64: d=8'h43;
8'h65: d=8'h4d;
8'h66: d=8'h33;
8'h67: d=8'h85;
8'h68: d=8'h45;
8'h69: d=8'hf9;
8'h6a: d=8'h02;
8'h6b: d=8'h7f;
8'h6c: d=8'h50;
8'h6d: d=8'h3c;
8'h6e: d=8'h9f;
8'h6f: d=8'ha8;
8'h70: d=8'h51;
8'h71: d=8'ha3;
8'h72: d=8'h40;
8'h73: d=8'h8f;
8'h74: d=8'h92;
8'h75: d=8'h9d;
8'h76: d=8'h38;
8'h77: d=8'hf5;
8'h78: d=8'hbc;
8'h79: d=8'hb6;
8'h7a: d=8'hda;
8'h7b: d=8'h21;
8'h7c: d=8'h10;
8'h7d: d=8'hff;
8'h7e: d=8'hf3;
8'h7f: d=8'hd2;
8'h80: d=8'hcd;
8'h81: d=8'h0c;
8'h82: d=8'h13;
8'h83: d=8'hec;
8'h84: d=8'h5f;
8'h85: d=8'h97;
8'h86: d=8'h44;
8'h87: d=8'h17;
8'h88: d=8'hc4;
8'h89: d=8'ha7;
8'h8a: d=8'h7e;
8'h8b: d=8'h3d;
8'h8c: d=8'h64;
8'h8d: d=8'h5d;
8'h8e: d=8'h19;
8'h8f: d=8'h73;
8'h90: d=8'h60;
8'h91: d=8'h81;
8'h92: d=8'h4f;
8'h93: d=8'hdc;
8'h94: d=8'h22;
8'h95: d=8'h2a;
8'h96: d=8'h90;
8'h97: d=8'h88;
8'h98: d=8'h46;
8'h99: d=8'hee;
8'h9a: d=8'hb8;
8'h9b: d=8'h14;
8'h9c: d=8'hde;
8'h9d: d=8'h5e;
8'h9e: d=8'h0b;
8'h9f: d=8'hdb;
8'ha0: d=8'he0;
8'ha1: d=8'h32;
8'ha2: d=8'h3a;
8'ha3: d=8'h0a;
8'ha4: d=8'h49;
8'ha5: d=8'h06;
8'ha6: d=8'h24;
8'ha7: d=8'h5c;
8'ha8: d=8'hc2;
8'ha9: d=8'hd3;
8'haa: d=8'hac;
8'hab: d=8'h62;
8'hac: d=8'h91;
8'had: d=8'h95;
8'hae: d=8'he4;
8'haf: d=8'h79;
8'hb0: d=8'he7;
8'hb1: d=8'hc8;
8'hb2: d=8'h37;
8'hb3: d=8'h6d;
8'hb4: d=8'h8d;
8'hb5: d=8'hd5;
8'hb6: d=8'h4e;
8'hb7: d=8'ha9;
8'hb8: d=8'h6c;
8'hb9: d=8'h56;
8'hba: d=8'hf4;
8'hbb: d=8'hea;
8'hbc: d=8'h65;
8'hbd: d=8'h7a;
8'hbe: d=8'hae;
8'hbf: d=8'h08;
8'hc0: d=8'hba;
8'hc1: d=8'h78;
8'hc2: d=8'h25;
8'hc3: d=8'h2e;
8'hc4: d=8'h1c;
8'hc5: d=8'ha6;
8'hc6: d=8'hb4;
8'hc7: d=8'hc6;
8'hc8: d=8'he8;
8'hc9: d=8'hdd;
8'hca: d=8'h74;
8'hcb: d=8'h1f;
8'hcc: d=8'h4b;
8'hcd: d=8'hbd;
8'hce: d=8'h8b;
8'hcf: d=8'h8a;
8'hd0: d=8'h70;
8'hd1: d=8'h3e;
8'hd2: d=8'hb5;
8'hd3: d=8'h66;
8'hd4: d=8'h48;
8'hd5: d=8'h03;
8'hd6: d=8'hf6;
8'hd7: d=8'h0e;
8'hd8: d=8'h61;
8'hd9: d=8'h35;
8'hda: d=8'h57;
8'hdb: d=8'hb9;
8'hdc: d=8'h86;
8'hdd: d=8'hc1;
8'hde: d=8'h1d;
8'hdf: d=8'h9e;
8'he0: d=8'he1;
8'he1: d=8'hf8;
8'he2: d=8'h98;
8'he3: d=8'h11;
8'he4: d=8'h69;
8'he5: d=8'hd9;
8'he6: d=8'h8e;
8'he7: d=8'h94;
8'he8: d=8'h9b;
8'he9: d=8'h1e;
8'hea: d=8'h87;
8'heb: d=8'he9;
8'hec: d=8'hce;
8'hed: d=8'h55;
8'hee: d=8'h28;
8'hef: d=8'hdf;
8'hf0: d=8'h8c;
8'hf1: d=8'ha1;
8'hf2: d=8'h89;
8'hf3: d=8'h0d;
8'hf4: d=8'hbf;
8'hf5: d=8'he6;
8'hf6: d=8'h42;
8'hf7: d=8'h68;
8'hf8: d=8'h41;
8'hf9: d=8'h99;
8'hfa: d=8'h2d;
8'hfb: d=8'h0f;
8'hfc: d=8'hb0;
8'hfd: d=8'h54;
8'hfe: d=8'hbb;
8'hff: d=8'h16;
endcase
endmodule
// The "inv_sbox" module
// ROM
module aes_inv_sbox(a,d);
input [7:0] a;
output [7:0] d;
reg [7:0] d;
always @(a)
case(a) // synopsys full_case parallel_case
8'h00: d=8'h52;
8'h01: d=8'h09;
8'h02: d=8'h6a;
8'h03: d=8'hd5;
8'h04: d=8'h30;
8'h05: d=8'h36;
8'h06: d=8'ha5;
8'h07: d=8'h38;
8'h08: d=8'hbf;
8'h09: d=8'h40;
8'h0a: d=8'ha3;
8'h0b: d=8'h9e;
8'h0c: d=8'h81;
8'h0d: d=8'hf3;
8'h0e: d=8'hd7;
8'h0f: d=8'hfb;
8'h10: d=8'h7c;
8'h11: d=8'he3;
8'h12: d=8'h39;
8'h13: d=8'h82;
8'h14: d=8'h9b;
8'h15: d=8'h2f;
8'h16: d=8'hff;
8'h17: d=8'h87;
8'h18: d=8'h34;
8'h19: d=8'h8e;
8'h1a: d=8'h43;
8'h1b: d=8'h44;
8'h1c: d=8'hc4;
8'h1d: d=8'hde;
8'h1e: d=8'he9;
8'h1f: d=8'hcb;
8'h20: d=8'h54;
8'h21: d=8'h7b;
8'h22: d=8'h94;
8'h23: d=8'h32;
8'h24: d=8'ha6;
8'h25: d=8'hc2;
8'h26: d=8'h23;
8'h27: d=8'h3d;
8'h28: d=8'hee;
8'h29: d=8'h4c;
8'h2a: d=8'h95;
8'h2b: d=8'h0b;
8'h2c: d=8'h42;
8'h2d: d=8'hfa;
8'h2e: d=8'hc3;
8'h2f: d=8'h4e;
8'h30: d=8'h08;
8'h31: d=8'h2e;
8'h32: d=8'ha1;
8'h33: d=8'h66;
8'h34: d=8'h28;
8'h35: d=8'hd9;
8'h36: d=8'h24;
8'h37: d=8'hb2;
8'h38: d=8'h76;
8'h39: d=8'h5b;
8'h3a: d=8'ha2;
8'h3b: d=8'h49;
8'h3c: d=8'h6d;
8'h3d: d=8'h8b;
8'h3e: d=8'hd1;
8'h3f: d=8'h25;
8'h40: d=8'h72;
8'h41: d=8'hf8;
8'h42: d=8'hf6;
8'h43: d=8'h64;
8'h44: d=8'h86;
8'h45: d=8'h68;
8'h46: d=8'h98;
8'h47: d=8'h16;
8'h48: d=8'hd4;
8'h49: d=8'ha4;
8'h4a: d=8'h5c;
8'h4b: d=8'hcc;
8'h4c: d=8'h5d;
8'h4d: d=8'h65;
8'h4e: d=8'hb6;
8'h4f: d=8'h92;
8'h50: d=8'h6c;
8'h51: d=8'h70;
8'h52: d=8'h48;
8'h53: d=8'h50;
8'h54: d=8'hfd;
8'h55: d=8'hed;
8'h56: d=8'hb9;
8'h57: d=8'hda;
8'h58: d=8'h5e;
8'h59: d=8'h15;
8'h5a: d=8'h46;
8'h5b: d=8'h57;
8'h5c: d=8'ha7;
8'h5d: d=8'h8d;
8'h5e: d=8'h9d;
8'h5f: d=8'h84;
8'h60: d=8'h90;
8'h61: d=8'hd8;
8'h62: d=8'hab;
8'h63: d=8'h00;
8'h64: d=8'h8c;
8'h65: d=8'hbc;
8'h66: d=8'hd3;
8'h67: d=8'h0a;
8'h68: d=8'hf7;
8'h69: d=8'he4;
8'h6a: d=8'h58;
8'h6b: d=8'h05;
8'h6c: d=8'hb8;
8'h6d: d=8'hb3;
8'h6e: d=8'h45;
8'h6f: d=8'h06;
8'h70: d=8'hd0;
8'h71: d=8'h2c;
8'h72: d=8'h1e;
8'h73: d=8'h8f;
8'h74: d=8'hca;
8'h75: d=8'h3f;
8'h76: d=8'h0f;
8'h77: d=8'h02;
8'h78: d=8'hc1;
8'h79: d=8'haf;
8'h7a: d=8'hbd;
8'h7b: d=8'h03;
8'h7c: d=8'h01;
8'h7d: d=8'h13;
8'h7e: d=8'h8a;
8'h7f: d=8'h6b;
8'h80: d=8'h3a;
8'h81: d=8'h91;
8'h82: d=8'h11;
8'h83: d=8'h41;
8'h84: d=8'h4f;
8'h85: d=8'h67;
8'h86: d=8'hdc;
8'h87: d=8'hea;
8'h88: d=8'h97;
8'h89: d=8'hf2;
8'h8a: d=8'hcf;
8'h8b: d=8'hce;
8'h8c: d=8'hf0;
8'h8d: d=8'hb4;
8'h8e: d=8'he6;
8'h8f: d=8'h73;
8'h90: d=8'h96;
8'h91: d=8'hac;
8'h92: d=8'h74;
8'h93: d=8'h22;
8'h94: d=8'he7;
8'h95: d=8'had;
8'h96: d=8'h35;
8'h97: d=8'h85;
8'h98: d=8'he2;
8'h99: d=8'hf9;
8'h9a: d=8'h37;
8'h9b: d=8'he8;
8'h9c: d=8'h1c;
8'h9d: d=8'h75;
8'h9e: d=8'hdf;
8'h9f: d=8'h6e;
8'ha0: d=8'h47;
8'ha1: d=8'hf1;
8'ha2: d=8'h1a;
8'ha3: d=8'h71;
8'ha4: d=8'h1d;
8'ha5: d=8'h29;
8'ha6: d=8'hc5;
8'ha7: d=8'h89;
8'ha8: d=8'h6f;
8'ha9: d=8'hb7;
8'haa: d=8'h62;
8'hab: d=8'h0e;
8'hac: d=8'haa;
8'had: d=8'h18;
8'hae: d=8'hbe;
8'haf: d=8'h1b;
8'hb0: d=8'hfc;
8'hb1: d=8'h56;
8'hb2: d=8'h3e;
8'hb3: d=8'h4b;
8'hb4: d=8'hc6;
8'hb5: d=8'hd2;
8'hb6: d=8'h79;
8'hb7: d=8'h20;
8'hb8: d=8'h9a;
8'hb9: d=8'hdb;
8'hba: d=8'hc0;
8'hbb: d=8'hfe;
8'hbc: d=8'h78;
8'hbd: d=8'hcd;
8'hbe: d=8'h5a;
8'hbf: d=8'hf4;
8'hc0: d=8'h1f;
8'hc1: d=8'hdd;
8'hc2: d=8'ha8;
8'hc3: d=8'h33;
8'hc4: d=8'h88;
8'hc5: d=8'h07;
8'hc6: d=8'hc7;
8'hc7: d=8'h31;
8'hc8: d=8'hb1;
8'hc9: d=8'h12;
8'hca: d=8'h10;
8'hcb: d=8'h59;
8'hcc: d=8'h27;
8'hcd: d=8'h80;
8'hce: d=8'hec;
8'hcf: d=8'h5f;
8'hd0: d=8'h60;
8'hd1: d=8'h51;
8'hd2: d=8'h7f;
8'hd3: d=8'ha9;
8'hd4: d=8'h19;
8'hd5: d=8'hb5;
8'hd6: d=8'h4a;
8'hd7: d=8'h0d;
8'hd8: d=8'h2d;
8'hd9: d=8'he5;
8'hda: d=8'h7a;
8'hdb: d=8'h9f;
8'hdc: d=8'h93;
8'hdd: d=8'hc9;
8'hde: d=8'h9c;
8'hdf: d=8'hef;
8'he0: d=8'ha0;
8'he1: d=8'he0;
8'he2: d=8'h3b;
8'he3: d=8'h4d;
8'he4: d=8'hae;
8'he5: d=8'h2a;
8'he6: d=8'hf5;
8'he7: d=8'hb0;
8'he8: d=8'hc8;
8'he9: d=8'heb;
8'hea: d=8'hbb;
8'heb: d=8'h3c;
8'hec: d=8'h83;
8'hed: d=8'h53;
8'hee: d=8'h99;
8'hef: d=8'h61;
8'hf0: d=8'h17;
8'hf1: d=8'h2b;
8'hf2: d=8'h04;
8'hf3: d=8'h7e;
8'hf4: d=8'hba;
8'hf5: d=8'h77;
8'hf6: d=8'hd6;
8'hf7: d=8'h26;
8'hf8: d=8'he1;
8'hf9: d=8'h69;
8'hfa: d=8'h14;
8'hfb: d=8'h63;
8'hfc: d=8'h55;
8'hfd: d=8'h21;
8'hfe: d=8'h0c;
8'hff: d=8'h7d;
endcase
endmodule
// The "rcon" module
module aes_rcon(clk, kld, out);
input clk;
input kld;
output [31:0] out;
reg [31:0] out;
reg [3:0] rcnt;
wire [3:0] rcnt_next;
always @(posedge clk)
if(kld) out <= #1 32'h01_00_00_00;
else out <= #1 frcon(rcnt_next);
assign rcnt_next = rcnt + 4'h1;
always @(posedge clk)
if(kld) rcnt <= #1 4'h0;
else rcnt <= #1 rcnt_next;
function [31:0] frcon;
input [3:0] i;
case(i) // synopsys parallel_case
4'h0: frcon=32'h01_00_00_00;
4'h1: frcon=32'h02_00_00_00;
4'h2: frcon=32'h04_00_00_00;
4'h3: frcon=32'h08_00_00_00;
4'h4: frcon=32'h10_00_00_00;
4'h5: frcon=32'h20_00_00_00;
4'h6: frcon=32'h40_00_00_00;
4'h7: frcon=32'h80_00_00_00;
4'h8: frcon=32'h1b_00_00_00;
4'h9: frcon=32'h36_00_00_00;
default: frcon=32'h00_00_00_00;
endcase
endfunction
endmodule
// The "key_expand" module
module aes_key_expand_128(clk, kld, key, wo_0, wo_1, wo_2, wo_3);
input clk;
input kld;
input [127:0] key;
output [31:0] wo_0, wo_1, wo_2, wo_3;
reg [31:0] w[3:0];
wire [31:0] tmp_w;
wire [31:0] subword;
wire [31:0] rcon;
assign wo_0 = w[0];
assign wo_1 = w[1];
assign wo_2 = w[2];
assign wo_3 = w[3];
always @(posedge clk) w[0] <= #1 kld ? key[127:096] : w[0]^subword^rcon;
always @(posedge clk) w[1] <= #1 kld ? key[095:064] : w[0]^w[1]^subword^rcon;
always @(posedge clk) w[2] <= #1 kld ? key[063:032] : w[0]^w[2]^w[1]^subword^rcon;
always @(posedge clk) w[3] <= #1 kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^rcon;
assign tmp_w = w[3];
aes_sbox u0( .a(tmp_w[23:16]), .d(subword[31:24]));
aes_sbox u1( .a(tmp_w[15:08]), .d(subword[23:16]));
aes_sbox u2( .a(tmp_w[07:00]), .d(subword[15:08]));
aes_sbox u3( .a(tmp_w[31:24]), .d(subword[07:00]));
aes_rcon r0( .clk(clk), .kld(kld), .out(rcon));
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Store buffer
// FUNCTION: FIFO - buffer with direct input order and 8-th inverse output order
// FILES: BUFRAM128C_2.v - 1-st,2-nd,3-d data buffer, contains:
// RAM2x128C.v - dual ported synchronous RAM, contains:
// RAM128.v -single ported synchronous RAM
// PROPERTIES: 1) Has the volume of 2x128 complex data
// 2) Contains 2- port RAM and address counter
// 3)Has 128-clock cycle period starting with the START impulse
// and continuing forever
// 4) Signal RDY precedes the 1-st correct datum outputted from the buffer
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`timescale 1 ns / 1 ps
`include "FFT128_CONFIG.inc"
module BUFRAM128C ( CLK ,RST ,ED ,START ,DR ,DI ,RDY ,DOR ,DOI );
`FFT128paramnb
output RDY ;
reg RDY ;
output [nb-1:0] DOR ;
wire [nb-1:0] DOR ;
output [nb-1:0] DOI ;
wire [nb-1:0] DOI ;
input CLK ;
wire CLK ;
input RST ;
wire RST ;
input ED ;
wire ED ;
input START ;
wire START ;
input [nb-1:0] DR ;
wire [nb-1:0] DR ;
input [nb-1:0] DI ;
wire [nb-1:0] DI ;
wire odd, we;
wire [6:0] addrw,addrr;
reg [7:0] addr;
reg [8:0] ct2; //counter for the RDY signal
always @(posedge CLK) // CTADDR
begin
if (RST) begin
addr<=7'b000_0000;
ct2<= 8'b1000_0001;
RDY<=1'b0; end
else if (START) begin
addr<=7'b000_0000;
ct2<= 8'b0000_0000;
RDY<=1'b0;end
else if (ED) begin
RDY<=1'b0;
addr<=addr+1;
if (ct2!=129)
ct2<=ct2+1;
if (ct2==128)
RDY<=1'b1;
end
end
assign addrw= addr[6:0];
assign odd=addr[7]; // signal which switches the 2 parts of the buffer
assign addrr={addr[3 : 0], addr[6 : 4]}; // 8-th inverse output address
assign we = ED;
RAM2x128C #(nb) URAM(.CLK(CLK),.ED(ED),.WE(we),.ODD(odd),
.ADDRW(addrw), .ADDRR(addrr),
.DR(DR),.DI(DI),
.DOR(DOR), .DOI(DOI));
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Store buffer
// FUNCTION: FIFO - buffer with direct input order and 8-th inverse output order
// FILES: BUFRAM128C_1.v - 1-st,2-nd,3-d data buffer, contains:
// RAM2x128C.v - dual ported synchronous RAM, contains:
// RAM128.v -single ported synchronous RAM
// PROPERTIES: 1) Has the volume of 2x128 complex data
// 2) Contains 2- port RAM and address counter
// 3)Has 128-clock cycle period starting with the START impulse
// and continuing forever
// 4) Signal RDY precedes the 1-st correct datum outputted from the buffer
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`timescale 1 ns / 1 ps
`include "FFT128_CONFIG.inc"
module BUFRAM128C_1 ( CLK ,RST ,ED ,START ,DR ,DI ,RDY ,DOR ,DOI );
`FFT128paramnb
output RDY ;
reg RDY ;
output [nb-1:0] DOR ;
wire [nb-1:0] DOR ;
output [nb-1:0] DOI ;
wire [nb-1:0] DOI ;
input CLK ;
wire CLK ;
input RST ;
wire RST ;
input ED ;
wire ED ;
input START ;
wire START ;
input [nb-1:0] DR ;
wire [nb-1:0] DR ;
input [nb-1:0] DI ;
wire [nb-1:0] DI ;
wire odd, we;
wire [6:0] addrw,addrr;
reg [7:0] addr;
reg [8:0] ct2; //counter for the RDY signal
always @(posedge CLK) // CTADDR
begin
if (RST) begin
addr<=7'b000_0000;
ct2<= 8'b1000_0001;
RDY<=1'b0; end
else if (START) begin
addr<=7'b000_0000;
ct2<= 8'b0000_0000;
RDY<=1'b0;end
else if (ED) begin
RDY<=1'b0;
addr<=addr+1;
if (ct2!=129)
ct2<=ct2+1;
if (ct2==128)
RDY<=1'b1;
end
end
assign addrw= addr[6:0];
assign odd=addr[7]; // signal which switches the 2 parts of the buffer
assign addrr={addr[2 : 0], addr[6 : 3]}; // 16-th inverse output address
assign we = ED;
RAM2x128C #(nb) URAM(.CLK(CLK),.ED(ED),.WE(we),.ODD(odd),
.ADDRW(addrw), .ADDRR(addrr),
.DR(DR),.DI(DI),
.DOR(DOR), .DOI(DOI));
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Store buffer
// FUNCTION: FIFO - buffer with direct input order and 8-th inverse output order
// FILES: BUFRAM128C_2.v - 1-st,2-nd,3-d data buffer, contains:
// RAM2x128C.v - dual ported synchronous RAM, contains:
// RAM128.v -single ported synchronous RAM
// PROPERTIES: 1) Has the volume of 2x128 complex data
// 2) Contains 2- port RAM and address counter
// 3)Has 128-clock cycle period starting with the START impulse
// and continuing forever
// 4) Signal RDY precedes the 1-st correct datum outputted from the buffer
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`timescale 1 ns / 1 ps
`include "FFT128_CONFIG.inc"
module BUFRAM128C_2 ( CLK ,RST ,ED ,START ,DR ,DI ,RDY ,DOR ,DOI );
`FFT128paramnb
output RDY ;
reg RDY ;
output [nb-1:0] DOR ;
wire [nb-1:0] DOR ;
output [nb-1:0] DOI ;
wire [nb-1:0] DOI ;
input CLK ;
wire CLK ;
input RST ;
wire RST ;
input ED ;
wire ED ;
input START ;
wire START ;
input [nb-1:0] DR ;
wire [nb-1:0] DR ;
input [nb-1:0] DI ;
wire [nb-1:0] DI ;
wire odd, we;
wire [6:0] addrw,addrr;
reg [7:0] addr;
reg [8:0] ct2; //counter for the RDY signal
always @(posedge CLK) // CTADDR
begin
if (RST) begin
addr<=7'b000_0000;
ct2<= 8'b1000_0001;
RDY<=1'b0; end
else if (START) begin
addr<=7'b000_0000;
ct2<= 8'b0000_0000;
RDY<=1'b0;end
else if (ED) begin
RDY<=1'b0;
addr<=addr+1;
if (ct2!=129)
ct2<=ct2+1;
if (ct2==128)
RDY<=1'b1;
end
end
assign addrw= addr[6:0];
assign odd=addr[7]; // signal which switches the 2 parts of the buffer
assign addrr={addr[3 : 0], addr[6 : 4]}; // 8-th inverse output address
assign we = ED;
RAM2x128C #(nb) URAM(.CLK(CLK),.ED(ED),.WE(we),.ODD(odd),
.ADDRW(addrw), .ADDRR(addrr),
.DR(DR),.DI(DI),
.DOR(DOR), .DOI(DOI));
endmodule
|
/*************************************************************************
* FILE: clkgen.v
* Written By: Michael J. Kelley
* Written On: March 4, 1996
* Updated By: Michael J. Kelley
* Updated On: March 4, 1996
*
* Description:
*
* This modules is used to generate a one-phase clock to be used with
* the system.v module. This clock governs the timing on the entire
* DLX processor.
*************************************************************************
*/
`timescale 1ns/1ps
`include "./dlx.defines"
module clkgen (
clk
);
output clk;
reg clk;
initial
begin
clk = 0;
end
always
begin
#(`ClockPeriod / 2) clk = 1;
#(`ClockPeriod / 2) clk = 0;
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Normalization unit
// FUNCTION: shifting left up to 3 bits
// FILES: CNORM.v
// PROPERTIES: 1) shifting left up to 3 bits controlled by the 2-bit code SHIFT
// 2) Is registered
// 3) Overflow detector detects the overflow event
// by the given shift condition. The detector is zeroed by the START signal
// 4) RDY is the START signal delayed to a single clock cycle
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// File :
// Generated :
//
// Description :
//
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`include "FFT128_CONFIG.inc"
module CNORM ( CLK ,ED ,START ,DR ,DI ,SHIFT ,OVF ,RDY ,DOR ,DOI );
`FFT128paramnb
output OVF ;
reg OVF ;
output RDY ;
reg RDY ;
output [nb+1:0] DOR ;
wire [nb+1:0] DOR ;
output [nb+1:0] DOI ;
wire [nb+1:0] DOI ;
input CLK ;
wire CLK ;
input ED ;
wire ED ;
input START ;
wire START ;
input [nb+2:0] DR ;
wire [nb+2:0] DR ;
input [nb+2:0] DI ;
wire [nb+2:0] DI ;
input [1:0] SHIFT ; //shift left code to 0,1,2,3 bits
wire [1:0] SHIFT ;
wire signed [nb+3:0] diri,diii;
assign diri = DR << SHIFT;
assign diii = DI << SHIFT;
reg [nb+2:0] dir,dii;
`ifdef FFT128round //rounding
always @( posedge CLK ) begin
if (ED) begin
if (diri[nb+2] && ~diri[0]) // <0 with LSB=00
dir<=diri;
else dir<=diri+2;
if (diii[nb+2] && ~diii[0])
dii<=diii;
else dii<=diii+2;
end
end
`else //truncation
always @( posedge CLK ) begin
if (ED) begin
dir<=diri;
dii<=diii;
end
end
`endif
always @( posedge CLK ) begin
if (ED) begin
RDY<=START;
if (START)
OVF<=0;
else
case (SHIFT)
2'b01 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2]);
2'b10 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2]) ||
(DR[nb+3] != DR[nb+1]) || (DI[nb+3] != DI[nb+1]);
2'b11 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2])||
(DR[nb+3] != DR[nb]) || (DI[nb+3] != DI[nb]) ||
(DR[nb+3] != DR[nb+1]) || (DI[nb+3] != DI[nb+1]);
endcase
end
end
assign DOR= dir[nb+3:2];
assign DOI= dii[nb+3:2];
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Normalization unit
// FUNCTION: shifting left up to 3 bits
// FILES: CNORM.v
// PROPERTIES: 1) shifting left up to 3 bits controlled by the 2-bit code SHIFT
// 2) Is registered
// 3) Overflow detector detects the overflow event
// by the given shift condition. The detector is zeroed by the START signal
// 4) RDY is the START signal delayed to a single clock cycle
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// File :
// Generated :
//
// Description :
//
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`include "FFT128_CONFIG.inc"
module CNORM_1 ( CLK ,ED ,START ,DR ,DI ,SHIFT ,OVF ,RDY ,DOR ,DOI );
`FFT128paramnb
output OVF ;
reg OVF ;
output RDY ;
reg RDY ;
output [nb+1:0] DOR ;
wire [nb+1:0] DOR ;
output [nb+1:0] DOI ;
wire [nb+1:0] DOI ;
input CLK ;
wire CLK ;
input ED ;
wire ED ;
input START ;
wire START ;
input [nb+2:0] DR ;
wire [nb+2:0] DR ;
input [nb+2:0] DI ;
wire [nb+2:0] DI ;
input [1:0] SHIFT ; //shift left code to 0,1,2,3 bits
wire [1:0] SHIFT ;
wire signed [nb+2:0] diri,diii;
assign diri = DR << SHIFT;
assign diii = DI << SHIFT;
reg [nb+2:0] dir,dii;
`ifdef FFT128round //rounding
always @( posedge CLK ) begin
if (ED) begin
if (diri[nb+2] && ~diri[0]) // <0 with LSB=00
dir<=diri;
else dir<=diri+2;
if (diii[nb+2] && ~diii[0])
dii<=diii;
else dii<=diii+2;
end
end
`else //truncation
always @( posedge CLK ) begin
if (ED) begin
dir<=diri;
dii<=diii;
end
end
`endif
always @( posedge CLK ) begin
if (ED) begin
RDY<=START;
if (START)
OVF<=0;
else
case (SHIFT)
2'b01 : OVF<= (DR[nb+2] != DR[nb+1]) || (DI[nb+2] != DI[nb+1]);
2'b10 : OVF<= (DR[nb+2] != DR[nb+1]) || (DI[nb+2] != DI[nb+1]) ||
(DR[nb+2] != DR[nb]) || (DI[nb+2] != DI[nb]);
2'b11 : OVF<= (DR[nb+2] != DR[nb+1]) || (DI[nb+2] != DI[nb+1])||
(DR[nb+2] != DR[nb]) || (DI[nb+2] != DI[nb]) ||
(DR[nb+2] != DR[nb-1]) || (DI[nb+2] != DI[nb-1]);
endcase
end
end
assign DOR= dir[nb+2:1];
assign DOI= dii[nb+2:1];
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Normalization unit
// FUNCTION: shifting left up to 3 bits
// FILES: CNORM.v
// PROPERTIES: 1) shifting left up to 3 bits controlled by the 2-bit code SHIFT
// 2) Is registered
// 3) Overflow detector detects the overflow event
// by the given shift condition. The detector is zeroed by the START signal
// 4) RDY is the START signal delayed to a single clock cycle
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// File :
// Generated :
//
// Description :
//
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`include "FFT128_CONFIG.inc"
module CNORM_2 ( CLK ,ED ,START ,DR ,DI ,SHIFT ,OVF ,RDY ,DOR ,DOI );
`FFT128paramnb
output OVF ;
reg OVF ;
output RDY ;
reg RDY ;
output [nb+1:0] DOR ;
wire [nb+1:0] DOR ;
output [nb+1:0] DOI ;
wire [nb+1:0] DOI ;
input CLK ;
wire CLK ;
input ED ;
wire ED ;
input START ;
wire START ;
input [nb+3:0] DR ;
wire [nb+3:0] DR ;
input [nb+3:0] DI ;
wire [nb+3:0] DI ;
input [1:0] SHIFT ; //shift left code to 0,1,2,3 bits
wire [1:0] SHIFT ;
wire signed [nb+3:0] diri,diii;
assign diri = DR << SHIFT;
assign diii = DI << SHIFT;
reg [nb+3:0] dir,dii;
`ifdef FFT128round //rounding
always @( posedge CLK ) begin
if (ED) begin
if (diri[nb+3] && ~diri[0]) // <0 with LSB=00
dir<=diri;
else dir<=diri+2;
if (diii[nb+3] && ~diii[0])
dii<=diii;
else dii<=diii+2;
end
end
`else //truncation
always @( posedge CLK ) begin
if (ED) begin
dir<=diri;
dii<=diii;
end
end
`endif
always @( posedge CLK ) begin
if (ED) begin
RDY<=START;
if (START)
OVF<=0;
else
case (SHIFT)
2'b01 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2]);
2'b10 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2]) ||
(DR[nb+3] != DR[nb+1]) || (DI[nb+3] != DI[nb+1]);
2'b11 : OVF<= (DR[nb+3] != DR[nb+2]) || (DI[nb+3] != DI[nb+2])||
(DR[nb+3] != DR[nb]) || (DI[nb+3] != DI[nb]) ||
(DR[nb+3] != DR[nb+1]) || (DI[nb+3] != DI[nb+1]);
endcase
end
end
assign DOR= dir[nb+3:2];
assign DOI= dii[nb+3:2];
endmodule
|
`include "./dlx.defines"
`timescale 1ns/1ps
module DAP (clk, MRST, s1,s2, DB1, DB2, DCP, SEL);
input clk;
input MRST;
input [31:0] DB1, DB2;
input s1, s2;
output reg[31:0] DCP;
output reg[1:0] SEL;
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
DCP <= 32'b0;
SEL <= 2'b00;
end
else if ((s2 == 1'b1) && (s1 == 1'b0))
begin
DCP <= DB2;
SEL <= 2'b10;
end
else if ((s1 == 1'b1) && (s2 == 1'b1))
begin
DCP <= DB1;
SEL <= 2'b11;
end
end
endmodule
|
`include "./dlx.defines"
`timescale 1ns/1ps
// assuming external read and write through memory as well (here just external) highlighted by E
// DInE won't be inserted into test boundary chain
// DOUT and DIN are reverse with respect to that of Dcache
module Dcache (DOutE1, DOutE2, DOutE3, DOutE4, DOutE5, DOut, DAddrE1, DAddrE2, DAddrE3, DAddrE4, DAddrE5, DAddrE, DAddr, DReadE, DRead, DWriteE1, DWriteE2, DWriteE3, DWriteE4, DWriteE5, DWrite, DInE, DIn, DWRR, DARR, DORR, DIS1, DIS2, DIS3, DIS4, REQ1, REQ2, REQ3, REQ4, state);
parameter N = 32;
parameter WORDS = 128; //Suppose first 48 for SC, and16 words/IP
input [`WordSize] DOut, DAddr, DOutE1, DAddrE1, DOutE2, DAddrE2, DOutE3, DAddrE3, DOutE4, DAddrE4, DOutE5, DAddrE5, DARR, DORR;
input DRead, DReadE;
input DWrite, DWriteE1, DWriteE2, DWriteE3, DWriteE4, DWriteE5, DWRR ;
output reg[`WordSize] DIn;
output DIS1, DIS2, DIS3, DIS4, REQ1, REQ2, REQ3, REQ4;
output [3:0] state;
input [`WordSize] DAddrE;
//input DReadE, DWriteE;
output reg[`WordSize] DInE;
reg [(N - 1):0] mem_array[(WORDS - 1):0];
wire [31:0] outvector;
// basically next the functioning of the memory controller for // single ported memory
always @(*)
begin
// by the Secuirty policy controller
if ((DRead == `LogicZero)&& (DWrite == `LogicOne))
begin
mem_array[DAddr] = DOut;
end
else if ((DRead == `LogicOne)&& (DWrite == `LogicZero))
begin
DIn = mem_array[DAddr];
end
else if ((DReadE == `LogicOne)) // just kept for external access
begin
DInE = mem_array[DAddrE];
end
end
always @(*)
begin
// address segmentation is present via inputs
if ((DWriteE1 == `LogicOne))
begin
mem_array[DAddrE1] = DOutE1;
end
if ((DWriteE2 == `LogicOne))
begin
mem_array[DAddrE2] = DOutE2;
end
if ((DWriteE3 == `LogicOne))
begin
mem_array[DAddrE3] = DOutE3;
end
if ((DWriteE4 == `LogicOne))
begin
mem_array[DAddrE4] = DOutE4;
end
if ((DWriteE5 == `LogicOne))
begin
mem_array[DAddrE5] = DOutE5;
end
if ((DWRR == 1'b1)) // for the write of the F values of the buffer
begin
mem_array[DARR] = DORR;
end
end
// the DIS and REQ outputs
assign outvector = mem_array[32'd20];
assign DIS1 = outvector[15];
assign DIS2 = outvector[14];
assign DIS3 = outvector[13];
assign DIS4 = outvector[12];
assign REQ1 = outvector[11];
assign REQ2 = outvector[10];
assign REQ3 = outvector[9];
assign REQ4 = outvector[8];
assign state = outvector[3:0];
endmodule
|
`include "./dlx.defines"
`timescale 1ns/1ps
// assuming external read and write through memory as well (here just external) highlighted by E
// DInE won't be inserted into test boundary chain
// DOUT and DIN are reverse with respect to that of Dcache
module SystemMem (DOutE1, DOutE2, DOutE3, DOut, DAddrE1, DAddrE2, DAddrE3, DAddr, DReadE1, DReadE2, DReadE3, DRead, DWriteE1, DWriteE2, DWriteE3, DWrite, DInE1, DInE2, DInE3, DIn);
parameter N = 32;
parameter WORDS = 128;
input [`WordSize] DOut, DAddr;
input DRead, DWrite;
output reg[`WordSize] DIn;
input [`WordSize] DOutE1, DAddrE1, DOutE2, DAddrE2, DOutE3, DAddrE3;
input DReadE1, DWriteE1, DReadE2, DWriteE2, DReadE3, DWriteE3 ;
output reg[`WordSize] DInE1, DInE2, DInE3;
reg [(N - 1):0] mem_array[(WORDS - 1):0];
// prioirity of processor first, then AES and then FFT..(if simultaneous) and Read over Write
// ACTUALLY SINGLE PORTED
always @(*)
begin
// Read Operation
// For a particular IP, both cannot read and write
if ((DRead == `LogicOne)&& (DWrite == `LogicZero))
begin
DIn = mem_array[DAddr];
end
else if ((DReadE1 == `LogicOne)&& (DWriteE1 == `LogicZero))
begin
DInE1 = mem_array[DAddrE1];
end
else if ((DReadE2 == `LogicOne)&& (DWriteE2 == `LogicZero))
begin
DInE2 = mem_array[DAddrE2];
end
else if ((DReadE3 == `LogicOne)&& (DWriteE3 == `LogicZero))
begin
DInE3 = mem_array[DAddrE3];
end
end
always @(*)
begin
if ((DRead == `LogicZero)&& (DWrite == `LogicOne))
begin
mem_array[DAddr] = DOut;
end
else if ((DReadE1 == `LogicZero)&& (DWriteE1 == `LogicOne))
begin
mem_array[DAddrE1] = DOutE1;
end
else if ((DReadE2 == `LogicZero)&& (DWriteE2 == `LogicOne))
begin
mem_array[DAddrE2] = DOutE2;
end
else if ((DReadE3 == `LogicZero)&& (DWriteE3 == `LogicOne))
begin
mem_array[DAddrE3] = DOutE3;
end
end
endmodule
|
`timescale 1ns/1ps
module debug_AES(clk, MRST, mode, ld, pause, done, key, t_in, t_out, DCP, Sel, EV, Val, TP, TPE, w01, w02, w03, w04);
input clk, MRST, mode, ld, done, pause;
input [127:0] key, t_in, t_out;
input [31:0] DCP;
input [1:0] Sel;
input [31:0] w01, w02, w03, w04;
output reg [31:0] Val, TP;
output reg TPE;
output reg [7:0] EV;
reg [7:0] CFGNO;
reg tag;
reg [1:0] sel1;
reg [31:0] CFR[0:7];
always @ (posedge clk)
begin
if (MRST == 1'b0)
begin
CFGNO <= 8'd255;
tag <= 1'b0;
sel1 <= 2'b0;
end
else if (DCP[31] == 1'b1)
begin
CFGNO <= DCP[7:0];
tag <= 1'b1;
sel1 <= Sel;
end
else
begin
tag <= 1'b0;
end
end
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
CFR[0] <= 0;
CFR[1] <= 0;
CFR[2] <= 0;
CFR[3] <= 0;
CFR[4] <= 0;
CFR[5] <= 0;
CFR[6] <= 0;
CFR[7] <= 0;
end
else if ((tag == 1'b1) && (CFGNO >= 8'd32) && (CFGNO <= 8'd47))
begin
CFR[CFGNO - 8'd32] <= DCP;
end
end
// info to the wrapper
reg [7:0] ev1;
reg [1:0] cucu;
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
EV <= 8'b0;
cucu <= 'd0;
Val <= 'd0;
end
else if ((CFR[0] > 32'd0)) // no datatigg
begin
if (sel1 == 2'b11) // SPI requiring access
begin
EV <= ev1;
if ((ev1 > 'd0) || ((cucu > 'd0)))
begin
cucu <= cucu + 2'd1;
if (cucu == 2'd0)
Val <= t_out[31:0];
else if (cucu == 2'd1)
Val <= t_out[63:32];
else if (cucu == 2'd2)
Val <= t_out[95:64];
else
Val <= t_out[127:96];
end
end
end
else
begin
EV <= 8'd0;
cucu <= 'd0;
Val <= 'd0;
end
end
reg ld1;
reg done1;
always @(posedge clk)
begin
ld1 <= ld;
done1 <= done;
end
reg [31:0] perfcoun;
reg active;
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
perfcoun <= 32'd0;
active <= 1'b0;
end
else if (((ld1 == 1'b0) && (ld == 1'b1)) || ((active == 1'b1) && (done == 1'b0)))
begin
perfcoun <= perfcoun + 32'b1;
active <= 1'b1;
end
else if ((done1 == 1'b0) && (done == 1'b1))
begin
active <= 1'b0;
end
else
begin
perfcoun <= 32'd0;
end
end
reg pause1;
always @(posedge clk)
begin
pause1 <= pause;
end
reg [31:0] pauscoun;
reg activa;
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
pauscoun <= 32'd0;
activa <= 1'b0;
end
else if (((pause1 == 1'b1) && (pause == 1'b0)) || ((activa == 1'b1) && (pause == 1'b0) && (active == 1'b1)))
begin
pauscoun <= pauscoun + 32'b1;
activa <= 1'b1;
end
else if ((pause1 == 1'b0) && (pause == 1'b1))
begin
activa <= 1'b0;
end
else
begin
pauscoun <= 32'd0;
end
end
always @(*)
begin
casex({CFR[0][31:8], CFR[0][7:0]})
{24'bx, 8'b00000001}:
begin
if (done == 1'b1)
begin
ev1 = 8'd1;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000010}:
begin
if ((ld1 == 1'b0) && (ld == 1'b1) && (mode == 1'b1)) // key
begin
ev1 = 8'd2;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000011}:
begin
if ((ld1 == 1'b0) && (ld == 1'b1) && (mode == 1'b0)) // key
begin
ev1 = 8'd3;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000100}:
begin
if ((ld1 == 1'b0) && (ld == 1'b1)) // text_in
begin
ev1 = 8'd4;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000101}:
begin
if (done == 1'b1) // text_out
begin
ev1 = 8'd5;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000110}:
begin
if ((active == 1'b1) && (pause1 == 1'b1) && (pause == 1'b0)) // pause
begin
ev1 = 8'd6;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000111}:
begin
if ((active == 1'b1) && (pause1 == 1'b0) && (pause == 1'b1)) // pause
begin
ev1 = 8'd7;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00001000}:
begin
if ((active == 1'b1) && ((perfcoun - pauscoun) == CFR[1])) // text_out
begin
ev1 = 8'd8;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00001001}:
begin
if ((active == 1'b1) && ((perfcoun - pauscoun) == CFR[1])) // key
begin
ev1 = 8'd9;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00001010}:
begin
if ((active == 1'b1) && ((perfcoun - pauscoun) == CFR[1])) // key
begin
ev1 = 8'd10;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00001011}:
begin
if ((active == 1'b1) && ((perfcoun - pauscoun) == CFR[1])) // key
begin
ev1 = 8'd11;
end
else
ev1 = 8'd0;
end
default:
begin
ev1 = 8'd0;
end
endcase
end
// distinct ev1's
reg [7:0] ev11;
always @(ev1) //latch
begin
if (ev1 > 8'd0)
ev11 = ev1;
end
// trace packets
reg [1:0] coun;
reg [2:0] coun1;
reg t1, t2, t3, t4, t5, t6;
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
TPE <= 1'b0;
TP <= 32'h0;
coun <= 2'd0;
coun1 <= 3'b0;
end
else if (ev1 == 8'b1)
begin
TPE <= 1'b1;
TP <= perfcoun;
end
else if (((ev1 == 8'd2)||(ev1 == 8'd3)|| (ev1 == 8'd4) || (ev1 == 8'd5)) || ((coun > 2'd0)))
begin
TPE <= 1'b1;
coun <= coun + 2'b1;
if (ev11 == 8'd2)
begin
if (coun == 2'd0)
TP <= key[31:0];
else if (coun == 2'd1)
TP <= key[63:32];
else if (coun == 2'd2)
TP <= key[95:64];
else if (coun == 2'd3)
TP <= key[127:96];
else
TP <= 0;
end
if (ev11 == 8'd3)
begin
if (coun == 2'd0)
TP <= key[31:0];
else if (coun == 2'd1)
TP <= key[63:32];
else if (coun == 2'd2)
TP <= key[95:64];
else if (coun == 2'd3)
TP <= key[127:96];
else
TP <= 0;
end
if (ev11 == 8'd4)
begin
if (coun == 2'd0)
TP <= t_in[31:0];
else if (coun == 2'd1)
TP <= t_in[63:32];
else if (coun == 2'd2)
TP <= t_in[95:64];
else if (coun == 2'd3)
TP <= t_in[127:96];
else
TP <= 0;
end
if (ev11 == 8'd5)
begin
if (coun == 2'd0)
TP <= t_out[31:0];
else if (coun == 2'd1)
TP <= t_out[63:32];
else if (coun == 2'd2)
TP <= t_out[95:64];
else if (coun == 2'd3)
TP <= t_out[127:96];
else
TP <= 0;
end
end
else if (ev1 == 8'd6)
begin
TP <= 32'hFFFFFFFF;
TPE <= 1'b1;
end
else if (ev1 == 8'd7)
begin
TP <= pauscoun;
TPE <= 1'b1;
end
else if ((ev1 == 8'd8) || (t1 == 1'b1))
begin
if (done == 1'b0)
begin
TP <= t_out[31:0]; // just a simplification
TPE <= 1'b1;
t1 <= 1'b1;
end
else
t1 <= 1'b0;
end
else if ((ev1 == 8'd9) || (t2 == 1'b1))
begin
if (done == 1'b0)
begin
TP <= w01;
TPE <= 1'b1;
t2 <= 1'b1;
end
else
t2 <= 1'b0;
end
else if ((ev1 == 8'd10) || (t3 == 1'b1))
begin
if (done == 1'b0)
begin
TP <= t_out[63:32]; // just a simplification
TPE <= 1'b1;
t3 <= 1'b1;
end
else
t3 <= 1'b0;
end
else if ((ev1 == 8'd11) || (t4 == 1'b1))
begin
if (done == 1'b0)
begin
TP <= w02;
TPE <= 1'b1;
t4 <= 1'b1;
end
else
t4 <= 1'b0;
end
else
begin
TPE <= 1'b0;
TP <= 32'b0;
end
end
endmodule
|
`include "./dlx.defines"
`timescale 1ns/1ps
module debug_DLX1 (clk, MRST, MRSTproc, stop, pause, IIn, IAddr, DIn, DOut, DAddr, DRead, DWrite, SPR1, SPR2, DCP, Sel, TP, TPE, EV, Val);
// SPR - Special Purpose Register
// DCP - Debug Configuration Port
// EV - transfer of event occurence info from debug logic to security wrapper
// Val - Any metadata associated with events (if necessary)
// TP - Trace Port for debug logic
input clk;
input MRST;
input MRSTproc;
input stop, pause;
input [`WordSize] IIn, IAddr, DIn, DOut, DAddr;
input DRead, DWrite;
input [31:0] SPR1, SPR2;
input [31:0] DCP;
input [1:0] Sel;
output reg [9:0] EV;
output reg [31:0] Val;
output reg [31:0] TP;
output reg TPE; // Trace Port Enable
// buffers for storing
reg [31:0] IA [0:7];
reg [31:0] ID [0:7];
reg [31:0] DA [0:7];
reg [31:0] DD [0:7];
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
IA[0] <= 0;
IA[1] <= 0;
IA[2] <= 0;
IA[3] <= 0;
IA[4] <= 0;
IA[5] <= 0;
IA[6] <= 0;
IA[7] <= 0;
DA[0] <= 0;
DA[1] <= 0;
DA[2] <= 0;
DA[3] <= 0;
DA[4] <= 0;
DA[5] <= 0;
DA[6] <= 0;
DA[7] <= 0;
end
else
begin
IA[0] <= IAddr;
IA[1] <= IA[0];
IA[2] <= IA[1];
IA[3] <= IA[2];
IA[4] <= IA[3];
IA[5] <= IA[4];
IA[6] <= IA[5];
IA[7] <= IA[6];
DA[0] <= DAddr;
DA[1] <= DA[0];
DA[2] <= DA[1];
DA[3] <= DA[2];
DA[4] <= DA[3];
DA[5] <= DA[4];
DA[6] <= DA[5];
DA[7] <= DA[6];
end
end
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
ID[0] <= 0;
ID[1] <= 0;
ID[2] <= 0;
ID[3] <= 0;
ID[4] <= 0;
ID[5] <= 0;
ID[6] <= 0;
ID[7] <= 0;
DD[0] <= 0;
DD[1] <= 0;
DD[2] <= 0;
DD[3] <= 0;
DD[4] <= 0;
DD[5] <= 0;
DD[6] <= 0;
DD[7] <= 0;
end
else
begin
ID[0] <= IIn;
ID[1] <= ID[0];
ID[2] <= ID[1];
ID[3] <= ID[2];
ID[4] <= ID[3];
ID[5] <= ID[4];
ID[6] <= ID[5];
ID[7] <= ID[6];
DD[0] <= DIn;
DD[1] <= DD[0];
DD[2] <= DD[1];
DD[3] <= DD[2];
DD[4] <= DD[3];
DD[5] <= DD[4];
DD[6] <= DD[5];
DD[7] <= DD[6];
end
end
// CFR - Configuration Register for Debug
reg [31:0] CFR[0:9];
// Instruction Compare - CFR 1-3
// Data Compare - CFR 4-6
// Special Function Register - 7-9
// Counter and Event Sequencer - 10
// configuring the debug registers via DPB
reg [7:0] CFGNO;
reg tag;
reg [1:0] sel1;
always @ (posedge clk)
begin
if (MRST == 1'b0)
begin
CFGNO <= 8'd255;
tag <= 1'b0;
sel1 <= 2'b0;
end
else if (DCP[31] == 1'b1)
begin
CFGNO <= DCP[7:0];
tag <= 1'b1;
sel1 <= Sel;
end
else
begin
tag <= 1'b0;
end
end
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
CFR[0] <= 0;
CFR[1] <= 0;
CFR[2] <= 0;
CFR[3] <= 0;
CFR[4] <= 0;
CFR[5] <= 0;
CFR[6] <= 0;
CFR[7] <= 0;
CFR[8] <= 0;
CFR[9] <= 0;
end
else if ((tag == 1'b1) && (CFGNO >= 8'd0) && (CFGNO <= 8'd15))
begin
CFR[CFGNO] <= DCP;
end
end
// the logic that instruments (trigger and trace) the DLX uP
// 1) program counter range/value comparison (with bit masking like at page/block levels only)
reg [7:0] ev1;
reg [7:0] ev2;
reg [7:0] ev3;
reg [7:0] ev4;
reg [1:0] cucu;
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
EV <= 10'b0;
Val <= 'd0;
cucu <= 'd0;
end
else if ((CFR[9][7:0] != 8'd0)) // no insttrig
begin
if (sel1 == 2'b11) // SPI req access
begin
EV <= {2'd3, ev4};
if ((ev4 > 'd0) || ((cucu > 'd0)))
begin
cucu <= cucu + 2'b1;
if (cucu == 2'd0)
Val <= IIn;
else if (cucu == 2'd1)
Val <= IAddr;
else if (cucu == 2'd2)
Val <= SPR1;
else
Val <= SPR2;
end
end
end
else if ((CFR[0][7:0] != 8'd0) && (CFR[3] == 'd0)) // no datatigg
begin
if (sel1 == 2'b11) // SPI requiring access
begin
EV <= {2'b0, ev1};
if ((ev1 > 'd0) || ((cucu > 'd0)))
begin
cucu <= cucu + 2'b1;
if (cucu == 2'd0)
Val <= IIn;
else if (cucu == 2'd1)
Val <= IAddr;
else if (cucu == 2'd2)
Val <= SPR1;
else
Val <= SPR2;
end
end
end
else if ((CFR[3][7:0] != 8'd0) && (CFR[0] == 'd0)) // no insttrig
begin
if (sel1 == 2'b11) // SPI req access
begin
EV <= {2'b1, ev2};
if ((ev2 > 'd0) || ((cucu > 'd0)))
begin
cucu <= cucu + 2'b1;
if (cucu == 2'd0)
Val <= IIn;
else if (cucu == 2'd1)
Val <= DAddr;
else if (cucu == 2'd2)
Val <= SPR1;
else
Val <= SPR2;
end
end
end
else if ((CFR[6][7:0] != 8'd0)) // no insttrig
begin
if (sel1 == 2'b11) // SPI req access
begin
EV <= {2'd2, ev3};
if ((ev3 > 'd0) || ((cucu > 'd0)))
begin
cucu <= cucu + 2'b1;
if (cucu == 2'd0)
Val <= IIn;
else if (cucu == 2'd1)
Val <= IAddr;
else if (cucu == 2'd2)
Val <= SPR1;
else
Val <= SPR2;
end
end
end
else
begin
EV <= 10'b0;
Val <= 'd0;
cucu <= 'd0;
end
end
reg [31:0] perfcoun; // full program performance counter
reg [31:0] perfcoun1;
reg active;
reg active1;
// based off custom logic
always @(posedge clk)
begin
if (MRSTproc == 1'b0)
begin
perfcoun <= 32'd0;
active <= 1'b0;
end
else if ((IAddr > 32'd0)&& (MRSTproc == 1'b1))
begin
perfcoun <= perfcoun + 32'd1;
active <= 1'b1;
end
else if (MRSTproc == 1'b0)
begin
active <= 1'b0;
end
else
begin
active <= 1'b0;
end
end
always @(posedge clk)
begin
active1 <= active;
end
always @(posedge clk)
begin
perfcoun1 <= perfcoun;
end
reg pause1;
always @(posedge clk)
begin
pause1 <= pause;
end
reg [31:0] pauscoun;
reg activa;
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
pauscoun <= 32'd0;
activa <= 1'b0;
end
else if (((pause1 == 1'b1) && (pause == 1'b0)) || ((activa == 1'b1) && (pause == 1'b0) && (active == 1'b1)))
begin
pauscoun <= pauscoun + 32'b1;
activa <= 1'b1;
end
else if ((pause1 == 1'b0) && (pause == 1'b1))
begin
activa <= 1'b0;
end
else
begin
pauscoun <= 32'd0;
end
end
// Instruction based event trigger
reg [2:0] number;
reg [7:0] blog;
always @(IAddr or IIn)
// what about IIn, like conditional branches, JAL, J, TRAP, RFE??
//always @(*)
begin
casex({CFR[0][31:8], CFR[0][7:0]})
{24'bx, 8'b00100001}: // exact comparison of address with CFR[1]
begin
if (IAddr == CFR[1])
begin
ev1 = 8'b1;
number = 3'b011;
end
else
ev1 = 8'b0;
end
{24'bx, 8'b01000001}: // exact comparison of address with CFR[1]
begin
if (IAddr == CFR[1])
begin
ev1 = 8'b1;
number = 3'b111;
end
else
ev1 = 8'b0;
end
{24'bx, 8'b01100001}: // exact comparison of address with CFR[1]
begin
if (IAddr == CFR[1])
begin
ev1 = 8'd2;
end
else
ev1 = 8'b0;
end
{24'bx, 8'b10000001}: // exact comparison of address with CFR[1]
begin
if (IAddr == CFR[1])
begin
ev1 = 8'd3;
number = 3'b011;
end
else
ev1 = 8'b0;
end
{24'bx, 8'b10100001}: // exact comparison of address with CFR[1]
begin
if (IAddr == CFR[1])
begin
ev1 = 8'd3;
number = 3'b111;
end
else
ev1 = 8'b0;
end
{24'bx, 8'b11000001}: // exact comparison of address with CFR[1]
begin
if (IAddr == CFR[1])
begin
ev1 = 8'd4;
end
else
ev1 = 8'b0;
end
{24'bx, 8'b00100010}: // exact comparison of page address with CFR[1]
begin
if (IAddr[31:12] == CFR[1][31:12])
begin
ev1 = 8'd5;
number = 3'b111;
end
else
ev1 = 8'b0;
end
{24'bx, 8'b01000010}: // exact comparison of page address with CFR[1]
begin
if (IAddr[31:12] == CFR[1][31:12])
begin
ev1 = 8'd6;
end
else
ev1 = 8'b0;
end
{24'bx, 8'b00100011}: // exact comparison of address with CFR[1]
begin
if ((IAddr >= CFR[1]) && (IAddr <= CFR[2]))
begin
ev1 = 8'd7;
//number = 3'b011;
end
else
ev1 = 8'b0;
end
{24'bx, 8'b01000011}: // exact comparison of address with CFR[1]
begin
if ((IAddr >= CFR[1]) && (IAddr <= CFR[2]))
begin
ev1 = 8'd7;
//number = 3'b111;
end
else
ev1 = 8'b0;
end
{24'bx, 8'b01100011}: // exact comparison of address with CFR[1]
begin
if ((IAddr >= CFR[1]) && (IAddr <= CFR[2]))
begin
ev1 = 8'd8;
end
else
ev1 = 8'b0;
end
{24'bx, 8'b00100011}: // exact comparison of address with CFR[1]
begin
if (IIn[31:26] == 6'b010001)
begin
ev1 = 8'd9; // trace IIn till stop // TRAP
end
else
ev1 = 8'b0;
end
{24'bx, 8'b01000011}: // exact comparison of address with CFR[1]
begin
if (IIn[31:26] == 6'b010000)
begin
ev1 = 8'd10; // trace IIn till stop // RFE
end
else
ev1 = 8'b0;
end
{24'bx, 8'b01100011}: // exact comparison of address with CFR[1]
begin
if (IIn[31:26] == 6'b01001x)
begin
ev1 = 8'd11; // trace IIn till stop // JR or JAR
end
else
ev1 = 8'b0;
end
{24'bx, 8'b10000011}: // exact comparison of address with CFR[1]
begin
if (IIn[31:26] > 6'b110011) // invalid address
begin
ev1 = 8'd12; // trace address till stop
end
else
ev1 = 8'b0;
end
// performance counter
{24'bx, 8'b00000100}: // exact comparison of address with CFR[1]
begin
if ((IAddr >= CFR[1]) && (IAddr < CFR[2])) // invalid address
begin
ev1 = 8'd13; // trace address till stop
end
else if (IAddr == CFR[2])
begin
ev1 = 8'd14;
end
else
ev1 = 8'd0;
//nothing
end
{24'bx, 8'b00000101}:
begin
if ((active == 1'b1) && (pause1 == 1'b1) && (pause == 1'b0)) // pause
begin
ev1 = 8'd15;
end
else
ev1 = 8'd0;
end
default:
begin
ev1 = 8'b0;
end
endcase
end
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
blog <= 8'b0;
end
else if ((ev1 == 8'd13) || (ev1 == 8'd14))
begin
blog <= blog + 1'b1;
end
else
begin
blog <= 8'b0;
end
end
// Involving data values/addresses/Read/Write
always @(*)
// what about IIn, like conditional branches, JAL, J, TRAP, RFE??
//always @(*)
begin
casex({CFR[3][31:8], CFR[3][7:0]})
{24'bx, 8'd1}:
begin
if (DIn == CFR[4])
begin
ev2 = 8'b1;
end
else
ev2 = 8'b0;
end
{24'bx, 8'd2}:
begin
if (DOut == CFR[4])
begin
ev2 = 8'd2;
end
else
ev2 = 8'b0;
end
{24'bx, 8'd3}:
begin
if (DIn[0] == CFR[4][0])
begin
ev2 = 8'd3;
end
else
ev2 = 8'd0;
end
{24'bx, 8'd4}:
begin
if (DOut[0] == CFR[4][0])
begin
ev2 = 8'd4;
end
else
ev2 = 8'd0;
end
{24'bx, 8'd5}:
begin
if (( DIn >= CFR[4]) && (DIn <= CFR[5]))
begin
ev2 = 8'h5;
end
else
ev2 = 8'b0;
end
{24'bx, 8'd6}:
begin
if (( DOut >= CFR[4]) && (DOut <= CFR[5]))
begin
ev2 = 8'h6;
end
else
ev2 = 8'b0;
end
{24'bx, 8'd7}:
begin
if (( DAddr >= CFR[4]) && (DAddr <= CFR[5]))
begin
ev2 = 8'h7;
end
else
ev2 = 8'b0;
end
{24'bx, 8'd8}:
begin
if (( DAddr[31:12] == CFR[4][31:12]))
begin
ev2 = 8'h8;
end
else
ev2 = 8'b0;
end
{24'bx, 8'd9}:
begin
if ((DIn == CFR[4]) && (DAddr == CFR[5]))
begin
ev2 = 8'h9;
end
else
ev2 = 8'b0;
end
{24'bx, 8'd10}:
begin
if (( DAddr[31:12] == CFR[4][31:12]) && (DRead == 1'b1))
begin
ev2 = 8'd10;
end
else
ev2 = 8'b0;
end
{24'bx, 8'd11}:
begin
if (( DAddr[31:12] == CFR[4][31:12]) && (DWrite == 1'b1))
begin
ev2 = 8'd11;
end
else
ev2 = 8'b0;
end
{24'bx, 8'd12}:
begin
ev2 = 8'd12;
end
default:
begin
ev2 = 8'b0;
end
endcase
end
// special function register
always @(*)
begin
casex({CFR[6][31:8], CFR[6][7:0]})
{24'bx, 8'd1}:
begin
if (SPR1[31:0] == CFR[7])
begin
ev3 = 8'b1;
end
else
ev3 = 8'b0;
end
{24'bx, 8'd2}:
begin
if (SPR1[0] == CFR[7][0])
begin
ev3 = 8'd2;
end
else
ev3 = 8'b0;
end
{24'bx, 8'd3}:
begin
if (SPR2 == CFR[8])
begin
ev3 = 8'd3;
end
else
ev3 = 8'b0;
end
{24'bx, 8'd4}:
begin
if (SPR2[0] == CFR[8][0])
begin
ev3 = 8'd4;
end
else
ev3 = 8'b0;
end
default:
begin
ev3 = 8'd0;
end
endcase
end
always @(*)
begin
casex({CFR[9][31:8], CFR[9][7:0]})
{24'bx, 8'd1}:
begin
ev4 = 8'd1;
end
{24'bx, 8'd2}:
begin
ev4 = 8'd2;
end
default:
begin
ev4 = 8'd0;
end
endcase
end
reg [2:0] coun;
reg [2:0] coun1;
reg [2:0] coun2;
reg [2:0] coun3;
reg [2:0] coun4;
// trace packet generator alternate
reg ind;
reg ind1;
reg ind2;
reg ind3;
reg ind4;
wire [2:0] num;
assign num = (number == 3'b011)?3'd3:3'd7;
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
TP <= 'h0;
TPE <= 'b0;
coun <= 'b0;
coun1 <= 'b0;
coun2 <= 'b0;
coun3 <= 'b0;
coun4 <= 'b0;
ind <= 1'b0;
ind1 <= 1'b0;
ind2 <= 1'b0;
ind3 <= 1'b0;
ind4 <= 1'b0;
end
//else if (sel1 == 2'b10) // external debugger
//begin
else if (((CFR[9] == 32'd1) && (ev3 == 8'd1) && (ev1 == 8'd4)) || ((coun > 0) && (coun <= 3'd7)))
begin
coun <= coun + 3'b1; // reusing this
TPE <= 1'b1;
TP <= ID[0];
end
else if (((CFR[9] == 32'd2) && (ev3 == 8'd1) && (ev1 == 8'd11)) || ((coun > 0) && (coun <= 3'd7)))
begin
coun <= coun + 3'b1; // reusing this
TPE <= 1'b1;
TP <= ID[0];
end
else if ((ev3 == 8'd1) || ((coun > 0) && (coun <= 3'd7)))
begin
coun <= coun + 3'b1; // reusing this
TPE <= 1'b1;
TP <= ID[7];
end
else if ((ev3 == 8'd2) || ((coun > 0) && (coun <= 3'd7)))
begin
coun <= coun + 3'b1; // reusing this
TPE <= 1'b1;
TP <= ID[7];
end
else if ((ev3 == 8'd3) || ((coun > 0) && (coun <= 3'd7)))
begin
coun <= coun + 3'b1; // reusing this
TPE <= 1'b1;
TP <= ID[0];
end
else if ((ev3 == 8'd4) || ((coun > 0) && (coun <= 3'd7)))
begin
coun <= coun + 3'b1; // reusing this
TPE <= 1'b1;
TP <= ID[0];
end
else if (((ev1 == 8'd1)&&(ev2 == 8'd0))|| ((coun > 0) && (coun <= number)))
begin
coun <= coun + 3'b1;
TPE <= 1'b1;
TP <= IA[number];
end
else if (((ev1 == 8'd2)&&(ev2 == 8'd0))|| (ind1 == 1'b1))
begin
TPE <= 1'b1;
TP <= IA[0];
if (stop == 1'b0)
ind1 <= 1'b1;
else
ind1 <= 1'b0;
end
else if (((ev1 == 8'd3)&&(ev2 == 8'd0))|| ((coun1 > 0) && (coun1 <= number)))
begin
coun1 <= coun1 + 3'b1;
TPE <= 1'b1;
TP <= ID[number];
end
else if (((ev1 == 8'd4)&&(ev2 == 8'd0))|| (ind == 1'b1))
begin
TPE <= 1'b1;
TP <= ID[0];
if (stop == 1'b0)
ind <= 1'b1;
else
ind <= 1'b0;
end
else if (((ev1 == 8'd5)&&(ev2 == 8'd0))|| ((coun2 > 0) && (coun2 <= number)))
begin
coun2 <= coun2 + 3'b1;
TPE <= 1'b1;
TP <= ID[number];
end
else if (((ev1 == 8'd6)&&(ev2 == 8'd0))|| (ind2 == 1'b1))
begin
TPE <= 1'b1;
TP <= ID[0];
if (stop == 1'b0)
ind2 <= 1'b1;
else
ind2 <= 1'b0;
end
else if (ev1 == 8'd7)
begin
TPE <= 1'b1;
TP <= ID[0];
end
else if (ev1 == 8'd8)
begin
TPE <= 1'b1;
TP <= IA[0];
end
else if (((ev1 == 8'd9) || (ev1 == 8'd10) || (ev1 == 8'd11) || (ev1 == 8'd12)) || (ind3 == 1'b1))
begin
TPE <= 1'b1;
TP <= ID[0];
if (stop == 1'b0)
ind3 <= 1'b1;
else
ind3 <= 1'b0;
end
else if (ev1 == 8'd14)
begin
TPE <= 1'b1;
TP <= {24'd0, blog};
end
else if (((ev2 > 8'b0) && (ev2 < 8'd11))|| (ind4 == 1'b1))
begin
TPE <= 1'b1;
TP <= ID[0];
if (stop == 1'b0)
ind4 <= 1'b1;
else
ind4 <= 1'b0;
end
else if ((ev2 == 8'd11) || ((coun4 > 3'b0) && (coun4 < 3'd7)))
begin
coun4 <= coun4 + 3'b1;
TPE <= 1'b1;
TP <= IA[7];
end
else if ((ev2 == 8'd12) && (active1 == 1'b1) && (active == 1'b0))
begin
TP <= perfcoun1;
TPE <= 1'b1;
end
else if ((ev2 == 8'd15) || (pause1 == 1'b0) && (pause == 1'b0)) // change
begin
TP <= pauscoun;
TPE <= 1'b1;
end
else
begin
TPE <= 1'b0;
TP <= 32'b0;
coun <= 3'b0;
coun1 <= 3'b0;
coun2 <= 3'b0;
coun3 <= 3'b0;
coun4 <= 3'b0;
ind <= 1'b0;
ind1 <= 1'b0;
ind2 <= 1'b0;
ind3 <= 1'b0;
ind4 <= 1'b0;
end
end
endmodule
|
`timescale 1 ns / 1 ps
`include "FFT128_CONFIG.inc"
module debug_FFT (clk, MRST, START, SHIFT, DR, DI, RDY, OVF1, OVF2, ADDR, DOR, DOI, DCP, Sel, EV, Val, TP, TPE);
`FFT128paramnb //nb is the data bit width
input clk;
input MRST;
input START;
input [3:0] SHIFT;
input [nb-1:0] DR, DI ;
input RDY, OVF1, OVF2;
input [6:0] ADDR;
input [nb+3:0] DOR, DOI;
output reg [7:0] EV;
output reg [31:0] Val;
output reg [31:0] TP;
output reg TPE;
input [31:0] DCP;
input [1:0] Sel;
// starting from configuration register 16 onwards
//0-15 - DLX
// configuring the debug registers via DPB
reg [7:0] CFGNO;
reg tag;
reg [1:0] sel1;
reg [31:0] CFR[0:7];
always @ (posedge clk)
begin
if (MRST == 1'b0)
begin
CFGNO <= 8'd255;
tag <= 1'b0;
sel1 <= 2'b0;
end
else if (DCP[31] == 1'b1)
begin
CFGNO <= DCP[7:0];
tag <= 1'b1;
sel1 <= Sel;
end
else
begin
tag <= 1'b0;
end
end
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
CFR[0] <= 0;
CFR[1] <= 0;
CFR[2] <= 0;
CFR[3] <= 0;
CFR[4] <= 0;
CFR[5] <= 0;
CFR[6] <= 0;
CFR[7] <= 0;
end
else if ((tag == 1'b1) && (CFGNO >= 8'd16) && (CFGNO <= 8'd31))
begin
CFR[CFGNO - 8'd16] <= DCP;
end
end
// info to the wrapper
reg [7:0] ev1;
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
EV <= 8'b0;
Val <= 32'b0;
end
else if ((CFR[0] > 32'd0)) // no datatigg
begin
if (sel1 == 2'b11) // SPC requiring access
begin
EV <= ev1;
if (ev1 > 8'd0)
begin
Val <= {DI, DR};
end
end
end
else
EV <= 8'd0;
end
// CFR 0 being 1 means only the performance counter
reg [31:0] perfcoun; // full program performance counter
reg active;
reg active1;
reg START1;
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
perfcoun <= 32'd0;
active <= 1'b0;
end
else if (((START1 == 1'b1) && (START == 1'b0)) || ((active == 1'b1) && (RDY == 1'b0)))
begin
perfcoun <= perfcoun + 32'b1;
active <= 1'b1;
end
else if (RDY == 1'b1)
begin
active <= 1'b0;
end
else
begin
perfcoun <= 32'd0;
end
end
// don't need to store perfcoun again
always @(posedge clk)
begin
active1 <= active;
end
always @(posedge clk)
begin
START1 <= START;
end
reg [nb+3:0] DOR1;
reg [nb+3:0] DOI1;
//reg [nb+3:0] DOI2;
//
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
DOR1 <= 20'd0;
DOI1 <= 20'd0;
end
else if (RDY == 1'b1)
begin
DOR1 <= DOR;
DOI1 <= DOI;
end
else
begin
DOR1 <= DOR;
DOI1 <= DOI;
end
end
reg [5:0] overflowcoun;
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
overflowcoun <= 6'd0;
end
else if (OVF1 == 1'b1)
begin
overflowcoun <= overflowcoun + 6'd1;
end
else if (RDY == 1'b1)
begin
overflowcoun <= 6'd0;
end
end
always @(*)
begin
casex({CFR[0][31:8], CFR[0][7:0]})
{24'bx, 8'b00000001}:
begin
if (RDY == 1'b1)
begin
ev1 = 8'd1;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000010}:
begin
if ((START1 == 1'b1) && (START == 1'b0))
begin
ev1 = 8'd2;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000011}:
begin
if (RDY == 1'b1)
begin
ev1 = 8'd3;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000100}:
begin
if (RDY == 1'b1)
begin
ev1 = 8'd4;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000101}:
begin
if ((OVF1 == 1'b1) && (OVF2 == 1'b1))
begin
ev1 = 8'd5;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000110}:
begin
if (overflowcoun > 6'd32)
begin
ev1 = 8'd6;
end
else
ev1 = 8'd0;
end
default:
begin
ev1 = 8'd0;
end
endcase
end
reg [1:0] coun;
reg [2:0] coun1;
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
TPE <= 1'b0;
TP <= 32'h0;
coun <= 2'd0;
coun1 <= 3'b0;
end
else if (ev1 == 8'b1)
begin
TPE <= 1'b1;
TP <= perfcoun;
end
else if (ev1 == 8'd2)
begin
TPE <= 1'b1;
TP <= {DI, DR};
end
else if ((ev1 == 8'd3) || ((coun > 2'd0) && (coun <= 2'd3)))
begin
TPE <= 1'b1;
coun <= coun + 2'b1;
if (coun == 2'b0)
TP <= {perfcoun};
else if (coun == 2'b1)
TP <= {12'b0, DOR};
else if (coun == 2'd2)
TP <= {12'b0, DOI1};
else if (coun == 2'd3)
TP <= {25'b0, ADDR};
end
else if ((ev1 == 8'd4) || ((coun1 > 3'd0) && (coun1 < 3'd6)))
begin
TPE <= 1'b1;
coun1 <= coun1 + 3'd1;
TP <= ADDR;
end
else if (ev1 == 8'd5)
begin
TPE <= 1'b1;
TP <= 32'hFFFFFFFF;
end
else if (ev1 == 8'd6)
begin
TPE <= 1'b1;
TP <= ADDR;
end
else
begin
TPE <= 1'b0;
TP <= 32'h0;
coun <= 2'b0;
end
end
endmodule
|
`include "./dlx.defines"
`timescale 1ns/1ps
module debug_mem (clk, MRST, din, dout, daddr, dread, dwrite, din1, dout1, daddr1, dread1, dwrite1, din2, dout2, daddr2, dread2, dwrite2, din3, dout3, daddr3, dread3, dwrite3, DCP, Sel, EV, Val, TP, TPE);
input clk, MRST;
input [31:0] din, din1, din2, din3, dout, dout1, dout2, dout3, daddr, daddr1, daddr2, daddr3;
input dread, dwrite, dread1, dwrite1, dread2, dwrite2, dread3, dwrite3 ;
input [31:0] DCP;
input [1:0] Sel;
output reg [31:0] Val, TP;
output reg TPE;
output reg [7:0] EV;
reg [7:0] CFGNO;
reg tag;
reg [1:0] sel1;
reg [31:0] CFR[0:7];
always @ (posedge clk)
begin
if (MRST == 1'b0)
begin
CFGNO <= 8'd255;
tag <= 1'b0;
sel1 <= 2'b0;
end
else if (DCP[31] == 1'b1)
begin
CFGNO <= DCP[7:0];
tag <= 1'b1;
sel1 <= Sel;
end
else
begin
tag <= 1'b0;
end
end
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
CFR[0] <= 0;
CFR[1] <= 0;
CFR[2] <= 0;
CFR[3] <= 0;
CFR[4] <= 0;
CFR[5] <= 0;
CFR[6] <= 0;
CFR[7] <= 0;
end
else if ((tag == 1'b1) && (CFGNO >= 8'd48) && (CFGNO <= 8'd64))
begin
CFR[CFGNO - 8'd48] <= DCP;
end
end
// info to the wrapper
reg [7:0] ev1;
reg [7:0] ev2;
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
EV <= 8'b0;
Val <= 32'd0;
end
else if ((CFR[0] > 32'd0)) // no datatigg
begin
if (sel1 == 2'b11) // SPI requiring access
begin
EV <= ev2;
if (ev2 > 'd0)
Val <= TP;
end
end
else
begin
EV <= 8'd0;
Val <= 'd0;
end
end
always @(posedge clk)
begin
ev2 <= ev1;
end
always @(*)
begin
casex({CFR[0][31:8], CFR[0][7:0]})
{24'bx, 8'b00000001}:
begin
if ((dread == 1'b1) && (daddr > CFR[1]) && (daddr < CFR[2]))
begin
ev1 = 8'd1;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000010}:
begin
if ((dwrite == 1'b1) && (daddr > CFR[1]) && (daddr < CFR[2]))
begin
ev1 = 8'd2;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000011}:
begin
if ((dread1 == 1'b1) && (daddr1 > CFR[1]) && (daddr1 < CFR[2]))
begin
ev1 = 8'd3;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000100}:
begin
if ((dwrite1 == 1'b1) && (daddr1 > CFR[1]) && (daddr1 < CFR[2]))
begin
ev1 = 8'd4;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000101}:
begin
if ((dread2 == 1'b1) && (daddr2 > CFR[1]) && (daddr2 < CFR[2]))
begin
ev1 = 8'd5;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000110}:
begin
if ((dwrite2 == 1'b1) && (daddr2 > CFR[1]) && (daddr2 < CFR[2]))
begin
ev1 = 8'd6;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000111}:
begin
if ((dread3 == 1'b1) && (daddr3 > CFR[1]) && (daddr3 < CFR[2]))
begin
ev1 = 8'd7;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00001000}:
begin
if ((dwrite3 == 1'b1) && (daddr3 > CFR[1]) && (daddr3 < CFR[2]))
begin
ev1 = 8'd8;
end
else
ev1 = 8'd0;
end
default:
begin
ev1 = 8'd0;
end
endcase
end
// trace packet generation
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
TPE <= 1'b0;
TP <= 32'h0;
end
else if (ev1 == 8'b1)
begin
TPE <= 1'b1;
TP <= din;
end
else if (ev1 == 8'd2)
begin
TPE <= 1'b1;
TP <= dout;
end
else if (ev1 == 8'd3)
begin
TPE <= 1'b1;
TP <= din1;
end
else if (ev1 == 8'd4)
begin
TPE <= 1'b1;
TP <= dout1;
end
else if (ev1 == 8'd5)
begin
TPE <= 1'b1;
TP <= din2;
end
else if (ev1 == 8'd6)
begin
TPE <= 1'b1;
TP <= dout2;
end
else if (ev1 == 8'd7)
begin
TPE <= 1'b1;
TP <= din3;
end
else if (ev1 == 8'd8)
begin
TPE <= 1'b1;
TP <= dout3;
end
else
begin
TPE <= 1'b0;
TP <= 'd0;
end
end
endmodule
|
`include "spi_defines.v"
`include "timescale.v"
module debug_SPI(clk, MRST, go, last_bit, dat_i, we_i, tx_sel, err_i, divider, s_out, DCP, Sel, EV, Val, TP, TPE);
input clk, MRST, go, last_bit, we_i, err_i;
input s_out;
input [31:0] dat_i;
input [3:0] tx_sel;
input [15:0] divider;
input [31:0] DCP;
input [1:0] Sel;
output reg [31:0] Val, TP;
output reg TPE;
output reg [7:0] EV;
reg [7:0] CFGNO;
reg tag;
reg [1:0] sel1;
reg [31:0] CFR[0:7];
always @ (posedge clk)
begin
if (MRST == 1'b0)
begin
CFGNO <= 8'd255;
tag <= 1'b0;
sel1 <= 2'b0;
end
else if (DCP[31] == 1'b1)
begin
CFGNO <= DCP[7:0];
tag <= 1'b1;
sel1 <= Sel;
end
else
begin
tag <= 1'b0;
end
end
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
CFR[0] <= 0;
CFR[1] <= 0;
CFR[2] <= 0;
CFR[3] <= 0;
CFR[4] <= 0;
CFR[5] <= 0;
CFR[6] <= 0;
CFR[7] <= 0;
end
else if ((tag == 1'b1) && (CFGNO >= 8'd64) && (CFGNO <= 8'd80))
begin
CFR[CFGNO - 8'd64] <= DCP;
end
end
// info to the wrapper
reg [7:0] ev1;
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
EV <= 8'b0;
end
else if ((CFR[0] > 32'd0))
begin
if (sel1 == 2'b11) // SPI requiring access
begin
EV <= ev1;
end
end
else
EV <= 8'd0;
end
reg go1;
reg active;
always @(posedge clk)
go1 <= go;
reg [15:0] perfcoun;
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
perfcoun <= 16'b0;
active <= 1'b0;
end
else if (((go1 == 1'b0)&& (go == 1'b1)) || (active == 1'b1))
begin
perfcoun <= perfcoun + 16'd1;
if (last_bit == 1'b1)
active <= 1'b0;
else
active <= 1'b1;
end
else
begin
perfcoun <= 'd0;
active <= 1'b0;
end
end
always @(*)
begin
casex({CFR[0][31:8], CFR[0][7:0]})
{24'bx, 8'b00000001}:
begin
if ((go1 == 1'b0) && (go == 1'b1))
begin
ev1 = 8'd1;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000010}:
begin
if (perfcoun == (CFR[1] << 2))
begin
ev1 = 8'd2;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000011}:
begin
if (last_bit == 1'b1)
begin
ev1 = 8'd3;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000100}:
begin
if (err_i == 1'b1)
begin
ev1 = 8'd4;
end
else
ev1 = 8'd0;
end
{24'bx, 8'b00000101}:
begin
if (dat_i == (CFR[1]))
begin
ev1 = 8'd5;
end
else
ev1 = 8'd0;
end
default:
begin
ev1 = 8'd0;
end
endcase
end
// trace packets
reg [1:0] coun;
reg activa;
always @(posedge clk)
begin
if (MRST == 1'b0)
begin
TPE <= 1'b0;
TP <= 32'h0;
coun <= 2'd0;
activa <= 'd0;
//coun1 <= 3'b0;
end
else if ((ev1 == 8'b1) || ((coun > 2'b0) && (coun < 2'b10)))
begin
TPE <= 1'b1;
coun <= coun + 2'b1;
if (coun == 2'b0)
TP <= dat_i;
else
TP <= {11'b0, we_i, tx_sel, divider};
end
else if ((ev1 == 8'd2) || (activa == 1'b1))
begin
TPE <= 1'b1;
TP <= {31'd0, s_out};
if (last_bit == 1'b0)
activa <= 1'b1;
else
activa <= 1'b0;
end
else if (ev1 == 8'd3)
begin
TPE <= 1'b1;
TP <= {16'd0, perfcoun};
end
else if (ev1 == 8'd4)
begin
TPE <= 1'b1;
TP <= {s_out, 15'd0, perfcoun};
end
else if (ev1 == 8'd5)
begin
TPE <= 1'b1;
TP <= 32'hFFFFFFFF;
end
else
begin
TPE <= 1'b0;
TP <= 'd0;
coun <= 2'd0;
activa <= 'd0;
end
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Top level of the high speed FFT core
// FUNCTION: Structural model of the high speed 128-complex point FFT
// core intended for synthesizing
// for any type FPGAs and ASIC.
// FILES: FFT128.v - root unit, this file,
// FFT128_CONFIG.inc - core configuration file
// BUFRAM128C.v - 1-st,2-nd,3-d data buffer, contains:
// RAM2x128C.v - dual ported synchronous RAM, contains:
// RAM128.v -single ported synchronous RAM
// FFT16.v- 1-st,2-nd stages implementing 16-point FFTs, contains
// MPU707.v, MPU707_2.v - multiplier to the factor 0.707.
// ROTATOR256.v - unit for rotating complex vectors, contains
// WROM256.v - ROM of twiddle factors.
// CNORM.v - normalization stages
// UNFFT256_TB.v - testbench file, includes:
// Wave_ROM256.v - ROM with input data and result reference data
// SineROM256_gen.pl - PERL script to generate the Wave_ROM256.v file
//
// PROPERTIES: 1. Fully pipelined, 1 complex data in, 1 complex result out each clock cycle
// 2. Input data, output data, coefficient widths are adjustable in range 8..16
// 3. Normalization stages trigger the data overflow and shift data right
// to prevent the overflow
// 4. Core can contain 2 or 3 data buffers. In the configuration of 2 buffers
// the results are in the shuffled order but provided with the proper address.
// 5. The core operation can be slowed down by the control of the ED input
// 6. The reset RST is synchronous one
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`timescale 1 ns / 1 ps
`include "FFT128_CONFIG.inc"
module FFT128 ( CLK ,RST ,ED ,START ,SHIFT ,DR ,DI ,RDY ,OVF1 ,OVF2 ,ADDR ,DOR ,DOI );
`FFT128paramnb //nb is the data bit width
output RDY ; // in the next cycle after RDY=1 the 0-th result is present
wire RDY ;
output OVF1 ; // 1 signals that an overflow occured in the 1-st stage
wire OVF1 ;
output OVF2 ; // 1 signals that an overflow occured in the 2-nd stage
wire OVF2 ;
output [6:0] ADDR ; //result data address/number
wire [6:0] ADDR ;
output [nb+3:0] DOR ;//Real part of the output data,
wire [nb+3:0] DOR ; // the bit width is nb+4, can be decreased when instantiating the core
output [nb+3:0] DOI ;//Imaginary part of the output data
wire [nb+3:0] DOI ;
input CLK ; //Clock signal is less than 300 MHz for the Xilinx Virtex5 FPGA
wire CLK ;
input RST ; //Reset signal, is the synchronous one with respect to CLK
wire RST ;
input ED ; //=1 enables the operation (eneabling CLK)
wire ED ;
input START ; // its falling edge starts the transform or the serie of transforms
wire START ; // and resets the overflow detectors
input [3:0] SHIFT ; // bits 1,0 -shift left code in the 1-st stage
wire [3:0] SHIFT ; // bits 3,2 -shift left code in the 2-nd stage
input [nb-1:0] DR ; // Real part of the input data, 0-th data goes just after
wire [nb-1:0] DR ; // the START signal or after 255-th data of the previous transform
input [nb-1:0] DI ; //Imaginary part of the input data
wire [nb-1:0] DI ;
wire [nb-1:0] dr1,di1;
wire [nb+1:0] dr3,di3,dr4,di4, dr5,di5 ;
wire [nb+2:0] dr2,di2;
wire [nb+5:0] dr6,di6;
wire [nb+3:0] dr7,di7,dr8,di8;
wire rdy1,rdy2,rdy3,rdy4,rdy5,rdy6,rdy7,rdy8;
reg [7:0] addri ;
// input buffer =8-bit inversion ordering
BUFRAM128C_1 #(nb) U_BUF1(.CLK(CLK), .RST(RST), .ED(ED), .START(START),
.DR(DR), .DI(DI), .RDY(rdy1), .DOR(dr1), .DOI(di1));
//1-st stage of FFT
FFT8 #(nb) U_FFT1(.CLK(CLK), .RST(RST), .ED(ED),
.START(rdy1),.DIR(dr1),.DII(di1),
.RDY(rdy2), .DOR(dr2),. DOI(di2));
wire [1:0] shiftl= SHIFT[1:0];
CNORM_1 #(nb) U_NORM1( .CLK(CLK), .ED(ED), //1-st normalization unit
.START(rdy2), // overflow detector reset
.DR(dr2), .DI(di2),
.SHIFT(shiftl), //shift left bit number
.OVF(OVF1),
.RDY(rdy3),
.DOR(dr3),.DOI(di3));
// rotator to the angles proportional to PI/64
ROTATOR128 #(nb+2) U_MPU (.CLK(CLK),.RST(RST),.ED(ED),
.START(rdy3),. DR(dr3),.DI(di3),
.RDY(rdy4), .DOR(dr4), .DOI(di4));
BUFRAM128C_2 #(nb+2) U_BUF2(.CLK(CLK),.RST(RST),.ED(ED), // intermediate buffer =8-bit inversion ordering
.START(rdy4),. DR(dr4),.DI(di4),
.RDY(rdy5), .DOR(dr5), .DOI(di5));
//2-nd stage of FFT
FFT16 #(nb+2) U_FFT2(.CLK(CLK), .RST(RST), .ED(ED),
.START(rdy5),. DIR(dr5),.DII(di5),
.RDY(rdy6), .DOR(dr6), .DOI(di6));
wire [1:0] shifth= SHIFT[3:2];
//2-nd normalization unit
CNORM_2 #(nb+2) U_NORM2 ( .CLK(CLK), .ED(ED),
.START(rdy6), // overflow detector reset
.DR(dr6), .DI(di6),
.SHIFT(shifth), //shift left bit number
.OVF(OVF2),
.RDY(rdy7),
.DOR(dr7), .DOI(di7));
BUFRAM128C #(nb+4) Ubuf3(.CLK(CLK),.RST(RST),.ED(ED), // intermediate buffer =8-bit inversion ordering
.START(rdy7),. DR(dr7),.DI(di7),
.RDY(rdy8), .DOR(dr8), .DOI(di8));
`ifdef FFT128parambuffers3 // 3-data buffer configuratiion
always @(posedge CLK) begin //POINTER to tC:/Users/Abhishek/Desktop/fulldesignS4/fft128.vhe result samples
if (RST)
addri<=7'b000_0000;
else if (rdy8==1 )
addri<=7'b000_0000;
else if (ED)
addri<=addri+1;
end
assign ADDR= addri ;
assign DOR=dr8;
assign DOI=di8;
assign RDY=rdy8;
`else
always @(posedge CLK) begin //POINTER to the result samples
if (RST)
addri<=7'b000_0000;
else if (rdy7)
addri<=7'b000_0000;
else if (ED)
addri<=addri+1;
end
assign #1 ADDR= {addri[2:0] , addri[6:3]} ;
assign #2 DOR= dr7;
assign #2 DOI= di7;
assign RDY= rdy7;
`endif
endmodule
|
`timescale 1 ns / 1 ps
`include "FFT128_CONFIG.inc"
module FFT128wrapper(MASRST, CLK, RSTT, ED, START, SHIFT, DR, DI, RDY, OVF1, OVF2, ADDR, DOR, DOI, WSI, WRSTN, SelectWIR, ShiftWR, CaptureWR, WSO, DWR, DO, DAD, SPCREQ, SPCDIS, MRST, DBus, Sel, TP1, TPE1);
`FFT128paramnb //nb is the data bit width
output RDY ; // in the next cycle after RDY=1 the 0-th result is present
wire RDY ;
output OVF1 ; // 1 signals that an overflow occured in the 1-st stage
wire OVF1 ;
output OVF2 ; // 1 signals that an overflow occured in the 2-nd stage
wire OVF2 ;
output [6:0] ADDR ; //result data address/number
wire [6:0] ADDR ;
output [nb+3:0] DOR ;//Real part of the output data,
wire [nb+3:0] DOR ; // the bit width is nb+4, can be decreased when instantiating the core
output [nb+3:0] DOI ;//Imaginary part of the output data
wire [nb+3:0] DOI ;
input CLK ; //Clock signal is less than 300 MHz for the Xilinx Virtex5 FPGA
input MASRST;
wire CLK ;
input RSTT ; //Reset signal, is the synchronous one with respect to CLK
wire RSTT ;
input ED ; //=1 enables the operation (eneabling CLK)
wire ED ;
input START ; // its falling edge starts the transform or the serie of transforms
wire START ; // and resets the overflow detectors
input [3:0] SHIFT ; // bits 1,0 -shift left code in the 1-st stage
wire [3:0] SHIFT ; // bits 3,2 -shift left code in the 2-nd stage
input [nb-1:0] DR ; // Real part of the input data, 0-th data goes just after
wire [nb-1:0] DR ; // the START signal or after 255-th data of the previous transform
input [nb-1:0] DI ; //Imaginary part of the input data
wire [nb-1:0] DI ;
input SPCREQ, SPCDIS;
input MRST;
input [31:0] DBus;
input [1:0] Sel;
output [31:0] TP1;
output TPE1;
wire [7:0] EV;
wire [31:0] Val;
// the boundary scan signals
input WSI, WRSTN, SelectWIR, ShiftWR, CaptureWR;
output WSO;
wire RST;
assign RST = (RSTT||SPCDIS);
//assign RST = (RSTT);
////added signals to interface with security policy controller
///**********************************************************///
///// SECURITY WRAPPER ////
///// here pause is the ED (was already there to halt the operation)
output reg DWR;
output reg [31:0]DO, DAD;
reg [31:0] DO1, DAD1; // stores the data to be sent to SPC
reg DWR1 ; //stores write to SPC status for next cycle
//wire [31:0] DO2;
reg [9:0] counter;
reg [3:0] state;
reg [nb+3:0] DOII;
reg [31:0] buff[0:3]; // basically stores the past 5 data i/p
//reg [2:0] fincoun;
//assign DO1[31:16] = DR; // start of computation
//assign DO1[15:0] = 16'b0;
//assign DO2[31:16] = DOR; // end of computation
//assign DO2[15:0] = 16'b1;
// logic for writing new info into the SPC Controller data cache
reg RST1, START1; // STARTF go down in next cycle after RSTF
reg RST2, START2;
reg RDY1;
reg ED1; // ED is basically for clock gating and stuff
// time stamp
always @(posedge CLK)
begin
if ((((RST2 == 1'b1)&&(RST == 1'b0))&&((START2 == 1'b1)&&(START == 1'b0))&& (ED == 1'b1))||(counter == 10'd450))
begin
counter <= 10'd0;
end
else if ((ED == 1'b1)&& (RST == 1'b0))
begin
counter <= counter + 10'd1; // 10-20 extra cycles for safety!!
end
//else if (MASRST == 1'b1) // not really sure if we needed this
//begin
//counter <= 10'd0;
//end
end
/////// EV stuff
reg [7:0] EV2;
always @(posedge CLK)
begin
EV2 <= EV;
end
// Debug - SPC interface and storage
reg [31:0] tempbuff;
//reg [1:0] cru;
always @(posedge CLK)
begin
if (MASRST == 1'b1)
begin
tempbuff <= 'd0;
end
else if ((EV[7:0] > 'd0))
begin
tempbuff <= Val;
end
else
tempbuff <= tempbuff; // has to store
end
// needs to store tempbuff to wait for SPCREQ
//end
//end
always @(posedge CLK)
begin
RST1 <= RST;
RST2 <= RST1;
START1 <= START;
START2 <= START1;
RDY1 <= RDY;
ED1 <= ED;
if (counter == 10'd441)
begin
DOII <= DOI;
end
else if (MASRST == 1'b1)
begin
DOII <= 20'd0;
end
end
// always assuming that EDF would be ON in general
// For normal mode WRSTN is 1'b1 and ShiftWR = 0 (scan =0, hold //= 0);
// combinational security wrapper logic
reg [2:0] pastcount;
always @(*)
begin
if (((RST2 == 1'b1)&&(RST == 1'b0))&&((START2 == 1'b1)&&(START == 1'b0))&& (ED == 1'b1))
begin
pastcount = pastcount + 3'd1;
end
else if (MASRST == 1'b1)
begin
pastcount = 3'd0;
end
end // need to incorporate a MASTER RESET signifying boot FROM SYTEM CONTROLLER
// what about the buffer
//always @(posedge CLK)
//begin
//if (((RST2 == 1'b1)&&(RST == 1'b0))&&((START2 == 1'b1)&&(START == 1'b0))&& (ED == 1'b1)) // start of operation
//begin
//buff[pastcount] <= {DR, DI};
//end
//end // need to incorporate a MASTER RESET FROM SYTEM CONTROLLER
// what about the buffer
always @(pastcount)
begin
//if (((RST2 == 1'b1)&&(RST == 1'b0))&&((START2 == 1'b1)&&(START == 1'b0))&& (ED == 1'b1)) // start of operation
//begin
buff[pastcount] <= {DR, DI};
//end
end // need to incorporate a MASTER RESET FROM SYTEM CONTROLLER
// external interface to SPC
//always @(posedge CLK)
//begin
//if ((counter == 10'd442)) // done as the address jumps from 4 to 6 at this instant (manual decrease)
//begin
//DAD <= DAD1 - 32'd1;
//end
//else
//begin
//DAD <= DAD1;
//end
//DO <= DO1;
//DWR <= DWR1;
//end
// THINKING in terms of a state machine /////////////////////////////////////
//
always @(posedge CLK)
begin
if (MASRST == 1'b1)
begin
state <= 4'd0;
end
else if ((WRSTN == 1'b1) && (ShiftWR == 1'b0)) // normal mode
begin
if (((RST2 == 1'b1)&&(RST == 1'b0))&&((START2 == 1'b1)&&(START == 1'b0))&& (ED == 1'b1))
begin
state <= 4'd1;
end
else if (counter == 10'b1) // send the imaginary i/p in next cycle
begin
state <= 4'd2;
end
else if ((RDY1 == 1'b0)&&(RDY == 1'b1)) // end of operation
begin
state <= 4'd3;
end
else if (counter == 10'd442)
begin
state <= 4'd4;
end
else if ((ED1 == 1'b1) && (ED == 1'b0))
begin
state <= 4'd5;
end
else if ((ED1 == 1'b0) && (ED == 1'b1))
begin
state <= 4'd6;
end
else if (SPCREQ == 1'b1)
begin
state <= 4'd15;
end
else if (EV > 'd0)
begin
state <= 4'd8;
end
else
begin
state <= 4'd7;
end
end
else //// test and other modes
begin
state <= 4'd0;
//if (((RST2 == 1'b1)&&(RST == 1'b0))&&((START2 == 1'b1)&&(START == 1'b0))&& (ED == 1'b1))
//begin
//state <= 4'd8;
//end
//else if (counter == 10'b1) // send the imaginary i/p in next cycle
//begin
//state <= 4'd9;
//end
//else if ((RDY1 == 1'b0)&&(RDY == 1'b1)) // end of operation
//begin
// state <= 4'd10;
//end
//else if (counter == 10'd442)
//begin
// state <= 4'd11;
//end
//else if ((ED1 == 1'b1) && (ED == 1'b0))
//begin
// state <= 4'd12;
//end
//else if ((ED1 == 1'b0) && (ED == 1'b1))
//begin
// state <= 4'd13;
//end
//else
//begin
// state <= 4'd14;
//end
//
end
end
//// SPCDIS anded to DWR just to maintaintain concistency with other IPs...NOT REQUIRED HERE AS RST LOGIC IS DONE IN A DIFFERENT WAY HERE (RSTT || SPCDIS)
always @(state)
begin
if (SPCDIS == 1'b0) // an addition (CAN REMOVE THE DWR ADDITIONS LATER)
begin
case(state)
4'd0: begin
DWR = 1'b0;
DAD = 32'd0;
DO = 32'd0;
end
4'd1: begin
DWR = 1'b1; // maintain consistency with other IPs i.e. NOT 1 && SPCDIS here
DAD =32'd48;
DO = {DR, SHIFT, 8'd0, state}; // initial data
end
4'd2:
begin
DWR = (1'b1 && (!SPCDIS));
DAD = DAD + 32'd1;
DO = {DI, SHIFT, 8'd0, state}; // initial data
end
4'd3:
begin
DWR = (1'b1 && (!SPCDIS));
DAD = DAD + 32'd1;
DO = {DOR, OVF2, 7'b0, state}; // end of operation and sending real
end
4'd4:
begin
DWR = (1'b1 && (!SPCDIS));
DAD = DAD + 32'd1;
DO = {DOII, 8'b0, state}; // end of operation and sending real
end
4'd5:
begin
DWR = (1'b1 && (!SPCDIS));
DAD = DAD + 32'd1;
DO = {counter, 18'b0, state}; // pause cycle
end
4'd6:
begin
DWR = (1'b1 && (!SPCDIS));
DAD = DAD + 32'd1;
DO = {28'b0, state}; // end of pause cycle
end
4'd7:
begin
DWR = 1'b0;
DAD = DAD ;
DO = 32'd0;
end
4'd8:
begin
DWR = (1'b1 && (!SPCDIS));
DAD = DAD + 32'd1;
DO = {10'd0, 10'd0, EV2, state}; // end of pause cycle
end
//4'd8: begin
// DWR = 1'b1;
// DAD =32'd48;
// DO = {DR, SHIFT, 8'd0, state}; // initial data
// end
//4'd9:
// begin
// DWR = (1'b1 && (!SPCDIS));
// DAD = DAD + 32'd1;
// DO = {DI, SHIFT, 8'd0, state}; // initial data
// end
//4'd10:
// begin
// DWR = (1'b1 && (!SPCDIS));
// DAD = DAD + 32'd1;
// DO = {DOR, OVF2, 7'b0, state}; // end of operation and sending real
// end
//4'd11:
// begin
// DWR = (1'b1 && (!SPCDIS));
// DAD = DAD + 32'd1;
// DO = {DOII, 8'b0, state}; // end of operation and sending real
// end
//4'd12:
// begin
// DWR = (1'b1 && (!SPCDIS));
// DAD = DAD + 32'd1;
// DO = {counter, 18'b0, state}; // pause cycle
// end
//4'd13:
// begin
// DWR = (1'b1 && (!SPCDIS));
// DAD = DAD + 32'd1;
// DO = {28'b0, state}; // end of pause cycle
// end
//4'd14:
// begin
// DWR = 1'b0;
// DAD = DAD ;
// DO = 32'd0;
// end
4'd15:
begin
DWR = (1'b1 && (!SPCDIS));
DAD = DAD + 32'd1;
DO = {ADDR, 21'd0, state} ;
end
endcase
end
end
///**********************************************************///
// DOI, DOR, ADDR at output (no READY) and SHIFT, DR, DI at input
// added signals
wire [nb-1:0] DIA;
wire [nb-1:0] DRA;
wire [3:0] SHIFTA;
wire [nb+3:0] DOIA;
wire [nb+3:0] DORA;
wire [6:0] ADDRA;
// boundary scan signals
wire Scan_en, Hold_en_incell, Hold_en_outcell;
wire test_din, test_dout;
wire Bypass_d, Bypass_q;
wire WIR_din, WIR_2_q, WIR_1_q, WIR_dout;
wire [81:0] CTI; // first DR, DI, SHIFT, ADDR, DOI, DOR
wire CK;
// design
FFT128 U1(CLK, RST, ED, START, SHIFTA, DRA, DIA, RDY, OVF1, OVF2, ADDRA, DORA, DOIA);
debug_FFT F1(CLK, MRST, START, SHIFT, DR, DI, RDY, OVF1, OVF2, ADDR, DOR, DOI, DBus, Sel, EV, Val, TP1, TPE1);
// no need of CLK to be anded with ED (like pause) as ED is an input to the block itself from beginning
// all the boundary scan stuff
assign CK = ((CLK && ED) || SPCDIS);
assign Scan_en = (WRSTN==1'b1) ? ShiftWR : 1'b0;
assign Hold_en_incell = (WRSTN==1'b1) ? 1'b0 : (({WIR_2_q, WIR_1_q, WIR_dout}==3'b010) ? (~CaptureWR) : 1); //WIR==3'b010 EXTEST
assign Hold_en_outcell = (WRSTN==1'b1) ? 1'b0 : (({WIR_2_q, WIR_1_q, WIR_dout}==3'b100) ? 1 : (~CaptureWR)); //WIR==3'b100 INTEST
assign test_din = (WRSTN==1'b1 && Scan_en==1'b1 && SelectWIR==1'b0 && {WIR_2_q, WIR_1_q, WIR_dout}!=3'b001) ? WSI : 1'b0;
assign Bypass_d = (WRSTN==1'b1 && Scan_en==1'b1 && SelectWIR==1'b0 && {WIR_2_q, WIR_1_q, WIR_dout}==3'b001) ? WSI : 1'b0; //WIR==3'b001 BYPASS
assign WIR_din = (WRSTN==1'b1 && Scan_en==1'b1 && SelectWIR==1'b1) ? WSI : 1'b0; //WIR==3'b001 BYPASS
assign WSO = (~WRSTN) ? 1'b0 : (SelectWIR ? WIR_dout : (({WIR_2_q, WIR_1_q, WIR_dout}==3'b001) ? Bypass_q : test_dout));
//Bypass Register
dff dff_bypass(.CK(CK), .Q(Bypass_q), .D(Bypass_d));
//WIR
dff dff_WIR_2(.CK(CK), .Q(WIR_2_q), .D(WIR_din));
dff dff_WIR_1(.CK(CK), .Q(WIR_1_q), .D(WIR_2_q));
dff dff_WIR_0(.CK(CK), .Q(WIR_dout), .D(WIR_1_q));
// connecting the wrapper boundary registers
// connecting the wrapper boundary registers
WBC WBC_I1(.clk(CK), .CTI(test_din), .CFI(DR[0]), .Scan_en(Scan_en), .Hold_en(Hold_en_incell), .CTO(CTI[0]), .CFO(DRA[0]));
genvar i;
generate
for (i = 0; i<15; i=i+1)
begin
WBC WBC_DR(.clk(CK), .CTI(CTI[i]), .CFI(DR[i+1]), .Scan_en(Scan_en), .Hold_en(Hold_en_incell), .CTO(CTI[i+1]), .CFO(DRA[i+1]));
end
endgenerate
generate
for (i = 0; i<16; i=i+1)
begin
WBC WBC_DI(.clk(CK), .CTI(CTI[i+15]), .CFI(DI[i]), .Scan_en(Scan_en), .Hold_en(Hold_en_incell), .CTO(CTI[i+1+15]), .CFO(DIA[i]));
end
endgenerate
generate
for (i = 0; i<4; i=i+1)
begin
WBC WBC_SHIFT(.clk(CK), .CTI(CTI[i+31]), .CFI(SHIFT[i]), .Scan_en(Scan_en), .Hold_en(Hold_en_incell), .CTO(CTI[i+1+31]), .CFO(SHIFTA[i]));
end
endgenerate
generate
for (i = 0; i<7; i=i+1)
begin
WBC WBC_ADDR(.clk(CK), .CTI(CTI[i+35]), .CFI(ADDRA[i]), .Scan_en(Scan_en), .Hold_en(Hold_en_outcell), .CTO(CTI[i+1+35]), .CFO(ADDR[i]));
end
endgenerate
generate
for (i = 0; i<20; i=i+1)
begin
WBC WBC_DOI(.clk(CK), .CTI(CTI[i+42]), .CFI(DOIA[i]), .Scan_en(Scan_en), .Hold_en(Hold_en_outcell), .CTO(CTI[i+1+42]), .CFO(DOI[i]));
end
endgenerate
generate
for (i = 0; i<19; i=i+1)
begin
WBC WBC_DOR(.clk(CK), .CTI(CTI[i+62]), .CFI(DORA[i]), .Scan_en(Scan_en), .Hold_en(Hold_en_outcell), .CTO(CTI[i+1+62]), .CFO(DOR[i]));
end
endgenerate
WBC WBC_O1(.clk(CK), .CTI(CTI[81]), .CFI(DORA[19]), .Scan_en(Scan_en), .Hold_en(Hold_en_outcell), .CTO(test_dout), .CFO(DOR[19]));
endmodule
// 2:1 MUX
module MUX (sel, in0, in1, out);
input sel, in0, in1;
output out;
assign out = sel? in1 : in0;
endmodule
// Wrapper boundary cell
module WBC (clk, CTI, CFI, Scan_en, Hold_en, CTO, CFO);
input clk, CTI, CFI, Scan_en, Hold_en;
output CTO, CFO;
wire DIN;
MUX MUX_in(.sel(Scan_en), .in0(CFO), .in1(CTI), .out(DIN));
MUX MUX_out(.sel(Hold_en), .in0(CFI), .in1(CTO), .out(CFO));
dff dff_1(.CK(clk), .Q(CTO), .D(DIN));
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Stage of FFT 128 processor
// FUNCTION: 16-point FFT
// FILES: FFT16.v - stage, contains
// MPUC707.v - multiplier to the factor 0.707.
// MPUC541.v - multiplier to the factor 0.541.
// MPUC1307.v - multiplier to the factor 1.307.
// MPUC924_383.v - multiplier to the factors 0.924 and 0.383.
// PROPERTIES: 1) Fully pipelined
// 2) Each clock cycle complex datum is entered
// and complex result is outputted
// 3) Has 16-clock cycle period starting with the START impulse
// and continuing forever
// 4) rounding is not used
// 5)Algorithm is from the book "H.J.Nussbaumer FFT and convolution algorithms".
// 6)IFFT is performed by substituting the output result order to the reversed one
// (by exchanging - to + and + to -)
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//Algorithm:
///procedure FFT16(
// X: in MEMOC; --
// y:out MEMOC) --
// is
// variable t1,t2,t3,t4,t5,t6,t7,t8,t9,t10: complex;
// variable t11,t12,t13,t14,t15,t16,t17,t18,t19,t20: complex;
// variable t21,t22,t23,t24,t25,t26: complex;
// variable m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10: complex;
// variable m11,m12,m13,m14,m15,m16,m17: complex;
// variable s1,s2,s3,s4,s5,s6,s7,s8,s9,s10: complex;
// variable s11,s12,s13,s14,s15,s16,s17,s18,s19,s20: complex;
// begin
// t1:=x(0) + x(8); m4:=x(0) - x(8);
// t2:=x(4) + x(12); m12:=-CBASE_j*(x(4)-x(12));
// t3:=x(2) + x(10); t4:=x(2) - x(10);
// t5:=x(6) + x(14); t6:=x(6) - x(14);
// t7:=x(1) + x(9); t8:=x(1) - x(9);
// t9:=x(3) + x(11); t10:=x(3) - x(11);
// t11:=x(5) + x(13); t12:=x(5) - x(13);
// t13:=x(7) + x(15); t14:=x(7) - x(15);
// t15:=t1 + t2; m3:= t1 - t2;
// t16:=t3 + t5; m11:= -CBASE_j*(t3 - t5);
// t17:=t15 + t16; m2:= t15 - t16;
// t18:=t7 + t11; t19:= t7 - t11;
// t20:=t9 + t13; t21:= t9 - t13;
// t22:=t18 + t20; m10:= -CBASE_j*(t18 - t20);
// t23:=t8 + t14; t24:= t8 - t14;
// t25:=t12 + t10; t26:= t12 - t10;
//
// m0:=t17 + t22; m1:=t17 - t22;
// m13:=-CBASE_j*c707*(t19 + t21); m5:=c707*(t19 - t21);
// m6:=c707*(t4 - t6); m14:=-CBASE_j*c707*(t4 + t6);
//
// m7:=c3*(t24+t26);
// m8:=c13*(t24);
// m9:=-s1_3*(t26);
// s7:= m8 - m7;
// s8:= m9 - m7;
//
// m15:=-CBASE_j*c1*(t23 + t25);
// m16:= -CBASE_j*s1_3*(t23);
// m17:=-CBASE_j*c13*(t25);
// s15:= m15 - m16;
// s16:= m15 - m17;
//
// s1:=m3 + m5; s2:=m3 - m5;
// s3:=m13 + m11; s4:=m13 - m11;
// s5:=m4 + m6; s6:=m4 - m6;
// s9:=s5 + s7; s10:=s5 - s7;
// s11:=s6 + s8; s12:=s6 - s8;
// s13:=m12 + m14; s14:=m12 - m14;
// s17:=s13 + s15; s18:=s13 - s15;
// s19:=s14 + s16; s20:=s14 - s16;
//
// y(0):=m0; y(8):=m1;
// y(1):=s9 + s17; y(15):=s9 - s17;
// y(2):=s1 + s3; y(14):=s1 - s3;
// y(3):=s12 - s20; y(13):=s12 + s20;
// y(4):=m2 + m10; y(12):=m2 - m10;
// y(5):=s11 + s19; y(11):=s11 - s19;
// y(6):=s2 + s4; y(10):=s2 - s4;
// y(7):=s10 - s18; y(9):=s10 + s18;
// end procedure;
//
`timescale 1ns / 1ps
`include "FFT128_CONFIG.inc"
module FFT16 ( DOR ,DII ,RST ,ED ,CLK ,DOI ,START ,DIR ,RDY );
`FFT128paramnb
input ED ; //slowdown impulse
wire ED ;
input RST ;
wire RST ;
input CLK ;
wire CLK ;
input [nb-1:0] DII ;
wire [nb-1:0] DII ;
input START ;
wire START ;
input [nb-1:0] DIR ;
wire [nb-1:0] DIR ;
output [nb+3:0] DOI ;
wire [nb+3:0] DOI ;
output [nb+3:0] DOR ;
wire [nb+3:0] DOR ;
output RDY ;
reg RDY ;
reg [3:0] ct; //main phase counter
reg [5:0] ctd; //delay counter
always @( posedge CLK) begin //Control counter
//
if (RST) begin
ct<=0;
ctd<=63;
RDY<=0; end
else if (START) begin
ct<=0;
ctd<=0;
RDY<=0; end
else if (ED) begin
RDY<=0;
ct<=ct+1;
if (ctd !=6'b111111)
ctd<=ctd+1;
if (ctd==44-16 )
RDY<=1;
end
end
reg signed [nb-1: 0] dr,d1r,d2r,d3r,d4r,d5r,d6r,d7r,d8r,di,d1i,d2i,d3i,d4i,d5i,d6i,d7i,d8i;
always @(posedge CLK) // input register file
begin
if (ED) begin
dr<=DIR;
d1r<=dr; d2r<=d1r; d3r<=d2r;d4r<=d3r;
d5r<=d4r;d6r<=d5r; d7r<=d6r; d8r<=d7r;
di<=DII;
d1i<=di; d2i<=d1i; d3i<=d2i; d4i<=d3i;
d5i<=d4i; d6i<=d5i;d7i<=d6i; d8i<=d7i;
end
end
reg signed [nb:0] s1r,s1d1r,s1d2r,s1d3r,s1d4r,s1d5r,s1d6r,s1d7r,s1d8r; //even result sums
reg signed [nb:0] s1i,s1d1i,s1d2i,s1d3i,s1d4i,s1d5i,s1d6i,s1d7i,s1d8i; //even result sums
reg signed [nb:0] s2r,s2d1r,s2d2r,s2d3r,s2d4r,s2d5r,s2d6r,s2d7r,s2d8r,m4_12r; //odd result sums
reg signed [nb:0] s2i,s2d1i,s2d2i,s2d3i,s2d4i,s2d5i,s2d6i,s2d7i,s2d8i,m4_12i; //odd result sums
always @(posedge CLK) begin // S1,S2 =t1-t14,m4,m12' and delayed
if (ED && ((ct==9) || (ct==10) || (ct==11) ||(ct==12) ||
(ct==13) || (ct==14) ||(ct==15) || (ct==0))) begin
s1r<=d8r + dr ;
s1i<=d8i + di ;
s2r<=d8r - dr ;
s2i<= d8i - di;
end
if (ED) begin //delayed results
s1d1r<=s1r; s1d2r<=s1d1r; s1d1i<=s1i; s1d2i<=s1d1i;
s1d3r<=s1d2r; s1d3i<=s1d2i; s1d4r<=s1d3r; s1d4i<=s1d3i;
s1d5r<=s1d4r; s1d5i<=s1d4i; s1d6r<=s1d5r; s1d6i<=s1d5i;
s1d7r<=s1d6r; s1d7i<=s1d6i; s1d8r<=s1d7r; s1d8i<=s1d7i;
s2d1r<=s2r; s2d2r<=s2d1r; s2d1i<=s2i; s2d2i<=s2d1i;
s2d3r<=s2d2r; s2d3i<=s2d2i; s2d4r<=s2d3r; s2d4i<=s2d3i;
s2d5r<=s2d4r; s2d5i<=s2d4i; s2d6r<=s2d5r; s2d6i<=s2d5i;
s2d7r<=s2d6r; s2d7i<=s2d6i; s2d8r<=s2d7r; s2d8i<=s2d7i;
if (ct==2) begin
m4_12r<=s2d8r; m4_12i<=s2d8i; end
else if (ct==6) begin
m4_12r<=s2d8i; m4_12i<= 0 - s2d8r;
end
end
end
///////////////////////////////////////////
//arm of even result calculations
////////////////////////////////////////////
reg signed [nb+1:0] s3r,s3d1r,s3d2r,s3d3r,s3d4r,s3d5r,s3d6r;
reg signed [nb+1:0] s3i,s3d1i,s3d2i,s3d3i,s3d4i,s3d5i,s3d6i;
always @(posedge CLK) begin //ALU S3:
if (ED) begin
case (ct)
14 ,15 : begin s3r<= s1d4r+s1r; //t15 //t18
s3i<= s1d4i+ s1i ;end
0 ,1 : begin s3r<= s1d6r - s1d2r; //m3, t19
s3i<= s1d6i - s1d2i ;end
2 ,3 : begin s3r<= s1d6r +s1d2r; //t16 ,t20
s3i<= s1d6i+ s1d2i ; end
4 ,5 : begin s3r<= s1d8r - s1d4r; // m11',t21
s3i<= s1d8i - s1d4i ; end
endcase
s3d1r<=s3r; s3d1i<=s3i; s3d2r<=s3d1r; s3d2i<=s3d1i;
s3d3r<=s3d2r; s3d3i<=s3d2i; s3d4r<=s3d3r; s3d4i<=s3d3i;
s3d5r<=s3d4r; s3d5i<=s3d4i; s3d6r<=s3d5r; s3d6i<=s3d5i;
end
end
reg signed [nb+2:0] s4r,s4d1r,s4d2r,s4d3r,s4d4r,s4d5r,s4d6r,s4d7r,m3r;
reg signed [nb+2:0] s4i,s4d1i,s4d2i,s4d3i,s4d4i,s4d5i,s4d6i,s4d7i,m3i;
always @ (posedge CLK) begin // S4
if (ED) begin
if ((ct==3) | (ct==4)) begin
s4r<= s3d4r + s3r; //t17 ,t22
s4i<= s3d4i + s3i; end
else if ((ct==5) | (ct==6) | (ct==8) ) begin
s4r<=s3d6r - s3d2r; //m2,m10', m5'
s4i<= s3d6i - s3d2i; end
else if (ct==7) begin
s4r<=s3d1r + s3d5r; //m13
s4i<= s3d1i + s3d5i;
end
s4d1r<=s4r; s4d1i<=s4i; s4d2r<=s4d1r; s4d2i<=s4d1i;
s4d3r<=s4d2r; s4d3i<=s4d2i; s4d4r<=s4d3r; s4d4i<=s4d3i;
s4d5r<=s4d4r; s4d5i<=s4d4i; s4d6r<=s4d5r; s4d6i<=s4d5i;
s4d7r<=s4d6r; s4d7i<=s4d6i;
if (ct==7) begin
m3r<=s3d6r; //m3
m3i<=s3d6i; end
end
end
wire em707,mpyj7;
assign em707 = ((ct==8) || (ct==10 )||(ct==1) || (ct==5)); //control signals for the multiplier
assign mpyj7 = ((ct==8) || (ct==5));
reg signed [nb+2:0] s7r,s7d1r;
reg signed [nb+2:0] s7i,s7d1i;
wire signed [nb+2:0] m707r,m707i,m70r,m70i;
assign m70r = ((ct==1) || (ct==5))? s7r :s4r; //multiplexor at the multiplier input
assign m70i = ((ct==1) || (ct==5))? s7i :s4i;
MPUC707 #(nb+3) UM707( .CLK(CLK),.ED(ED),.DS(em707), .MPYJ(mpyj7), //multiplier by 0.707
.DR(m70r),.DI(m70i) ,.DOR(m707r) ,.DOI(m707i));
reg signed [nb+2:0] s3jr,s3ji, m10r,m10i;
always @ (posedge CLK) begin //multiply by J
if (ED) begin
case (ct)
11: begin s3jr<= s3d6i; //m11
s3ji<=0 - s3d6r; end
14: begin s3jr<= s4d7i; //m10
s3ji<=0 - s4d7r; end
endcase
if (ct==1) begin
m10r<=s3jr; //m10
m10i<=s3ji;
end
end
end
reg signed [nb+3:0] s5r,s5d1r,s5d2r,s5d3r,s5d4r,s5d5r,s5d6r,s5d7r,s5d8r,s5d9r, s5d10r,m2r,m2dr;
reg signed [nb+3:0] s5i,s5d1i,s5d2i,s5d3i,s5d4i,s5d5i,s5d6i,s5d7i,s5d8i,s5d9i,s5d10i,m2i,m2di;
always @ (posedge CLK) // S5:
if (ED) begin
case (ct)
10: begin s5r<=s4d5r + s4d6r; //m0
s5i<=s4d5i + s4d6i; end
11: begin s5r<=s4d7r - s4d6r; //m1
s5i<=s4d7i - s4d6i; end
12: begin s5r<=m707r + s3jr; //S3
s5i<= m707i+s3ji;end
13: begin s5r<=m707r - s3jr; //S4
s5i<= m707i - s3ji;end
14: begin s5r<= m3r+m707r; //S1
s5i<= m3i+m707i ;end
15: begin s5r<=m3r-m707r ; //S2
s5i<= m3i -m707i ;end
6: begin //S2
s5d10r<=s5d9r ; //S2
s5d10i<=s5d9i ;end
endcase
if ((ct==4)||(ct==5)||(ct==6)||(ct==7)) begin
s5d9r<=s5d8r ; s5d9i<=s5d8i ; end
s5d1r<=s5r; s5d1i<=s5i; s5d2r<=s5d1r; s5d2i<=s5d1i;
s5d3r<=s5d2r; s5d3i<=s5d2i; s5d4r<=s5d3r; s5d4i<=s5d3i;
s5d5r<=s5d4r; s5d5i<=s5d4i; s5d6r<=s5d5r; s5d6i<=s5d5i;
s5d7r<=s5d6r; s5d7i<=s5d6i; s5d8r<=s5d7r; s5d8i<=s5d7i;
if (ct==13) begin
m2r<=s4d7r; m2i<=s4d7i; end
if (ct==1) begin
m2dr<=m2r; m2di<=m2i; end
end
reg signed [nb+3:0] s6r,s6i ;
`ifdef FFT128paramifft // For IFFT
always @ (posedge CLK) begin // S6-- result adder
if (ED)
case (ct)
13: begin s6r<=s5d2r; // -- Y0
s6i<=(s5d2i);end //-- Y0
15: begin
s6r<=s5d2r - s5r ; //Y2
s6i<=s5d2i - s5i ; end
1: begin
s6r<=m2r - s3jr ; //Y4
s6i<=m2i - s3ji ; end
3: begin
s6r<=s5d3r - s5d5r ; //Y6
s6i<= s5d3i -s5d5i ; end
5:begin s6r<=(s5d9r) ; //-- Y8
s6i<=(s5d9i) ; end
7: begin
s6r<= s5d7r + s5d9r ; // Y10
s6i<= s5d7i + s5d9i ; end
9: begin // Y12
s6r<=m2dr +m10r ;
s6i<=m2di + m10i ;
end
11: begin // Y14
s6r<= s5d9r + s5d10r ;
s6i<= s5d9i + s5d10i ;
end
endcase
end
`else
always @ (posedge CLK) begin // S6-- result adder
if (ED)
case (ct)
13: begin s6r<=s5d2r; // -- Y0
s6i<=s5d2i;end //-- Y0
15: begin
s6r<=s5d2r + s5r ; //Y2
s6i<=s5d2i + s5i ; end
1: begin
s6r<=m2r + s3jr ; //Y4
s6i<=m2i + s3ji ; end
3: begin
s6r<=s5d3r + s5d5r ; //Y6
s6i<= s5d3i +s5d5i ; end
5:begin s6r<=s5d9r; //-- Y8
s6i<=s5d9i; end
7: begin
s6r<= s5d7r - s5d9r ; // Y10
s6i<= s5d7i - s5d9i ; end
9: begin // Y12
s6r<=m2dr -m10r ;
s6i<=m2di - m10i ;
end
11: begin // Y14
s6r<= s5d9r - s5d10r ;
s6i<= s5d9i - s5d10i ;
end
endcase
end
`endif
///////////////////////////////////////////////////////////
//arm of odd result calculations
//////////////////////////////////////////////////////////
always @(posedge CLK) begin //ALU S7:
if (ED)
case (ct)
15:begin s7r<= s2d2r-s2r; //t26
s7i<= s2d2i- s2i ;end
0: begin s7r<= s2d4r-s2r; //m6'
s7i<= s2d4i- s2i ;
s7d1r<=s7r;
s7d1i<=s7i;end
1: begin s7r<= s2d6r - s2r; //t24
s7i<= s2d6i - s2i; end
2: begin s7r<= s7r -s7d1r; //m7'
s7i<= s7i- s7d1i ; end
3: begin s7r<= s2d8r + s2d2r; // t23
s7i<= s2d8i + s2d2i ; end
4: begin s7r<= s2d8r + s2d4r; // m14'
s7i<= s2d8i + s2d4i ;
s7d1r<=s7r;
s7d1i<=s7i;end
5: begin s7r<= s2d8r + s2d6r; // t25
s7i<= s2d8i + s2d6i ; end
6: begin s7r<= s7r + s7d1r; //m15'
s7i<= s7i + s7d1i ; end
endcase
end
wire em541,mpyj541;
wire signed [nb+2:0] m541r,m541i;
assign em541 = ((ct==0) || (ct==4)); //control signals for the multiplier
assign mpyj541 = ((ct==4));
MPUC541 #(nb+3) UM541( .CLK(CLK),.ED(ED),.DS(em541), .MPYJ(mpyj541), //multiplier by 0.383
.DR(s7r),.DI(s7i) ,.DOR(m541r) ,.DOI(m541i));
wire em1307,mpyj1307;
wire signed [nb+2:0] m1307r,m1307i;
assign em1307 = ((ct==2) || (ct==6)); //control signals for the multiplier
assign mpyj1307 = ((ct==6));
MPUC1307 #(nb+3) UM1307( .CLK(CLK),.ED(ED),.DS(em1307), .MPYJ(mpyj1307), //multiplier by 1.306
.DR(s7r),.DI(s7i) ,.DOR(m1307r) ,.DOI(m1307i));
wire em383,mpyj383,c383;
wire signed [nb+2:0] m383r,m383i;
assign em383 = ((ct==3) || (ct==7)); //control signals for the multiplier
assign mpyj383 = ((ct==7));
assign c383 = (ct==3);
MPUC924_383 #(nb+3) UM383(.CLK(CLK),.ED(ED),.DS(em383),.MPYJ(mpyj383),.C383(c383), //multiplier by 0.383
.DR(s7r),.DI(s7i) ,.DOR(m383r) ,.DOI(m383i));
reg signed [nb+2:0] m8_17r,m8_17i,m9_16r,m9_16i;
always @(posedge CLK) begin //Reg-s
if (ED) begin
if (ct==4 || ct==8) begin
m9_16r<=m541r; //M9_ M16
m9_16i<=m541i;
end
if ( ct==6 || ct==10) begin
m8_17r<=m1307r; //M8_ M17
m8_17i<=m1307i;
end
end
end
reg signed [nb+2:0] s8r,s8i,s8d1r,s8d2r,s8d3r,s8d4r,s8d1i,s8d2i,s8d3i,s8d4i ;
always @ (posedge CLK) begin // S8-- adder
if (ED)
case (ct)
5,9: begin s8r<=m4_12r +m707r ; // -- S5 S13
s8i<=m4_12i +m707i ;end //--
6,10: begin
s8r<=m4_12r - m707r ; // -- S6 , S14
s8i<=m4_12i - m707i ; end
7: begin
s8r<=m8_17r - m383r ; // -- S7 ,S15
s8i<=m8_17i -m383i ; end
8: begin
s8r<=m9_16r - m383r ; // -- S8 , S16
s8i<=m9_16i -m383i ; end
11: begin
s8r<=m383r - m9_16r ; // -- S7 ,S15
s8i<=m383i - m9_16i; end
12: begin
s8r<=m383r - m8_17r; // -- S8 , S16
s8i<=m383i - m8_17i; end
endcase
s8d1r<=s8r; s8d1i<=s8i; s8d2r<=s8d1r; s8d2i<=s8d1i;
s8d3r<=s8d2r; s8d3i<=s8d2i; s8d4r<=s8d3r; s8d4i<=s8d3i;
end
reg signed [nb+3:0] s9r,s9d1r,s9d2r,s9d3r,s9d4r,s9d5r,s9d6r,s9d7r,s9d8r,s9d9r, s9d10r,s9d11r,s9d12r,s9d13r;
reg signed [nb+3:0] s9i,s9d1i,s9d2i,s9d3i,s9d4i,s9d5i,s9d6i,s9d7i,s9d8i,s9d9i,s9d10i,s9d11i,s9d12i,s9d13i;
always @ (posedge CLK) // ALU s9:
if (ED) begin
case (ct)
8,9,12: begin s9r<= s8r + s8d2r; // S9,S11 , S17
s9i<=s8i + s8d2i ; end
13: begin s9r<= s8d2r - s8r; // S20
s9i<=s8d2i - s8i ; end
10,11,14: begin s9r<=s8d4r - s8d2r; //S10, S12,S18
s9i<=s8d4i - s8d2i; end
15: begin s9r<=s8d4r + s8d2r; //S19
s9i<=s8d4i + s8d2i; end
endcase
s9d1r<=s9r; s9d1i<=s9i; s9d2r<=s9d1r; s9d2i<=s9d1i;
s9d3r<=s9d2r; s9d3i<=s9d2i; s9d4r<=s9d3r; s9d4i<=s9d3i;
s9d5r<=s9d4r; s9d5i<=s9d4i; s9d6r<=s9d5r; s9d6i<=s9d5i;
s9d7r<=s9d6r; s9d7i<=s9d6i; s9d8r<=s9d7r; s9d8i<=s9d7i;
s9d9r<=s9d8r ; s9d9i<=s9d8i ;
if ((ct!=8)) begin
s9d10r<=s9d9r ; s9d10i<=s9d9i ;
s9d11r<=s9d10r ; s9d11i<=s9d10i ; end
if ((ct==4) ||(ct==5) ||(ct==7) ||(ct==9) ) begin
s9d12r<=s9d11r ; s9d12i<=s9d11i ; end
if ((ct==5))begin
s9d13r<=s9d12r ; s9d13i<=s9d12i ; end
end
reg signed [nb+3:0] s10r,s10i;
reg signed [nb+3:0] s10dr,s10di;
`ifdef FFT256paramifft //For IFFT
always @ (posedge CLK) begin // S10-- result adder
if (ED)
case (ct)
13: begin s10r<=s9d4r -s9r ; // -- Y1
s10i<=s9d4i -s9i ;end //
15: begin
s10r<=s9d3r + s9d1r ; //-- Y3
s10i<=s9d3i + s9d1i ; end
1: begin
s10r<=s9d7r - s9d1r ; //-- Y5
s10i<=s9d7i - s9d1i ; end
3: begin
s10r<=s9d8r + s9d4r ; // -- Y7
s10i<= s9d8i + s9d4i ;end
5:begin s10r<=s9d10r - s9d6r ; //-- Y9
s10i<=s9d10i - s9d6i ; end
7: begin
s10r<=s9d12r + s9d7r ; //-- Y11
s10i<=s9d12i + s9d7i ; end
9: begin
s10r<= s9d12r - s9d10r ; // Y13
s10i<=s9d12i - s9d10i ; end
11: begin
s10r<= s9d13r + s9d12r ; // Y15
s10i<= s9d13i + s9d12i ; end
endcase
s10dr<=s10r; s10di<=s10i;
end
`else
// reg signed [nb+3:0] s10r,s10i,s10dr,s10di;
always @ (posedge CLK) begin // S10-- result adder
if (ED)
case (ct)
13: begin s10r<=s9d4r +s9r ; // -- Y0
s10i<=s9d4i +s9i ;end //
15: begin
s10r<=s9d3r - s9d1r ; //-- Y3
s10i<=s9d3i - s9d1i ; end
1: begin
s10r<=s9d7r +s9d1r ; //-- Y5
s10i<=s9d7i +s9d1i ; end
3: begin
s10r<=s9d8r - s9d4r ; // -- Y7
s10i<= s9d8i - s9d4i ;end
5:begin s10r<=s9d10r + s9d6r ; //-- Y9
s10i<=s9d10i + s9d6i ; end
7: begin
s10r<=s9d12r - s9d7r ; //-- Y11
s10i<=s9d12i - s9d7i ; end
9: begin
s10r<= s9d12r + s9d10r ; // Y13
s10i<=s9d12i + s9d10i ; end
11: begin
s10r<= s9d13r - s9d12r ; // Y15
s10i<= s9d13i - s9d12i ; end
endcase
s10dr<=s10r; s10di<=s10i;
end
`endif
//wire signed [nb+3:0] s6sr,s6si; //saturation of results
// assign s6sr = (~s6r[nb+4]&&s6r[nb+3])? ((1'b1 <<(nb+3))-1) : s6r[nb+3:0];
// assign s6si = (~s6i[nb+4]&&s6i[nb+3])? ((1'b1<<(nb+3))-1) : s6i[nb+3:0];
//
wire selo;
assign selo = ct-(ct/2)*2;
assign #1 DOR=selo? s10dr:s6r;
assign #1 DOI= selo? s10di:s6i;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : First stage of FFT 128 processor
// FUNCTION: 8-point FFT
// FILES: FFT8_3.v - 1-st stage, contains
// MPUC707.v - multiplier to the factor 0.707.
// PROPERTIES: 1) Fully pipelined
// 2) Each clock cycle complex datum is entered
// and complex result is outputted
// 3) Has 8-clock cycle period starting with the START impulse
// and continuing forever
// 4) rounding is not used
// 5)Algorithm is from the book "H.J.Nussbaumer FFT and convolution algorithms".
// 6)IFFT is performed by substituting the output result order to the reversed one
// (by exchanging - to + and + to -)
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//Algorithm:
// procedure FFT8(
// D: in MEMOC8; -- input array
// DO:out MEMOC8) -- output ARRAY
// is
// variable t1,t2,t3,t4,t5,t6,t7,t8,m0,m1,m2,m3,m4,m5,m6,m7: complex;
// variable s1,s2,s3,s4: complex;
// begin
// t1:=D(0) + D(4);
// m3:=D(0) - D(4);
// t2:=D(6) + D(2);
// m6:=CBASE_j*(D(6)-D(2));
// t3:=D(1) + D(5);
// t4:=D(1) - D(5);
// t5:=D(3) + D(7);
// t6:=D(3) - D(7);
// t8:=t5 + t3;
// m5:=CBASE_j*(t5-t3);
// t7:=t1 + t2;
// m2:=t1 - t2;
// m0:=t7 + t8;
// m1:=t7 - t8;
// m4:=SQRT(0.5)*(t4 - t6);
// m7:=-CBASE_j*SQRT(0.5)*(t4 + t6);
// s1:=m3 + m4;
// s2:=m3 - m4;
// s3:=m6 + m7;
// s4:=m6 - m7;
// DO(0):=m0;
// DO(4):=m1;
// DO(1):=s1 + s3;
// DO(7):=s1 - s3;
// DO(2):=m2 + m5;
// DO(6):=m2 - m5;
// DO(5):=s2 + s4;
// DO(3):=s2 - s4;
// end procedure;
//
// Note that MPUC707 is multiplied a complex data for 2 clk cycles
//_____________________________________________________________
`timescale 1ps / 1ps
`include "FFT128_CONFIG.inc"
module FFT8 ( DOR ,DII ,RST ,ED ,CLK ,DOI ,START ,DIR ,RDY );
`FFT128paramnb
input ED ;
wire ED ;
input RST ;
wire RST ;
input CLK ;
wire CLK ;
input [nb-1:0] DII ;
wire [nb-1:0] DII ;
input START ;
wire START ;
input [nb-1:0] DIR ;
wire [nb-1:0] DIR ;
output [nb+2:0] DOI ;
wire [nb+2:0] DOI ;
output [nb+2:0] DOR ;
wire [nb+2:0] DOR ;
output RDY ;
reg RDY ;
reg [2:0] ct; //main phase counter
reg [4:0] ctd; //delay counter
always @( posedge CLK) begin //Control counter
//
if (RST) begin
ct<=0;
ctd<=16;
RDY<=0; end
else if (START) begin
ct<=0;
ctd<=0;
RDY<=0; end
else if (ED) begin
RDY<=0;
ct<=ct+1;
if (ctd !=5'b10000)
ctd<=ctd+1;
if (ctd==15 )
RDY<=1;
end
end
reg signed [nb-1: 0] dr,d1r,d2r,d3r,d4r,di,d1i,d2i,d3i,d4i;
always @(posedge CLK) // input register file
begin
if (ED) begin
dr<=DIR;
d1r<=dr;
d2r<=d1r;
d3r<=d2r;
d4r<=d3r;
di<=DII;
d1i<=di;
d2i<=d1i;
d3i<=d2i;
d4i<=d3i;
end
end
reg signed [nb:0] s1r,s2r,s1d1r,s1d2r,s1d3r,s2d1r,s2d2r,s2d3r,m3r;
reg signed [nb:0] s1i,s2i,s1d1i,s1d2i,s1d3i,s2d1i,s2d2i,s2d3i,m3i;
always @(posedge CLK) begin // S1,S2 =t1-t6,m3 and delayed
if (ED && ((ct==5) || (ct==6) || (ct==7) || (ct==0))) begin
s1r<=d4r + dr ;
s1i<=d4i + di ;
s2r<=d4r - dr ;
s2i<= d4i - di;
end
if (ED) begin
s1d1r<=s1r;
s1d2r<=s1d1r;
s1d1i<=s1i;
s1d2i<=s1d1i;
if (ct==0 || ct==1) begin //## note for vhdl
s1d3r<=s1d2r;
s1d3i<=s1d2i;
end
if (ct==6 || ct==7 || ct==0) begin
s2d1r<=s2r;
s2d2r<=s2d1r;
s2d1i<=s2i;
s2d2i<=s2d1i;
end
if (ct==0) begin
s2d3r<=s2d2r;
s2d3i<=s2d2i;
end
if (ct==7) begin
m3r<=s2d3r;
m3i<=s2d3i;
end
end
end
reg signed [nb+1:0] s3r,s4r,s3d1r,s3d2r,s3d3r,s3d4r,s3d5r,s3d6r,s3d7r;
reg signed [nb+1:0] s3i,s4i,s3d1i,s3d2i,s3d3i,s3d4i,s3d5i,s3d6i,s3d7i;
always @(posedge CLK) begin //ALU S3:
if (ED)
case (ct)
0: begin s3r<= s1d2r+s1r; //t7
s3i<= s1d2i+ s1i ;end
1: begin s3r<= s1d3r - s1d1r; //m2
s3i<= s1d3i - s1d1i; end
2: begin s3r<= s1d3r +s1r; //t8
s3i<= s1d3i+ s1i ; end
3: begin s3r<= s1d3r - s1r; //
s3i<= s1d3i - s1i ; end
endcase
s3d1r<=s3r; s3d1i<=s3i;
s3d2r<=s3d1r; s3d2i<=s3d1i;
s3d3r<=s3d2r; s3d3i<=s3d2i;
if (ct==4 || ct==5 || ct==6|| ct==7) begin
s3d4r<=s3d3r; s3d4i<=s3d3i;
s3d5r<=s3d4r; s3d5i<=s3d4i; //t8
end
if ( ct==6|| ct==7) begin
s3d6r<=s3d5r; s3d6i<=s3d5i; //m2
s3d7r<=s3d6r; s3d7i<=s3d6i; //t7
end
end
always @ (posedge CLK) begin // S4
if (ED) begin
if (ct==1) begin
s4r<= s2d2r + s2r;
s4i<= s2d2i + s2i; end
else if (ct==2) begin
s4r<=s2d2r - s2r;
s4i<= s2d2i - s2i;
end
end
end
wire ds,mpyj;
assign ds = (ct==2 || ct==4 );
assign mpyj = (ct==2); // the multiplication by 0707 is followed by *J
wire signed [nb+1:0] m4m7r,m4m7i;
MPUC707 #(nb+2) UM707(.CLK(CLK),.ED(ED), .DS(ds), .MPYJ(mpyj) ,
.DR(s4r),.DI(s4i),
.DOR(m4m7r) ,.DOI(m4m7i) );
reg signed [nb+1:0] sjr,sji, m7r,m7i;
always @ (posedge CLK) begin //multiply by J
if (ED) begin
if (ct==6) begin
m7r<=m4m7r; //m7
m7i<=m4m7i;
end
case (ct)
6: begin sjr<= s2d1i; //m6
sji<=0 - s2d1r; end
1: begin sjr<= s3d4i; //m5
sji<=0 - s3d4r; end
endcase
end
end
reg signed [nb+2:0] s7r,s7i,rs3r,rs3i;
always @ (posedge CLK) // S7:
if (ED)
case (ct)
0:begin s7r<= sjr + m7r;
s7i<= sji + m7i; end
1:begin s7r<= sjr - m7r;
s7i<= sji - m7i;
rs3r<=s7r;
rs3i<=s7i; end
endcase
reg signed [nb+2:0] s5r,rs1r;
reg signed [nb+2:0] s5i,rs1i;
always @ (posedge CLK) // S5:
if (ED)
case (ct)
0:begin s5r<= m3r + m4m7r;
s5i<= m3i + m4m7i; end
1:begin s5r<= m3r - m4m7r;
s5i<= m3i - m4m7i;
rs1r<=s5r;
rs1i<=s5i; end
endcase
reg signed [nb+3:0] s6r,s6i ;
`ifdef FFT128paramifft
always @ (posedge CLK) begin // S6-- result adder
if (ED)
case (ct)
0: begin s6r<=s3d7r +s3d5r ; // -- D0
s6i<=s3d7i +s3d5i ;end //-- D0
1: begin
s6r<=s5r - s7r ; //-- D1
s6i<=s5i - s7i ; end
2: begin
s6r<=s3d6r -sjr ; //-- D2
s6i<=s3d6i -sji ; end
3: begin
s6r<=s5r + s7r ; // -- D3
s6i<= s5i + s7i ;end
4:begin s6r<=s3d7r - s3d5r ; //-- D4
s6i<=s3d7i - s3d5i ; end
5: begin
s6r<=s5r - s7r ; //-- D5
s6i<=s5i - s7i ; end
6: begin
s6r<= s3d6r + sjr ; // D6
s6i<=s3d6i + sji ; end
7: begin
s6r<= rs1r + rs3r ; // D0
s6i<= rs1i + rs3i ; end
endcase
end
`else
always @ (posedge CLK) begin // S6-- result adder
if (ED)
case (ct)
0: begin s6r<=s3d7r +s3d5r ; // -- D0
s6i<=s3d7i +s3d5i ;end //-- D0
1: begin
s6r<=s5r + s7r ; //-- D1
s6i<=s5i + s7i ; end
2: begin
s6r<=s3d6r +sjr ; //-- D2
s6i<=s3d6i +sji ; end
3: begin
s6r<=s5r - s7r ; // -- D3
s6i<= s5i - s7i ;end
4:begin s6r<=s3d7r - s3d5r ; //-- D4
s6i<=s3d7i - s3d5i ; end
5: begin
s6r<=s5r + s7r ; //-- D5
s6i<=s5i + s7i ; end
6: begin
s6r<= s3d6r - sjr ; // D6
s6i<=s3d6i - sji ; end
7: begin
s6r<= rs1r - rs3r ; // D0
s6i<= rs1i - rs3i ; end
endcase
end
`endif
assign #1 DOR=s6r[nb+2:0];
assign #1 DOI= s6i[nb+2:0];
endmodule
|
`include "./dlx.defines"
`timescale 1ns/1ps
// extending it for memory operations (here external represented by E)
module IcacheSP (
PHI1,
MRST,
IAddr,
IIn,
IAddrE,
IInE,
IWriteE
);
parameter WORDS = 128;
input PHI1;
input MRST;
input [`WordSize] IAddr;
output reg[`WordSize] IIn;
input [`WordSize] IAddrE;
input IWriteE;
input [`WordSize] IInE; // IIn and IInE by opposite conventions
//reg [31:0] mem_array[(WORDS - 1):0] = {32'b`//00100000001000010000000000000110,
//32'b`00000000000000000000000000000000,
//32'b`00000000000000000000000000000000,
//32'b`00000000000000000000000000000000,
//32'b`11001100011000010000000000000101};
reg [31:0] mem_array[(WORDS - 1):0];
initial
begin
$readmemb("test11BRANCH3.dat", mem_array);
//$readmemb("test11onlystoreandload.dat", mem_array);
//$readmemb("testSPCinteraction.dat", mem_array);
//$readmemb("testSPCFFT.dat", mem_array);
//$readmemb("testSPCDLX.dat", mem_array);
//$readmemb("testSPCAES.dat", mem_array);
//$readmemb("testSPCinteraction.dat", mem_array);
//$readmemb("testSPCREAD.dat", mem_array);
end
always @(negedge PHI1)
begin
if (MRST == 1'b1)
begin
IIn <= mem_array[IAddr/4];
end
else if (IWriteE == 1'b1)
begin
mem_array[IAddrE] <= IInE;
end
end
endmodule
|
`include "./dlx.defines"
`timescale 1ns/1ps
// extending it for memory operations (here external represented by E)
module Icache (
PHI1,
MRST,
IAddr,
IIn,
IAddrE,
IInE,
IWriteE
);
parameter WORDS = 64;
input PHI1;
input MRST;
input [`WordSize] IAddr;
output reg[`WordSize] IIn;
input [`WordSize] IAddrE;
input IWriteE;
input [`WordSize] IInE; // IIn and IInE by opposite conventions
//reg [31:0] mem_array[(WORDS - 1):0] = {32'b`//00100000001000010000000000000110,
//32'b`00000000000000000000000000000000,
//32'b`00000000000000000000000000000000,
//32'b`00000000000000000000000000000000,
//32'b`11001100011000010000000000000101};
reg [31:0] mem_array[(WORDS - 1):0];
initial
begin
//$readmemb("test11BRANCH.dat", mem_array);
//$readmemb("test11onlystoreandload.dat", mem_array);
// $readmemb("TOPprog.dat", mem_array); // external write to memory
end
always @(negedge PHI1)
begin
if (MRST == 1'b1)
begin
IIn <= mem_array[IAddr/4];
end
else if (IWriteE == 1'b1)
begin
mem_array[IAddrE] <= IInE;
end
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Complex Multiplier by 0.7071
// FUNCTION: Constant multiplier to cos(PI/8)+cos(3*PI/8) =1.307
// FILES: MPU1307.v
// PROPERTIES: 1) Is based on shifts right and add
// 2) for short input bit width 1.307 is approximated as 1_0100_111 = 1_0101_00T
// 3) for medium bit width 1.3066 is approximated as 1_0100_1110_0111_11= 1_0101_00T0_1000_0T
// 4) for long bit width 1.30656 is approximated as 1_0100_1110_0111_1011=1_0101_00T0_1000_0T0T
// 5) hardware is 3 or 5, or 6 adders +1
// 6) MPYJ switches multiply by j
// 6) A complex data is multiplied for 2 cycles, latent delay=4
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`include "FFT128_CONFIG.inc"
module MPUC1307 ( CLK,DS ,ED, MPYJ,DR,DI ,DOR ,DOI, );
`FFT128paramnb
input CLK ;
wire CLK ;
input DS ;
wire DS ;
input ED; //data strobe
input MPYJ ; //the result is multiplied by -j
wire MPYJ ;
input [nb-1:0] DR ;
wire signed [nb-1:0] DR ;
input [nb-1:0] DI ;
wire signed [nb-1:0] DI ;
output [nb:0] DOR ;
reg [nb:0] DOR ;
output [nb:0] DOI ;
reg [nb:0] DOI ;
reg signed [nb+2 :0] dx5;
reg signed [nb-1 :0] dx7;
reg signed [nb-1 :0] dii;
reg signed [nb : 0] dt;
wire signed [nb+3 : 0] dx5p;
wire signed [nb+3 : 0] dot;
reg edd,edd2, edd3; //delayed data enable impulse
reg mpyjd,mpyjd2,mpyjd3;
reg [nb:0] doo ;
reg [nb:0] droo ;
always @(posedge CLK)
begin
if (ED) begin
edd<=DS;
edd2<=edd;
edd3<=edd2;
mpyjd<=MPYJ;
mpyjd2<=mpyjd;
mpyjd3<=mpyjd2; //1_0100_1110_0111_1011
if (DS) begin // 1_0101_00T0_1000_0T0T
dx5<=DR+(DR <<2); //multiply by 5
dx7<=DR-(DR>>>3); //multiply by 7, shifted right to 2
dt<=DR;
dii<=DI;
end
else begin
dx5<=dii+(dii <<2); //multiply by 5
dx7<=dii-(dii>>>3); //multiply by 7, shifted right to 3
dt<=dii;
end
doo<=dot >>>3;
droo<=doo;
if (edd3)
if (mpyjd3) begin
DOR<=doo;
DOI<= - droo; end
else begin
DOR<=droo;
DOI<= doo; end
end
end
assign dx5p=(dx5<<1)+(dx7>>>1); // multiply by 1_0101_00T
`ifdef FFT128bitwidth_coef_high
assign dot= (dx5p+(dt>>>6) -(dx5>>>13));// multiply by 1_0101_00T0_1000_0T0T
`else
assign dot= dx5p+(dt>>>6);
`endif
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Complex Multiplier by 0.5411
// FUNCTION: Constant multiplier to cos(PI/8)-cos(3*PI/8) =0.5411
// FILES: MPU541.v
// PROPERTIES: 1) Is based on shifts right and add
// 2) for short input bit width 0.541 is approximated as 0_1000_1010_1
// 3) for medium bit width 1.3066 is approximated as 0_1000_1010_1001
// 4) for long bit width 1.30656 is approximated as 0_1000_1010_1000_11
// 5) hardware is 3,or4, or 5 adders +1
// 6) MPYJ switches multiply by j
// 6) A complex data is multiplied for 2 cycles, latent delay=4
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`include "FFT128_CONFIG.inc"
module MPUC541 ( CLK,DS ,ED, MPYJ,DR,DI ,DOR ,DOI, );
`FFT128paramnb
input CLK ;
wire CLK ;
input DS ;
wire DS ;
input ED; //data strobe
input MPYJ ; //the result is multiplied by -j
wire MPYJ ;
input [nb-1:0] DR ;
wire signed [nb-1:0] DR ;
input [nb-1:0] DI ;
wire signed [nb-1:0] DI ;
output [nb-1:0] DOR ;
reg [nb-1:0] DOR ;
output [nb-1:0] DOI ;
reg [nb-1:0] DOI ;
reg signed [nb :0] dx5;
reg signed [nb :0] dx3;
reg signed [nb-1 :0] dii;
reg signed [nb-1 : 0] dt;
wire signed [nb+1 : 0] dx5p;
wire signed [nb+1 : 0] dot;
reg edd,edd2, edd3; //delayed data enable impulse
reg mpyjd,mpyjd2,mpyjd3;
reg [nb-1:0] doo ;
reg [nb-1:0] droo ;
always @(posedge CLK)
begin
if (ED) begin
edd<=DS;
edd2<=edd;
edd3<=edd2;
mpyjd<=MPYJ;
mpyjd2<=mpyjd;
mpyjd3<=mpyjd2;
if (DS) begin // 0_1000_1010_1000_11
dx5<=DR+(DR >>>2); //multiply by 5
dx3<=DR+(DR >>>1); //multiply by 3,
dt<=DR;
dii<=DI;
end
else begin
dx5<=dii+(dii >>>2); //multiply by 5
dx3<=dii +(dii >>>1); //multiply by 3
dt<=dii;
end
doo<=dot >>>2;
droo<=doo;
if (edd3)
if (mpyjd3) begin
DOR<=doo;
DOI<= - droo; end
else begin
DOR<=droo;
DOI<= doo; end
end
end
assign dx5p=(dt<<1)+(dx5>>>3); // multiply by 0_1000_101
`ifdef FFT128bitwidth_coef_high
assign dot= (dx5p+(dt>>>7) +(dx3>>>11));// multiply by // 0_1000_1010_1000_11
`else
assign dot= dx5p+(dt>>>7);
`endif
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Complex Multiplier by 0.7071
// FUNCTION: Constant multiplier
// FILES: MPU707.v
// PROPERTIES: 1) Is based on shifts right and add
// 2) for short input bit width 0.7071 is approximated as 10110101 then rounding is not used
// 3) for long input bit width 0.7071 is approximated as 10110101000000101
// 4) hardware is 4 or 5 adders
// 5) MPYJ switches multiply by j
// 6) A complex data is multiplied for 2 cycles
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`include "FFT128_CONFIG.inc"
module MPUC707 ( CLK,ED, DS, MPYJ,DR,DI ,DOR ,DOI, );
`FFT128paramnb
// MPUC707 #(nb+2) UM707(.CLK(CLK),.ED(ED), .DS(es), .MPYJ(mpyj) ,
input CLK ;
wire CLK ;
input DS ; //data strobe
wire DS ;
input ED; //slowdown
input MPYJ ; //the result is multiplied by -j
wire MPYJ ;
input [nb-1:0] DR ;
wire signed [nb-1:0] DR ;
input [nb-1:0] DI ;
wire signed [nb-1:0] DI ;
output [nb-1:0] DOR ;
reg [nb-1:0] DOR ;
output [nb-1:0] DOI ;
reg [nb-1:0] DOI ;
reg signed [nb+1 :0] dx5;
reg signed [nb : 0] dt;
reg signed [nb-1 : 0] dii;
wire signed [nb+2 : 0] dx5p;
wire signed [nb+3 : 0] dot;
reg edd,edd2, edd3; //delayed data enable impulse
reg mpyjd,mpyjd2,mpyjd3;
reg [nb-1:0] doo ;
reg [nb-1:0] droo ;
always @(posedge CLK)
begin
if (ED) begin
edd<=DS;
edd2<=edd;
edd3<=edd2;
mpyjd<=MPYJ;
mpyjd2<=mpyjd;
mpyjd3<=mpyjd2;
if (DS) begin
dx5<=DR+(DR <<2); //multiply by 5
dt<=DR;
dii<=DI;
end
else begin
dx5<=dii+(dii <<2); //multiply by 5
dt<=dii;
end
doo<=(dot >>>4) ;
droo<=doo;
if (edd3)
if (mpyjd3) begin
DOR<=doo;
DOI<= - droo; end
else begin
DOR<=droo;
DOI<= doo; end
end
end
assign dx5p=(dx5<<1)+(dx5>>>2); // multiply by 101101
`ifdef FFT128bitwidth_coef_high
assign dot= dx5p+(dt>>>4)+(dx5>>>12);// (dt>>>9); // multiply by 10110101000000101
`else
assign dot= dx5p+(dt>>>4) ; // multiply by 10110101
`endif
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Complex Multiplier by 0.924
// FUNCTION: Constant multiplier to cos(PI/8)-cos(3*PI/8) =0.9239
// FILES: MPU924.v
// PROPERTIES: 1) Is based on shifts right and add
// 2) for short input bit width 0.924 is approximated as 0.1110_1100_1 =1_00T0_1100_1
// 3) for long bit width 0.9239 is appr. as 0.1110_1100_1000_0011 =1_00T0_1100_1000_0011
// 4) for short input bit width 0.383 is approximated as 0_0110_001
// 5) for long bit width 0.3827 is approximated as 0_0110_0001_1111_1 = 0_0110_0010_0000_T// 4) hardware is 4, or 5 adders +1
// 6) MPYJ switches multiply by j , C383=1 selects the coefficient 0.383
// 7) A complex data is multiplied for 2 cycles, latent delay=4
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`include "FFT128_CONFIG.inc"
module MPUC924_383 ( CLK,DS ,ED, MPYJ,C383,DR,DI ,DOR ,DOI, );
`FFT128paramnb
input CLK ;
wire CLK ;
input DS ;
wire DS ;
input ED; //data strobe
input MPYJ ; //the result is multiplied by -j
wire MPYJ ;
input C383 ; //the coefficient is 0.383
wire C383 ;
input [nb-1:0] DR ;
wire signed [nb-1:0] DR ;
input [nb-1:0] DI ;
wire signed [nb-1:0] DI ;
output [nb-1:0] DOR ;
reg [nb-1:0] DOR ;
output [nb-1:0] DOI ;
reg [nb-1:0] DOI ;
reg signed [nb+1 :0] dx7;
reg signed [nb :0] dx3;
reg signed [nb-1 :0] dii;
reg signed [nb-1 : 0] dt;
wire signed [nb+1 : 0] dx5p;
wire signed [nb+1 : 0] dot;
reg edd,edd2, edd3; //delayed data enable impulse
reg mpyjd,mpyjd2,mpyjd3,c3d,c3d2,c3d3;
reg [nb-1:0] doo ;
reg [nb-1:0] droo ;
always @(posedge CLK)
begin
if (ED) begin
edd<=DS;
edd2<=edd;
edd3<=edd2;
mpyjd<=MPYJ;
mpyjd2<=mpyjd;
mpyjd3<=mpyjd2;
c3d<=C383;
c3d2<=c3d;
c3d3<=c3d2;
if (DS) begin // 1_00T0_1100_1000_0011
dx7<=(DR<<2) - (DR >>>1); //multiply by 7
dx3<=DR+(DR >>>1); //multiply by 3,
dt<=DR;
dii<=DI;
end
else begin
dx7<=(dii<<2) - (dii >>>1); //multiply by 7
dx3<=dii +(dii >>>1); //multiply by 3
dt<=dii;
end
if (c3d || c3d2) doo<=dot >>>2;
else doo<=dot >>>2;
droo<=doo;
if (edd3)
if (mpyjd3) begin
DOR<=doo;
DOI<= - droo; end
else begin
DOR<=droo;
DOI<= doo; end
end
end
assign dx5p= (c3d || c3d2)? ((dt>>>5)+dx3) : ( dx7+(dx3>>>3)); // multiply by 0_0110_001
//or multiply by 1_00T0_11
`ifdef FFT128bitwidth_coef_high
assign dot= (c3d || c3d2)? dx5p-(dt>>>11) :(dx5p+((dt>>>7) +(dx3>>>13)));// by 0_0110_0010_0000_T
//or multiply by 1_00T0_1100_1000_0011
`else
assign dot= (c3d || c3d2)? dx5p : (dx5p+(dt>>>7));
//or multiply by 1_00T0_1100_1
`endif
endmodule
|
// FFT active signal - RSTF from 1-0, STARTF from 1-0 (time is 880+10 clock cycles OR above signals back to 1)
// DLX processor (also ICache) - MRSTD from 0-1 (have to be MRSTD back to 1 as progs are of var length)
// Memory (DCache) - DReadED and DWriteED must be low (practice should be followed although functionally it might be OK without following it) as well as not (MRSTD from 0-1 i.e. DLX not active)
// AES - rstA from 0-1 and then ldA from 1 to 0 (time is 30 cycles OR above signals back to initial values)
//SPI - rstS from 1-0 and also goS is 1
//outputs (coarse grained now as one per module and low or high)
// PF, PD, PM, PA, PS
// res is a boot up signal so that PF,.....etc have initial values
module PMC(MASRST, clk, res, RSTF, STARTF, MRSTD, DReadED, DWriteED, rstA, ldA, rstS, goS, PF,PD,PM,PA,PS);
input MASRST;
input clk, res, RSTF, STARTF, MRSTD, DReadED, DWriteED, rstA, ldA, rstS, goS;
output PF,PD,PM,PA,PS;
// temporary signals
reg [9:0] FFTcoun;
reg [4:0] AEScoun1;
reg [2:0] AEScoun2;
reg RSTF1, STARTF1; // STARTF go down in next cycle after RSTF
reg RSTF2, STARTF2; // safe guard band as RSTF abd RSTF1 can change at CLK
reg C;
reg MRSTD1, MRSTD2;
reg CD;
reg CM, CM1;
reg rstA1, ldA1;
reg rstA2, ldA2; // restrictions on time of ld after rst - relaxed to 8 cycles atleast to avoid any lag or synchronicity probs???
reg CA1;
reg CA2;
reg CS;
reg rstS1, rstS2;
//FFT (when is it active or about to be active????)
always @(posedge clk)
begin
if (((RSTF2 == 1'b1)&&(RSTF == 1'b0))&&((STARTF2 == 1'b1)&&(STARTF == 1'b0))) //*** STARTF has to go down #2 after RSTF
begin
FFTcoun <= 10'b0;
C <= 1'b1;
end
else
begin
FFTcoun <= FFTcoun + 10'b1;
if ((FFTcoun < 10'd900))
begin
C <= C;
end
else
begin
C <= 1'b0;
end
end
end
always @(posedge clk)
begin
RSTF1 <= RSTF;
RSTF2 <= RSTF1;
STARTF1 <= STARTF;
STARTF2 <= STARTF1;
end
// assume VDD power gated by NMOS ....PF = 0 means unconnected)
assign PF = (C == 1'b1);
// DLX (activity monitor)
always @(posedge clk)
begin
MRSTD1 <= MRSTD;
MRSTD2 <= MRSTD1;
end
always @(posedge clk)
begin
if (res == 1'b1)
begin
CD <= 1'b0;
end
else if ((MRSTD2 == 1'b0)&&(MRSTD == 1'b1))
begin
CD <= 1'b1;
end
else if ((MRSTD2 == 1'b1)&&(MRSTD == 1'b0))
begin
CD <= 1'b0;
end
else
begin
CD <= CD;
end
end
assign PD = (CD == 1'b1);
// Data Memory (activity monitor)
// processor and external DMA mode access
always @(posedge clk)
begin
if (res == 1'b1)
begin
CM <= 1'b0;
end
else if (((MRSTD2 == 1'b0)&&(MRSTD == 1'b1)))
begin
CM <= 1'b1;
end
else if (((MRSTD2 == 1'b1)&&(MRSTD == 1'b0)))
begin
CM <= 1'b0;
end
else
begin
CM <= CM;
end
if ((DReadED || DWriteED) == 1'b1)
begin
CM1 <= 1'b1;
end
else
begin
CM1 <= 1'b0;
end
end
assign PM = ((CM == 1'b1)||(CM1 == 1'b1));
// AES (activity monitor)
always @(posedge clk)
begin
if ((rstA2 == 1'b0)&&(rstA == 1'b1))
begin
AEScoun2 <= 3'b0;
CA1 <= 1'b1;
end
else
begin
AEScoun2 <= AEScoun2 + 3'b1;
if ((AEScoun2 < 3'b111))
begin
CA1 <= CA1;
end
else
begin
CA1 <= 1'b0;
end
end
if ((ldA2 == 1'b1)&&(ldA == 1'b0))
begin
AEScoun1 <= 5'b0;
CA2 <= 1'b1;
end
else
begin
AEScoun1 <= AEScoun1 + 5'b1;
if ((AEScoun1 < 5'd30))
begin
CA2 <= CA2;
end
else
begin
CA2 <= 1'b0;
end
end
end
assign PA = ((CA1 == 1'b1)||(CA2 == 1'b1));
always @(posedge clk)
begin
rstA1 <= rstA;
rstA2 <= rstA1;
ldA1 <= ldA;
ldA2 <= ldA1;
end
// SPI (activity monitor)
// based on reset or go
always @(posedge clk)
begin
rstS1 <= rstS;
rstS2 <= rstS1;
end
always @(posedge clk)
begin
if (((rstS2 == 1'b1)&&(rstS == 1'b0)))
begin
CS <= 1'b1;
end
else if ((rstS2 == 1'b0)&&(rstS == 1'b1))
begin
CS <= 1'b0;
end
else if (goS == 1'b1)
begin
CS <= 1'b1;
end
else if (goS == 1'b0)
begin
CS <= 1'b0;
end
end
assign PS = (CS == 1'b1);
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : 1-port synchronous RAM
// FUNCTION: 1-port synchronous RAM
// FILES: RAM256.v -single ported synchronous RAM
// PROPERTIES: 1) Has the volume of 256 data
// 2) RAM is synchronous one, the read datum is outputted in 2 cycles after the address setting
// 3) Can be substituted to any 2-port synchronous RAM
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`timescale 1 ns / 1 ps
`include "FFT128_CONFIG.inc"
module RAM128 ( CLK, ED,WE ,ADDR ,DI ,DO );
`FFT128paramnb
output [nb-1:0] DO ;
reg [nb-1:0] DO ;
input CLK ;
wire CLK ;
input ED;
input WE ;
wire WE ;
input [6:0] ADDR ;
wire [6:0] ADDR ;
input [nb-1:0] DI ;
wire [nb-1:0] DI ;
reg [nb-1:0] mem [127:0];
reg [6:0] addrrd;
always @(posedge CLK) begin
if (ED) begin
if (WE) mem[ADDR] <= DI;
addrrd <= ADDR; //storing the address
DO <= mem[addrrd]; // registering the read datum
end
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : 2-port RAM
// FUNCTION: 2-port RAM with 1 port to write and 1 port to read
// FILES: RAM2x256C.v - dual ported synchronous RAM, contains:
// RAM256.v -single ported synchronous RAM
// PROPERTIES: 1) Has the volume of 2x256 complex data
// 2) Contains 4 single port RAMs for real and imaginary parts of data in the 2-fold volume
// Two halves of RAM are switched on and off in the write mode by the signal ODD
// 3) RAM is synchronous one, the read datum is outputted in 2 cycles after the address setting
// 4) Can be substituted to any 2-port synchronous RAM for example,
// to one RAMB16_S36_S36 in Xilinx FPGAs
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`timescale 1 ns / 1 ps
`include "FFT128_CONFIG.inc"
module RAM2x128C ( CLK ,ED ,WE ,ODD ,ADDRW ,ADDRR ,DR ,DI ,DOR ,DOI );
`FFT128paramnb
output [nb-1:0] DOR ;
wire [nb-1:0] DOR ;
output [nb-1:0] DOI ;
wire [nb-1:0] DOI ;
input CLK ;
wire CLK ;
input ED ;
wire ED ;
input WE ; //write enable
wire WE ;
input ODD ; // RAM part switshing
wire ODD ;
input [6:0] ADDRW ;
wire [6:0] ADDRW ;
input [6:0] ADDRR ;
wire [6:0] ADDRR ;
input [nb-1:0] DR ;
wire [nb-1:0] DR ;
input [nb-1:0] DI ;
wire [nb-1:0] DI ;
reg oddd,odd2;
always @( posedge CLK) begin //switch which reswiches the RAM parts
if (ED) begin
oddd<=ODD;
odd2<=oddd;
end
end
`ifdef FFT128bufferports1
//One-port RAMs are used
wire we0,we1;
wire [nb-1:0] dor0,dor1,doi0,doi1;
wire [6:0] addr0,addr1;
assign addr0 =ODD? ADDRW: ADDRR; //MUXA0
assign addr1 = ~ODD? ADDRW:ADDRR; // MUXA1
assign we0 =ODD? WE: 0; // MUXW0:
assign we1 =~ODD? WE: 0; // MUXW1:
//1-st half - write when odd=1 read when odd=0
RAM128 #(nb) URAM0(.CLK(CLK),.ED(ED),.WE(we0), .ADDR(addr0),.DI(DR),.DO(dor0)); //
RAM128 #(nb) URAM1(.CLK(CLK),.ED(ED),.WE(we0), .ADDR(addr0),.DI(DI),.DO(doi0));
//2-d half
RAM128 #(nb) URAM2(.CLK(CLK),.ED(ED),.WE(we1), .ADDR(addr1),.DI(DR),.DO(dor1));//
RAM128 #(nb) URAM3(.CLK(CLK),.ED(ED),.WE(we1), .ADDR(addr1),.DI(DI),.DO(doi1));
assign DOR=~odd2? dor0 : dor1; // MUXDR:
assign DOI=~odd2? doi0 : doi1; // MUXDI:
`else
//Two-port RAM is used
wire [7:0] addrr2 = {ODD,ADDRR};
wire [7:0] addrw2 = {~ODD,ADDRW};
wire [2*nb-1:0] di= {DR,DI} ;
//wire [2*nb-1:0] doi;
reg [2*nb-1:0] doi;
reg [2*nb-1:0] ram [255:0];
reg [7:0] read_addra;
always @(posedge CLK) begin
if (ED)
begin
if (WE)
ram[addrw2] <= di;
read_addra <= addrr2;
doi = ram[read_addra];
end
end
//assign
assign DOR=doi[2*nb-1:nb]; // Real read data
assign DOI=doi[nb-1:0]; // Imaginary read data
`endif
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : rotating unit, stays between 2 stages of FFT pipeline
// FUNCTION: complex multiplication to the twiddle factors proper to the 64 point FFT
// for any type FPGAs and ASIC.
// FILES: ROTATOR128_v.v - this file,
// WROM128.v - ROM of twiddle factors.
// PROPERTIES: 1) Has 128-clock cycle period starting with the START impulse
// and continuing forever
// 2) rounding is not used
// 3)intended for synthesizing
//
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`timescale 1ns / 1ps
`include "FFT128_CONFIG.inc"
module ROTATOR128 (CLK ,RST,ED,START, DR,DI, DOR, DOI,RDY );
`FFT128paramnb
`FFT128paramnw
input RST ;
wire RST ;
input CLK ;
wire CLK ;
input ED ; //operation enable
input [nb-1:0] DI; //Imaginary part of data
wire [nb-1:0] DI ;
input [nb-1:0] DR ; //Real part of data
input START ; //1-st Data is entered after this impulse
wire START ;
output [nb-1:0] DOI ; //Imaginary part of data
wire [nb-1:0] DOI ;
output [nb-1:0] DOR ; //Real part of data
wire [nb-1:0] DOR ;
output RDY ; //repeats START impulse following the output data
reg RDY ;
reg [6:0] addrw;
reg sd1,sd2;
always @( posedge CLK) //address counter for twiddle factors
begin
if (RST) begin
addrw<=0;
sd1<=0;
sd2<=0;
end
else if (START && ED) begin
addrw[6:0]<=0;
sd1<=START;
sd2<=0;
end
else if (ED) begin
addrw<=addrw+1;
sd1<=START;
sd2<=sd1;
RDY<=sd2;
end
end
wire [6:0] addrwi;
assign addrwi={addrw[4 : 0], addrw[6 : 3] };
wire signed [nw-1:0] wr,wi; //twiddle factor coefficients
//twiddle factor ROM
WROM128 UROM( .ADDR(addrwi), .WR(wr),.WI(wi) );
reg signed [nb-1 : 0] drd,did;
reg signed [nw-1 : 0] wrd,wid;
wire signed [nw+nb-1 : 0] drri,drii,diri,diii;
reg signed [nb:0] drr,dri,dir,dii,dwr,dwi;
assign drri=drd*wrd;
assign diri=did*wrd;
assign drii=drd*wid;
assign diii=did*wid;
always @(posedge CLK) //complex multiplier
begin
if (ED) begin
drd<=DR;
did<=DI;
wrd<=wr;
wid<=wi;
drr<=drri[nw+nb-1 :nw-1]; //msbs of multiplications are stored
dri<=drii[nw+nb-1 : nw-1];
dir<=diri[nw+nb-1 : nw-1];
dii<=diii[nw+nb-1 : nw-1];
dwr<=drr - dii;
dwi<=dri + dir;
end
end
assign DOR=dwr[nb:1];
assign DOI=dwi[nb:1];
endmodule
|
`include "./dlx.defines"
`timescale 1ns/1ps
module securitypolicy(
PHI1, MASRST, // One-Phase clock for DLX
DAddr, DAddrE1, DAddrE2, DAddrE3, DAddrE4, DAddrE5, DRead, DWrite, DWriteE1, DWriteE2, DWriteE3, DWriteE4, DWriteE5, DOut, DOutE1, DOutE2, DOutE3, DOutE4, DOutE5, DIn, // Data Cache interface
IAddr, IAddrE, IRead, IIn, IInE, // Instruction Cache interface
MRST, TCE, TMS, TDI, TDO, // Test Controls
WSI, WRSTN, SelectWIR, ShiftWR, CaptureWR, WSO, STATE, SPCDISF, SPCDISD, SPCDISA, SPCDISS, SPCREQF, SPCREQD, SPCREQA, SPCREQS
);
input MASRST;
input PHI1;
input MRST;
input [`WordSize] DAddrE1, DOutE1, DAddrE2, DOutE2, DAddrE3, DOutE3, DAddrE4, DOutE4, DAddrE5, DOutE5;
input DWriteE1, DWriteE2, DWriteE3, DWriteE4, DWriteE5;
input [`WordSize] IAddrE, IInE; // added external //signals
output [`WordSize] DAddr, DOut, DIn;
output DRead, DWrite;
output [`WordSize] IAddr; // Instruction Cache read address
output IRead; // Instruction Cache read enable
output [`WordSize] IIn; // Instruction from (change) Instruction Cache
input MRST; // Master Reset
input TCE; // Test Clock Enable
input TMS; // Test Mode Select
input TDI; // Test Data In
output TDO; // Test Data Out
// the actual security involved signals
output reg[3:0] STATE;
output reg SPCDISF, SPCREQF, SPCDISD, SPCREQD, SPCDISA, SPCREQA, SPCDISS, SPCREQS;
// boundary scan signals
input WSI, WRSTN, SelectWIR, ShiftWR, CaptureWR;
output WSO;
/// flags to indicate freshly written values
reg F1, F2, F3, F4, F5;
//// addresses to indicate the last read address of the security info of IPs by SPC
reg [31:0] add1, add2, add3, add4, add5;
wire [`WordSize] DAddr1, DOut1, DIn1;
wire DRead1, DWrite1;
wire [`WordSize] IAddr1;
wire IRead1, TDO1;
wire [`WordSize] IIn1;
wire [`WordSize] DInE;
reg [`WordSize] DAddrE;
reg DReadE;
// as of now, DOutE, DAddrE inserted into boundary scan and on //output side DOut, DAddr (can be extended to include IIn, IAddr.)
// boundary scan extra signals
wire [`WordSize] DOutE1A, DAddrE1A; // doing it just for first IP
wire [`WordSize] DOutA, DAddrA;
wire Scan_en, Hold_en_incell, Hold_en_outcell;
wire test_din, test_dout;
wire Bypass_d, Bypass_q;
wire WIR_din, WIR_2_q, WIR_1_q, WIR_dout;
wire [126:0] CTI; // first DR, DI, SHIFT, ADDR, DOI, DOR
wire CK;
wire DIS1, DIS2, DIS3, DIS4, REQ1, REQ2, REQ3, REQ4;
wire [3:0] state;
IcacheSP IC111 (.PHI1(PHI1), .IAddr(IAddr1), .MRST(MRST), .IIn(IIn1), .IInE(IInE), .IAddrE(IAddrE), .IWriteE(`LogicZero));
// debug try
//Icache IC1 (.PHI1(PHI1), .IAddr(IAddr1), .MRST(MRST), .IIn(IIn1), .IInE(32'b0), .IAddrE(32'b0), .IWriteE(`LogicZero));
dlx DLX11 (
.PHI1 (PHI1),
.DIn (DIn1),
.IIn (IIn1),
.MRST (MRST),
.TCE (`LogicZero),
.TMS (`LogicZero),
.TDI (`LogicZero),
.DAddr (DAddr1),
.DRead (DRead1),
.DWrite (DWrite1),
.DOut (DOut1),
.IAddr (IAddr1),
.IRead (IRead1),
.TDO (TDO1)
);
wire [31:0]yy;
reg [31:0] xx;
reg ww;
//assign yy = {27'b0, F5, F4, F3, F2, F1};
assign yy = {28'b0, F4, F3, F2, F1};
always @(yy)
begin
xx = 32'd1;
ww = 1'b1;
end
//reg [31:0] yy1, xx1;
//reg ww1;
//always @(posedge PHI1)
//begin
//if (MASRST == 1'b1)
//begin
//yy1 <= 32'b0;
//xx1 <= 32'b0;
//ww1 <= 1'b0;
//end
//else
Dcache DC111 (.state(state), .DWRR(ww), .DORR(yy), .DARR(xx), .DOut(DOut1), .DOutE1(DOutE1), .DOutE2(DOutE2), .DOutE3(DOutE3), .DOutE4(DOutE4), .DOutE5(DOutE5), .DAddr(DAddr1), .DAddrE1(DAddrE1), .DAddrE2(DAddrE2), .DAddrE3(DAddrE3), .DAddrE4(DAddrE4), .DAddrE5(DAddrE5),.DRead(DRead1), .DReadE(DReadE), .DWrite(DWrite1), .DWriteE1(DWriteE1), .DWriteE2(DWriteE2), .DWriteE3(DWriteE3), .DWriteE4(DWriteE4), .DWriteE5(DWriteE5), .DIn(DIn1), .DAddrE(DAddrE), .DInE(DInE), .DIS1(DIS1),.DIS2(DIS2),.DIS3(DIS3),.DIS4(DIS4), .REQ1(REQ1),.REQ2(REQ2),.REQ3(REQ3),.REQ4(REQ4) );
assign DOutA = DOut1;
assign DRead = DRead1;
assign DIn = DIn1;
assign DAddrA = DAddr1;
assign DWrite = DWrite1;
assign IAddr = IAddr1;
assign IIn = IIn1;
assign IRead = IRead1;
assign TDO = TDO1;
////// the security interfaces of the SPC outside what is inside the DLX and the trace buffer
//// if the address changes, that means a new write has been made by the IP to the SPC
//always @(DAddrE1, DAddrE2, DAddrE3, DAddrE4, DAddrE5)
always @(posedge PHI1)
begin
if (MASRST == 1'b1)
begin
F1 <= 1'b0;
F2 <= 1'b0;
F3 <= 1'b0;
F4 <= 1'b0;
F5 <= 1'b0;
end
//if ((DAddrE1 > add1) && (DWriteE1 == 1'b1)) // ****** will have to update if the address rolls over
if ((DAddrE1 > add1)) // why only assign during the write condition ??? DAddr cannot be less than add
begin
F1 <= 1'b1;
end
//else if (add1 == DAddrE1) // dont mix if and else if together
if (add1 >= DAddrE1) // this is mutually exclusive as compared to prev
begin
F1 <= 1'b0;
end
//if ((DAddrE2 > add2) && (DWriteE2 == 1'b1))
if ((DAddrE2 > add2))
begin
F2 <= 1'b1;
end
if (add2 >= DAddrE2) // this is mutually exclusive as compared to prev (greater for the initial case)
begin
F2 <= 1'b0;
end
//if ((DAddrE3 > add3) && (DWriteE3 == 1'b1))
if ((DAddrE3 > add3))
begin
F3 <= 1'b1;
end
if (add3 >= DAddrE3) // this is mutually exclusive as compared to prev
begin
F3 <= 1'b0;
end
if ((DAddrE4 > add4))
begin
F4 <= 1'b1;
end
if (add4 >= DAddrE4) // this is mutually exclusive as compared to prev
begin
F4 <= 1'b0;
end
if ((DAddrE5 > add5))
begin
F5 <= 1'b1;
end
if (add5 >= DAddrE5) // this is mutually exclusive as compared to prev
begin
F5 <= 1'b0;
end
end
///// NOW logic for add 1, 2 ,3 i.e. reading of the cntents of diff IPs by SPC
// reset them initially
always @(posedge PHI1)
begin
if (MASRST == 1'b1)
begin
add1 <= 32'd48;
add2 <= 32'd64;
add3 <= 32'd80;
add4 <= 32'd96;
add5 <= 32'd112;
end
if (((DAddr1 >= 32'd48) && (DAddr1 < 32'd64)) && (DRead1 == 1'b1))
begin
if (add1 < 32'd63)
begin
add1 <= add1 + 32'b1;
end
else
begin
add1 <= 32'd48;
end
end
if (((DAddr1 >= 32'd64) && (DAddr1 < 32'd80)) && (DRead1 == 1'b1))
begin
if (add2 < 32'd79)
begin
add2 <= add2 + 32'b1;
end
else
begin
add2 <= 32'd64;
end
end
if (((DAddr1 >= 32'd80) && (DAddr1 < 32'd96)) && (DRead1 == 1'b1))
begin
if (add3 < 32'd95)
begin
add3 <= add3 + 32'b1;
end
else
begin
add3 <= 32'd80;
end
end
if (((DAddr1 >= 32'd96) && (DAddr1 < 32'd112)) && (DRead1 == 1'b1))
begin
if (add4 < 32'd111)
begin
add4 <= add4 + 32'b1;
end
else
begin
add4 <= 32'd96;
end
end
if (((DAddr1 >= 32'd112) && (DAddr1 < 32'd128)) && (DRead1 == 1'b1))
begin
if (add5 < 32'd127)
begin
add5 <= add5 + 32'b1;
end
else
begin
add5 <= 32'd112;
end
end
end
always @(posedge PHI1)
begin
if (MASRST == 1'b1)
begin
STATE <= 4'd0;
SPCDISF <= 1'b0;
SPCREQF <= 1'b0;
SPCDISD <= 1'b1;
SPCREQD <= 1'b0;
SPCDISA <= 1'b1;
SPCREQA <= 1'b0;
SPCDISS <= 1'b0;
SPCREQS <= 1'b0;
end
else
begin
STATE <= state;
SPCDISF <= DIS1;
SPCREQF <= REQ1;
SPCDISD <= DIS2;
SPCREQD <= REQ2;
SPCDISA <= DIS3;
SPCREQA <= REQ3;
SPCDISS <= DIS4;
SPCREQS <= REQ4;
end
end
//////// Now as there is no direct system for interrupt (for F == 1, 2 etc.), we have to store the Fs and the adds in the memory
//and make the processor read it in all/intermediate periodic cycles to gauge/monitor what to do
// all the boundary scan stuff
assign CK = PHI1;
assign Scan_en = (WRSTN==1'b1) ? ShiftWR : 1'b0;
assign Hold_en_incell = (WRSTN==1'b1) ? 1'b0 : (({WIR_2_q, WIR_1_q, WIR_dout}==3'b010) ? (~CaptureWR) : 1); //WIR==3'b010 EXTEST
assign Hold_en_outcell = (WRSTN==1'b1) ? 1'b0 : (({WIR_2_q, WIR_1_q, WIR_dout}==3'b100) ? 1 : (~CaptureWR)); //WIR==3'b100 INTEST
assign test_din = (WRSTN==1'b1 && Scan_en==1'b1 && SelectWIR==1'b0 && {WIR_2_q, WIR_1_q, WIR_dout}!=3'b001) ? WSI : 1'b0;
assign Bypass_d = (WRSTN==1'b1 && Scan_en==1'b1 && SelectWIR==1'b0 && {WIR_2_q, WIR_1_q, WIR_dout}==3'b001) ? WSI : 1'b0; //WIR==3'b001 BYPASS
assign WIR_din = (WRSTN==1'b1 && Scan_en==1'b1 && SelectWIR==1'b1) ? WSI : 1'b0; //WIR==3'b001 BYPASS
assign WSO = (~WRSTN) ? 1'b0 : (SelectWIR ? WIR_dout : (({WIR_2_q, WIR_1_q, WIR_dout}==3'b001) ? Bypass_q : test_dout));
//Bypass Register
dff dff_bypass(.CK(CK), .Q(Bypass_q), .D(Bypass_d));
//WIR
dff dff_WIR_2(.CK(CK), .Q(WIR_2_q), .D(WIR_din));
dff dff_WIR_1(.CK(CK), .Q(WIR_1_q), .D(WIR_2_q));
dff dff_WIR_0(.CK(CK), .Q(WIR_dout), .D(WIR_1_q));
// connecting the wrapper boundary registers
WBC WBC_I1(.clk(CK), .CTI(test_din), .CFI(DAddrE1[0]), .Scan_en(Scan_en), .Hold_en(Hold_en_incell), .CTO(CTI[0]), .CFO(DAddrE1A[0]));
genvar i;
generate
for (i = 0; i<31; i=i+1)
begin
WBC WBC_DAddrE(.clk(CK), .CTI(CTI[i]), .CFI(DAddrE1[i+1]), .Scan_en(Scan_en), .Hold_en(Hold_en_incell), .CTO(CTI[i+1]), .CFO(DAddrE1A[i+1]));
end
endgenerate
generate
for (i = 0; i<32; i=i+1)
begin
WBC WBC_DOutE(.clk(CK), .CTI(CTI[i+31]), .CFI(DOutE1[i]), .Scan_en(Scan_en), .Hold_en(Hold_en_incell), .CTO(CTI[i+1+31]), .CFO(DOutE1A[i]));
end
endgenerate
generate
for (i = 0; i<32; i=i+1)
begin
WBC WBC_DOut(.clk(CK), .CTI(CTI[i+63]), .CFI(DOutA[i]), .Scan_en(Scan_en), .Hold_en(Hold_en_outcell), .CTO(CTI[i+1+63]), .CFO(DOut[i]));
end
endgenerate
generate
for (i = 0; i<31; i=i+1)
begin
WBC WBC_DAddr(.clk(CK), .CTI(CTI[i+95]), .CFI(DAddrA[i]), .Scan_en(Scan_en), .Hold_en(Hold_en_outcell), .CTO(CTI[i+1+95]), .CFO(DAddr[i]));
end
endgenerate
WBC WBC_O1(.clk(CK), .CTI(CTI[126]), .CFI(DAddrA[31]), .Scan_en(Scan_en), .Hold_en(Hold_en_outcell), .CTO(test_dout), .CFO(DAddr[31]));
endmodule
// D flip-flop
module dff (CK,Q,D);
input CK,D;
output Q;
reg Q ;
always @(posedge CK)
Q <=D;
endmodule
// 2:1 MUX
module MUX (sel, in0, in1, out);
input sel, in0, in1;
output out;
assign out = sel? in1 : in0;
endmodule
// Wrapper boundary cell
module WBC (clk, CTI, CFI, Scan_en, Hold_en, CTO, CFO);
input clk, CTI, CFI, Scan_en, Hold_en;
output CTO, CFO;
wire DIN;
MUX MUX_in(.sel(Scan_en), .in0(CFO), .in1(CTI), .out(DIN));
MUX MUX_out(.sel(Hold_en), .in0(CFI), .in1(CTO), .out(CFO));
dff dff_1(.CK(clk), .Q(CTO), .D(DIN));
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_clgen.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot (simons@opencores.org) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "spi_defines.v"
`include "timescale.v"
module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge);
parameter Tp = 1;
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
input go; // start transfer
input last_clk; // last clock
input [`SPI_DIVIDER_LEN-1:0] divider; // clock divider (output clock is divided by this value)
output clk_out; // output clock
output pos_edge; // pulse marking positive edge of clk_out
output neg_edge; // pulse marking negative edge of clk_out
reg clk_out;
reg pos_edge;
reg neg_edge;
reg [`SPI_DIVIDER_LEN-1:0] cnt; // clock counter
wire cnt_zero; // conter is equal to zero
wire cnt_one; // conter is equal to one
assign cnt_zero = cnt == {`SPI_DIVIDER_LEN{1'b0}};
assign cnt_one = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
// Counter counts half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
cnt <= #Tp {`SPI_DIVIDER_LEN{1'b1}};
else
begin
if(!enable || cnt_zero)
cnt <= #Tp divider;
else
cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
end
end
// clk_out is asserted every other half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
clk_out <= #Tp 1'b0;
else
clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
end
// Pos and neg edge signals
always @(posedge clk_in or posedge rst)
begin
if(rst)
begin
pos_edge <= #Tp 1'b0;
neg_edge <= #Tp 1'b0;
end
else
begin
pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_define.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot (simons@opencores.org) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Number of bits used for devider register. If used in system with
// low frequency of system clock this can be reduced.
// Use SPI_DIVIDER_LEN for fine tuning theexact number.
//
//`define SPI_DIVIDER_LEN_8
`define SPI_DIVIDER_LEN_16
//`define SPI_DIVIDER_LEN_24
//`define SPI_DIVIDER_LEN_32
`ifdef SPI_DIVIDER_LEN_8
`define SPI_DIVIDER_LEN 8 // Can be set from 1 to 8
`endif
`ifdef SPI_DIVIDER_LEN_16
`define SPI_DIVIDER_LEN 16 // Can be set from 9 to 16
`endif
`ifdef SPI_DIVIDER_LEN_24
`define SPI_DIVIDER_LEN 24 // Can be set from 17 to 24
`endif
`ifdef SPI_DIVIDER_LEN_32
`define SPI_DIVIDER_LEN 32 // Can be set from 25 to 32
`endif
//
// Maximum nuber of bits that can be send/received at once.
// Use SPI_MAX_CHAR for fine tuning the exact number, when using
// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8.
//
`define SPI_MAX_CHAR_128
//`define SPI_MAX_CHAR_64
//`define SPI_MAX_CHAR_32
//`define SPI_MAX_CHAR_24
//`define SPI_MAX_CHAR_16
//`define SPI_MAX_CHAR_8
`ifdef SPI_MAX_CHAR_128
`define SPI_MAX_CHAR 128 // Can only be set to 128
`define SPI_CHAR_LEN_BITS 7
`endif
`ifdef SPI_MAX_CHAR_64
`define SPI_MAX_CHAR 64 // Can only be set to 64
`define SPI_CHAR_LEN_BITS 6
`endif
`ifdef SPI_MAX_CHAR_32
`define SPI_MAX_CHAR 32 // Can be set from 25 to 32
`define SPI_CHAR_LEN_BITS 5
`endif
`ifdef SPI_MAX_CHAR_24
`define SPI_MAX_CHAR 24 // Can be set from 17 to 24
`define SPI_CHAR_LEN_BITS 5
`endif
`ifdef SPI_MAX_CHAR_16
`define SPI_MAX_CHAR 16 // Can be set from 9 to 16
`define SPI_CHAR_LEN_BITS 4
`endif
`ifdef SPI_MAX_CHAR_8
`define SPI_MAX_CHAR 8 // Can be set from 1 to 8
`define SPI_CHAR_LEN_BITS 3
`endif
//
// Number of device select signals. Use SPI_SS_NB for fine tuning the
// exact number.
//
`define SPI_SS_NB_8
//`define SPI_SS_NB_16
//`define SPI_SS_NB_24
//`define SPI_SS_NB_32
`ifdef SPI_SS_NB_8
`define SPI_SS_NB 8 // Can be set from 1 to 8
`endif
`ifdef SPI_SS_NB_16
`define SPI_SS_NB 16 // Can be set from 9 to 16
`endif
`ifdef SPI_SS_NB_24
`define SPI_SS_NB 24 // Can be set from 17 to 24
`endif
`ifdef SPI_SS_NB_32
`define SPI_SS_NB 32 // Can be set from 25 to 32
`endif
//
// Bits of WISHBONE address used for partial decoding of SPI registers.
//
`define SPI_OFS_BITS 4:2
//
// Register offset
//
`define SPI_RX_0 0
`define SPI_RX_1 1
`define SPI_RX_2 2
`define SPI_RX_3 3
`define SPI_TX_0 0
`define SPI_TX_1 1
`define SPI_TX_2 2
`define SPI_TX_3 3
`define SPI_CTRL 4
`define SPI_DEVIDE 5
`define SPI_SS 6
//
// Number of bits in ctrl register
//
`define SPI_CTRL_BIT_NB 14
//
// Control register bit position
//
`define SPI_CTRL_ASS 13
`define SPI_CTRL_IE 12
`define SPI_CTRL_LSB 11
`define SPI_CTRL_TX_NEGEDGE 10
`define SPI_CTRL_RX_NEGEDGE 9
`define SPI_CTRL_GO 8
`define SPI_CTRL_RES_1 7
`define SPI_CTRL_CHAR_LEN 6:0
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_shift.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot (simons@opencores.org) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "spi_defines.v"
`include "timescale.v"
module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
pos_edge, neg_edge, rx_negedge, tx_negedge,
tip, last,
p_in, p_out, s_clk, s_in, s_out);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
input [3:0] latch; // latch signal for storing the data in shift register
input [3:0] byte_sel; // byte select signals for storing the data in shift register
input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
input lsb; // lbs first on the line
input go; // start stansfer
input pos_edge; // recognize posedge of sclk
input neg_edge; // recognize negedge of sclk
input rx_negedge; // s_in is sampled on negative edge
input tx_negedge; // s_out is driven on negative edge
output tip; // transfer in progress
output last; // last bit
input [31:0] p_in; // parallel in
output [`SPI_MAX_CHAR-1:0] p_out; // parallel out
input s_clk; // serial clock
input s_in; // serial in
output s_out; // serial out
reg s_out;
reg tip;
reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count
reg [`SPI_MAX_CHAR-1:0] data; // shift register
wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position
wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position
wire rx_clk; // rx clock enable
wire tx_clk; // tx clock enable
assign p_out = data;
assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) :
(rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
assign last = !(|cnt);
assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
// Character bit counter
always @(posedge clk or posedge rst)
begin
if(rst)
cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
else
begin
if(tip)
cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
else
cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
end
end
// Transfer in progress
always @(posedge clk or posedge rst)
begin
if(rst)
tip <= #Tp 1'b0;
else if(go && ~tip)
tip <= #Tp 1'b1;
else if(tip && last && pos_edge)
tip <= #Tp 1'b0;
end
// Sending bits to the line
always @(posedge clk or posedge rst)
begin
if (rst)
s_out <= #Tp 1'b0;
else
s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
end
// Receiving bits from the line
always @(posedge clk or posedge rst)
begin
if (rst)
data <= #Tp {`SPI_MAX_CHAR{1'b0}};
`ifdef SPI_MAX_CHAR_128
else if (latch[0] && !tip)
begin
if (byte_sel[3])
data[31:24] <= #Tp p_in[31:24];
if (byte_sel[2])
data[23:16] <= #Tp p_in[23:16];
if (byte_sel[1])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
end
else if (latch[1] && !tip)
begin
if (byte_sel[3])
data[63:56] <= #Tp p_in[31:24];
if (byte_sel[2])
data[55:48] <= #Tp p_in[23:16];
if (byte_sel[1])
data[47:40] <= #Tp p_in[15:8];
if (byte_sel[0])
data[39:32] <= #Tp p_in[7:0];
end
else if (latch[2] && !tip)
begin
if (byte_sel[3])
data[95:88] <= #Tp p_in[31:24];
if (byte_sel[2])
data[87:80] <= #Tp p_in[23:16];
if (byte_sel[1])
data[79:72] <= #Tp p_in[15:8];
if (byte_sel[0])
data[71:64] <= #Tp p_in[7:0];
end
else if (latch[3] && !tip)
begin
if (byte_sel[3])
data[127:120] <= #Tp p_in[31:24];
if (byte_sel[2])
data[119:112] <= #Tp p_in[23:16];
if (byte_sel[1])
data[111:104] <= #Tp p_in[15:8];
if (byte_sel[0])
data[103:96] <= #Tp p_in[7:0];
end
`else
`ifdef SPI_MAX_CHAR_64
else if (latch[0] && !tip)
begin
if (byte_sel[3])
data[31:24] <= #Tp p_in[31:24];
if (byte_sel[2])
data[23:16] <= #Tp p_in[23:16];
if (byte_sel[1])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
end
else if (latch[1] && !tip)
begin
if (byte_sel[3])
data[63:56] <= #Tp p_in[31:24];
if (byte_sel[2])
data[55:48] <= #Tp p_in[23:16];
if (byte_sel[1])
data[47:40] <= #Tp p_in[15:8];
if (byte_sel[0])
data[39:32] <= #Tp p_in[7:0];
end
`else
else if (latch[0] && !tip)
begin
`ifdef SPI_MAX_CHAR_8
if (byte_sel[0])
data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0];
`endif
`ifdef SPI_MAX_CHAR_16
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
if (byte_sel[1])
data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8];
`endif
`ifdef SPI_MAX_CHAR_24
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
if (byte_sel[1])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[2])
data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16];
`endif
`ifdef SPI_MAX_CHAR_32
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
if (byte_sel[1])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[2])
data[23:16] <= #Tp p_in[23:16];
if (byte_sel[3])
data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24];
`endif
end
`endif
`endif
else
data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_top.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot (simons@opencores.org) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "spi_defines.v"
`include "timescale.v"
//// BRING OUT TIP (Transfer in Progress)
module spi_top
(MASRST,
// Wishbone signals
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, go, divider, spi_tx_sel, wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o,
// SPI signals
ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i, DWR, DO, DAD, Pause, SPCREQ, SPCDIS, MRST, DBus, Sel, TP1, TPE1
);
// maybe go would have sufficied for pause, but still adding an extra signal for surety!!!
parameter Tp = 1;
input MASRST;
// Wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input [4:0] wb_adr_i; // lower address bits
input [32-1:0] wb_dat_i; // databus input
output [32-1:0] wb_dat_o; // databus output
//input [3:0] wb_sel_i; // byte select inputs
input wb_we_i; // write enable input
input go ; // start enable
input wb_stb_i; // stobe/core select signal
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_err_o; // termination w/ error
output wb_int_o; // interrupt request signal output
input [`SPI_DIVIDER_LEN-1:0] divider;
input [3:0] spi_tx_sel;
input Pause, SPCREQ, SPCDIS;
output reg DWR;
output reg [31:0]DO, DAD;
output [31:0] TP1, TPE1;
input MRST;
input MRST;
input [31:0] DBus;
input [1:0] Sel;
wire [7:0] EV;
wire [31:0] Val;
// SPI signals
output [`SPI_SS_NB-1:0] ss_pad_o; // slave select
output sclk_pad_o; // serial clock
output mosi_pad_o; // master out slave in
input miso_pad_i; // master in slave out
reg [32-1:0] wb_dat_o;
reg wb_ack_o;
reg wb_int_o;
// Internal signals
//reg [`SPI_DIVIDER_LEN-1:0] divider; // Divider register
reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register
reg [`SPI_SS_NB-1:0] ss; // Slave select register
reg [32-1:0] wb_dat; // wb data out
wire [`SPI_MAX_CHAR-1:0] rx; // Rx register
wire rx_negedge; // miso is sampled on negative edge
wire tx_negedge; // mosi is driven on negative edge
wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len
wire go; // go
wire lsb; // lsb first on line
wire ie; // interrupt enable
wire ass; // automatic slave select
wire spi_divider_sel; // divider register select
wire spi_ctrl_sel; // ctrl register select
//wire [3:0] spi_tx_sel; // tx_l register select
wire spi_ss_sel; // ss register select
wire tip; // transfer in progress
wire pos_edge; // recognize posedge of sclk
wire neg_edge; // recognize negedge of sclk
wire last_bit; // marks last character bit
wire [3:0] wb_sel_i; // new one here
// Wb acknowledge
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
wb_ack_o <= #Tp 1'b0;
else
wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o;
end
// Wb error
assign wb_err_o = 1'b0;
// Interrupt
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
wb_int_o <= #Tp 1'b0;
else if (ie && tip && last_bit && pos_edge)
wb_int_o <= #Tp 1'b1;
else if (wb_ack_o)
wb_int_o <= #Tp 1'b0;
end
assign rx_negedge = 1'b1;
assign tx_negedge = 1'b1;
assign char_len = 7'b1111111;
assign lsb = 1'b1;
assign ie = 1'b1;
assign wb_sel_i = 4'b1111;
// What about go????????????????????????? (put it at input)
assign ss_pad_o = 8'b00000001;
reg EN;
spi_clgen clgen (.clk_in((wb_clk_i) && (Pause)), .rst((wb_rst_i) || (SPCDIS)), .go(go), .enable(tip), .last_clk(last_bit),
.divider(divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge),
.neg_edge(neg_edge));
spi_shift shift (.clk((wb_clk_i) && (Pause)), .rst((wb_rst_i) || (SPCDIS)), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
.latch(spi_tx_sel[3:0] & {4{(wb_we_i)||(EN)}}), .byte_sel(wb_sel_i), .lsb(lsb),
.go(go), .pos_edge(pos_edge), .neg_edge(neg_edge),
.rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
.tip(tip), .last(last_bit),
.p_in(wb_dat_i), .p_out(rx),
.s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
debug_SPI SPY(wb_clk_i, MRST, go, last_bit, wb_dat_i, wb_we_i, spi_tx_sel, wb_err_o, divider, mosi_pad_o, DBus, Sel, EV, Val, TP1, TPE1);
////// security wrapper ///////
reg [9:0] counter;
reg [3:0] state;
reg [127:0] buff[0:3];
reg wb_rst_i1;
reg go1;
reg Pause1;
reg wb_int_o1;
always @(posedge wb_clk_i)
begin
wb_rst_i1 <= wb_rst_i;
Pause1 <= Pause;
go1 <= go;
wb_int_o1 <= wb_int_o;
end
always @(posedge wb_clk_i)
begin
if (((wb_rst_i == 1'b0) && (go1 == 1'b0) && (go == 1'b1) && (Pause == 1'b1)) || ((wb_int_o1 == 1'b0) && (wb_int_o == 1'b1)))
begin
counter <= 10'd0;
end
else if ((wb_rst_i == 1'b0) && (go == 1'b1) && (Pause == 1'b1) && (SPCDIS == 1'b0))
begin
counter <= counter + 10'd1;
end
end
//////////////////////////////////////////////////////////////////
reg [2:0] pastcount;
always @(*)
begin
if ((go1 == 1'b0)&&(go == 1'b1))
begin
pastcount = pastcount + 3'd1;
end
else if (MASRST == 1'b1)
begin
pastcount = 3'd0;
end
end // need to incorporate a MASTER RESET signifying boot FROM SYTEM CONTROLLER
// what about the buffer
always @(pastcount)
begin
//if ((go1 == 1'b0)&&(go == 1'b1)) //// please check on this //////////////////////////////////////
//begin
buff[pastcount] = wb_dat_i; //
//end
end // need to incorporate a MASTER RESET FROM SYTEM CONTROLLER
always @(posedge wb_clk_i)
begin
if (go == 1'b1)
begin
EN = 1'b1; // suppose wb_e cannot be zero during operation
end
else
begin
EN = 1'b0;
end
end
always @(posedge wb_clk_i)
begin
if (MASRST == 1'b1)
begin
state <= 4'd0;
end
else if ((wb_rst_i == 1'b0) && (go1 == 1'b0) && (go == 1'b1) && (Pause == 1'b1))
begin
state <= 4'd1;
end
else if ((Pause1 == 1'b1) && (Pause == 1'b0))
begin
state <= 4'd2;
end
else if ((Pause1 == 1'b0) && (Pause == 1'b1))
begin
state <= 4'd3;
end
else if ((wb_int_o1 == 1'b0) && (wb_int_o == 1'b1))
begin
state <= 4'd4;
end
else if (SPCREQ == 1'b1)
begin
state <= 4'd5;
end
else
begin
state <= 4'd6;
end
end
always @(state)
begin
if (SPCDIS == 1'b0) // an addition (CAN REMOVE THE DWR ADDITIONS LATER)
begin
case(state)
4'd0: begin
DWR = 1'b0;
DAD = 32'd0;
DO = 32'd0;
end
4'd1: begin
DWR = (1'b1);
DAD = 32'd96;
DO = {spi_tx_sel, divider, 8'd0, state};
end
4'd2: begin
DWR = (1'b1 && (!SPCDIS));
DAD = DAD + 32'd1;
DO = {counter, 18'd0, state};
end
4'd3: begin
DWR = (1'b1 && (!SPCDIS));
DAD = DAD + 32'd1;
DO = {28'd0, state};
end
4'd4: begin
DWR = (1'b1 && (!SPCDIS));
DAD = DAD + 32'd1;
DO = {tip, 27'd0, state};
end
4'd5: begin
DWR = (1'b1 && (!SPCDIS));
DAD = DAD + 32'd1;
DO = {divider, counter, 2'd0, state};
end
4'd6: begin
DWR = 1'b0;
DAD = DAD;
DO = 32'd0;
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
|
`include "./dlx.defines"
`timescale 1ns/1ps
module together (
PHI, MASRST, // One-Phase clock for DLX
DAddr, DAddrE, DAddrE2, DAddrE3, DRead, DWrite, DReadE, DWriteE, DReadE2, DWriteE2, DReadE3, DWriteE3, DOut, DOutE, DOutE2, DOutE3, DIn, DInE, DInE2, DInE3, STATE, IAddr, IAddrE, IRead, IIn, IInE, IWriteE, // Instruction Cache interface
MRST, Pause, TCE, TMS, TDI, TDO, // Test Controls
WSI, WRSTN, SelectWIR, ShiftWR, CaptureWR, WSO, DWR, DO, DAD, SPCREQ, SPCDIS, LDS, LDF, MACcalc, MACactual, DBus, Sel, TP1, TPE1, MRST11, stop, TP2, TPE2);
//// actually the change from PHI1 to PHI was absolutely not necessary, confusing (doesn't hurt, so not reverted back)
input MASRST;
input PHI;
input MRST;
input MRST11;
input [`WordSize] DAddrE, DAddrE2, DAddrE3, DOutE, DOutE2, DOutE3, IAddrE, IInE; // added external //signals
output [`WordSize] DAddr, DOut, DIn, DInE,DInE2, DInE3;
output DRead, DWrite;
input DReadE, DWriteE;
input DReadE2, DWriteE2;
input DReadE3, DWriteE3;
output [`WordSize] IAddr; // Instruction Cache read address
output IRead; // Instruction Cache read enable
output [`WordSize] IIn; // Instruction from (change) Instruction Cache
input MRST; // Master Reset
input TCE; // Test Clock Enable
input TMS; // Test Mode Select
input TDI; // Test Data In
output TDO; // Test Data Out
input IWriteE;
input [31:0] DBus;
input [1:0] Sel;
//input [3:0] STATE1; // deciding the enable signals from security controller to system memory
input [3:0] STATE;
input SPCREQ, SPCDIS; // coming from the SPCcontroller
input Pause;
input LDS, LDF; // coming from master controller signifying start and end of instruction load
input MACcalc, MACactual; // MACcalc coming from cryto module directly current 1 bit signal
// boundary scan signals
input WSI, WRSTN, SelectWIR, ShiftWR, CaptureWR;
output WSO;
wire [`WordSize] DAddr1, DOut1, DIn1;
wire DRead1, DWrite1;
wire [`WordSize] IAddr1;
wire IRead1, TDO1;
wire [`WordSize] IIn1;
//wire [`WordSize] DInE;
// as of now, DOutE, DAddrE inserted into boundary scan and on //output side DOut, DAddr (can be extended to include IIn, IAddr.)
// boundary scan extra signals
wire [`WordSize] DOutEA, DAddrEA;
wire [`WordSize] DOutA, DAddrA;
wire Scan_en, Hold_en_incell, Hold_en_outcell;
wire test_din, test_dout;
wire Bypass_d, Bypass_q;
wire WIR_din, WIR_2_q, WIR_1_q, WIR_dout;
wire [126:0] CTI; // first DR, DI, SHIFT, ADDR, DOI, DOR
wire CK;
reg EN; // control the timing of writes into Icache/memory
reg cert; // enabling the integrity check of firmwire
wire [31:0] Val;
output [31:0] TP1;
output TPE1;
output [31:0] TP2;
output TPE2;
wire [9:0] EV;
wire [31:0] TP;
wire TPE;
assign TP1 = TP;
assign TPE1 = TPE;
input stop;
wire [31:0] Val1;
wire [7:0] EV1;
Icache IC1 (.PHI1(PHI && Pause && cert), .IAddr(IAddr1), .MRST(MRST && SPCDIS), .IIn(IIn1), .IInE(IInE), .IAddrE(IAddrE), .IWriteE(IWriteE && EN));
// debug try
//Icache IC1 (.PHI1(PHI1), .IAddr(IAddr1), .MRST(MRST), .IIn(IIn1), .IInE(32'b0), .IAddrE(32'b0), .IWriteE(`LogicZero));
// can put the SPCDIS in RST as well
dlx DLX (
.PHI1 (PHI && Pause && cert),
.DIn (DIn1),
.IIn (IIn1),
.MRST (MRST && SPCDIS),
.TCE (`LogicZero),
.TMS (`LogicZero),
.TDI (`LogicZero),
.DAddr (DAddr1),
.DRead (DRead1),
.DWrite (DWrite1),
.DOut (DOut1),
.IAddr (IAddr1),
.IRead (IRead1),
.TDO (TDO1)
);
reg r0, r1, r2, r3;
reg w0, w1, w2, w3;
// DLX, AES, FFT, SPI (in order of terminology used)
always @(STATE)
begin
case(STATE)
4'd0: begin
r0 = 1'b1; r1 = 1'b1; r2 = 1'b1; r3 = 1'b1;
w0 = 1'b1; w1 = 1'b1; w2 = 1'b1; w3 = 1'b1;
end
4'd1: begin // suppose AES working
r0 = 1'b0; r1 = 1'b1; r2 = 1'b0; r3 = 1'b0;
w0 = 1'b0; w1 = 1'b1; w2 = 1'b0; w3 = 1'b0;
end
4'd2: begin // suppose DLXworking just after AES (information flow case)
r0 = 1'b1; r1 = 1'b1; r2 = 1'b0; r3 = 1'b0;
w0 = 1'b1; w1 = 1'b1; w2 = 1'b0; w3 = 1'b0;
end
4'd3: begin // external operations through SPI
r0 = 1'b1; r1 = 1'b0; r2 = 1'b1; r3 = 1'b1;
w0 = 1'b1; w1 = 1'b0; w2 = 1'b1; w3 = 1'b1;
end
default: begin
r0 = 1'b1; r1 = 1'b1; r2 = 1'b1; r3 = 1'b1;
w0 = 1'b1; w1 = 1'b1; w2 = 1'b1; w3 = 1'b1;
end
endcase
end
// state based
//Dcache DC1 (.DOut(DOut1), .DAddr(DAddr1), .DRead(DRead1), //.DWrite(DWrite1), .DIn(DIn1), .DOutE(DOutEA), .DAddrE(DAddrEA), //.DInE(DInE), .DReadE(`LogicZero), .DWriteE(`LogicZero));
//SystemMem SM1 (.DOut(DOut1), .DAddr(DAddr1), .DRead(DRead1), .DWrite(DWrite1), .DIn(DIn1), .DOutE1(DOutEA), .DAddrE1(DAddrEA), .DInE1(DInE), .DReadE1(DReadE), .DWriteE1(DWriteE), .DOutE2(DOutE2), .DAddrE2(DAddrE2), .DInE2(DInE2), .DReadE2(DReadE2), .DWriteE2(DWriteE2), .DOutE3(DOutE3), .DAddrE3(DAddrE3), .DInE3(DInE3), .DReadE3(DReadE3), .DWriteE3(DWriteE3));
SystemMem SM1 (.DOut(DOut1), .DAddr(DAddr1), .DRead(DRead1 && r0), .DWrite(DWrite1 && w0), .DIn(DIn1), .DOutE1(DOutEA), .DAddrE1(DAddrEA), .DInE1(DInE), .DReadE1(DReadE && r1), .DWriteE1(DWriteE && w1), .DOutE2(DOutE2), .DAddrE2(DAddrE2), .DInE2(DInE2), .DReadE2(DReadE2 && r2), .DWriteE2(DWriteE2 && w2), .DOutE3(DOutE3), .DAddrE3(DAddrE3), .DInE3(DInE3), .DReadE3(DReadE3 && r3), .DWriteE3(DWriteE3 && w3));
assign DOutA = DOut1;
assign DRead = DRead1;
assign DIn = DIn1;
assign DAddrA = DAddr1;
assign DWrite = DWrite1;
assign IAddr = IAddr1;
assign IIn = IIn1;
assign IRead = IRead1;
assign TDO = TDO1;
debug_DLX1 ETM(PHI, MRST11, MRST, stop, Pause, IIn1, IAddr1, DIn1, DOut1, DAddr1, DRead1, DWrite1, 32'b1, 32'd2,DBus, Sel, TP, TPE, EV, Val);
// debug logic needed for system memory
debug_mem MEMI(PHI, MRST11, DIn1, DOut1, DAddr1, (DRead1&&r0), (DWrite1 && w0), DInE, DOutEA, DAddrEA, (DReadE&&r1), (DWriteE && w1), DInE2, DOutE2, DAddrE2, (DReadE2&&r2), (DWriteE2 && w2), DInE3, DOutE3, DAddrE3, (DReadE3&&r3), (DWriteE3 && w3), DBus, Sel, EV1, Val1, TP2, TPE2);
// Debug - SPC interface and storage
reg [31:0] tempbuff[0:3];
reg [1:0] cru;
reg [31:0] tempbuff1;
always @(posedge PHI)
begin
if (MASRST == 1'b1)
begin
tempbuff[0] <= 'd0;
tempbuff[1] <= 'd0;
tempbuff[2] <= 'd0;
tempbuff[3] <= 'd0;
cru <= 'd0;
end
else if ((EV[7:0] > 'd0) || (cru > 2'b0))
begin
cru <= cru + 2'b1;
tempbuff[3] <= tempbuff[2];
tempbuff[2] <= tempbuff[1];
tempbuff[1] <= tempbuff[0];
tempbuff[0] <= Val;
end
else
begin
cru <= 2'b0;
// needs to store tempbuff to wait for SPCREQ
end
end
reg [9:0] EV2;
reg [7:0] EV3;
always @(posedge PHI)
begin
EV2 <= EV;
end
always @(posedge PHI)
begin
if (MASRST == 1'b1)
begin
tempbuff1 <= 'd0;
end
else if ((EV1[7:0] > 'd0))
begin
tempbuff1 <= Val1;
end
// needs to store tempbuff to wait for SPCREQ
end
always @(posedge PHI)
begin
EV3 <= EV1;
end
////added signals to interface with security policy controller
///**********************************************************///
///////////////////////////////// security wrapper ///////////////////
output reg DWR;
output reg [31:0]DO, DAD;
reg [9:0] counter;
reg [4:0] state;
reg [31:0] buff[0:3];
//reg resultcheck;
reg MRST1;
reg Pause1;
reg LDS1;
reg LDF1;
always @(posedge PHI)
begin
MRST1 <= MRST;
Pause1 <= Pause;
LDS1 <= LDS;
LDF1 <= LDF;
end
//// logic for counter
///// assuming same counter for both instruction load as well as DLX processing
// time stamp
always @(posedge PHI)
begin
if (((MRST1 == 1'b0)&&(MRST == 1'b1)&& (Pause == 1'b1)) || ((LDS1 == 1'b0)&&(LDS == 1'b1)&& (Pause == 1'b1)))
begin
counter <= 10'd0;
end
else if ((((LDS == 1'b1)&& (cert == 1'b1))||((MRST == 1'b1) && (cert == 1'b1)))&& (Pause == 1'b1) && (SPCDIS == 1'b1)) // no mention of load finish req
begin
counter <= counter + 10'd1;
end
end
reg [9:0] totalcount;
// assign totalcount = ((LDF1 == 1'b0)&& (LDF == 1'b1))? counter:10'b0; // just when loading instruction finishes
// has to be register form
always @(posedge PHI)
begin
if (MASRST == 1'b1)
begin
totalcount <= 10'd0;
end
else if ((LDF1 == 1'b0)&& (LDF == 1'b1))
begin
totalcount <= counter;
end
end
//////////////////////////////////////////////////////////////////
reg [2:0] pastcount;
always @(*)
begin
if ((MRST1 == 1'b0)&&(MRST == 1'b1))
begin
pastcount = pastcount + 3'd1;
end
else if (MASRST == 1'b1)
begin
pastcount = 3'd0;
end
end // need to incorporate a MASTER RESET signifying boot FROM SYTEM CONTROLLER
// what about the buffer
always @(pastcount)
//begin
//if (((MRST1 == 1'b0)&&(MRST == 1'b1)))
begin
buff[pastcount] = totalcount; //
//end
end // need to incorporate a MASTER RESET FROM SYTEM CONTROLLER
// EN signal to prevent instruction memory write during the time of execution
always @(posedge PHI)
begin
if ((WRSTN == 1'b1) && (ShiftWR == 1'b0)) // normal mode (can be in other terms as well)
begin
if (MRST == 1'b1)
begin
EN = 1'b0;
end
else
begin
EN = 1'b1;
end
end
else
begin
EN = 1'b1; // during TEST mode
end
end
/// the certification
always @(posedge PHI)
begin
if (MASRST == 1'b1)
begin
cert <= 1'b1;
end
else if ((LDS1 == 1'b0) && (LDS == 1'b1) && (Pause == 1'b1))
begin
cert <= 1'b0;
end
else if (MACactual == MACcalc) // verifying if the key meets randomness criteria (local implementation , doesnot have to send to SPC)
begin
cert <= 1'b1;
end
end
// any firmwire integrity check or so???
// do something like this as if the integrity check is successful then start execution
///////////NOW FOR THE STATES
///// states for instruction load start, finish (total inst), pause; execution start, finish, pause
/// data memory access??????
//// think about how a TOCTOU policy might be implemented......from that regard, what info???
always @(posedge PHI)
begin
if (MASRST == 1'b1)
begin
state <= 5'd0;
end
else if ((WRSTN == 1'b1) && (ShiftWR == 1'b0)) // normal mode
begin
if ((LDS1 == 1'b0) && (LDS == 1'b1) && (Pause == 1'b1))
begin
state <= 5'd1;
end
else if ((LDS == 1'b1) && (counter == 10'b1))
begin
state <= 5'd2; // passed the integrity check test
end
else if ((LDF1 == 1'b0) && (LDF == 1'b1) && (Pause == 1'b1))
begin
state <= 5'd3;
end
else if ((LDS == 1'b1) && (Pause1 == 1'b1) && (Pause == 1'b0) )
begin
state <= 5'd4;
end
else if ((LDS == 1'b1) && (Pause1 == 1'b0) && (Pause == 1'b1) )
begin
state <= 5'd5;
end
// now starts the instruction execution stuff
else if ((MRST1 == 1'b0)&&(MRST == 1'b1) && (Pause == 1'b1))
begin
state <= 5'd6;
end
else if ((IAddr1/4 == totalcount) && (MRST == 1'b1) && (Pause == 1'b1)) // last instruction start execution
begin
state <= 5'd7;
end
else if ((MRST1 == 1'b1)&&(MRST == 1'b0) && (Pause == 1'b1))
begin
state <= 5'd8; //actual end
end
else if ((MRST == 1'b1) && (Pause1 == 1'b1) && (Pause == 1'b0) )
begin
state <= 5'd9;
end
else if ((MRST == 1'b1) && (Pause1 == 1'b0) && (Pause == 1'b1) )
begin
state <= 5'd10;
end
else if (SPCREQ == 1'b1)
begin
state <= 5'd11;
end
else if (EV[7:0] > 'd0)
begin
state <= 5'd12;
end
else if (EV1[7:0] > 'd0)
begin
state <= 5'd14;
end
else
begin
state <= 5'd13;
end
end
else // test mode
begin
state <= 'd0;
//if ((LDS1 == 1'b0) && (LDS == 1'b1) && (Pause == 1'b1))
//begin
//state <= 5'd13;
//end
//else if ((LDS == 1'b1) && (counter == 10'b1))
//begin
//state <= 5'd14; // passed the integrity check test
//end
//else if ((LDF1 == 1'b0) && (LDF == 1'b1) && (Pause == 1'b1))
//begin
//state <= 5'd15;
//end
//else if ((LDS == 1'b1) && (Pause1 == 1'b1) && (Pause == 1'b0) )
//begin
//state <= 5'd16;
//end
//else if ((LDS == 1'b1) && (Pause1 == 1'b0) && (Pause == 1'b1) )
//begin
//state <= 5'd17;
//end
//// now starts the instruction execution stuff
//else if ((MRST1 == 1'b0)&&(MRST == 1'b1) && (Pause == 1'b1))
//begin
//state <= 5'd18;
//end
//else if ((IAddr1/4 == totalcount) && (MRST == 1'b1) && (Pause == 1'b1)) // last instruction start execution
//begin
//state <= 5'd19;
//end
//else if ((MRST1 == 1'b1)&&(MRST == 1'b0) && (Pause == 1'b1))
//begin
//state <= 5'd20; //actual end
//end
//else if ((MRST == 1'b1) && (Pause1 == 1'b1) && (Pause == 1'b0) )
//begin
//state <= 5'd21;
//end
//else if ((MRST == 1'b1) && (Pause1 == 1'b0) && (Pause == 1'b1) )
//begin
//state <= 5'd22;
//end
//else if (SPCREQ == 1'b1)
//begin
//state <= 5'd23;
//end
//else
//begin
//state <= 5'd24;
//end
end
end
///**********************************************************///
//// outputs at different stages // has 32 different addresses to write too as an asumption
always @(state)
begin
//if ((SPCDIS && cert) == 1'b1) // an addition (CAN REMOVE THE DWR ADDITIONS LATER)
//begin
case(state)
5'd0: begin
DWR = 1'b0;
DAD = 32'd0;
DO = 32'd0;
end
5'd1: begin
DWR = 1'b1; // could be 1 && SPCDIS to prevent any write if SPCDIS = 0 from apriori (will depend on SPC logic implementation)
DAD = 32'd64;
DO = {totalcount, 17'd0, state}; // actually the previous one's this data
end
5'd2: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {cert, 26'b0, state};
end
5'd3: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {counter, 17'd0, state};
end
5'd4: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {counter, 17'd0, state};
end
5'd5: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {27'd0, state};
end
5'd6: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {totalcount, 17'd0, state};
end
5'd7: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {27'd0, state};
end
5'd8: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {counter, 17'd0, state};
end
5'd9: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {counter, 17'd0, state};
end
5'd10: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {27'd0, state};
end
5'd11: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {tempbuff[0][15:0], 11'd0, state};
//DO = {IAddr1[15:0], 11'd0, state};
end
5'd12: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {counter, 7'd0, EV2, state};
end
5'd13: begin
DWR = 1'b0;
DAD = DAD;
DO = 32'd0;
end
5'd14: begin
DWR = (1'b1 && cert && SPCDIS);
DAD = DAD + 32'd1;
DO = {12'd0, 7'd0, EV3, state};
end
//5'd13: begin
// DWR = 1'b1;
// DAD = 32'd64;
// DO = {totalcount, 17'd0, state};
// end
//5'd14: begin
// DWR = (1'b1 && cert && SPCDIS);
// DAD = DAD + 32'd1;
// DO = {cert, 26'd0, state};
// end
//5'd15: begin
// DWR = (1'b1 && cert && SPCDIS);
// DAD = DAD + 32'd1;
// DO = {counter, 17'd0, state};
// end
//5'd16: begin
// DWR = (1'b1 && cert && SPCDIS);
// DAD = DAD + 32'd1;
// DO = {counter, 17'd0, state};
// end
//5'd17: begin
// DWR = (1'b1 && cert && SPCDIS);
// DAD = DAD + 32'd1;
// DO = {27'd0, state};
// end
//5'd18: begin
// DWR = (1'b1 && cert && SPCDIS);
// DAD = DAD + 32'd1;
// DO = {totalcount, 17'd0, state};
//
// end
//5'd19: begin
// DWR = (1'b1 && cert && SPCDIS);
// DAD = DAD + 32'd1;
// DO = {27'd0, state};
// end
//5'd20: begin
// DWR = (1'b1 && cert && SPCDIS);
// DAD = DAD + 32'd1;
// DO = {counter, 17'd0, state};
// end
//5'd21: begin
// DWR = (1'b1 && cert && SPCDIS);
// DAD = DAD + 32'd1;
// DO = {counter, 17'd0, state};
// end
//5'd22: begin
// DWR = (1'b1 && cert && SPCDIS);
// DAD = DAD + 32'd1;
// DO = {27'd0, state};
// end
//5'd23: begin
// DWR = (1'b1 && cert && SPCDIS);
// DAD = DAD + 32'd1;
// DO = {IAddr1[15:0], 11'd0, state};
// end
//5'd24: begin
// DWR = 1'b0;
// DAD = DAD;
// DO = 32'd0;
// end
// fill in the rest of the stuff
endcase
//end
end
// all the boundary scan stuff
assign CK = (PHI && Pause && SPCDIS) ; // diffeerent here as SPCDIS is also included
assign Scan_en = (WRSTN==1'b1) ? ShiftWR : 1'b0;
assign Hold_en_incell = (WRSTN==1'b1) ? 1'b0 : (({WIR_2_q, WIR_1_q, WIR_dout}==3'b010) ? (~CaptureWR) : 1); //WIR==3'b010 EXTEST
assign Hold_en_outcell = (WRSTN==1'b1) ? 1'b0 : (({WIR_2_q, WIR_1_q, WIR_dout}==3'b100) ? 1 : (~CaptureWR)); //WIR==3'b100 INTEST
assign test_din = (WRSTN==1'b1 && Scan_en==1'b1 && SelectWIR==1'b0 && {WIR_2_q, WIR_1_q, WIR_dout}!=3'b001) ? WSI : 1'b0;
assign Bypass_d = (WRSTN==1'b1 && Scan_en==1'b1 && SelectWIR==1'b0 && {WIR_2_q, WIR_1_q, WIR_dout}==3'b001) ? WSI : 1'b0; //WIR==3'b001 BYPASS
assign WIR_din = (WRSTN==1'b1 && Scan_en==1'b1 && SelectWIR==1'b1) ? WSI : 1'b0; //WIR==3'b001 BYPASS
assign WSO = (~WRSTN) ? 1'b0 : (SelectWIR ? WIR_dout : (({WIR_2_q, WIR_1_q, WIR_dout}==3'b001) ? Bypass_q : test_dout));
//Bypass Register
dff dff_bypass(.CK(CK), .Q(Bypass_q), .D(Bypass_d));
//WIR
dff dff_WIR_2(.CK(CK), .Q(WIR_2_q), .D(WIR_din));
dff dff_WIR_1(.CK(CK), .Q(WIR_1_q), .D(WIR_2_q));
dff dff_WIR_0(.CK(CK), .Q(WIR_dout), .D(WIR_1_q));
// connecting the wrapper boundary registers
WBC WBC_I1(.clk(CK), .CTI(test_din), .CFI(DAddrE[0]), .Scan_en(Scan_en), .Hold_en(Hold_en_incell), .CTO(CTI[0]), .CFO(DAddrEA[0]));
genvar i;
generate
for (i = 0; i<31; i=i+1)
begin
WBC WBC_DAddrE(.clk(CK), .CTI(CTI[i]), .CFI(DAddrE[i+1]), .Scan_en(Scan_en), .Hold_en(Hold_en_incell), .CTO(CTI[i+1]), .CFO(DAddrEA[i+1]));
end
endgenerate
generate
for (i = 0; i<32; i=i+1)
begin
WBC WBC_DOutE(.clk(CK), .CTI(CTI[i+31]), .CFI(DOutE[i]), .Scan_en(Scan_en), .Hold_en(Hold_en_incell), .CTO(CTI[i+1+31]), .CFO(DOutEA[i]));
end
endgenerate
generate
for (i = 0; i<32; i=i+1)
begin
WBC WBC_DOut(.clk(CK), .CTI(CTI[i+63]), .CFI(DOutA[i]), .Scan_en(Scan_en), .Hold_en(Hold_en_outcell), .CTO(CTI[i+1+63]), .CFO(DOut[i]));
end
endgenerate
generate
for (i = 0; i<31; i=i+1)
begin
WBC WBC_DAddr(.clk(CK), .CTI(CTI[i+95]), .CFI(DAddrA[i]), .Scan_en(Scan_en), .Hold_en(Hold_en_outcell), .CTO(CTI[i+1+95]), .CFO(DAddr[i]));
end
endgenerate
WBC WBC_O1(.clk(CK), .CTI(CTI[126]), .CFI(DAddrA[31]), .Scan_en(Scan_en), .Hold_en(Hold_en_outcell), .CTO(test_dout), .CFO(DAddr[31]));
endmodule
// D flip-flop
module dff (CK,Q,D);
input CK,D;
output Q;
reg Q ;
always @(posedge CK)
Q <=D;
endmodule
// 2:1 MUX
module MUX (sel, in0, in1, out);
input sel, in0, in1;
output out;
assign out = sel? in1 : in0;
endmodule
// Wrapper boundary cell
module WBC (clk, CTI, CFI, Scan_en, Hold_en, CTO, CFO);
input clk, CTI, CFI, Scan_en, Hold_en;
output CTO, CFO;
wire DIN;
MUX MUX_in(.sel(Scan_en), .in0(CFO), .in1(CTI), .out(DIN));
MUX MUX_out(.sel(Hold_en), .in0(CFI), .in1(CTO), .out(CFO));
dff dff_1(.CK(clk), .Q(CTO), .D(DIN));
endmodule
|
/*************************************************************************
* FILE: dlx.v
* Written By: Michael J. Kelley
* Written On: December 18, 1995
* Updated By: Michael J. Kelley
* Updated On: March 4, 1996
*
* Description:
*
* This file contains the hardware description of the DLX architecture
* as specified by Hennessy and Patterson in Computer Architecture a
* Quantitative Approach.
*************************************************************************
*/
//`include "/l/users/mkelley/DLX/verilog/dlx.defines"
`include "./dlx.defines"
`timescale 1ns/1ps
module dlx (
PHI1, // One-Phase clock for DLX
DAddr, DRead, DWrite, DOut, DIn, // Data Cache interface
IAddr, IRead, IIn, // Instruction Cache interface
MRST, TCE, TMS, TDI, TDO // Test Controls
);
/*************************************************************************
* Parameter Declarations
*************************************************************************
*/
input PHI1; // One-Phase clock signal used
output [`WordSize] DAddr; // Address for Data Cache read/write
output DRead; // Data Cache read enable
output DWrite; // Data Cache write enable
output [`WordSize] DOut; // Data Input to Data Cache (write)
input [`WordSize] DIn; // Data Output from Data Cache (read)
output [`WordSize] IAddr; // Instruction Cache read address
output IRead; // Instruction Cache read enable
input [`WordSize] IIn; // Instruction from Instruction Cache
input MRST; // Master Reset
input TCE; // Test Clock Enable
input TMS; // Test Mode Select
input TDI; // Test Data In
output TDO; // Test Data Out
wire [`WordSize] DAddr;
wire DRead, MemControl_DRead;
wire DWrite, MemControl_DWrite;
wire [`WordSize] DOut, DataWriteReg_Q;
wire [`WordSize] IAddr, IR2_Q;
wire IRead;
wire TDO;
wire [`WordSize] RegFile_OUT1, SourceMux_IN1, TargetMux_IN1, PC2_Q, PC4_D;
wire [`WordSize] PCMux_Y, PC2_D, PC1_Q, PC3_D, IDControl_IR2, PCAdd_A;
wire [`WordSize] WBMux_Y, SourceReg_Q, DataWriteMux_IN0, IR3_Q, ALU_F ;
wire [`WordSize] TargetReg_Q, DataWriteMux_IN1, PCAdd_SUM;
wire [`WordSize] WBMux_IN0, WBMux_IN1, WBControl_IR5, PC4_Q, IR4_Q;
wire [4:0] RegFile_W, DestinationReg_Q, DestinationMux_Y, WriteDestinationReg_Q;
wire [`WordSize] IR5_Q;
wire IFControl_Equal, WBControl_WriteEnable;
wire [`WordSize] PCFEED;
wire PCFEEDEN;
IF_stage part1_IF (
PHI1, MRST, IFControl_Equal,
IIn, PCAdd_SUM, RegFile_OUT1,PCFEED, PCFEEDEN,
IAddr, PC3_D, IDControl_IR2, PCAdd_A
);
ID_stage part2_ID (
PHI1, MRST, WBControl_WriteEnable,
IDControl_IR2, WBMux_Y, PCAdd_A, PC3_D,
WriteDestinationReg_Q,
RegFile_OUT1, PCAdd_SUM, SourceMux_IN1, TargetMux_IN1, PC4_D, IR3_Q,
IFControl_Equal
);
EX_stage part3_EX (
PHI1, MRST,
IR3_Q, IR5_Q, WBMux_Y, SourceMux_IN1, TargetMux_IN1, PCAdd_A, PC4_D,
IR4_Q, DAddr, DOut, PC4_Q,
DestinationReg_Q, PCFEED, PCFEEDEN
);
MEM_stage part4_MEM (
PHI1, MRST,
DIn, DAddr, IR4_Q, PC4_Q,
DestinationReg_Q,
WBMux_IN0, WBMux_IN1, IR5_Q,
WriteDestinationReg_Q,
DRead, DWrite
);
WB_stage part5_WB (
WBMux_IN0, WBMux_IN1, IR5_Q,
WBMux_Y,
WBControl_WriteEnable
);
endmodule
/*************************************************************************
* Instruction Fetch (IF) Stage of DLX Pipeline
*************************************************************************
*/
module IF_stage (
PHI1, MRST, IFControl_Equal,
IIn, PCAdd_SUM, RegFile_OUT1, PCFEED, PCFEEDEN,
IAddr, PC3_D, IDControl_IR2, PCAdd_A
);
input [`WordSize] IIn, PCAdd_SUM, RegFile_OUT1;
input PHI1, MRST, IFControl_Equal;
output [`WordSize] IAddr, PC3_D, IDControl_IR2, PCAdd_A;
input [`WordSize] PCFEED;
input PCFEEDEN;
wire [`WordSize] PC1_Q, PCInc_SUM, PC1_D, IFControl_PCVector;
wire [1:0] IFControl_PCMuxSelect;
reg [`WordSize] PC_D1;
IFCtrl
IFControl (
.IR2 (IDControl_IR2),
.Equal (IFControl_Equal),
.MRST (MRST),
.PCMuxSelect (IFControl_PCMuxSelect),
.PCVector (IFControl_PCVector)
);
addhsv #(32, 1, "AUTO")
PCInc (
.A (PC1_Q),
.B (`PCInc),
.CIN (`LogicZero),
.SUM (PCInc_SUM),
.COUT (),
.OVF ()
);
// addition for branch
always @(*)
begin
if (PCFEEDEN == 1'b1)
begin
PC_D1 = PCFEED;
end
else
begin
PC_D1 = PC1_D;
end
end
newmux4 #(32, 1, "AUTO")
PCMux (
.S0 (IFControl_PCMuxSelect[0]),
.S1 (IFControl_PCMuxSelect[1]),
.IN0 (PCInc_SUM),
.IN1 (PCAdd_SUM),
.IN2 (IFControl_PCVector),
.IN3 (RegFile_OUT1),
.Y (PC1_D)
);
dff_cq #(32, 1, "AUTO")
PC1 (
.CLK (PHI1),
.CLR (MRST),
.D (PC_D1),
.Q (PC1_Q),
.QBAR ()
),
PC2 (
.CLK (PHI1),
.CLR (MRST),
.D (PC1_Q),
.Q (PC3_D),
.QBAR ()
);
assign IAddr = PC1_Q;
dff_cq #(32, 1, "AUTO")
IR2 (
.CLK (PHI1),
.CLR (MRST),
.D (IIn),
.Q (IDControl_IR2),
.QBAR ()
),
PCIncReg (
.CLK (PHI1),
.CLR (MRST),
.D (PCInc_SUM),
.Q (PCAdd_A),
.QBAR ()
);
endmodule
/*************************************************************************
* Instruction Decode (ID) Stage of DLX Pipeline
*************************************************************************
*/
module ID_stage (
PHI1, MRST, WBControl_WriteEnable,
IDControl_IR2, WBMux_Y, PCAdd_A, PC3_D,
WriteDestinationReg_Q,
RegFile_OUT1, PCAdd_SUM, SourceMux_IN1, TargetMux_IN1, PC4_D, IR3_Q,
IFControl_Equal
);
input PHI1, MRST, WBControl_WriteEnable;
input [`WordSize] IDControl_IR2, WBMux_Y, PCAdd_A, PC3_D;
input [4:0] WriteDestinationReg_Q;
output [`WordSize] RegFile_OUT1, PCAdd_SUM, SourceMux_IN1, TargetMux_IN1, PC4_D, IR3_Q;
output IFControl_Equal;
wire [1:0] IDControl_PCAddMuxSelect;
wire [`WordSize] TargetReg_D, PCAddMux_Y;
reg [`WordSize] PCMUX;
IDCtrl
IDControl (
.IR2 (IDControl_IR2),
.PCAddMuxSelect (IDControl_PCAddMuxSelect)
);
regfile2r #(32, 32, 5, "AUTO")
RegFile (
.W (WriteDestinationReg_Q),
.IN0 (WBMux_Y),
.R1 (IDControl_IR2[`RS]),
.R2 (IDControl_IR2[`RT]),
.RE1 (`LogicOne),
.RE2 (`LogicOne),
.WE (WBControl_WriteEnable & ~PHI1),
.OUT1 (RegFile_OUT1),
.OUT2 (TargetReg_D)
);
newmux3 #(32, 1, "AUTO")
PCAddMux (
.S0 (IDControl_PCAddMuxSelect[0]),
.S1 (IDControl_PCAddMuxSelect[1]),
.IN0 ({{16{IDControl_IR2[15]}}, IDControl_IR2[`Immediate]}),
.IN1 ({{6{IDControl_IR2[25]}}, IDControl_IR2[`Target]}),
.IN2 (RegFile_OUT1),
.Y (PCAddMux_Y)
);
always @(*)
begin
if (IDControl_IR2[`OP] == `BEQZ)
begin
PCMUX = `PCInc;
end
else
begin
PCMUX = PCAddMux_Y;
end
end
addhsv #(32, 1, "AUTO")
PCAdd (
.A (PCAdd_A),
.B (PCMUX),
.CIN (`LogicZero),
.SUM (PCAdd_SUM),
.COUT (),
.OVF ()
);
zero_compare #(1, "AUTO")
Compare (
.A (RegFile_OUT1),
.A_lessthan_zero (),
.A_lessthan_equal_zero (),
.A_greaterthan_equal_zero (),
.A_greaterthan_zero (),
.A_equal_zero (IFControl_Equal),
.A_not_equal_zero ()
);
dff_cq #(32, 1, "AUTO")
SourceReg (
.CLK (PHI1),
.CLR (MRST),
.D (RegFile_OUT1),
.Q (SourceMux_IN1),
.QBAR ()
),
TargetReg (
.CLK (PHI1),
.CLR (MRST),
.D (TargetReg_D),
.Q (TargetMux_IN1),
.QBAR ()
),
PC3 (
.CLK (PHI1),
.CLR (MRST),
.D (PC3_D),
.Q (PC4_D),
.QBAR ()
);
dff_cq #(32, 1, "AUTO")
IR3 (
.CLK (PHI1),
.CLR (MRST),
.D (IDControl_IR2),
.Q (IR3_Q),
.QBAR ()
);
endmodule
/*************************************************************************
* Execute (EX) Stage of DLX Pipeline
*************************************************************************
*/
module EX_stage (
PHI1, MRST,
IR3_Q, IR5_Q, WBMux_Y, SourceMux_IN1, TargetMux_IN1, PCAdd_A, PC4_D,
IR4_Q, DAddr, DOut, PC4_Q,
DestinationReg_Q, PCFEED, PCFEEDEN
); // additional outputs for branch
input PHI1, MRST;
input [`WordSize] IR3_Q, IR5_Q, WBMux_Y, SourceMux_IN1, TargetMux_IN1, PCAdd_A, PC4_D;
output [`WordSize] IR4_Q, DAddr, DOut, PC4_Q;
output [4:0] DestinationReg_Q;
output [`WordSize] PCFEED;
output PCFEEDEN;
wire [`WordSize] SourceMux_Y, TargetMux_Y;
wire [1:0] EXControl_DestinationMuxSelect, EXControl_ALUorShiftMuxSelect, EXControl_SourceMuxSelect, EXControl_TargetMuxSelect;
wire [1:0] EXControl_CompareMux1Select, EXControl_CompareMux2Select, EXControl_CompareResultMuxSelect;
wire DataWriteMux_S0;
wire [5:0] EXControl_ALUSelect;
wire [4:0] ShiftLeft_S, DestinationReg_D;
wire [`WordSize] DataWriteReg_D, ALU_F, Shift_Y, ALUorShiftMux_Y, CompareResultMux_Y;
wire CompareMux1_IN0, CompareMux1_IN1, CompareMux1_IN2, CompareMux2_IN0, CompareMux2_IN1, CompareMux2_IN2;
wire CompareMux1_Y, CompareMux2_Y;
// my addition
reg [`WordSize] SourceMux_Y1;
reg [`WordSize] PCFEED1;
reg PCFEEDEN1;
EXCtrl
EXControl (
.IR3 (IR3_Q),
.IR4 (IR4_Q),
.IR5 (IR5_Q),
.ShiftAmount (TargetMux_Y),
.DestinationMuxSelect (EXControl_DestinationMuxSelect),
.DataWriteMuxSelect (DataWriteMux_S0),
.ALUSelect (EXControl_ALUSelect),
.ShiftSelect (ShiftLeft_S),
.ALUorShiftMuxSelect (EXControl_ALUorShiftMuxSelect),
.SourceMuxSelect (EXControl_SourceMuxSelect),
.TargetMuxSelect (EXControl_TargetMuxSelect),
.CompareMux1Select (EXControl_CompareMux1Select),
.CompareMux2Select (EXControl_CompareMux2Select),
.CompareResultMuxSelect (EXControl_CompareResultMuxSelect)
);
newmux4 #(32, 1, "AUTO")
SourceMux (
.S0 (EXControl_SourceMuxSelect[0]),
.S1 (EXControl_SourceMuxSelect[1]),
.IN0 (WBMux_Y),
.IN1 (SourceMux_IN1),
.IN2 (DAddr),
.IN3 (PCAdd_A),
.Y (SourceMux_Y)
);
newmux4 #(32, 1, "AUTO")
TargetMux (
.S0 (EXControl_TargetMuxSelect[0]),
.S1 (EXControl_TargetMuxSelect[1]),
.IN0 (WBMux_Y),
.IN1 (TargetMux_IN1),
.IN2 ({{16{IR3_Q[15]}},IR3_Q[`Immediate]}),
.IN3 (DAddr),
.Y (TargetMux_Y)
);
newmux3_5 #(5, 1, "AUTO")
DestinationMux (
.S0 (EXControl_DestinationMuxSelect[0]),
.S1 (EXControl_DestinationMuxSelect[1]),
.IN0 (IR3_Q[`RT]),
.IN1 (IR3_Q[`RD]),
.IN2 (5'b11111),
.Y (DestinationReg_D)
);
//addition
always @(*)
begin
if (IR3_Q[`OP] == `SW)
begin
SourceMux_Y1 = TargetMux_IN1;
end
else
begin
SourceMux_Y1 = SourceMux_Y;
end
end
//addition
always @(*)
begin
if (IR3_Q[`OP] == `BEQZ)
begin
if (SourceMux_Y == 1'b0)
begin
PCFEED1 = TargetMux_Y;
PCFEEDEN1 = 1'b1;
end
else
begin
PCFEED1 = 0;
PCFEEDEN1 = 1'b0;
end
end
else
begin
PCFEED1 = 0;
PCFEEDEN1 = 1'b0;
end
end
dff_cq #(32, 1, "AUTO")
PCF1 (
.CLK (PHI1),
.CLR (MRST),
.D (PCFEED1),
.Q (PCFEED),
.QBAR ()
);
dff_cq #(1, 1, "AUTO")
PCFE1 (
.CLK (PHI1),
.CLR (MRST),
.D (PCFEEDEN1),
.Q (PCFEEDEN),
.QBAR ()
);
newmux2 #(32, 1, "AUTO")
DataWriteMux (
.S0 (DataWriteMux_S0),
.IN0 (SourceMux_Y1),
.IN1 (TargetMux_Y),
.Y (DataWriteReg_D)
);
alu #(32, 1, "AUTO")
ALU (
.C0 (EXControl_ALUSelect[0]),
.A (SourceMux_Y),
.B (TargetMux_Y),
.S0 (EXControl_ALUSelect[2]),
.S1 (EXControl_ALUSelect[3]),
.S2 (EXControl_ALUSelect[4]),
.S3 (EXControl_ALUSelect[5]),
.M (EXControl_ALUSelect[1]),
.F (ALU_F),
.COUT ()
);
shifter
Shifter (
.IN0 (SourceMux_Y),
.S (ShiftLeft_S),
.S2 (EXControl_ALUorShiftMuxSelect),
.Y (Shift_Y)
);
newmux2 #(32, 1, "AUTO")
ALUorShiftMux (
.S0 (|EXControl_ALUorShiftMuxSelect),
.IN0 (ALU_F),
.IN1 (Shift_Y),
.Y (ALUorShiftMux_Y)
);
zero_compare #(1, "AUTO")
Compare2 (
.A (ALU_F),
.A_lessthan_zero (CompareMux1_IN0),
.A_lessthan_equal_zero (CompareMux1_IN1),
.A_greaterthan_equal_zero (CompareMux1_IN2),
.A_greaterthan_zero (CompareMux2_IN0),
.A_equal_zero (CompareMux2_IN1),
.A_not_equal_zero (CompareMux2_IN2)
);
newmux3_1 #(1, 1, "AUTO")
CompareMux1 (
.S0 (EXControl_CompareMux1Select[0]),
.S1 (EXControl_CompareMux1Select[1]),
.IN0 (CompareMux1_IN0),
.IN1 (CompareMux1_IN1),
.IN2 (CompareMux1_IN2),
.Y (CompareMux1_Y)
),
CompareMux2 (
.S0 (EXControl_CompareMux2Select[0]),
.S1 (EXControl_CompareMux2Select[1]),
.IN0 (CompareMux2_IN0),
.IN1 (CompareMux2_IN1),
.IN2 (CompareMux2_IN2),
.Y (CompareMux2_Y)
);
newmux4 #(32, 1, "AUTO")
CompareResultMux (
.S0 (EXControl_CompareResultMuxSelect[0]),
.S1 (EXControl_CompareResultMuxSelect[1]),
.IN0 ({31'b0, CompareMux1_Y}),
.IN1 ({31'b0, CompareMux2_Y}),
.IN2 (ALUorShiftMux_Y),
.IN3 ({IR3_Q[15:0], 16'b0}),
.Y (CompareResultMux_Y)
);
dff_cq #(32, 1, "AUTO")
ALUReg (
.CLK (PHI1),
.CLR (MRST),
.D (CompareResultMux_Y),
.Q (DAddr),
.QBAR ()
),
DataWriteReg (
.CLK (PHI1),
.CLR (MRST),
.D (DataWriteReg_D),
.Q (DOut),
.QBAR ()
),
PC4 (
.CLK (PHI1),
.CLR (MRST),
.D (PC4_D),
.Q (PC4_Q),
.QBAR ()
);
dff_cq #(32, 1, "AUTO")
IR4 (
.CLK (PHI1),
.CLR (MRST),
.D (IR3_Q),
.Q (IR4_Q),
.QBAR ()
);
dff_cq5 #(5, 1, "AUTO")
DestinationReg (
.CLK (PHI1),
.CLR (MRST),
.D (DestinationReg_D),
.Q (DestinationReg_Q),
.QBAR ()
);
endmodule
/*************************************************************************
* Memory (MEM) Stage of DLX Pipeline
*************************************************************************
*/
module MEM_stage (
PHI1, MRST,
DIn, DAddr, IR4_Q, PC4_Q,
DestinationReg_Q,
WBMux_IN0, WBMux_IN1, IR5_Q,
WriteDestinationReg_Q,
DRead, DWrite
);
input PHI1, MRST;
input [`WordSize] DIn, DAddr, IR4_Q, PC4_Q;
input [4:0] DestinationReg_Q;
output [`WordSize] WBMux_IN0, WBMux_IN1, IR5_Q;
output [4:0] WriteDestinationReg_Q;
output DRead, DWrite;
MemCtrl
MemControl (
.IR4 (IR4_Q),
.DRead (DRead),
.DWrite (DWrite)
);
dff_cq #(32, 1, "AUTO")
MemDataReg (
.CLK (PHI1),
.CLR (MRST),
.D (DIn),
.Q (WBMux_IN0),
.QBAR ()
),
ALUDataReg (
.CLK (PHI1),
.CLR (MRST),
.D (DAddr),
.Q (WBMux_IN1),
.QBAR ()
),
PC5 (
.CLK (PHI1),
.CLR (MRST),
.D (PC4_Q),
.Q (),
.QBAR ()
);
dff_cq #(32, 1, "AUTO")
IR5 (
.CLK (PHI1),
.CLR (MRST),
.D (IR4_Q),
.Q (IR5_Q),
.QBAR ()
);
dff_cq5 #(5, 1, "AUTO")
WriteDestinationReg (
.CLK (PHI1),
.CLR (MRST),
.D (DestinationReg_Q),
.Q (WriteDestinationReg_Q),
.QBAR ()
);
endmodule
/*************************************************************************
* Write Back (WB) Stage of DLX Pipeline
*************************************************************************
*/
module WB_stage (
WBMux_IN0, WBMux_IN1, IR5_Q,
WBMux_Y,
WBControl_WriteEnable
);
input [`WordSize] WBMux_IN0, WBMux_IN1, IR5_Q;
output [`WordSize] WBMux_Y;
output WBControl_WriteEnable;
wire WBMux_S0;
WBCtrl
WBControl (
.IR5 (IR5_Q),
.WBMuxSelect (WBMux_S0),
.WriteEnable (WBControl_WriteEnable)
);
newmux2 #(32, 1, "AUTO")
WBMux (
.S0 (WBMux_S0),
.IN0 (WBMux_IN0),
.IN1 (WBMux_IN1),
.Y (WBMux_Y)
);
endmodule
//------------------------------------------------------------
// Copyright 1992, 1993 Cascade Design Automation Corporation.
//------------------------------------------------------------
module adder_generic(a,b,cin,cout,ovf,y);
parameter n = 32;
input [(n - 1):0] a;
input [(n - 1):0] b;
input cin;
output cout;
output ovf;
output [(n - 1):0] y;
reg cout;
reg ovf;
reg [(n - 1):0] y;
reg [n:0] temp;
always
@(a or b or cin)
begin
temp = ((cin + {1'b0,a}) + b);
cout = temp[n];
y = temp[(n - 1):0];
ovf = (((a[(n - 1)] & b[(n - 1)]) & ( ~ temp[(n - 1)])) | ((( ~ a[(n - 1)]) & ( ~ b[(n - 1)])) & temp[(n - 1)]));
end
endmodule
//------------------------------------------------------------
// Copyright 1992, 1993 Cascade Design Automation Corporation.
//------------------------------------------------------------
module addhsv(A,B,CIN,COUT,OVF,SUM);
parameter N = 32;
parameter DPFLAG = 1;
parameter GROUP = "dpath1";
parameter BUFFER_SIZE = "DEFAULT";
parameter
d_COUT_r = 1,
d_COUT_f = 1,
d_OVF_r = 1,
d_OVF_f = 1,
d_SUM = 1;
input [(N - 1):0] A;
input [(N - 1):0] B;
input CIN;
output COUT;
output OVF;
output [(N - 1):0] SUM;
wire COUT_temp;
wire OVF_temp;
wire [(N - 1):0] SUM_temp;
assign #(d_COUT_r,d_COUT_f) COUT = COUT_temp;
assign #(d_OVF_r,d_OVF_f) OVF = OVF_temp;
assign #(d_SUM) SUM = SUM_temp;
adder_generic #(N) inst1 (A,B,CIN,COUT_temp,OVF_temp,SUM_temp);
endmodule
//------------------------------------------------------------
// Copyright 1992, 1993 Cascade Design Automation Corporation.
//------------------------------------------------------------
module alu(A,B,C0,M,S0,S1,S2,S3,COUT,F);
parameter N = 32;
parameter FAST = 0;
parameter DPFLAG = 1;
parameter GROUP = "dpath1";
parameter BUFFER_SIZE = "DEFAULT";
parameter
d_COUT_r = 1,
d_COUT_f = 1,
d_F = 1;
input [(N - 1):0] A;
input [(N - 1):0] B;
input C0;
input M;
input S0;
input S1;
input S2;
input S3;
output COUT;
output [(N - 1):0] F;
wire [(N - 1):0] A_temp;
wire [(N - 1):0] B_temp;
wire COUT_temp;
wire [(N - 1):0] F_temp;
reg [3:0] s;
wire overflow;
assign A_temp = A|A;
assign B_temp = B|B;
assign #(d_COUT_r,d_COUT_f) COUT = COUT_temp;
assign #(d_F) F = F_temp;
/*
initial
begin
if((DPFLAG == 0))
$display("(WARNING) The instance %m of type alu can't be implemented as a standard cell.");
end
*/
always
@(S0 or S1 or S2 or S3)
begin
s[3] = S3;
s[2] = S2;
s[1] = S1;
s[0] = S0;
end
alu_generic #(N) inst1 (A_temp,B_temp,C0,M,s,COUT_temp,F_temp,overflow);
endmodule
//------------------------------------------------------------
// Copyright 1992, 1993 Cascade Design Automation Corporation.
//------------------------------------------------------------
module alu_generic(a,b,cin,m,s,cout,out,overflow);
parameter n = 32;
input [(n - 1):0] a;
input [(n - 1):0] b;
input cin;
input m;
input [3:0] s;
output cout;
output [(n - 1):0] out;
output overflow;
reg cout;
reg [(n - 1):0] out;
reg overflow;
reg [(n - 1):0] logic;
reg [(n - 1):0] pr;
reg [(n - 1):0] pr1;
reg [n:0] arith;
reg [n:0] aa;
reg cinbar;
always
@(a or b or cin or s or m)
begin
overflow = 1'b0;
cinbar = ( ~ cin);
if((s == 4'd0))
begin
logic = ( ~ a);
aa = ( ~ 128'b0);
aa[n] = 1'b0;
arith = ({1'b0,a} + aa);
if((cin == 1'b1))
arith = (arith + 1'b1);
if(((1'b0 == arith[(n - 1)]) && (a[(n - 1)] == 1'b1)))
overflow = 1'b1;
end
else if((s == 4'd1))
begin
logic = ( ~ (a & b));
pr = (a & b);
aa = ( ~ 128'b0);
aa[n] = 1'b0;
arith = ({1'b0,pr} + aa);
if((cin == 1'b1))
arith = (arith + 1'b1);
if(((arith[(n - 1)] == 1'b0) && (pr[(n - 1)] == 1'b1)))
overflow = 1'b1;
end
else if((s == 4'd2))
begin
logic = (( ~ a) | b);
pr = ( ~ logic);
aa = ( ~ 128'b0);
aa[n] = 1'b0;
arith = ({1'b0,pr} + aa);
if((cin == 1'b1))
arith = (arith + 1'b1);
if(((arith[(n - 1)] == 1'b0) && (pr[(n - 1)] == 1'b1)))
overflow = 1'b1;
end
else if((s == 4'd3))
begin
logic = ( ~ 128'b0);
arith = ({1'b0,logic} + cin);
end
else if((s == 4'd4))
begin
logic = ( ~ (a | b));
pr = (a | ( ~ b));
arith = (a + ({1'b0,pr} + cin));
//if(((1'b0 == (pr[(n - 1)] ^ a[(n - 1)])) && (pr[(n - 1)] !== arith[(n - 1)])))
if(((1'b0 == (pr[(n - 1)] ^ a[(n - 1)])) && (pr[(n - 1)] != arith[(n - 1)])))
overflow = 1'b1;
end
else if((s == 4'd5))
begin
logic = ( ~ b);
pr = (a & b);
pr1 = (a | ( ~ b));
arith = (pr + ({1'b0,pr1} + cin));
//if(((1'b0 == (pr[(n - 1)] ^ pr1[(n - 1)])) && (pr[(n - 1)] !== arith[(n - 1)])))
if(((1'b0 == (pr[(n - 1)] ^ pr1[(n - 1)])) && (pr[(n - 1)] != arith[(n - 1)])))
overflow = 1'b1;
end
else if((s == 4'd6))
begin
logic = ( ~ (a ^ b));
pr = (( ~ (b + cinbar)) + 1'b1);
arith = ({1'b0,a} + pr);
//if((((a[(n - 1)] ^ b[(n - 1)]) == 1'b1) && (a[(n - 1)] !== arith[(n - 1)])))
if((((a[(n - 1)] ^ b[(n - 1)]) == 1'b1) && (a[(n - 1)] != arith[(n - 1)])))
overflow = 1'b1;
end
else if((s == 4'd7))
begin
logic = (a | ( ~ b));
arith = ({1'b0,logic} + cin);
if(((logic[(n - 1)] == 1'b0) && (arith[(n - 1)] == 1'b1)))
overflow = 1'b1;
end
else if((s == 4'd8))
begin
logic = (( ~ a) & b);
pr = (a | b);
arith = (a + ({1'b0,pr} + cin));
//if(((1'b0 == (pr[(n - 1)] ^ a[(n - 1)])) && (pr[(n - 1)] !== arith[(n - 1)])))
if(((1'b0 == (pr[(n - 1)] ^ a[(n - 1)])) && (pr[(n - 1)] != arith[(n - 1)])))
overflow = 1'b1;
end
else if((s == 4'd9))
begin
logic = (a ^ b);
arith = (a + ({1'b0,b} + cin));
//if(((1'b0 == (a[(n - 1)] ^ b[(n - 1)])) && (a[(n - 1)] !== arith[(n - 1)])))
if(((1'b0 == (a[(n - 1)] ^ b[(n - 1)])) && (a[(n - 1)] != arith[(n - 1)])))
overflow = 1'b1;
end
else if((s == 4'd10))
begin
logic = b;
pr = (a & ( ~ b));
pr1 = (a | b);
arith = (pr + ({1'b0,pr1} + cin));
//if(((1'b0 == (pr[(n - 1)] ^ b[(n - 1)])) && (pr[(n - 1)] !== arith[(n - 1)])))
if(((1'b0 == (pr[(n - 1)] ^ b[(n - 1)])) && (pr[(n - 1)] != arith[(n - 1)])))
overflow = 1'b1;
end
else if((s == 4'd11))
begin
logic = (a | b);
arith = ({1'b0,logic} + cin);
if(((logic[(n - 1)] == 1'b0) && (arith[(n - 1)] == 1'b1)))
overflow = 1'b1;
end
else if((s == 4'd12))
begin
logic = 128'b0;
arith = (a + ({1'b0,a} + cin));
//if((a[(n - 1)] !== arith[(n - 1)]))
if((a[(n - 1)] != arith[(n - 1)]))
overflow = 1'b1;
end
else if((s == 4'd13))
begin
logic = (a & ( ~ b));
pr = (a & b);
arith = (pr + ({1'b0,a} + cin));
//if(((1'b0 == (pr[(n - 1)] ^ a[(n - 1)])) && (pr[(n - 1)] !== arith[(n - 1)])))
if(((1'b0 == (pr[(n - 1)] ^ a[(n - 1)])) && (pr[(n - 1)] != arith[(n - 1)])))
overflow = 1'b1;
end
else if((s == 4'd14))
begin
logic = (a & b);
pr = (a & ( ~ b));
arith = (pr + ({1'b0,a} + cin));
//if(((1'b0 == (pr[(n - 1)] ^ a[(n - 1)])) && (pr[(n - 1)] !== arith[(n - 1)])))
if(((1'b0 == (pr[(n - 1)] ^ a[(n - 1)])) && (pr[(n - 1)] != arith[(n - 1)])))
overflow = 1'b1;
end
else if((s == 4'd15))
begin
logic = a;
arith = ({1'b0,a} + cin);
if(((logic[(n - 1)] == 1'b0) && (arith[(n - 1)] == 1'b1)))
overflow = 1'b1;
end
else
begin
logic = 128'bX;
arith = 128'bX;
end
if((m == 1'b0))
begin
cout = 1'b0;
out = logic;
overflow = 1'b0;
end
else if((m == 1'b1))
begin
cout = arith[n];
out = arith[(n - 1):0];
//if((arith[(n - 1)] === 1'bx))
if((arith[(n - 1)] == 1'bx))
begin
overflow = 1'bx;
cout = 1'bx;
end
//else if(( ! ((( & out) === 1'b0) || (( | out) === 1'b1))))
else if(( ! ((( & out) == 1'b0) || (( | out) == 1'b1))))
begin
overflow = 1'bx;
cout = 1'bx;
end
end
else
begin
cout = 1'bX;
out = 128'bX;
end
end
endmodule
//------------------------------------------------------------
// Copyright 1992, 1993 Cascade Design Automation Corporation.
//------------------------------------------------------------
module buff(IN0,Y);
parameter N = 32;
parameter DPFLAG = 1;
parameter GROUP = "dpath1";
parameter BUFFER_SIZE = "DEFAULT";
parameter
d_Y = 1;
input [(N - 1):0] IN0;
output [(N - 1):0] Y;
wire [(N - 1):0] IN0_temp;
reg [(N - 1):0] Y_temp;
assign IN0_temp = IN0|IN0;
assign #(d_Y) Y = Y_temp;
always
@(IN0_temp)
Y_temp = IN0_temp;
endmodule
//------------------------------------------------------------
// Copyright 1992, 1993 Cascade Design Automation Corporation.
//------------------------------------------------------------
module dff_cq(CLK,CLR,D,Q,QBAR);
parameter N = 32;
parameter DPFLAG = 1;
parameter GROUP = "dpath1";
parameter BUFFER_SIZE = "DEFAULT";
parameter
d_Q = 1,
d_QBAR = 1;
input CLK;
input CLR;
input [(N - 1):0] D;
output [(N - 1):0] Q;
output [(N - 1):0] QBAR;
wire [(N - 1):0] D_temp;
wire [(N - 1):0] Q_temp;
reg [(N - 1):0] QBAR_temp;
supply0 GND;
supply1 VDD;
assign D_temp = D|D;
assign #(d_Q) Q = Q_temp;
assign #(d_QBAR) QBAR = QBAR_temp;
always
@(Q_temp)
QBAR_temp = ( ~ Q_temp);
dff_generic #(N) inst1 (CLK,CLR,D_temp,GND,VDD,VDD,GND,Q_temp);
wire [127:0] D_tcheck = D;
specify
specparam
t_hold_D = 0,
t_setup_D = 0,
t_width_CLK = 0,
t_width_CLR = 0;
$hold(posedge CLK , D_tcheck , t_hold_D);
$setup(D_tcheck , posedge CLK , t_setup_D);
$width(posedge CLK , t_width_CLK);
$width(negedge CLR , t_width_CLR);
endspecify
endmodule
//------------------------------------------------------------
// Copyright 1992, 1993 Cascade Design Automation Corporation.
//------------------------------------------------------------
module dff_cq5(CLK,CLR,D,Q,QBAR);
parameter N = 5;
parameter DPFLAG = 1;
parameter GROUP = "dpath1";
parameter BUFFER_SIZE = "DEFAULT";
parameter
d_Q = 1,
d_QBAR = 1;
input CLK;
input CLR;
input [(N - 1):0] D;
output [(N - 1):0] Q;
output [(N - 1):0] QBAR;
wire [(N - 1):0] D_temp;
wire [(N - 1):0] Q_temp;
reg [(N - 1):0] QBAR_temp;
supply0 GND;
supply1 VDD;
assign D_temp = D|D;
assign #(d_Q) Q = Q_temp;
assign #(d_QBAR) QBAR = QBAR_temp;
always
@(Q_temp)
QBAR_temp = ( ~ Q_temp);
dff_generic #(N) inst1 (CLK,CLR,D_temp,GND,VDD,VDD,GND,Q_temp);
wire [127:0] D_tcheck = D;
specify
specparam
t_hold_D = 0,
t_setup_D = 0,
t_width_CLK = 0,
t_width_CLR = 0;
$hold(posedge CLK , D_tcheck , t_hold_D);
$setup(D_tcheck , posedge CLK , t_setup_D);
$width(posedge CLK , t_width_CLK);
$width(negedge CLR , t_width_CLR);
endspecify
endmodule
//------------------------------------------------------------
// Copyright 1992, 1993 Cascade Design Automation Corporation.
//------------------------------------------------------------
module dff_generic(CLK,CLR,D,HOLD,PRE,SCANIN,TEST,Q);
parameter N = 8;
input CLK;
input CLR;
input [(N - 1):0] D;
input HOLD;
input PRE;
input SCANIN;
input TEST;
output [(N - 1):0] Q;
reg [(N - 1):0] Q;
reg [(N - 1):0] temp;
always
@(posedge CLK)
begin
if(((CLR == 1'b0) && (PRE == 1'b1)))
begin
Q = 128'b0;
end
else if(((PRE == 1'b0) && (CLR == 1'b1)))
begin
Q = ( ~ 128'b0);
end
// else if(((CLR !== 1'b1) || (PRE !== 1'b1)))
// begin
// Q = 128'bx;
// end
// end
// always
// @(posedge CLK)
// begin
else if(((PRE == 1'b1) && (CLR == 1'b1)))
begin
if((TEST == 1'b0))
begin
case(HOLD)
1'b0 : begin
Q = D;
end
1'b1 : begin
end
default:
Q = 128'bx;
endcase
end
else if((TEST == 1'b1))
begin
Q = (Q << 1);
Q[0] = SCANIN;
end
else
Q = 128'bx;
end
end
endmodule
/*************************************************************************
* FILE: dlx_modules.v
* Written By: Michael J. Kelley
* Written On: December 18, 1995
* Updated By: Michael J. Kelley
* Updated On: March 4, 1996
*
* Description:
* This file contains the hardware description of the control logic
* for each of the 5 stages of the DLX pipeline
*************************************************************************
*/
//`include "/l/users/mkelley/DLX/verilog/dlx.defines"
//`include "./dlx.defines"
//*************************************************************************
//ADD THE IFCtrl AND IDCtrl MODULES HERE..............
module IFCtrl (
IR2, // Instruction that is being decoded in Stage II
Equal, // Result from the equal comparator in Stage II
MRST, // Reset signal for CPU
PCMuxSelect, // Select Signals for the PCMux in Stage I
PCVector // Exception Vectors
);
/*************************************************************************
* Parameter Declarations
*************************************************************************
*/
input [`WordSize] IR2;
input Equal;
input MRST;
output [1:0] PCMuxSelect;
output [`WordSize] PCVector;
reg [1:0] PCMuxSelect;
reg ifBranch;
always @(IR2 or Equal or MRST)
begin
PCMuxSelect <= 2'b00;
casex({ IR2[`OP], IR2[`OPx], Equal, MRST})
{ `J, 6'bxxxxxx, 1'bx, 1'b1}: PCMuxSelect <= 2'b01;
{ `JAL, 6'bxxxxxx, 1'bx, 1'b1}: PCMuxSelect <= 2'b01;
{ `BEQZ, 6'bxxxxxx, 1'b1, 1'b1}: PCMuxSelect <= 2'b01;
{ `BNEZ, 6'bxxxxxx, 1'b0, 1'b1}: PCMuxSelect <= 2'b01;
{ `RFE, 6'bxxxxxx, 1'bx, 1'bx}: PCMuxSelect <= 2'b10;
{ `TRAP, 6'bxxxxxx, 1'bx, 1'bx}: PCMuxSelect <= 2'b10;
{ `JR, 6'bxxxxxx, 1'bx, 1'b1}: PCMuxSelect <= 2'b11;
{ `JALR, 6'bxxxxxx, 1'bx, 1'b1}: PCMuxSelect <= 2'b11;
{6'bxxxxxx, `TRAP2, 1'bx, 1'bx}: PCMuxSelect <= 2'b10;
{6'bxxxxxx, 6'bxxxxxx, 1'bx, 1'b0}: PCMuxSelect <= 2'b10;
default: PCMuxSelect <= 2'b00;
endcase
end
assign PCVector[`WordSize] = 32'h00000000;
endmodule
module IDCtrl (
IR2, // Instruction that is being decoded in Stage II
PCAddMuxSelect // Select Signals for the PCAddMux in Stage II
);
/*************************************************************************
* Parameter Declarations
*************************************************************************
*/
input [`WordSize] IR2;
output [1:0] PCAddMuxSelect;
reg [1:0] PCAddMuxSelect;
always @(IR2)
begin
PCAddMuxSelect <= 2'b00;
case(IR2[`OP])
`BEQZ : PCAddMuxSelect <= 2'b00;
`BNEZ : PCAddMuxSelect <= 2'b00;
`J : PCAddMuxSelect <= 2'b01;
`JAL : PCAddMuxSelect <= 2'b01;
`JR : PCAddMuxSelect <= 2'b10;
`JALR : PCAddMuxSelect <= 2'b10;
default : PCAddMuxSelect <= 2'b00;
endcase
end
endmodule
//**********************************************************************
//**********************************************************************
module EXCtrl (
IR3, // Instruction that is being decoded in stage II
IR4,
IR5,
ShiftAmount,
DestinationMuxSelect,
DataWriteMuxSelect,
ALUSelect,
ShiftSelect,
ALUorShiftMuxSelect,
SourceMuxSelect,
TargetMuxSelect,
CompareMux1Select,
CompareMux2Select,
CompareResultMuxSelect
);
/*************************************************************************
* Parameter Declarations
*************************************************************************
*/
input [`WordSize] IR3;
input [`WordSize] IR4;
input [`WordSize] IR5;
input [`WordSize] ShiftAmount;
output [1:0] DestinationMuxSelect;
output DataWriteMuxSelect;
output [5:0] ALUSelect;
output [4:0] ShiftSelect;
output [1:0] ALUorShiftMuxSelect;
output [1:0] SourceMuxSelect;
output [1:0] TargetMuxSelect;
output [1:0] CompareMux1Select;
output [1:0] CompareMux2Select;
output [1:0] CompareResultMuxSelect;
reg [1:0] DestinationMuxSelect;
reg DataWriteMuxSelect;
reg [5:0] ALUSelect;
reg [4:0] ShiftSelect;
reg [1:0] ALUorShiftMuxSelect;
reg [1:0] SourceMuxSelect;
reg [1:0] TargetMuxSelect;
reg [1:0] CompareMux1Select;
reg [1:0] CompareMux2Select;
reg [1:0] CompareResultMuxSelect;
reg [4:0] SourceReg;
reg [4:0] TargetReg;
reg [4:0] IR4WriteReg;
reg [4:0] IR5WriteReg;
reg [1:0] Immediate;
always @(IR3[`OP] or IR3[`OPx] or IR3[`RS] or IR3[`RT] or ShiftAmount[4:0])
begin
casex({IR3[`OP], IR3[`OPx]})
{`SPECIAL, `ADD}:
begin
ALUSelect = 6'b100110;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b01;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b01;
end
{`SPECIAL, `ADDU}:
begin
ALUSelect = 6'b100110;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b01;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b01;
end
{`SPECIAL, `SUB}:
begin
ALUSelect = 6'b011011;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b01;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b01;
end
{`SPECIAL, `SUBU}:
begin
ALUSelect = 6'b011011;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b01;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b01;
end
{`SPECIAL, `AND}:
begin
ALUSelect = 6'b111000;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b01;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b01;
end
{`SPECIAL, `OR}:
begin
ALUSelect = 6'b101100;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b01;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b01;
end
{`SPECIAL, `XOR}:
begin
ALUSelect = 6'b100100;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b01;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b01;
end
{`SPECIAL, `SLL}:
begin
ALUSelect = `DC6;
ShiftSelect = ShiftAmount[4:0];
ALUorShiftMuxSelect = 2'b01;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b01;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b01;
end
{`SPECIAL, `SRL}:
begin
ALUSelect = `DC6;
ShiftSelect = ShiftAmount[4:0];
ALUorShiftMuxSelect = 2'b10;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b01;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b01;
end
{`SPECIAL, `SRA}:
begin
ALUSelect = `DC6;
ShiftSelect = ShiftAmount[4:0];
ALUorShiftMuxSelect = 2'b11;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b01;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b01;
end
{`SPECIAL, `TRAP}:
begin
ALUSelect = `DC6;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = `DC2;
SourceReg = `R0;
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b01;
end
{`SPECIAL, `SEQ}:
begin
ALUSelect = 6'b011011;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b01;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = `DC2;
CompareMux2Select = 2'b01;
CompareResultMuxSelect = 2'b01;
Immediate = 2'b01;
end
{`SPECIAL, `SNE}:
begin
ALUSelect = 6'b011011;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b01;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = `DC2;
CompareMux2Select = 2'b10;
CompareResultMuxSelect = 2'b01;
Immediate = 2'b01;
end
{`SPECIAL, `SLT}:
begin
ALUSelect = 6'b011011;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b01;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = 2'b00;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b00;
Immediate = 2'b01;
end
{`SPECIAL, `SGT}:
begin
ALUSelect = 6'b011011;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b01;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = `DC2;
CompareMux2Select = 2'b00;
CompareResultMuxSelect = 2'b01;
Immediate = 2'b01;
end
{`SPECIAL, `SLE}:
begin
ALUSelect = 6'b011011;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b01;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = 2'b01;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b00;
Immediate = 2'b01;
end
{`SPECIAL, `SGE}:
begin
ALUSelect = 6'b011011;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b01;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = 2'b10;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b00;
Immediate = 2'b01;
end
{`J, `DC6}:
begin
ALUSelect = `DC6;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = `DC2;
SourceReg = `R0;
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`JAL, `DC6}:
begin
ALUSelect = 6'b111100;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b10;
SourceReg = `R0;
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`BEQZ, `DC6}:
begin
//ALUSelect = `DC6;
ALUSelect = 6'b000100;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = `DC2;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`BNEZ, `DC6}:
begin
ALUSelect = `DC6;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = `DC2;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`ADDI, `DC6}:
begin
ALUSelect = 6'b100110;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`ADDUI, `DC6}:
begin
ALUSelect = 6'b100110;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`SUBI, `DC6}:
begin
ALUSelect = 6'b011011;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`SUBUI, `DC6}:
begin
ALUSelect = 6'b011011;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`ANDI, `DC6}:
begin
ALUSelect = 6'b111000;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`ORI, `DC6}:
begin
ALUSelect = 6'b101100;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`XORI, `DC6}:
begin
ALUSelect = 6'b100100;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`LHI, `DC6}:
begin
ALUSelect = `DC6;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = `R0;
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b11;
Immediate = 2'b10;
end
{`RFE, `DC6}:
begin
ALUSelect = `DC6;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = `DC2;
SourceReg = `R0;
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`TRAP, `DC6}:
begin
ALUSelect = `DC6;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = `DC2;
SourceReg = `R0;
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b01;
end
{`JR, `DC6}:
begin
ALUSelect = `DC6;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = `DC2;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b01;
end
{`JALR, `DC6}:
begin
ALUSelect = 6'b111100;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b10;
SourceReg = `R0;
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`SEQI, `DC6}:
begin
ALUSelect = 6'b011011;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = 2'b01;
CompareResultMuxSelect = 2'b01;
Immediate = 2'b10;
end
{`SNEI, `DC6}:
begin
ALUSelect = 6'b011011;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = 2'b10;
CompareResultMuxSelect = 2'b01;
Immediate = 2'b10;
end
{`SLTI, `DC6}:
begin
ALUSelect = 6'b011011;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = 2'b00;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b00;
Immediate = 2'b10;
end
{`SGTI, `DC6}:
begin
ALUSelect = 6'b011011;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = 2'b00;
CompareResultMuxSelect = 2'b01;
Immediate = 2'b10;
end
{`SLEI, `DC6}:
begin
ALUSelect = 6'b011011;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = 2'b01;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b00;
Immediate = 2'b10;
end
{`SGEI, `DC6}:
begin
ALUSelect = 6'b011011;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = 2'b00;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = 2'b10;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b00;
Immediate = 2'b10;
end
{`SLLI, `DC6}:
begin
ALUSelect = `DC6;
ShiftSelect = ShiftAmount[4:0];
ALUorShiftMuxSelect = 2'b01;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`SRLI, `DC6}:
begin
ALUSelect = `DC6;
ShiftSelect = ShiftAmount[4:0];
ALUorShiftMuxSelect = 2'b10;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`SRAI, `DC6}:
begin
ALUSelect = `DC6;
ShiftSelect = ShiftAmount[4:0];
ALUorShiftMuxSelect = 2'b11;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`LB, `DC6}:
begin
ALUSelect = `DC6;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`LH, `DC6}:
begin
ALUSelect = `DC6;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`LW, `DC6}:
begin
ALUSelect = 6'b101011; // big change `DC6
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`LBU, `DC6}:
begin
ALUSelect = `DC6;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`LHU, `DC6}:
begin
ALUSelect = `DC6;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = `DC1;
DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`SB, `DC6}:
begin
ALUSelect = `DC6;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = 1'b0;
DestinationMuxSelect = `DC2;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`SH, `DC6}:
begin
ALUSelect = `DC6;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = 1'b0;
DestinationMuxSelect = `DC2;
SourceReg = IR3[`RS];
TargetReg = `R0;
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
{`SW, `DC6}:
begin
ALUSelect = 6'b100110; // big change `DC6
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = 1'b0; // change from 0
DestinationMuxSelect = `DC2;
//DestinationMuxSelect = 2'b00;
SourceReg = IR3[`RS];
TargetReg = `R0;
//TargetReg = IR3[`RT]; // another big change
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
default:
begin
ALUSelect = `DC6;
ShiftSelect = `DC5;
ALUorShiftMuxSelect = `DC2;
DataWriteMuxSelect = 1'b1;
DestinationMuxSelect = `DC2;
SourceReg = IR3[`RS];
TargetReg = IR3[`RT];
CompareMux1Select = `DC2;
CompareMux2Select = `DC2;
CompareResultMuxSelect = 2'b10;
Immediate = 2'b10;
end
endcase
end
always @(IR4[`OP] or IR4[`OPx] or IR4[`RD] or IR4[`RT])
begin
casex({IR4[`OP], IR4[`OPx]})
{`SPECIAL, `ADD}: IR4WriteReg = IR4[`RD];
{`SPECIAL, `ADDU}: IR4WriteReg = IR4[`RD];
{`SPECIAL, `SUB}: IR4WriteReg = IR4[`RD];
{`SPECIAL, `SUBU}: IR4WriteReg = IR4[`RD];
{`SPECIAL, `AND}: IR4WriteReg = IR4[`RD];
{`SPECIAL, `OR}: IR4WriteReg = IR4[`RD];
{`SPECIAL, `XOR}: IR4WriteReg = IR4[`RD];
{`SPECIAL, `SLL}: IR4WriteReg = IR4[`RD];
{`SPECIAL, `SRL}: IR4WriteReg = IR4[`RD];
{`SPECIAL, `SRA}: IR4WriteReg = IR4[`RD];
{`SPECIAL, `SEQ}: IR4WriteReg = IR4[`RD];
{`SPECIAL, `SNE}: IR4WriteReg = IR4[`RD];
{`SPECIAL, `SLT}: IR4WriteReg = IR4[`RD];
{`SPECIAL, `SGT}: IR4WriteReg = IR4[`RD];
{`SPECIAL, `SLE}: IR4WriteReg = IR4[`RD];
{`SPECIAL, `SGE}: IR4WriteReg = IR4[`RD];
{`ADDI, `DC6}: IR4WriteReg = IR4[`RT];
{`ADDUI, `DC6}: IR4WriteReg = IR4[`RT];
{`SUBI, `DC6}: IR4WriteReg = IR4[`RT];
{`SUBUI, `DC6}: IR4WriteReg = IR4[`RT];
{`ANDI, `DC6}: IR4WriteReg = IR4[`RT];
{`ORI, `DC6}: IR4WriteReg = IR4[`RT];
{`XORI, `DC6}: IR4WriteReg = IR4[`RT];
{`LHI, `DC6}: IR4WriteReg = IR4[`RT];
{`JALR, `DC6}: IR4WriteReg = IR4[`RD];
{`SEQI, `DC6}: IR4WriteReg = IR4[`RT];
{`SNEI, `DC6}: IR4WriteReg = IR4[`RT];
{`SLTI, `DC6}: IR4WriteReg = IR4[`RT];
{`SGTI, `DC6}: IR4WriteReg = IR4[`RT];
{`SLEI, `DC6}: IR4WriteReg = IR4[`RT];
{`SGEI, `DC6}: IR4WriteReg = IR4[`RT];
{`SLLI, `DC6}: IR4WriteReg = IR4[`RT];
{`SRLI, `DC6}: IR4WriteReg = IR4[`RT];
{`SRAI, `DC6}: IR4WriteReg = IR4[`RT];
{`LB, `DC6}: IR4WriteReg = IR4[`RT];
{`LH, `DC6}: IR4WriteReg = IR4[`RT];
{`LW, `DC6}: IR4WriteReg = IR4[`RT];
{`LBU, `DC6}: IR4WriteReg = IR4[`RT];
{`LHU, `DC6}: IR4WriteReg = IR4[`RT];
default: IR4WriteReg = `R0;
endcase
end
always @(IR5[`OP] or IR5[`OPx] or IR5[`RD] or IR5[`RT])
begin
casex({IR5[`OP], IR5[`OPx]})
{`SPECIAL, `ADD}: IR5WriteReg = IR5[`RD];
{`SPECIAL, `ADDU}: IR5WriteReg = IR5[`RD];
{`SPECIAL, `SUB}: IR5WriteReg = IR5[`RD];
{`SPECIAL, `SUBU}: IR5WriteReg = IR5[`RD];
{`SPECIAL, `AND}: IR5WriteReg = IR5[`RD];
{`SPECIAL, `OR}: IR5WriteReg = IR5[`RD];
{`SPECIAL, `XOR}: IR5WriteReg = IR5[`RD];
{`SPECIAL, `SLL}: IR5WriteReg = IR5[`RD];
{`SPECIAL, `SRL}: IR5WriteReg = IR5[`RD];
{`SPECIAL, `SRA}: IR5WriteReg = IR5[`RD];
{`SPECIAL, `SEQ}: IR5WriteReg = IR5[`RD];
{`SPECIAL, `SNE}: IR5WriteReg = IR5[`RD];
{`SPECIAL, `SLT}: IR5WriteReg = IR5[`RD];
{`SPECIAL, `SGT}: IR5WriteReg = IR5[`RD];
{`SPECIAL, `SLE}: IR5WriteReg = IR5[`RD];
{`SPECIAL, `SGE}: IR5WriteReg = IR5[`RD];
{`ADDI, `DC6}: IR5WriteReg = IR5[`RT];
{`ADDUI, `DC6}: IR5WriteReg = IR5[`RT];
{`SUBI, `DC6}: IR5WriteReg = IR5[`RT];
{`SUBUI, `DC6}: IR5WriteReg = IR5[`RT];
{`ANDI, `DC6}: IR5WriteReg = IR5[`RT];
{`ORI, `DC6}: IR5WriteReg = IR5[`RT];
{`XORI, `DC6}: IR5WriteReg = IR5[`RT];
{`LHI, `DC6}: IR5WriteReg = IR5[`RT];
{`JALR, `DC6}: IR5WriteReg = IR5[`RD];
{`SEQI, `DC6}: IR5WriteReg = IR5[`RT];
{`SNEI, `DC6}: IR5WriteReg = IR5[`RT];
{`SLTI, `DC6}: IR5WriteReg = IR5[`RT];
{`SGTI, `DC6}: IR5WriteReg = IR5[`RT];
{`SLEI, `DC6}: IR5WriteReg = IR5[`RT];
{`SGEI, `DC6}: IR5WriteReg = IR5[`RT];
{`SLLI, `DC6}: IR5WriteReg = IR5[`RT];
{`SRLI, `DC6}: IR5WriteReg = IR5[`RT];
{`SRAI, `DC6}: IR5WriteReg = IR5[`RT];
{`LB, `DC6}: IR5WriteReg = IR5[`RT];
{`LH, `DC6}: IR5WriteReg = IR5[`RT];
{`LW, `DC6}: IR5WriteReg = IR5[`RT];
{`LBU, `DC6}: IR5WriteReg = IR5[`RT];
{`LHU, `DC6}: IR5WriteReg = IR5[`RT];
default: IR5WriteReg = `R0;
endcase
end
always @(SourceReg or TargetReg or IR4WriteReg or IR5WriteReg or Immediate)
begin
casex({SourceReg, IR4WriteReg, IR5WriteReg})
{`R0, `DC5, `DC5}: SourceMuxSelect = 2'b11;
{SourceReg, SourceReg, `DC5}: SourceMuxSelect = 2'b10;
{SourceReg, `DC5, SourceReg}: SourceMuxSelect = 2'b00;
default: SourceMuxSelect = 2'b01;
endcase
casex({TargetReg, IR4WriteReg, IR5WriteReg})
{`R0, `DC5, `DC5}:
// my additions
//if (IR3[`OP] == `SW)
//begin
//TargetMuxSelect = 2'b01;
//end
//else
//begin
TargetMuxSelect = Immediate;
//end
{TargetReg, TargetReg, `DC5}: TargetMuxSelect = 2'b11;
{TargetReg, `DC5, TargetReg}: TargetMuxSelect = 2'b00;
default: TargetMuxSelect = Immediate;
endcase
end
endmodule
module MemCtrl (
IR4,
DRead,
DWrite
);
/*************************************************************************
* Parameter Declarations
*************************************************************************
*/
input [`WordSize] IR4;
output DRead;
output DWrite;
reg DRead;
reg DWrite;
always @(IR4[`OP] or IR4[`OPx])
begin
casex({IR4[`OP], IR4[`OPx]})
{`LB, `DC6}:
begin
DRead = `LogicOne;
DWrite = `LogicZero;
end
{`LBU, `DC6}:
begin
DRead = `LogicOne;
DWrite = `LogicZero;
end
{`LH, `DC6}:
begin
DRead = `LogicOne;
DWrite = `LogicZero;
end
{`LHU, `DC6}:
begin
DRead = `LogicOne;
DWrite = `LogicZero;
end
{`LW, `DC6}:
begin
DRead = `LogicOne;
DWrite = `LogicZero;
end
{`SB, `DC6}:
begin
DRead = `LogicZero;
DWrite = `LogicOne;
end
{`SH, `DC6}:
begin
DRead = `LogicZero;
DWrite = `LogicOne;
end
{`SW, `DC6}:
begin
DRead = `LogicZero;
DWrite = `LogicOne;
end
default:
begin
DRead = `LogicZero;
DWrite = `LogicZero;
end
endcase
end
endmodule
module WBCtrl (
IR5,
WBMuxSelect,
WriteEnable
);
/*************************************************************************
* Parameter Declarations
*************************************************************************
*/
input [`WordSize] IR5;
output WBMuxSelect;
output WriteEnable;
reg WBMuxSelect;
reg WriteEnable;
always @(IR5[`OP] or IR5[`OPx])
begin
casex({IR5[`OP], IR5[`OPx]})
{`LB, `DC6}: WBMuxSelect = 1'b0;
{`LH, `DC6}: WBMuxSelect = 1'b0;
{`LW, `DC6}: WBMuxSelect = 1'b0;
{`LBU, `DC6}: WBMuxSelect = 1'b0;
{`LHU, `DC6}: WBMuxSelect = 1'b0;
default: WBMuxSelect = 1'b1;
endcase
casex({IR5[`OP], IR5[`OPx]})
{`SPECIAL, `ADD}: WriteEnable = 1'b1;
{`SPECIAL, `ADDU}: WriteEnable = 1'b1;
{`SPECIAL, `SUB}: WriteEnable = 1'b1;
{`SPECIAL, `SUBU}: WriteEnable = 1'b1;
{`SPECIAL, `AND}: WriteEnable = 1'b1;
{`SPECIAL, `OR}: WriteEnable = 1'b1;
{`SPECIAL, `XOR}: WriteEnable = 1'b1;
{`SPECIAL, `SLL}: WriteEnable = 1'b1;
{`SPECIAL, `SRL}: WriteEnable = 1'b1;
{`SPECIAL, `SRA}: WriteEnable = 1'b1;
{`SPECIAL, `SEQ}: WriteEnable = 1'b1;
{`SPECIAL, `SNE}: WriteEnable = 1'b1;
{`SPECIAL, `SLT}: WriteEnable = 1'b1;
{`SPECIAL, `SGT}: WriteEnable = 1'b1;
{`SPECIAL, `SLE}: WriteEnable = 1'b1;
{`SPECIAL, `SGE}: WriteEnable = 1'b1;
{`ADDI, `DC6}: WriteEnable = 1'b1;
{`ADDUI, `DC6}: WriteEnable = 1'b1;
{`SUBI, `DC6}: WriteEnable = 1'b1;
{`SUBUI, `DC6}: WriteEnable = 1'b1;
{`ANDI, `DC6}: WriteEnable = 1'b1;
{`ORI, `DC6}: WriteEnable = 1'b1;
{`XORI, `DC6}: WriteEnable = 1'b1;
{`LHI, `DC6}: WriteEnable = 1'b1;
{`JAL, `DC6}: WriteEnable = 1'b1;
{`JALR, `DC6}: WriteEnable = 1'b1;
{`SEQI, `DC6}: WriteEnable = 1'b1;
{`SNEI, `DC6}: WriteEnable = 1'b1;
{`SLTI, `DC6}: WriteEnable = 1'b1;
{`SGTI, `DC6}: WriteEnable = 1'b1;
{`SLEI, `DC6}: WriteEnable = 1'b1;
{`SGEI, `DC6}: WriteEnable = 1'b1;
{`SLLI, `DC6}: WriteEnable = 1'b1;
{`SRLI, `DC6}: WriteEnable = 1'b1;
{`SRAI, `DC6}: WriteEnable = 1'b1;
{`LB, `DC6}: WriteEnable = 1'b1;
{`LH, `DC6}: WriteEnable = 1'b1;
{`LW, `DC6}: WriteEnable = 1'b1;
{`LBU, `DC6}: WriteEnable = 1'b1;
{`LHU, `DC6}: WriteEnable = 1'b1;
default: WriteEnable = 1'b0;
endcase
end
endmodule
//------------------------------------------------------------
// Copyright 1992, 1993 Cascade Design Automation Corporation.
//------------------------------------------------------------
module newmux2(IN0,IN1,S0,Y);
parameter N = 32;
parameter DPFLAG = 1;
parameter GROUP = "dpath1";
parameter BUFFER_SIZE = "DEFAULT";
parameter
d_Y = 1;
input [(N - 1):0] IN0;
input [(N - 1):0] IN1;
input S0;
output [(N - 1):0] Y;
wire [(N - 1):0] IN0_temp;
wire [(N - 1):0] IN1_temp;
reg [(N - 1):0] Y_temp;
reg [(N - 1):0] XX;
assign IN0_temp = IN0|IN0;
assign IN1_temp = IN1|IN1;
assign #(d_Y) Y = Y_temp;
/*
initial
XX = 128'bx;
*/
always
@(IN0_temp or IN1_temp or S0)
begin
if((S0 == 1'b0))
Y_temp = IN0_temp;
else if((S0 == 1'b1))
Y_temp = IN1_temp;
else
Y_temp = (((IN0_temp ^ IN1_temp) & XX) | IN0_temp);
end
endmodule
//------------------------------------------------------------
// Copyright 1992, 1993 Cascade Design Automation Corporation.
//------------------------------------------------------------
module newmux3(IN0,IN1,IN2,S0,S1,Y);
parameter N = 32;
parameter DPFLAG = 1;
parameter GROUP = "dpath1";
parameter BUFFER_SIZE = "DEFAULT";
parameter
d_Y = 1;
input [(N - 1):0] IN0;
input [(N - 1):0] IN1;
input [(N - 1):0] IN2;
input S0;
input S1;
output [(N - 1):0] Y;
wire [(N - 1):0] IN0_temp;
wire [(N - 1):0] IN1_temp;
wire [(N - 1):0] IN2_temp;
reg [(N - 1):0] Y_temp;
reg [(N - 1):0] XX;
assign IN0_temp = IN0|IN0;
assign IN1_temp = IN1|IN1;
assign IN2_temp = IN2|IN2;
assign #(d_Y) Y = Y_temp;
/*
initial
XX = 128'bx;
*/
always
@(IN0_temp or IN1_temp or IN2_temp or S0 or S1)
begin
if(((S1 == 1'b0) && (S0 == 1'b0)))
Y_temp = IN0_temp;
else if(((S1 == 1'b0) && (S0 == 1'b1)))
Y_temp = IN1_temp;
else if((S1 == 1'b1))
Y_temp = IN2_temp;
else
Y_temp = (((((IN0_temp | IN1_temp) | IN2_temp) ^ ((IN0_temp & IN1_temp) & IN2_temp)) & XX) ^ IN0_temp);
end
endmodule
//------------------------------------------------------------
// Copyright 1992, 1993 Cascade Design Automation Corporation.
//------------------------------------------------------------
module newmux3_1(IN0,IN1,IN2,S0,S1,Y);
parameter N = 1;
parameter DPFLAG = 1;
parameter GROUP = "dpath1";
parameter BUFFER_SIZE = "DEFAULT";
parameter
d_Y = 1;
input [(N - 1):0] IN0;
input [(N - 1):0] IN1;
input [(N - 1):0] IN2;
input S0;
input S1;
output [(N - 1):0] Y;
wire [(N - 1):0] IN0_temp;
wire [(N - 1):0] IN1_temp;
wire [(N - 1):0] IN2_temp;
reg [(N - 1):0] Y_temp;
reg [(N - 1):0] XX;
assign IN0_temp = IN0|IN0;
assign IN1_temp = IN1|IN1;
assign IN2_temp = IN2|IN2;
assign #(d_Y) Y = Y_temp;
/*
initial
XX = 128'bx;
*/
always
@(IN0_temp or IN1_temp or IN2_temp or S0 or S1)
begin
if(((S1 == 1'b0) && (S0 == 1'b0)))
Y_temp = IN0_temp;
else if(((S1 == 1'b0) && (S0 == 1'b1)))
Y_temp = IN1_temp;
else if((S1 == 1'b1))
Y_temp = IN2_temp;
else
Y_temp = (((((IN0_temp | IN1_temp) | IN2_temp) ^ ((IN0_temp & IN1_temp) & IN2_temp)) & XX) ^ IN0_temp);
end
endmodule
//------------------------------------------------------------
// Copyright 1992, 1993 Cascade Design Automation Corporation.
//------------------------------------------------------------
module newmux3_5(IN0,IN1,IN2,S0,S1,Y);
parameter N = 5;
parameter DPFLAG = 1;
parameter GROUP = "dpath1";
parameter BUFFER_SIZE = "DEFAULT";
parameter
d_Y = 1;
input [(N - 1):0] IN0;
input [(N - 1):0] IN1;
input [(N - 1):0] IN2;
input S0;
input S1;
output [(N - 1):0] Y;
wire [(N - 1):0] IN0_temp;
wire [(N - 1):0] IN1_temp;
wire [(N - 1):0] IN2_temp;
reg [(N - 1):0] Y_temp;
reg [(N - 1):0] XX;
assign IN0_temp = IN0|IN0;
assign IN1_temp = IN1|IN1;
assign IN2_temp = IN2|IN2;
assign #(d_Y) Y = Y_temp;
/*
initial
XX = 128'bx;
*/
always
@(IN0_temp or IN1_temp or IN2_temp or S0 or S1)
begin
if(((S1 == 1'b0) && (S0 == 1'b0)))
Y_temp = IN0_temp;
else if(((S1 == 1'b0) && (S0 == 1'b1)))
Y_temp = IN1_temp;
else if((S1 == 1'b1))
Y_temp = IN2_temp;
else
Y_temp = (((((IN0_temp | IN1_temp) | IN2_temp) ^ ((IN0_temp & IN1_temp) & IN2_temp)) & XX) ^ IN0_temp);
end
endmodule
//------------------------------------------------------------
// Copyright 1992, 1993 Cascade Design Automation Corporation.
//------------------------------------------------------------
module newmux4(IN0,IN1,IN2,IN3,S0,S1,Y);
parameter N = 32;
parameter DPFLAG = 1;
parameter GROUP = "dpath1";
parameter BUFFER_SIZE = "DEFAULT";
parameter
d_Y = 1;
input [(N - 1):0] IN0;
input [(N - 1):0] IN1;
input [(N - 1):0] IN2;
input [(N - 1):0] IN3;
input S0;
input S1;
output [(N - 1):0] Y;
wire [(N - 1):0] IN0_temp;
wire [(N - 1):0] IN1_temp;
wire [(N - 1):0] IN2_temp;
wire [(N - 1):0] IN3_temp;
reg [(N - 1):0] Y_temp;
reg [(N - 1):0] XX;
assign IN0_temp = IN0|IN0;
assign IN1_temp = IN1|IN1;
assign IN2_temp = IN2|IN2;
assign IN3_temp = IN3|IN3;
assign #(d_Y) Y = Y_temp;
/*
initial
XX = 128'bx;
*/
always
@(IN0_temp or IN1_temp or IN2_temp or IN3_temp or S0 or S1)
begin
if(((S1 == 1'b0) && (S0 == 1'b0)))
Y_temp = IN0_temp;
else if(((S1 == 1'b0) && (S0 == 1'b1)))
Y_temp = IN1_temp;
else if(((S1 == 1'b1) && (S0 == 1'b0)))
Y_temp = IN2_temp;
else if(((S1 == 1'b1) && (S0 == 1'b1)))
Y_temp = IN3_temp;
else
Y_temp = ((((((IN0_temp | IN1_temp) | IN2_temp) | IN3_temp) ^ (((IN0_temp & IN1_temp) & IN2_temp) & IN3_temp)) & XX) ^ IN0_temp);
end
endmodule
//------------------------------------------------------------
// Copyright 1992, 1993 Cascade Design Automation Corporation.
//------------------------------------------------------------
module regfile2r(IN0,R1,R2,RE1,RE2,W,WE,OUT1,OUT2);
parameter N = 32;
parameter WORDS = 32;
parameter M = 5;
parameter GROUP = "dpath1";
parameter BUFFER_SIZE = "DEFAULT";
parameter
d_OUT1 = 1,
d_OUT2 = 1;
input [(N - 1):0] IN0;
input [(M - 1):0] R1;
input [(M - 1):0] R2;
input RE1;
input RE2;
input [(M - 1):0] W;
input WE;
output [(N - 1):0] OUT1;
output [(N - 1):0] OUT2;
reg [(N - 1):0] OUT1_temp;
reg [(N - 1):0] OUT2_temp;
reg flag1;
reg flag2;
reg error_flag;
reg [(M - 1):0] W_old;
reg [(N - 1):0] mem_array[(WORDS - 1):0];
integer i;
assign #(d_OUT1) OUT1 = OUT1_temp;
assign #(d_OUT2) OUT2 = OUT2_temp;
always @(WE or IN0 or W)
if (WE == 1'b1) mem_array[W] = IN0 ;
always @(RE1 or R1)
if (RE1 == 1'b1) OUT1_temp = mem_array[R1] ;
always @(RE2 or R2)
if (RE2 == 1'b1) OUT2_temp = mem_array[R2] ;
endmodule
module shifter(IN0,S,S2,Y);
input [31:0] IN0;
input [4:0] S;
input [1:0] S2;
output [31:0] Y;
reg [31:0] Y;
reg [31:0] mask;
always @(IN0 or S or S2) begin
mask = 32'hFFFFFFFF ;
if((IN0[31] == 1) && (S2 == 2'b11)) mask = (mask >> S) ;
case(S2)
2'b01: Y = (IN0 << S); // SLL, SLLI
2'b10: Y = (IN0 >> S); // SRL, SRLI
2'b11: Y = ((IN0 >> S) | (~mask)); // SRA, SRAI
default: Y = IN0 ; // don't care
endcase
end
endmodule
// File: zero_compare
// Written By: Michael J. Kelley
// Written On: 9/15/95
// Updated By: Michael J. Kelley
// Updated On: 9/18/95
//
// Description:
//
// This module simply compares a 32-bit number against zero. It will activate
// the appropriate output lines depending on the result. The output values are
// the following:
// A < 0
// A <= 0
// A > 0
// A >= 0
// By testing these lines, one will be able to detect what A is with respect to
// zero.
module zero_compare(
A, // 32-bit number to compare to zero
A_lessthan_zero, // output is one when A < 0
A_lessthan_equal_zero, // output is one when A <= 0
A_greaterthan_equal_zero, // output is one when A >= 0
A_greaterthan_zero, // output is one when A > 0
A_equal_zero, // output is one when A == 0
A_not_equal_zero // output is one when A != 0
);
// declaring parameters
parameter DPFLAG = 0;
parameter GROUP = "AUTO";
input [31:0] A;
output A_lessthan_zero; wire A_lessthan_zero;
output A_lessthan_equal_zero; wire A_lessthan_equal_zero;
output A_greaterthan_equal_zero; wire A_greaterthan_equal_zero;
output A_greaterthan_zero; wire A_greaterthan_zero;
output A_equal_zero; wire A_equal_zero;
output A_not_equal_zero; wire A_not_equal_zero;
// A is less than zero if the most significant bit is 1.
assign A_lessthan_zero = A[31];
buff #(1,DPFLAG,GROUP)
buffer(.IN0(A[31]), .Y(A_lessthan_zero));
// A is less than or equal to zero if all the bits are zero or if the most
// significant bit is one.
assign A_lessthan_equal_zero = (!(A[0] | A[1] | A[2] | A[3] | A[4] | A[5] | A[6] |
A[7] | A[8] | A[9] | A[10] | A[11] | A[12] | A[13] | A[14] | A[15] | A[16] |
A[17] | A[18] | A[19] | A[20] | A[21] | A[22] | A[23] | A[24] | A[25] | A[26] |
A[27] | A[28] | A[29] | A[30] | A[31]) | (A[31]));
// A is greater than or equal to zero whenever the most significant bit of A is
// zero.
assign A_greaterthan_equal_zero = !(A[31]);
// A is greater than zero if at least one of the bits is one (except for the most
// significant bit).
assign A_greaterthan_zero = ((A[0] | A[1] | A[2] | A[3] | A[4] | A[5] | A[6] |
A[7] | A[8] | A[9] | A[10] | A[11] | A[12] | A[13] | A[14] | A[15] | A[16] |
A[17] | A[18] | A[19] | A[20] | A[21] | A[22] | A[23] | A[24] | A[25] | A[26] |
A[27] | A[28] | A[29] | A[30] | A[31]) & !(A[31]));
assign A_equal_zero = A_greaterthan_equal_zero && A_lessthan_equal_zero;
assign A_not_equal_zero = !A_equal_zero;
endmodule
|
`timescale 1 ns / 1 ps
`include "FFT128_CONFIG.inc"
`include "./dlx.defines"
`include "spi_defines.v"
`include "timescale.v"
// connection FFT - DLX - AES - (probably USB)-external (F - D - A)
// same clocks for all modules
// adding the securitypolicycontroller
// needs to modify the DAAddrESP to other types (FFT-DLX-AES etc)
module TOPmost(MASRST, CLKF, RSTF, EDF, STARTF, SHIFTF, DRF, DIF, RDYF, DORF, DOIF, WSIF, WRSTNF, SelectWIRF, ShiftWRF, CaptureWRF, MRSTD, DAddrED, DReadED, DWriteED, DAddrE2D, DReadE2D, DWriteE2D, DAddrE3D, DReadE3D, DWriteE3D, DAddrD, DOutD, DInD, IAddrD, IInD, IAddrED, IInED, IWriteED, WRSTND, SelectWIRD, ShiftWRD, CaptureWRD, PauseD, LDSD, LDFD, MACcalcD, MACactualD, modeA, rstA, kldA, ldA, doneA, keyA, text_inA1, text_outA, PauseA, WRSTNA, SelectWIRA, ShiftWRA, CaptureWRA,WSOA,rstS, weS, tx_selS, goS, intS, ssS, sclkS, mosiS, misoS, PauseS, resPMC, PF, PD, PM, PA, PS, DAddrSP, DOutSP, DInSP, IInSP, MRSTSP, WRSTNSP, SelectWIRSP, ShiftWRSP, CaptureWRSP, WSOSP, MRSTDAP, DB1, DB2, s1, s2, MRST11, stop, MRST12, TP11, TPE11);
`FFT128paramnb
//input [3:0] STATE1;
// for FFT
input CLKF, RSTF, EDF, STARTF, MASRST;
input [3:0] SHIFTF ;
input [nb-1:0] DRF ;
input [nb-1:0] DIF ;
output RDYF;
output [nb+3:0] DORF;
output [nb+3:0] DOIF;
input WSIF, WRSTNF, SelectWIRF, ShiftWRF, CaptureWRF;
wire SPCREQF, SPCDISF;
input MRST12;
// for DLX
input MRSTD, DReadED, DWriteED, DReadE2D, DWriteE2D, DReadE3D, DWriteE3D ;
input [`WordSize] DAddrED, DAddrE2D, DAddrE3D;
output [`WordSize] DAddrD, DOutD, DInD, IAddrD, IInD;
input WRSTND, SelectWIRD, ShiftWRD, CaptureWRD;
input MRST11;
input stop;
input [`WordSize] IInED, IAddrED;
input IWriteED;
input MACcalcD; //ideally from crypto core (MAC or simething)
input MACactualD; // actual MAC for firmwire
input PauseD;
wire SPCREQD, SPCDISD; // SPC stuff will not be inputs to module in future
input LDFD, LDSD;
// for AES
input rstA, modeA, ldA, kldA;
input [127:0] keyA;
output doneA;
output [127:0] text_outA;
output [127:0] text_inA1;
input PauseA;
wire SPCREQA, SPCDISA; // SPC stuff will not be inputs to module in future
input WRSTNA, SelectWIRA, ShiftWRA, CaptureWRA;
output WSOA;
// for the security policy controller
input MRSTSP;
output [`WordSize] DAddrSP, DOutSP, DInSP, IInSP;
input WRSTNSP, SelectWIRSP, ShiftWRSP, CaptureWRSP;
output WSOSP;
// for SPI
input rstS, weS;
input [3:0] tx_selS;
input goS;
output intS;
output ssS, sclkS, mosiS;
input misoS;
input PauseS;
wire SPCREQS, SPCDISS;
// for PMC
input resPMC;
output PF,PD,PM,PA,PS;
wire [3:0] STATE;
// other module signal definitions
// for FFT
wire OVF1F, OVF2F, WSOF;
wire [6:0] ADDRF;
wire [`WordSize] DAD1, DO1;
wire DWR1;
//DLX
// DOutED and WSID comes from FFT module
//wire [`WordSize] IAddrED, IInED; // changed this one
wire [`WordSize] DOutED1, DInED, DInE2D, DInE3D;
reg [`WordSize] DOutED, DOutE2D, DOutE3D; //** after doing simulations **//
wire DReadD, DWriteD;
wire WSID, WSOD;
wire PH; // separate clock domain for DLX
wire [`WordSize] DAD2, DO2;
wire DWR2;
// AES
wire [127:0] text_inA;
wire WSIA;
wire [`WordSize] DAD3, DO3;
wire DWR3;
// SPI
reg [31:0] dati;
wire [`SPI_DIVIDER_LEN-1:0] divider;
reg [127:0]CS;
wire [`WordSize] DAD4, DO4;
wire DWR4;
// Security Policy Controller
wire [`WordSize] DAddrESP, DOutESP, IAddrSP, IAddrESP, IInESP ;
wire DReadSP, DWriteSP, IReadSP, WSISP, PH11;
// connections between involving DAddrED, DOutD (introduce DReadED....) [done]
// DAP Port
input MRSTDAP, s1, s2;
input [31:0] DB1, DB2;
wire [31:0] DBus;
wire [1:0] Sel;
wire [31:0] TP;
wire TPE;
output reg [63:0] TP11;
output reg TPE11;
wire [31:0] TP2;
wire TPE2;
wire [31:0] TP3;
wire TPE3;
wire [31:0] TP4;
wire TPE4;
wire [31:0] TP5;
wire TPE5;
wire [31:0] TP6;
wire TPE6;
assign TP2 = TP;
assign TPE2 = TPE;
// module instantiations
FFT128wrapper F0(MASRST, CLKF, RSTF, EDF, STARTF, SHIFTF, DRF, DIF, RDYF, OVF1F, OVF2F, ADDRF, DORF, DOIF, WSIF, WRSTNF, SelectWIRF, ShiftWRF, CaptureWRF, WSOF, DWR1, DO1, DAD1, SPCREQF, SPCDISF, MRST12, DBus, Sel, TP3, TPE3);
//assign DOutED = ([DORF[15:0] DOIF[15:0]]); // check this
// **** a work around ***************** //
always @(*)
begin
if (!(DORF == 20'b0))
begin
DOutE2D[31:16] = DORF[15:0];
DOutE2D[15:0] = DOIF[15:0];
end
end
assign DOutED1[31:16] = DORF[15:0];
assign DOutED1[15:0] = DOIF[15:0];
assign WSID = WSOF;
clkgen CLKGEN(
.clk (PH)
);
together T0(
PH, MASRST, DAddrD, DAddrED, DAddrE2D, DAddrE3D, DReadD, DWriteD, DReadED, DWriteED, DReadE2D, DWriteE2D, DReadE3D, DWriteE3D, DOutD, DOutED, DOutE2D, DOutE3D, DInD, DInED, DInE2D, DInE3D, STATE, IAddrD, IAddrED, , IInD, IInED, IWriteED, MRSTD, PauseD, `LogicZero, `LogicZero, `LogicZero, , WSID, WRSTND, SelectWIRD, ShiftWRD, CaptureWRD, WSOD, DWR2, DO2, DAD2, SPCREQD, SPCDISD, LDSD, LDFD, MACcalcD, MACactualD, DBus, Sel, TP, TPE, MRST11, stop, TP5, TPE5);
//assign text_inA = ([DInED DInED DInED DInED]);
assign text_inA[127:96] = DInED;
assign text_inA[31:0] = DInED;
assign text_inA[63:32] = DInED;
assign text_inA[95:64] = DInED;
//assign text_inA[127:96] = DInED;
//assign text_inA[31:0] = 32'b1;
//assign text_inA[63:32] = 32'b1;
//assign text_inA[95:64] = 32'b1;
//assign text_inA[127:96] = 32'b1;
assign WSIA = WSOD;
assign text_inA1 = text_inA;
AEStopwrapper A0(MASRST, CLKF, modeA, rstA, kldA, ldA, doneA, keyA, text_inA, text_outA, PauseA, WSIA, WRSTNA, SelectWIRA, ShiftWRA, CaptureWRA, WSOA, DWR3, DO3, DAD3, SPCREQA, SPCDISA, MRST11, DBus, Sel, TP4, TPE4);
assign divider = 16'b1; // SCLK is 1/4 th that of CLK
always @(*)
begin
if (doneA == 1'b1)
CS = text_outA;
end
always @(*)
begin
if (tx_selS == 4'b0001)
begin
dati = CS[31:0];
end
else if (tx_selS == 4'b0010)
begin
dati = CS[63:32];
end
else if (tx_selS == 4'b0100)
begin
dati = CS[95:64];
end
else if (tx_selS == 4'b1000)
begin
dati = CS[127:96];
end
end
//spi_top ST0(MASRST, CLKF, rstS, , dati, , weS, goS, divider, tx_selS, , ,ack, , intS, ssS, sclkS, mosiS, misoS);
spi_top ST0(MASRST, CLKF, rstS, , dati, , weS, goS, divider, tx_selS, , ,ack, , intS, ssS, sclkS, mosiS, misoS, DWR4, DO4, DAD4, PauseS, SPCREQS, SPCDISS, MRST11, DBus, Sel, TP6, TPE6);
PMC PM0(MASRST, CLKF, resPMC, RSTF, STARTF, MRSTD, DReadED, DWriteED, rstA, ldA, rstS, goS, PF,PD,PM,PA,PS);
// security policy controller
assign WSISP = WSOA;
clkgen CLKGEN1(
.clk (PH11)
);
securitypolicy SP0(
PH11, MASRST, DAddrSP, DAD1, DAD2, DAD3, DAD4, , DReadSP, DWriteSP, DWR1, DWR2, DWR3, DWR4 , ,DOutSP, DO1, DO2, DO3, DO4 , , DInSP, IAddrSP, IAddrESP, IReadSP, IInSP, IInESP, MRSTSP, , , , ,WSISP, WRSTSP, SelectWIRSP, ShiftWRSP, CaptureWRSP, WSOSP,
STATE, SPCDISF, SPCDISD, SPCDISA, SPCDISS, SPCREQF, SPCREQD, SPCREQA, SPCREQS);
// Debug Access Port
DAP D1 (CLKF, MRSTDAP, s1, s2, DB1, DB2, DBus, Sel);
reg [27:0] globalcounter;
always @(posedge CLKF)
begin
if (MASRST == 1'b1)
begin
globalcounter <= 28'd0;
end
else
begin
globalcounter <= globalcounter + 28'b1;
end
end
// trace port configurations
//reg [31:0] tracebuffer [0:15];
always @(posedge CLKF)
begin
if (MASRST == 1'b1)
begin
TP11 <= 64'd0;
TPE11 <= 1'b0;
end
else if (TPE2 == 1'b1)
begin
TPE11 <= 1'b1;
TP11 <= {TP2, globalcounter, 4'b0001};
end
else if (TPE5 == 1'b1)
// assuming data memory and proc events of ineterst do not //overlap
begin
TPE11 <= 1'b1;
TP11 <= {TP5, globalcounter, 4'b0010};
end
else if (TPE3 == 1'b1)
begin
TPE11 <= 1'b1;
//TP11 <= {TP3, (globalcounter - 28'b1), 4'b0011};
TP11 <= {TP3, (globalcounter), 4'b0011};
end
else if (TPE4 == 1'b1)
begin
TPE11 <= 1'b1;
//TP11 <= {TP4, (globalcounter - 28'b1), 4'b0100};
TP11 <= {TP4, (globalcounter), 4'b0100};
end
else
begin
TP11 <= 64'd0;
TPE11 <= 1'b0;
end
end
endmodule
|
`timescale 1 ns / 1 ps
`include "FFT128_CONFIG.inc"
`include "./dlx.defines"
`include "spi_defines.v"
`include "timescale.v"
module test;
`FFT128paramnb
// FFT signals
reg MASRST;
reg CLKF, RSTF, EDF, STARTF;
reg [3:0] SHIFTF;
reg [nb-1:0] DRF;
reg [nb-1:0] DIF;
wire RDYF;
wire [nb+3:0] DOIF;
wire [nb+3:0] DORF;
reg WSIF, WRSTNF, SelectWIRF, ShiftWRF, CaptureWRF;
reg SPCREQF, SPCDISF; // now keeping it as external signal
// DLX signals (2 - FFT, E - AES)
reg MRSTD, DReadED, DWriteED, DReadE2D, DWriteE2D, DReadE3D, DWriteE3D;
reg [`WordSize] DAddrED, DAddrE2D, DAddrE3D;
wire [`WordSize] DAddrD, DOutD, DInD, IAddrD, IInD;
reg WRSTND, SelectWIRD, ShiftWRD, CaptureWRD;
reg [4:0] i;
reg [`WordSize] IInED, IAddrED;
reg IWriteED;
//reg [3:0] STATE1; // just for a small test
reg PauseD;
reg SPCDISD, SPCREQD;
reg LDSD, LDFD;
reg MACcalcD, MACactualD;
//AES
reg rstA, modeA, ldA, kldA;
reg [127:0] keyA;
wire doneA;
wire [127:0] text_outA;
wire [127:0] text_inA1;
reg PauseA;
reg SPCREQA, SPCDISA; // now keeping it as external signal
reg WRSTNA, SelectWIRA, ShiftWRA, CaptureWRA;
wire WSOA;
// SPI
reg rstS, weS, goS, misoS;
reg [3:0] tx_selS;
wire intS, ssS, sclkS, mosiS;
reg PauseS;
reg SPCDISS, SPCREQS;
// PMC
wire PF, PD, PM, PA, PS;
reg resPMC;
// Security Policy Controller
reg MRSTSP;
wire [`WordSize] DAddrSP, DOutSP, DInSP, IInSP, WSOSP;
reg WRSTNSP, SelectWIRSP, ShiftWRSP, CaptureWRSP;
// DAP
reg MRSTDAP, s1,s2;
reg [31:0] DB1, DB2;
reg MRST11;
reg stop;
//wire [31:0] TP2;
//wire TPE2;
//wire [31:0] TP3;
//wire TPE3;
reg MRST12;
//wire [31:0] TP4;
//wire TPE4;
wire [31:0] TP11;
wire TPE11;
// module instantiation
TOPmost TM0(MASRST, CLKF, RSTF, EDF, STARTF, SHIFTF, DRF, DIF, RDYF, DORF, DOIF, WSIF, WRSTNF, SelectWIRF, ShiftWRF, CaptureWRF, MRSTD, DAddrED, DReadED, DWriteED, DAddrE2D, DReadE2D, DWriteE2D, DAddrE3D, DReadE3D, DWriteE3D, DAddrD, DOutD, DInD, IAddrD, IInD, IAddrED, IInED, IWriteED, WRSTND, SelectWIRD, ShiftWRD, CaptureWRD, PauseD, LDSD, LDFD, MACcalcD, MACactualD, modeA, rstA, kldA, ldA, doneA, keyA, text_inA1, text_outA, PauseA, WRSTNA, SelectWIRA, ShiftWRA, CaptureWRA,WSOA, rstS, weS, tx_selS, goS, intS, ssS, sclkS, mosiS, misoS, PauseS, resPMC, PF, PD, PM, PA, PS, DAddrSP, DOutSP, DInSP, IInSP, MRSTSP, WRSTNSP, SelectWIRSP, ShiftWRSP, CaptureWRSP, WSOSP, MRSTDAP, DB1, DB2, s1, s2, MRST11, stop, MRST12, TP11, TPE11);
initial
begin
CLKF = 1'b0;
forever
begin
#1 CLKF = !CLKF;
end
end
// monitor mode (atleast initially)
initial
begin
// signal values given (normal functional mode)
// initialization
// FFT
MASRST = 1'b1;
//STATE = 4'd3;
//STATE1 = 4'd0;
RSTF = 1'b1;
STARTF = 1'b1;
EDF = 1'b1;
SHIFTF = 4'b1010;
DRF = 16'b1000111000001111;
DIF = 16'b1111000001011010;
WRSTNF = 1'b1;
ShiftWRF = 1'b0; // CGHANGED IN THIS VERSION IN ALL
CaptureWRF = 1'b1;
SelectWIRF = 1'b1;
WSIF = 1'b1;
#2 WSIF = 1'b1;
#2 WSIF = 1'b1;
#8 SelectWIRF = 1'b0;
SPCREQF = 1'b0;
SPCDISF = 1'b0; // the logic level is reverse as compared to AES and DLX
// DLX
force TM0.T0.DLX.part2_ID.RegFile.WE = 0 ;
for (i = 0; i < 24; i = i+1)
begin
force TM0.T0.DLX.part2_ID.RegFile.W = i ;
force TM0.T0.DLX.part2_ID.RegFile.IN0 = 0 ;
#2 force TM0.T0.DLX.part2_ID.RegFile.WE = 1 ;
#2 force TM0.T0.DLX.part2_ID.RegFile.WE = 0 ;
end
#4 release TM0.T0.DLX.part2_ID.RegFile.W;
release TM0.T0.DLX.part2_ID.RegFile.IN0;
release TM0.T0.DLX.part2_ID.RegFile.WE;
$display("Starting simulation.");
MRSTD = `LogicZero;
DAddrED = 32'd2;
DAddrE2D = 32'd1;
DReadED = `LogicZero;
DWriteED = `LogicZero;
DReadE2D = `LogicZero;
DWriteE2D = `LogicZero;
WRSTND = 1'b1;
ShiftWRD = 1'b0;
CaptureWRD = 1'b1;
SelectWIRD = 1'b1;
#8 SelectWIRD = 1'b0;
IAddrED = 32'd0;
IInED = 32'd0;
IWriteED = 1'b0;
PauseD = 1'b1;
LDSD = 1'b0;
LDFD = 1'b0;
SPCDISD = 1'b1;
SPCREQD = 1'b0;
MACcalcD = 1'b1;
MACactualD = 1'b1;
// AES
rstA = 1'b0;
modeA = 1'b1;
//ENA = 1'b1;
PauseA = 1'b1;
SPCREQA = 1'b0;
SPCDISA = 1'b1;
keyA = 128'd39851273900764;
ldA = 1'b0;
WRSTNA = 1'b1;
ShiftWRA = 1'b0;
CaptureWRA = 1'b1;
SelectWIRA = 1'b1;
#8 SelectWIRA = 1'b0;
// SPI
rstS = 1'b1;
weS = 1'b1;
goS = 1'b0;
tx_selS = 4'b0001;
PauseS = 1'b1;
SPCREQS = 1'b0;
SPCDISS = 1'b0;
// security policy controller
force TM0.SP0.DLX11.part2_ID.RegFile.WE = 0 ;
for (i = 0; i < 24; i = i+1)
begin
force TM0.SP0.DLX11.part2_ID.RegFile.W = i ;
force TM0.SP0.DLX11.part2_ID.RegFile.IN0 = 0 ;
#2 force TM0.SP0.DLX11.part2_ID.RegFile.WE = 1 ;
#2 force TM0.SP0.DLX11.part2_ID.RegFile.WE = 0 ;
end
#4 release TM0.SP0.DLX11.part2_ID.RegFile.W;
release TM0.SP0.DLX11.part2_ID.RegFile.IN0;
release TM0.SP0.DLX11.part2_ID.RegFile.WE;
MRSTSP = `LogicZero;
WRSTNSP = 1'b1;
ShiftWRSP = 1'b0;
CaptureWRSP = 1'b1;
SelectWIRSP = 1'b1;
#8 SelectWIRSP = 1'b0;
// DAP
MRSTDAP = 1'b0;
DB1 = 32'b0;
DB2 = 32'b0;
s1 = 1'b1;
s2 = 1'b1;
#40 MRSTDAP = 1'b1;
MRST11 = 1'b0;
MRST12 = 1'b0;
stop = 1'b0;
//s2 = 1'b1;
//s1 = 1'b1;
#20 MRST11 = 1'b1;
//#20 MRST12 = 1'b1;
MRST12 = 1'b1;
//#20 DB2 = 32'b10000000000000000000000001000000; // SPI
//#20 DB2 = 32'b00000000000000000000000000000010;
//#20 DB2 = 32'b10000000000000000000000001000001;
//#20 DB2 = 32'b00000000000000000000000000001000;
#20 DB1 = 32'b10000000000000000000000000100000; // AES
#20 DB1 = 32'b00000000000000000000000000001011;
#20 DB1 = 32'b10000000000000000000000000100001;
#20 DB1 = 32'b00000000000000000000000000000100;
#20 DB1 = 32'b10000000000000000000000000000000; // DLX
#20 DB1 = 32'b00000000000000000000000000100011;
#60 DB1 = 32'b10000000000000000000000000000001;
#20 DB1 = 32'b00000000000000000000000000010000;
#60 DB1 = 32'b10000000000000000000000000000010;
#20 DB1 = 32'b00000000000000000000000000011000;
#20 DB1 = 32'b10000000000000000000000000010000; // FFT
#20 DB1 = 32'b00000000000000000000000000000011;
#20 DB1 = 32'b10000000000000000000000000110000; // mem
#20 DB1 = 32'b00000000000000000000000000000001;
#20 DB1 = 32'b10000000000000000000000000110001;
#20 DB1 = 32'b00000000000000000000000000010000;
#20 DB1 = 32'b10000000000000000000000000110010;
#20 DB1 = 32'b00000000000000000000000000100000;
//#20 DB2 = 32'b10000000000000000000000000010000;
//#20 DB2 = 32'b00000000000000000000000000000100;
//#20 DB2 = 32'b10000000000000000000000000000000;
//#20 DB2 = 32'b00000000000000000000000011000001;
//#60 DB2 = 32'b10000000000000000000000000000001;
//#20 DB2 = 32'b00000000000000000000000000011000;
//#20 DB2 = 32'b10000000000000000000000000000000;
//#20 DB2 = 32'b00000000000000000000000000000100;
//#60 DB2 = 32'b10000000000000000000000000000001;
//#20 DB2 = 32'b00000000000000000000000000000100;
//#40 DB2 = 32'b10000000000000000000000000000010;
//#20 DB2 = 32'b00000000000000000000000000100000;
//#20 DB2 = 32'b10000000000000000000000000000011;
//#20 DB2 = 32'b00000000000000000000000000001100;
//#60 DB2 = 32'b10000000000000000000000000000100;
//#20 DB2 = 32'b00000000000000000000000000000010;
//PMC
resPMC = 1'b1;
#2 resPMC = 1'b0;
MASRST = 1'b0;
//#60 MRSTSP = `LogicOne; // NEW POSITION
// MRSTSP = `LogicOne; // causing error while revisiting
// enable logic
//#2 RSTF = 1'b0;
#300 RSTF = 1'b0;
#2 STARTF = 1'b0;
//#4 STARTF = 1'b1;
//#3 RSTF = 1'b1;
//#300 SPCDISF = 1'b1;
//#120 SPCDISF = 1'b0; // changing SPCDISF starts the thing from beginning, but RDY is still asserted, but no DOI and DOR!!!!! need for STARTF to go from 1 to 0 again to start
#400 SPCREQF = 1'b1;
#20 SPCREQF = 1'b0;
//#200 EDF = 1'b0;
//#40 EDF = 1'b1;
//#2 STARTF = 1'b1;
//#2 STARTF = 1'b0;
MRSTSP = `LogicOne; // NEW POSITION
#200 LDSD = 1'b1;
////// load the instruction cache of the normal DLX processor with instructions
//LDSD = 1'b1;
IInED = 32'b10101100010000010000000000000000;
IWriteED = 1'b1;
#20 IWriteED = 1'b0;
#1 IAddrED = 32'd1;
IInED = 32'b00000000000000000000000000000000;
IWriteED = 1'b1;
#20 IWriteED = 1'b0;
#1 IAddrED = 32'd2;
IInED = 32'b00000000000000000000000000000000;
IWriteED = 1'b1;
#20 IWriteED = 1'b0;
#1 IAddrED = 32'd3;
IInED = 32'b00000000000000000000000000000000;
IWriteED = 1'b1;
#20 IWriteED = 1'b0;
#1 IAddrED = 32'd4;
IInED = 32'b00100000001000010000000000000110;
IWriteED = 1'b1;
#20 IWriteED = 1'b0;
#1 IAddrED = 32'd5;
IInED = 32'b00000000000000000000000000000000;
IWriteED = 1'b1;
#20 IWriteED = 1'b0;
#1 IAddrED = 32'd6;
IInED = 32'b00000000000000000000000000000000;
IWriteED = 1'b1;
#20 IWriteED = 1'b0;
#1 IAddrED = 32'd7;
IInED = 32'b00000000000000000000000000000000;
IWriteED = 1'b1;
#20 IWriteED = 1'b0;
#1 IAddrED = 32'd8;
IInED = 32'b11001100100000010000000000000010;
IWriteED = 1'b1;
#20 IWriteED = 1'b0;
#1 IAddrED = 32'd9;
IInED = 32'b00000000000000000000000000000000;
IWriteED = 1'b1;
#20 IWriteED = 1'b0;
#1 IAddrED = 32'd10;
IInED = 32'b00000000000000000000000000000000;
IWriteED = 1'b1;
#20 IWriteED = 1'b0;
#1 IAddrED = 32'd11;
IInED = 32'b00000000000000000000000000000000;
IWriteED = 1'b1;
#20 IWriteED = 1'b0;
//#40 SPCDISF = 1'b0;
LDFD = 1'b1;
#2 LDSD = 1'b0;
// DLX clock domain = 10X
//#280 DWriteE2D = `LogicOne; //**** time???
//#30 DWriteE2D = `LogicOne; //**** time???
#10 DWriteE2D = `LogicOne; //**** time???
//#574 EDF = 1'b0; // stop the FFT engine to avoid spurious writes
#14 EDF = 1'b0; // stop the FFT engine to avoid spurious writes
// for simultaneous writes to the SPC data memory
//RSTF = 1'b1;
//STARTF = 1'b1;
// simulataneosu operation suppose with DLX (hence after MRSTD)
//#12 DWriteE2D = `LogicZero; // *** time??
#16 DWriteE2D = `LogicZero; // *** time??
#2 MRSTD = `LogicOne; // ***** time for MRST???
// simulatneous operation starts here???
//RSTF = 1'b0;
//#2 STARTF = 1'b0;
//#2 EDF = 1'b1;
#85 PauseD = 1'b0;
#38 PauseD = 1'b1;
//stop = 1'b1;
//#2 SPCDISD = 1'b0;
//#28 SPCDISD = 1'b1;
//#240 MRSTD = 1'b0;
#155 MRSTD = 1'b0;
//stop = 1'b1;
// DAddrED = 32'd2;
#20 DReadED = `LogicOne; // ** time??
#10 rstA = 1'b1; // ** check times
//#2 rstA = 1'b0;
#1 ldA = 1'b1;
#6 ldA = 1'b0;
//#4 ldA = 1'b1;
#8 SPCREQA = 1'b1;
#6 SPCREQA = 1'b0;
//SPCDISA = 1'b0;
#5 PauseA = 1'b0;
#5 PauseA = 1'b1;
//#16 PauseA = 1'b0; // could be reset as well
#8 PauseA = 1'b0; // could be reset as well
// SPI
#8 rstS = 1'b0;
//#14 MRSTSP = `LogicOne;
//MRSTSP = `LogicOne;
#2 tx_selS = 4'b0010;
#2 tx_selS = 4'b0100;
#2 tx_selS = 4'b1000;
#2 goS = 1'b1;
//#28 PauseS = 1'b0;
//#20 PauseS = 1'b1;
//#40 SPCDISS = 1'b1;
//#20 SPCDISS = 1'b0;
#2 MRSTSP = `LogicZero;
//#600 MRSTSP = `LogicZero;
end
initial
begin
$monitor($time, "FFT, AES SPI engine finish signal %b", RDYF, doneA, intS);
//$monitor($time, "values are %b", TM0.SP0.DLX11.part2_ID.RegFile.IN0);
//$monitor($time, "buffer %b", TM0.ST0.buff[1]);
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 128 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// o.uzenkov@unicore.co.ua ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : Twiddle factor ROM for 128-point FFT
// FUNCTION:
// FILES: WROM128.v - ROM of twiddle factors.
// PROPERTIES: 1) Has 128 complex coefficients which form a table 8x16,
// and stay in the needed order, as they are addressed
// by the simple counter
// 2) 16-bit values are stored. When shorter bit width is set
// then rounding is not used
// 3) for FFT and IFFT depending on paramifft
//
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`include "FFT128_CONFIG.inc"
`timescale 1 ns / 1 ps
module WROM128 ( WI ,WR ,ADDR );
`FFT128paramnw
input [6:0] ADDR ;
wire [6:0] ADDR ;
output [nw-1:0] WI ;
wire [nw-1:0] WI ;
output [nw-1:0] WR ;
wire [nw-1:0] WR ;
wire [15:0] cosw[0:127];
assign cosw[0]=16'h7FFF;assign cosw[1]=16'h7FFF;assign cosw[2]=16'h7FFF;assign cosw[3]=16'h7FFF;assign cosw[4]=16'h7FFF;assign cosw[5]=16'h7FFF;assign cosw[6]=16'h7FFF;assign cosw[7]=16'h7FFF;assign cosw[8]=16'h7FFF;assign cosw[9]=16'h7FFF;assign cosw[10]=16'h7FFF;assign cosw[11]=16'h7FFF;assign cosw[12]=16'h7FFF;assign cosw[13]=16'h7FFF;assign cosw[14]=16'h7FFF;assign cosw[15]=16'h7FFF;
assign cosw[16]=16'h7FFF;assign cosw[17]=16'h7FD7;assign cosw[18]=16'h7F61;assign cosw[19]=16'h7E9C;assign cosw[20]=16'h7D89;assign cosw[21]=16'h7C29;assign cosw[22]=16'h7A7C;assign cosw[23]=16'h7883;assign cosw[24]=16'h7640;assign cosw[25]=16'h73B5;assign cosw[26]=16'h70E1;assign cosw[27]=16'h6DC9;assign cosw[28]=16'h6A6C;assign cosw[29]=16'h66CE;assign cosw[30]=16'h62F1;assign cosw[31]=16'h5ED6;
assign cosw[32]=16'h7FFF;assign cosw[33]=16'h7F61;assign cosw[34]=16'h7D89;assign cosw[35]=16'h7A7C;assign cosw[36]=16'h7640;assign cosw[37]=16'h70E1;assign cosw[38]=16'h6A6C;assign cosw[39]=16'h62F1;assign cosw[40]=16'h5A81;assign cosw[41]=16'h5133;assign cosw[42]=16'h471C;assign cosw[43]=16'h3C56;assign cosw[44]=16'h30FB;assign cosw[45]=16'h2527;assign cosw[46]=16'h18F8;assign cosw[47]=16'h0C8B;
assign cosw[48]=16'h7FFF;assign cosw[49]=16'h7E9C;assign cosw[50]=16'h7A7C;assign cosw[51]=16'h73B5;assign cosw[52]=16'h6A6C;assign cosw[53]=16'h5ED6;assign cosw[54]=16'h5133;assign cosw[55]=16'h41CD;assign cosw[56]=16'h30FB;assign cosw[57]=16'h1F19;assign cosw[58]=16'h0C8B;assign cosw[59]=16'hF9B9;assign cosw[60]=16'hE708;assign cosw[61]=16'hD4E2;assign cosw[62]=16'hC3AA;assign cosw[63]=16'hB3C1;
assign cosw[64]=16'h7FFF;assign cosw[65]=16'h7D89;assign cosw[66]=16'h7640;assign cosw[67]=16'h6A6C;assign cosw[68]=16'h5A81;assign cosw[69]=16'h471C;assign cosw[70]=16'h30FB;assign cosw[71]=16'h18F8;assign cosw[72]=16'h0000;assign cosw[73]=16'hE708;assign cosw[74]=16'hCF05;assign cosw[75]=16'hB8E4;assign cosw[76]=16'hA57F;assign cosw[77]=16'h9594;assign cosw[78]=16'h89C0;assign cosw[79]=16'h8277;
assign cosw[80]=16'h7FFF;assign cosw[81]=16'h7C29;assign cosw[82]=16'h70E1;assign cosw[83]=16'h5ED6;assign cosw[84]=16'h471C;assign cosw[85]=16'h2B1E;assign cosw[86]=16'h0C8B;assign cosw[87]=16'hED39;assign cosw[88]=16'hCF05;assign cosw[89]=16'hB3C1;assign cosw[90]=16'h9D0F;assign cosw[91]=16'h8C4B;assign cosw[92]=16'h8277;assign cosw[93]=16'h8029;assign cosw[94]=16'h8584;assign cosw[95]=16'h9237;
assign cosw[96]=16'h7FFF;assign cosw[97]=16'h7A7C;assign cosw[98]=16'h6A6C;assign cosw[99]=16'h5133;assign cosw[100]=16'h30FB;assign cosw[101]=16'h0C8B;assign cosw[102]=16'hE708;assign cosw[103]=16'hC3AA;assign cosw[104]=16'hA57F;assign cosw[105]=16'h8F1F;assign cosw[106]=16'h8277;assign cosw[107]=16'h809F;assign cosw[108]=16'h89C0;assign cosw[109]=16'h9D0F;assign cosw[110]=16'hB8E4;assign cosw[111]=16'hDAD9;
assign cosw[112]=16'h7FFF;assign cosw[113]=16'h7883;assign cosw[114]=16'h62F1;assign cosw[115]=16'h41CD;assign cosw[116]=16'h18F8;assign cosw[117]=16'hED39;assign cosw[118]=16'hC3AA;assign cosw[119]=16'hA12A;assign cosw[120]=16'h89C0;assign cosw[121]=16'h8029;assign cosw[122]=16'h8584;assign cosw[123]=16'h9932;assign cosw[124]=16'hB8E4;assign cosw[125]=16'hE0E7;assign cosw[126]=16'h0C8B;assign cosw[127]=16'h36B9;
wire [15:0] sinw[0:127];
`ifdef FFT256paramifft //Inverse FFT
assign sinw[0]=16'h0000;assign sinw[1]=16'h0000;assign sinw[2]=16'h0000;assign sinw[3]=16'h0000;assign sinw[4]=16'h0000;assign sinw[5]=16'h0000;assign sinw[6]=16'h0000;assign sinw[7]=16'h0000;assign sinw[8]=16'h0000;assign sinw[9]=16'h0000;assign sinw[10]=16'h0000;assign sinw[11]=16'h0000;assign sinw[12]=16'h0000;assign sinw[13]=16'h0000;assign sinw[14]=16'h0000;assign sinw[15]=16'h0000;
assign sinw[16]=16'h0000;assign sinw[17]=16'h0647;assign sinw[18]=16'h0C8B;assign sinw[19]=16'h12C7;assign sinw[20]=16'h18F8;assign sinw[21]=16'h1F19;assign sinw[22]=16'h2527;assign sinw[23]=16'h2B1E;assign sinw[24]=16'h30FB;assign sinw[25]=16'h36B9;assign sinw[26]=16'h3C56;assign sinw[27]=16'h41CD;assign sinw[28]=16'h471C;assign sinw[29]=16'h4C3F;assign sinw[30]=16'h5133;assign sinw[31]=16'h55F4;
assign sinw[32]=16'h0000;assign sinw[33]=16'h0C8B;assign sinw[34]=16'h18F8;assign sinw[35]=16'h2527;assign sinw[36]=16'h30FB;assign sinw[37]=16'h3C56;assign sinw[38]=16'h471C;assign sinw[39]=16'h5133;assign sinw[40]=16'h5A81;assign sinw[41]=16'h62F1;assign sinw[42]=16'h6A6C;assign sinw[43]=16'h70E1;assign sinw[44]=16'h7640;assign sinw[45]=16'h7A7C;assign sinw[46]=16'h7D89;assign sinw[47]=16'h7F61;
assign sinw[48]=16'h0000;assign sinw[49]=16'h12C7;assign sinw[50]=16'h2527;assign sinw[51]=16'h36B9;assign sinw[52]=16'h471C;assign sinw[53]=16'h55F4;assign sinw[54]=16'h62F1;assign sinw[55]=16'h6DC9;assign sinw[56]=16'h7640;assign sinw[57]=16'h7C29;assign sinw[58]=16'h7F61;assign sinw[59]=16'h7FD7;assign sinw[60]=16'h7D89;assign sinw[61]=16'h7883;assign sinw[62]=16'h70E1;assign sinw[63]=16'h66CE;
assign sinw[64]=16'h0000;assign sinw[65]=16'h18F8;assign sinw[66]=16'h30FB;assign sinw[67]=16'h471C;assign sinw[68]=16'h5A81;assign sinw[69]=16'h6A6C;assign sinw[70]=16'h7640;assign sinw[71]=16'h7D89;assign sinw[72]=16'h7FFF;assign sinw[73]=16'h7D89;assign sinw[74]=16'h7640;assign sinw[75]=16'h6A6C;assign sinw[76]=16'h5A81;assign sinw[77]=16'h471C;assign sinw[78]=16'h30FB;assign sinw[79]=16'h18F8;
assign sinw[80]=16'h0000;assign sinw[81]=16'h1F19;assign sinw[82]=16'h3C56;assign sinw[83]=16'h55F4;assign sinw[84]=16'h6A6C;assign sinw[85]=16'h7883;assign sinw[86]=16'h7F61;assign sinw[87]=16'h7E9C;assign sinw[88]=16'h7640;assign sinw[89]=16'h66CE;assign sinw[90]=16'h5133;assign sinw[91]=16'h36B9;assign sinw[92]=16'h18F8;assign sinw[93]=16'hF9B9;assign sinw[94]=16'hDAD9;assign sinw[95]=16'hBE33;
assign sinw[96]=16'h0000;assign sinw[97]=16'h2527;assign sinw[98]=16'h471C;assign sinw[99]=16'h62F1;assign sinw[100]=16'h7640;assign sinw[101]=16'h7F61;assign sinw[102]=16'h7D89;assign sinw[103]=16'h70E1;assign sinw[104]=16'h5A81;assign sinw[105]=16'h3C56;assign sinw[106]=16'h18F8;assign sinw[107]=16'hF375;assign sinw[108]=16'hCF05;assign sinw[109]=16'hAECD;assign sinw[110]=16'h9594;assign sinw[111]=16'h8584;
assign sinw[112]=16'h0000;assign sinw[113]=16'h2B1E;assign sinw[114]=16'h5133;assign sinw[115]=16'h6DC9;assign sinw[116]=16'h7D89;assign sinw[117]=16'h7E9C;assign sinw[118]=16'h70E1;assign sinw[119]=16'h55F4;assign sinw[120]=16'h30FB;assign sinw[121]=16'h0647;assign sinw[122]=16'hDAD9;assign sinw[123]=16'hB3C1;assign sinw[124]=16'h9594;assign sinw[125]=16'h83D7;assign sinw[126]=16'h809F;assign sinw[127]=16'h8C4B;
`else //Forward FFT
assign sinw[0]=16'h0000;assign sinw[1]=16'h0000;assign sinw[2]=16'h0000;assign sinw[3]=16'h0000;assign sinw[4]=16'h0000;assign sinw[5]=16'h0000;assign sinw[6]=16'h0000;assign sinw[7]=16'h0000;assign sinw[8]=16'h0000;assign sinw[9]=16'h0000;assign sinw[10]=16'h0000;assign sinw[11]=16'h0000;assign sinw[12]=16'h0000;assign sinw[13]=16'h0000;assign sinw[14]=16'h0000;assign sinw[15]=16'h0000;
assign sinw[16]=16'h0000;assign sinw[17]=16'hF9B9;assign sinw[18]=16'hF375;assign sinw[19]=16'hED39;assign sinw[20]=16'hE708;assign sinw[21]=16'hE0E7;assign sinw[22]=16'hDAD9;assign sinw[23]=16'hD4E2;assign sinw[24]=16'hCF05;assign sinw[25]=16'hC947;assign sinw[26]=16'hC3AA;assign sinw[27]=16'hBE33;assign sinw[28]=16'hB8E4;assign sinw[29]=16'hB3C1;assign sinw[30]=16'hAECD;assign sinw[31]=16'hAA0C;
assign sinw[32]=16'h0000;assign sinw[33]=16'hF375;assign sinw[34]=16'hE708;assign sinw[35]=16'hDAD9;assign sinw[36]=16'hCF05;assign sinw[37]=16'hC3AA;assign sinw[38]=16'hB8E4;assign sinw[39]=16'hAECD;assign sinw[40]=16'hA57F;assign sinw[41]=16'h9D0F;assign sinw[42]=16'h9594;assign sinw[43]=16'h8F1F;assign sinw[44]=16'h89C0;assign sinw[45]=16'h8584;assign sinw[46]=16'h8277;assign sinw[47]=16'h809F;
assign sinw[48]=16'h0000;assign sinw[49]=16'hED39;assign sinw[50]=16'hDAD9;assign sinw[51]=16'hC947;assign sinw[52]=16'hB8E4;assign sinw[53]=16'hAA0C;assign sinw[54]=16'h9D0F;assign sinw[55]=16'h9237;assign sinw[56]=16'h89C0;assign sinw[57]=16'h83D7;assign sinw[58]=16'h809F;assign sinw[59]=16'h8029;assign sinw[60]=16'h8277;assign sinw[61]=16'h877D;assign sinw[62]=16'h8F1F;assign sinw[63]=16'h9932;
assign sinw[64]=16'h0000;assign sinw[65]=16'hE708;assign sinw[66]=16'hCF05;assign sinw[67]=16'hB8E4;assign sinw[68]=16'hA57F;assign sinw[69]=16'h9594;assign sinw[70]=16'h89C0;assign sinw[71]=16'h8277;assign sinw[72]=16'h8001;assign sinw[73]=16'h8277;assign sinw[74]=16'h89C0;assign sinw[75]=16'h9594;assign sinw[76]=16'hA57F;assign sinw[77]=16'hB8E4;assign sinw[78]=16'hCF05;assign sinw[79]=16'hE708;
assign sinw[80]=16'h0000;assign sinw[81]=16'hE0E7;assign sinw[82]=16'hC3AA;assign sinw[83]=16'hAA0C;assign sinw[84]=16'h9594;assign sinw[85]=16'h877D;assign sinw[86]=16'h809F;assign sinw[87]=16'h8164;assign sinw[88]=16'h89C0;assign sinw[89]=16'h9932;assign sinw[90]=16'hAECD;assign sinw[91]=16'hC947;assign sinw[92]=16'hE708;assign sinw[93]=16'h0647;assign sinw[94]=16'h2527;assign sinw[95]=16'h41CD;
assign sinw[96]=16'h0000;assign sinw[97]=16'hDAD9;assign sinw[98]=16'hB8E4;assign sinw[99]=16'h9D0F;assign sinw[100]=16'h89C0;assign sinw[101]=16'h809F;assign sinw[102]=16'h8277;assign sinw[103]=16'h8F1F;assign sinw[104]=16'hA57F;assign sinw[105]=16'hC3AA;assign sinw[106]=16'hE708;assign sinw[107]=16'h0C8B;assign sinw[108]=16'h30FB;assign sinw[109]=16'h5133;assign sinw[110]=16'h6A6C;assign sinw[111]=16'h7A7C;
assign sinw[112]=16'h0000;assign sinw[113]=16'hD4E2;assign sinw[114]=16'hAECD;assign sinw[115]=16'h9237;assign sinw[116]=16'h8277;assign sinw[117]=16'h8164;assign sinw[118]=16'h8F1F;assign sinw[119]=16'hAA0C;assign sinw[120]=16'hCF05;assign sinw[121]=16'hF9B9;assign sinw[122]=16'h2527;assign sinw[123]=16'h4C3F;assign sinw[124]=16'h6A6C;assign sinw[125]=16'h7C29;assign sinw[126]=16'h7F61;assign sinw[127]=16'h73B5;
`endif
wire [15:0] wri,wii ;
assign wri=cosw[ADDR];
assign wii=sinw[ADDR];
wire [nw:0] wrt,wit;
assign wrt = wri[15:16-nw];
assign wit = wii[15:16-nw];
assign WR= wrt[nw-1:0];
assign WI= wit[nw-1:0];
endmodule
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a generic wishbone bus (B3). The number of masters and
* slaves are configurable. Ten slaves can be connected with a
* configurable memory map.
*
* Instantiation example:
* wb_bus_b3
* #(.DATA_WIDTH(32), .ADDR_WIDTH(32),
* .MASTERS(4), .SLAVES(2),
* .S0_RANGE_WIDTH(1), .S0_RANGE_MATCH(1'b0),
* .S1_RANGE_WIDTH(4), .S1_RANGE_MATCH(4'he))
* bus(.clk_i(clk), rst_i(rst),
* .m_adr_i({m_adr_i[3],..,m_adr_i[0]},
* ...
* );
*
* DATA_WIDTH and ADDR_WIDTH are defined in bits. DATA_WIDTH must be
* full bytes (i.e., multiple of 8)!
*
* The ports are flattened. That means, that all masters share the bus
* signal ports. With four masters and a data width of 32 bit the
* m_cyc_i port is 4 bit wide and the m_dat_i is 128 (=4*32) bit wide.
* The signals are arranged from right to left, meaning the m_dat_i is
* defined as [DATA_WIDTH*MASTERS-1:0] and each port m is assigned to
* [(m+1)*DATA_WIDTH-1:m*DATA_WIDTH].
*
* The memory map is defined with the S?_RANGE_WIDTH and
* S?_RANGE_MATCH parameters. The WIDTH sets the number of most
* significant bits (i.e., those from the left) that are relevant to
* define the memory range. The MATCH accordingly sets the value of
* those bits of the address that define the memory range.
*
* Example (32 bit addresses):
* Slave 0: 0x00000000-0x0effffff
* Slave 1: 0x10000000-0x1fffffff
* Slave 2: 0x20000000-0x2fffffff
* Slave 3: 0x30000000-0x3fffffff
* Slave 4: 0x40000000-0x4fffffff
* Slave 5: 0x50000000-0x5fffffff
* Slave 6: 0x60000000-0x6fffffff
* Slave 7: 0x70000000-0x7fffffff
* Slave 8: 0x80000000-0x8fffffff
* Slave 9: 0x90000000-0x9fffffff
* Slave 0 is defined by the uppermost bit, which is 0 for this
* address range. Slave 1 is defined by the uppermost two bit, that
* are 10 for the memory range. Slave 2 is defined by 8 bit which are
* e0 for the memory range.
*
* This results in:
* S0_RANGE_WIDTH(1), S0_RANGE_MATCH(1'b0)
* S1_RANGE_WIDTH(4), S1_RANGE_MATCH(4'b0001)
* S2_RANGE_WIDTH(4), S2_RANGE_MATCH(4'b0010)
* S3_RANGE_WIDTH(4), S3_RANGE_MATCH(4'b0011)
* S4_RANGE_WIDTH(4), S4_RANGE_MATCH(4'b0100)
* S5_RANGE_WIDTH(4), S5_RANGE_MATCH(4'b0101)
* S6_RANGE_WIDTH(4), S6_RANGE_MATCH(4'b0110)
* S7_RANGE_WIDTH(4), S7_RANGE_MATCH(4'b0111)
* S8_RANGE_WIDTH(4), S8_RANGE_MATCH(4'b1000)
* S9_RANGE_WIDTH(4), S9_RANGE_MATCH(4'b1001)
* Author(s):
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*/
module wb_bus_b3
#(
/* User parameters */
// Set the number of masters and slaves
parameter MASTERS = 1,
parameter SLAVES = 10,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = 1,
parameter S0_RANGE_WIDTH = 1,
parameter S0_RANGE_MATCH = 1'b0,
parameter S1_ENABLE = 1,
parameter S1_RANGE_WIDTH = 4,
parameter S1_RANGE_MATCH = 4'b0001,
parameter S2_ENABLE = 1,
parameter S2_RANGE_WIDTH = 4,
parameter S2_RANGE_MATCH = 4'b0010,
parameter S3_ENABLE = 1,
parameter S3_RANGE_WIDTH = 4,
parameter S3_RANGE_MATCH = 4'b0011,
parameter S4_ENABLE = 1,
parameter S4_RANGE_WIDTH = 4,
parameter S4_RANGE_MATCH = 4'b0100,
parameter S5_ENABLE = 1,
parameter S5_RANGE_WIDTH = 4,
parameter S5_RANGE_MATCH = 4'b0101,
parameter S6_ENABLE = 1,
parameter S6_RANGE_WIDTH = 4,
parameter S6_RANGE_MATCH = 4'b0110,
parameter S7_ENABLE = 1,
parameter S7_RANGE_WIDTH = 4,
parameter S7_RANGE_MATCH = 4'b0111,
parameter S8_ENABLE = 1,
parameter S8_RANGE_WIDTH = 4,
parameter S8_RANGE_MATCH = 4'b1000,
parameter S9_ENABLE = 1,
parameter S9_RANGE_WIDTH = 4,
parameter S9_RANGE_MATCH = 4'b1001,
//Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3
)
(
/* Ports */
input clk_i,
input rst_i,
input [ADDR_WIDTH*MASTERS-1:0] m_adr_i,
input [DATA_WIDTH*MASTERS-1:0] m_dat_i,
input [MASTERS-1:0] m_cyc_i,
input [MASTERS-1:0] m_stb_i,
input [SEL_WIDTH*MASTERS-1:0] m_sel_i,
input [MASTERS-1:0] m_we_i,
input [MASTERS*3-1:0] m_cti_i,
input [MASTERS*2-1:0] m_bte_i,
output [DATA_WIDTH*MASTERS-1:0] m_dat_o,
output [MASTERS-1:0] m_ack_o,
output [MASTERS-1:0] m_err_o,
output [MASTERS-1:0] m_rty_o,
output [ADDR_WIDTH*SLAVES-1:0] s_adr_o,
output [DATA_WIDTH*SLAVES-1:0] s_dat_o,
output [SLAVES-1:0] s_cyc_o,
output [SLAVES-1:0] s_stb_o,
output [SEL_WIDTH*SLAVES-1:0] s_sel_o,
output [SLAVES-1:0] s_we_o,
output [SLAVES*3-1:0] s_cti_o,
output [SLAVES*2-1:0] s_bte_o,
input [DATA_WIDTH*SLAVES-1:0] s_dat_i,
input [SLAVES-1:0] s_ack_i,
input [SLAVES-1:0] s_err_i,
input [SLAVES-1:0] s_rty_i,
// The snoop port forwards all write accesses on their success for
// one cycle.
output [DATA_WIDTH-1:0] snoop_adr_o,
output snoop_en_o,
input bus_hold,
output bus_hold_ack
);
wire [ADDR_WIDTH-1:0] bus_adr;
wire [DATA_WIDTH-1:0] bus_wdat;
wire bus_cyc;
wire bus_stb;
wire [SEL_WIDTH-1:0] bus_sel;
wire bus_we;
wire [2:0] bus_cti;
wire [1:0] bus_bte;
wire [DATA_WIDTH-1:0] bus_rdat;
wire bus_ack;
wire bus_err;
wire bus_rty;
/* wb_mux AUTO_TEMPLATE(
.s_dat_o (bus_wdat),
.s_dat_i (bus_rdat),
.s_\(.*\)_o (bus_\1),
.s_\(.*\)_i (bus_\1),
); */
wb_mux
#(.MASTERS(MASTERS), .ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH))
u_mux(/*AUTOINST*/
// Outputs
.m_dat_o (m_dat_o[DATA_WIDTH*MASTERS-1:0]),
.m_ack_o (m_ack_o[MASTERS-1:0]),
.m_err_o (m_err_o[MASTERS-1:0]),
.m_rty_o (m_rty_o[MASTERS-1:0]),
.s_adr_o (bus_adr), // Templated
.s_dat_o (bus_wdat), // Templated
.s_cyc_o (bus_cyc), // Templated
.s_stb_o (bus_stb), // Templated
.s_sel_o (bus_sel), // Templated
.s_we_o (bus_we), // Templated
.s_cti_o (bus_cti), // Templated
.s_bte_o (bus_bte), // Templated
.bus_hold_ack (bus_hold_ack),
// Inputs
.clk_i (clk_i),
.rst_i (rst_i),
.m_adr_i (m_adr_i[ADDR_WIDTH*MASTERS-1:0]),
.m_dat_i (m_dat_i[DATA_WIDTH*MASTERS-1:0]),
.m_cyc_i (m_cyc_i[MASTERS-1:0]),
.m_stb_i (m_stb_i[MASTERS-1:0]),
.m_sel_i (m_sel_i[SEL_WIDTH*MASTERS-1:0]),
.m_we_i (m_we_i[MASTERS-1:0]),
.m_cti_i (m_cti_i[MASTERS*3-1:0]),
.m_bte_i (m_bte_i[MASTERS*2-1:0]),
.s_dat_i (bus_rdat), // Templated
.s_ack_i (bus_ack), // Templated
.s_err_i (bus_err), // Templated
.s_rty_i (bus_rty), // Templated
.bus_hold (bus_hold));
/* wb_decode AUTO_TEMPLATE(
.m_dat_o (bus_rdat),
.m_dat_i (bus_wdat),
.m_\(.*\)_i (bus_\1),
.m_\(.*\)_o (bus_\1),
); */
wb_decode
#(.SLAVES(SLAVES), .ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.S0_ENABLE(S0_ENABLE),
.S0_RANGE_WIDTH(S0_RANGE_WIDTH), .S0_RANGE_MATCH(S0_RANGE_MATCH),
.S1_ENABLE(S1_ENABLE),
.S1_RANGE_WIDTH(S1_RANGE_WIDTH), .S1_RANGE_MATCH(S1_RANGE_MATCH),
.S2_ENABLE(S2_ENABLE),
.S2_RANGE_WIDTH(S2_RANGE_WIDTH), .S2_RANGE_MATCH(S2_RANGE_MATCH),
.S3_ENABLE(S3_ENABLE),
.S3_RANGE_WIDTH(S3_RANGE_WIDTH), .S3_RANGE_MATCH(S3_RANGE_MATCH),
.S4_ENABLE(S4_ENABLE),
.S4_RANGE_WIDTH(S4_RANGE_WIDTH), .S4_RANGE_MATCH(S4_RANGE_MATCH),
.S5_ENABLE(S5_ENABLE),
.S5_RANGE_WIDTH(S5_RANGE_WIDTH), .S5_RANGE_MATCH(S5_RANGE_MATCH),
.S6_ENABLE(S6_ENABLE),
.S6_RANGE_WIDTH(S6_RANGE_WIDTH), .S6_RANGE_MATCH(S6_RANGE_MATCH),
.S7_ENABLE(S7_ENABLE),
.S7_RANGE_WIDTH(S7_RANGE_WIDTH), .S7_RANGE_MATCH(S7_RANGE_MATCH),
.S8_ENABLE(S8_ENABLE),
.S8_RANGE_WIDTH(S8_RANGE_WIDTH), .S8_RANGE_MATCH(S8_RANGE_MATCH),
.S9_ENABLE(S9_ENABLE),
.S9_RANGE_WIDTH(S9_RANGE_WIDTH), .S9_RANGE_MATCH(S9_RANGE_MATCH))
u_decode(/*AUTOINST*/
// Outputs
.m_dat_o (bus_rdat), // Templated
.m_ack_o (bus_ack), // Templated
.m_err_o (bus_err), // Templated
.m_rty_o (bus_rty), // Templated
.s_adr_o (s_adr_o[ADDR_WIDTH*SLAVES-1:0]),
.s_dat_o (s_dat_o[DATA_WIDTH*SLAVES-1:0]),
.s_cyc_o (s_cyc_o[SLAVES-1:0]),
.s_stb_o (s_stb_o[SLAVES-1:0]),
.s_sel_o (s_sel_o[SEL_WIDTH*SLAVES-1:0]),
.s_we_o (s_we_o[SLAVES-1:0]),
.s_cti_o (s_cti_o[SLAVES*3-1:0]),
.s_bte_o (s_bte_o[SLAVES*2-1:0]),
// Inputs
.clk_i (clk_i),
.rst_i (rst_i),
.m_adr_i (bus_adr), // Templated
.m_dat_i (bus_wdat), // Templated
.m_cyc_i (bus_cyc), // Templated
.m_stb_i (bus_stb), // Templated
.m_sel_i (bus_sel), // Templated
.m_we_i (bus_we), // Templated
.m_cti_i (bus_cti), // Templated
.m_bte_i (bus_bte), // Templated
.s_dat_i (s_dat_i[DATA_WIDTH*SLAVES-1:0]),
.s_ack_i (s_ack_i[SLAVES-1:0]),
.s_err_i (s_err_i[SLAVES-1:0]),
.s_rty_i (s_rty_i[SLAVES-1:0]));
// Snoop address comes direct from master bus
assign snoop_adr_o = bus_adr;
// Snoop on acknowledge and write. Mask with strobe to be sure
// there actually is a something happing and no dangling signals
// and always ack'ing slaves.
assign snoop_en_o = bus_ack & bus_stb & bus_we;
endmodule // wb_bus_b3
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a generic slave selector for the Wishbone bus (B3). The
* number of slaves is configurable and up to ten slaves can be
* connected with a configurable memory map.
*
* Instantiation example:
* wb_sselect
* #(.DATA_WIDTH(32), .ADDR_WIDTH(32),
* .SLAVES(2),
* .S0_ENABLE (1), .S0_RANGE_WIDTH(1), .S0_RANGE_MATCH(1'b0),
* .S1_ENABLE (1), .S1_RANGE_WIDTH(4), .S1_RANGE_MATCH(4'he))
* sselect(.clk_i(clk), rst_i(rst),
* .s_adr_o({m_adr_o[3],..,m_adr_o[0]},
* ...
* );
*
* DATA_WIDTH and ADDR_WIDTH are defined in bits. DATA_WIDTH must be
* full bytes (i.e., multiple of 8)!
*
* The ports are flattened. That means, that all slaves share the bus
* signal ports. With four slaves and a data width of 32 bit the
* s_cyc_o port is 4 bit wide and the s_dat_o is 128 (=4*32) bit wide.
* The signals are arranged from right to left, meaning the s_dat_o is
* defined as [DATA_WIDTH*SLAVES-1:0] and each port s is assigned to
* [(s+1)*DATA_WIDTH-1:s*DATA_WIDTH].
*
* The memory map is defined with the S?_RANGE_WIDTH and
* S?_RANGE_MATCH parameters. The WIDTH sets the number of most
* significant bits (i.e., those from the left) that are relevant to
* define the memory range. The MATCH accordingly sets the value of
* those bits of the address that define the memory range.
*
* Example (32 bit addresses):
* Slave 0: 0x00000000-0x7fffffff
* Slave 1: 0x80000000-0xbfffffff
* Slave 2: 0xe0000000-0xe0ffffff
*
* Slave 0 is defined by the uppermost bit, which is 0 for this
* address range. Slave 1 is defined by the uppermost two bit, that
* are 10 for the memory range. Slave 2 is defined by 8 bit which are
* e0 for the memory range.
*
* This results in:
* S0_RANGE_WIDTH(1), S0_RANGE_MATCH(1'b0)
* S1_RANGE_WIDTH(2), S1_RANGE_MATCH(2'b10)
* S2_RANGE_WIDTH(8), S2_RANGE_MATCH(8'he0)
*
*
* Finally, the slaves can be individually masked to ease
* instantiation using the Sx_ENABLE parameter. By defaults all slaves
* are enabled (and selected as long as x < SLAVES).
*
* Author(s):
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*/
module wb_decode
#(
/* User parameters */
// Set the number of slaves
parameter SLAVES = 10,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3,
// Memory range definitions, see above
// The number of parameters actually limits the number of slaves as
// there is no generic way that is handled by all tools to define
// variable width parameter arrays.
parameter S0_ENABLE = 1,
parameter S0_RANGE_WIDTH = 1,
parameter S0_RANGE_MATCH = 1'b0,
parameter S1_ENABLE = 1,
parameter S1_RANGE_WIDTH = 4,
parameter S1_RANGE_MATCH = 4'b0001,
parameter S2_ENABLE = 1,
parameter S2_RANGE_WIDTH = 4,
parameter S2_RANGE_MATCH = 4'b0010,
parameter S3_ENABLE = 1,
parameter S3_RANGE_WIDTH = 4,
parameter S3_RANGE_MATCH = 4'b0011,
parameter S4_ENABLE = 1,
parameter S4_RANGE_WIDTH = 4,
parameter S4_RANGE_MATCH = 4'b0100,
parameter S5_ENABLE = 1,
parameter S5_RANGE_WIDTH = 4,
parameter S5_RANGE_MATCH = 4'b0101,
parameter S6_ENABLE = 1,
parameter S6_RANGE_WIDTH = 4,
parameter S6_RANGE_MATCH = 4'b0110,
parameter S7_ENABLE = 1,
parameter S7_RANGE_WIDTH = 4,
parameter S7_RANGE_MATCH = 4'b0111,
parameter S8_ENABLE = 1,
parameter S8_RANGE_WIDTH = 4,
parameter S8_RANGE_MATCH = 4'b1000,
parameter S9_ENABLE = 1,
parameter S9_RANGE_WIDTH = 4,
parameter S9_RANGE_MATCH = 4'b1001
)
(
/* Ports */
input clk_i,
input rst_i,
input [ADDR_WIDTH-1:0] m_adr_i,
input [DATA_WIDTH-1:0] m_dat_i,
input m_cyc_i,
input m_stb_i,
input [SEL_WIDTH-1:0] m_sel_i,
input m_we_i,
input [2:0] m_cti_i,
input [1:0] m_bte_i,
output reg [DATA_WIDTH-1:0] m_dat_o,
output m_ack_o,
output m_err_o,
output m_rty_o,
output reg [ADDR_WIDTH*SLAVES-1:0] s_adr_o,
output reg [DATA_WIDTH*SLAVES-1:0] s_dat_o,
output reg [SLAVES-1:0] s_cyc_o,
output reg [SLAVES-1:0] s_stb_o,
output reg [SEL_WIDTH*SLAVES-1:0] s_sel_o,
output reg [SLAVES-1:0] s_we_o,
output reg [SLAVES*3-1:0] s_cti_o,
output reg [SLAVES*2-1:0] s_bte_o,
input [DATA_WIDTH*SLAVES-1:0] s_dat_i,
input [SLAVES-1:0] s_ack_i,
input [SLAVES-1:0] s_err_i,
input [SLAVES-1:0] s_rty_i
);
wire [SLAVES-1:0] s_select;
// Generate the slave select signals based on the master bus
// address and the memory range parameters
generate
if (SLAVES > 0)
assign s_select[0] = S0_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S0_RANGE_WIDTH] == S0_RANGE_MATCH[S0_RANGE_WIDTH-1:0]);
if (SLAVES > 1)
assign s_select[1] = S1_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S1_RANGE_WIDTH] == S1_RANGE_MATCH[S1_RANGE_WIDTH-1:0]);
if (SLAVES > 2)
assign s_select[2] = S2_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S2_RANGE_WIDTH] == S2_RANGE_MATCH[S2_RANGE_WIDTH-1:0]);
if (SLAVES > 3)
assign s_select[3] = S3_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S3_RANGE_WIDTH] == S3_RANGE_MATCH[S3_RANGE_WIDTH-1:0]);
if (SLAVES > 4)
assign s_select[4] = S4_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S4_RANGE_WIDTH] == S4_RANGE_MATCH[S4_RANGE_WIDTH-1:0]);
if (SLAVES > 5)
assign s_select[5] = S5_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S5_RANGE_WIDTH] == S5_RANGE_MATCH[S5_RANGE_WIDTH-1:0]);
if (SLAVES > 6)
assign s_select[6] = S6_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S6_RANGE_WIDTH] == S6_RANGE_MATCH[S6_RANGE_WIDTH-1:0]);
if (SLAVES > 7)
assign s_select[7] = S7_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S7_RANGE_WIDTH] == S7_RANGE_MATCH[S7_RANGE_WIDTH-1:0]);
if (SLAVES > 8)
assign s_select[8] = S8_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S8_RANGE_WIDTH] == S8_RANGE_MATCH[S8_RANGE_WIDTH-1:0]);
if (SLAVES > 9)
assign s_select[9] = S9_ENABLE & (m_adr_i[ADDR_WIDTH-1 -: S9_RANGE_WIDTH] == S9_RANGE_MATCH[S9_RANGE_WIDTH-1:0]);
endgenerate
// If two s_select are high or none, we might have an bus error
wire bus_error;
assign bus_error = ~^s_select;
reg m_ack, m_err, m_rty;
// Mux the slave bus based on the slave select signal (one hot!)
always @(*) begin : bus_s_mux
integer i;
m_dat_o = {DATA_WIDTH{1'b0}};
m_ack = 1'b0;
m_err = 1'b0;
m_rty = 1'b0;
for (i = 0; i < SLAVES; i = i + 1) begin
s_adr_o[i*ADDR_WIDTH +: ADDR_WIDTH] = m_adr_i;
s_dat_o[i*DATA_WIDTH +: DATA_WIDTH] = m_dat_i;
s_sel_o[i*SEL_WIDTH +: SEL_WIDTH] = m_sel_i;
s_we_o[i] = m_we_i;
s_cti_o[i*3 +: 3] = m_cti_i;
s_bte_o[i*2 +: 2] = m_bte_i;
s_cyc_o[i] = m_cyc_i & s_select[i];
s_stb_o[i] = m_stb_i & s_select[i];
if (s_select[i]) begin
m_dat_o = s_dat_i[i*DATA_WIDTH +: DATA_WIDTH];
m_ack = s_ack_i[i];
m_err = s_err_i[i];
m_rty = s_rty_i[i];
end
end
end
assign m_ack_o = m_ack & !bus_error;
assign m_err_o = m_err | bus_error;
assign m_rty_o = m_rty & !bus_error;
endmodule // wb_sselect
|
/* Copyright (c) 2013 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a round-robin arbiter for N participants, which is a
* parameter. The arbiter itself contains no register but is purely
* combinational which allows for various use cases. It simply
* calculates the next grant (nxt_gnt) based on the current grant
* (gnt) and the requests (req).
*
* That means, the gnt should in general be a register and especially
* there must be no combinational path from nxt_gnt to gnt!
*
* The normal usage is something like registering the gnt from
* nxt_gnt. Furthermore it is important that the gnt has an initial
* value which also must be one hot!
*
* Author(s):
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*/
module wb_interconnect_arb_rr(/*AUTOARG*/
// Outputs
nxt_gnt,
// Inputs
req, gnt
);
/* User parameters */
// Number of participants
parameter N = 1;
/* Ports */
// Request
input [N-1:0] req;
// Current grant
input [N-1:0] gnt;
// Next grant
output [N-1:0] nxt_gnt;
// Sanity check
// synthesis translate_off
//always @(*)
// if (~^gnt)
// $fatal("signal <gnt> must always be one hot!");
// synthesis translate_on
// At a first glance, the computation of the nxt_gnt signal looks
// strange, but the principle is easy:
//
// * For each participant we compute a mask of width N. Based on
// the current gnt signal the mask contains a 1 at the position
// of other participants that will be served in round robin
// before the participant in case they request it.
//
// * The mask is 0 on all positions for the participant "left" of
// the currently granted participant as no other has precedence
// over this one. The mask has all one except the participant
// itself for the currently arbitrated participant.
//
// * From the mask and the request the nxt_gnt is calculated,
// roughly said as: if there is no other participant which has a
// higher precedence that also requests, the participant gets
// granted.
//
// Example 1:
// req = 1010
// gnt = 1000
// nxt_gnt = 0010
//
// mask[0] = 0000
// mask[1] = 0001
// mask[2] = 0011
// mask[3] = 0111
//
// Example 2:
// req = 1010
// gnt = 0100
// nxt_gnt = 1000
//
// mask[0] = 1000
// mask[1] = 1001
// mask[2] = 1011
// mask[3] = 0000
// Mask net
reg [N-1:0] mask [0:N-1];
// Calculate the mask
always @(*) begin : calc_mask
integer i,j;
for (i=0;i<N;i=i+1) begin
// Initialize mask as 0
mask[i] = {N{1'b0}};
// All participants to the "right" up to the current grant
// holder have precendence and therefore a 1 in the mask.
// First check if the next right from us has the grant.
// Afterwards the mask is calculated iteratively based on
// this.
if(i>0)
// For i=N:1 the next right is i-1
mask[i][i-1] = ~gnt[i-1];
else
// For i=0 the next right is N-1
mask[i][N-1] = ~gnt[N-1];
// Now the mask contains a 1 when the next right to us is not
// the grant holder. If it is the grant holder that means,
// that we are the next served (if necessary) as no other has
// higher precendence, which is then calculated in the
// following by filling up 1s up to the grant holder. To stop
// filling up there and not fill up any after this is
// iterative by always checking if the one before was not
// before the grant holder.
for (j=2;j<N;j=j+1) begin
if (i-j>=0)
mask[i][i-j] = mask[i][i-j+1] & ~gnt[i-j];
else if(i-j+1>=0)
mask[i][i-j+N] = mask[i][i-j+1] & ~gnt[i-j+N];
else
mask[i][i-j+N] = mask[i][i-j+N+1] & ~gnt[i-j+N];
end
end
end // always @ (*)
// Calculate the nxt_gnt
genvar k;
generate
for (k=0;k<N;k=k+1) begin : gen_nxt_gnt
// (mask[k] & req) masks all requests with higher precendence
// Example 1: 0: 0000 1: 0000 2: 0010 3: 0010
// Example 2: 0: 1000 1: 1000 2: 1010 3: 0000
//
// ~|(mask[k] & req) is there is none of them
// Example 1: 0: 1 1: 1 2: 0 3: 0
// Example 2: 1: 0 1: 0 2: 0 3: 1
//
// One might expect at this point that there was only one of
// them that matches, but this is guaranteed by the last part
// that is checking if this one has a request itself. In
// example 1, k=0 does not have a request, if it had, the
// result of the previous calculation would be 0 for k=1.
// Therefore: (~|(mask[k] & req) & req[k]) selects the next one.
// Example 1: 0: 0 1: 1 2: 0 3: 0
// Example 2: 0: 0 1: 0 2: 0 3: 1
//
// This is already the result. (0010 and 1000). Nevertheless,
// it is necessary to capture the case of no request at all
// (~|req). In that case, nxt_gnt would be 0, what iself
// leads to a problem in the next cycle (always grants).
// Therefore the current gnt is hold in case of no request by
// (~|req & gnt[k]).
assign nxt_gnt[k] = (~|(mask[k] & req) & req[k]) | (~|req & gnt[k]);
end
endgenerate
endmodule // wb_interconnect_arb_rr
|
/* Copyright (c) 2013-2017 by the author(s)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* =============================================================================
*
* This is a generic wishbone bus multiplexer (B3). The number of
* masters is configurable.
*
* DATA_WIDTH and ADDR_WIDTH are defined in bits. DATA_WIDTH must be
* full bytes (i.e., multiple of 8)!
*
* The ports are flattened. That means, that all masters share the bus
* signal ports. With four masters and a data width of 32 bit the
* m_cyc_i port is 4 bit wide and the m_dat_i is 128 (=4*32) bit wide.
* The signals are arranged from right to left, meaning the m_dat_i is
* defined as [DATA_WIDTH*MASTERS-1:0] and each port m is assigned to
* [(m+1)*DATA_WIDTH-1:m*DATA_WIDTH].
*
* Author(s):
* Stefan Wallentowitz <stefan.wallentowitz@tum.de>
*/
// TODO: * check bus hold signal correctness
module wb_mux
#(
/* User parameters */
// Set the number of slaves
parameter MASTERS = 1,
// Set bus address and data width in bits
// DATA_WIDTH must be a multiple of 8 (full bytes)!
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32,
/* Derived local parameters */
// Width of byte select registers
localparam SEL_WIDTH = DATA_WIDTH >> 3
)
(
/* Ports */
input clk_i,
input rst_i,
input [ADDR_WIDTH*MASTERS-1:0] m_adr_i,
input [DATA_WIDTH*MASTERS-1:0] m_dat_i,
input [MASTERS-1:0] m_cyc_i,
input [MASTERS-1:0] m_stb_i,
input [SEL_WIDTH*MASTERS-1:0] m_sel_i,
input [MASTERS-1:0] m_we_i,
input [MASTERS*3-1:0] m_cti_i,
input [MASTERS*2-1:0] m_bte_i,
output reg [DATA_WIDTH*MASTERS-1:0] m_dat_o,
output reg [MASTERS-1:0] m_ack_o,
output reg [MASTERS-1:0] m_err_o,
output reg [MASTERS-1:0] m_rty_o,
output reg [ADDR_WIDTH-1:0] s_adr_o,
output reg [DATA_WIDTH-1:0] s_dat_o,
output reg s_cyc_o,
output reg s_stb_o,
output reg [SEL_WIDTH-1:0] s_sel_o,
output reg s_we_o,
output reg [2:0] s_cti_o,
output reg [1:0] s_bte_o,
input [DATA_WIDTH-1:0] s_dat_i,
input s_ack_i,
input s_err_i,
input s_rty_i,
input bus_hold,
output reg bus_hold_ack
);
// The granted master is one hot encoded
wire [MASTERS-1:0] grant;
// The granted master from previous cycle (register)
reg [MASTERS-1:0] prev_grant;
// This is a net that masks the actual requests. The arbiter
// selects a different master each cycle. Therefore we need to
// actively control the return of the bus arbitration. That means
// as long as the granted master still holds is cycle signal, we
// mask out all other requests (be setting the requests to grant).
// When the cycle signal is released, we set the request to all
// masters cycle signals.
reg [MASTERS-1:0] m_req;
// This is the arbitration net from round robin
wire [MASTERS-1:0] arb_grant;
reg [MASTERS-1:0] prev_arb_grant;
// It is masked with the bus_hold_ack to hold back the arbitration
// as long as the bus is held
assign grant = arb_grant & {MASTERS{!bus_hold_ack}};
always @(*) begin
if (|(m_cyc_i & prev_grant)) begin
// The bus is not released this cycle
m_req = prev_grant;
bus_hold_ack = 1'b0;
end else begin
m_req = m_cyc_i;
bus_hold_ack = bus_hold;
end
end
// We register the grant signal. This is needed nevertheless for
// fair arbitration (round robin)
always @(posedge clk_i) begin
if (rst_i) begin
prev_arb_grant <= {{MASTERS-1{1'b0}},1'b1};
prev_grant <= {{MASTERS-1{1'b0}},1'b1};
end else begin
prev_arb_grant <= arb_grant;
prev_grant <= grant;
end
end
/* wb_interconnect_arb_rr AUTO_TEMPLATE(
.gnt (prev_arb_grant),
.nxt_gnt (arb_grant),
.req (m_req),
); */
wb_interconnect_arb_rr
#(.N(MASTERS))
u_arbiter(/*AUTOINST*/
// Outputs
.nxt_gnt (arb_grant), // Templated
// Inputs
.req (m_req), // Templated
.gnt (prev_arb_grant)); // Templated
// Mux the bus based on the grant signal which must be one hot!
always @(*) begin : bus_m_mux
integer i;
s_adr_o = {ADDR_WIDTH{1'bx}};
s_dat_o = {DATA_WIDTH{1'bx}};
s_sel_o = {SEL_WIDTH{1'bx}};
s_we_o = 1'bx;
s_cti_o = 3'bx;
s_bte_o = 2'bx;
s_cyc_o = 1'b0;
s_stb_o = 1'b0;
for (i = 0; i < MASTERS; i = i + 1) begin
m_dat_o[i*DATA_WIDTH +: DATA_WIDTH] = s_dat_i;
m_ack_o[i] = grant[i] & s_ack_i;
m_err_o[i] = grant[i] & s_err_i;
m_rty_o[i] = grant[i] & s_rty_i;
if (grant[i]) begin
s_adr_o = m_adr_i[(i+1)*ADDR_WIDTH-1 -: ADDR_WIDTH];
s_dat_o = m_dat_i[(i+1)*DATA_WIDTH-1 -: DATA_WIDTH];
s_sel_o = m_sel_i[(i+1)*SEL_WIDTH-1 -: SEL_WIDTH];
s_we_o = m_we_i[i];
s_cti_o = m_cti_i[(i+1)*3-1 -: 3];
s_bte_o = m_bte_i[(i+1)*2-1 -: 2];
s_cyc_o = m_cyc_i[i];
s_stb_o = m_stb_i[i];
end
end
end
endmodule // wb_sselect
|
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// assumes input does not change between start going high and out_valid
module aes_128(clk, start, state, key, out, out_valid);
input clk;
input start;
input [127:0] state, key;
output [127:0] out;
output out_valid;
reg [127:0] s0, k0;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9,
k1, k2, k3, k4, k5, k6, k7, k8, k9,
k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b;
reg start_r;
always @(posedge clk)
begin
start_r <= start;
end
wire start_posedge = start & ~start_r;
reg [4:0] validCounter;
always @ (posedge clk)
begin
if(start_posedge)
begin
s0 <= state ^ key;
k0 <= key;
validCounter <= 21;
end
else if(~out_valid)
begin
validCounter <= validCounter - 1;
end
end
assign out_valid = (validCounter == 0);
expand_key_128
a1 (clk, k0, k1, k0b, 8'h1),
a2 (clk, k1, k2, k1b, 8'h2),
a3 (clk, k2, k3, k2b, 8'h4),
a4 (clk, k3, k4, k3b, 8'h8),
a5 (clk, k4, k5, k4b, 8'h10),
a6 (clk, k5, k6, k5b, 8'h20),
a7 (clk, k6, k7, k6b, 8'h40),
a8 (clk, k7, k8, k7b, 8'h80),
a9 (clk, k8, k9, k8b, 8'h1b),
a10 (clk, k9, , k9b, 8'h36);
one_round
r1 (clk, s0, k0b, s1),
r2 (clk, s1, k1b, s2),
r3 (clk, s2, k2b, s3),
r4 (clk, s3, k3b, s4),
r5 (clk, s4, k4b, s5),
r6 (clk, s5, k5b, s6),
r7 (clk, s6, k6b, s7),
r8 (clk, s7, k7b, s8),
r9 (clk, s8, k8b, s9);
final_round
rf (clk, s9, k9b, out);
endmodule
module expand_key_128(clk, in, out_1, out_2, rcon);
input clk;
input [127:0] in;
input [7:0] rcon;
output reg [127:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3,
v0, v1, v2, v3;
reg [31:0] k0a, k1a, k2a, k3a;
wire [31:0] k0b, k1b, k2b, k3b, k4a;
assign {k0, k1, k2, k3} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
assign v2 = v1 ^ k2;
assign v3 = v2 ^ k3;
always @ (posedge clk)
{k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};
S4
S4_0 (clk, {k3[23:0], k3[31:24]}, k4a);
assign k0b = k0a ^ k4a;
assign k1b = k1a ^ k4a;
assign k2b = k2a ^ k4a;
assign k3b = k3a ^ k4a;
always @ (posedge clk)
out_1 <= {k0b, k1b, k2b, k3b};
assign out_2 = {k0b, k1b, k2b, k3b};
endmodule
|
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// This is a fully unrolled implementation
module aes_192 (clk, rst, start, state, key, out, out_valid);
input clk;
input rst;
input start;
input [127:0] state;
input [191:0] key;
output [127:0] out;
output out_valid;
// Internals signals and such
reg [127:0] s0;
reg [191:0] k0;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11;
wire [191:0] k1, k2, k3, k4, k5, k6, k7, k8, k9, k10, k11;
wire [127:0] k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b, k10b, k11b;
reg start_r;
wire start_posedge = start & ~start_r;
reg [4:0] validCounter;
always @(posedge clk or posedge rst)
begin
if (rst)
start_r <= 1'b0;
else
start_r <= start;
end // end always
always @ (posedge clk or posedge rst)
begin
if (rst) begin
s0 <= 0;
k0 <= 0;
validCounter <= 0;
end else
if(start_posedge)
begin
s0 <= state ^ key[191:64];
k0 <= key;
validCounter <= 26;
end
else if(validCounter > 1)
begin
validCounter <= validCounter - 1;
end
end // end always
assign out_valid = (validCounter == 1);
expand_key_type_D_192 a0 (clk, rst, k0, 8'h1, k1, k0b);
expand_key_type_B_192 a1 (clk, rst, k1, k2, k1b);
expand_key_type_A_192 a2 (clk, rst, k2, 8'h2, k3, k2b);
expand_key_type_C_192 a3 (clk, rst, k3, 8'h4, k4, k3b);
expand_key_type_B_192 a4 (clk, rst, k4, k5, k4b);
expand_key_type_A_192 a5 (clk, rst, k5, 8'h8, k6, k5b);
expand_key_type_C_192 a6 (clk, rst, k6, 8'h10, k7, k6b);
expand_key_type_B_192 a7 (clk, rst, k7, k8, k7b);
expand_key_type_A_192 a8 (clk, rst, k8, 8'h20, k9, k8b);
expand_key_type_C_192 a9 (clk, rst, k9, 8'h40, k10, k9b);
expand_key_type_B_192 a10 (clk, rst, k10, k11, k10b);
expand_key_type_A_192 a11 (clk, rst, k11, 8'h80, , k11b);
one_round
r1 (clk, rst, s0, k0b, s1),
r2 (clk, rst, s1, k1b, s2),
r3 (clk, rst, s2, k2b, s3),
r4 (clk, rst, s3, k3b, s4),
r5 (clk, rst, s4, k4b, s5),
r6 (clk, rst, s5, k5b, s6),
r7 (clk, rst, s6, k6b, s7),
r8 (clk, rst, s7, k7b, s8),
r9 (clk, rst, s8, k8b, s9),
r10 (clk, rst, s9, k9b, s10),
r11 (clk, rst, s10, k10b, s11);
final_round
rf (clk, rst, s11, k11b, out);
endmodule
/* expand k0,k1,k2,k3 for every two clock cycles */
module expand_key_type_A_192 (clk, rst, in, rcon, out_1, out_2);
input clk;
input rst;
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output [127:0] out_2;
// Internal signals
wire [31:0] k0, k1, k2, k3, k4, k5, v0, v1, v2, v3;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
assign v2 = v1 ^ k2;
assign v3 = v2 ^ k3;
always @ (posedge clk or posedge rst)
begin
if (rst)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {32'd0, 32'd0, 32'd0, 32'd0, 32'd0, 32'd0};
else
{k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, v2, v3, k4, k5};
end // end always
S4 S4_0 (clk, rst, {k5[23:0], k5[31:24]}, k6a);
assign k0b = k0a ^ k6a;
assign k1b = k1a ^ k6a;
assign k2b = k2a ^ k6a;
assign k3b = k3a ^ k6a;
assign {k4b, k5b} = {k4a, k5a};
always @ (posedge clk or posedge rst)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
end // end always
assign out_2 = {k0b, k1b, k2b, k3b};
endmodule // end module expand_key_type_A_192
/* expand k2,k3,k4,k5 for every two clock cycles */
module expand_key_type_B_192 (clk, rst, in, out_1, out_2);
input clk;
input rst;
input [191:0] in;
output reg [191:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5, v2, v3, v4, v5;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v2 = k1 ^ k2;
assign v3 = v2 ^ k3;
assign v4 = v3 ^ k4;
assign v5 = v4 ^ k5;
always @ (posedge clk or posedge rst)
begin
if (rst)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {32'd0, 32'd0, 32'd0, 32'd0, 32'd0, 32'd0};
else
{k0a, k1a, k2a, k3a, k4a, k5a} <= {k0, k1, v2, v3, v4, v5};
end // end always
always @ (posedge clk or posedge rst)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0a, k1a, k2a, k3a, k4a, k5a};
end
assign out_2 = {k2a, k3a, k4a, k5a};
endmodule // end expand_key_type_B_192
/* expand k0,k1,k4,k5 for every two clock cycles */
module expand_key_type_C_192 (clk, rst, in, rcon, out_1, out_2);
input clk;
input rst;
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5, v4, v5, v0, v1;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v4 = k3 ^ k4;
assign v5 = v4 ^ k5;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
always @ (posedge clk or posedge rst)
begin
if (rst)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {32'd0, 32'd0, 32'd0, 32'd0, 32'd0, 32'd0};
else
{k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, k2, k3, v4, v5};
end
S4 S4_0 (clk, rst, {v5[23:0], v5[31:24]}, k6a);
assign k0b = k0a ^ k6a;
assign k1b = k1a ^ k6a;
assign {k2b, k3b, k4b, k5b} = {k2a, k3a, k4a, k5a};
always @ (posedge clk or posedge rst)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
end
assign out_2 = {k4b, k5b, k0b, k1b};
endmodule // end expand_key_type_C_192
/* expand k0,k1 for every two clock cycles */
module expand_key_type_D_192 (clk, rst, in, rcon, out_1, out_2);
input clk;
input rst;
input [191:0] in;
input [7:0] rcon;
output reg [191:0] out_1;
output [127:0] out_2;
wire [31:0] k0, k1, k2, k3, k4, k5, v0, v1;
reg [31:0] k0a, k1a, k2a, k3a, k4a, k5a;
wire [31:0] k0b, k1b, k2b, k3b, k4b, k5b, k6a;
assign {k0, k1, k2, k3, k4, k5} = in;
assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
assign v1 = v0 ^ k1;
always @ (posedge clk or posedge rst)
begin
if (rst)
{k0a, k1a, k2a, k3a, k4a, k5a} <= {32'd0, 32'd0, 32'd0, 32'd0, 32'd0, 32'd0};
else
{k0a, k1a, k2a, k3a, k4a, k5a} <= {v0, v1, k2, k3, k4, k5};
end // end always
S4 S4_0 (clk, rst, {k5[23:0], k5[31:24]}, k6a);
assign k0b = k0a ^ k6a;
assign k1b = k1a ^ k6a;
assign {k2b, k3b, k4b, k5b} = {k2a, k3a, k4a, k5a};
always @ (posedge clk or posedge rst)
begin
if (rst)
out_1 <= 0;
else
out_1 <= {k0b, k1b, k2b, k3b, k4b, k5b};
end // end always
assign out_2 = {k4b, k5b, k0b, k1b};
endmodule // end expand_key_type_D_192
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : aes_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-AES core
//
module aes_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
// As of now, no errors are generated
assign wb_err_o = 1'b0;
// Interrupt is unused
assign int_o = 1'b0;
// Internal registers
reg start, start_r;
reg [31:0] pt [0:3];
reg [31:0] key [0:5];
reg wb_stb_i_r;
wire [127:0] pt_big = {pt[0], pt[1], pt[2], pt[3]};
wire [191:0] key_big = {key[0], key[1], key[2], key[3], key[4], key[5]};
wire [127:0] ct;
wire ct_valid;
// Generate the acknowledgement signal
assign wb_ack_o = wb_stb_i_r && wb_stb_i;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i or negedge wb_rst_i)
begin
if(wb_rst_i)
begin
start <= 0;
start_r <= 0;
pt[0] <= 0;
pt[1] <= 0;
pt[2] <= 0;
pt[3] <= 0;
key[0] <= 0;
key[1] <= 0;
key[2] <= 0;
key[3] <= 0;
key[4] <= 0;
key[5] <= 0;
wb_stb_i_r <= 1'b0;
end
else begin
// Generate registered version of start (for edge detection)
start_r <= start;
// Generate a registered version of the write strobe
wb_stb_i_r <= wb_stb_i;
// Perform a write
if(wb_stb_i & wb_we_i) begin
case(wb_adr_i[5:2])
0: start <= wb_dat_i[0];
1: pt[3] <= wb_dat_i;
2: pt[2] <= wb_dat_i;
3: pt[1] <= wb_dat_i;
4: pt[0] <= wb_dat_i;
5: key[5] <= wb_dat_i;
6: key[4] <= wb_dat_i;
7: key[3] <= wb_dat_i;
8: key[2] <= wb_dat_i;
9: key[1] <= wb_dat_i;
10: key[0] <= wb_dat_i;
default:
;
endcase
end else begin // end if wb_stb_i & wb_we_i
start <= 1'b0;
end
end // end else begin
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[5:2])
1:
wb_dat_o = pt[3];
2:
wb_dat_o = pt[2];
3:
wb_dat_o = pt[1];
4:
wb_dat_o = pt[0];
5:
wb_dat_o = key[5];
6:
wb_dat_o = key[4];
7:
wb_dat_o = key[3];
8:
wb_dat_o = key[2];
9:
wb_dat_o = key[1];
10:
wb_dat_o = key[0];
11:
wb_dat_o = {31'b0, ct_valid};
12:
wb_dat_o = ct[127:96];
13:
wb_dat_o = ct[95:64];
14:
wb_dat_o = ct[63:32];
15:
wb_dat_o = ct[31:0];
default:
wb_dat_o = 32'b0;
endcase
end // always @ (*)
aes_192 aes(
.clk(wb_clk_i),
.rst(wb_rst_i),
.state(pt_big),
.key(key_big),
.start(start && ~start_r), // start on detected position edge
.out(ct),
.out_valid(ct_valid)
);
endmodule
|
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* verilator lint_off UNOPTFLAT */
/* one AES round for every two clock cycles */
module one_round (clk, rst, state_in, key, state_out);
input clk;
input rst;
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33,
k0, k1, k2, k3;
assign {k0, k1, k2, k3} = key;
assign {s0, s1, s2, s3} = state_in;
table_lookup
t0 (clk, rst, s0, p00, p01, p02, p03),
t1 (clk, rst, s1, p10, p11, p12, p13),
t2 (clk, rst, s2, p20, p21, p22, p23),
t3 (clk, rst, s3, p30, p31, p32, p33);
assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0;
assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1;
assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2;
assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3;
always @ (posedge clk)
state_out <= {z0, z1, z2, z3};
endmodule
/* AES final round for every two clock cycles */
module final_round (clk, rst, state_in, key_in, state_out);
input clk;
input rst;
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33;
assign {k0, k1, k2, k3} = key_in;
assign {s0, s1, s2, s3} = state_in;
S4
S4_1 (clk, rst, s0, {p00, p01, p02, p03}),
S4_2 (clk, rst, s1, {p10, p11, p12, p13}),
S4_3 (clk, rst, s2, {p20, p21, p22, p23}),
S4_4 (clk, rst, s3, {p30, p31, p32, p33});
assign z0 = {p00, p11, p22, p33} ^ k0;
assign z1 = {p10, p21, p32, p03} ^ k1;
assign z2 = {p20, p31, p02, p13} ^ k2;
assign z3 = {p30, p01, p12, p23} ^ k3;
always @ (posedge clk or posedge rst)
if (rst)
state_out <= 0;
else
state_out <= {z0, z1, z2, z3};
endmodule
|
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* verilator lint_off UNOPTFLAT */
module table_lookup (clk, rst, state, p0, p1, p2, p3);
input clk;
input rst;
input [31:0] state;
output [31:0] p0, p1, p2, p3;
wire [7:0] b0, b1, b2, b3;
assign {b0, b1, b2, b3} = state;
T
t0 (clk, rst, b0, {p0[23:0], p0[31:24]}),
t1 (clk, rst, b1, {p1[15:0], p1[31:16]}),
t2 (clk, rst, b2, {p2[7:0], p2[31:8]} ),
t3 (clk, rst, b3, p3);
endmodule // end table_lookup
/* substitue four bytes in a word */
module S4 (clk, rst, in, out);
input clk;
input rst;
input [31:0] in;
output [31:0] out;
S
S_0 (clk, rst, in[31:24], out[31:24]),
S_1 (clk, rst, in[23:16], out[23:16]),
S_2 (clk, rst, in[15:8], out[15:8] ),
S_3 (clk, rst, in[7:0], out[7:0] );
endmodule // end S4
/* S_box, S_box, S_box*(x+1), S_box*x */
module T (clk, rst, in, out);
input clk;
input rst;
input [7:0] in;
output [31:0] out;
S
s0 (clk, rst, in, out[31:24]);
assign out[23:16] = out[31:24];
xS
s4 (clk, rst, in, out[7:0]);
assign out[15:8] = out[23:16] ^ out[7:0];
endmodule // end T
/* S box */
module S (clk, rst, in, out);
input clk;
input rst;
input [7:0] in;
output reg [7:0] out;
always @ (posedge clk or posedge rst)
if (rst)
out <= 8'd0;
else
case (in)
8'h00: out <= 8'h63;
8'h01: out <= 8'h7c;
8'h02: out <= 8'h77;
8'h03: out <= 8'h7b;
8'h04: out <= 8'hf2;
8'h05: out <= 8'h6b;
8'h06: out <= 8'h6f;
8'h07: out <= 8'hc5;
8'h08: out <= 8'h30;
8'h09: out <= 8'h01;
8'h0a: out <= 8'h67;
8'h0b: out <= 8'h2b;
8'h0c: out <= 8'hfe;
8'h0d: out <= 8'hd7;
8'h0e: out <= 8'hab;
8'h0f: out <= 8'h76;
8'h10: out <= 8'hca;
8'h11: out <= 8'h82;
8'h12: out <= 8'hc9;
8'h13: out <= 8'h7d;
8'h14: out <= 8'hfa;
8'h15: out <= 8'h59;
8'h16: out <= 8'h47;
8'h17: out <= 8'hf0;
8'h18: out <= 8'had;
8'h19: out <= 8'hd4;
8'h1a: out <= 8'ha2;
8'h1b: out <= 8'haf;
8'h1c: out <= 8'h9c;
8'h1d: out <= 8'ha4;
8'h1e: out <= 8'h72;
8'h1f: out <= 8'hc0;
8'h20: out <= 8'hb7;
8'h21: out <= 8'hfd;
8'h22: out <= 8'h93;
8'h23: out <= 8'h26;
8'h24: out <= 8'h36;
8'h25: out <= 8'h3f;
8'h26: out <= 8'hf7;
8'h27: out <= 8'hcc;
8'h28: out <= 8'h34;
8'h29: out <= 8'ha5;
8'h2a: out <= 8'he5;
8'h2b: out <= 8'hf1;
8'h2c: out <= 8'h71;
8'h2d: out <= 8'hd8;
8'h2e: out <= 8'h31;
8'h2f: out <= 8'h15;
8'h30: out <= 8'h04;
8'h31: out <= 8'hc7;
8'h32: out <= 8'h23;
8'h33: out <= 8'hc3;
8'h34: out <= 8'h18;
8'h35: out <= 8'h96;
8'h36: out <= 8'h05;
8'h37: out <= 8'h9a;
8'h38: out <= 8'h07;
8'h39: out <= 8'h12;
8'h3a: out <= 8'h80;
8'h3b: out <= 8'he2;
8'h3c: out <= 8'heb;
8'h3d: out <= 8'h27;
8'h3e: out <= 8'hb2;
8'h3f: out <= 8'h75;
8'h40: out <= 8'h09;
8'h41: out <= 8'h83;
8'h42: out <= 8'h2c;
8'h43: out <= 8'h1a;
8'h44: out <= 8'h1b;
8'h45: out <= 8'h6e;
8'h46: out <= 8'h5a;
8'h47: out <= 8'ha0;
8'h48: out <= 8'h52;
8'h49: out <= 8'h3b;
8'h4a: out <= 8'hd6;
8'h4b: out <= 8'hb3;
8'h4c: out <= 8'h29;
8'h4d: out <= 8'he3;
8'h4e: out <= 8'h2f;
8'h4f: out <= 8'h84;
8'h50: out <= 8'h53;
8'h51: out <= 8'hd1;
8'h52: out <= 8'h00;
8'h53: out <= 8'hed;
8'h54: out <= 8'h20;
8'h55: out <= 8'hfc;
8'h56: out <= 8'hb1;
8'h57: out <= 8'h5b;
8'h58: out <= 8'h6a;
8'h59: out <= 8'hcb;
8'h5a: out <= 8'hbe;
8'h5b: out <= 8'h39;
8'h5c: out <= 8'h4a;
8'h5d: out <= 8'h4c;
8'h5e: out <= 8'h58;
8'h5f: out <= 8'hcf;
8'h60: out <= 8'hd0;
8'h61: out <= 8'hef;
8'h62: out <= 8'haa;
8'h63: out <= 8'hfb;
8'h64: out <= 8'h43;
8'h65: out <= 8'h4d;
8'h66: out <= 8'h33;
8'h67: out <= 8'h85;
8'h68: out <= 8'h45;
8'h69: out <= 8'hf9;
8'h6a: out <= 8'h02;
8'h6b: out <= 8'h7f;
8'h6c: out <= 8'h50;
8'h6d: out <= 8'h3c;
8'h6e: out <= 8'h9f;
8'h6f: out <= 8'ha8;
8'h70: out <= 8'h51;
8'h71: out <= 8'ha3;
8'h72: out <= 8'h40;
8'h73: out <= 8'h8f;
8'h74: out <= 8'h92;
8'h75: out <= 8'h9d;
8'h76: out <= 8'h38;
8'h77: out <= 8'hf5;
8'h78: out <= 8'hbc;
8'h79: out <= 8'hb6;
8'h7a: out <= 8'hda;
8'h7b: out <= 8'h21;
8'h7c: out <= 8'h10;
8'h7d: out <= 8'hff;
8'h7e: out <= 8'hf3;
8'h7f: out <= 8'hd2;
8'h80: out <= 8'hcd;
8'h81: out <= 8'h0c;
8'h82: out <= 8'h13;
8'h83: out <= 8'hec;
8'h84: out <= 8'h5f;
8'h85: out <= 8'h97;
8'h86: out <= 8'h44;
8'h87: out <= 8'h17;
8'h88: out <= 8'hc4;
8'h89: out <= 8'ha7;
8'h8a: out <= 8'h7e;
8'h8b: out <= 8'h3d;
8'h8c: out <= 8'h64;
8'h8d: out <= 8'h5d;
8'h8e: out <= 8'h19;
8'h8f: out <= 8'h73;
8'h90: out <= 8'h60;
8'h91: out <= 8'h81;
8'h92: out <= 8'h4f;
8'h93: out <= 8'hdc;
8'h94: out <= 8'h22;
8'h95: out <= 8'h2a;
8'h96: out <= 8'h90;
8'h97: out <= 8'h88;
8'h98: out <= 8'h46;
8'h99: out <= 8'hee;
8'h9a: out <= 8'hb8;
8'h9b: out <= 8'h14;
8'h9c: out <= 8'hde;
8'h9d: out <= 8'h5e;
8'h9e: out <= 8'h0b;
8'h9f: out <= 8'hdb;
8'ha0: out <= 8'he0;
8'ha1: out <= 8'h32;
8'ha2: out <= 8'h3a;
8'ha3: out <= 8'h0a;
8'ha4: out <= 8'h49;
8'ha5: out <= 8'h06;
8'ha6: out <= 8'h24;
8'ha7: out <= 8'h5c;
8'ha8: out <= 8'hc2;
8'ha9: out <= 8'hd3;
8'haa: out <= 8'hac;
8'hab: out <= 8'h62;
8'hac: out <= 8'h91;
8'had: out <= 8'h95;
8'hae: out <= 8'he4;
8'haf: out <= 8'h79;
8'hb0: out <= 8'he7;
8'hb1: out <= 8'hc8;
8'hb2: out <= 8'h37;
8'hb3: out <= 8'h6d;
8'hb4: out <= 8'h8d;
8'hb5: out <= 8'hd5;
8'hb6: out <= 8'h4e;
8'hb7: out <= 8'ha9;
8'hb8: out <= 8'h6c;
8'hb9: out <= 8'h56;
8'hba: out <= 8'hf4;
8'hbb: out <= 8'hea;
8'hbc: out <= 8'h65;
8'hbd: out <= 8'h7a;
8'hbe: out <= 8'hae;
8'hbf: out <= 8'h08;
8'hc0: out <= 8'hba;
8'hc1: out <= 8'h78;
8'hc2: out <= 8'h25;
8'hc3: out <= 8'h2e;
8'hc4: out <= 8'h1c;
8'hc5: out <= 8'ha6;
8'hc6: out <= 8'hb4;
8'hc7: out <= 8'hc6;
8'hc8: out <= 8'he8;
8'hc9: out <= 8'hdd;
8'hca: out <= 8'h74;
8'hcb: out <= 8'h1f;
8'hcc: out <= 8'h4b;
8'hcd: out <= 8'hbd;
8'hce: out <= 8'h8b;
8'hcf: out <= 8'h8a;
8'hd0: out <= 8'h70;
8'hd1: out <= 8'h3e;
8'hd2: out <= 8'hb5;
8'hd3: out <= 8'h66;
8'hd4: out <= 8'h48;
8'hd5: out <= 8'h03;
8'hd6: out <= 8'hf6;
8'hd7: out <= 8'h0e;
8'hd8: out <= 8'h61;
8'hd9: out <= 8'h35;
8'hda: out <= 8'h57;
8'hdb: out <= 8'hb9;
8'hdc: out <= 8'h86;
8'hdd: out <= 8'hc1;
8'hde: out <= 8'h1d;
8'hdf: out <= 8'h9e;
8'he0: out <= 8'he1;
8'he1: out <= 8'hf8;
8'he2: out <= 8'h98;
8'he3: out <= 8'h11;
8'he4: out <= 8'h69;
8'he5: out <= 8'hd9;
8'he6: out <= 8'h8e;
8'he7: out <= 8'h94;
8'he8: out <= 8'h9b;
8'he9: out <= 8'h1e;
8'hea: out <= 8'h87;
8'heb: out <= 8'he9;
8'hec: out <= 8'hce;
8'hed: out <= 8'h55;
8'hee: out <= 8'h28;
8'hef: out <= 8'hdf;
8'hf0: out <= 8'h8c;
8'hf1: out <= 8'ha1;
8'hf2: out <= 8'h89;
8'hf3: out <= 8'h0d;
8'hf4: out <= 8'hbf;
8'hf5: out <= 8'he6;
8'hf6: out <= 8'h42;
8'hf7: out <= 8'h68;
8'hf8: out <= 8'h41;
8'hf9: out <= 8'h99;
8'hfa: out <= 8'h2d;
8'hfb: out <= 8'h0f;
8'hfc: out <= 8'hb0;
8'hfd: out <= 8'h54;
8'hfe: out <= 8'hbb;
8'hff: out <= 8'h16;
endcase
endmodule
/* S box * x */
module xS (clk, rst, in, out);
input clk;
input rst;
input [7:0] in;
output reg [7:0] out;
always @ (posedge clk or posedge rst)
if (rst)
out <= 8'd0;
else
case (in)
8'h00: out <= 8'hc6;
8'h01: out <= 8'hf8;
8'h02: out <= 8'hee;
8'h03: out <= 8'hf6;
8'h04: out <= 8'hff;
8'h05: out <= 8'hd6;
8'h06: out <= 8'hde;
8'h07: out <= 8'h91;
8'h08: out <= 8'h60;
8'h09: out <= 8'h02;
8'h0a: out <= 8'hce;
8'h0b: out <= 8'h56;
8'h0c: out <= 8'he7;
8'h0d: out <= 8'hb5;
8'h0e: out <= 8'h4d;
8'h0f: out <= 8'hec;
8'h10: out <= 8'h8f;
8'h11: out <= 8'h1f;
8'h12: out <= 8'h89;
8'h13: out <= 8'hfa;
8'h14: out <= 8'hef;
8'h15: out <= 8'hb2;
8'h16: out <= 8'h8e;
8'h17: out <= 8'hfb;
8'h18: out <= 8'h41;
8'h19: out <= 8'hb3;
8'h1a: out <= 8'h5f;
8'h1b: out <= 8'h45;
8'h1c: out <= 8'h23;
8'h1d: out <= 8'h53;
8'h1e: out <= 8'he4;
8'h1f: out <= 8'h9b;
8'h20: out <= 8'h75;
8'h21: out <= 8'he1;
8'h22: out <= 8'h3d;
8'h23: out <= 8'h4c;
8'h24: out <= 8'h6c;
8'h25: out <= 8'h7e;
8'h26: out <= 8'hf5;
8'h27: out <= 8'h83;
8'h28: out <= 8'h68;
8'h29: out <= 8'h51;
8'h2a: out <= 8'hd1;
8'h2b: out <= 8'hf9;
8'h2c: out <= 8'he2;
8'h2d: out <= 8'hab;
8'h2e: out <= 8'h62;
8'h2f: out <= 8'h2a;
8'h30: out <= 8'h08;
8'h31: out <= 8'h95;
8'h32: out <= 8'h46;
8'h33: out <= 8'h9d;
8'h34: out <= 8'h30;
8'h35: out <= 8'h37;
8'h36: out <= 8'h0a;
8'h37: out <= 8'h2f;
8'h38: out <= 8'h0e;
8'h39: out <= 8'h24;
8'h3a: out <= 8'h1b;
8'h3b: out <= 8'hdf;
8'h3c: out <= 8'hcd;
8'h3d: out <= 8'h4e;
8'h3e: out <= 8'h7f;
8'h3f: out <= 8'hea;
8'h40: out <= 8'h12;
8'h41: out <= 8'h1d;
8'h42: out <= 8'h58;
8'h43: out <= 8'h34;
8'h44: out <= 8'h36;
8'h45: out <= 8'hdc;
8'h46: out <= 8'hb4;
8'h47: out <= 8'h5b;
8'h48: out <= 8'ha4;
8'h49: out <= 8'h76;
8'h4a: out <= 8'hb7;
8'h4b: out <= 8'h7d;
8'h4c: out <= 8'h52;
8'h4d: out <= 8'hdd;
8'h4e: out <= 8'h5e;
8'h4f: out <= 8'h13;
8'h50: out <= 8'ha6;
8'h51: out <= 8'hb9;
8'h52: out <= 8'h00;
8'h53: out <= 8'hc1;
8'h54: out <= 8'h40;
8'h55: out <= 8'he3;
8'h56: out <= 8'h79;
8'h57: out <= 8'hb6;
8'h58: out <= 8'hd4;
8'h59: out <= 8'h8d;
8'h5a: out <= 8'h67;
8'h5b: out <= 8'h72;
8'h5c: out <= 8'h94;
8'h5d: out <= 8'h98;
8'h5e: out <= 8'hb0;
8'h5f: out <= 8'h85;
8'h60: out <= 8'hbb;
8'h61: out <= 8'hc5;
8'h62: out <= 8'h4f;
8'h63: out <= 8'hed;
8'h64: out <= 8'h86;
8'h65: out <= 8'h9a;
8'h66: out <= 8'h66;
8'h67: out <= 8'h11;
8'h68: out <= 8'h8a;
8'h69: out <= 8'he9;
8'h6a: out <= 8'h04;
8'h6b: out <= 8'hfe;
8'h6c: out <= 8'ha0;
8'h6d: out <= 8'h78;
8'h6e: out <= 8'h25;
8'h6f: out <= 8'h4b;
8'h70: out <= 8'ha2;
8'h71: out <= 8'h5d;
8'h72: out <= 8'h80;
8'h73: out <= 8'h05;
8'h74: out <= 8'h3f;
8'h75: out <= 8'h21;
8'h76: out <= 8'h70;
8'h77: out <= 8'hf1;
8'h78: out <= 8'h63;
8'h79: out <= 8'h77;
8'h7a: out <= 8'haf;
8'h7b: out <= 8'h42;
8'h7c: out <= 8'h20;
8'h7d: out <= 8'he5;
8'h7e: out <= 8'hfd;
8'h7f: out <= 8'hbf;
8'h80: out <= 8'h81;
8'h81: out <= 8'h18;
8'h82: out <= 8'h26;
8'h83: out <= 8'hc3;
8'h84: out <= 8'hbe;
8'h85: out <= 8'h35;
8'h86: out <= 8'h88;
8'h87: out <= 8'h2e;
8'h88: out <= 8'h93;
8'h89: out <= 8'h55;
8'h8a: out <= 8'hfc;
8'h8b: out <= 8'h7a;
8'h8c: out <= 8'hc8;
8'h8d: out <= 8'hba;
8'h8e: out <= 8'h32;
8'h8f: out <= 8'he6;
8'h90: out <= 8'hc0;
8'h91: out <= 8'h19;
8'h92: out <= 8'h9e;
8'h93: out <= 8'ha3;
8'h94: out <= 8'h44;
8'h95: out <= 8'h54;
8'h96: out <= 8'h3b;
8'h97: out <= 8'h0b;
8'h98: out <= 8'h8c;
8'h99: out <= 8'hc7;
8'h9a: out <= 8'h6b;
8'h9b: out <= 8'h28;
8'h9c: out <= 8'ha7;
8'h9d: out <= 8'hbc;
8'h9e: out <= 8'h16;
8'h9f: out <= 8'had;
8'ha0: out <= 8'hdb;
8'ha1: out <= 8'h64;
8'ha2: out <= 8'h74;
8'ha3: out <= 8'h14;
8'ha4: out <= 8'h92;
8'ha5: out <= 8'h0c;
8'ha6: out <= 8'h48;
8'ha7: out <= 8'hb8;
8'ha8: out <= 8'h9f;
8'ha9: out <= 8'hbd;
8'haa: out <= 8'h43;
8'hab: out <= 8'hc4;
8'hac: out <= 8'h39;
8'had: out <= 8'h31;
8'hae: out <= 8'hd3;
8'haf: out <= 8'hf2;
8'hb0: out <= 8'hd5;
8'hb1: out <= 8'h8b;
8'hb2: out <= 8'h6e;
8'hb3: out <= 8'hda;
8'hb4: out <= 8'h01;
8'hb5: out <= 8'hb1;
8'hb6: out <= 8'h9c;
8'hb7: out <= 8'h49;
8'hb8: out <= 8'hd8;
8'hb9: out <= 8'hac;
8'hba: out <= 8'hf3;
8'hbb: out <= 8'hcf;
8'hbc: out <= 8'hca;
8'hbd: out <= 8'hf4;
8'hbe: out <= 8'h47;
8'hbf: out <= 8'h10;
8'hc0: out <= 8'h6f;
8'hc1: out <= 8'hf0;
8'hc2: out <= 8'h4a;
8'hc3: out <= 8'h5c;
8'hc4: out <= 8'h38;
8'hc5: out <= 8'h57;
8'hc6: out <= 8'h73;
8'hc7: out <= 8'h97;
8'hc8: out <= 8'hcb;
8'hc9: out <= 8'ha1;
8'hca: out <= 8'he8;
8'hcb: out <= 8'h3e;
8'hcc: out <= 8'h96;
8'hcd: out <= 8'h61;
8'hce: out <= 8'h0d;
8'hcf: out <= 8'h0f;
8'hd0: out <= 8'he0;
8'hd1: out <= 8'h7c;
8'hd2: out <= 8'h71;
8'hd3: out <= 8'hcc;
8'hd4: out <= 8'h90;
8'hd5: out <= 8'h06;
8'hd6: out <= 8'hf7;
8'hd7: out <= 8'h1c;
8'hd8: out <= 8'hc2;
8'hd9: out <= 8'h6a;
8'hda: out <= 8'hae;
8'hdb: out <= 8'h69;
8'hdc: out <= 8'h17;
8'hdd: out <= 8'h99;
8'hde: out <= 8'h3a;
8'hdf: out <= 8'h27;
8'he0: out <= 8'hd9;
8'he1: out <= 8'heb;
8'he2: out <= 8'h2b;
8'he3: out <= 8'h22;
8'he4: out <= 8'hd2;
8'he5: out <= 8'ha9;
8'he6: out <= 8'h07;
8'he7: out <= 8'h33;
8'he8: out <= 8'h2d;
8'he9: out <= 8'h3c;
8'hea: out <= 8'h15;
8'heb: out <= 8'hc9;
8'hec: out <= 8'h87;
8'hed: out <= 8'haa;
8'hee: out <= 8'h50;
8'hef: out <= 8'ha5;
8'hf0: out <= 8'h03;
8'hf1: out <= 8'h59;
8'hf2: out <= 8'h09;
8'hf3: out <= 8'h1a;
8'hf4: out <= 8'h65;
8'hf5: out <= 8'hd7;
8'hf6: out <= 8'h84;
8'hf7: out <= 8'hd0;
8'hf8: out <= 8'h82;
8'hf9: out <= 8'h29;
8'hfa: out <= 8'h5a;
8'hfb: out <= 8'h1e;
8'hfc: out <= 8'h7b;
8'hfd: out <= 8'ha8;
8'hfe: out <= 8'h6d;
8'hff: out <= 8'h2c;
endcase
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Defines of the Core ////
//// ////
//// Known problems (limits): ////
//// None ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - gorban@opencores.org ////
//// - Jacob Gorban ////
//// - Igor Mohor (igorm@opencores.org) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Timescale define
`timescale 1ns/10ps
|
/////////////////////////////////////////////////////////////////////
//// ////
//// CRP ////
//// DES Crypt Module ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module crp(P, R, K_sub);
/* verilator lint_off LITENDIAN */
output [1:32] P;
input [1:32] R;
input [1:48] K_sub;
wire [1:48] E;
wire [1:48] X;
wire [1:32] S;
/* verilator lint_on LITENDIAN */
assign E[1:48] = { R[32], R[1], R[2], R[3], R[4], R[5], R[4], R[5],
R[6], R[7], R[8], R[9], R[8], R[9], R[10], R[11],
R[12], R[13], R[12], R[13], R[14], R[15], R[16],
R[17], R[16], R[17], R[18], R[19], R[20], R[21],
R[20], R[21], R[22], R[23], R[24], R[25], R[24],
R[25], R[26], R[27], R[28], R[29], R[28], R[29],
R[30], R[31], R[32], R[1]};
assign X = E ^ K_sub;
sbox1 u0( .addr(X[01:06]), .dout(S[01:04]) );
sbox2 u1( .addr(X[07:12]), .dout(S[05:08]) );
sbox3 u2( .addr(X[13:18]), .dout(S[09:12]) );
sbox4 u3( .addr(X[19:24]), .dout(S[13:16]) );
sbox5 u4( .addr(X[25:30]), .dout(S[17:20]) );
sbox6 u5( .addr(X[31:36]), .dout(S[21:24]) );
sbox7 u6( .addr(X[37:42]), .dout(S[25:28]) );
sbox8 u7( .addr(X[43:48]), .dout(S[29:32]) );
assign P[1:32] = { S[16], S[7], S[20], S[21], S[29], S[12], S[28],
S[17], S[1], S[15], S[23], S[26], S[5], S[18],
S[31], S[10], S[2], S[8], S[24], S[14], S[32],
S[27], S[3], S[9], S[19], S[13], S[30], S[6],
S[22], S[11], S[4], S[25]};
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// DES ////
//// DES Top Level module ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module des3(desOut, out_valid, start, desIn, key1, key2, key3, decrypt, clk);
output reg[63:0] desOut;
output out_valid;
input start;
input [63:0] desIn;
input [55:0] key1;
input [55:0] key2;
input [55:0] key3;
input decrypt;
input clk;
/* verilator lint_off LITENDIAN */
wire [1:48] K_sub;
wire [1:64] IP, FP;
reg [1:64] FP_R;
reg [1:32] L, R;
wire [1:32] Xin;
wire [1:32] Lout;
wire [1:32] Rout;
wire [1:32] out;
/* verilator lint_on LITENDIAN */
reg [5:0] roundSel;
reg start_r;
always @(posedge clk)
begin
start_r <= start;
end
wire start_posedge = start & ~start_r;
reg [7:0] validCounter;
wire [63:0] des;
always @ (posedge clk)
begin
if(start_posedge)
begin
roundSel <= 6'h00;
end
else if(~out_valid)
begin
roundSel <= roundSel +1;
end
end
assign out_valid = (roundSel == 6'h30);
always @ (posedge clk)
begin
if(!out_valid)
begin
desOut <= des;
end
end
crp u0(
.P(out),
.R(Lout),
.K_sub(K_sub));
// Select a subkey from key.
key_sel3 u1(
.K_sub(K_sub),
.key1(key1),
.key2(key2),
.key3(key3),
.roundSel(roundSel),
.decrypt(decrypt)
);
assign Lout = (roundSel == 0) ? IP[33:64] : ((roundSel == 16) ? FP_R[33:64] : ((roundSel == 32) ? FP_R[33:64] : R));
assign Xin = (roundSel == 0) ? IP[01:32] : ((roundSel == 16) ? FP_R[01:32] : ((roundSel == 32) ? FP_R[01:32] : L));
always @(posedge clk)
FP_R <= FP;
assign Rout = Xin ^ out;
assign FP = { Rout, Lout};
always @(posedge clk)
L <= Lout;
always @(posedge clk)
R <= Rout;
// Perform initial permutation
assign IP[1:64] = {desIn[06], desIn[14], desIn[22], desIn[30], desIn[38], desIn[46],
desIn[54], desIn[62], desIn[04], desIn[12], desIn[20], desIn[28],
desIn[36], desIn[44], desIn[52], desIn[60], desIn[02], desIn[10],
desIn[18], desIn[26], desIn[34], desIn[42], desIn[50], desIn[58],
desIn[00], desIn[08], desIn[16], desIn[24], desIn[32], desIn[40],
desIn[48], desIn[56], desIn[07], desIn[15], desIn[23], desIn[31],
desIn[39], desIn[47], desIn[55], desIn[63], desIn[05], desIn[13],
desIn[21], desIn[29], desIn[37], desIn[45], desIn[53], desIn[61],
desIn[03], desIn[11], desIn[19], desIn[27], desIn[35], desIn[43],
desIn[51], desIn[59], desIn[01], desIn[09], desIn[17], desIn[25],
desIn[33], desIn[41], desIn[49], desIn[57] };
// Perform final permutation
assign des = {FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32],
FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31],
FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30],
FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29],
FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28],
FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27],
FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26],
FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] };
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// DES TEST BENCH ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module test;
reg clk;
reg [319:0] x[512:0];
reg [319:0] tmp;
reg [5:0] cnt;
integer select;
integer decrypt;
wire [63:0] desOut;
wire [63:0] des_in;
wire [63:0] exp_out;
wire [55:0] key1;
wire [55:0] key2;
wire [55:0] key3;
integer ZZZ;
initial
begin
$display("\n\n");
$display("*********************************************************");
$display("* Area Optimized DES core simulation started ... *");
$display("*********************************************************");
$display("\n");
//`ifdef WAVES
// $shm_open("waves");
// $shm_probe("AS",test,"AS");
// $display("INFO: Signal dump enabled ...\n\n");
//`endif
if(1)
begin
$dumpfile("./iverilog/test.vcd");
$dumpvars(0,test);
end
clk=0;
ZZZ=0;
// key1 key2 key3 Test data Out data
x[0]=320'h0101010101010101_0101010101010101_0101010101010101_95F8A5E5DD31D900_8000000000000000;
x[1]=320'h0101010101010101_0101010101010101_0101010101010101_9D64555A9A10B852_0000001000000000;
x[2]=320'h3849674C2602319E_3849674C2602319E_3849674C2602319E_51454B582DDF440A_7178876E01F19B2A;
x[3]=320'h04B915BA43FEB5B6_04B915BA43FEB5B6_04B915BA43FEB5B6_42FD443059577FA2_AF37FB421F8C4095;
x[4]=320'h0123456789ABCDEF_0123456789ABCDEF_0123456789ABCDEF_736F6D6564617461_3D124FE2198BA318;
x[5]=320'h0123456789ABCDEF_5555555555555555_0123456789ABCDEF_736F6D6564617461_FBABA1FF9D05E9B1;
x[6]=320'h0123456789ABCDEF_5555555555555555_FEDCBA9876543210_736F6D6564617461_18d748e563620572;
x[7]=320'h0352020767208217_8602876659082198_64056ABDFEA93457_7371756967676C65_c07d2a0fa566fa30;
x[8]=320'h0101010101010101_8001010101010101_0101010101010102_0000000000000000_e6e6dd5b7e722974;
x[9]=320'h1046103489988020_9107D01589190101_19079210981A0101_0000000000000000_e1ef62c332fe825b;
decrypt = 0;
@(posedge clk);
$display("");
$display("**************************************");
$display("* Starting DES Test ... *");
$display("**************************************");
$display("");
for(decrypt=0;decrypt<2;decrypt=decrypt+1)
begin
if(decrypt)
$display("Running Encrypt test ...\n");
else
$display("Running Decrypt test ...\n");
for(select=0;select<16;select=select+1)
begin
tmp=x[select];
for(cnt=0;cnt<47;cnt=cnt+1)
@(posedge clk);
#10;
if((exp_out !== desOut) | (^exp_out===1'bx) | (^desOut===1'bx))
$display("ERROR: (%0d) Expected %x Got %x", select, exp_out, desOut);
else
$display("PASS : (%0d) Expected %x Got %x", select, exp_out, desOut);
//#2 $display("%h %h %h %h %h", key3, key2, key1, des_in, exp_out);
@(posedge clk);
end
end
$display("");
$display("**************************************");
$display("* DES Test done ... *");
$display("**************************************");
$display("");
$finish;
end // end of innitial
always #100 clk=~clk;
assign #1 key1 = {tmp[319:313],tmp[311:305],tmp[303:297],tmp[295:289],
tmp[287:281],tmp[279:273],tmp[271:265],tmp[263:257]};
assign #1 key2 = {tmp[255:249],tmp[247:241],tmp[239:233],tmp[231:225],
tmp[223:217],tmp[215:209],tmp[207:201],tmp[199:193]};
assign #1 key3 = {tmp[191:185],tmp[183:177],tmp[175:169],tmp[167:161],
tmp[159:153],tmp[151:145],tmp[143:137],tmp[135:129]};
assign #1 des_in = decrypt[0] ? tmp[63:0] : tmp[127:64];
assign exp_out = decrypt[0] ? tmp[127:64] : tmp[63:0];
des3 u0( .clk( clk ),
.desOut( desOut ),
.desIn( des_in ),
.key1( key1 ),
.key2( key2 ),
.key3( key3 ),
.roundSel( cnt ),
.decrypt( decrypt[0] )
);
endmodule
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : des3_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-DES3 core
//
module des3_top #(
parameter remove_parity_bits=0)
(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg start, start_r;
reg decrypt;
reg [31:0] desIn [0:1];
reg [31:0] key [0:5];
reg wb_stb_i_r;
wire [63:0] des_in={desIn[0], desIn[1]};
wire [55:0] key_1;
wire [55:0] key_2;
wire [55:0] key_3;
wire [63:0] ct;
wire ct_valid;
// The following generate logic is to used to remove the parity bits from the key
// This was performed in the C test code that loaded vectors
genvar i;
generate if (remove_parity_bits == 1) begin
for (i = 0; i < 4; i = i + 1) begin
assign key_1[34 + i*7:28 + i*7] = key[0][i*8+1 + 6:i*8+1];
assign key_1[ 6 + i*7: i*7] = key[1][i*8+1 + 6:i*8+1];
assign key_2[34 + i*7:28 + i*7] = key[2][i*8+1 + 6:i*8+1];
assign key_2[ 6 + i*7: i*7] = key[3][i*8+1 + 6:i*8+1];
assign key_3[34 + i*7:28 + i*7] = key[4][i*8+1 + 6:i*8+1];
assign key_3[ 6 + i*7: i*7] = key[5][i*8+1 + 6:i*8+1];
end // generate for (i = 0; i < 4; i = i + 1)
end else begin
assign key_1 = {key[0][27:0], key[1][27:0]};
assign key_2 = {key[2][27:0], key[3][27:0]};
assign key_3 = {key[4][27:0], key[5][27:0]};
end // end else
endgenerate
// Generate the acknowledgement signal
assign wb_ack_o = wb_stb_i_r && wb_stb_i;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i)
begin
if(wb_rst_i)
begin
start <= 0;
start_r <= 0;
decrypt <= 0;
desIn[1] <= 0;
desIn[0] <= 0;
key[5] <= 0;
key[4] <= 0;
key[3] <= 0;
key[2] <= 0;
key[1] <= 0;
key[0] <= 0;
wb_stb_i_r <= 1'b0;
end
else begin
// Generate registered versions of start
start_r <= start;
// Generate a registered version of the write strobe
wb_stb_i_r <= wb_stb_i;
// Peform a write
if(wb_stb_i & wb_we_i) begin
case(wb_adr_i[5:2])
0:
start <= wb_dat_i[0];
1:
decrypt <= wb_dat_i[0];
2:
desIn[1]<= wb_dat_i;
3:
desIn[0]<= wb_dat_i;
4:
key[5] <= wb_dat_i;
5:
key[4] <= wb_dat_i;
6:
key[3] <= wb_dat_i;
7:
key[2] <= wb_dat_i;
8:
key[1] <= wb_dat_i;
9:
key[0] <= wb_dat_i;
default:
;
endcase
end else begin // if wb_stb_i & wb_we_i
start <= 1'b0;
end
end // else
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[5:2])
2:
wb_dat_o = desIn[1];
3:
wb_dat_o = desIn[0];
4:
wb_dat_o = key[5];
5:
wb_dat_o = key[4];
6:
wb_dat_o = key[3];
7:
wb_dat_o = key[2];
8:
wb_dat_o = key[1];
9:
wb_dat_o = key[0];
10:
wb_dat_o = {31'b0, ct_valid};
11:
wb_dat_o = ct[63:32];
12:
wb_dat_o = ct[31:0];
default:
wb_dat_o = 32'b0;
endcase
end // always @ (*)
des3 des3(
.desOut(ct),
.out_valid(ct_valid),
.start(start && ~start_r),
.desIn(des_in),
.key1(key_1),
.key2(key_2),
.key3(key_3),
.decrypt(decrypt),
.clk(wb_clk_i));
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// KEY_SEL ////
//// Select one of 16 sub-keys for round ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module key_sel3(K_sub, key1, key2, key3, roundSel, decrypt);
/* verilator lint_off LITENDIAN */
output [1:48] K_sub;
/* verilator lint_on LITENDIAN */
input [55:0] key1, key2, key3;
input [5:0] roundSel;
input decrypt;
wire decrypt_int;
reg [55:0] K;
reg [1:48] K_sub;
/* verilator lint_off LITENDIAN */
wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9;
wire [1:48] K10, K11, K12, K13, K14, K15, K16;
/* verilator lint_on LITENDIAN */
always @(roundSel or decrypt or key1 or key2 or key3)
case ({decrypt, roundSel[5:4]}) // synopsys full_case parallel_case
3'b0_00:
K = key1;
3'b0_01:
K = key2;
3'b0_10:
K = key3;
3'b1_00:
K = key3;
3'b1_01:
K = key2;
3'b1_10:
K = key1;
3'b0_11:
K = 56'b0;
3'b1_11:
K = 56'b0;
endcase
assign decrypt_int = (roundSel[5:4]==2'h1) ? !decrypt : decrypt;
always @(K1 or K2 or K3 or K4 or K5 or K6 or K7 or K8 or K9 or K10
or K11 or K12 or K13 or K14 or K15 or K16 or roundSel)
case(roundSel[3:0]) // synopsys full_case parallel_case
0:
K_sub = K1;
1:
K_sub = K2;
2:
K_sub = K3;
3:
K_sub = K4;
4:
K_sub = K5;
5:
K_sub = K6;
6:
K_sub = K7;
7:
K_sub = K8;
8:
K_sub = K9;
9:
K_sub = K10;
10:
K_sub = K11;
11:
K_sub = K12;
12:
K_sub = K13;
13:
K_sub = K14;
14:
K_sub = K15;
15:
K_sub = K16;
endcase
assign K16[1] = decrypt_int ? K[47] : K[40];
assign K16[2] = decrypt_int ? K[11] : K[4];
assign K16[3] = decrypt_int ? K[26] : K[19];
assign K16[4] = decrypt_int ? K[3] : K[53];
assign K16[5] = decrypt_int ? K[13] : K[6];
assign K16[6] = decrypt_int ? K[41] : K[34];
assign K16[7] = decrypt_int ? K[27] : K[20];
assign K16[8] = decrypt_int ? K[6] : K[24];
assign K16[9] = decrypt_int ? K[54] : K[47];
assign K16[10] = decrypt_int ? K[48] : K[41];
assign K16[11] = decrypt_int ? K[39] : K[32];
assign K16[12] = decrypt_int ? K[19] : K[12];
assign K16[13] = decrypt_int ? K[53] : K[46];
assign K16[14] = decrypt_int ? K[25] : K[18];
assign K16[15] = decrypt_int ? K[33] : K[26];
assign K16[16] = decrypt_int ? K[34] : K[27];
assign K16[17] = decrypt_int ? K[17] : K[10];
assign K16[18] = decrypt_int ? K[5] : K[55];
assign K16[19] = decrypt_int ? K[4] : K[54];
assign K16[20] = decrypt_int ? K[55] : K[48];
assign K16[21] = decrypt_int ? K[24] : K[17];
assign K16[22] = decrypt_int ? K[32] : K[25];
assign K16[23] = decrypt_int ? K[40] : K[33];
assign K16[24] = decrypt_int ? K[20] : K[13];
assign K16[25] = decrypt_int ? K[36] : K[29];
assign K16[26] = decrypt_int ? K[31] : K[51];
assign K16[27] = decrypt_int ? K[21] : K[14];
assign K16[28] = decrypt_int ? K[8] : K[1];
assign K16[29] = decrypt_int ? K[23] : K[16];
assign K16[30] = decrypt_int ? K[52] : K[45];
assign K16[31] = decrypt_int ? K[14] : K[7];
assign K16[32] = decrypt_int ? K[29] : K[22];
assign K16[33] = decrypt_int ? K[51] : K[44];
assign K16[34] = decrypt_int ? K[9] : K[2];
assign K16[35] = decrypt_int ? K[35] : K[28];
assign K16[36] = decrypt_int ? K[30] : K[23];
assign K16[37] = decrypt_int ? K[2] : K[50];
assign K16[38] = decrypt_int ? K[37] : K[30];
assign K16[39] = decrypt_int ? K[22] : K[15];
assign K16[40] = decrypt_int ? K[0] : K[52];
assign K16[41] = decrypt_int ? K[42] : K[35];
assign K16[42] = decrypt_int ? K[38] : K[31];
assign K16[43] = decrypt_int ? K[16] : K[9];
assign K16[44] = decrypt_int ? K[43] : K[36];
assign K16[45] = decrypt_int ? K[44] : K[37];
assign K16[46] = decrypt_int ? K[1] : K[49];
assign K16[47] = decrypt_int ? K[7] : K[0];
assign K16[48] = decrypt_int ? K[28] : K[21];
assign K15[1] = decrypt_int ? K[54] : K[33];
assign K15[2] = decrypt_int ? K[18] : K[54];
assign K15[3] = decrypt_int ? K[33] : K[12];
assign K15[4] = decrypt_int ? K[10] : K[46];
assign K15[5] = decrypt_int ? K[20] : K[24];
assign K15[6] = decrypt_int ? K[48] : K[27];
assign K15[7] = decrypt_int ? K[34] : K[13];
assign K15[8] = decrypt_int ? K[13] : K[17];
assign K15[9] = decrypt_int ? K[4] : K[40];
assign K15[10] = decrypt_int ? K[55] : K[34];
assign K15[11] = decrypt_int ? K[46] : K[25];
assign K15[12] = decrypt_int ? K[26] : K[5];
assign K15[13] = decrypt_int ? K[3] : K[39];
assign K15[14] = decrypt_int ? K[32] : K[11];
assign K15[15] = decrypt_int ? K[40] : K[19];
assign K15[16] = decrypt_int ? K[41] : K[20];
assign K15[17] = decrypt_int ? K[24] : K[3];
assign K15[18] = decrypt_int ? K[12] : K[48];
assign K15[19] = decrypt_int ? K[11] : K[47];
assign K15[20] = decrypt_int ? K[5] : K[41];
assign K15[21] = decrypt_int ? K[6] : K[10];
assign K15[22] = decrypt_int ? K[39] : K[18];
assign K15[23] = decrypt_int ? K[47] : K[26];
assign K15[24] = decrypt_int ? K[27] : K[6];
assign K15[25] = decrypt_int ? K[43] : K[22];
assign K15[26] = decrypt_int ? K[38] : K[44];
assign K15[27] = decrypt_int ? K[28] : K[7];
assign K15[28] = decrypt_int ? K[15] : K[49];
assign K15[29] = decrypt_int ? K[30] : K[9];
assign K15[30] = decrypt_int ? K[0] : K[38];
assign K15[31] = decrypt_int ? K[21] : K[0];
assign K15[32] = decrypt_int ? K[36] : K[15];
assign K15[33] = decrypt_int ? K[31] : K[37];
assign K15[34] = decrypt_int ? K[16] : K[50];
assign K15[35] = decrypt_int ? K[42] : K[21];
assign K15[36] = decrypt_int ? K[37] : K[16];
assign K15[37] = decrypt_int ? K[9] : K[43];
assign K15[38] = decrypt_int ? K[44] : K[23];
assign K15[39] = decrypt_int ? K[29] : K[8];
assign K15[40] = decrypt_int ? K[7] : K[45];
assign K15[41] = decrypt_int ? K[49] : K[28];
assign K15[42] = decrypt_int ? K[45] : K[51];
assign K15[43] = decrypt_int ? K[23] : K[2];
assign K15[44] = decrypt_int ? K[50] : K[29];
assign K15[45] = decrypt_int ? K[51] : K[30];
assign K15[46] = decrypt_int ? K[8] : K[42];
assign K15[47] = decrypt_int ? K[14] : K[52];
assign K15[48] = decrypt_int ? K[35] : K[14];
assign K14[1] = decrypt_int ? K[11] : K[19];
assign K14[2] = decrypt_int ? K[32] : K[40];
assign K14[3] = decrypt_int ? K[47] : K[55];
assign K14[4] = decrypt_int ? K[24] : K[32];
assign K14[5] = decrypt_int ? K[34] : K[10];
assign K14[6] = decrypt_int ? K[5] : K[13];
assign K14[7] = decrypt_int ? K[48] : K[24];
assign K14[8] = decrypt_int ? K[27] : K[3];
assign K14[9] = decrypt_int ? K[18] : K[26];
assign K14[10] = decrypt_int ? K[12] : K[20];
assign K14[11] = decrypt_int ? K[3] : K[11];
assign K14[12] = decrypt_int ? K[40] : K[48];
assign K14[13] = decrypt_int ? K[17] : K[25];
assign K14[14] = decrypt_int ? K[46] : K[54];
assign K14[15] = decrypt_int ? K[54] : K[5];
assign K14[16] = decrypt_int ? K[55] : K[6];
assign K14[17] = decrypt_int ? K[13] : K[46];
assign K14[18] = decrypt_int ? K[26] : K[34];
assign K14[19] = decrypt_int ? K[25] : K[33];
assign K14[20] = decrypt_int ? K[19] : K[27];
assign K14[21] = decrypt_int ? K[20] : K[53];
assign K14[22] = decrypt_int ? K[53] : K[4];
assign K14[23] = decrypt_int ? K[4] : K[12];
assign K14[24] = decrypt_int ? K[41] : K[17];
assign K14[25] = decrypt_int ? K[2] : K[8];
assign K14[26] = decrypt_int ? K[52] : K[30];
assign K14[27] = decrypt_int ? K[42] : K[52];
assign K14[28] = decrypt_int ? K[29] : K[35];
assign K14[29] = decrypt_int ? K[44] : K[50];
assign K14[30] = decrypt_int ? K[14] : K[51];
assign K14[31] = decrypt_int ? K[35] : K[45];
assign K14[32] = decrypt_int ? K[50] : K[1];
assign K14[33] = decrypt_int ? K[45] : K[23];
assign K14[34] = decrypt_int ? K[30] : K[36];
assign K14[35] = decrypt_int ? K[1] : K[7];
assign K14[36] = decrypt_int ? K[51] : K[2];
assign K14[37] = decrypt_int ? K[23] : K[29];
assign K14[38] = decrypt_int ? K[31] : K[9];
assign K14[39] = decrypt_int ? K[43] : K[49];
assign K14[40] = decrypt_int ? K[21] : K[31];
assign K14[41] = decrypt_int ? K[8] : K[14];
assign K14[42] = decrypt_int ? K[0] : K[37];
assign K14[43] = decrypt_int ? K[37] : K[43];
assign K14[44] = decrypt_int ? K[9] : K[15];
assign K14[45] = decrypt_int ? K[38] : K[16];
assign K14[46] = decrypt_int ? K[22] : K[28];
assign K14[47] = decrypt_int ? K[28] : K[38];
assign K14[48] = decrypt_int ? K[49] : K[0];
assign K13[1] = decrypt_int ? K[25] : K[5];
assign K13[2] = decrypt_int ? K[46] : K[26];
assign K13[3] = decrypt_int ? K[4] : K[41];
assign K13[4] = decrypt_int ? K[13] : K[18];
assign K13[5] = decrypt_int ? K[48] : K[53];
assign K13[6] = decrypt_int ? K[19] : K[24];
assign K13[7] = decrypt_int ? K[5] : K[10];
assign K13[8] = decrypt_int ? K[41] : K[46];
assign K13[9] = decrypt_int ? K[32] : K[12];
assign K13[10] = decrypt_int ? K[26] : K[6];
assign K13[11] = decrypt_int ? K[17] : K[54];
assign K13[12] = decrypt_int ? K[54] : K[34];
assign K13[13] = decrypt_int ? K[6] : K[11];
assign K13[14] = decrypt_int ? K[3] : K[40];
assign K13[15] = decrypt_int ? K[11] : K[48];
assign K13[16] = decrypt_int ? K[12] : K[17];
assign K13[17] = decrypt_int ? K[27] : K[32];
assign K13[18] = decrypt_int ? K[40] : K[20];
assign K13[19] = decrypt_int ? K[39] : K[19];
assign K13[20] = decrypt_int ? K[33] : K[13];
assign K13[21] = decrypt_int ? K[34] : K[39];
assign K13[22] = decrypt_int ? K[10] : K[47];
assign K13[23] = decrypt_int ? K[18] : K[55];
assign K13[24] = decrypt_int ? K[55] : K[3];
assign K13[25] = decrypt_int ? K[16] : K[49];
assign K13[26] = decrypt_int ? K[7] : K[16];
assign K13[27] = decrypt_int ? K[1] : K[38];
assign K13[28] = decrypt_int ? K[43] : K[21];
assign K13[29] = decrypt_int ? K[31] : K[36];
assign K13[30] = decrypt_int ? K[28] : K[37];
assign K13[31] = decrypt_int ? K[49] : K[31];
assign K13[32] = decrypt_int ? K[9] : K[42];
assign K13[33] = decrypt_int ? K[0] : K[9];
assign K13[34] = decrypt_int ? K[44] : K[22];
assign K13[35] = decrypt_int ? K[15] : K[52];
assign K13[36] = decrypt_int ? K[38] : K[43];
assign K13[37] = decrypt_int ? K[37] : K[15];
assign K13[38] = decrypt_int ? K[45] : K[50];
assign K13[39] = decrypt_int ? K[2] : K[35];
assign K13[40] = decrypt_int ? K[35] : K[44];
assign K13[41] = decrypt_int ? K[22] : K[0];
assign K13[42] = decrypt_int ? K[14] : K[23];
assign K13[43] = decrypt_int ? K[51] : K[29];
assign K13[44] = decrypt_int ? K[23] : K[1];
assign K13[45] = decrypt_int ? K[52] : K[2];
assign K13[46] = decrypt_int ? K[36] : K[14];
assign K13[47] = decrypt_int ? K[42] : K[51];
assign K13[48] = decrypt_int ? K[8] : K[45];
assign K12[1] = decrypt_int ? K[39] : K[48];
assign K12[2] = decrypt_int ? K[3] : K[12];
assign K12[3] = decrypt_int ? K[18] : K[27];
assign K12[4] = decrypt_int ? K[27] : K[4];
assign K12[5] = decrypt_int ? K[5] : K[39];
assign K12[6] = decrypt_int ? K[33] : K[10];
assign K12[7] = decrypt_int ? K[19] : K[53];
assign K12[8] = decrypt_int ? K[55] : K[32];
assign K12[9] = decrypt_int ? K[46] : K[55];
assign K12[10] = decrypt_int ? K[40] : K[17];
assign K12[11] = decrypt_int ? K[6] : K[40];
assign K12[12] = decrypt_int ? K[11] : K[20];
assign K12[13] = decrypt_int ? K[20] : K[54];
assign K12[14] = decrypt_int ? K[17] : K[26];
assign K12[15] = decrypt_int ? K[25] : K[34];
assign K12[16] = decrypt_int ? K[26] : K[3];
assign K12[17] = decrypt_int ? K[41] : K[18];
assign K12[18] = decrypt_int ? K[54] : K[6];
assign K12[19] = decrypt_int ? K[53] : K[5];
assign K12[20] = decrypt_int ? K[47] : K[24];
assign K12[21] = decrypt_int ? K[48] : K[25];
assign K12[22] = decrypt_int ? K[24] : K[33];
assign K12[23] = decrypt_int ? K[32] : K[41];
assign K12[24] = decrypt_int ? K[12] : K[46];
assign K12[25] = decrypt_int ? K[30] : K[35];
assign K12[26] = decrypt_int ? K[21] : K[2];
assign K12[27] = decrypt_int ? K[15] : K[51];
assign K12[28] = decrypt_int ? K[2] : K[7];
assign K12[29] = decrypt_int ? K[45] : K[22];
assign K12[30] = decrypt_int ? K[42] : K[23];
assign K12[31] = decrypt_int ? K[8] : K[44];
assign K12[32] = decrypt_int ? K[23] : K[28];
assign K12[33] = decrypt_int ? K[14] : K[50];
assign K12[34] = decrypt_int ? K[31] : K[8];
assign K12[35] = decrypt_int ? K[29] : K[38];
assign K12[36] = decrypt_int ? K[52] : K[29];
assign K12[37] = decrypt_int ? K[51] : K[1];
assign K12[38] = decrypt_int ? K[0] : K[36];
assign K12[39] = decrypt_int ? K[16] : K[21];
assign K12[40] = decrypt_int ? K[49] : K[30];
assign K12[41] = decrypt_int ? K[36] : K[45];
assign K12[42] = decrypt_int ? K[28] : K[9];
assign K12[43] = decrypt_int ? K[38] : K[15];
assign K12[44] = decrypt_int ? K[37] : K[42];
assign K12[45] = decrypt_int ? K[7] : K[43];
assign K12[46] = decrypt_int ? K[50] : K[0];
assign K12[47] = decrypt_int ? K[1] : K[37];
assign K12[48] = decrypt_int ? K[22] : K[31];
assign K11[1] = decrypt_int ? K[53] : K[34];
assign K11[2] = decrypt_int ? K[17] : K[55];
assign K11[3] = decrypt_int ? K[32] : K[13];
assign K11[4] = decrypt_int ? K[41] : K[47];
assign K11[5] = decrypt_int ? K[19] : K[25];
assign K11[6] = decrypt_int ? K[47] : K[53];
assign K11[7] = decrypt_int ? K[33] : K[39];
assign K11[8] = decrypt_int ? K[12] : K[18];
assign K11[9] = decrypt_int ? K[3] : K[41];
assign K11[10] = decrypt_int ? K[54] : K[3];
assign K11[11] = decrypt_int ? K[20] : K[26];
assign K11[12] = decrypt_int ? K[25] : K[6];
assign K11[13] = decrypt_int ? K[34] : K[40];
assign K11[14] = decrypt_int ? K[6] : K[12];
assign K11[15] = decrypt_int ? K[39] : K[20];
assign K11[16] = decrypt_int ? K[40] : K[46];
assign K11[17] = decrypt_int ? K[55] : K[4];
assign K11[18] = decrypt_int ? K[11] : K[17];
assign K11[19] = decrypt_int ? K[10] : K[48];
assign K11[20] = decrypt_int ? K[4] : K[10];
assign K11[21] = decrypt_int ? K[5] : K[11];
assign K11[22] = decrypt_int ? K[13] : K[19];
assign K11[23] = decrypt_int ? K[46] : K[27];
assign K11[24] = decrypt_int ? K[26] : K[32];
assign K11[25] = decrypt_int ? K[44] : K[21];
assign K11[26] = decrypt_int ? K[35] : K[43];
assign K11[27] = decrypt_int ? K[29] : K[37];
assign K11[28] = decrypt_int ? K[16] : K[52];
assign K11[29] = decrypt_int ? K[0] : K[8];
assign K11[30] = decrypt_int ? K[1] : K[9];
assign K11[31] = decrypt_int ? K[22] : K[30];
assign K11[32] = decrypt_int ? K[37] : K[14];
assign K11[33] = decrypt_int ? K[28] : K[36];
assign K11[34] = decrypt_int ? K[45] : K[49];
assign K11[35] = decrypt_int ? K[43] : K[51];
assign K11[36] = decrypt_int ? K[7] : K[15];
assign K11[37] = decrypt_int ? K[38] : K[42];
assign K11[38] = decrypt_int ? K[14] : K[22];
assign K11[39] = decrypt_int ? K[30] : K[7];
assign K11[40] = decrypt_int ? K[8] : K[16];
assign K11[41] = decrypt_int ? K[50] : K[31];
assign K11[42] = decrypt_int ? K[42] : K[50];
assign K11[43] = decrypt_int ? K[52] : K[1];
assign K11[44] = decrypt_int ? K[51] : K[28];
assign K11[45] = decrypt_int ? K[21] : K[29];
assign K11[46] = decrypt_int ? K[9] : K[45];
assign K11[47] = decrypt_int ? K[15] : K[23];
assign K11[48] = decrypt_int ? K[36] : K[44];
assign K10[1] = decrypt_int ? K[10] : K[20];
assign K10[2] = decrypt_int ? K[6] : K[41];
assign K10[3] = decrypt_int ? K[46] : K[24];
assign K10[4] = decrypt_int ? K[55] : K[33];
assign K10[5] = decrypt_int ? K[33] : K[11];
assign K10[6] = decrypt_int ? K[4] : K[39];
assign K10[7] = decrypt_int ? K[47] : K[25];
assign K10[8] = decrypt_int ? K[26] : K[4];
assign K10[9] = decrypt_int ? K[17] : K[27];
assign K10[10] = decrypt_int ? K[11] : K[46];
assign K10[11] = decrypt_int ? K[34] : K[12];
assign K10[12] = decrypt_int ? K[39] : K[17];
assign K10[13] = decrypt_int ? K[48] : K[26];
assign K10[14] = decrypt_int ? K[20] : K[55];
assign K10[15] = decrypt_int ? K[53] : K[6];
assign K10[16] = decrypt_int ? K[54] : K[32];
assign K10[17] = decrypt_int ? K[12] : K[47];
assign K10[18] = decrypt_int ? K[25] : K[3];
assign K10[19] = decrypt_int ? K[24] : K[34];
assign K10[20] = decrypt_int ? K[18] : K[53];
assign K10[21] = decrypt_int ? K[19] : K[54];
assign K10[22] = decrypt_int ? K[27] : K[5];
assign K10[23] = decrypt_int ? K[3] : K[13];
assign K10[24] = decrypt_int ? K[40] : K[18];
assign K10[25] = decrypt_int ? K[31] : K[7];
assign K10[26] = decrypt_int ? K[49] : K[29];
assign K10[27] = decrypt_int ? K[43] : K[23];
assign K10[28] = decrypt_int ? K[30] : K[38];
assign K10[29] = decrypt_int ? K[14] : K[49];
assign K10[30] = decrypt_int ? K[15] : K[50];
assign K10[31] = decrypt_int ? K[36] : K[16];
assign K10[32] = decrypt_int ? K[51] : K[0];
assign K10[33] = decrypt_int ? K[42] : K[22];
assign K10[34] = decrypt_int ? K[0] : K[35];
assign K10[35] = decrypt_int ? K[2] : K[37];
assign K10[36] = decrypt_int ? K[21] : K[1];
assign K10[37] = decrypt_int ? K[52] : K[28];
assign K10[38] = decrypt_int ? K[28] : K[8];
assign K10[39] = decrypt_int ? K[44] : K[52];
assign K10[40] = decrypt_int ? K[22] : K[2];
assign K10[41] = decrypt_int ? K[9] : K[44];
assign K10[42] = decrypt_int ? K[1] : K[36];
assign K10[43] = decrypt_int ? K[7] : K[42];
assign K10[44] = decrypt_int ? K[38] : K[14];
assign K10[45] = decrypt_int ? K[35] : K[15];
assign K10[46] = decrypt_int ? K[23] : K[31];
assign K10[47] = decrypt_int ? K[29] : K[9];
assign K10[48] = decrypt_int ? K[50] : K[30];
assign K9[1] = decrypt_int ? K[24] : K[6];
assign K9[2] = decrypt_int ? K[20] : K[27];
assign K9[3] = decrypt_int ? K[3] : K[10];
assign K9[4] = decrypt_int ? K[12] : K[19];
assign K9[5] = decrypt_int ? K[47] : K[54];
assign K9[6] = decrypt_int ? K[18] : K[25];
assign K9[7] = decrypt_int ? K[4] : K[11];
assign K9[8] = decrypt_int ? K[40] : K[47];
assign K9[9] = decrypt_int ? K[6] : K[13];
assign K9[10] = decrypt_int ? K[25] : K[32];
assign K9[11] = decrypt_int ? K[48] : K[55];
assign K9[12] = decrypt_int ? K[53] : K[3];
assign K9[13] = decrypt_int ? K[5] : K[12];
assign K9[14] = decrypt_int ? K[34] : K[41];
assign K9[15] = decrypt_int ? K[10] : K[17];
assign K9[16] = decrypt_int ? K[11] : K[18];
assign K9[17] = decrypt_int ? K[26] : K[33];
assign K9[18] = decrypt_int ? K[39] : K[46];
assign K9[19] = decrypt_int ? K[13] : K[20];
assign K9[20] = decrypt_int ? K[32] : K[39];
assign K9[21] = decrypt_int ? K[33] : K[40];
assign K9[22] = decrypt_int ? K[41] : K[48];
assign K9[23] = decrypt_int ? K[17] : K[24];
assign K9[24] = decrypt_int ? K[54] : K[4];
assign K9[25] = decrypt_int ? K[45] : K[52];
assign K9[26] = decrypt_int ? K[8] : K[15];
assign K9[27] = decrypt_int ? K[2] : K[9];
assign K9[28] = decrypt_int ? K[44] : K[51];
assign K9[29] = decrypt_int ? K[28] : K[35];
assign K9[30] = decrypt_int ? K[29] : K[36];
assign K9[31] = decrypt_int ? K[50] : K[2];
assign K9[32] = decrypt_int ? K[38] : K[45];
assign K9[33] = decrypt_int ? K[1] : K[8];
assign K9[34] = decrypt_int ? K[14] : K[21];
assign K9[35] = decrypt_int ? K[16] : K[23];
assign K9[36] = decrypt_int ? K[35] : K[42];
assign K9[37] = decrypt_int ? K[7] : K[14];
assign K9[38] = decrypt_int ? K[42] : K[49];
assign K9[39] = decrypt_int ? K[31] : K[38];
assign K9[40] = decrypt_int ? K[36] : K[43];
assign K9[41] = decrypt_int ? K[23] : K[30];
assign K9[42] = decrypt_int ? K[15] : K[22];
assign K9[43] = decrypt_int ? K[21] : K[28];
assign K9[44] = decrypt_int ? K[52] : K[0];
assign K9[45] = decrypt_int ? K[49] : K[1];
assign K9[46] = decrypt_int ? K[37] : K[44];
assign K9[47] = decrypt_int ? K[43] : K[50];
assign K9[48] = decrypt_int ? K[9] : K[16];
assign K8[1] = decrypt_int ? K[6] : K[24];
assign K8[2] = decrypt_int ? K[27] : K[20];
assign K8[3] = decrypt_int ? K[10] : K[3];
assign K8[4] = decrypt_int ? K[19] : K[12];
assign K8[5] = decrypt_int ? K[54] : K[47];
assign K8[6] = decrypt_int ? K[25] : K[18];
assign K8[7] = decrypt_int ? K[11] : K[4];
assign K8[8] = decrypt_int ? K[47] : K[40];
assign K8[9] = decrypt_int ? K[13] : K[6];
assign K8[10] = decrypt_int ? K[32] : K[25];
assign K8[11] = decrypt_int ? K[55] : K[48];
assign K8[12] = decrypt_int ? K[3] : K[53];
assign K8[13] = decrypt_int ? K[12] : K[5];
assign K8[14] = decrypt_int ? K[41] : K[34];
assign K8[15] = decrypt_int ? K[17] : K[10];
assign K8[16] = decrypt_int ? K[18] : K[11];
assign K8[17] = decrypt_int ? K[33] : K[26];
assign K8[18] = decrypt_int ? K[46] : K[39];
assign K8[19] = decrypt_int ? K[20] : K[13];
assign K8[20] = decrypt_int ? K[39] : K[32];
assign K8[21] = decrypt_int ? K[40] : K[33];
assign K8[22] = decrypt_int ? K[48] : K[41];
assign K8[23] = decrypt_int ? K[24] : K[17];
assign K8[24] = decrypt_int ? K[4] : K[54];
assign K8[25] = decrypt_int ? K[52] : K[45];
assign K8[26] = decrypt_int ? K[15] : K[8];
assign K8[27] = decrypt_int ? K[9] : K[2];
assign K8[28] = decrypt_int ? K[51] : K[44];
assign K8[29] = decrypt_int ? K[35] : K[28];
assign K8[30] = decrypt_int ? K[36] : K[29];
assign K8[31] = decrypt_int ? K[2] : K[50];
assign K8[32] = decrypt_int ? K[45] : K[38];
assign K8[33] = decrypt_int ? K[8] : K[1];
assign K8[34] = decrypt_int ? K[21] : K[14];
assign K8[35] = decrypt_int ? K[23] : K[16];
assign K8[36] = decrypt_int ? K[42] : K[35];
assign K8[37] = decrypt_int ? K[14] : K[7];
assign K8[38] = decrypt_int ? K[49] : K[42];
assign K8[39] = decrypt_int ? K[38] : K[31];
assign K8[40] = decrypt_int ? K[43] : K[36];
assign K8[41] = decrypt_int ? K[30] : K[23];
assign K8[42] = decrypt_int ? K[22] : K[15];
assign K8[43] = decrypt_int ? K[28] : K[21];
assign K8[44] = decrypt_int ? K[0] : K[52];
assign K8[45] = decrypt_int ? K[1] : K[49];
assign K8[46] = decrypt_int ? K[44] : K[37];
assign K8[47] = decrypt_int ? K[50] : K[43];
assign K8[48] = decrypt_int ? K[16] : K[9];
assign K7[1] = decrypt_int ? K[20] : K[10];
assign K7[2] = decrypt_int ? K[41] : K[6];
assign K7[3] = decrypt_int ? K[24] : K[46];
assign K7[4] = decrypt_int ? K[33] : K[55];
assign K7[5] = decrypt_int ? K[11] : K[33];
assign K7[6] = decrypt_int ? K[39] : K[4];
assign K7[7] = decrypt_int ? K[25] : K[47];
assign K7[8] = decrypt_int ? K[4] : K[26];
assign K7[9] = decrypt_int ? K[27] : K[17];
assign K7[10] = decrypt_int ? K[46] : K[11];
assign K7[11] = decrypt_int ? K[12] : K[34];
assign K7[12] = decrypt_int ? K[17] : K[39];
assign K7[13] = decrypt_int ? K[26] : K[48];
assign K7[14] = decrypt_int ? K[55] : K[20];
assign K7[15] = decrypt_int ? K[6] : K[53];
assign K7[16] = decrypt_int ? K[32] : K[54];
assign K7[17] = decrypt_int ? K[47] : K[12];
assign K7[18] = decrypt_int ? K[3] : K[25];
assign K7[19] = decrypt_int ? K[34] : K[24];
assign K7[20] = decrypt_int ? K[53] : K[18];
assign K7[21] = decrypt_int ? K[54] : K[19];
assign K7[22] = decrypt_int ? K[5] : K[27];
assign K7[23] = decrypt_int ? K[13] : K[3];
assign K7[24] = decrypt_int ? K[18] : K[40];
assign K7[25] = decrypt_int ? K[7] : K[31];
assign K7[26] = decrypt_int ? K[29] : K[49];
assign K7[27] = decrypt_int ? K[23] : K[43];
assign K7[28] = decrypt_int ? K[38] : K[30];
assign K7[29] = decrypt_int ? K[49] : K[14];
assign K7[30] = decrypt_int ? K[50] : K[15];
assign K7[31] = decrypt_int ? K[16] : K[36];
assign K7[32] = decrypt_int ? K[0] : K[51];
assign K7[33] = decrypt_int ? K[22] : K[42];
assign K7[34] = decrypt_int ? K[35] : K[0];
assign K7[35] = decrypt_int ? K[37] : K[2];
assign K7[36] = decrypt_int ? K[1] : K[21];
assign K7[37] = decrypt_int ? K[28] : K[52];
assign K7[38] = decrypt_int ? K[8] : K[28];
assign K7[39] = decrypt_int ? K[52] : K[44];
assign K7[40] = decrypt_int ? K[2] : K[22];
assign K7[41] = decrypt_int ? K[44] : K[9];
assign K7[42] = decrypt_int ? K[36] : K[1];
assign K7[43] = decrypt_int ? K[42] : K[7];
assign K7[44] = decrypt_int ? K[14] : K[38];
assign K7[45] = decrypt_int ? K[15] : K[35];
assign K7[46] = decrypt_int ? K[31] : K[23];
assign K7[47] = decrypt_int ? K[9] : K[29];
assign K7[48] = decrypt_int ? K[30] : K[50];
assign K6[1] = decrypt_int ? K[34] : K[53];
assign K6[2] = decrypt_int ? K[55] : K[17];
assign K6[3] = decrypt_int ? K[13] : K[32];
assign K6[4] = decrypt_int ? K[47] : K[41];
assign K6[5] = decrypt_int ? K[25] : K[19];
assign K6[6] = decrypt_int ? K[53] : K[47];
assign K6[7] = decrypt_int ? K[39] : K[33];
assign K6[8] = decrypt_int ? K[18] : K[12];
assign K6[9] = decrypt_int ? K[41] : K[3];
assign K6[10] = decrypt_int ? K[3] : K[54];
assign K6[11] = decrypt_int ? K[26] : K[20];
assign K6[12] = decrypt_int ? K[6] : K[25];
assign K6[13] = decrypt_int ? K[40] : K[34];
assign K6[14] = decrypt_int ? K[12] : K[6];
assign K6[15] = decrypt_int ? K[20] : K[39];
assign K6[16] = decrypt_int ? K[46] : K[40];
assign K6[17] = decrypt_int ? K[4] : K[55];
assign K6[18] = decrypt_int ? K[17] : K[11];
assign K6[19] = decrypt_int ? K[48] : K[10];
assign K6[20] = decrypt_int ? K[10] : K[4];
assign K6[21] = decrypt_int ? K[11] : K[5];
assign K6[22] = decrypt_int ? K[19] : K[13];
assign K6[23] = decrypt_int ? K[27] : K[46];
assign K6[24] = decrypt_int ? K[32] : K[26];
assign K6[25] = decrypt_int ? K[21] : K[44];
assign K6[26] = decrypt_int ? K[43] : K[35];
assign K6[27] = decrypt_int ? K[37] : K[29];
assign K6[28] = decrypt_int ? K[52] : K[16];
assign K6[29] = decrypt_int ? K[8] : K[0];
assign K6[30] = decrypt_int ? K[9] : K[1];
assign K6[31] = decrypt_int ? K[30] : K[22];
assign K6[32] = decrypt_int ? K[14] : K[37];
assign K6[33] = decrypt_int ? K[36] : K[28];
assign K6[34] = decrypt_int ? K[49] : K[45];
assign K6[35] = decrypt_int ? K[51] : K[43];
assign K6[36] = decrypt_int ? K[15] : K[7];
assign K6[37] = decrypt_int ? K[42] : K[38];
assign K6[38] = decrypt_int ? K[22] : K[14];
assign K6[39] = decrypt_int ? K[7] : K[30];
assign K6[40] = decrypt_int ? K[16] : K[8];
assign K6[41] = decrypt_int ? K[31] : K[50];
assign K6[42] = decrypt_int ? K[50] : K[42];
assign K6[43] = decrypt_int ? K[1] : K[52];
assign K6[44] = decrypt_int ? K[28] : K[51];
assign K6[45] = decrypt_int ? K[29] : K[21];
assign K6[46] = decrypt_int ? K[45] : K[9];
assign K6[47] = decrypt_int ? K[23] : K[15];
assign K6[48] = decrypt_int ? K[44] : K[36];
assign K5[1] = decrypt_int ? K[48] : K[39];
assign K5[2] = decrypt_int ? K[12] : K[3];
assign K5[3] = decrypt_int ? K[27] : K[18];
assign K5[4] = decrypt_int ? K[4] : K[27];
assign K5[5] = decrypt_int ? K[39] : K[5];
assign K5[6] = decrypt_int ? K[10] : K[33];
assign K5[7] = decrypt_int ? K[53] : K[19];
assign K5[8] = decrypt_int ? K[32] : K[55];
assign K5[9] = decrypt_int ? K[55] : K[46];
assign K5[10] = decrypt_int ? K[17] : K[40];
assign K5[11] = decrypt_int ? K[40] : K[6];
assign K5[12] = decrypt_int ? K[20] : K[11];
assign K5[13] = decrypt_int ? K[54] : K[20];
assign K5[14] = decrypt_int ? K[26] : K[17];
assign K5[15] = decrypt_int ? K[34] : K[25];
assign K5[16] = decrypt_int ? K[3] : K[26];
assign K5[17] = decrypt_int ? K[18] : K[41];
assign K5[18] = decrypt_int ? K[6] : K[54];
assign K5[19] = decrypt_int ? K[5] : K[53];
assign K5[20] = decrypt_int ? K[24] : K[47];
assign K5[21] = decrypt_int ? K[25] : K[48];
assign K5[22] = decrypt_int ? K[33] : K[24];
assign K5[23] = decrypt_int ? K[41] : K[32];
assign K5[24] = decrypt_int ? K[46] : K[12];
assign K5[25] = decrypt_int ? K[35] : K[30];
assign K5[26] = decrypt_int ? K[2] : K[21];
assign K5[27] = decrypt_int ? K[51] : K[15];
assign K5[28] = decrypt_int ? K[7] : K[2];
assign K5[29] = decrypt_int ? K[22] : K[45];
assign K5[30] = decrypt_int ? K[23] : K[42];
assign K5[31] = decrypt_int ? K[44] : K[8];
assign K5[32] = decrypt_int ? K[28] : K[23];
assign K5[33] = decrypt_int ? K[50] : K[14];
assign K5[34] = decrypt_int ? K[8] : K[31];
assign K5[35] = decrypt_int ? K[38] : K[29];
assign K5[36] = decrypt_int ? K[29] : K[52];
assign K5[37] = decrypt_int ? K[1] : K[51];
assign K5[38] = decrypt_int ? K[36] : K[0];
assign K5[39] = decrypt_int ? K[21] : K[16];
assign K5[40] = decrypt_int ? K[30] : K[49];
assign K5[41] = decrypt_int ? K[45] : K[36];
assign K5[42] = decrypt_int ? K[9] : K[28];
assign K5[43] = decrypt_int ? K[15] : K[38];
assign K5[44] = decrypt_int ? K[42] : K[37];
assign K5[45] = decrypt_int ? K[43] : K[7];
assign K5[46] = decrypt_int ? K[0] : K[50];
assign K5[47] = decrypt_int ? K[37] : K[1];
assign K5[48] = decrypt_int ? K[31] : K[22];
assign K4[1] = decrypt_int ? K[5] : K[25];
assign K4[2] = decrypt_int ? K[26] : K[46];
assign K4[3] = decrypt_int ? K[41] : K[4];
assign K4[4] = decrypt_int ? K[18] : K[13];
assign K4[5] = decrypt_int ? K[53] : K[48];
assign K4[6] = decrypt_int ? K[24] : K[19];
assign K4[7] = decrypt_int ? K[10] : K[5];
assign K4[8] = decrypt_int ? K[46] : K[41];
assign K4[9] = decrypt_int ? K[12] : K[32];
assign K4[10] = decrypt_int ? K[6] : K[26];
assign K4[11] = decrypt_int ? K[54] : K[17];
assign K4[12] = decrypt_int ? K[34] : K[54];
assign K4[13] = decrypt_int ? K[11] : K[6];
assign K4[14] = decrypt_int ? K[40] : K[3];
assign K4[15] = decrypt_int ? K[48] : K[11];
assign K4[16] = decrypt_int ? K[17] : K[12];
assign K4[17] = decrypt_int ? K[32] : K[27];
assign K4[18] = decrypt_int ? K[20] : K[40];
assign K4[19] = decrypt_int ? K[19] : K[39];
assign K4[20] = decrypt_int ? K[13] : K[33];
assign K4[21] = decrypt_int ? K[39] : K[34];
assign K4[22] = decrypt_int ? K[47] : K[10];
assign K4[23] = decrypt_int ? K[55] : K[18];
assign K4[24] = decrypt_int ? K[3] : K[55];
assign K4[25] = decrypt_int ? K[49] : K[16];
assign K4[26] = decrypt_int ? K[16] : K[7];
assign K4[27] = decrypt_int ? K[38] : K[1];
assign K4[28] = decrypt_int ? K[21] : K[43];
assign K4[29] = decrypt_int ? K[36] : K[31];
assign K4[30] = decrypt_int ? K[37] : K[28];
assign K4[31] = decrypt_int ? K[31] : K[49];
assign K4[32] = decrypt_int ? K[42] : K[9];
assign K4[33] = decrypt_int ? K[9] : K[0];
assign K4[34] = decrypt_int ? K[22] : K[44];
assign K4[35] = decrypt_int ? K[52] : K[15];
assign K4[36] = decrypt_int ? K[43] : K[38];
assign K4[37] = decrypt_int ? K[15] : K[37];
assign K4[38] = decrypt_int ? K[50] : K[45];
assign K4[39] = decrypt_int ? K[35] : K[2];
assign K4[40] = decrypt_int ? K[44] : K[35];
assign K4[41] = decrypt_int ? K[0] : K[22];
assign K4[42] = decrypt_int ? K[23] : K[14];
assign K4[43] = decrypt_int ? K[29] : K[51];
assign K4[44] = decrypt_int ? K[1] : K[23];
assign K4[45] = decrypt_int ? K[2] : K[52];
assign K4[46] = decrypt_int ? K[14] : K[36];
assign K4[47] = decrypt_int ? K[51] : K[42];
assign K4[48] = decrypt_int ? K[45] : K[8];
assign K3[1] = decrypt_int ? K[19] : K[11];
assign K3[2] = decrypt_int ? K[40] : K[32];
assign K3[3] = decrypt_int ? K[55] : K[47];
assign K3[4] = decrypt_int ? K[32] : K[24];
assign K3[5] = decrypt_int ? K[10] : K[34];
assign K3[6] = decrypt_int ? K[13] : K[5];
assign K3[7] = decrypt_int ? K[24] : K[48];
assign K3[8] = decrypt_int ? K[3] : K[27];
assign K3[9] = decrypt_int ? K[26] : K[18];
assign K3[10] = decrypt_int ? K[20] : K[12];
assign K3[11] = decrypt_int ? K[11] : K[3];
assign K3[12] = decrypt_int ? K[48] : K[40];
assign K3[13] = decrypt_int ? K[25] : K[17];
assign K3[14] = decrypt_int ? K[54] : K[46];
assign K3[15] = decrypt_int ? K[5] : K[54];
assign K3[16] = decrypt_int ? K[6] : K[55];
assign K3[17] = decrypt_int ? K[46] : K[13];
assign K3[18] = decrypt_int ? K[34] : K[26];
assign K3[19] = decrypt_int ? K[33] : K[25];
assign K3[20] = decrypt_int ? K[27] : K[19];
assign K3[21] = decrypt_int ? K[53] : K[20];
assign K3[22] = decrypt_int ? K[4] : K[53];
assign K3[23] = decrypt_int ? K[12] : K[4];
assign K3[24] = decrypt_int ? K[17] : K[41];
assign K3[25] = decrypt_int ? K[8] : K[2];
assign K3[26] = decrypt_int ? K[30] : K[52];
assign K3[27] = decrypt_int ? K[52] : K[42];
assign K3[28] = decrypt_int ? K[35] : K[29];
assign K3[29] = decrypt_int ? K[50] : K[44];
assign K3[30] = decrypt_int ? K[51] : K[14];
assign K3[31] = decrypt_int ? K[45] : K[35];
assign K3[32] = decrypt_int ? K[1] : K[50];
assign K3[33] = decrypt_int ? K[23] : K[45];
assign K3[34] = decrypt_int ? K[36] : K[30];
assign K3[35] = decrypt_int ? K[7] : K[1];
assign K3[36] = decrypt_int ? K[2] : K[51];
assign K3[37] = decrypt_int ? K[29] : K[23];
assign K3[38] = decrypt_int ? K[9] : K[31];
assign K3[39] = decrypt_int ? K[49] : K[43];
assign K3[40] = decrypt_int ? K[31] : K[21];
assign K3[41] = decrypt_int ? K[14] : K[8];
assign K3[42] = decrypt_int ? K[37] : K[0];
assign K3[43] = decrypt_int ? K[43] : K[37];
assign K3[44] = decrypt_int ? K[15] : K[9];
assign K3[45] = decrypt_int ? K[16] : K[38];
assign K3[46] = decrypt_int ? K[28] : K[22];
assign K3[47] = decrypt_int ? K[38] : K[28];
assign K3[48] = decrypt_int ? K[0] : K[49];
assign K2[1] = decrypt_int ? K[33] : K[54];
assign K2[2] = decrypt_int ? K[54] : K[18];
assign K2[3] = decrypt_int ? K[12] : K[33];
assign K2[4] = decrypt_int ? K[46] : K[10];
assign K2[5] = decrypt_int ? K[24] : K[20];
assign K2[6] = decrypt_int ? K[27] : K[48];
assign K2[7] = decrypt_int ? K[13] : K[34];
assign K2[8] = decrypt_int ? K[17] : K[13];
assign K2[9] = decrypt_int ? K[40] : K[4];
assign K2[10] = decrypt_int ? K[34] : K[55];
assign K2[11] = decrypt_int ? K[25] : K[46];
assign K2[12] = decrypt_int ? K[5] : K[26];
assign K2[13] = decrypt_int ? K[39] : K[3];
assign K2[14] = decrypt_int ? K[11] : K[32];
assign K2[15] = decrypt_int ? K[19] : K[40];
assign K2[16] = decrypt_int ? K[20] : K[41];
assign K2[17] = decrypt_int ? K[3] : K[24];
assign K2[18] = decrypt_int ? K[48] : K[12];
assign K2[19] = decrypt_int ? K[47] : K[11];
assign K2[20] = decrypt_int ? K[41] : K[5];
assign K2[21] = decrypt_int ? K[10] : K[6];
assign K2[22] = decrypt_int ? K[18] : K[39];
assign K2[23] = decrypt_int ? K[26] : K[47];
assign K2[24] = decrypt_int ? K[6] : K[27];
assign K2[25] = decrypt_int ? K[22] : K[43];
assign K2[26] = decrypt_int ? K[44] : K[38];
assign K2[27] = decrypt_int ? K[7] : K[28];
assign K2[28] = decrypt_int ? K[49] : K[15];
assign K2[29] = decrypt_int ? K[9] : K[30];
assign K2[30] = decrypt_int ? K[38] : K[0];
assign K2[31] = decrypt_int ? K[0] : K[21];
assign K2[32] = decrypt_int ? K[15] : K[36];
assign K2[33] = decrypt_int ? K[37] : K[31];
assign K2[34] = decrypt_int ? K[50] : K[16];
assign K2[35] = decrypt_int ? K[21] : K[42];
assign K2[36] = decrypt_int ? K[16] : K[37];
assign K2[37] = decrypt_int ? K[43] : K[9];
assign K2[38] = decrypt_int ? K[23] : K[44];
assign K2[39] = decrypt_int ? K[8] : K[29];
assign K2[40] = decrypt_int ? K[45] : K[7];
assign K2[41] = decrypt_int ? K[28] : K[49];
assign K2[42] = decrypt_int ? K[51] : K[45];
assign K2[43] = decrypt_int ? K[2] : K[23];
assign K2[44] = decrypt_int ? K[29] : K[50];
assign K2[45] = decrypt_int ? K[30] : K[51];
assign K2[46] = decrypt_int ? K[42] : K[8];
assign K2[47] = decrypt_int ? K[52] : K[14];
assign K2[48] = decrypt_int ? K[14] : K[35];
assign K1[1] = decrypt_int ? K[40] : K[47];
assign K1[2] = decrypt_int ? K[4] : K[11];
assign K1[3] = decrypt_int ? K[19] : K[26];
assign K1[4] = decrypt_int ? K[53] : K[3];
assign K1[5] = decrypt_int ? K[6] : K[13];
assign K1[6] = decrypt_int ? K[34] : K[41];
assign K1[7] = decrypt_int ? K[20] : K[27];
assign K1[8] = decrypt_int ? K[24] : K[6];
assign K1[9] = decrypt_int ? K[47] : K[54];
assign K1[10] = decrypt_int ? K[41] : K[48];
assign K1[11] = decrypt_int ? K[32] : K[39];
assign K1[12] = decrypt_int ? K[12] : K[19];
assign K1[13] = decrypt_int ? K[46] : K[53];
assign K1[14] = decrypt_int ? K[18] : K[25];
assign K1[15] = decrypt_int ? K[26] : K[33];
assign K1[16] = decrypt_int ? K[27] : K[34];
assign K1[17] = decrypt_int ? K[10] : K[17];
assign K1[18] = decrypt_int ? K[55] : K[5];
assign K1[19] = decrypt_int ? K[54] : K[4];
assign K1[20] = decrypt_int ? K[48] : K[55];
assign K1[21] = decrypt_int ? K[17] : K[24];
assign K1[22] = decrypt_int ? K[25] : K[32];
assign K1[23] = decrypt_int ? K[33] : K[40];
assign K1[24] = decrypt_int ? K[13] : K[20];
assign K1[25] = decrypt_int ? K[29] : K[36];
assign K1[26] = decrypt_int ? K[51] : K[31];
assign K1[27] = decrypt_int ? K[14] : K[21];
assign K1[28] = decrypt_int ? K[1] : K[8];
assign K1[29] = decrypt_int ? K[16] : K[23];
assign K1[30] = decrypt_int ? K[45] : K[52];
assign K1[31] = decrypt_int ? K[7] : K[14];
assign K1[32] = decrypt_int ? K[22] : K[29];
assign K1[33] = decrypt_int ? K[44] : K[51];
assign K1[34] = decrypt_int ? K[2] : K[9];
assign K1[35] = decrypt_int ? K[28] : K[35];
assign K1[36] = decrypt_int ? K[23] : K[30];
assign K1[37] = decrypt_int ? K[50] : K[2];
assign K1[38] = decrypt_int ? K[30] : K[37];
assign K1[39] = decrypt_int ? K[15] : K[22];
assign K1[40] = decrypt_int ? K[52] : K[0];
assign K1[41] = decrypt_int ? K[35] : K[42];
assign K1[42] = decrypt_int ? K[31] : K[38];
assign K1[43] = decrypt_int ? K[9] : K[16];
assign K1[44] = decrypt_int ? K[36] : K[43];
assign K1[45] = decrypt_int ? K[37] : K[44];
assign K1[46] = decrypt_int ? K[49] : K[1];
assign K1[47] = decrypt_int ? K[0] : K[7];
assign K1[48] = decrypt_int ? K[21] : K[28];
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module sbox1(addr, dout);
/* verilator lint_off LITENDIAN */
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
/* verilator lint_on LITENDIAN */
always @(addr)
begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0:
dout = 14;
1:
dout = 4;
2:
dout = 13;
3:
dout = 1;
4:
dout = 2;
5:
dout = 15;
6:
dout = 11;
7:
dout = 8;
8:
dout = 3;
9:
dout = 10;
10:
dout = 6;
11:
dout = 12;
12:
dout = 5;
13:
dout = 9;
14:
dout = 0;
15:
dout = 7;
16:
dout = 0;
17:
dout = 15;
18:
dout = 7;
19:
dout = 4;
20:
dout = 14;
21:
dout = 2;
22:
dout = 13;
23:
dout = 1;
24:
dout = 10;
25:
dout = 6;
26:
dout = 12;
27:
dout = 11;
28:
dout = 9;
29:
dout = 5;
30:
dout = 3;
31:
dout = 8;
32:
dout = 4;
33:
dout = 1;
34:
dout = 14;
35:
dout = 8;
36:
dout = 13;
37:
dout = 6;
38:
dout = 2;
39:
dout = 11;
40:
dout = 15;
41:
dout = 12;
42:
dout = 9;
43:
dout = 7;
44:
dout = 3;
45:
dout = 10;
46:
dout = 5;
47:
dout = 0;
48:
dout = 15;
49:
dout = 12;
50:
dout = 8;
51:
dout = 2;
52:
dout = 4;
53:
dout = 9;
54:
dout = 1;
55:
dout = 7;
56:
dout = 5;
57:
dout = 11;
58:
dout = 3;
59:
dout = 14;
60:
dout = 10;
61:
dout = 0;
62:
dout = 6;
63:
dout = 13;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module sbox2(addr, dout);
/* verilator lint_off LITENDIAN */
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
/* verilator lint_on LITENDIAN */
always @(addr)
begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0:
dout = 15;
1:
dout = 1;
2:
dout = 8;
3:
dout = 14;
4:
dout = 6;
5:
dout = 11;
6:
dout = 3;
7:
dout = 4;
8:
dout = 9;
9:
dout = 7;
10:
dout = 2;
11:
dout = 13;
12:
dout = 12;
13:
dout = 0;
14:
dout = 5;
15:
dout = 10;
16:
dout = 3;
17:
dout = 13;
18:
dout = 4;
19:
dout = 7;
20:
dout = 15;
21:
dout = 2;
22:
dout = 8;
23:
dout = 14;
24:
dout = 12;
25:
dout = 0;
26:
dout = 1;
27:
dout = 10;
28:
dout = 6;
29:
dout = 9;
30:
dout = 11;
31:
dout = 5;
32:
dout = 0;
33:
dout = 14;
34:
dout = 7;
35:
dout = 11;
36:
dout = 10;
37:
dout = 4;
38:
dout = 13;
39:
dout = 1;
40:
dout = 5;
41:
dout = 8;
42:
dout = 12;
43:
dout = 6;
44:
dout = 9;
45:
dout = 3;
46:
dout = 2;
47:
dout = 15;
48:
dout = 13;
49:
dout = 8;
50:
dout = 10;
51:
dout = 1;
52:
dout = 3;
53:
dout = 15;
54:
dout = 4;
55:
dout = 2;
56:
dout = 11;
57:
dout = 6;
58:
dout = 7;
59:
dout = 12;
60:
dout = 0;
61:
dout = 5;
62:
dout = 14;
63:
dout = 9;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module sbox3(addr, dout);
/* verilator lint_off LITENDIAN */
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
/* verilator lint_on LITENDIAN */
always @(addr)
begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0:
dout = 10;
1:
dout = 0;
2:
dout = 9;
3:
dout = 14;
4:
dout = 6;
5:
dout = 3;
6:
dout = 15;
7:
dout = 5;
8:
dout = 1;
9:
dout = 13;
10:
dout = 12;
11:
dout = 7;
12:
dout = 11;
13:
dout = 4;
14:
dout = 2;
15:
dout = 8;
16:
dout = 13;
17:
dout = 7;
18:
dout = 0;
19:
dout = 9;
20:
dout = 3;
21:
dout = 4;
22:
dout = 6;
23:
dout = 10;
24:
dout = 2;
25:
dout = 8;
26:
dout = 5;
27:
dout = 14;
28:
dout = 12;
29:
dout = 11;
30:
dout = 15;
31:
dout = 1;
32:
dout = 13;
33:
dout = 6;
34:
dout = 4;
35:
dout = 9;
36:
dout = 8;
37:
dout = 15;
38:
dout = 3;
39:
dout = 0;
40:
dout = 11;
41:
dout = 1;
42:
dout = 2;
43:
dout = 12;
44:
dout = 5;
45:
dout = 10;
46:
dout = 14;
47:
dout = 7;
48:
dout = 1;
49:
dout = 10;
50:
dout = 13;
51:
dout = 0;
52:
dout = 6;
53:
dout = 9;
54:
dout = 8;
55:
dout = 7;
56:
dout = 4;
57:
dout = 15;
58:
dout = 14;
59:
dout = 3;
60:
dout = 11;
61:
dout = 5;
62:
dout = 2;
63:
dout = 12;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module sbox4(addr, dout);
/* verilator lint_off LITENDIAN */
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
/* verilator lint_on LITENDIAN */
always @(addr)
begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0:
dout = 7;
1:
dout = 13;
2:
dout = 14;
3:
dout = 3;
4:
dout = 0;
5:
dout = 6;
6:
dout = 9;
7:
dout = 10;
8:
dout = 1;
9:
dout = 2;
10:
dout = 8;
11:
dout = 5;
12:
dout = 11;
13:
dout = 12;
14:
dout = 4;
15:
dout = 15;
16:
dout = 13;
17:
dout = 8;
18:
dout = 11;
19:
dout = 5;
20:
dout = 6;
21:
dout = 15;
22:
dout = 0;
23:
dout = 3;
24:
dout = 4;
25:
dout = 7;
26:
dout = 2;
27:
dout = 12;
28:
dout = 1;
29:
dout = 10;
30:
dout = 14;
31:
dout = 9;
32:
dout = 10;
33:
dout = 6;
34:
dout = 9;
35:
dout = 0;
36:
dout = 12;
37:
dout = 11;
38:
dout = 7;
39:
dout = 13;
40:
dout = 15;
41:
dout = 1;
42:
dout = 3;
43:
dout = 14;
44:
dout = 5;
45:
dout = 2;
46:
dout = 8;
47:
dout = 4;
48:
dout = 3;
49:
dout = 15;
50:
dout = 0;
51:
dout = 6;
52:
dout = 10;
53:
dout = 1;
54:
dout = 13;
55:
dout = 8;
56:
dout = 9;
57:
dout = 4;
58:
dout = 5;
59:
dout = 11;
60:
dout = 12;
61:
dout = 7;
62:
dout = 2;
63:
dout = 14;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module sbox5(addr, dout);
/* verilator lint_off LITENDIAN */
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
/* verilator lint_on LITENDIAN */
always @(addr)
begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0:
dout = 2;
1:
dout = 12;
2:
dout = 4;
3:
dout = 1;
4:
dout = 7;
5:
dout = 10;
6:
dout = 11;
7:
dout = 6;
8:
dout = 8;
9:
dout = 5;
10:
dout = 3;
11:
dout = 15;
12:
dout = 13;
13:
dout = 0;
14:
dout = 14;
15:
dout = 9;
16:
dout = 14;
17:
dout = 11;
18:
dout = 2;
19:
dout = 12;
20:
dout = 4;
21:
dout = 7;
22:
dout = 13;
23:
dout = 1;
24:
dout = 5;
25:
dout = 0;
26:
dout = 15;
27:
dout = 10;
28:
dout = 3;
29:
dout = 9;
30:
dout = 8;
31:
dout = 6;
32:
dout = 4;
33:
dout = 2;
34:
dout = 1;
35:
dout = 11;
36:
dout = 10;
37:
dout = 13;
38:
dout = 7;
39:
dout = 8;
40:
dout = 15;
41:
dout = 9;
42:
dout = 12;
43:
dout = 5;
44:
dout = 6;
45:
dout = 3;
46:
dout = 0;
47:
dout = 14;
48:
dout = 11;
49:
dout = 8;
50:
dout = 12;
51:
dout = 7;
52:
dout = 1;
53:
dout = 14;
54:
dout = 2;
55:
dout = 13;
56:
dout = 6;
57:
dout = 15;
58:
dout = 0;
59:
dout = 9;
60:
dout = 10;
61:
dout = 4;
62:
dout = 5;
63:
dout = 3;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module sbox6(addr, dout);
/* verilator lint_off LITENDIAN */
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
/* verilator lint_on LITENDIAN */
always @(addr)
begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0:
dout = 12;
1:
dout = 1;
2:
dout = 10;
3:
dout = 15;
4:
dout = 9;
5:
dout = 2;
6:
dout = 6;
7:
dout = 8;
8:
dout = 0;
9:
dout = 13;
10:
dout = 3;
11:
dout = 4;
12:
dout = 14;
13:
dout = 7;
14:
dout = 5;
15:
dout = 11;
16:
dout = 10;
17:
dout = 15;
18:
dout = 4;
19:
dout = 2;
20:
dout = 7;
21:
dout = 12;
22:
dout = 9;
23:
dout = 5;
24:
dout = 6;
25:
dout = 1;
26:
dout = 13;
27:
dout = 14;
28:
dout = 0;
29:
dout = 11;
30:
dout = 3;
31:
dout = 8;
32:
dout = 9;
33:
dout = 14;
34:
dout = 15;
35:
dout = 5;
36:
dout = 2;
37:
dout = 8;
38:
dout = 12;
39:
dout = 3;
40:
dout = 7;
41:
dout = 0;
42:
dout = 4;
43:
dout = 10;
44:
dout = 1;
45:
dout = 13;
46:
dout = 11;
47:
dout = 6;
48:
dout = 4;
49:
dout = 3;
50:
dout = 2;
51:
dout = 12;
52:
dout = 9;
53:
dout = 5;
54:
dout = 15;
55:
dout = 10;
56:
dout = 11;
57:
dout = 14;
58:
dout = 1;
59:
dout = 7;
60:
dout = 6;
61:
dout = 0;
62:
dout = 8;
63:
dout = 13;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module sbox7(addr, dout);
/* verilator lint_off LITENDIAN */
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
/* verilator lint_on LITENDIAN */
always @(addr)
begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0:
dout = 4;
1:
dout = 11;
2:
dout = 2;
3:
dout = 14;
4:
dout = 15;
5:
dout = 0;
6:
dout = 8;
7:
dout = 13;
8:
dout = 3;
9:
dout = 12;
10:
dout = 9;
11:
dout = 7;
12:
dout = 5;
13:
dout = 10;
14:
dout = 6;
15:
dout = 1;
16:
dout = 13;
17:
dout = 0;
18:
dout = 11;
19:
dout = 7;
20:
dout = 4;
21:
dout = 9;
22:
dout = 1;
23:
dout = 10;
24:
dout = 14;
25:
dout = 3;
26:
dout = 5;
27:
dout = 12;
28:
dout = 2;
29:
dout = 15;
30:
dout = 8;
31:
dout = 6;
32:
dout = 1;
33:
dout = 4;
34:
dout = 11;
35:
dout = 13;
36:
dout = 12;
37:
dout = 3;
38:
dout = 7;
39:
dout = 14;
40:
dout = 10;
41:
dout = 15;
42:
dout = 6;
43:
dout = 8;
44:
dout = 0;
45:
dout = 5;
46:
dout = 9;
47:
dout = 2;
48:
dout = 6;
49:
dout = 11;
50:
dout = 13;
51:
dout = 8;
52:
dout = 1;
53:
dout = 4;
54:
dout = 10;
55:
dout = 7;
56:
dout = 9;
57:
dout = 5;
58:
dout = 0;
59:
dout = 15;
60:
dout = 14;
61:
dout = 2;
62:
dout = 3;
63:
dout = 12;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SBOX ////
//// The SBOX is essentially a 64x4 ROM ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
module sbox8(addr, dout);
/* verilator lint_off LITENDIAN */
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
/* verilator lint_on LITENDIAN */
always @(addr)
begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0:
dout = 13;
1:
dout = 2;
2:
dout = 8;
3:
dout = 4;
4:
dout = 6;
5:
dout = 15;
6:
dout = 11;
7:
dout = 1;
8:
dout = 10;
9:
dout = 9;
10:
dout = 3;
11:
dout = 14;
12:
dout = 5;
13:
dout = 0;
14:
dout = 12;
15:
dout = 7;
16:
dout = 1;
17:
dout = 15;
18:
dout = 13;
19:
dout = 8;
20:
dout = 10;
21:
dout = 3;
22:
dout = 7;
23:
dout = 4;
24:
dout = 12;
25:
dout = 5;
26:
dout = 6;
27:
dout = 11;
28:
dout = 0;
29:
dout = 14;
30:
dout = 9;
31:
dout = 2;
32:
dout = 7;
33:
dout = 11;
34:
dout = 4;
35:
dout = 1;
36:
dout = 9;
37:
dout = 12;
38:
dout = 14;
39:
dout = 2;
40:
dout = 0;
41:
dout = 6;
42:
dout = 10;
43:
dout = 13;
44:
dout = 15;
45:
dout = 3;
46:
dout = 5;
47:
dout = 8;
48:
dout = 2;
49:
dout = 1;
50:
dout = 14;
51:
dout = 7;
52:
dout = 4;
53:
dout = 10;
54:
dout = 8;
55:
dout = 13;
56:
dout = 15;
57:
dout = 12;
58:
dout = 9;
59:
dout = 0;
60:
dout = 3;
61:
dout = 5;
62:
dout = 6;
63:
dout = 11;
endcase
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Defines of the Core ////
//// ////
//// Known problems (limits): ////
//// None ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - gorban@opencores.org ////
//// - Jacob Gorban ////
//// - Igor Mohor (igorm@opencores.org) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Timescale define
`timescale 1ns/10ps
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : md5_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-MD5 core
//
module md5_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg startHash, startHash_r;
reg [31:0] data [15:0];
reg message_reset, message_reset_r;
wire [511:0] bigData = {data[0], data[1], data[2], data[3], data[4], data[5], data[6], data[7], data[8], data[9], data[10], data[11], data[12], data[13], data[14], data[15]};
wire [127:0] hash;
wire ready;
wire hashValid;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i)
begin
if(wb_rst_i)
begin
startHash <= 0;
startHash_r <= 0;
message_reset <= 0;
message_reset_r <= 0;
data[0] <= 0;
data[1] <= 0;
data[2] <= 0;
data[3] <= 0;
data[4] <= 0;
data[5] <= 0;
data[6] <= 0;
data[7] <= 0;
data[8] <= 0;
data[9] <= 0;
data[10] <= 0;
data[11] <= 0;
data[12] <= 0;
data[13] <= 0;
data[14] <= 0;
data[15] <= 0;
end
else begin
// Generate a registered versions of startHash and message_reset
startHash_r <= startHash;
message_reset_r <= message_reset;
// Perform a write
if(wb_stb_i & wb_we_i) begin
case(wb_adr_i[6:2])
0: startHash <= wb_dat_i[0];
1: data[15] <= wb_dat_i;
2: data[14] <= wb_dat_i;
3: data[13] <= wb_dat_i;
4: data[12] <= wb_dat_i;
5: data[11] <= wb_dat_i;
6: data[10] <= wb_dat_i;
7: data[9] <= wb_dat_i;
8: data[8] <= wb_dat_i;
9: data[7] <= wb_dat_i;
10: data[6] <= wb_dat_i;
11: data[5] <= wb_dat_i;
12: data[4] <= wb_dat_i;
13: data[3] <= wb_dat_i;
14: data[2] <= wb_dat_i;
15: data[1] <= wb_dat_i;
16: data[0] <= wb_dat_i;
22: message_reset <= wb_dat_i[0];
default:
;
endcase
end else begin // if(wb_stb_i & wb_we_i)
startHash <= 1'b0;
message_reset <= 1'b0;
end // end else
end // else
end // end always
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[6:2])
0: wb_dat_o = {31'b0, ready};
1: wb_dat_o = data[15];
2: wb_dat_o = data[14];
3: wb_dat_o = data[13];
4: wb_dat_o = data[12];
5: wb_dat_o = data[11];
6: wb_dat_o = data[10];
7: wb_dat_o = data[9];
8: wb_dat_o = data[8];
9: wb_dat_o = data[7];
10: wb_dat_o = data[6];
11: wb_dat_o = data[5];
12: wb_dat_o = data[4];
13: wb_dat_o = data[3];
14: wb_dat_o = data[2];
15: wb_dat_o = data[1];
16: wb_dat_o = data[0];
17: wb_dat_o = {31'b0, hashValid};
21: wb_dat_o = hash[127:96];
20: wb_dat_o = hash[95:64];
19: wb_dat_o = hash[63:32];
18: wb_dat_o = hash[31:0];
default:
wb_dat_o = 32'b0;
endcase
end
pancham pancham(
.clk(wb_clk_i),
.rst(wb_rst_i | (message_reset & ~message_reset_r)),
.msg_padded(bigData),
.msg_in_valid(startHash && ~startHash_r),
.msg_output(hash),
.msg_out_valid(hashValid),
.ready(ready)
);
endmodule
|
/*****************************************************************
Pancham is an MD5 compliant IP core for cryptographic
applications.
Copyright (C) 2003 Swapnajit Mittra, Project VeriPage
(Contact email: verilog_tutorial at hotmail.com
Website : http://www.angelfire.com/ca/verilog)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the
Free Software Foundation, Inc.
59 Temple Place, Suite 330
Boston, MA 02111-1307
USA
******************************************************************/
/*
* This is the main module that computes a 128-bit message
* digest from a maximum of 512-bit long input message using
* MD5 algorithm.
*
* Modified by Matthew Hicks (mdhicks@gmail.com)
* Input from 128-bit to 512-bit
* Hold valid outputs
* Carry over constants between encryptions
* Support for arbitrary size encryption
* Address some Verilator warnings
* Convert vector direction
*
*/
// ROUNDs
`define ROUND1 2'b00
`define ROUND2 2'b01
`define ROUND3 2'b10
`define ROUND4 2'b11
// T_i = 4294967296*abs(sin(i))
`define T_1 32'hd76aa478
`define T_2 32'he8c7b756
`define T_3 32'h242070db
`define T_4 32'hc1bdceee
`define T_5 32'hf57c0faf
`define T_6 32'h4787c62a
`define T_7 32'ha8304613
`define T_8 32'hfd469501
`define T_9 32'h698098d8
`define T_10 32'h8b44f7af
`define T_11 32'hffff5bb1
`define T_12 32'h895cd7be
`define T_13 32'h6b901122
`define T_14 32'hfd987193
`define T_15 32'ha679438e
`define T_16 32'h49b40821
`define T_17 32'hf61e2562
`define T_18 32'hc040b340
`define T_19 32'h265e5a51
`define T_20 32'he9b6c7aa
`define T_21 32'hd62f105d
`define T_22 32'h2441453
`define T_23 32'hd8a1e681
`define T_24 32'he7d3fbc8
`define T_25 32'h21e1cde6
`define T_26 32'hc33707d6
`define T_27 32'hf4d50d87
`define T_28 32'h455a14ed
`define T_29 32'ha9e3e905
`define T_30 32'hfcefa3f8
`define T_31 32'h676f02d9
`define T_32 32'h8d2a4c8a
`define T_33 32'hfffa3942
`define T_34 32'h8771f681
`define T_35 32'h6d9d6122
`define T_36 32'hfde5380c
`define T_37 32'ha4beea44
`define T_38 32'h4bdecfa9
`define T_39 32'hf6bb4b60
`define T_40 32'hbebfbc70
`define T_41 32'h289b7ec6
`define T_42 32'heaa127fa
`define T_43 32'hd4ef3085
`define T_44 32'h4881d05
`define T_45 32'hd9d4d039
`define T_46 32'he6db99e5
`define T_47 32'h1fa27cf8
`define T_48 32'hc4ac5665
`define T_49 32'hf4292244
`define T_50 32'h432aff97
`define T_51 32'hab9423a7
`define T_52 32'hfc93a039
`define T_53 32'h655b59c3
`define T_54 32'h8f0ccc92
`define T_55 32'hffeff47d
`define T_56 32'h85845dd1
`define T_57 32'h6fa87e4f
`define T_58 32'hfe2ce6e0
`define T_59 32'ha3014314
`define T_60 32'h4e0811a1
`define T_61 32'hf7537e82
`define T_62 32'hbd3af235
`define T_63 32'h2ad7d2bb
`define T_64 32'heb86d391
/* verilator lint_off UNOPTFLAT */
module pancham (
clk
, rst
, msg_padded
, msg_in_valid
, msg_output
, msg_out_valid
, ready
);
//--------------------------------
//
// Input/Output declarations
//
//--------------------------------
input clk; // input clock
input rst; // global rst
input [511:0] msg_padded; // input message, already padded
input msg_in_valid; // input message is valid, active high
output [127:0] msg_output; // output message, always 128 bit wide
output msg_out_valid; // if asserted, output message is valid
output ready; // the core is ready for an input message
//--------------------------------
//
// Variable declarations
//
//--------------------------------
// inputs
wire clk;
wire rst;
wire [511:0] msg_padded;
wire msg_in_valid;
// output
wire [127:0] msg_output;
reg msg_out_valid;
wire ready;
// scratch pads
reg [1:0] round;
reg [31:0] a;
reg [31:0] A;
reg [31:0] AA;
reg [31:0] next_A;
reg [31:0] b;
reg [31:0] B;
reg [31:0] BB;
reg [31:0] next_B;
reg [31:0] c;
reg [31:0] C;
reg [31:0] CC;
reg [31:0] next_C;
reg [31:0] d;
reg [31:0] D;
reg [31:0] DD;
reg [31:0] next_D;
reg [31:0] m;
reg [31:0] s;
reg [31:0] t;
reg [3:0] phase; // Counter to determine 16 phases within each round.
wire [31:0] next_a;
reg [7:0] current_state;
reg [7:0] next_state;
reg [8*11:1] ascii_state;
//--------------------------------
//
// Parameter definitions
//
//--------------------------------
parameter SALT_A = 32'h67452301;
parameter SALT_B = 32'hefcdab89;
parameter SALT_C = 32'h98badcfe;
parameter SALT_D = 32'h10325476;
parameter ONE = 72'h1;
parameter IDLE_BIT = 0;
parameter IDLE = ONE << IDLE_BIT;
parameter ROUND1_BIT = 1;
parameter ROUND1 = ONE << ROUND1_BIT;
parameter ROUND2_BIT = 2;
parameter ROUND2 = ONE << ROUND2_BIT;
parameter ROUND3_BIT = 3;
parameter ROUND3 = ONE << ROUND3_BIT;
parameter ROUND4_BIT = 4;
parameter ROUND4 = ONE << ROUND4_BIT;
parameter FINISH_OFF_BIT = 5;
parameter FINISH_OFF = ONE << FINISH_OFF_BIT;
parameter TURN_ARND_BIT = 6;
parameter TURN_ARND = ONE << TURN_ARND_BIT;
//--------------------------------
//
// Submodule instantiation
//
//--------------------------------
pancham_round ROUND (
.a (a )
, .b (b )
, .c (c )
, .d (d )
, .m (m )
, .s (s )
, .t (t )
, .round (round)
, .next_a (next_a)
);
wire [31:0] m0 = msg_padded[31:0];
wire [31:0] m1 = msg_padded[63:32];
wire [31:0] m2 = msg_padded[95:64];
wire [31:0] m3 = msg_padded[127:96];
wire [31:0] m4 = msg_padded[159:128];
wire [31:0] m5 = msg_padded[191:160];
wire [31:0] m6 = msg_padded[223:192];
wire [31:0] m7 = msg_padded[255:224];
wire [31:0] m8 = msg_padded[287:256];
wire [31:0] m9 = msg_padded[319:288];
wire [31:0] m10 = msg_padded[351:320];
wire [31:0] m11 = msg_padded[383:352];
wire [31:0] m12 = msg_padded[415:384];
wire [31:0] m13 = msg_padded[447:416];
wire [31:0] m14 = msg_padded[479:448];
wire [31:0] m15 = msg_padded[511:480];
//--------------------------------
//
// Actual code starts here
//
//--------------------------------
always @(current_state
or msg_in_valid
or A
or B
or C
or D
or phase
or msg_padded
or next_a
or AA
or BB
or CC
or DD
)
begin // {
round = `ROUND1;
next_A = A;
next_B = B;
next_C = C;
next_D = D;
a = 32'h0;
b = 32'h0;
c = 32'h0;
d = 32'h0;
m = 32'h0;
s = 32'h0;
t = 32'h0;
next_state = current_state;
case (1'b1) // synopsys full_case parallel_case
current_state[IDLE_BIT]:
begin // {
// synopsys translate_off
ascii_state = "IDLE";
// synopsys translate_on
if (msg_in_valid)
next_state = ROUND1[7:0];
end // }
//----------------------------------------------------------------
//--------------------------- ROUND 1 ----------------------------
//----------------------------------------------------------------
current_state[ROUND1_BIT]:
begin // {
// synopsys translate_off
ascii_state = "ROUND1";
// synopsys translate_on
round = `ROUND1;
case (phase)
4'b0000:
begin
a=A;
b=B;
c=C;
d=D;
m=m0;
s=32'd07;
t= `T_1;
next_A=next_a;
end
4'b0001:
begin
a=D;
b=A;
c=B;
d=C;
m=m1;
s=32'd12;
t= `T_2;
next_D=next_a;
end
4'b0010:
begin
a=C;
b=D;
c=A;
d=B;
m=m2;
s=32'd17;
t= `T_3;
next_C=next_a;
end
4'b0011:
begin
a=B;
b=C;
c=D;
d=A;
m=m3;
s=32'd22;
t= `T_4;
next_B=next_a;
end
4'b0100:
begin
a=A;
b=B;
c=C;
d=D;
m=m4;
s=32'd07;
t= `T_5;
next_A=next_a;
end
4'b0101:
begin
a=D;
b=A;
c=B;
d=C;
m=m5;
s=32'd12;
t= `T_6;
next_D=next_a;
end
4'b0110:
begin
a=C;
b=D;
c=A;
d=B;
m=m6;
s=32'd17;
t= `T_7;
next_C=next_a;
end
4'b0111:
begin
a=B;
b=C;
c=D;
d=A;
m=m7;
s=32'd22;
t= `T_8;
next_B=next_a;
end
4'b1000:
begin
a=A;
b=B;
c=C;
d=D;
m=m8;
s=32'd07;
t= `T_9;
next_A=next_a;
end
4'b1001:
begin
a=D;
b=A;
c=B;
d=C;
m=m9;
s=32'd12;
t=`T_10;
next_D=next_a;
end
4'b1010:
begin
a=C;
b=D;
c=A;
d=B;
m=m10;
s=32'd17;
t=`T_11;
next_C=next_a;
end
4'b1011:
begin
a=B;
b=C;
c=D;
d=A;
m=m11;
s=32'd22;
t=`T_12;
next_B=next_a;
end
4'b1100:
begin
a=A;
b=B;
c=C;
d=D;
m=m12;
s=32'd7;
t=`T_13;
next_A=next_a;
end
4'b1101:
begin
a=D;
b=A;
c=B;
d=C;
m=m13;
s=32'd12;
t=`T_14;
next_D=next_a;
end
4'b1110:
begin
a=C;
b=D;
c=A;
d=B;
m=m14;
s=32'd17;
t=`T_15;
next_C=next_a;
end
4'b1111:
begin
a=B;
b=C;
c=D;
d=A;
m=m15;
s=32'd22;
t=`T_16;
next_B=next_a;
end
endcase
if (phase == 4'b1111)
next_state = ROUND2[7:0];
end // }
//----------------------------------------------------------------
//--------------------------- ROUND 2 ----------------------------
//----------------------------------------------------------------
current_state[ROUND2_BIT]:
begin // {
// synopsys translate_off
ascii_state = "ROUND2";
// synopsys translate_on
round = `ROUND2;
case (phase)
4'b0000:
begin
a=A;
b=B;
c=C;
d=D;
m=m1;
s=32'd05;
t=`T_17;
next_A=next_a;
end
4'b0001:
begin
a=D;
b=A;
c=B;
d=C;
m=m6;
s=32'd09;
t=`T_18;
next_D=next_a;
end
4'b0010:
begin
a=C;
b=D;
c=A;
d=B;
m=m11;
s=32'd14;
t=`T_19;
next_C=next_a;
end
4'b0011:
begin
a=B;
b=C;
c=D;
d=A;
m=m0;
s=32'd20;
t=`T_20;
next_B=next_a;
end
4'b0100:
begin
a=A;
b=B;
c=C;
d=D;
m=m5;
s=32'd05;
t=`T_21;
next_A=next_a;
end
4'b0101:
begin
a=D;
b=A;
c=B;
d=C;
m=m10;
s=32'd09;
t=`T_22;
next_D=next_a;
end
4'b0110:
begin
a=C;
b=D;
c=A;
d=B;
m=m15;
s=32'd14;
t=`T_23;
next_C=next_a;
end
4'b0111:
begin
a=B;
b=C;
c=D;
d=A;
m=m4;
s=32'd20;
t=`T_24;
next_B=next_a;
end
4'b1000:
begin
a=A;
b=B;
c=C;
d=D;
m=m9;
s=32'd05;
t=`T_25;
next_A=next_a;
end
4'b1001:
begin
a=D;
b=A;
c=B;
d=C;
m=m14;
s=32'd9;
t=`T_26;
next_D=next_a;
end
4'b1010:
begin
a=C;
b=D;
c=A;
d=B;
m=m3;
s=32'd14;
t=`T_27;
next_C=next_a;
end
4'b1011:
begin
a=B;
b=C;
c=D;
d=A;
m=m8;
s=32'd20;
t=`T_28;
next_B=next_a;
end
4'b1100:
begin
a=A;
b=B;
c=C;
d=D;
m=m13;
s=32'd05;
t=`T_29;
next_A=next_a;
end
4'b1101:
begin
a=D;
b=A;
c=B;
d=C;
m=m2;
s=32'd09;
t=`T_30;
next_D=next_a;
end
4'b1110:
begin
a=C;
b=D;
c=A;
d=B;
m=m7;
s=32'd14;
t=`T_31;
next_C=next_a;
end
4'b1111:
begin
a=B;
b=C;
c=D;
d=A;
m=m12;
s=32'd20;
t=`T_32;
next_B=next_a;
end
endcase
if (phase == 4'b1111)
next_state = ROUND3[7:0];
end // }
//----------------------------------------------------------------
//--------------------------- ROUND 3 ----------------------------
//----------------------------------------------------------------
current_state[ROUND3_BIT]:
begin // {
// synopsys translate_off
ascii_state = "ROUND3";
// synopsys translate_on
round = `ROUND3;
case (phase)
4'b0000:
begin
a=A;
b=B;
c=C;
d=D;
m=m5;
s=32'd04;
t=`T_33;
next_A=next_a;
end
4'b0001:
begin
a=D;
b=A;
c=B;
d=C;
m=m8;
s=32'd11;
t=`T_34;
next_D=next_a;
end
4'b0010:
begin
a=C;
b=D;
c=A;
d=B;
m=m11;
s=32'd16;
t=`T_35;
next_C=next_a;
end
4'b0011:
begin
a=B;
b=C;
c=D;
d=A;
m=m14;
s=32'd23;
t=`T_36;
next_B=next_a;
end
4'b0100:
begin
a=A;
b=B;
c=C;
d=D;
m=m1;
s=32'd04;
t=`T_37;
next_A=next_a;
end
4'b0101:
begin
a=D;
b=A;
c=B;
d=C;
m=m4;
s=32'd11;
t=`T_38;
next_D=next_a;
end
4'b0110:
begin
a=C;
b=D;
c=A;
d=B;
m=m7;
s=32'd16;
t=`T_39;
next_C=next_a;
end
4'b0111:
begin
a=B;
b=C;
c=D;
d=A;
m=m10;
s=32'd23;
t=`T_40;
next_B=next_a;
end
4'b1000:
begin
a=A;
b=B;
c=C;
d=D;
m=m13;
s=32'd04;
t=`T_41;
next_A=next_a;
end
4'b1001:
begin
a=D;
b=A;
c=B;
d=C;
m=m0;
s=32'd11;
t=`T_42;
next_D=next_a;
end
4'b1010:
begin
a=C;
b=D;
c=A;
d=B;
m=m3;
s=32'd16;
t=`T_43;
next_C=next_a;
end
4'b1011:
begin
a=B;
b=C;
c=D;
d=A;
m=m6;
s=32'd23;
t=`T_44;
next_B=next_a;
end
4'b1100:
begin
a=A;
b=B;
c=C;
d=D;
m=m9;
s=32'd04;
t=`T_45;
next_A=next_a;
end
4'b1101:
begin
a=D;
b=A;
c=B;
d=C;
m=m12;
s=32'd11;
t=`T_46;
next_D=next_a;
end
4'b1110:
begin
a=C;
b=D;
c=A;
d=B;
m=m15;
s=32'd16;
t=`T_47;
next_C=next_a;
end
4'b1111:
begin
a=B;
b=C;
c=D;
d=A;
m=m2;
s=32'd23;
t=`T_48;
next_B=next_a;
end
endcase
if (phase == 4'b1111)
next_state = ROUND4[7:0];
end // }
//----------------------------------------------------------------
//--------------------------- ROUND 4 ----------------------------
//----------------------------------------------------------------
current_state[ROUND4_BIT]:
begin // {
// synopsys translate_off
ascii_state = "ROUND4";
// synopsys translate_on
round = `ROUND4;
case (phase)
4'b0000:
begin
a=A;
b=B;
c=C;
d=D;
m=m0;
s=32'd06;
t=`T_49;
next_A=next_a;
end
4'b0001:
begin
a=D;
b=A;
c=B;
d=C;
m=m7;
s=32'd10;
t=`T_50;
next_D=next_a;
end
4'b0010:
begin
a=C;
b=D;
c=A;
d=B;
m=m14;
s=32'd15;
t=`T_51;
next_C=next_a;
end
4'b0011:
begin
a=B;
b=C;
c=D;
d=A;
m=m5;
s=32'd21;
t=`T_52;
next_B=next_a;
end
4'b0100:
begin
a=A;
b=B;
c=C;
d=D;
m=m12;
s=32'd06;
t=`T_53;
next_A=next_a;
end
4'b0101:
begin
a=D;
b=A;
c=B;
d=C;
m=m3;
s=32'd10;
t=`T_54;
next_D=next_a;
end
4'b0110:
begin
a=C;
b=D;
c=A;
d=B;
m=m10;
s=32'd15;
t=`T_55;
next_C=next_a;
end
4'b0111:
begin
a=B;
b=C;
c=D;
d=A;
m=m1;
s=32'd21;
t=`T_56;
next_B=next_a;
end
4'b1000:
begin
a=A;
b=B;
c=C;
d=D;
m=m8;
s=32'd06;
t=`T_57;
next_A=next_a;
end
4'b1001:
begin
a=D;
b=A;
c=B;
d=C;
m=m15;
s=32'd10;
t=`T_58;
next_D=next_a;
end
4'b1010:
begin
a=C;
b=D;
c=A;
d=B;
m=m6;
s=32'd15;
t=`T_59;
next_C=next_a;
end
4'b1011:
begin
a=B;
b=C;
c=D;
d=A;
m=m13;
s=32'd21;
t=`T_60;
next_B=next_a;
end
4'b1100:
begin
a=A;
b=B;
c=C;
d=D;
m=m4;
s=32'd06;
t=`T_61;
next_A=next_a;
end
4'b1101:
begin
a=D;
b=A;
c=B;
d=C;
m=m11;
s=32'd10;
t=`T_62;
next_D=next_a;
end
4'b1110:
begin
a=C;
b=D;
c=A;
d=B;
m=m2;
s=32'd15;
t=`T_63;
next_C=next_a;
end
4'b1111:
begin
a=B;
b=C;
c=D;
d=A;
m=m9;
s=32'd21;
t=`T_64;
next_B=next_a;
end
endcase
if (phase == 4'b1111)
next_state = FINISH_OFF[7:0];
end // }
//----------------------------------------------------------------
current_state[FINISH_OFF_BIT]:
begin // {
// synopsys translate_off
ascii_state = "FINISH_OFF";
// synopsys translate_on
next_A = AA + A;
next_B = BB + B;
next_C = CC + C;
next_D = DD + D;
next_state = TURN_ARND[7:0];
end // }
//----------------------------------------------------------------
// One cycle for making the system to come to reset state
current_state[TURN_ARND_BIT]:
begin // {
// synopsys translate_off
ascii_state = "TURN_ARND";
// synopsys translate_on
next_state = IDLE[7:0];
end // }
endcase
end // }
//--------------------------------
//
// Flops and other combinatorial
// logic definition
//
//--------------------------------
// Outputs
assign msg_output = {{A[7:0], A[15:8], A[23:16], A[31:24]}
,{B[7:0], B[15:8], B[23:16], B[31:24]}
,{C[7:0], C[15:8], C[23:16], C[31:24]}
,{D[7:0], D[15:8], D[23:16], D[31:24]}};
always @(posedge clk)
msg_out_valid <= current_state[FINISH_OFF_BIT];
assign ready = current_state[IDLE_BIT];
// Internal scratch pads
always @(posedge clk)
if (next_state[ROUND1_BIT] && current_state[IDLE_BIT])
begin // {
AA <= A;
BB <= B;
CC <= C;
DD <= D;
end // }
// Initialize A, B, C and D and then compute them
always @(posedge clk)
if (rst )
begin // {
A <= SALT_A;
B <= SALT_B;
C <= SALT_C;
D <= SALT_D;
end // }
else
begin // {
A <= next_A;
B <= next_B;
C <= next_C;
D <= next_D;
end // }
// Determine one of the 16 phases within each round
always @(posedge clk)
if (rst)
phase <= 4'b0;
else if (next_state[ROUND1_BIT] && current_state[IDLE_BIT])
phase <= 4'b0;
else
phase <= phase + 4'b1;
// Assign current_state based on rst and the next_state
always @(posedge clk)
if (rst)
current_state <= IDLE[7:0];
else
current_state <= next_state;
endmodule
|
/*****************************************************************
Pancham is an MD5 compliant IP core for cryptographic applicati
-ons.
Copyright (C) 2003 Swapnajit Mittra, Project VeriPage
(Contact email: verilog_tutorial at hotmail.com
Website : http://www.angelfire.com/ca/verilog)
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the
Free Software Foundation, Inc.
59 Temple Place, Suite 330
Boston, MA 02111-1307
USA
******************************************************************/
/*
* pancham_round performs the rounds 1-4 of the MD5 algorithm
* described in RFC1321 for a 128-bit long input message.
*
* Inputs: [abcd m[k] s abs(sin(2*pi*t/64))] as described
* in RFC1321.Also the round number (1-4).
*
* Outputs: the modified 'a' value as describes in RFC1321
* on the left hand side of the round #n equation.
*
*/
`define ROUND1 2'b00
`define ROUND2 2'b01
`define ROUND3 2'b10
`define ROUND4 2'b11
module pancham_round (
a
, b
, c
, d
, m
, s
, t
, round
, next_a
);
input [31:0] a;
input [31:0] b;
input [31:0] c;
input [31:0] d;
input [31:0] m; // Note that for a 128-bit long input message, X[k] = M[k] = m
input [31:0] s;
input [31:0] t; // t-th sample of abs(sin(i)), i = 1, 2, ..., 64
input [1:0] round; // round number (1-4).
output [31:0] next_a;
wire [31:0] a; //
wire [31:0] b;
wire [31:0] c;
wire [31:0] d;
wire [31:0] m;
wire [31:0] s;
wire [31:0] t;
wire [1:0] round;
reg [31:0] next_a;
reg [31:0] add_result;
reg [31:0] rotate_result1;
reg [31:0] rotate_result2;
always @(a
or b
or c
or d
or m
or s
or t
or round)
begin // {
case (round)
`ROUND1:
begin // {
add_result = (a + F(b,c,d) + m + t);
rotate_result1 = add_result << s;
rotate_result2 = add_result >> (32-s);
next_a = b + (rotate_result1 | rotate_result2);
end // }
`ROUND2:
begin // {
add_result = (a + G(b,c,d) + m + t);
rotate_result1 = add_result << s;
rotate_result2 = add_result >> (32-s);
next_a = b + (rotate_result1 | rotate_result2);
end // }
`ROUND3:
begin // {
add_result = (a + H(b,c,d) + m + t);
rotate_result1 = add_result << s;
rotate_result2 = add_result >> (32-s);
next_a = b + (rotate_result1 | rotate_result2);
end // }
`ROUND4:
begin // {
add_result = (a + I(b,c,d) + m + t);
rotate_result1 = add_result << s;
rotate_result2 = add_result >> (32-s);
next_a = b + (rotate_result1 | rotate_result2);
end // }
endcase
end // }
//--------------------------------
//
// Function declarations
//
//--------------------------------
// Step 4 functions F, G, H and I
function [31:0] F;
input [31:0] x, y, z;
begin // {
F = (x&y)|((~x)&z);
end // }
endfunction // }
function [31:0] G;
input [31:0] x, y, z;
begin // {
G = (x&z)|(y&(~z));
end // }
endfunction
function [31:0] H;
input [31:0] x, y, z;
begin // {
H = (x^y^z);
end // }
endfunction
function [31:0] I;
input [31:0] x, y, z;
begin // {
I = (y^(x|(~z)));
end // }
endfunction
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Defines of the Core ////
//// ////
//// Known problems (limits): ////
//// None ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - gorban@opencores.org ////
//// - Jacob Gorban ////
//// - Igor Mohor (igorm@opencores.org) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Timescale define
`timescale 1ns/10ps
|
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/100ps
//------------------------------------------------------------------
// Test module.
//------------------------------------------------------------------
module tb_modexp();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// Debug output control.
parameter DEBUG = 0;
parameter VCD = 1;
// Clock defines.
localparam CLK_HALF_PERIOD = 1;
localparam CLK_PERIOD = 2 * CLK_HALF_PERIOD;
// Address defines
localparam OPERAND_WIDTH = 32;
localparam ADDRESS_WIDTH = 8;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_CYCLES_HIGH = 8'h10;
localparam ADDR_CYCLES_LOW = 8'h11;
localparam ADDR_MODULUS_LENGTH = 8'h20;
localparam ADDR_EXPONENT_LENGTH = 8'h21;
localparam ADDR_MODULUS_PTR_RST = 8'h30;
localparam ADDR_MODULUS_DATA = 8'h31;
localparam ADDR_EXPONENT_PTR_RST = 8'h40;
localparam ADDR_EXPONENT_DATA = 8'h41;
localparam ADDR_MESSAGE_PTR_RST = 8'h50;
localparam ADDR_MESSAGE_DATA = 8'h51;
localparam ADDR_RESULT_PTR_RST = 8'h60;
localparam ADDR_RESULT_DATA = 8'h61;
localparam DEFAULT_MODLENGTH = 8'h80; // 2048 bits.
localparam DEFAULT_EXPLENGTH = 8'h80;
localparam CORE_NAME0 = 32'h6d6f6465; // "mode"
localparam CORE_NAME1 = 32'h78702020; // "xp "
localparam CORE_VERSION = 32'h302e3532; // "0.52"
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg [127 : 0] result_data;
reg tb_clk;
reg tb_reset_n;
reg tb_cs;
reg tb_we;
reg [31 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
wire tb_error;
reg tb_cyc;
reg [3 : 0] tb_sel;
wire tb_ack;
wire tb_err;
wire tb_int;
reg [31 : 0] pmsg [63 : 0];
reg [31 : 0] cmsg [63 : 0];
reg [31 : 0] gmsg [63 : 0];
integer f1;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
modexp dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.cs(tb_cs),
.we(tb_we),
.address(tb_address[10:2]),
.write_data(tb_write_data),
.read_data(tb_read_data));
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut();
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
$display("");
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim();
begin
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_cs = 0;
tb_we = 0;
tb_address = 32'h00000000;
tb_write_data = 32'h00000000;
end
endtask // init_sim
//----------------------------------------------------------------
// read_word()
//
// Read a data word from the given address in the DUT.
//----------------------------------------------------------------
task read_word(input [7 : 0] address);
begin
tb_address = {22'b0,address,2'b0};
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
tb_cs = 0;
if (DEBUG)
begin
$display("*** (read_word) Reading 0x%08x from 0x%02x.", tb_read_data, address);
$display("");
end
end
endtask // read_word
//----------------------------------------------------------------
// write_word()
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [ 7 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
begin
$display("*** (write_word) Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
tb_address = {22'b0,address,2'b0};
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask // write_word
//----------------------------------------------------------------
// wait_ready()
//
// Wait until the ready flag in the core is set.
//----------------------------------------------------------------
task wait_ready();
begin
while (tb_read_data != 32'h00000001)
read_word(8'h09);
if (DEBUG)
$display("*** (wait_ready) Ready flag has been set.");
end
endtask // wait_ready
//----------------------------------------------------------------
// assertEquals
//----------------------------------------------------------------
function assertEquals(
input [31:0] expected,
input [31:0] actual
);
begin
if (expected === actual)
begin
assertEquals = 1; // success
end
else
begin
$display("*** Expected: 0x%08x, got 0x%08x", expected, actual);
assertEquals = 0; // failure
end
end
endfunction // assertEquals
//----------------------------------------------------------------
// assertSuccess
//----------------------------------------------------------------
task assertSuccess(input success);
begin
if (success !== 1)
begin
$display("*** Test -> FAILED");
error_ctr = error_ctr + 1;
end
else
$display("*** Test -> passed");
end
endtask // assertSuccess
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results();
begin
$display("");
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// exp32bit_mod2048bit_test();
//----------------------------------------------------------------
task exp32bit_mod2048bit_test();
integer i;
integer success;
reg [31 : 0] read_data;
reg [31 : 0] exp [63 : 0];
reg [31 : 0] mod [63 : 0];
reg [31 : 0] msg [63 : 0];
reg [31 : 0] res [63 : 0];
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("");
$display("Test with e = 65537 and 2048 bit modulus -- Encrypting");
$readmemh("./gen/exp", exp);
$readmemh("./gen/mod", mod);
$readmemh("./gen/msg", msg);
$readmemh("./gen/res", res);
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
write_word(ADDR_EXPONENT_DATA , exp[0]);
write_word(ADDR_MODULUS_PTR_RST, 32'h00000000);
write_word(ADDR_MODULUS_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MODULUS_DATA, mod[i]);
if(DEBUG) $display("writing: %d -> %h", i, mod[i]);
end
write_word(ADDR_MESSAGE_PTR_RST, 32'h00000000);
write_word(ADDR_MESSAGE_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MESSAGE_DATA, msg[i]);
if(DEBUG) $display("Writing: %d -> %h", i, msg[i]);
end
write_word(ADDR_EXPONENT_LENGTH, 32'h00000001);
write_word(ADDR_MODULUS_LENGTH , 32'h00000041);
// Start processing and wait for ready.
write_word(ADDR_CTRL, 32'h00000001);
wait_ready();
write_word(ADDR_RESULT_PTR_RST, 32'h00000000);
read_word(ADDR_RESULT_DATA); read_data=tb_read_data;
success=success&assertEquals(32'h00000000, read_data);
for(i=0; i<64; i=i+1) begin
read_word(ADDR_RESULT_DATA);
read_data=tb_read_data;
success=success&assertEquals(res[i], read_data);
if(DEBUG) $display("Reading: %d -> %h -> %h", i, res[i], read_data);
end
if (success !== 1)
begin
$display("*** ERROR: e65537_2048bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_2048bit_modulus success.");
end
endtask // e65537_2048bit_modulus
//----------------------------------------------------------------
// modexp_encrypt
//----------------------------------------------------------------
task modexp_encrypt();
integer i;
integer success;
reg [31 : 0] pubexp [1];
reg [31 : 0] pubmod [63 : 0];
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("");
$display("Encrypting -- exp = 65537 and 2048 bit mod");
$readmemh("./gen/pTextHEX", pmsg);
$readmemh("./gen/exponent", pubexp);
$readmemh("./gen/modulus", pubmod);
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
write_word(ADDR_EXPONENT_DATA , pubexp[0]);
if(DEBUG) $display("Writing EXP: %d %h", pubexp[0], pubexp[0]);
write_word(ADDR_MODULUS_PTR_RST, 32'h00000000);
write_word(ADDR_MODULUS_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MODULUS_DATA, pubmod[i]);
if(DEBUG) $display("Writing MOD: %d -> %h", i, pubmod[i]);
end
write_word(ADDR_MESSAGE_PTR_RST, 32'h00000000);
write_word(ADDR_MESSAGE_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MESSAGE_DATA, pmsg[i]);
if(DEBUG) $display("Writing MSG: %d -> %h", i, pmsg[i]);
end
write_word(ADDR_EXPONENT_LENGTH, 32'h00000001);
write_word(ADDR_MODULUS_LENGTH , 32'h00000041);
// Start processing and wait for ready.
write_word(ADDR_CTRL, 32'h00000001);
wait_ready();
write_word(ADDR_RESULT_PTR_RST, 32'h00000000);
read_word(ADDR_RESULT_DATA); cmsg[0]=tb_read_data;
//success=success&assertEquals(32'h00000000, cmsg[0]);
f1 = $fopen("./gen/cTextHEX", "w");
for(i=0; i<64; i=i+1) begin
read_word(ADDR_RESULT_DATA);
cmsg[i]=tb_read_data;
if(DEBUG) $display("Reading: %d -> %h ", i, cmsg[i]);
$fwrite(f1, "%h\n",cmsg[i]);
end
$fclose(f1);
assertSuccess(success);
end
endtask // e65537_2048bit_modulus
//----------------------------------------------------------------
// modexp_decrypt
//----------------------------------------------------------------
task modexp_decrypt();
integer i;
integer success;
reg [31 : 0] rdata;
reg [31 : 0] read_data;
reg [31 : 0] priexp [63 : 0];
reg [31 : 0] primod [63 : 0];
begin
$display("");
$display("*** Running -> modexp_decrypt()");
$readmemh("./gen/priExponent", priexp);
$readmemh("./gen/priModulus", primod);
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Decrypting -- 2048 bit exp and 2048 bit mod");
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
write_word(ADDR_EXPONENT_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_EXPONENT_DATA, priexp[i]);
if(DEBUG) $display("Writing EXP: %d -> %h", i, priexp[i]);
end
write_word(ADDR_MODULUS_PTR_RST, 32'h00000000);
write_word(ADDR_MODULUS_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MODULUS_DATA, primod[i]);
if(DEBUG) $display("Writing MOD: %d -> %h", i, primod[i]);
end
write_word(ADDR_MESSAGE_PTR_RST, 32'h00000000);
write_word(ADDR_MESSAGE_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MESSAGE_DATA, cmsg[i]);
if(DEBUG) $display("Writing MSG: %d -> %h", i, cmsg[i]);
end
write_word(ADDR_EXPONENT_LENGTH, 32'h00000041);
write_word(ADDR_MODULUS_LENGTH , 32'h00000041);
// Start processing and wait for ready.
write_word(ADDR_CTRL, 32'h00000001);
wait_ready();
write_word(ADDR_RESULT_PTR_RST, 32'h00000000);
read_word(ADDR_RESULT_DATA); rdata=tb_read_data;
success=success&assertEquals(32'h00000000, rdata);
f1 = $fopen("./gen/gTextHEX", "w");
for(i=0; i<64; i=i+1) begin
read_word(ADDR_RESULT_DATA);
rdata=tb_read_data;
if(DEBUG) $display("Reading: %d -> %h ", i, rdata);
$fwrite(f1, "%h\n",rdata);
success=success&assertEquals(pmsg[i], rdata);
end
$fclose(f1);
assertSuccess(success);
end
endtask // e65537_2048bit_modulus
//----------------------------------------------------------------
// modexp_32bits
//----------------------------------------------------------------
task modexp_32bits(input [31:0] Wmsg,
input [31:0] Wexp,
input [31:0] Wmod,
input [31:0] Wres);
reg [31 : 0] Rmsg;
reg [31 : 0] Rexp;
reg [31 : 0] Rmod;
reg [31 : 0] Rres;
integer success;
begin
$display("");
$display("*** Running -> modexp_32bits()");
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("*** Writing -> MES: %h EXP: %h MOD: %h", Wmsg, Wexp, Wmod);
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
write_word(ADDR_EXPONENT_DATA , Wexp);
write_word(ADDR_MODULUS_PTR_RST , 32'h00000000);
write_word(ADDR_MODULUS_DATA , Wmod);
write_word(ADDR_MESSAGE_PTR_RST , 32'h00000000);
write_word(ADDR_MESSAGE_DATA , Wmsg);
write_word(ADDR_EXPONENT_LENGTH , 32'h00000001);
write_word(ADDR_MODULUS_LENGTH , 32'h00000001);
// Start processing and wait for ready.
write_word(ADDR_CTRL , 32'h00000001);
wait_ready();
write_word(ADDR_MESSAGE_PTR_RST , 32'h00000000);
read_word(ADDR_MESSAGE_DATA);
Rmsg=tb_read_data;
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
read_word(ADDR_EXPONENT_DATA);
Rexp=tb_read_data;
write_word(ADDR_MODULUS_PTR_RST , 32'h00000000);
read_word(ADDR_MODULUS_DATA);
Rmod=tb_read_data;
write_word(ADDR_RESULT_PTR_RST , 32'h00000000);
read_word(ADDR_RESULT_DATA);
Rres=tb_read_data;
$display("*** Reading -> MES: %h EXP: %h MOD: %h RES: %h", Rmsg, Rexp, Rmod, Rres);
success=success&assertEquals(Wres, Rres);
assertSuccess(success);
end
endtask // e65537_2048bit_modulus
//----------------------------------------------------------------
// main
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : main
if(VCD) begin
$dumpfile("./iverilog/tb_modexp.vcd");
$dumpvars(0,tb_modexp);
//$dumpvars(1,tb_clk, tb_reset_n, tb_cs, tb_we, tb_address, tb_write_data, tb_read_data);
end
$display(" -= Testbench for modexp started =-");
$display(" =================================");
$display("");
init_sim();
reset_dut();
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000005, 32'h00000001); //msg^exp < mod -> 1^2 < 5
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000003, 32'h00000001); //msg^exp < mod -> 1^2 < 3
modexp_32bits(32'h00000002, 32'h00000002, 32'h00000005, 32'h00000004); //msg^exp < mod -> 2^2 < 5
modexp_32bits(32'h00000002, 32'h00000002, 32'h00000003, 32'h00000001); //msg^exp > mod -> 2^2 > 3
modexp_32bits(32'h00000004, 32'h0000000D, 32'h000001F1, 32'h000001bd); //msg^exp > mod -> 4^13 > 497
modexp_32bits(32'h01234567, 32'h89ABCDEF, 32'h11111111, 32'h0D9EF081); //msg^exp > mod -> 19088743^2309737967 > 286331153
modexp_32bits(32'h30000000, 32'hC0000000, 32'h00A00001, 32'h0000CC3F); //msg^exp > mod -> 805306368^3221225472 > 10485761 <- Passes
//modexp_32bits(32'h30000000, 32'hC0000000, 32'h00A00000, 32'h00600000); //msg^exp > mod -> 805306368^3221225472 > 10485760 <- Fails
//modexp_32bits(32'h00000002, 32'h00000003, 32'h00000001, 32'h00000000); //mod 1 <- FAILS Does not check
/*
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000002, 32'h00000001); //1 mod 2 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000003, 32'h00000001); //1 mod 3 = 1 -> 1 <- passes
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000004, 32'h00000001); //1 mod 4 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000005, 32'h00000001); //1 mod 5 = 1 -> 1 <- passes
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000006, 32'h00000001); //1 mod 6 = 1 -> 4 <- FAILS
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000002, 32'h00000000); //2 mod 2 = 0 -> passes
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000003, 32'h00000002); //2 mod 3 = 2 -> passes
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000004, 32'h00000002); //2 mod 4 = 2 -> 0 <- FAILS
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000005, 32'h00000002); //2 mod 5 = 2 -> passes
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000006, 32'h00000002); //2 mod 6 = 2 -> passes
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000002, 32'h00000001); //3 mod 2 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000003, 32'h00000000); //3 mod 3 = 0 -> 3 <- FAILS
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000004, 32'h00000003); //3 mod 4 = 3 -> 0 <- FAILS
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000005, 32'h00000003); //3 mod 5 = 3 -> passes
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000006, 32'h00000003); //3 mod 6 = 3 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000002, 32'h00000000); //4 mod 2 = 0 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000003, 32'h00000001); //4 mod 3 = 1 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000004, 32'h00000000); //4 mod 4 = 0 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000005, 32'h00000004); //4 mod 5 = 4 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000006, 32'h00000004); //4 mod 6 = 4 -> passes
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000002, 32'h00000001); //5 mod 2 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000003, 32'h00000002); //5 mod 3 = 2 -> passes
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000004, 32'h00000001); //5 mod 4 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000005, 32'h00000000); //5 mod 5 = 0 -> 5 <- FAILS
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000006, 32'h00000005); //5 mod 6 = 5 -> passes
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000002, 32'h00000000); //6 mod 2 = 0 -> passes
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000003, 32'h00000000); //6 mod 3 = 0 -> 3 <- FAILS
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000004, 32'h00000002); //6 mod 4 = 2 -> 0 <- FAILS
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000005, 32'h00000001); //6 mod 5 = 1 -> passes
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000006, 32'h00000000); //6 mod 6 = 0 -> 1 <- FAILS
*/
/*
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000002, 32'h00000000); //8^6 mod 2 = 0 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000003, 32'h00000001); //8^6 mod 3 = 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000004, 32'h00000000); //8^6 mod 4 = 0 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000005, 32'h00000004); //8^6 mod 5 = 4 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000006, 32'h00000004); //8^6 mod 6 = 4 -> 1 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000007, 32'h00000001); //8^6 mod 7 = 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000008, 32'h00000000); //8^6 mod 8 = 0 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000009, 32'h00000001); //8^6 mod 9 = 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000A, 32'h00000004); //8^6 mod 10= 4 -> 9 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000B, 32'h00000003); //8^6 mod 11= 3 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000C, 32'h00000004); //8^6 mod 12= 4 -> 5 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000D, 32'h0000000C); //8^6 mod 13= 12-> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000E, 32'h00000008); //8^6 mod 14= 8 -> 5 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000F, 32'h00000004); //8^6 mod 15= 4 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000010, 32'h00000000); //8^6 mod 16= 0 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000011, 32'h00000004); //8^6 mod 17= 4 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000012, 32'h0000000A); //8^6 mod 18= 10-> 13<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000013, 32'h00000001); //8^6 mod 19= 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000014, 32'h00000004); //8^6 mod 20= 4 -> 11<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000015, 32'h00000001); //8^6 mod 21= 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000016, 32'h0000000E); //8^6 mod 22= 14-> 1 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000017, 32'h0000000D); //8^6 mod 23= 13-> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000018, 32'h00000010); //8^6 mod 24= 16-> 9 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000019, 32'h00000013); //8^6 mod 25= 19-> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001A, 32'h0000000C); //8^6 mod 26= 12-> 19<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001B, 32'h00000001); //8^6 mod 27= 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001C, 32'h00000008); //8^6 mod 28= 8 -> 19<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001D, 32'h0000000D); //8^6 mod 29= 13-> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001E, 32'h00000004); //8^6 mod 30= 4 -> 13<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001F, 32'h00000008); //8^6 mod 31= 8 -> passes
*/
//exp32bit_mod2048bit_test();
//modexp_encrypt();
//modexp_decrypt();
display_test_results();
$display("");
$display("*** modexp simulation done. ***");
$finish;
end // main
endmodule // tb_modexp
//======================================================================
// EOF tb_modexp.v
//======================================================================
|
//======================================================================
//
// tb_modexp.v
// -----------
// Testbench modular exponentiation core.
//
//
// Author: Joachim Strombergson, Peter Magnusson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/100ps
//------------------------------------------------------------------
// Test module.
//------------------------------------------------------------------
module tb_modexp();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// Debug output control.
parameter DEBUG = 0;
parameter DEBUG_EI = 0;
parameter DEBUG_RESULT = 0;
parameter DISPLAY_TEST_CYCLES = 1;
// Clock defines.
localparam CLK_HALF_PERIOD = 1;
localparam CLK_PERIOD = 2 * CLK_HALF_PERIOD;
// The DUT address map.
localparam GENERAL_PREFIX = 4'h0;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_START_BIT = 0;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_MODULUS_LENGTH = 8'h20;
localparam ADDR_EXPONENT_LENGTH = 8'h21;
localparam ADDR_LENGTH = 8'h22;
localparam ADDR_MODULUS_PTR_RST = 8'h30;
localparam ADDR_MODULUS_DATA = 8'h31;
localparam ADDR_EXPONENT_PTR_RST = 8'h40;
localparam ADDR_EXPONENT_DATA = 8'h41;
localparam ADDR_MESSAGE_PTR_RST = 8'h50;
localparam ADDR_MESSAGE_DATA = 8'h51;
localparam ADDR_RESULT_PTR_RST = 8'h60;
localparam ADDR_RESULT_DATA = 8'h61;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] test_cycle_ctr;
reg test_cycle_ctr_rst;
reg test_cycle_ctr_inc;
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg [31 : 0] read_data;
reg [127 : 0] result_data;
reg tb_clk;
reg tb_reset_n;
reg tb_cs;
reg tb_we;
reg [11 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
wire tb_error;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
modexp dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.cs(tb_cs),
.we(tb_we),
.address(tb_address),
.write_data(tb_write_data),
.read_data(tb_read_data)
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
end
end
//----------------------------------------------------------------
// test_cycle_counter
//
// Used to measure the number of cycles it takes to perform
// a given test case.
//----------------------------------------------------------------
always @ (posedge tb_clk)
begin
if (test_cycle_ctr_rst)
test_cycle_ctr = 64'h0000000000000000;
if (test_cycle_ctr_inc)
test_cycle_ctr = test_cycle_ctr + 1;
end
//----------------------------------------------------------------
// start_test_cycle_ctr
//
// Reset and start the test cycle counter.
//----------------------------------------------------------------
task start_test_cycle_ctr();
begin
test_cycle_ctr_rst = 1;
#(CLK_PERIOD);
test_cycle_ctr_rst = 0;
test_cycle_ctr_inc = 1;
end
endtask // start_test_cycle_ctr()
//----------------------------------------------------------------
// stop_test_cycle_ctr()
//
// Stop the test cycle counter and optionally display the
// result.
//----------------------------------------------------------------
task stop_test_cycle_ctr();
begin
test_cycle_ctr_inc = 0;
#(CLK_PERIOD);
if (DISPLAY_TEST_CYCLES)
$display("*** Number of cycles performed during test: 0x%016x", test_cycle_ctr);
end
endtask // stop_test_cycle_ctr()
//----------------------------------------------------------------
// ei_monitor()
//
// Displays ei_new, the most important variable for determining
// what modexp will do (i.e. should Z=MONTPROD( Z, P, M) be
// performed
//----------------------------------------------------------------
always @*
begin : ei_monitor
if (DEBUG_EI)
if (dut.modexp_ctrl_reg == dut.CTRL_ITERATE_Z_P)
$display("loop counter %d: ei = %d", dut.loop_counter_reg, dut.ei_reg);
end
//----------------------------------------------------------------
// z_monitor()
//
// Displays the contents of the result_mem.
//----------------------------------------------------------------
always @*
begin : result_monitor
if (DEBUG_RESULT)
$display("result_mem[0][1] = %x %x",dut.result_mem.mem[0],dut.result_mem.mem[1]);
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
task dump_dut_state();
begin
$display("cycle: 0x%016x", cycle_ctr);
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
$display("cs = 0x%01x, we = 0x%01x", tb_cs, tb_we);
$display("addr = 0x%08x, read_data = 0x%08x, write_data = 0x%08x",
tb_address, tb_read_data, tb_write_data);
$display("");
$display("State:");
$display("ready_reg = 0x%01x, start_reg = 0x%01x, start_new = 0x%01x",
dut.core_inst.ready_reg, dut.start_reg, dut.start_new);
$display("residue_valid = 0x%01x", dut.core_inst.residue_valid_reg);
$display("loop_counter_reg = 0x%08x", dut.core_inst.loop_counter_reg);
$display("exponent_length_reg = 0x%02x exponent_length_m1 = 0x%02x modulus_length_reg = 0x%02x modulus_length_m1 = 0x%02x",
dut.exponent_length_reg, dut.core_inst.exponent_length_m1, dut.modulus_length_reg, dut.core_inst.modulus_length_m1);
$display("ctrl_reg = 0x%04x", dut.core_inst.modexp_ctrl_reg);
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut();
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
$display("");
end
endtask // reset_dut
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results();
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim();
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_cs = 0;
tb_we = 0;
tb_address = 8'h00;
tb_write_data = 32'h00000000;
end
endtask // init_sim
//----------------------------------------------------------------
// read_word()
//
// Read a data word from the given address in the DUT.
// the word read will be available in the global variable
// read_data.
//----------------------------------------------------------------
task read_word(input [11 : 0] address);
begin
tb_address = address;
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
read_data = tb_read_data;
tb_cs = 0;
if (DEBUG)
begin
$display("*** (read_word) Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
end
end
endtask // read_word
//----------------------------------------------------------------
// write_word()
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [11 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
begin
$display("*** (write_word) Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
tb_address = address;
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask // write_word
//----------------------------------------------------------------
// wait_ready()
//
// Wait until the ready flag in the core is set.
//----------------------------------------------------------------
task wait_ready();
begin
while (tb_read_data != 32'h00000001)
read_word({GENERAL_PREFIX, ADDR_STATUS});
if (DEBUG)
$display("*** (wait_ready) Ready flag has been set.");
end
endtask // wait_ready
//----------------------------------------------------------------
// dump_message_mem()
//
// Dump the contents of the message memory.
//----------------------------------------------------------------
task dump_message_mem();
reg [8 : 0] i;
begin
$display("Contents of the message memory:");
for (i = 0 ; i < 256 ; i = i + 8)
begin
$display("message_mem[0x%02x .. 0x%02x] = 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x",
i[7 : 0], (i[7 : 0] + 8'h07),
dut.core_inst.message_mem.mem[(i[7 : 0] + 0)], dut.core_inst.message_mem.mem[(i[7 : 0] + 1)],
dut.core_inst.message_mem.mem[(i[7 : 0] + 2)], dut.core_inst.message_mem.mem[(i[7 : 0] + 3)],
dut.core_inst.message_mem.mem[(i[7 : 0] + 4)], dut.core_inst.message_mem.mem[(i[7 : 0] + 5)],
dut.core_inst.message_mem.mem[(i[7 : 0] + 6)], dut.core_inst.message_mem.mem[(i[7 : 0] + 7)],
);
end
$display("");
end
endtask // dump_message_mem
//----------------------------------------------------------------
// dump_exponent_mem()
//
// Dump the contents of the exponent memory.
//----------------------------------------------------------------
task dump_exponent_mem();
reg [8 : 0] i;
begin
$display("Contents of the exponent memory:");
for (i = 0 ; i < 256 ; i = i + 8)
begin
$display("exponent_mem[0x%02x .. 0x%02x] = 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x",
i[7 : 0], (i[7 : 0] + 8'h07),
dut.core_inst.exponent_mem.mem[(i[7 : 0] + 0)], dut.core_inst.exponent_mem.mem[(i[7 : 0] + 1)],
dut.core_inst.exponent_mem.mem[(i[7 : 0] + 2)], dut.core_inst.exponent_mem.mem[(i[7 : 0] + 3)],
dut.core_inst.exponent_mem.mem[(i[7 : 0] + 4)], dut.core_inst.exponent_mem.mem[(i[7 : 0] + 5)],
dut.core_inst.exponent_mem.mem[(i[7 : 0] + 6)], dut.core_inst.exponent_mem.mem[(i[7 : 0] + 7)],
);
end
$display("");
end
endtask // dump_exponent_mem
//----------------------------------------------------------------
// dump_modulus_mem()
//
// Dump the contents of the modulus memory.
//----------------------------------------------------------------
task dump_modulus_mem();
reg [8 : 0] i;
begin
$display("Contents of the modulus memory:");
for (i = 0 ; i < 256 ; i = i + 8)
begin
$display("modulus_mem[0x%02x .. 0x%02x] = 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x",
i[7 : 0], (i[7 : 0] + 8'h07),
dut.core_inst.modulus_mem.mem[(i[7 : 0] + 0)], dut.core_inst.modulus_mem.mem[(i[7 : 0] + 1)],
dut.core_inst.modulus_mem.mem[(i[7 : 0] + 2)], dut.core_inst.modulus_mem.mem[(i[7 : 0] + 3)],
dut.core_inst.modulus_mem.mem[(i[7 : 0] + 4)], dut.core_inst.modulus_mem.mem[(i[7 : 0] + 5)],
dut.core_inst.modulus_mem.mem[(i[7 : 0] + 6)], dut.core_inst.modulus_mem.mem[(i[7 : 0] + 7)],
);
end
$display("");
end
endtask // dump_modulus_mem
//----------------------------------------------------------------
// dump_residue_mem()
//
// Dump the contents of the residue memory.
//----------------------------------------------------------------
task dump_residue_mem();
reg [8 : 0] i;
begin
$display("Contents of the residue memory:");
for (i = 0 ; i < 256 ; i = i + 8)
begin
$display("residue_mem[0x%02x .. 0x%02x] = 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x",
i[7 : 0], (i[7 : 0] + 8'h07),
dut.core_inst.residue_mem.mem[(i[7 : 0] + 0)], dut.core_inst.residue_mem.mem[(i[7 : 0] + 1)],
dut.core_inst.residue_mem.mem[(i[7 : 0] + 2)], dut.core_inst.residue_mem.mem[(i[7 : 0] + 3)],
dut.core_inst.residue_mem.mem[(i[7 : 0] + 4)], dut.core_inst.residue_mem.mem[(i[7 : 0] + 5)],
dut.core_inst.residue_mem.mem[(i[7 : 0] + 6)], dut.core_inst.residue_mem.mem[(i[7 : 0] + 7)],
);
end
$display("");
end
endtask // dump_residue_mem
//----------------------------------------------------------------
// dump_result_mem()
//
// Dump the contents of the result memory.
//----------------------------------------------------------------
task dump_result_mem();
reg [8 : 0] i;
begin
$display("Contents of the result memory:");
for (i = 0 ; i < 256 ; i = i + 8)
begin
$display("result_mem[0x%02x .. 0x%02x] = 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x",
i[7 : 0], (i[7 : 0] + 8'h07),
dut.core_inst.result_mem.mem[(i[7 : 0] + 0)], dut.core_inst.result_mem.mem[(i[7 : 0] + 1)],
dut.core_inst.result_mem.mem[(i[7 : 0] + 2)], dut.core_inst.result_mem.mem[(i[7 : 0] + 3)],
dut.core_inst.result_mem.mem[(i[7 : 0] + 4)], dut.core_inst.result_mem.mem[(i[7 : 0] + 5)],
dut.core_inst.result_mem.mem[(i[7 : 0] + 6)], dut.core_inst.result_mem.mem[(i[7 : 0] + 7)],
);
end
$display("");
end
endtask // dump_result_mem
//----------------------------------------------------------------
// dump_memories()
//
// Dump the contents of the memories in the dut.
//----------------------------------------------------------------
task dump_memories();
begin
dump_message_mem();
dump_exponent_mem();
dump_modulus_mem();
dump_residue_mem();
dump_result_mem();
end
endtask // dump_memories
//----------------------------------------------------------------
// tc1
//
// A first, very simple testcase where we want to do:
// c = m ** e % N with the following (decimal) test values:
// m = 3
// e = 7
// n = 11
// c = 3 ** 7 % 11 = 9
//----------------------------------------------------------------
task tc1();
reg [31 : 0] read_data;
begin
tc_ctr = tc_ctr + 1;
$display("TC1: Trying to calculate 3**7 mod 11 = 9");
// Write 3 to message memory.
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000003);
// Write 7 to exponent memory and set length to one word.
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000007);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
// Write 11 to modulus memory and set length to one word.
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h0000000b);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000001);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
// Read out result word and check result.
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA});
read_data = tb_read_data;
if (read_data == 32'h00000009)
begin
$display("*** TC1 successful.");
$display("");
end
else
begin
$display("*** ERROR: TC1 NOT successful.");
$display("Expected: 0x09, got 0x%08x", read_data);
error_ctr = error_ctr + 1;
dump_memories();
end
end
endtask // tc1
//----------------------------------------------------------------
// tc2
//
// c = m ** e % N with the following (decimal) test values:
// m = 251
// e = 251
// n = 257
// c = 251 ** 251 % 257 = 183
//----------------------------------------------------------------
task tc2();
reg [31 : 0] read_data;
begin
tc_ctr = tc_ctr + 1;
$display("TC2: Trying to calculate 251**251 mod 257 = 183");
// Write 13 to message memory.
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h000000fb);
// Write 11 to exponent memory and set length to one word.
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h000000fb);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
// Write 7 to modulus memory and set length to one word.
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000101);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000001);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
// Read out result word and check result.
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA});
read_data = tb_read_data;
if (read_data == 32'h000000b7)
begin
$display("*** TC2 successful.");
$display("");
end
else
begin
$display("*** ERROR: TC2 NOT successful.");
$display("Expected: 0x000000b7, got 0x%08x", read_data);
error_ctr = error_ctr + 1;
end
end
endtask // tc2
//----------------------------------------------------------------
// tc3
//
// c = m ** e % N with the following (decimal) test values:
// m = 0x81
// e = 0x41
// n = 0x87
// c = 0x81 ** 0x41 % 0x87 = 0x36
//----------------------------------------------------------------
task tc3();
reg [31 : 0] read_data;
begin
tc_ctr = tc_ctr + 1;
$display("TC3: Trying to calculate 0x81 ** 0x41 mod 0x87 = 0x36");
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000081);
// Write 11 to exponent memory and set length to one word.
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000041);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
// Write 7 to modulus memory and set length to one word.
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000087);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000001);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
// Read out result word and check result.
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA});
read_data = tb_read_data;
if (read_data == 32'h00000036)
begin
$display("*** TC3 successful.");
$display("");
end
else
begin
$display("*** ERROR: TC3 NOT successful.");
$display("Expected: 0x06, got 0x%08x", read_data);
error_ctr = error_ctr + 1;
end
end
endtask // tc3
//----------------------------------------------------------------
// assertEquals
//----------------------------------------------------------------
function assertEquals(
input [31:0] expected,
input [31:0] actual
);
begin
if (expected === actual)
begin
assertEquals = 1; // success
end
else
begin
$display("Expected: 0x%08x, got 0x%08x", expected, actual);
assertEquals = 0; // failure
end
end
endfunction // assertEquals
integer success;
//----------------------------------------------------------------
// autogenerated_BASIC_33bit()
//
// Task that tests modexp with 33 bit oprerands.
//----------------------------------------------------------------
task autogenerated_BASIC_33bit();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("autogenerated_BASIC_33bit: 00000001946473e1 ** h000000010e85e74f mod 0000000170754797 ");
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h946473e1);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h0e85e74f);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h70754797);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000002);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000002);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7761ed4f, read_data);
if (success !== 1)
begin
$display("*** ERROR: autogenerated_BASIC_33bit was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** autogenerated_BASIC_33bit success.");
end
endtask // autogenerated_BASIC_33bit
//----------------------------------------------------------------
// autogenerated_BASIC_128bit()
//
// Task that tests modexp with 128 bit operands.
//----------------------------------------------------------------
task autogenerated_BASIC_128bit();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("autogenerated_BASIC_128bit");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h3285c343);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h2acbcb0f);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h4d023228);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h2ecc73db);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h29462882);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h12caa2d5);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb80e1c66);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h1006807f);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h267d2f2e);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h51c216a7);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hda752ead);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h48d22d89);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000004);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000005);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0ddc404d, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h91600596, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7425a8d8, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha066ca56, read_data);
if (success !== 1)
begin
$display("*** ERROR: autogenerated_BASIC_128bit was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** autogenerated_BASIC_128bit success.");
end
endtask // autogenerated_BASIC_128bit
//----------------------------------------------------------------
// e64bit_64bit_modulus()
//----------------------------------------------------------------
task e64bit_64bit_modulus();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with 64 bit exponent and 64 bit modulus.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h12345678);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h97543211);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hfeababab);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hdeadbeef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffee);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hbeefbeef);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000002);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000003);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'he52c5b9f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h85de87eb, read_data);
if (success !== 1)
begin
$display("*** ERROR: 64 bit exponent and 64 bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** 64 bit exponent and 64 bit modulus success.");
end
endtask // e64bit_64bit_modulus
//----------------------------------------------------------------
// e65537_64bit_modulus()
//----------------------------------------------------------------
task e65537_64bit_modulus();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with e = 65537 and 64 bit modulus.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hf077656f);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h3bf9e69b);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb6684dc3);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h79a5824b);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000003);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h132d8e17, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hdd4d85a4, read_data);
if (success !== 1)
begin
$display("*** ERROR: e65537_64bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_64bit_modulus success.");
end
endtask // e65537_64bit_modulus
//----------------------------------------------------------------
// e65537_64bit_modulus_elength()
//----------------------------------------------------------------
task e65537_64bit_modulus_elength();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with e = 65537 and 64 bit modulus, explicit exponent length.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hf077656f);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h3bf9e69b);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb6684dc3);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h79a5824b);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000003);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h132d8e17, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hdd4d85a4, read_data);
if (success !== 1)
begin
$display("*** ERROR: e65537_64bit_modulus with explicit elength was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_64bit_modulus success.");
end
endtask // e65537_64bit_modulus_elength
//----------------------------------------------------------------
// e65537_128bit_modulus()
//----------------------------------------------------------------
task e65537_128bit_modulus();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with e = 65537 and 128 bit modulus.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hf5e8eee0);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hc06b048a);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h964b2105);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h2c36ad6b);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h956e61b3);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h27997bc4);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h94e7e5c9);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb53585cf);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000005);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h9c6d322c, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h25ab8bd3, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4aa80100, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf0f3a02c, read_data);
if (success !== 1)
begin
$display("*** ERROR: e65537_128bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_128bit_modulus success.");
end
endtask // e65537_128bit_modulus
//----------------------------------------------------------------
// e65537_256bit_modulus()
//
// Task that tests modexp with small exponent and 256 bit modulus.
//----------------------------------------------------------------
task e65537_256bit_modulus();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with e = 65537 and 256 bit modulus.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hf169d36e);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hbe2ce61d);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hc2e87809);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h4fed15c3);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h7c70eac5);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'ha123e643);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h299b36d2);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h788e583b);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hf169d36e);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hbe2ce61d);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hc2e87809);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h4fed15c3);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h7c70eac5);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'ha123e643);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h299b36d2);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h788e583a);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000009);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf169d36e, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hbe2ce61d, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hc2e87809, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4fed15c3, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7c70eac5, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha123e643, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h299b36d2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h788e583a, read_data);
if (success !== 1)
begin
$display("*** ERROR: e65537_256bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_256bit_modulus success.");
end
endtask // e65537_256bit_modulus
//----------------------------------------------------------------
// e65537_1024bit_modulus()
//
// Task that tests modexp with small exponent and
// 2048 bit modulus.
//----------------------------------------------------------------
task e65537_1024bit_modulus();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with e = 65537 and 1024 bit modulus.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000021);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h45d55343, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha0971add, read_data);
if (success !== 1)
begin
$display("*** ERROR: e65537_1024bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_1024bit_modulus success.");
end
endtask // e65537_1024bit_modulus
//----------------------------------------------------------------
// e65537_1536bit_modulus()
//
// Task that tests modexp with small exponent and
// 1536 bit modulus.
//----------------------------------------------------------------
task e65537_1536bit_modulus();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with e = 65537 and 1536 bit modulus.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000031);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4ade4f46, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h02cb4a2f, read_data);
if (success !== 1)
begin
$display("*** ERROR: e65537_1536bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_1536bit_modulus success.");
end
endtask // e65537_1536bit_modulus
//----------------------------------------------------------------
// e65537_1664bit_modulus()
//
// Task that tests modexp with small exponent and
// 1664 bit modulus.
//----------------------------------------------------------------
task e65537_1664bit_modulus();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with e = 65537 and 1664 bit modulus.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000035);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h88671c15, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2aeeb8b2, read_data);
if (success !== 1)
begin
$display("*** ERROR: e65537_1664bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_1664it_modulus success.");
end
endtask // e65537_1664bit_modulus
//----------------------------------------------------------------
// e65537_2048bit_modulus()
//
// Task that tests modexp with small exponent and
// 2048 bit modulus.
//----------------------------------------------------------------
task e65537_2048bit_modulus();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Test with e = 65537 and 2048 bit modulus.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hffeeffef);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffaabbcc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hddeeffff);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000001);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000041);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf1752196, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4c36e92f, read_data);
if (success !== 1)
begin
$display("*** ERROR: e65537_2048bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_2048bit_modulus success.");
end
endtask // e65537_2048bit_modulus
//----------------------------------------------------------------
// rob_dec_1024()
//
// Task that tests modexp with 1024 bit decipher/sign with
// real RSA key operands.
//----------------------------------------------------------------
task rob_dec_1024();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Desipher/Sign Test with Rob 1024 bit operands.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h3ff26c9e);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h32685b93);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h66570228);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hf0603c4e);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h04a717c1);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h8038b116);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'heb48325e);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hcada992a);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h920bb241);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h5aee4afe);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'he2a37e87);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hb35b9519);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hb335775d);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h989553e9);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h1326f46e);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h2cdf6b7b);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h84aabfa9);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hef24c600);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hb56872ad);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h5edb9041);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'he8ecd7f8);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h535133fb);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hdefc92c7);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h42384226);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h7d40e5f5);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hc91bd745);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h9578e460);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hfc858374);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h3172bed3);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h73b6957c);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'hc0d6a68e);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h33156a61);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h0001ffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hffffffff);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00303130);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h0d060960);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h86480165);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h03040201);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h05000420);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h8e36fc9a);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'ha31724c3);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h2416263c);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h0366a175);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hfabbb92b);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h741ca649);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h6107074d);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h0343b597);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hd075ec0a);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h95048ef8);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hcaa69073);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h8d9d58e9);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h1764b437);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h50b58cad);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h8a6e3199);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h135f80ee);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h84eb2bde);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h58d38ee3);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h5825e91e);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hafdeb1ba);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'ha15a160b);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h0057c47c);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hc7765e31);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h868a3e15);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h5ee57cef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hb008c4dd);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h6a0a89ee);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h98a4ee9c);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h971a07de);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h61e5b0d3);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hcf70e1cd);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hc6a0de5b);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h451f2fb9);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hdb995196);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h9f2f884b);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h4b09749a);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'he6c4ddbe);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h7ee61f79);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h265c6adf);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hb16b3015);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000021);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000021);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h06339a64, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h367db02a, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf41158cc, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h95e76049, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4519c165, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h111184be, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'he41d8ee2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2ae5f5d1, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h1da7f962, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hac93ac88, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h915eee13, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha3350c22, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hf0dfa62e, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hfdfc2b62, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h29f26e27, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hbebdc84e, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h4746df79, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h7b387ad2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h13423c9f, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h98e8a146, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hff486b6c, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h1a85414e, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h73117121, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hb700e547, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hab4e07b2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h21b988b8, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h24dd77c2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h046b0a20, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hcddb986a, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hac75c2f2, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hb044ed59, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hea565879, read_data);
if (success !== 1)
begin
$display("*** ERROR: rob_dec_1024 was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** rob_dec_1024 success.");
end
endtask // rob_dec_1024
//----------------------------------------------------------------
// rob_enc_1024()
//
// Task that tests modexp with 1024 bit encipher/verify with
// real RSA key operands.
//----------------------------------------------------------------
task rob_enc_1024();
reg [31 : 0] read_data;
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Encipher/Verify Test with Rob 1024 bit operands.");
write_word({GENERAL_PREFIX, ADDR_EXPONENT_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_DATA}, 32'h00010001);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h06339a64);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h367db02a);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hf41158cc);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h95e76049);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h4519c165);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h111184be);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'he41d8ee2);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h2ae5f5d1);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h1da7f962);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hac93ac88);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h915eee13);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'ha3350c22);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hf0dfa62e);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hfdfc2b62);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h29f26e27);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hbebdc84e);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h4746df79);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h7b387ad2);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h13423c9f);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h98e8a146);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hff486b6c);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h1a85414e);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h73117121);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb700e547);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hab4e07b2);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h21b988b8);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h24dd77c2);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'h046b0a20);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hcddb986a);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hac75c2f2);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hb044ed59);
write_word({GENERAL_PREFIX, ADDR_MESSAGE_DATA}, 32'hea565879);
write_word({GENERAL_PREFIX, ADDR_MODULUS_PTR_RST}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h00000000);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hd075ec0a);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h95048ef8);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hcaa69073);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h8d9d58e9);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h1764b437);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h50b58cad);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h8a6e3199);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h135f80ee);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h84eb2bde);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h58d38ee3);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h5825e91e);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hafdeb1ba);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'ha15a160b);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h0057c47c);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hc7765e31);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h868a3e15);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h5ee57cef);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hb008c4dd);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h6a0a89ee);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h98a4ee9c);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h971a07de);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h61e5b0d3);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hcf70e1cd);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hc6a0de5b);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h451f2fb9);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hdb995196);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h9f2f884b);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h4b09749a);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'he6c4ddbe);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h7ee61f79);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'h265c6adf);
write_word({GENERAL_PREFIX, ADDR_MODULUS_DATA}, 32'hb16b3015);
write_word({GENERAL_PREFIX, ADDR_EXPONENT_LENGTH}, 32'h00000021);
write_word({GENERAL_PREFIX, ADDR_MODULUS_LENGTH}, 32'h00000021);
start_test_cycle_ctr();
// Start processing and wait for ready.
write_word({GENERAL_PREFIX, ADDR_CTRL}, 32'h00000001);
wait_ready();
stop_test_cycle_ctr();
write_word({GENERAL_PREFIX, ADDR_RESULT_PTR_RST}, 32'h00000000);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00000000, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0001ffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hffffffff, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h00303130, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0d060960, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h86480165, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h03040201, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h05000420, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h8e36fc9a, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'ha31724c3, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h2416263c, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0366a175, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'hfabbb92b, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h741ca649, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h6107074d, read_data);
read_word({GENERAL_PREFIX, ADDR_RESULT_DATA}); read_data = tb_read_data; success = success & assertEquals(32'h0343b597, read_data);
if (success !== 1)
begin
$display("*** ERROR: rob_enc_1024 was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** rob_enc_1024 success.");
end
endtask // rob_enc_1024
//----------------------------------------------------------------
// main
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : main
$display(" -= Testbench for modexp started =-");
$display(" =================================");
$display("");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
// tc1();
// tc2();
// tc3();
// autogenerated_BASIC_33bit();
// autogenerated_BASIC_128bit();
// e64bit_64bit_modulus();
// e65537_64bit_modulus();
// e65537_64bit_modulus_elength();
// e65537_128bit_modulus();
// e65537_256bit_modulus();
// e65537_1024bit_modulus();
// e65537_1536bit_modulus();
// e65537_1664bit_modulus();
e65537_2048bit_modulus();
// rob_dec_1024();
// rob_enc_1024();
display_test_results();
$display("");
$display("*** modexp simulation done. ***");
$finish;
end // main
endmodule // tb_modexp
//======================================================================
// EOF tb_modexp.v
//======================================================================
|
//------------------------------------------------------------------
// Simulator directives.
//------------------------------------------------------------------
`timescale 1ns/100ps
//------------------------------------------------------------------
// Test module.
//------------------------------------------------------------------
module tb_top();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// Debug output control.
parameter DEBUG = 0;
parameter VCD = 1;
// Clock defines.
localparam CLK_HALF_PERIOD = 1;
localparam CLK_PERIOD = 2 * CLK_HALF_PERIOD;
// Address defines
localparam OPERAND_WIDTH = 32;
localparam ADDRESS_WIDTH = 8;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_CYCLES_HIGH = 8'h10;
localparam ADDR_CYCLES_LOW = 8'h11;
localparam ADDR_MODULUS_LENGTH = 8'h20;
localparam ADDR_EXPONENT_LENGTH = 8'h21;
localparam ADDR_MODULUS_PTR_RST = 8'h30;
localparam ADDR_MODULUS_DATA = 8'h31;
localparam ADDR_EXPONENT_PTR_RST = 8'h40;
localparam ADDR_EXPONENT_DATA = 8'h41;
localparam ADDR_MESSAGE_PTR_RST = 8'h50;
localparam ADDR_MESSAGE_DATA = 8'h51;
localparam ADDR_RESULT_PTR_RST = 8'h60;
localparam ADDR_RESULT_DATA = 8'h61;
localparam DEFAULT_MODLENGTH = 8'h80; // 2048 bits.
localparam DEFAULT_EXPLENGTH = 8'h80;
localparam CORE_NAME0 = 32'h6d6f6465; // "mode"
localparam CORE_NAME1 = 32'h78702020; // "xp "
localparam CORE_VERSION = 32'h302e3532; // "0.52"
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg [127 : 0] result_data;
reg tb_clk;
reg tb_reset;
reg tb_cs;
reg tb_we;
reg [31 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
wire tb_error;
reg tb_cyc;
reg [3 : 0] tb_sel;
wire tb_ack;
wire tb_err;
wire tb_int;
reg [31 : 0] pmsg [63 : 0];
reg [31 : 0] cmsg [63 : 0];
reg [31 : 0] gmsg [63 : 0];
integer f1;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
modexp_top dut(
.wb_adr_i(tb_address),
.wb_cyc_i(tb_cyc),//
.wb_dat_i(tb_write_data),
.wb_sel_i(tb_sel),//
.wb_stb_i(tb_cs),
.wb_we_i(tb_we),
.wb_ack_o(tb_ack),//
.wb_err_o(tb_err),//
.wb_dat_o(tb_read_data),
.wb_clk_i(tb_clk),
.wb_rst_i(tb_reset),
.int_o(tb_int)//
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut();
begin
$display("*** Toggle reset.");
tb_reset = 1;
#(2 * CLK_PERIOD);
tb_reset = 0;
$display("");
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim();
begin
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset = 0;
tb_cs = 0;
tb_we = 0;
tb_address = 32'h00000000;
tb_write_data = 32'h00000000;
end
endtask // init_sim
//----------------------------------------------------------------
// read_word()
//
// Read a data word from the given address in the DUT.
//----------------------------------------------------------------
task read_word(input [7 : 0] address);
begin
tb_address = {22'b0,address,2'b0};
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
tb_cs = 0;
if (DEBUG)
begin
$display("*** (read_word) Reading 0x%08x from 0x%02x.", tb_read_data, address);
$display("");
end
end
endtask // read_word
//----------------------------------------------------------------
// write_word()
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [ 7 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
begin
$display("*** (write_word) Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
tb_address = {22'b0,address,2'b0};
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask // write_word
//----------------------------------------------------------------
// wait_ready()
//
// Wait until the ready flag in the core is set.
//----------------------------------------------------------------
task wait_ready();
begin
while (tb_read_data != 32'h00000001)
read_word(8'h09);
if (DEBUG)
$display("*** (wait_ready) Ready flag has been set.");
end
endtask // wait_ready
//----------------------------------------------------------------
// assertEquals
//----------------------------------------------------------------
function assertEquals(
input [31:0] expected,
input [31:0] actual
);
begin
if (expected === actual)
begin
assertEquals = 1; // success
end
else
begin
$display("*** Expected: 0x%08x, got 0x%08x", expected, actual);
assertEquals = 0; // failure
end
end
endfunction // assertEquals
//----------------------------------------------------------------
// assertSuccess
//----------------------------------------------------------------
task assertSuccess(input success);
begin
if (success !== 1)
begin
$display("*** Test -> FAILED");
error_ctr = error_ctr + 1;
end
else
$display("*** Test -> passed");
end
endtask // assertSuccess
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results();
begin
$display("");
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// exp32bit_mod2048bit_test
//----------------------------------------------------------------
task exp32bit_mod2048bit_test();
integer i;
integer success;
reg [31 : 0] read_data;
reg [31 : 0] exp [63 : 0];
reg [31 : 0] mod [63 : 0];
reg [31 : 0] msg [63 : 0];
reg [31 : 0] res [63 : 0];
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("");
$display("Test with e = 65537 and 2048 bit modulus -- Encrypting");
$readmemh("./gen/exp", exp);
$readmemh("./gen/mod", mod);
$readmemh("./gen/msg", msg);
$readmemh("./gen/res", res);
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
write_word(ADDR_EXPONENT_DATA , exp[0]);
write_word(ADDR_MODULUS_PTR_RST, 32'h00000000);
write_word(ADDR_MODULUS_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MODULUS_DATA, mod[i]);
if(DEBUG) $display("writing: %d -> %h", i, mod[i]);
end
write_word(ADDR_MESSAGE_PTR_RST, 32'h00000000);
write_word(ADDR_MESSAGE_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MESSAGE_DATA, msg[i]);
if(DEBUG) $display("Writing: %d -> %h", i, msg[i]);
end
write_word(ADDR_EXPONENT_LENGTH, 32'h00000001);
write_word(ADDR_MODULUS_LENGTH , 32'h00000041);
// Start processing and wait for ready.
write_word(ADDR_CTRL, 32'h00000001);
wait_ready();
write_word(ADDR_RESULT_PTR_RST, 32'h00000000);
read_word(ADDR_RESULT_DATA); read_data=tb_read_data;
success=success&assertEquals(32'h00000000, read_data);
for(i=0; i<64; i=i+1) begin
read_word(ADDR_RESULT_DATA);
read_data=tb_read_data;
success=success&assertEquals(res[i], read_data);
if(DEBUG) $display("Reading: %d -> %h -> %h", i, res[i], read_data);
end
if (success !== 1)
begin
$display("*** ERROR: e65537_2048bit_modulus was NOT successful.");
error_ctr = error_ctr + 1;
end
else
$display("*** e65537_2048bit_modulus success.");
end
endtask // exp32bit_mod2048bit_test
//----------------------------------------------------------------
// modexp_encrypt
//----------------------------------------------------------------
task modexp_encrypt();
integer i;
integer success;
reg [31 : 0] pubexp [1];
reg [31 : 0] pubmod [63 : 0];
begin
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("");
$display("Encrypting -- exp = 65537 and 2048 bit mod");
$readmemh("./gen/pTextHEX", pmsg);
$readmemh("./gen/exponent", pubexp);
$readmemh("./gen/modulus", pubmod);
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
write_word(ADDR_EXPONENT_DATA , pubexp[0]);
if(DEBUG) $display("Writing EXP: %d %h", pubexp[0], pubexp[0]);
write_word(ADDR_MODULUS_PTR_RST, 32'h00000000);
write_word(ADDR_MODULUS_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MODULUS_DATA, pubmod[i]);
if(DEBUG) $display("Writing MOD: %d -> %h", i, pubmod[i]);
end
write_word(ADDR_MESSAGE_PTR_RST, 32'h00000000);
write_word(ADDR_MESSAGE_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MESSAGE_DATA, pmsg[i]);
if(DEBUG) $display("Writing MSG: %d -> %h", i, pmsg[i]);
end
write_word(ADDR_EXPONENT_LENGTH, 32'h00000001);
write_word(ADDR_MODULUS_LENGTH , 32'h00000041);
// Start processing and wait for ready.
write_word(ADDR_CTRL, 32'h00000001);
wait_ready();
write_word(ADDR_RESULT_PTR_RST, 32'h00000000);
read_word(ADDR_RESULT_DATA); cmsg[0]=tb_read_data;
//success=success&assertEquals(32'h00000000, cmsg[0]);
f1 = $fopen("./gen/cTextHEX", "w");
for(i=0; i<64; i=i+1) begin
read_word(ADDR_RESULT_DATA);
cmsg[i]=tb_read_data;
if(DEBUG) $display("Reading: %d -> %h ", i, cmsg[i]);
$fwrite(f1, "%h\n",cmsg[i]);
end
$fclose(f1);
assertSuccess(success);
end
endtask // modexp_encrypt
//----------------------------------------------------------------
// modexp_decrypt
//----------------------------------------------------------------
task modexp_decrypt();
integer i;
integer success;
reg [31 : 0] rdata;
reg [31 : 0] read_data;
reg [31 : 0] priexp [63 : 0];
reg [31 : 0] primod [63 : 0];
begin
$display("");
$display("*** Running -> modexp_decrypt()");
$readmemh("./gen/priExponent", priexp);
$readmemh("./gen/priModulus", primod);
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("Decrypting -- 2048 bit exp and 2048 bit mod");
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
write_word(ADDR_EXPONENT_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_EXPONENT_DATA, priexp[i]);
if(DEBUG) $display("Writing EXP: %d -> %h", i, priexp[i]);
end
write_word(ADDR_MODULUS_PTR_RST, 32'h00000000);
write_word(ADDR_MODULUS_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MODULUS_DATA, primod[i]);
if(DEBUG) $display("Writing MOD: %d -> %h", i, primod[i]);
end
write_word(ADDR_MESSAGE_PTR_RST, 32'h00000000);
write_word(ADDR_MESSAGE_DATA , 32'h00000000);
for(i=0; i<64; i=i+1) begin
write_word(ADDR_MESSAGE_DATA, cmsg[i]);
if(DEBUG) $display("Writing MSG: %d -> %h", i, cmsg[i]);
end
write_word(ADDR_EXPONENT_LENGTH, 32'h00000041);
write_word(ADDR_MODULUS_LENGTH , 32'h00000041);
// Start processing and wait for ready.
write_word(ADDR_CTRL, 32'h00000001);
wait_ready();
write_word(ADDR_RESULT_PTR_RST, 32'h00000000);
read_word(ADDR_RESULT_DATA); rdata=tb_read_data;
success=success&assertEquals(32'h00000000, rdata);
f1 = $fopen("./gen/gTextHEX", "w");
for(i=0; i<64; i=i+1) begin
read_word(ADDR_RESULT_DATA);
rdata=tb_read_data;
if(DEBUG) $display("Reading: %d -> %h ", i, rdata);
$fwrite(f1, "%h\n",rdata);
success=success&assertEquals(pmsg[i], rdata);
end
$fclose(f1);
assertSuccess(success);
end
endtask // modexp_decrypt
//----------------------------------------------------------------
// modexp_32bits
//----------------------------------------------------------------
task modexp_32bits(input [31:0] Wmsg,
input [31:0] Wexp,
input [31:0] Wmod,
input [31:0] Wres);
reg [31 : 0] Rmsg;
reg [31 : 0] Rexp;
reg [31 : 0] Rmod;
reg [31 : 0] Rres;
integer success;
begin
$display("");
$display("*** Running -> modexp_32bits()");
success = 32'h1;
tc_ctr = tc_ctr + 1;
$display("*** Writing -> MES: %h EXP: %h MOD: %h", Wmsg, Wexp, Wmod);
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
write_word(ADDR_EXPONENT_DATA , Wexp);
write_word(ADDR_MODULUS_PTR_RST , 32'h00000000);
write_word(ADDR_MODULUS_DATA , Wmod);
write_word(ADDR_MESSAGE_PTR_RST , 32'h00000000);
write_word(ADDR_MESSAGE_DATA , Wmsg);
write_word(ADDR_EXPONENT_LENGTH , 32'h00000001);
write_word(ADDR_MODULUS_LENGTH , 32'h00000001);
// Start processing and wait for ready.
write_word(ADDR_CTRL , 32'h00000001);
wait_ready();
write_word(ADDR_MESSAGE_PTR_RST , 32'h00000000);
read_word(ADDR_MESSAGE_DATA);
Rmsg=tb_read_data;
write_word(ADDR_EXPONENT_PTR_RST, 32'h00000000);
read_word(ADDR_EXPONENT_DATA);
Rexp=tb_read_data;
write_word(ADDR_MODULUS_PTR_RST , 32'h00000000);
read_word(ADDR_MODULUS_DATA);
Rmod=tb_read_data;
write_word(ADDR_RESULT_PTR_RST , 32'h00000000);
read_word(ADDR_RESULT_DATA);
Rres=tb_read_data;
$display("*** Reading -> MES: %h EXP: %h MOD: %h RES: %h", Rmsg, Rexp, Rmod, Rres);
success=success&assertEquals(Wres, Rres);
assertSuccess(success);
end
endtask // modexp_32bits
//----------------------------------------------------------------
// main
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : main
if(VCD) begin
$dumpfile("./iverilog/tb_top.vcd");
$dumpvars(0,tb_top);
//$dumpvars(1,tb_clk, tb_reset, tb_cs, tb_we, tb_address, tb_write_data, tb_read_data);
end
$display(" -= Testbench for modexp started =-");
$display(" =================================");
$display("");
init_sim();
reset_dut();
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000005, 32'h00000001); //msg^exp < mod -> 1^2 < 5
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000003, 32'h00000001); //msg^exp < mod -> 1^2 < 3
modexp_32bits(32'h00000002, 32'h00000002, 32'h00000005, 32'h00000004); //msg^exp < mod -> 2^2 < 5
modexp_32bits(32'h00000002, 32'h00000002, 32'h00000003, 32'h00000001); //msg^exp > mod -> 2^2 > 3
modexp_32bits(32'h00000004, 32'h0000000D, 32'h000001F1, 32'h000001bd); //msg^exp > mod -> 4^13 > 497
modexp_32bits(32'h01234567, 32'h89ABCDEF, 32'h11111111, 32'h0D9EF081); //msg^exp > mod -> 19088743^2309737967 > 286331153
modexp_32bits(32'h30000000, 32'hC0000000, 32'h00A00001, 32'h0000CC3F); //msg^exp > mod -> 805306368^3221225472 > 10485761 <- Passes
//modexp_32bits(32'h30000000, 32'hC0000000, 32'h00A00000, 32'h00600000); //msg^exp > mod -> 805306368^3221225472 > 10485760 <- Fails
//modexp_32bits(32'h00000002, 32'h00000003, 32'h00000001, 32'h00000000); //mod 1 <- FAILS Does not check
/*
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000002, 32'h00000001); //1 mod 2 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000003, 32'h00000001); //1 mod 3 = 1 -> 1 <- passes
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000004, 32'h00000001); //1 mod 4 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000005, 32'h00000001); //1 mod 5 = 1 -> 1 <- passes
modexp_32bits(32'h00000001, 32'h00000002, 32'h00000006, 32'h00000001); //1 mod 6 = 1 -> 4 <- FAILS
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000002, 32'h00000000); //2 mod 2 = 0 -> passes
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000003, 32'h00000002); //2 mod 3 = 2 -> passes
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000004, 32'h00000002); //2 mod 4 = 2 -> 0 <- FAILS
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000005, 32'h00000002); //2 mod 5 = 2 -> passes
modexp_32bits(32'h00000002, 32'h00000001, 32'h00000006, 32'h00000002); //2 mod 6 = 2 -> passes
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000002, 32'h00000001); //3 mod 2 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000003, 32'h00000000); //3 mod 3 = 0 -> 3 <- FAILS
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000004, 32'h00000003); //3 mod 4 = 3 -> 0 <- FAILS
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000005, 32'h00000003); //3 mod 5 = 3 -> passes
modexp_32bits(32'h00000003, 32'h00000001, 32'h00000006, 32'h00000003); //3 mod 6 = 3 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000002, 32'h00000000); //4 mod 2 = 0 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000003, 32'h00000001); //4 mod 3 = 1 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000004, 32'h00000000); //4 mod 4 = 0 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000005, 32'h00000004); //4 mod 5 = 4 -> passes
modexp_32bits(32'h00000004, 32'h00000001, 32'h00000006, 32'h00000004); //4 mod 6 = 4 -> passes
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000002, 32'h00000001); //5 mod 2 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000003, 32'h00000002); //5 mod 3 = 2 -> passes
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000004, 32'h00000001); //5 mod 4 = 1 -> 0 <- FAILS
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000005, 32'h00000000); //5 mod 5 = 0 -> 5 <- FAILS
modexp_32bits(32'h00000005, 32'h00000001, 32'h00000006, 32'h00000005); //5 mod 6 = 5 -> passes
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000002, 32'h00000000); //6 mod 2 = 0 -> passes
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000003, 32'h00000000); //6 mod 3 = 0 -> 3 <- FAILS
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000004, 32'h00000002); //6 mod 4 = 2 -> 0 <- FAILS
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000005, 32'h00000001); //6 mod 5 = 1 -> passes
modexp_32bits(32'h00000006, 32'h00000001, 32'h00000006, 32'h00000000); //6 mod 6 = 0 -> 1 <- FAILS
*/
/*
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000002, 32'h00000000); //8^6 mod 2 = 0 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000003, 32'h00000001); //8^6 mod 3 = 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000004, 32'h00000000); //8^6 mod 4 = 0 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000005, 32'h00000004); //8^6 mod 5 = 4 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000006, 32'h00000004); //8^6 mod 6 = 4 -> 1 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000007, 32'h00000001); //8^6 mod 7 = 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000008, 32'h00000000); //8^6 mod 8 = 0 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000009, 32'h00000001); //8^6 mod 9 = 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000A, 32'h00000004); //8^6 mod 10= 4 -> 9 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000B, 32'h00000003); //8^6 mod 11= 3 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000C, 32'h00000004); //8^6 mod 12= 4 -> 5 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000D, 32'h0000000C); //8^6 mod 13= 12-> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000E, 32'h00000008); //8^6 mod 14= 8 -> 5 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000000F, 32'h00000004); //8^6 mod 15= 4 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000010, 32'h00000000); //8^6 mod 16= 0 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000011, 32'h00000004); //8^6 mod 17= 4 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000012, 32'h0000000A); //8^6 mod 18= 10-> 13<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000013, 32'h00000001); //8^6 mod 19= 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000014, 32'h00000004); //8^6 mod 20= 4 -> 11<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000015, 32'h00000001); //8^6 mod 21= 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000016, 32'h0000000E); //8^6 mod 22= 14-> 1 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000017, 32'h0000000D); //8^6 mod 23= 13-> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000018, 32'h00000010); //8^6 mod 24= 16-> 9 <- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h00000019, 32'h00000013); //8^6 mod 25= 19-> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001A, 32'h0000000C); //8^6 mod 26= 12-> 19<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001B, 32'h00000001); //8^6 mod 27= 1 -> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001C, 32'h00000008); //8^6 mod 28= 8 -> 19<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001D, 32'h0000000D); //8^6 mod 29= 13-> passes
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001E, 32'h00000004); //8^6 mod 30= 4 -> 13<- FAILS
modexp_32bits(32'h00000008, 32'h00000006, 32'h0000001F, 32'h00000008); //8^6 mod 31= 8 -> passes
*/
//exp32bit_mod2048bit_test();
//modexp_encrypt();
//modexp_decrypt();
display_test_results();
$display("");
$display("*** modexp simulation done. ***");
$finish;
end // main
endmodule // tb_modexp
//======================================================================
// EOF tb_modexp.v
//======================================================================
|
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Defines of the Core ////
//// ////
//// Known problems (limits): ////
//// None ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - gorban@opencores.org ////
//// - Jacob Gorban ////
//// - Igor Mohor (igorm@opencores.org) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Timescale define
`timescale 1ns/10ps
|
//======================================================================
//
// adder.v
// -------
// Adder with separate carry in and carry out. Used in the montprod
// amd residue modules of the modexp core.
//
//
// Author: Peter Magnusson, Joachim Strömbergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module adder #(parameter OPW = 32)
(
input [(OPW - 1) : 0] a,
input [(OPW - 1) : 0] b,
input carry_in,
output wire [(OPW - 1) : 0] sum,
output wire carry_out
);
reg [(OPW) : 0] adder_result;
assign sum = adder_result[(OPW - 1) : 0];
assign carry_out = adder_result[(OPW)];
always @*
begin
adder_result = {1'b0, a} + {1'b0, b} + {{OPW{1'b0}}, carry_in};
end
endmodule // adder
//======================================================================
// EOF adder.v
//======================================================================
|
//======================================================================
//
// blockmem1rw1.v
// --------------
// Synchronous block memory with one read and one write port.
// The data size is the same for both read and write operations.
//
// The memory is used in the modexp core.
//
// paremeter OPW is operand word width in bits.
// parameter ADW is address width in bits.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem1r1w #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire [(ADW - 1) : 0] read_addr,
output wire [(OPW - 1) : 0] read_data,
input wire wr,
input wire [(ADW - 1) : 0] write_addr,
input wire [(OPW - 1) : 0] write_data
);
reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data;
assign read_data = tmp_read_data;
always @ (posedge clk)
begin : reg_mem
if (wr)
mem[write_addr] <= write_data;
tmp_read_data <= mem[read_addr];
end
endmodule // blockmem1r1w
//======================================================================
// EOF blockmem1r1w.v
//======================================================================
|
//======================================================================
//
// blockmem2r1w.v
// --------------
// Synchronous block memory with two read ports and one write port.
// The data size is the same for both read and write operations.
//
// The memory is used in the modexp core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem2r1w #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire [(ADW - 1) : 0] read_addr0,
output wire [(OPW - 1) : 0] read_data0,
input wire [(ADW - 1) : 0] read_addr1,
output wire [(OPW - 1) : 0] read_data1,
input wire wr,
input wire [(ADW - 1) : 0] write_addr,
input wire [(OPW - 1) : 0] write_data
);
reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data0;
reg [(OPW - 1) : 0] tmp_read_data1;
assign read_data0 = tmp_read_data0;
assign read_data1 = tmp_read_data1;
always @ (posedge clk)
begin : reg_mem
if (wr)
mem[write_addr] <= write_data;
tmp_read_data0 <= mem[read_addr0];
tmp_read_data1 <= mem[read_addr1];
end
endmodule // blockmem2r1w
//======================================================================
// EOF blockmem2r1w.v
//======================================================================
|
//======================================================================
//
// blockmem2r1wptr.v
// -----------------
// Synchronous block memory with two read ports and one write port.
// For port 1 the address is implicit and instead given by the
// internal pointer. The pointer is automatically increased
// when the cs signal is set. The pointer is reset to zero when
// the rst signal is asserted.
//
//
// NOTE: This memory needs to be rebuilt if interface 0 is changed
// to use bigger operand widths and fewer words than interface 1.
// This adaption is NOT automatic.
//
//
// The memory is used in the modexp core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem2r1wptr #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire reset_n,
input wire [(ADW - 1) : 0] read_addr0,
output wire [(OPW - 1) : 0] read_data0,
output wire [31 : 0] read_data1,
input wire rst,
input wire cs,
input wire wr,
input wire [31 : 0] write_data
);
//----------------------------------------------------------------
// Memories and regs including update variables and write enable.
//----------------------------------------------------------------
reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data0;
reg [31 : 0] tmp_read_data1;
reg [7 : 0] ptr_reg;
reg [7 : 0] ptr_new;
reg ptr_we;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data0 = tmp_read_data0;
assign read_data1 = tmp_read_data1;
//----------------------------------------------------------------
// mem_update
//
// Clocked update of memory This should cause
// the memory to be implemented as a block memory.
//----------------------------------------------------------------
always @ (posedge clk)
begin : mem_update
if (wr)
mem[ptr_reg] <= write_data;
tmp_read_data0 <= mem[read_addr0];
tmp_read_data1 <= mem[ptr_reg];
end
//----------------------------------------------------------------
// ptr_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : ptr_update
if (!reset_n)
ptr_reg <= 8'h00;
else
if (ptr_we)
ptr_reg <= ptr_new;
end
//----------------------------------------------------------------
// ptr_logic
//----------------------------------------------------------------
always @*
begin : ptr_logic
ptr_new = 8'h00;
ptr_we = 1'b0;
if (rst)
begin
ptr_new = 8'h00;
ptr_we = 1'b1;
end
if (cs)
begin
ptr_new = ptr_reg + 1'b1;
ptr_we = 1'b1;
end
end
endmodule // blockmem2r1wptr
//======================================================================
// EOF blockmem2r1wptr.v
//======================================================================
|
//======================================================================
//
// blockmem2r1wptr.v
// -----------------
// Synchronous block memory with two read ports and one write port.
// For port 1 the address is implicit and instead given by the
// internal pointer. But write address is explicitly given.
//
// The memory is used in the modexp core.
//
//
// NOTE: This memory needs to be rebuilt if interface 0 is changed
// to use bigger operand widths and fewer words than interface 1.
// This adaption is NOT automatic.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blockmem2rptr1w #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire reset_n,
input wire [(ADW - 1) : 0] read_addr0,
output wire [(OPW - 1) : 0] read_data0,
output wire [31 : 0] read_data1,
input wire rst,
input wire cs,
input wire wr,
input wire [07 : 0] write_addr,
input wire [31 : 0] write_data
);
//----------------------------------------------------------------
// Memories and regs including update variables and write enable.
//----------------------------------------------------------------
reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data0;
reg [31 : 0] tmp_read_data1;
reg [7 : 0] ptr_reg;
reg [7 : 0] ptr_new;
reg ptr_we;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data0 = tmp_read_data0;
assign read_data1 = tmp_read_data1;
//----------------------------------------------------------------
// mem_update
//
// Clocked update of memory This should cause
// the memory to be implemented as a block memory.
//----------------------------------------------------------------
always @ (posedge clk)
begin : mem_update
if (wr)
mem[write_addr] <= write_data;
tmp_read_data0 <= mem[read_addr0];
tmp_read_data1 <= mem[ptr_reg];
end
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_mem_update
if (!reset_n)
ptr_reg <= 8'h00;
else
if (ptr_we)
ptr_reg <= ptr_new;
end
//----------------------------------------------------------------
// ptr_logic
//----------------------------------------------------------------
always @*
begin : ptr_logic
ptr_new = 8'h00;
ptr_we = 1'b0;
if (rst)
begin
ptr_new = 8'h00;
ptr_we = 1'b1;
end
if (cs)
begin
ptr_new = ptr_reg + 1'b1;
ptr_we = 1'b1;
end
end
endmodule // blockmem2r1wptr
//======================================================================
// EOF blockmem2r1wptr.v
//======================================================================
|
//======================================================================
//
// modexp.v
// --------
// Top level wrapper for the modula exponentiation core. The core
// is used to implement public key algorithms such as RSA,
// DH, ElGamal etc.
//
// The core calculates the following function:
//
// C = M ** e mod N
//
// M is a message with a length of n bits
// e is the exponent with a length of m bits
// N is the modulus with a length of n bits
//
// n can be 32 and up to and including 8192 bits in steps
// of 32 bits.
// m can be one and up to and including 8192 bits in steps
// of 32 bits.
//
// The core has a 32-bit memory like interface, but provides
// status signals to inform the system that a given operation
// has is done. Additionally, any errors will also be asserted.
//
//
// Author: Joachim Strombergson, Peter Magnusson
// Copyright (c) 2015, NORDUnet A/S
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
//======================================================================
module modexp(
input wire clk,
input wire reset_n,
input wire cs,
input wire we,
input wire [ 7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// The operand width is the internal operand width in bits.
// The address width is the size of the address space used. This
// value must be balances with OPERAND_WIDTH to allow a total
// of 8192 bits of data. OPERAND_WIDTH * (ADDRESS_WIDTH ** 2)
// is the formula. Note that the API data with is always 32 bits.
localparam OPERAND_WIDTH = 32;
localparam ADDRESS_WIDTH = 8;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_CYCLES_HIGH = 8'h10;
localparam ADDR_CYCLES_LOW = 8'h11;
localparam ADDR_MODULUS_LENGTH = 8'h20;
localparam ADDR_EXPONENT_LENGTH = 8'h21;
localparam ADDR_MODULUS_PTR_RST = 8'h30;
localparam ADDR_MODULUS_DATA = 8'h31;
localparam ADDR_EXPONENT_PTR_RST = 8'h40;
localparam ADDR_EXPONENT_DATA = 8'h41;
localparam ADDR_MESSAGE_PTR_RST = 8'h50;
localparam ADDR_MESSAGE_DATA = 8'h51;
localparam ADDR_RESULT_PTR_RST = 8'h60;
localparam ADDR_RESULT_DATA = 8'h61;
localparam DEFAULT_MODLENGTH = 8'h80; // 2048 bits.
localparam DEFAULT_EXPLENGTH = 8'h80;
localparam CORE_NAME0 = 32'h6d6f6465; // "mode"
localparam CORE_NAME1 = 32'h78702020; // "xp "
localparam CORE_VERSION = 32'h302e3532; // "0.52"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [07 : 0] exponent_length_reg;
reg [07 : 0] exponent_length_new;
reg exponent_length_we;
reg [07 : 0] modulus_length_reg;
reg [07 : 0] modulus_length_new;
reg modulus_length_we;
reg start_reg;
reg start_new;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg exponent_mem_api_rst;
reg exponent_mem_api_cs;
reg exponent_mem_api_wr;
wire [31 : 0] exponent_mem_api_read_data;
reg modulus_mem_api_rst;
reg modulus_mem_api_cs;
reg modulus_mem_api_wr;
wire [31 : 0] modulus_mem_api_read_data;
reg message_mem_api_rst;
reg message_mem_api_cs;
reg message_mem_api_wr;
wire [31 : 0] message_mem_api_read_data;
reg result_mem_api_rst;
reg result_mem_api_cs;
wire [31 : 0] result_mem_api_read_data;
wire ready;
wire [63 : 0] cycles;
reg [31 : 0] tmp_read_data;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
modexp_core #(.OPW(OPERAND_WIDTH), .ADW(ADDRESS_WIDTH))
core_inst(
.clk(clk),
.reset_n(reset_n),
.start(start_reg),
.ready(ready),
.exponent_length(exponent_length_reg),
.modulus_length(modulus_length_reg),
.cycles(cycles),
.exponent_mem_api_cs(exponent_mem_api_cs),
.exponent_mem_api_wr(exponent_mem_api_wr),
.exponent_mem_api_rst(exponent_mem_api_rst),
.exponent_mem_api_write_data(write_data),
.exponent_mem_api_read_data(exponent_mem_api_read_data),
.modulus_mem_api_cs(modulus_mem_api_cs),
.modulus_mem_api_wr(modulus_mem_api_wr),
.modulus_mem_api_rst(modulus_mem_api_rst),
.modulus_mem_api_write_data(write_data),
.modulus_mem_api_read_data(modulus_mem_api_read_data),
.message_mem_api_cs(message_mem_api_cs),
.message_mem_api_wr(message_mem_api_wr),
.message_mem_api_rst(message_mem_api_rst),
.message_mem_api_write_data(write_data),
.message_mem_api_read_data(message_mem_api_read_data),
.result_mem_api_cs(result_mem_api_cs),
.result_mem_api_rst(result_mem_api_rst),
.result_mem_api_read_data(result_mem_api_read_data)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
start_reg <= 1'b0;
exponent_length_reg <= DEFAULT_EXPLENGTH;
modulus_length_reg <= DEFAULT_MODLENGTH;
end
else
begin
start_reg <= start_new;
if (exponent_length_we)
begin
exponent_length_reg <= write_data[7 : 0];
end
if (modulus_length_we)
begin
modulus_length_reg <= write_data[7 : 0];
end
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
modulus_length_we = 1'b0;
exponent_length_we = 1'b0;
start_new = 1'b0;
modulus_mem_api_rst = 1'b0;
modulus_mem_api_cs = 1'b0;
modulus_mem_api_wr = 1'b0;
exponent_mem_api_rst = 1'b0;
exponent_mem_api_cs = 1'b0;
exponent_mem_api_wr = 1'b0;
message_mem_api_rst = 1'b0;
message_mem_api_cs = 1'b0;
message_mem_api_wr = 1'b0;
result_mem_api_rst = 1'b0;
result_mem_api_cs = 1'b0;
tmp_read_data = 32'h00000000;
if (cs)
begin
if (we)
begin
case (address)
ADDR_CTRL:
begin
start_new = write_data[0];
end
ADDR_MODULUS_LENGTH:
begin
modulus_length_we = 1'b1;
end
ADDR_EXPONENT_LENGTH:
begin
exponent_length_we = 1'b1;
end
ADDR_MODULUS_PTR_RST:
begin
modulus_mem_api_rst = 1'b1;
end
ADDR_MODULUS_DATA:
begin
modulus_mem_api_cs = 1'b1;
modulus_mem_api_wr = 1'b1;
end
ADDR_EXPONENT_PTR_RST:
begin
exponent_mem_api_rst = 1'b1;
end
ADDR_EXPONENT_DATA:
begin
exponent_mem_api_cs = 1'b1;
exponent_mem_api_wr = 1'b1;
end
ADDR_MESSAGE_PTR_RST:
begin
message_mem_api_rst = 1'b1;
end
ADDR_MESSAGE_DATA:
begin
message_mem_api_cs = 1'b1;
message_mem_api_wr = 1'b1;
end
ADDR_RESULT_PTR_RST:
begin
result_mem_api_rst = 1'b1;
end
default:
begin
end
endcase // case (address[7 : 0])
end // if (we)
else
begin
case (address)
ADDR_NAME0:
tmp_read_data = CORE_NAME0;
ADDR_NAME1:
tmp_read_data = CORE_NAME1;
ADDR_VERSION:
tmp_read_data = CORE_VERSION;
ADDR_CTRL:
tmp_read_data = {31'h00000000, start_reg};
ADDR_STATUS:
tmp_read_data = {31'h00000000, ready};
ADDR_CYCLES_HIGH:
tmp_read_data = cycles[63 : 32];
ADDR_CYCLES_LOW:
tmp_read_data = cycles[31 : 0];
ADDR_MODULUS_LENGTH:
tmp_read_data = {24'h000000, modulus_length_reg};
ADDR_EXPONENT_LENGTH:
tmp_read_data = {24'h000000, exponent_length_reg};
ADDR_MODULUS_DATA:
begin
modulus_mem_api_cs = 1'b1;
tmp_read_data = modulus_mem_api_read_data;
end
ADDR_EXPONENT_DATA:
begin
exponent_mem_api_cs = 1'b1;
tmp_read_data = exponent_mem_api_read_data;
end
ADDR_MESSAGE_DATA:
begin
message_mem_api_cs = 1'b1;
tmp_read_data = message_mem_api_read_data;
end
ADDR_RESULT_DATA:
begin
result_mem_api_cs = 1'b1;
tmp_read_data = result_mem_api_read_data;
end
default:
begin
end
endcase // case (address)
end // else: !if(we)
end // if (cs)
end // block: api
endmodule // modexp
//======================================================================
// EOF modexp.v
//======================================================================
|
//======================================================================
//
// modexp_core.v
// -------------
// Modular exponentiation core for implementing public key algorithms
// such as RSA, DH, ElGamal etc.
//
// The core calculates the following function:
//
// C = M ** e mod N
//
// M is a message with a length of n bits
// e is the exponent with a length of m bits
// N is the modulus with a length of n bits
//
// n can be 32 and up to and including 8192 bits in steps
// of 32 bits.
// m can be one and up to and including 8192 bits in steps
// of 32 bits.
//
// The core has access ports for the exponent, modulus, message and
// result memories.
//
//
// Author: Joachim Strombergson, Peter Magnusson
// Copyright (c) 2015, NORDUnet A/S
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
//======================================================================
module modexp_core #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire reset_n,
input wire start,
output wire ready,
input wire [07 : 0] exponent_length,
input wire [07 : 0] modulus_length,
output wire [63 : 0] cycles,
input wire exponent_mem_api_cs,
input wire exponent_mem_api_wr,
input wire exponent_mem_api_rst,
input wire [31 : 0] exponent_mem_api_write_data,
output wire [31 : 0] exponent_mem_api_read_data,
input wire modulus_mem_api_cs,
input wire modulus_mem_api_wr,
input wire modulus_mem_api_rst,
input wire [31 : 0] modulus_mem_api_write_data,
output wire [31 : 0] modulus_mem_api_read_data,
input wire message_mem_api_cs,
input wire message_mem_api_wr,
input wire message_mem_api_rst,
input wire [31 : 0] message_mem_api_write_data,
output wire [31 : 0] message_mem_api_read_data,
input wire result_mem_api_cs,
input wire result_mem_api_rst,
output wire [31 : 0] result_mem_api_read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam MONTPROD_SELECT_ONE_NR = 3'h0;
localparam MONTPROD_SELECT_X_NR = 3'h1;
localparam MONTPROD_SELECT_Z_P = 3'h2;
localparam MONTPROD_SELECT_P_P = 3'h3;
localparam MONTPROD_SELECT_Z_ONE = 3'h4;
localparam MONTPROD_DEST_Z = 2'b00;
localparam MONTPROD_DEST_P = 2'b01;
localparam MONTPROD_DEST_NOWHERE = 2'b10;
localparam CTRL_IDLE = 4'h0;
localparam CTRL_RESIDUE = 4'h1;
localparam CTRL_CALCULATE_Z0 = 4'h2;
localparam CTRL_CALCULATE_P0 = 4'h3;
localparam CTRL_ITERATE = 4'h4;
localparam CTRL_ITERATE_Z_P = 4'h5;
localparam CTRL_ITERATE_P_P = 4'h6;
localparam CTRL_ITERATE_END = 4'h7;
localparam CTRL_CALCULATE_ZN = 4'h8;
localparam CTRL_DONE = 4'h9;
//for rsa, c=M^65537 etc, there is no need to slow down to hide the exponent
localparam EXPONATION_MODE_SECRET_SECURE = 1'b0;
localparam EXPONATION_MODE_PUBLIC_FAST = 1'b1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg ready_reg;
reg ready_new;
reg ready_we;
reg [2 : 0] montprod_select_reg;
reg [2 : 0] montprod_select_new;
reg montprod_select_we;
reg [1 : 0] montprod_dest_reg;
reg [1 : 0] montprod_dest_new;
reg montprod_dest_we;
reg [3 : 0] modexp_ctrl_reg;
reg [3 : 0] modexp_ctrl_new;
reg modexp_ctrl_we;
reg [31 : 0] one_reg;
reg [31 : 0] one_new;
reg [31 : 0] b_one_reg;
reg [31 : 0] b_one_new;
reg [12 : 0] loop_counter_reg;
reg [12 : 0] loop_counter_new;
reg loop_counter_we;
reg [07 : 0] E_word_index;
reg [04 : 0] E_bit_index;
reg last_iteration;
reg ei_reg;
reg ei_new;
reg ei_we;
reg exponation_mode_reg;
reg exponation_mode_new;
reg exponation_mode_we;
reg [31 : 0] cycle_ctr_low_reg;
reg [31 : 0] cycle_ctr_low_new;
reg cycle_ctr_low_we;
reg [31 : 0] cycle_ctr_high_reg;
reg [31 : 0] cycle_ctr_high_new;
reg cycle_ctr_high_we;
reg cycle_ctr_state_reg;
reg cycle_ctr_state_new;
reg cycle_ctr_state_we;
reg cycle_ctr_start;
reg cycle_ctr_stop;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [07 : 0] modulus_mem_int_rd_addr;
wire [31 : 0] modulus_mem_int_rd_data;
reg [07 : 0] message_mem_int_rd_addr;
wire [31 : 0] message_mem_int_rd_data;
reg [07 : 0] exponent_mem_int_rd_addr;
wire [31 : 0] exponent_mem_int_rd_data;
reg [07 : 0] result_mem_int_rd_addr;
wire [31 : 0] result_mem_int_rd_data;
reg [07 : 0] result_mem_int_wr_addr;
reg [31 : 0] result_mem_int_wr_data;
reg result_mem_int_we;
reg [07 : 0] p_mem_rd0_addr;
wire [31 : 0] p_mem_rd0_data;
reg [07 : 0] p_mem_rd1_addr;
wire [31 : 0] p_mem_rd1_data;
reg [07 : 0] p_mem_wr_addr;
reg [31 : 0] p_mem_wr_data;
reg p_mem_we;
reg [31 : 0] tmp_read_data;
reg montprod_calc;
wire montprod_ready;
reg [07 : 0] montprod_length;
wire [07 : 0] montprod_opa_addr;
reg [31 : 0] montprod_opa_data;
wire [07 : 0] montprod_opb_addr;
reg [31 : 0] montprod_opb_data;
wire [07 : 0] montprod_opm_addr;
reg [31 : 0] montprod_opm_data;
wire [07 : 0] montprod_result_addr;
wire [31 : 0] montprod_result_data;
wire montprod_result_we;
reg residue_calculate;
wire residue_ready;
reg [14 : 0] residue_nn;
reg [07 : 0] residue_length;
wire [07 : 0] residue_opa_rd_addr;
wire [31 : 0] residue_opa_rd_data;
wire [07 : 0] residue_opa_wr_addr;
wire [31 : 0] residue_opa_wr_data;
wire residue_opa_wr_we;
wire [07 : 0] residue_opm_addr;
reg [31 : 0] residue_opm_data;
reg [07 : 0] residue_mem_montprod_read_addr;
wire [31 : 0] residue_mem_montprod_read_data;
reg residue_valid_reg;
reg residue_valid_new;
reg residue_valid_int_validated;
wire [7 : 0] modulus_length_m1;
wire [7 : 0] exponent_length_m1;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_reg;
assign cycles = {cycle_ctr_high_reg, cycle_ctr_low_reg};
assign modulus_length_m1 = modulus_length - 8'h1;
assign exponent_length_m1 = exponent_length - 8'h1;
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
montprod #(.OPW(OPW), .ADW(ADW))
montprod_inst(
.clk(clk),
.reset_n(reset_n),
.calculate(montprod_calc),
.ready(montprod_ready),
.length(montprod_length),
.opa_addr(montprod_opa_addr),
.opa_data(montprod_opa_data),
.opb_addr(montprod_opb_addr),
.opb_data(montprod_opb_data),
.opm_addr(montprod_opm_addr),
.opm_data(montprod_opm_data),
.result_addr(montprod_result_addr),
.result_data(montprod_result_data),
.result_we(montprod_result_we)
);
residue #(.OPW(OPW), .ADW(ADW))
residue_inst(
.clk(clk),
.reset_n(reset_n),
.calculate(residue_calculate),
.ready(residue_ready),
.nn(residue_nn),
.length(residue_length),
.opa_rd_addr(residue_opa_rd_addr),
.opa_rd_data(residue_opa_rd_data),
.opa_wr_addr(residue_opa_wr_addr),
.opa_wr_data(residue_opa_wr_data),
.opa_wr_we(residue_opa_wr_we),
.opm_addr(residue_opm_addr),
.opm_data(residue_opm_data)
);
blockmem2r1w #(.OPW(OPW), .ADW(ADW))
residue_mem(
.clk(clk),
.read_addr0(residue_opa_rd_addr),
.read_data0(residue_opa_rd_data),
.read_addr1(residue_mem_montprod_read_addr),
.read_data1(residue_mem_montprod_read_data),
.wr(residue_opa_wr_we),
.write_addr(residue_opa_wr_addr),
.write_data(residue_opa_wr_data)
);
blockmem2r1w #(.OPW(OPW), .ADW(ADW))
p_mem(
.clk(clk),
.read_addr0(p_mem_rd0_addr),
.read_data0(p_mem_rd0_data),
.read_addr1(p_mem_rd1_addr),
.read_data1(p_mem_rd1_data),
.wr(p_mem_we),
.write_addr(p_mem_wr_addr),
.write_data(p_mem_wr_data)
);
blockmem2r1wptr #(.OPW(OPW), .ADW(ADW))
exponent_mem(
.clk(clk),
.reset_n(reset_n),
.read_addr0(exponent_mem_int_rd_addr),
.read_data0(exponent_mem_int_rd_data),
.read_data1(exponent_mem_api_read_data),
.rst(exponent_mem_api_rst),
.cs(exponent_mem_api_cs),
.wr(exponent_mem_api_wr),
.write_data(exponent_mem_api_write_data)
);
blockmem2r1wptr #(.OPW(OPW), .ADW(ADW))
modulus_mem(
.clk(clk),
.reset_n(reset_n),
.read_addr0(modulus_mem_int_rd_addr),
.read_data0(modulus_mem_int_rd_data),
.read_data1(modulus_mem_api_read_data),
.rst(modulus_mem_api_rst),
.cs(modulus_mem_api_cs),
.wr(modulus_mem_api_wr),
.write_data(modulus_mem_api_write_data)
);
blockmem2r1wptr #(.OPW(OPW), .ADW(ADW))
message_mem(
.clk(clk),
.reset_n(reset_n),
.read_addr0(message_mem_int_rd_addr),
.read_data0(message_mem_int_rd_data),
.read_data1(message_mem_api_read_data),
.rst(message_mem_api_rst),
.cs(message_mem_api_cs),
.wr(message_mem_api_wr),
.write_data(message_mem_api_write_data)
);
blockmem2rptr1w #(.OPW(OPW), .ADW(ADW))
result_mem(
.clk(clk),
.reset_n(reset_n),
.read_addr0(result_mem_int_rd_addr[7 : 0]),
.read_data0(result_mem_int_rd_data),
.read_data1(result_mem_api_read_data),
.rst(result_mem_api_rst),
.cs(result_mem_api_cs),
.wr(result_mem_int_we),
.write_addr(result_mem_int_wr_addr),
.write_data(result_mem_int_wr_data)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
ready_reg <= 1'b1;
montprod_select_reg <= MONTPROD_SELECT_ONE_NR;
montprod_dest_reg <= MONTPROD_DEST_NOWHERE;
modexp_ctrl_reg <= CTRL_IDLE;
one_reg <= 32'h0;
b_one_reg <= 32'h0;
loop_counter_reg <= 13'b0;
ei_reg <= 1'b0;
residue_valid_reg <= 1'b0;
exponation_mode_reg <= EXPONATION_MODE_SECRET_SECURE;
cycle_ctr_low_reg <= 32'h00000000;
cycle_ctr_high_reg <= 32'h00000000;
cycle_ctr_state_reg <= 1'b0;
end
else
begin
one_reg <= one_new;
b_one_reg <= b_one_new;
residue_valid_reg <= residue_valid_new;
if (ready_we)
ready_reg <= ready_new;
if (montprod_select_we)
montprod_select_reg <= montprod_select_new;
if (montprod_dest_we)
montprod_dest_reg <= montprod_dest_new;
if (loop_counter_we)
loop_counter_reg <= loop_counter_new;
if (ei_we)
ei_reg <= ei_new;
if (exponation_mode_we)
exponation_mode_reg <= exponation_mode_new;
if (cycle_ctr_low_we)
cycle_ctr_low_reg <= cycle_ctr_low_new;
if (cycle_ctr_high_we)
cycle_ctr_high_reg <= cycle_ctr_high_new;
if (cycle_ctr_state_we)
cycle_ctr_state_reg <= cycle_ctr_state_new;
if (modexp_ctrl_we)
modexp_ctrl_reg <= modexp_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// cycle_ctr
//
// Implementation of the cycle counter
//----------------------------------------------------------------
always @*
begin : cycle_ctr
cycle_ctr_low_new = 32'h00000000;
cycle_ctr_low_we = 1'b0;
cycle_ctr_high_new = 32'h00000000;
cycle_ctr_high_we = 1'b0;
cycle_ctr_state_new = 1'b0;
cycle_ctr_state_we = 1'b0;
if (cycle_ctr_start)
begin
cycle_ctr_low_new = 32'h00000000;
cycle_ctr_low_we = 1'b1;
cycle_ctr_high_new = 32'h00000000;
cycle_ctr_high_we = 1'b1;
cycle_ctr_state_new = 1'b1;
cycle_ctr_state_we = 1'b1;
end
if (cycle_ctr_stop)
begin
cycle_ctr_state_new = 1'b0;
cycle_ctr_state_we = 1'b1;
end
if (cycle_ctr_state_reg)
begin
cycle_ctr_low_new = cycle_ctr_low_reg + 1'b1;
cycle_ctr_low_we = 1'b1;
if (cycle_ctr_low_new == 32'h00000000)
begin
cycle_ctr_high_new = cycle_ctr_high_reg + 1'b1;
cycle_ctr_high_we = 1'b1;
end
end
end // cycle_ctr
//----------------------------------------------------------------
// one
//
// generates the big integer one ( 00... 01 )
//----------------------------------------------------------------
always @*
begin : one_process
one_new = 32'h00000000;
b_one_new = 32'h00000000;
if (montprod_opa_addr == modulus_length_m1)
one_new = 32'h00000001;
if (montprod_opb_addr == modulus_length_m1)
b_one_new = 32'h00000001;
end
//----------------------------------------------------------------
// Read mux for modulus. Needed since it is being
// addressed by two sources.
//----------------------------------------------------------------
always @*
begin : modulus_mem_reader_process
if (modexp_ctrl_reg == CTRL_RESIDUE)
modulus_mem_int_rd_addr = residue_opm_addr;
else
modulus_mem_int_rd_addr = montprod_opm_addr;
end
//----------------------------------------------------------------
// Feeds residue calculator.
//----------------------------------------------------------------
always @*
begin : residue_process
//N*2, N=length*32, *32 = shl5, *64 = shl6
residue_nn = { 1'b0, modulus_length, 6'h0 };
residue_length = modulus_length;
residue_opm_data = modulus_mem_int_rd_data;
end
//----------------------------------------------------------------
// Detects if modulus has been updated and we need to
// recalculate the residue
// and we need residue is valid or not.
//----------------------------------------------------------------
always @*
begin : residue_valid_process
residue_valid_new = residue_valid_reg;
if (modulus_mem_api_cs & modulus_mem_api_wr)
residue_valid_new = 1'b0;
else if ( residue_valid_int_validated == 1'b1)
residue_valid_new = 1'b1;
end
//----------------------------------------------------------------
// montprod_op_select
//
// Select operands used during montprod calculations depending
// on what operation we want to do.
//----------------------------------------------------------------
always @*
begin : montprod_op_select
montprod_length = modulus_length;
result_mem_int_rd_addr = montprod_opa_addr;
message_mem_int_rd_addr = montprod_opa_addr;
p_mem_rd0_addr = montprod_opa_addr;
residue_mem_montprod_read_addr = montprod_opb_addr;
p_mem_rd1_addr = montprod_opb_addr;
montprod_opm_data = modulus_mem_int_rd_data;
case (montprod_select_reg)
MONTPROD_SELECT_ONE_NR:
begin
montprod_opa_data = one_reg;
montprod_opb_data = residue_mem_montprod_read_data;
end
MONTPROD_SELECT_X_NR:
begin
montprod_opa_data = message_mem_int_rd_data;
montprod_opb_data = residue_mem_montprod_read_data;
end
MONTPROD_SELECT_Z_P:
begin
montprod_opa_data = result_mem_int_rd_data;
montprod_opb_data = p_mem_rd1_data;
end
MONTPROD_SELECT_P_P:
begin
montprod_opa_data = p_mem_rd0_data;
montprod_opb_data = p_mem_rd1_data;
end
MONTPROD_SELECT_Z_ONE:
begin
montprod_opa_data = result_mem_int_rd_data;
montprod_opb_data = b_one_reg;
end
default:
begin
montprod_opa_data = 32'h00000000;
montprod_opb_data = 32'h00000000;
end
endcase // case (montprod_selcect_reg)
end
//----------------------------------------------------------------
// memory write mux
//
// Direct memory write signals to correct memory.
//----------------------------------------------------------------
always @*
begin : memory_write_process
result_mem_int_wr_addr = montprod_result_addr;
result_mem_int_wr_data = montprod_result_data;
result_mem_int_we = 1'b0;
p_mem_wr_addr = montprod_result_addr;
p_mem_wr_data = montprod_result_data;
p_mem_we = 1'b0;
case (montprod_dest_reg)
MONTPROD_DEST_Z:
result_mem_int_we = montprod_result_we;
MONTPROD_DEST_P:
p_mem_we = montprod_result_we;
default:
begin
end
endcase
// inhibit Z=Z*P when ei = 0
if (modexp_ctrl_reg == CTRL_ITERATE_Z_P)
result_mem_int_we = result_mem_int_we & ei_reg;
end
//----------------------------------------------------------------
// loop_counter
//
// Calculate the loop counter and related variables.
//----------------------------------------------------------------
always @*
begin : loop_counters_process
loop_counter_new = 13'b0;
loop_counter_we = 1'b0;
if (loop_counter_reg == {exponent_length_m1, 5'b11111})
last_iteration = 1'b1;
else
last_iteration = 1'b0;
case (modexp_ctrl_reg)
CTRL_CALCULATE_P0:
begin
loop_counter_new = 13'b0;
loop_counter_we = 1'b1;
end
CTRL_ITERATE_END:
begin
loop_counter_new = loop_counter_reg + 1'b1;
loop_counter_we = 1'b1;
end
default:
begin
end
endcase
end
//----------------------------------------------------------------
// exponent
//
// Reads the exponent.
//----------------------------------------------------------------
always @*
begin : exponent_process
// Accessing new instead of reg - pick up update at
// CTRL_ITERATE_NEW to remove a pipeline stall.
E_word_index = exponent_length_m1 - loop_counter_new[ 12 : 5 ];
E_bit_index = loop_counter_reg[ 04 : 0 ];
exponent_mem_int_rd_addr = E_word_index;
ei_new = exponent_mem_int_rd_data[ E_bit_index ];
if (modexp_ctrl_reg == CTRL_ITERATE)
ei_we = 1'b1;
else
ei_we = 1'b0;
end
//----------------------------------------------------------------
// modexp_ctrl
//
// Control FSM logic needed to perform the modexp operation.
//----------------------------------------------------------------
always @*
begin
ready_new = 1'b0;
ready_we = 1'b0;
montprod_select_new = MONTPROD_SELECT_ONE_NR;
montprod_select_we = 0;
montprod_dest_new = MONTPROD_DEST_NOWHERE;
montprod_dest_we = 0;
montprod_calc = 0;
modexp_ctrl_new = CTRL_IDLE;
modexp_ctrl_we = 1'b0;
cycle_ctr_start = 1'b0;
cycle_ctr_stop = 1'b0;
residue_calculate = 1'b0;
residue_valid_int_validated = 1'b0;
case (modexp_ctrl_reg)
CTRL_IDLE:
begin
if (start)
begin
ready_new = 1'b0;
ready_we = 1'b1;
cycle_ctr_start = 1'b1;
if (residue_valid_reg)
begin
//residue has alrady been calculated, start with MONTPROD( 1, Nr, MODULUS )
montprod_select_new = MONTPROD_SELECT_ONE_NR;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_Z;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_CALCULATE_Z0;
modexp_ctrl_we = 1;
end
else
begin
//modulus has been written and residue (Nr) must be calculated
modexp_ctrl_new = CTRL_RESIDUE;
modexp_ctrl_we = 1;
residue_calculate = 1'b1;
end
end
end
CTRL_RESIDUE:
begin
if (residue_ready)
begin
montprod_select_new = MONTPROD_SELECT_ONE_NR;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_Z;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_CALCULATE_Z0;
modexp_ctrl_we = 1;
residue_valid_int_validated = 1'b1; //update registers telling residue is valid
end
end
CTRL_CALCULATE_Z0:
begin
if (montprod_ready)
begin
montprod_select_new = MONTPROD_SELECT_X_NR;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_P;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_CALCULATE_P0;
modexp_ctrl_we = 1;
end
end
CTRL_CALCULATE_P0:
begin
if (montprod_ready == 1'b1)
begin
modexp_ctrl_new = CTRL_ITERATE;
modexp_ctrl_we = 1;
end
end
CTRL_ITERATE:
begin
montprod_select_new = MONTPROD_SELECT_Z_P;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_Z;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_ITERATE_Z_P;
modexp_ctrl_we = 1;
if (ei_new == 1'b0 && exponation_mode_reg == EXPONATION_MODE_PUBLIC_FAST)
begin
//Skip the fake montgomery calculation, exponation_mode_reg optimizing for speed not blinding.
montprod_select_new = MONTPROD_SELECT_P_P;
montprod_dest_new = MONTPROD_DEST_P;
modexp_ctrl_new = CTRL_ITERATE_P_P;
end
end
CTRL_ITERATE_Z_P:
if (montprod_ready)
begin
montprod_select_new = MONTPROD_SELECT_P_P;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_P;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_ITERATE_P_P;
modexp_ctrl_we = 1;
end
CTRL_ITERATE_P_P:
if (montprod_ready == 1'b1)
begin
modexp_ctrl_new = CTRL_ITERATE_END;
modexp_ctrl_we = 1;
end
CTRL_ITERATE_END:
begin
if (!last_iteration)
begin
modexp_ctrl_new = CTRL_ITERATE;
modexp_ctrl_we = 1;
end
else
begin
montprod_select_new = MONTPROD_SELECT_Z_ONE;
montprod_select_we = 1;
montprod_dest_new = MONTPROD_DEST_Z;
montprod_dest_we = 1;
montprod_calc = 1;
modexp_ctrl_new = CTRL_CALCULATE_ZN;
modexp_ctrl_we = 1;
end
end
CTRL_CALCULATE_ZN:
begin
if (montprod_ready)
begin
modexp_ctrl_new = CTRL_DONE;
modexp_ctrl_we = 1;
end
end
CTRL_DONE:
begin
cycle_ctr_stop = 1'b1;
ready_new = 1'b1;
ready_we = 1'b1;
modexp_ctrl_new = CTRL_IDLE;
modexp_ctrl_we = 1;
end
default:
begin
end
endcase // case (modexp_ctrl_reg)
end
endmodule // modexp_core
//======================================================================
// EOF modexp_core.v
//======================================================================
|
module modexp_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i; //Address
input wb_cyc_i; //bus cycle
input [dw-1:0] wb_dat_i; //Data IN
input [3:0] wb_sel_i; //Select Input Array
input wb_stb_i; //Chip Select
input wb_we_i; //Write Or Read Enabled
output wb_ack_o; //Acknowledge
output wb_err_o; //Error
output reg [dw-1:0] wb_dat_o; //Data OUT
output int_o; //Interrupt
input wb_clk_i; //Clk
input wb_rst_i; //Reset
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
wire reset_n=!wb_rst_i;
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// The operand width is the internal operand width in bits.
// The address width is the size of the address space used. This
// value must be balances with OPERAND_WIDTH to allow a total
// of 8192 bits of data. OPERAND_WIDTH * (ADDRESS_WIDTH ** 2)
// is the formula. Note that the API data with is always 32 bits.
localparam OPERAND_WIDTH = 32;
localparam ADDRESS_WIDTH = 8;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam CTRL_INIT_BIT = 0;
localparam CTRL_NEXT_BIT = 1;
localparam ADDR_STATUS = 8'h09;
localparam STATUS_READY_BIT = 0;
localparam ADDR_CYCLES_HIGH = 8'h10;
localparam ADDR_CYCLES_LOW = 8'h11;
localparam ADDR_MODULUS_LENGTH = 8'h20;
localparam ADDR_EXPONENT_LENGTH = 8'h21;
localparam ADDR_MODULUS_PTR_RST = 8'h30;
localparam ADDR_MODULUS_DATA = 8'h31;
localparam ADDR_EXPONENT_PTR_RST = 8'h40;
localparam ADDR_EXPONENT_DATA = 8'h41;
localparam ADDR_MESSAGE_PTR_RST = 8'h50;
localparam ADDR_MESSAGE_DATA = 8'h51;
localparam ADDR_RESULT_PTR_RST = 8'h60;
localparam ADDR_RESULT_DATA = 8'h61;
localparam DEFAULT_MODLENGTH = 8'h80; // 2048 bits.
localparam DEFAULT_EXPLENGTH = 8'h80;
localparam CORE_NAME0 = 32'h6d6f6465; // "mode"
localparam CORE_NAME1 = 32'h78702020; // "xp "
localparam CORE_VERSION = 32'h302e3532; // "0.52"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [07 : 0] exponent_length_reg;
reg [07 : 0] exponent_length_new;
reg exponent_length_we;
reg [07 : 0] modulus_length_reg;
reg [07 : 0] modulus_length_new;
reg modulus_length_we;
reg start_reg;
reg start_new;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg exponent_mem_api_rst;
reg exponent_mem_api_cs;
reg exponent_mem_api_wr;
wire [31 : 0] exponent_mem_api_read_data;
reg modulus_mem_api_rst;
reg modulus_mem_api_cs;
reg modulus_mem_api_wr;
wire [31 : 0] modulus_mem_api_read_data;
reg message_mem_api_rst;
reg message_mem_api_cs;
reg message_mem_api_wr;
wire [31 : 0] message_mem_api_read_data;
reg result_mem_api_rst;
reg result_mem_api_cs;
wire [31 : 0] result_mem_api_read_data;
wire ready;
wire [63 : 0] cycles;
//reg [31 : 0] wb_dat_o;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
//assign wb_dat_o = wb_dat_o;
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
modexp_core #(.OPW(OPERAND_WIDTH), .ADW(ADDRESS_WIDTH))
core_inst(
.clk(wb_clk_i),
.reset_n(reset_n),
.start(start_reg),
.ready(ready),
.exponent_length(exponent_length_reg),
.modulus_length(modulus_length_reg),
.cycles(cycles),
.exponent_mem_api_cs(exponent_mem_api_cs),
.exponent_mem_api_wr(exponent_mem_api_wr),
.exponent_mem_api_rst(exponent_mem_api_rst),
.exponent_mem_api_write_data(wb_dat_i),
.exponent_mem_api_read_data(exponent_mem_api_read_data),
.modulus_mem_api_cs(modulus_mem_api_cs),
.modulus_mem_api_wr(modulus_mem_api_wr),
.modulus_mem_api_rst(modulus_mem_api_rst),
.modulus_mem_api_write_data(wb_dat_i),
.modulus_mem_api_read_data(modulus_mem_api_read_data),
.message_mem_api_cs(message_mem_api_cs),
.message_mem_api_wr(message_mem_api_wr),
.message_mem_api_rst(message_mem_api_rst),
.message_mem_api_write_data(wb_dat_i),
.message_mem_api_read_data(message_mem_api_read_data),
.result_mem_api_cs(result_mem_api_cs),
.result_mem_api_rst(result_mem_api_rst),
.result_mem_api_read_data(result_mem_api_read_data)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge wb_clk_i or negedge reset_n)
begin
if (!reset_n)
begin
start_reg <= 1'b0;
exponent_length_reg <= DEFAULT_EXPLENGTH;
modulus_length_reg <= DEFAULT_MODLENGTH;
end
else
begin
start_reg <= start_new;
if (exponent_length_we)
begin
exponent_length_reg <= wb_dat_i[7 : 0];
end
if (modulus_length_we)
begin
modulus_length_reg <= wb_dat_i[7 : 0];
end
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
modulus_length_we = 1'b0;
exponent_length_we = 1'b0;
start_new = 1'b0;
modulus_mem_api_rst = 1'b0;
modulus_mem_api_cs = 1'b0;
modulus_mem_api_wr = 1'b0;
exponent_mem_api_rst = 1'b0;
exponent_mem_api_cs = 1'b0;
exponent_mem_api_wr = 1'b0;
message_mem_api_rst = 1'b0;
message_mem_api_cs = 1'b0;
message_mem_api_wr = 1'b0;
result_mem_api_rst = 1'b0;
result_mem_api_cs = 1'b0;
wb_dat_o = 32'h00000000;
if (wb_stb_i)
begin
if (wb_we_i)
begin
case (wb_adr_i[9:2])
ADDR_CTRL:
begin
start_new = wb_dat_i[0];
end
ADDR_MODULUS_LENGTH:
begin
modulus_length_we = 1'b1;
end
ADDR_EXPONENT_LENGTH:
begin
exponent_length_we = 1'b1;
end
ADDR_MODULUS_PTR_RST:
begin
modulus_mem_api_rst = 1'b1;
end
ADDR_MODULUS_DATA:
begin
modulus_mem_api_cs = 1'b1;
modulus_mem_api_wr = 1'b1;
end
ADDR_EXPONENT_PTR_RST:
begin
exponent_mem_api_rst = 1'b1;
end
ADDR_EXPONENT_DATA:
begin
exponent_mem_api_cs = 1'b1;
exponent_mem_api_wr = 1'b1;
end
ADDR_MESSAGE_PTR_RST:
begin
message_mem_api_rst = 1'b1;
end
ADDR_MESSAGE_DATA:
begin
message_mem_api_cs = 1'b1;
message_mem_api_wr = 1'b1;
end
ADDR_RESULT_PTR_RST:
begin
result_mem_api_rst = 1'b1;
end
default:
begin
end
endcase // case (wb_adr_i[7 : 0])
end // if (wb_we_i)
else
begin
case (wb_adr_i[9:2])
ADDR_NAME0:
wb_dat_o = CORE_NAME0;
ADDR_NAME1:
wb_dat_o = CORE_NAME1;
ADDR_VERSION:
wb_dat_o = CORE_VERSION;
ADDR_CTRL:
wb_dat_o = {31'h00000000, start_reg};
ADDR_STATUS:
wb_dat_o = {31'h00000000, ready};
ADDR_CYCLES_HIGH:
wb_dat_o = cycles[63 : 32];
ADDR_CYCLES_LOW:
wb_dat_o = cycles[31 : 0];
ADDR_MODULUS_LENGTH:
wb_dat_o = {24'h000000, modulus_length_reg};
ADDR_EXPONENT_LENGTH:
wb_dat_o = {24'h000000, exponent_length_reg};
ADDR_MODULUS_DATA:
begin
modulus_mem_api_cs = 1'b1;
wb_dat_o = modulus_mem_api_read_data;
end
ADDR_EXPONENT_DATA:
begin
exponent_mem_api_cs = 1'b1;
wb_dat_o = exponent_mem_api_read_data;
end
ADDR_MESSAGE_DATA:
begin
message_mem_api_cs = 1'b1;
wb_dat_o = message_mem_api_read_data;
end
ADDR_RESULT_DATA:
begin
result_mem_api_cs = 1'b1;
wb_dat_o = result_mem_api_read_data;
end
default:
begin
end
endcase // case (wb_adr_i)
end // else: !if(wb_we_i)
end // if (wb_stb_i)
end // block: api
endmodule // modexp
//======================================================================
// EOF modexp_top.v
//======================================================================
|
//======================================================================
//
// montprod.v
// ---------
// Montgomery product calculator for the modular exponentiantion core.
//
// parameter OPW is operand word width in bits.
// parameter ADW is address width in bits.
//
//
// Author: Peter Magnusson, Joachim Strombergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module montprod #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire reset_n,
input wire calculate,
output wire ready,
input wire [(ADW - 1) : 0] length,
output wire [(ADW - 1) : 0] opa_addr,
input wire [(OPW - 1) : 0] opa_data,
output wire [(ADW - 1) : 0] opb_addr,
input wire [(OPW - 1) : 0] opb_data,
output wire [(ADW - 1) : 0] opm_addr,
input wire [(OPW - 1) : 0] opm_data,
output wire [(ADW - 1) : 0] result_addr,
output wire [(OPW - 1) : 0] result_data,
output wire result_we
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam CTRL_IDLE = 4'h0;
localparam CTRL_LOOP_ITER = 4'h1;
localparam CTRL_LOOP_BQ = 4'h2;
localparam CTRL_CALC_ADD = 4'h3;
localparam CTRL_STALLPIPE_ADD = 4'h4;
localparam CTRL_CALC_SDIV2 = 4'h5;
localparam CTRL_STALLPIPE_SDIV2 = 4'h6;
localparam CTRL_L_STALLPIPE_ES = 4'h7;
localparam CTRL_EMIT_S = 4'h8;
localparam SMUX_ZERO = 2'h0;
localparam SMUX_ADD = 2'h1;
localparam SMUX_SHR = 2'h2;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg ready_reg;
reg ready_new;
reg ready_we;
reg [3 : 0] montprod_ctrl_reg;
reg [3 : 0] montprod_ctrl_new;
reg montprod_ctrl_we;
reg [1 : 0] s_mux_new;
reg [1 : 0] s_mux_reg;
reg s_mem_we_reg;
reg s_mem_we_new;
reg [(ADW - 1) : 0] s_mem_read_addr_reg;
reg q_new;
reg q_reg;
reg b_new;
reg b_reg;
reg bq_we;
reg [12 : 0] loop_ctr_reg;
reg [12 : 0] loop_ctr_new;
reg loop_ctr_we;
reg loop_ctr_set;
reg loop_ctr_dec;
reg [(13 - ADW - 1) : 0] b_bit_index_reg;
reg [(13 - ADW - 1) : 0] b_bit_index_new;
reg b_bit_index_we;
reg [(ADW - 1) : 0] word_index_reg;
reg [(ADW - 1) : 0] word_index_new;
reg word_index_we;
reg [(ADW - 1) : 0] word_index_prev_reg;
reg reset_word_index_lsw;
reg reset_word_index_msw;
reg inc_word_index;
reg dec_word_index;
reg add_carry_in_sa_reg;
reg add_carry_in_sa_new;
reg add_carry_in_sm_reg;
reg add_carry_in_sm_new;
reg shr_carry_in_reg;
reg shr_carry_in_new;
reg first_iteration_reg;
reg first_iteration_new;
reg first_iteration_we;
reg test_reg;
reg test_new;
reg [(OPW - 2) : 0] shr_data_out_reg;
reg shr_carry_out_reg;
reg shr_carry_out_new;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
wire [(OPW - 1) : 0] add_result_sa;
wire add_carry_out_sa;
wire [(OPW - 1) : 0] add_result_sm;
wire add_carry_out_sm;
reg [(ADW - 1) : 0] b_word_index; //loop counter as a word index
/* verilator lint_off UNOPTFLAT */
reg [(OPW - 1) : 0] shr_data_in;
/* verilator lint_on UNOPTFLAT */
wire shr_carry_out;
wire [(OPW - 1) : 0] shr_data_out;
reg [(ADW - 1) : 0] tmp_opa_addr;
reg tmp_result_we;
reg [(ADW - 1) : 0] s_mem_read_addr;
wire [(OPW - 1) : 0] s_mem_read_data;
reg [(ADW - 1) : 0] s_mem_write_addr;
reg [(OPW - 1) : 0] s_mem_write_data;
reg [(OPW - 1) : 0] tmp_s_mem_write_data;
reg [(OPW - 1) : 0] sa_adder_data_in;
/* verilator lint_off UNOPTFLAT */
reg [(OPW - 1) : 0] muxed_s_mem_read_data;
/* verilator lint_on UNOPTFLAT */
reg [(OPW - 1) : 0] shifted_s_mem_write_data;
wire [(ADW - 1) : 0] length_m1;
// Temporary debug wires.
reg [1 : 0] state_trace;
reg [1 : 0] mux_trace;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign length_m1 = length - 1'b1;
assign opa_addr = tmp_opa_addr;
assign opb_addr = b_word_index;
assign opm_addr = word_index_reg;
assign result_addr = word_index_prev_reg;
assign result_data = s_mem_read_data;
assign result_we = tmp_result_we;
assign ready = ready_reg;
//----------------------------------------------------------------
// Instantions
//----------------------------------------------------------------
blockmem1r1w #(.OPW(OPW), .ADW(ADW)) s_mem(
.clk(clk),
.read_addr(s_mem_read_addr),
.read_data(s_mem_read_data),
.wr(s_mem_we_reg),
.write_addr(s_mem_write_addr),
.write_data(s_mem_write_data)
);
adder #(.OPW(OPW)) s_adder_sm(
.a(muxed_s_mem_read_data),
.b(opm_data),
.carry_in(add_carry_in_sm_reg),
.sum(add_result_sm),
.carry_out(add_carry_out_sm)
);
adder #(.OPW(OPW)) s_adder_sa(
.a(sa_adder_data_in),
.b(opa_data),
.carry_in(add_carry_in_sa_reg),
.sum(add_result_sa),
.carry_out(add_carry_out_sa)
);
shr #(.OPW(OPW)) shifter(
.a(shr_data_in),
.carry_in(shr_carry_in_reg),
.adiv2(shr_data_out),
.carry_out(shr_carry_out)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
test_reg <= 1'b1;
ready_reg <= 1'b1;
loop_ctr_reg <= 13'h0;
word_index_reg <= {ADW{1'b0}};
word_index_prev_reg <= {ADW{1'b0}};
add_carry_in_sa_reg <= 1'b0;
add_carry_in_sm_reg <= 1'b0;
shr_data_out_reg <= {(OPW - 1){1'b0}};
shr_carry_in_reg <= 1'b0;
b_reg <= 1'b0;
q_reg <= 1'b0;
s_mux_reg <= SMUX_ZERO;
s_mem_we_reg <= 1'b0;
s_mem_read_addr_reg <= {ADW{1'b0}};
b_bit_index_reg <= {(13 - ADW){1'b0}};
first_iteration_reg <= 1'b0;
montprod_ctrl_reg <= CTRL_IDLE;
end
else
begin
test_reg <= test_new;
s_mem_read_addr_reg <= s_mem_read_addr;
s_mem_we_reg <= s_mem_we_new;
s_mux_reg <= s_mux_new;
word_index_prev_reg <= word_index_reg;
shr_carry_in_reg <= shr_carry_in_new;
add_carry_in_sa_reg <= add_carry_in_sa_new;
add_carry_in_sm_reg <= add_carry_in_sm_new;
shr_data_out_reg <= shr_data_out[(OPW - 2) : 0];
if (word_index_we)
word_index_reg <= word_index_new;
if (first_iteration_we)
first_iteration_reg <= first_iteration_new;
if (b_bit_index_we)
b_bit_index_reg <= b_bit_index_new;
if (bq_we)
begin
b_reg <= b_new;
q_reg <= q_new;
end
if (ready_we)
ready_reg <= ready_new;
if (loop_ctr_we)
loop_ctr_reg <= loop_ctr_new;
if (montprod_ctrl_we)
begin
montprod_ctrl_reg <= montprod_ctrl_new;
end
end
end // reg_update
//----------------------------------------------------------------
// s_logic
//
// Logic to calculate S memory updates including address
// and write enable. This is the main montprod datapath.
//----------------------------------------------------------------
always @*
begin : s_logic
shr_carry_in_new = 1'b0;
muxed_s_mem_read_data = {OPW{1'b0}};
sa_adder_data_in = {OPW{1'b0}};
add_carry_in_sa_new = 1'b0;
add_carry_in_sm_new = 1'b0;
s_mem_read_addr = word_index_reg;
s_mem_write_addr = s_mem_read_addr_reg;
s_mem_write_data = {OPW{1'b0}};
s_mem_we_new = 1'b0;
state_trace = 0;
mux_trace = 0;
tmp_s_mem_write_data = {OPW{1'b0}};
test_new = 1'b0;
case (montprod_ctrl_reg)
CTRL_LOOP_ITER:
begin
s_mem_read_addr = length_m1;
end
CTRL_CALC_ADD:
begin
//s = (s + q*M + b*A) >>> 1;, if(b==1) S+= A. Takes (1..length) cycles.
s_mem_we_new = b_reg | q_reg | first_iteration_reg;
state_trace = 1;
test_new = 1'b1;
end
CTRL_CALC_SDIV2:
begin
//s = (s + q*M + b*A) >>> 1; s>>=1. Takes (1..length) cycles.
s_mem_we_new = 1'b1;
end
default:
begin
end
endcase
case (s_mux_reg)
SMUX_ADD:
begin
mux_trace = 1;
if (first_iteration_reg)
muxed_s_mem_read_data = {OPW{1'b0}};
else
muxed_s_mem_read_data = s_mem_read_data;
if (q_reg)
sa_adder_data_in = add_result_sm;
else
sa_adder_data_in = muxed_s_mem_read_data;
if (b_reg)
tmp_s_mem_write_data = add_result_sa;
else if (q_reg)
tmp_s_mem_write_data = add_result_sm;
else if (first_iteration_reg)
tmp_s_mem_write_data = {OPW{1'b0}};
s_mem_write_data = tmp_s_mem_write_data;
add_carry_in_sa_new = add_carry_out_sa;
add_carry_in_sm_new = add_carry_out_sm;
// Experimental integration of shift in add.
shr_data_in = tmp_s_mem_write_data;
shifted_s_mem_write_data = {shr_carry_out, shr_data_out_reg};
end
SMUX_SHR:
begin
shr_data_in = s_mem_read_data;
s_mem_write_data = shr_data_out;
shr_carry_in_new = shr_carry_out;
end
default:
begin
end
endcase
end // s_logic
//----------------------------------------------------------------
// bq
//
// Extract b and q bits.
// b: current bit of B used.
// q = (s - b * A) & 1
// update the b bit and word indices based on loop counter.
//----------------------------------------------------------------
always @*
begin : bq
b_new = opb_data[b_bit_index_reg];
if (first_iteration_reg)
q_new = 1'b0 ^ (opa_data[0] & b_new);
else
q_new = s_mem_read_data[0] ^ (opa_data[0] & b_new);
// B_bit_index = 5'h1f - loop_counter[4:0];
b_bit_index_new = ((2**(13 - ADW)) - 1'b1) - loop_ctr_reg[(13 - ADW - 1) : 0];
b_word_index = loop_ctr_reg[12 : (13 - ADW)];
end // bq
//----------------------------------------------------------------
// word_index
//
// Logic that implements the word index used to drive
// addresses for operands.
//----------------------------------------------------------------
always @*
begin : word_index
word_index_new = {ADW{1'b0}};
word_index_we = 1'b0;
if (reset_word_index_lsw)
begin
word_index_new = length_m1;
word_index_we = 1'b1;
end
if (reset_word_index_msw)
begin
word_index_new = {ADW{1'b0}};
word_index_we = 1'b1;
end
if (inc_word_index)
begin
word_index_new = word_index_reg + 1'b1;
word_index_we = 1'b1;
end
if (dec_word_index)
begin
word_index_new = word_index_reg - 1'b1;
word_index_we = 1'b1;
end
end // word_index
//----------------------------------------------------------------
// loop_ctr
// Logic for updating the loop counter.
//----------------------------------------------------------------
always @*
begin : loop_ctr
loop_ctr_new = 13'h0;
loop_ctr_we = 1'b0;
if (loop_ctr_set)
begin
loop_ctr_new = {length, {(13 - ADW){1'b0}}} - 1'b1;
loop_ctr_we = 1'b1;
end
if (loop_ctr_dec)
begin
loop_ctr_new = loop_ctr_reg - 1'b1;
loop_ctr_we = 1'b1;
end
end
//----------------------------------------------------------------
// montprod_ctrl
//
// Control FSM for the montgomery product calculator.
//----------------------------------------------------------------
always @*
begin : montprod_ctrl
ready_new = 1'b0;
ready_we = 1'b0;
loop_ctr_set = 1'b0;
loop_ctr_dec = 1'b0;
b_bit_index_we = 1'b0;
bq_we = 1'b0;
s_mux_new = SMUX_ZERO;
dec_word_index = 1'b0;
inc_word_index = 1'b0;
reset_word_index_lsw = 1'b0;
reset_word_index_msw = 1'b0;
first_iteration_new = 1'b0;
first_iteration_we = 1'b0;
tmp_opa_addr = word_index_reg;
tmp_result_we = 1'b0;
montprod_ctrl_new = CTRL_IDLE;
montprod_ctrl_we = 1'b0;
case (montprod_ctrl_reg)
CTRL_IDLE:
begin
if (calculate)
begin
first_iteration_new = 1'b1;
first_iteration_we = 1'b1;
ready_new = 1'b0;
ready_we = 1'b1;
reset_word_index_lsw = 1'b1;
loop_ctr_set = 1'b1;
montprod_ctrl_new = CTRL_LOOP_ITER;
montprod_ctrl_we = 1'b1;
end
end
//calculate q = (s - b * A) & 1;.
// Also abort loop if done.
CTRL_LOOP_ITER:
begin
tmp_opa_addr = length_m1;
b_bit_index_we = 1'b1;
montprod_ctrl_new = CTRL_LOOP_BQ;
montprod_ctrl_we = 1'b1;
end
CTRL_LOOP_BQ:
begin
reset_word_index_lsw = 1'b1;
bq_we = 1'b1;
montprod_ctrl_new = CTRL_CALC_ADD;
montprod_ctrl_we = 1'b1;
end
CTRL_CALC_ADD:
begin
s_mux_new = SMUX_ADD;
if (word_index_reg == 0)
begin
reset_word_index_lsw = 1'b1;
montprod_ctrl_new = CTRL_STALLPIPE_ADD;
montprod_ctrl_we = 1'b1;
end
else
begin
dec_word_index = 1'b1;
end
end
CTRL_STALLPIPE_ADD:
begin
first_iteration_new = 1'b0;
first_iteration_we = 1'b1;
reset_word_index_msw = 1'b1;
montprod_ctrl_new = CTRL_CALC_SDIV2;
montprod_ctrl_we = 1'b1;
end
CTRL_CALC_SDIV2:
begin
s_mux_new = SMUX_SHR;
if (word_index_reg == length_m1)
begin
montprod_ctrl_new = CTRL_STALLPIPE_SDIV2;
montprod_ctrl_we = 1'b1;
end
else
inc_word_index = 1'b1;
end
CTRL_STALLPIPE_SDIV2:
begin
loop_ctr_dec = 1'b1;
montprod_ctrl_new = CTRL_LOOP_ITER;
montprod_ctrl_we = 1'b1;
reset_word_index_lsw = 1'b1;
if (loop_ctr_reg == 0)
begin
montprod_ctrl_new = CTRL_L_STALLPIPE_ES;
montprod_ctrl_we = 1'b1;
end
end
CTRL_L_STALLPIPE_ES:
begin
montprod_ctrl_new = CTRL_EMIT_S;
montprod_ctrl_we = 1'b1;
end
CTRL_EMIT_S:
begin
dec_word_index = 1'b1;
tmp_result_we = 1'b1;
if (word_index_prev_reg == 0)
begin
ready_new = 1'b1;
ready_we = 1'b1;
montprod_ctrl_new = CTRL_IDLE;
montprod_ctrl_we = 1'b1;
end
end
default:
begin
end
endcase // case (montprod_ctrl_reg)
end // montprod_ctrl
endmodule // montprod
//======================================================================
// EOF montprod.v
//======================================================================
|
//======================================================================
//
// residue.v
// ---------
// Modulus 2**2N residue calculator for montgomery calculations.
//
// m_residue_2_2N_array( N, M, Nr)
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
// for (int i = 0; i < 2 * N; i++)
// Nr = Nr shift left 1
// if (Nr less than M) continue;
// Nr = Nr - M
// return Nr
//
//
//
// Author: Peter Magnusson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module residue #(parameter OPW = 32, parameter ADW = 8)
(
input wire clk,
input wire reset_n,
input wire calculate,
output wire ready,
input wire [14 : 0] nn, //MAX(2*N)=8192*2 (14 bit)
input wire [(ADW - 1) : 0] length,
output wire [(ADW - 1) : 0] opa_rd_addr,
input wire [(OPW - 1) : 0] opa_rd_data,
output wire [(ADW - 1) : 0] opa_wr_addr,
output wire [(OPW - 1) : 0] opa_wr_data,
output wire opa_wr_we,
output wire [(ADW - 1) : 0] opm_addr,
input wire [(OPW - 1) : 0] opm_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam CTRL_IDLE = 4'h0;
localparam CTRL_INIT = 4'h1;
localparam CTRL_INIT_STALL = 4'h2;
localparam CTRL_SHL = 4'h3;
localparam CTRL_SHL_STALL = 4'h4;
localparam CTRL_COMPARE = 4'h5;
localparam CTRL_COMPARE_STALL = 4'h6;
localparam CTRL_SUB = 4'h7;
localparam CTRL_SUB_STALL = 4'h8;
localparam CTRL_LOOP = 4'h9;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [(ADW - 1) : 0] opa_rd_addr_reg;
reg [(ADW - 1) : 0] opa_wr_addr_reg;
reg [(OPW - 1) : 0] opa_wr_data_reg;
reg opa_wr_we_reg;
reg [(ADW - 1) : 0] opm_addr_reg;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [03 : 0] residue_ctrl_reg;
reg [03 : 0] residue_ctrl_new;
reg residue_ctrl_we;
reg reset_word_index;
reg reset_n_counter;
reg [14 : 0] loop_counter_1_to_nn_reg; //for i = 1 to nn (2*N)
reg [14 : 0] loop_counter_1_to_nn_new;
reg loop_counter_1_to_nn_we;
reg [14 : 0] nn_reg;
reg nn_we;
reg [(ADW - 1) : 0] length_m1_reg;
reg [(ADW - 1) : 0] length_m1_new;
reg length_m1_we;
reg [(ADW - 1) : 0] word_index_reg;
reg [(ADW - 1) : 0] word_index_new;
reg word_index_we;
reg [(OPW - 1) : 0] one_data;
wire [(OPW - 1) : 0] sub_data;
wire [(OPW - 1) : 0] shl_data;
reg sub_carry_in_new;
reg sub_carry_in_reg;
wire sub_carry_out;
reg shl_carry_in_new;
reg shl_carry_in_reg;
wire shl_carry_out;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign opa_rd_addr = opa_rd_addr_reg;
assign opa_wr_addr = opa_wr_addr_reg;
assign opa_wr_data = opa_wr_data_reg;
assign opa_wr_we = opa_wr_we_reg;
assign opm_addr = opm_addr_reg;
assign ready = ready_reg;
//----------------------------------------------------------------
// Instantions
//----------------------------------------------------------------
adder #(.OPW(OPW)) add_inst(
.a(opa_rd_data),
.b( ~ opm_data),
.carry_in(sub_carry_in_reg),
.sum(sub_data),
.carry_out(sub_carry_out)
);
shl #(.OPW(OPW)) shl_inst(
.a(opa_rd_data),
.carry_in(shl_carry_in_reg),
.amul2(shl_data),
.carry_out(shl_carry_out)
);
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
residue_ctrl_reg <= CTRL_IDLE;
word_index_reg <= {ADW{1'b1}};
length_m1_reg <= {ADW{1'b1}};
nn_reg <= 15'h0;
loop_counter_1_to_nn_reg <= 15'h0;
ready_reg <= 1'b1;
sub_carry_in_reg <= 1'b0;
shl_carry_in_reg <= 1'b0;
end
else
begin
if (residue_ctrl_we)
residue_ctrl_reg <= residue_ctrl_new;
if (word_index_we)
word_index_reg <= word_index_new;
if (length_m1_we)
length_m1_reg <= length_m1_new;
if (nn_we)
nn_reg <= nn;
if (loop_counter_1_to_nn_we)
loop_counter_1_to_nn_reg <= loop_counter_1_to_nn_new;
if (ready_we)
ready_reg <= ready_new;
sub_carry_in_reg <= sub_carry_in_new;
shl_carry_in_reg <= shl_carry_in_new;
end
end // reg_update
//----------------------------------------------------------------
// loop counter process. implements for (int i = 0; i < 2 * N; i++)
//
// m_residue_2_2N_array( N, M, Nr)
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
// for (int i = 0; i < 2 * N; i++)
// Nr = Nr shift left 1
// if (Nr less than M) continue;
// Nr = Nr - M
// return Nr
//
//----------------------------------------------------------------
always @*
begin : process_1_to_2n
loop_counter_1_to_nn_new = loop_counter_1_to_nn_reg + 15'h1;
loop_counter_1_to_nn_we = 1'b0;
if (reset_n_counter)
begin
loop_counter_1_to_nn_new = 15'h1;
loop_counter_1_to_nn_we = 1'b1;
end
if (residue_ctrl_reg == CTRL_LOOP)
loop_counter_1_to_nn_we = 1'b1;
end
//----------------------------------------------------------------
// implements looping over words in a multiword operation
//----------------------------------------------------------------
always @*
begin : word_index_process
word_index_new = word_index_reg - 1'b1;
word_index_we = 1'b1;
if (reset_word_index)
word_index_new = length_m1_reg;
if (residue_ctrl_reg == CTRL_IDLE)
//reduce a pipeline stage with early read
word_index_new = length_m1_new;
end
//----------------------------------------------------------------
// writer process. implements:
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
// Nr = Nr shift left 1
// Nr = Nr - M
//
// m_residue_2_2N_array( N, M, Nr)
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
// for (int i = 0; i < 2 * N; i++)
// Nr = Nr shift left 1
// if (Nr less than M) continue;
// Nr = Nr - M
// return Nr
//----------------------------------------------------------------
always @*
begin : writer_process
opa_wr_addr_reg = word_index_reg;
case (residue_ctrl_reg)
CTRL_INIT:
begin
opa_wr_data_reg = one_data;
opa_wr_we_reg = 1'b1;
end
CTRL_SUB:
begin
opa_wr_data_reg = sub_data;
opa_wr_we_reg = 1'b1;
end
CTRL_SHL:
begin
opa_wr_data_reg = shl_data;
opa_wr_we_reg = 1'b1;
end
default:
begin
opa_wr_data_reg = 32'h0;
opa_wr_we_reg = 1'b0;
end
endcase
end
//----------------------------------------------------------------
// reader process. reads from new value because it occurs one
// cycle earlier than the writer.
//----------------------------------------------------------------
always @*
begin : reader_process
opa_rd_addr_reg = word_index_new;
opm_addr_reg = word_index_new;
end
//----------------------------------------------------------------
// carry process. "Ripple carry awesomeness!"
//----------------------------------------------------------------
always @*
begin : carry_process
case (residue_ctrl_reg)
CTRL_COMPARE:
sub_carry_in_new = sub_carry_out;
CTRL_SUB:
sub_carry_in_new = sub_carry_out;
default:
sub_carry_in_new = 1'b1;
endcase
case (residue_ctrl_reg)
CTRL_SHL:
shl_carry_in_new = shl_carry_out;
default:
shl_carry_in_new = 1'b0;
endcase
end
//----------------------------------------------------------------
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
//----------------------------------------------------------------
always @*
begin : one_process
one_data = 32'h0;
if (residue_ctrl_reg == CTRL_INIT)
if (word_index_reg == length_m1_reg)
one_data = {{(OPW - 1){1'b0}}, 1'b1};
end
//----------------------------------------------------------------
// residue_ctrl
//
// Control FSM for residue
//----------------------------------------------------------------
always @*
begin : residue_ctrl
ready_new = 1'b0;
ready_we = 1'b0;
reset_word_index = 1'b0;
reset_n_counter = 1'b0;
length_m1_new = length - 1'b1;
length_m1_we = 1'b0;
nn_we = 1'b0;
residue_ctrl_new = CTRL_IDLE;
residue_ctrl_we = 1'b0;
case (residue_ctrl_reg)
CTRL_IDLE:
if (calculate)
begin
ready_new = 1'b0;
ready_we = 1'b1;
reset_word_index = 1'b1;
length_m1_we = 1'b1;
nn_we = 1'b1;
residue_ctrl_new = CTRL_INIT;
residue_ctrl_we = 1'b1;
end
// Nr = 00...01 ; Nr = 1 == 2**(2N-2N)
CTRL_INIT:
if (word_index_reg == 0)
begin
residue_ctrl_new = CTRL_INIT_STALL;
residue_ctrl_we = 1'b1;
end
CTRL_INIT_STALL:
begin
reset_word_index = 1'b1;
reset_n_counter = 1'b1;
residue_ctrl_new = CTRL_SHL;
residue_ctrl_we = 1'b1;
end
// Nr = Nr shift left 1
CTRL_SHL:
begin
if (word_index_reg == 0)
begin
residue_ctrl_new = CTRL_SHL_STALL;
residue_ctrl_we = 1'b1;
end
end
CTRL_SHL_STALL:
begin
reset_word_index = 1'b1;
residue_ctrl_new = CTRL_COMPARE;
residue_ctrl_we = 1'b1;
end
//if (Nr less than M) continue
CTRL_COMPARE:
if (word_index_reg == 0)
begin
residue_ctrl_new = CTRL_COMPARE_STALL;
residue_ctrl_we = 1'b1;
end
CTRL_COMPARE_STALL:
begin
reset_word_index = 1'b1;
residue_ctrl_we = 1'b1;
if (sub_carry_in_reg == 1'b1)
//TODO: Bug! detect CF to detect less than, but no detect ZF to detect equal to.
residue_ctrl_new = CTRL_SUB;
else
residue_ctrl_new = CTRL_LOOP;
end
//Nr = Nr - M
CTRL_SUB:
if (word_index_reg == 0)
begin
residue_ctrl_new = CTRL_SUB_STALL;
residue_ctrl_we = 1'b1;
end
CTRL_SUB_STALL:
begin
residue_ctrl_new = CTRL_LOOP;
residue_ctrl_we = 1'b1;
end
//for (int i = 0; i < 2 * N; i++)
CTRL_LOOP:
begin
if (loop_counter_1_to_nn_reg == nn_reg)
begin
ready_new = 1'b1;
ready_we = 1'b1;
residue_ctrl_new = CTRL_IDLE;
residue_ctrl_we = 1'b1;
end
else
begin
reset_word_index = 1'b1;
residue_ctrl_new = CTRL_SHL;
residue_ctrl_we = 1'b1;
end
end
default:
begin
end
endcase
end
endmodule // residue
//======================================================================
// EOF residue.v
//======================================================================
|
//======================================================================
//
// shl.v
// -----
// One bit left shift of words with carry in and carry out. Used in
// the residue module of the modexp core.
//
//
// Author: Peter Magnusson, Joachim Strömbergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module shl #(parameter OPW = 32)
(
input wire [(OPW - 1) : 0] a,
input wire carry_in,
output wire [(OPW - 1) : 0] amul2,
output wire carry_out
);
assign amul2 = {a[(OPW - 2) : 0], carry_in};
assign carry_out = a[(OPW - 1)];
endmodule // shl
//======================================================================
// EOF shl.v
//======================================================================
|
//======================================================================
//
// shr32.v
// -------
// One bit right shift with carry in and carry out.
// Used in the montprod module of the modexp core.
//
//
// Author: Peter Magnusson, Joachim Strömbergson
// Copyright (c) 2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module shr #(parameter OPW = 32)
(
input wire [(OPW - 1) : 0] a,
input wire carry_in,
output wire [(OPW - 1) : 0] adiv2,
output wire carry_out
);
assign adiv2 = {carry_in, a[(OPW - 1) : 1]};
assign carry_out = a[0];
endmodule // shr
//======================================================================
// EOF shr.v
//======================================================================
|
//======================================================================
//
// sha256_core.v
// -------------
// Verilog 2001 implementation of the SHA-256 hash function.
// This is the internal core with wide interfaces.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
// Modified by Matthew Hicks:
// Convert to synchronous, positive level reset
// Fix at 256-bit mode
module sha256(
input wire clk,
input wire rst,
input wire init,
input wire next,
input wire [511 : 0] block,
output wire ready,
output wire [255 : 0] digest,
output wire digest_valid
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter SHA256_H0_0 = 32'h6a09e667;
parameter SHA256_H0_1 = 32'hbb67ae85;
parameter SHA256_H0_2 = 32'h3c6ef372;
parameter SHA256_H0_3 = 32'ha54ff53a;
parameter SHA256_H0_4 = 32'h510e527f;
parameter SHA256_H0_5 = 32'h9b05688c;
parameter SHA256_H0_6 = 32'h1f83d9ab;
parameter SHA256_H0_7 = 32'h5be0cd19;
parameter SHA256_ROUNDS = 63;
parameter CTRL_IDLE = 0;
parameter CTRL_ROUNDS = 1;
parameter CTRL_DONE = 2;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] a_reg;
reg [31 : 0] a_new;
reg [31 : 0] b_reg;
reg [31 : 0] b_new;
reg [31 : 0] c_reg;
reg [31 : 0] c_new;
reg [31 : 0] d_reg;
reg [31 : 0] d_new;
reg [31 : 0] e_reg;
reg [31 : 0] e_new;
reg [31 : 0] f_reg;
reg [31 : 0] f_new;
reg [31 : 0] g_reg;
reg [31 : 0] g_new;
reg [31 : 0] h_reg;
reg [31 : 0] h_new;
reg a_h_we;
reg [31 : 0] H0_reg;
reg [31 : 0] H0_new;
reg [31 : 0] H1_reg;
reg [31 : 0] H1_new;
reg [31 : 0] H2_reg;
reg [31 : 0] H2_new;
reg [31 : 0] H3_reg;
reg [31 : 0] H3_new;
reg [31 : 0] H4_reg;
reg [31 : 0] H4_new;
reg [31 : 0] H5_reg;
reg [31 : 0] H5_new;
reg [31 : 0] H6_reg;
reg [31 : 0] H6_new;
reg [31 : 0] H7_reg;
reg [31 : 0] H7_new;
reg H_we;
reg [5 : 0] t_ctr_reg;
reg [5 : 0] t_ctr_new;
reg t_ctr_we;
reg t_ctr_inc;
reg t_ctr_rst;
reg digest_valid_reg;
reg digest_valid_new;
reg digest_valid_we;
reg [1 : 0] sha256_ctrl_reg;
reg [1 : 0] sha256_ctrl_new;
reg sha256_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg digest_init;
reg digest_update;
reg state_init;
reg state_update;
reg first_block;
reg ready_flag;
reg [31 : 0] t1;
reg [31 : 0] t2;
wire [31 : 0] k_data;
reg w_init;
reg w_next;
wire [31 : 0] w_data;
//----------------------------------------------------------------
// Module instantiantions.
//----------------------------------------------------------------
sha256_k_constants k_constants_inst(
.addr(t_ctr_reg),
.K(k_data)
);
sha256_w_mem w_mem_inst(
.clk(clk),
.rst(rst),
.block(block),
.init(w_init),
.next(w_next),
.w(w_data)
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_flag;
assign digest = {H0_reg, H1_reg, H2_reg, H3_reg,
H4_reg, H5_reg, H6_reg, H7_reg};
assign digest_valid = digest_valid_reg;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
if (rst)
begin
a_reg <= 32'h0;
b_reg <= 32'h0;
c_reg <= 32'h0;
d_reg <= 32'h0;
e_reg <= 32'h0;
f_reg <= 32'h0;
g_reg <= 32'h0;
h_reg <= 32'h0;
H0_reg <= 32'h0;
H1_reg <= 32'h0;
H2_reg <= 32'h0;
H3_reg <= 32'h0;
H4_reg <= 32'h0;
H5_reg <= 32'h0;
H6_reg <= 32'h0;
H7_reg <= 32'h0;
digest_valid_reg <= 0;
t_ctr_reg <= 6'h0;
sha256_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (a_h_we)
begin
a_reg <= a_new;
b_reg <= b_new;
c_reg <= c_new;
d_reg <= d_new;
e_reg <= e_new;
f_reg <= f_new;
g_reg <= g_new;
h_reg <= h_new;
end
if (H_we)
begin
H0_reg <= H0_new;
H1_reg <= H1_new;
H2_reg <= H2_new;
H3_reg <= H3_new;
H4_reg <= H4_new;
H5_reg <= H5_new;
H6_reg <= H6_new;
H7_reg <= H7_new;
end
if (t_ctr_we)
t_ctr_reg <= t_ctr_new;
if (digest_valid_we)
digest_valid_reg <= digest_valid_new;
if (sha256_ctrl_we)
sha256_ctrl_reg <= sha256_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// digest_logic
//
// The logic needed to init as well as update the digest.
//----------------------------------------------------------------
always @*
begin : digest_logic
H0_new = 32'h0;
H1_new = 32'h0;
H2_new = 32'h0;
H3_new = 32'h0;
H4_new = 32'h0;
H5_new = 32'h0;
H6_new = 32'h0;
H7_new = 32'h0;
H_we = 0;
if (digest_init)
begin
H_we = 1;
H0_new = SHA256_H0_0;
H1_new = SHA256_H0_1;
H2_new = SHA256_H0_2;
H3_new = SHA256_H0_3;
H4_new = SHA256_H0_4;
H5_new = SHA256_H0_5;
H6_new = SHA256_H0_6;
H7_new = SHA256_H0_7;
end
if (digest_update)
begin
H0_new = H0_reg + a_reg;
H1_new = H1_reg + b_reg;
H2_new = H2_reg + c_reg;
H3_new = H3_reg + d_reg;
H4_new = H4_reg + e_reg;
H5_new = H5_reg + f_reg;
H6_new = H6_reg + g_reg;
H7_new = H7_reg + h_reg;
H_we = 1;
end
end // digest_logic
//----------------------------------------------------------------
// t1_logic
//
// The logic for the T1 function.
//----------------------------------------------------------------
always @*
begin : t1_logic
reg [31 : 0] sum1;
reg [31 : 0] ch;
sum1 = {e_reg[5 : 0], e_reg[31 : 6]} ^
{e_reg[10 : 0], e_reg[31 : 11]} ^
{e_reg[24 : 0], e_reg[31 : 25]};
ch = (e_reg & f_reg) ^ ((~e_reg) & g_reg);
t1 = h_reg + sum1 + ch + w_data + k_data;
end // t1_logic
//----------------------------------------------------------------
// t2_logic
//
// The logic for the T2 function
//----------------------------------------------------------------
always @*
begin : t2_logic
reg [31 : 0] sum0;
reg [31 : 0] maj;
sum0 = {a_reg[1 : 0], a_reg[31 : 2]} ^
{a_reg[12 : 0], a_reg[31 : 13]} ^
{a_reg[21 : 0], a_reg[31 : 22]};
maj = (a_reg & b_reg) ^ (a_reg & c_reg) ^ (b_reg & c_reg);
t2 = sum0 + maj;
end // t2_logic
//----------------------------------------------------------------
// state_logic
//
// The logic needed to init as well as update the state during
// round processing.
//----------------------------------------------------------------
always @*
begin : state_logic
a_new = 32'h0;
b_new = 32'h0;
c_new = 32'h0;
d_new = 32'h0;
e_new = 32'h0;
f_new = 32'h0;
g_new = 32'h0;
h_new = 32'h0;
a_h_we = 0;
if (state_init)
begin
a_h_we = 1;
if (first_block)
begin
a_new = SHA256_H0_0;
b_new = SHA256_H0_1;
c_new = SHA256_H0_2;
d_new = SHA256_H0_3;
e_new = SHA256_H0_4;
f_new = SHA256_H0_5;
g_new = SHA256_H0_6;
h_new = SHA256_H0_7;
end
else
begin
a_new = H0_reg;
b_new = H1_reg;
c_new = H2_reg;
d_new = H3_reg;
e_new = H4_reg;
f_new = H5_reg;
g_new = H6_reg;
h_new = H7_reg;
end
end
if (state_update)
begin
a_new = t1 + t2;
b_new = a_reg;
c_new = b_reg;
d_new = c_reg;
e_new = d_reg + t1;
f_new = e_reg;
g_new = f_reg;
h_new = g_reg;
a_h_we = 1;
end
end // state_logic
//----------------------------------------------------------------
// t_ctr
//
// Update logic for the round counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : t_ctr
t_ctr_new = 0;
t_ctr_we = 0;
if (t_ctr_rst)
begin
t_ctr_new = 0;
t_ctr_we = 1;
end
if (t_ctr_inc)
begin
t_ctr_new = t_ctr_reg + 1'b1;
t_ctr_we = 1;
end
end // t_ctr
//----------------------------------------------------------------
// sha256_ctrl_fsm
//
// Logic for the state machine controlling the core behaviour.
//----------------------------------------------------------------
always @*
begin : sha256_ctrl_fsm
digest_init = 0;
digest_update = 0;
state_init = 0;
state_update = 0;
first_block = 0;
ready_flag = 0;
w_init = 0;
w_next = 0;
t_ctr_inc = 0;
t_ctr_rst = 0;
digest_valid_new = 0;
digest_valid_we = 0;
sha256_ctrl_new = CTRL_IDLE;
sha256_ctrl_we = 0;
case (sha256_ctrl_reg)
CTRL_IDLE:
begin
ready_flag = 1;
if (init)
begin
digest_init = 1;
w_init = 1;
state_init = 1;
first_block = 1;
t_ctr_rst = 1;
digest_valid_new = 0;
digest_valid_we = 1;
sha256_ctrl_new = CTRL_ROUNDS;
sha256_ctrl_we = 1;
end
if (next)
begin
t_ctr_rst = 1;
w_init = 1;
state_init = 1;
digest_valid_new = 0;
digest_valid_we = 1;
sha256_ctrl_new = CTRL_ROUNDS;
sha256_ctrl_we = 1;
end
end
CTRL_ROUNDS:
begin
w_next = 1;
state_update = 1;
t_ctr_inc = 1;
if (t_ctr_reg == SHA256_ROUNDS)
begin
sha256_ctrl_new = CTRL_DONE;
sha256_ctrl_we = 1;
end
end
CTRL_DONE:
begin
digest_update = 1;
digest_valid_new = 1;
digest_valid_we = 1;
sha256_ctrl_new = CTRL_IDLE;
sha256_ctrl_we = 1;
end
endcase // case (sha256_ctrl_reg)
end // sha256_ctrl_fsm
endmodule // sha256_core
//======================================================================
// EOF sha256_core.v
//======================================================================
|
//======================================================================
//
// sha256_k_constants.v
// --------------------
// The table K with constants in the SHA-256 hash function.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module sha256_k_constants(
input wire [5 : 0] addr,
output wire [31 : 0] K
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_K;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign K = tmp_K;
//----------------------------------------------------------------
// addr_mux
//----------------------------------------------------------------
always @*
begin : addr_mux
case(addr)
00:
tmp_K = 32'h428a2f98;
01:
tmp_K = 32'h71374491;
02:
tmp_K = 32'hb5c0fbcf;
03:
tmp_K = 32'he9b5dba5;
04:
tmp_K = 32'h3956c25b;
05:
tmp_K = 32'h59f111f1;
06:
tmp_K = 32'h923f82a4;
07:
tmp_K = 32'hab1c5ed5;
08:
tmp_K = 32'hd807aa98;
09:
tmp_K = 32'h12835b01;
10:
tmp_K = 32'h243185be;
11:
tmp_K = 32'h550c7dc3;
12:
tmp_K = 32'h72be5d74;
13:
tmp_K = 32'h80deb1fe;
14:
tmp_K = 32'h9bdc06a7;
15:
tmp_K = 32'hc19bf174;
16:
tmp_K = 32'he49b69c1;
17:
tmp_K = 32'hefbe4786;
18:
tmp_K = 32'h0fc19dc6;
19:
tmp_K = 32'h240ca1cc;
20:
tmp_K = 32'h2de92c6f;
21:
tmp_K = 32'h4a7484aa;
22:
tmp_K = 32'h5cb0a9dc;
23:
tmp_K = 32'h76f988da;
24:
tmp_K = 32'h983e5152;
25:
tmp_K = 32'ha831c66d;
26:
tmp_K = 32'hb00327c8;
27:
tmp_K = 32'hbf597fc7;
28:
tmp_K = 32'hc6e00bf3;
29:
tmp_K = 32'hd5a79147;
30:
tmp_K = 32'h06ca6351;
31:
tmp_K = 32'h14292967;
32:
tmp_K = 32'h27b70a85;
33:
tmp_K = 32'h2e1b2138;
34:
tmp_K = 32'h4d2c6dfc;
35:
tmp_K = 32'h53380d13;
36:
tmp_K = 32'h650a7354;
37:
tmp_K = 32'h766a0abb;
38:
tmp_K = 32'h81c2c92e;
39:
tmp_K = 32'h92722c85;
40:
tmp_K = 32'ha2bfe8a1;
41:
tmp_K = 32'ha81a664b;
42:
tmp_K = 32'hc24b8b70;
43:
tmp_K = 32'hc76c51a3;
44:
tmp_K = 32'hd192e819;
45:
tmp_K = 32'hd6990624;
46:
tmp_K = 32'hf40e3585;
47:
tmp_K = 32'h106aa070;
48:
tmp_K = 32'h19a4c116;
49:
tmp_K = 32'h1e376c08;
50:
tmp_K = 32'h2748774c;
51:
tmp_K = 32'h34b0bcb5;
52:
tmp_K = 32'h391c0cb3;
53:
tmp_K = 32'h4ed8aa4a;
54:
tmp_K = 32'h5b9cca4f;
55:
tmp_K = 32'h682e6ff3;
56:
tmp_K = 32'h748f82ee;
57:
tmp_K = 32'h78a5636f;
58:
tmp_K = 32'h84c87814;
59:
tmp_K = 32'h8cc70208;
60:
tmp_K = 32'h90befffa;
61:
tmp_K = 32'ha4506ceb;
62:
tmp_K = 32'hbef9a3f7;
63:
tmp_K = 32'hc67178f2;
endcase // case (addr)
end // block: addr_mux
endmodule // sha256_k_constants
//======================================================================
// sha256_k_constants.v
//======================================================================
|
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : sha256_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-SHA256 core
//
module sha256_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg startHash, startHash_r;
reg newMessage, newMessage_r;
reg [31:0] data [0:15];
wire [511:0] bigData = {data[15], data[14], data[13], data[12], data[11], data[10], data[9], data[8], data[7], data[6], data[5], data[4], data[3], data[2], data[1], data[0]};
wire [255:0] hash;
wire ready;
wire hashValid;
// Implement SHA256 I/O memory map interface
// Write side
always @(posedge wb_clk_i)
begin
if(wb_rst_i)
begin
startHash <= 0;
startHash_r <= 0;
newMessage <= 0;
newMessage_r <= 0;
data[0] <= 0;
data[1] <= 0;
data[2] <= 0;
data[3] <= 0;
data[4] <= 0;
data[5] <= 0;
data[6] <= 0;
data[7] <= 0;
data[8] <= 0;
data[9] <= 0;
data[10] <= 0;
data[11] <= 0;
data[12] <= 0;
data[13] <= 0;
data[14] <= 0;
data[15] <= 0;
end
else begin
// Generate a registered versions of startHash and newMessage
startHash_r <= startHash;
newMessage_r <= newMessage;
// Perform a write
if(wb_stb_i & wb_we_i) begin
case(wb_adr_i[6:2])
0: begin
startHash <= wb_dat_i[0];
newMessage <= wb_dat_i[1];
end
1: data[0] <= wb_dat_i;
2: data[1] <= wb_dat_i;
3: data[2] <= wb_dat_i;
4: data[3] <= wb_dat_i;
5: data[4] <= wb_dat_i;
6: data[5] <= wb_dat_i;
7: data[6] <= wb_dat_i;
8: data[7] <= wb_dat_i;
9: data[8] <= wb_dat_i;
10: data[9] <= wb_dat_i;
11: data[10] <= wb_dat_i;
12: data[11] <= wb_dat_i;
13: data[12] <= wb_dat_i;
14: data[13] <= wb_dat_i;
15: data[14] <= wb_dat_i;
16: data[15] <= wb_dat_i;
default:
;
endcase
end else begin
startHash <= 1'b0;
newMessage <= 1'b0;
end // end else
end
end // end always
// Implement SHA256 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[6:2])
0: wb_dat_o = {31'b0, ready};
1: wb_dat_o = data[0];
2: wb_dat_o = data[1];
3: wb_dat_o = data[2];
4: wb_dat_o = data[3];
5: wb_dat_o = data[4];
6: wb_dat_o = data[5];
7: wb_dat_o = data[6];
8: wb_dat_o = data[7];
9: wb_dat_o = data[8];
10: wb_dat_o = data[9];
11: wb_dat_o = data[10];
12: wb_dat_o = data[11];
13: wb_dat_o = data[12];
14: wb_dat_o = data[13];
15: wb_dat_o = data[14];
16: wb_dat_o = data[15];
17: wb_dat_o = {31'b0, hashValid};
18: wb_dat_o = hash[31:0];
19: wb_dat_o = hash[63:32];
20: wb_dat_o = hash[95:64];
21: wb_dat_o = hash[127:96];
22: wb_dat_o = hash[159:128];
23: wb_dat_o = hash[191:160];
24: wb_dat_o = hash[223:192];
25: wb_dat_o = hash[255:224];
default:
wb_dat_o = 32'b0;
endcase
end
sha256 sha256(
.clk(wb_clk_i),
.rst(wb_rst_i),
.init(startHash && ~startHash_r),
.next(newMessage && ~newMessage_r),
.block(bigData),
.digest(hash),
.digest_valid(hashValid),
.ready(ready)
);
endmodule
|
//======================================================================
//
// sha256_w_mem_regs.v
// -------------------
// The W memory. This version uses 16 32-bit registers as a sliding
// window to generate the 64 words.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module sha256_w_mem(
input wire clk,
input wire rst,
input wire [511 : 0] block,
input wire init,
input wire next,
output wire [31 : 0] w
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter CTRL_IDLE = 0;
parameter CTRL_UPDATE = 1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] w_mem [0 : 15];
reg [31 : 0] w_mem00_new;
reg [31 : 0] w_mem01_new;
reg [31 : 0] w_mem02_new;
reg [31 : 0] w_mem03_new;
reg [31 : 0] w_mem04_new;
reg [31 : 0] w_mem05_new;
reg [31 : 0] w_mem06_new;
reg [31 : 0] w_mem07_new;
reg [31 : 0] w_mem08_new;
reg [31 : 0] w_mem09_new;
reg [31 : 0] w_mem10_new;
reg [31 : 0] w_mem11_new;
reg [31 : 0] w_mem12_new;
reg [31 : 0] w_mem13_new;
reg [31 : 0] w_mem14_new;
reg [31 : 0] w_mem15_new;
reg w_mem_we;
reg [5 : 0] w_ctr_reg;
reg [5 : 0] w_ctr_new;
reg w_ctr_we;
reg w_ctr_inc;
reg w_ctr_rst;
reg [1 : 0] sha256_w_mem_ctrl_reg;
reg [1 : 0] sha256_w_mem_ctrl_new;
reg sha256_w_mem_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] w_tmp;
reg [31 : 0] w_new;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign w = w_tmp;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
if (rst)
begin
w_mem[00] <= 32'h0;
w_mem[01] <= 32'h0;
w_mem[02] <= 32'h0;
w_mem[03] <= 32'h0;
w_mem[04] <= 32'h0;
w_mem[05] <= 32'h0;
w_mem[06] <= 32'h0;
w_mem[07] <= 32'h0;
w_mem[08] <= 32'h0;
w_mem[09] <= 32'h0;
w_mem[10] <= 32'h0;
w_mem[11] <= 32'h0;
w_mem[12] <= 32'h0;
w_mem[13] <= 32'h0;
w_mem[14] <= 32'h0;
w_mem[15] <= 32'h0;
w_ctr_reg <= 6'h00;
sha256_w_mem_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (w_mem_we)
begin
w_mem[00] <= w_mem00_new;
w_mem[01] <= w_mem01_new;
w_mem[02] <= w_mem02_new;
w_mem[03] <= w_mem03_new;
w_mem[04] <= w_mem04_new;
w_mem[05] <= w_mem05_new;
w_mem[06] <= w_mem06_new;
w_mem[07] <= w_mem07_new;
w_mem[08] <= w_mem08_new;
w_mem[09] <= w_mem09_new;
w_mem[10] <= w_mem10_new;
w_mem[11] <= w_mem11_new;
w_mem[12] <= w_mem12_new;
w_mem[13] <= w_mem13_new;
w_mem[14] <= w_mem14_new;
w_mem[15] <= w_mem15_new;
end
if (w_ctr_we)
w_ctr_reg <= w_ctr_new;
if (sha256_w_mem_ctrl_we)
sha256_w_mem_ctrl_reg <= sha256_w_mem_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// select_w
//
// Mux for the external read operation. This is where we exract
// the W variable.
//----------------------------------------------------------------
always @*
begin : select_w
if (w_ctr_reg < 16)
begin
w_tmp = w_mem[w_ctr_reg[3 : 0]];
end
else
begin
w_tmp = w_new;
end
end // select_w
//----------------------------------------------------------------
// w_new_logic
//
// Logic that calculates the next value to be inserted into
// the sliding window of the memory.
//----------------------------------------------------------------
always @*
begin : w_mem_update_logic
reg [31 : 0] w_0;
reg [31 : 0] w_1;
reg [31 : 0] w_9;
reg [31 : 0] w_14;
reg [31 : 0] d0;
reg [31 : 0] d1;
w_mem00_new = 32'h0;
w_mem01_new = 32'h0;
w_mem02_new = 32'h0;
w_mem03_new = 32'h0;
w_mem04_new = 32'h0;
w_mem05_new = 32'h0;
w_mem06_new = 32'h0;
w_mem07_new = 32'h0;
w_mem08_new = 32'h0;
w_mem09_new = 32'h0;
w_mem10_new = 32'h0;
w_mem11_new = 32'h0;
w_mem12_new = 32'h0;
w_mem13_new = 32'h0;
w_mem14_new = 32'h0;
w_mem15_new = 32'h0;
w_mem_we = 0;
w_0 = w_mem[0];
w_1 = w_mem[1];
w_9 = w_mem[9];
w_14 = w_mem[14];
d0 = {w_1[6 : 0], w_1[31 : 7]} ^
{w_1[17 : 0], w_1[31 : 18]} ^
{3'b000, w_1[31 : 3]};
d1 = {w_14[16 : 0], w_14[31 : 17]} ^
{w_14[18 : 0], w_14[31 : 19]} ^
{10'b0000000000, w_14[31 : 10]};
w_new = d1 + w_9 + d0 + w_0;
if (init)
begin
w_mem00_new = block[511 : 480];
w_mem01_new = block[479 : 448];
w_mem02_new = block[447 : 416];
w_mem03_new = block[415 : 384];
w_mem04_new = block[383 : 352];
w_mem05_new = block[351 : 320];
w_mem06_new = block[319 : 288];
w_mem07_new = block[287 : 256];
w_mem08_new = block[255 : 224];
w_mem09_new = block[223 : 192];
w_mem10_new = block[191 : 160];
w_mem11_new = block[159 : 128];
w_mem12_new = block[127 : 96];
w_mem13_new = block[95 : 64];
w_mem14_new = block[63 : 32];
w_mem15_new = block[31 : 0];
w_mem_we = 1;
end
else if (w_ctr_reg > 15)
begin
w_mem00_new = w_mem[01];
w_mem01_new = w_mem[02];
w_mem02_new = w_mem[03];
w_mem03_new = w_mem[04];
w_mem04_new = w_mem[05];
w_mem05_new = w_mem[06];
w_mem06_new = w_mem[07];
w_mem07_new = w_mem[08];
w_mem08_new = w_mem[09];
w_mem09_new = w_mem[10];
w_mem10_new = w_mem[11];
w_mem11_new = w_mem[12];
w_mem12_new = w_mem[13];
w_mem13_new = w_mem[14];
w_mem14_new = w_mem[15];
w_mem15_new = w_new;
w_mem_we = 1;
end
end // w_mem_update_logic
//----------------------------------------------------------------
// w_ctr
// W schedule adress counter. Counts from 0x10 to 0x3f and
// is used to expand the block into words.
//----------------------------------------------------------------
always @*
begin : w_ctr
w_ctr_new = 0;
w_ctr_we = 0;
if (w_ctr_rst)
begin
w_ctr_new = 6'h00;
w_ctr_we = 1;
end
if (w_ctr_inc)
begin
w_ctr_new = w_ctr_reg + 6'h01;
w_ctr_we = 1;
end
end // w_ctr
//----------------------------------------------------------------
// sha256_w_mem_fsm
// Logic for the w shedule FSM.
//----------------------------------------------------------------
always @*
begin : sha256_w_mem_fsm
w_ctr_rst = 0;
w_ctr_inc = 0;
sha256_w_mem_ctrl_new = CTRL_IDLE;
sha256_w_mem_ctrl_we = 0;
case (sha256_w_mem_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
w_ctr_rst = 1;
sha256_w_mem_ctrl_new = CTRL_UPDATE;
sha256_w_mem_ctrl_we = 1;
end
end
CTRL_UPDATE:
begin
if (next)
begin
w_ctr_inc = 1;
end
if (w_ctr_reg == 6'h3f)
begin
sha256_w_mem_ctrl_new = CTRL_IDLE;
sha256_w_mem_ctrl_we = 1;
end
end
endcase // case (sha256_ctrl_reg)
end // sha256_ctrl_fsm
endmodule // sha256_w_mem
//======================================================================
// sha256_w_mem.v
//======================================================================
|
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Defines of the Core ////
//// ////
//// Known problems (limits): ////
//// None ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - gorban@opencores.org ////
//// - Jacob Gorban ////
//// - Igor Mohor (igorm@opencores.org) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Timescale define
`timescale 1ns/10ps
|
/*
* This source file contains a Verilog description of an IP core
* automatically generated by the SPIRAL HDL Generator.
*
* This product includes a hardware design developed by Carnegie Mellon University.
*
* Copyright (c) 2005-2011 by Peter A. Milder for the SPIRAL Project,
* Carnegie Mellon University
*
* For more information, see the SPIRAL project website at:
* http://www.spiral.net
*
* This design is provided for internal, non-commercial research use only
* and is not for redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
// Input/output stream: 2 complex words per cycle
// Throughput: one transform every 32 cycles
// Latency: 332 cycles
// Resources required:
// 20 multipliers (16 x 16 bit)
// 34 adders (16 x 16 bit)
// 4 RAMs (16 words, 32 bits per word)
// 4 RAMs (8 words, 32 bits per word)
// 12 RAMs (64 words, 32 bits per word)
// 4 RAMs (32 words, 32 bits per word)
// 2 ROMs (32 words, 16 bits per word)
// 2 ROMs (8 words, 16 bits per word)
// 12 ROMs (32 words, 5 bits per word)
// 2 ROMs (16 words, 16 bits per word)
// Generated on Tue Sep 04 00:43:02 EDT 2018
// Latency: 332 clock cycles
// Throughput: 1 transform every 32 cycles
// We use an interleaved complex data format. X0 represents the
// real portion of the first input, and X1 represents the imaginary
// portion. The X variables are system inputs and the Y variables
// are system outputs.
// The design uses a system of flag signals to indicate the
// beginning of the input and output data streams. The 'next'
// input (asserted high), is used to instruct the system that the
// input stream will begin on the following cycle.
// This system has a 'gap' of 32 cycles. This means that
// 32 cycles must elapse between the beginning of the input
// vectors.
// The output signal 'next_out' (also asserted high) indicates
// that the output vector will begin streaming out of the system
// on the following cycle.
// The system has a latency of 332 cycles. This means that
// the 'next_out' will be asserted 332 cycles after the user
// asserts 'next'.
// The simple testbench below will demonstrate the timing for loading
// and unloading data vectors.
// The system reset signal is asserted high.
// Please note: when simulating floating point code, you must include
// Xilinx's DSP slice simulation module.
// Latency: 332
// Gap: 32
// module_name_is:dft_top
module dft_top(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [15:0] t0_0;
wire [15:0] t0_1;
wire [15:0] t0_2;
wire [15:0] t0_3;
wire next_0;
wire [15:0] t1_0;
wire [15:0] t1_1;
wire [15:0] t1_2;
wire [15:0] t1_3;
wire next_1;
wire [15:0] t2_0;
wire [15:0] t2_1;
wire [15:0] t2_2;
wire [15:0] t2_3;
wire next_2;
wire [15:0] t3_0;
wire [15:0] t3_1;
wire [15:0] t3_2;
wire [15:0] t3_3;
wire next_3;
wire [15:0] t4_0;
wire [15:0] t4_1;
wire [15:0] t4_2;
wire [15:0] t4_3;
wire next_4;
wire [15:0] t5_0;
wire [15:0] t5_1;
wire [15:0] t5_2;
wire [15:0] t5_3;
wire next_5;
wire [15:0] t6_0;
wire [15:0] t6_1;
wire [15:0] t6_2;
wire [15:0] t6_3;
wire next_6;
wire [15:0] t7_0;
wire [15:0] t7_1;
wire [15:0] t7_2;
wire [15:0] t7_3;
wire next_7;
wire [15:0] t8_0;
wire [15:0] t8_1;
wire [15:0] t8_2;
wire [15:0] t8_3;
wire next_8;
wire [15:0] t9_0;
wire [15:0] t9_1;
wire [15:0] t9_2;
wire [15:0] t9_3;
wire next_9;
wire [15:0] t10_0;
wire [15:0] t10_1;
wire [15:0] t10_2;
wire [15:0] t10_3;
wire next_10;
wire [15:0] t11_0;
wire [15:0] t11_1;
wire [15:0] t11_2;
wire [15:0] t11_3;
wire next_11;
wire [15:0] t12_0;
wire [15:0] t12_1;
wire [15:0] t12_2;
wire [15:0] t12_3;
wire next_12;
wire [15:0] t13_0;
wire [15:0] t13_1;
wire [15:0] t13_2;
wire [15:0] t13_3;
wire next_13;
wire [15:0] t14_0;
wire [15:0] t14_1;
wire [15:0] t14_2;
wire [15:0] t14_3;
wire next_14;
wire [15:0] t15_0;
wire [15:0] t15_1;
wire [15:0] t15_2;
wire [15:0] t15_3;
wire next_15;
wire [15:0] t16_0;
wire [15:0] t16_1;
wire [15:0] t16_2;
wire [15:0] t16_3;
wire next_16;
wire [15:0] t17_0;
wire [15:0] t17_1;
wire [15:0] t17_2;
wire [15:0] t17_3;
wire next_17;
wire [15:0] t18_0;
wire [15:0] t18_1;
wire [15:0] t18_2;
wire [15:0] t18_3;
wire next_18;
assign t0_0 = X0;
assign Y0 = t18_0;
assign t0_1 = X1;
assign Y1 = t18_1;
assign t0_2 = X2;
assign Y2 = t18_2;
assign t0_3 = X3;
assign Y3 = t18_3;
assign next_0 = next;
assign next_out = next_18;
// latency=68, gap=32
rc82445 stage0(.clk(clk), .reset(reset), .next(next_0), .next_out(next_1),
.X0(t0_0), .Y0(t1_0),
.X1(t0_1), .Y1(t1_1),
.X2(t0_2), .Y2(t1_2),
.X3(t0_3), .Y3(t1_3));
// latency=2, gap=32
codeBlock82447 stage1(.clk(clk), .reset(reset), .next_in(next_1), .next_out(next_2),
.X0_in(t1_0), .Y0(t2_0),
.X1_in(t1_1), .Y1(t2_1),
.X2_in(t1_2), .Y2(t2_2),
.X3_in(t1_3), .Y3(t2_3));
// latency=8, gap=32
rc82529 stage2(.clk(clk), .reset(reset), .next(next_2), .next_out(next_3),
.X0(t2_0), .Y0(t3_0),
.X1(t2_1), .Y1(t3_1),
.X2(t2_2), .Y2(t3_2),
.X3(t2_3), .Y3(t3_3));
// latency=8, gap=32
DirSum_82710 stage3(.next(next_3), .clk(clk), .reset(reset), .next_out(next_4),
.X0(t3_0), .Y0(t4_0),
.X1(t3_1), .Y1(t4_1),
.X2(t3_2), .Y2(t4_2),
.X3(t3_3), .Y3(t4_3));
// latency=2, gap=32
codeBlock82713 stage4(.clk(clk), .reset(reset), .next_in(next_4), .next_out(next_5),
.X0_in(t4_0), .Y0(t5_0),
.X1_in(t4_1), .Y1(t5_1),
.X2_in(t4_2), .Y2(t5_2),
.X3_in(t4_3), .Y3(t5_3));
// latency=12, gap=32
rc82795 stage5(.clk(clk), .reset(reset), .next(next_5), .next_out(next_6),
.X0(t5_0), .Y0(t6_0),
.X1(t5_1), .Y1(t6_1),
.X2(t5_2), .Y2(t6_2),
.X3(t5_3), .Y3(t6_3));
// latency=8, gap=32
DirSum_82984 stage6(.next(next_6), .clk(clk), .reset(reset), .next_out(next_7),
.X0(t6_0), .Y0(t7_0),
.X1(t6_1), .Y1(t7_1),
.X2(t6_2), .Y2(t7_2),
.X3(t6_3), .Y3(t7_3));
// latency=2, gap=32
codeBlock82987 stage7(.clk(clk), .reset(reset), .next_in(next_7), .next_out(next_8),
.X0_in(t7_0), .Y0(t8_0),
.X1_in(t7_1), .Y1(t8_1),
.X2_in(t7_2), .Y2(t8_2),
.X3_in(t7_3), .Y3(t8_3));
// latency=20, gap=32
rc83069 stage8(.clk(clk), .reset(reset), .next(next_8), .next_out(next_9),
.X0(t8_0), .Y0(t9_0),
.X1(t8_1), .Y1(t9_1),
.X2(t8_2), .Y2(t9_2),
.X3(t8_3), .Y3(t9_3));
// latency=8, gap=32
DirSum_83274 stage9(.next(next_9), .clk(clk), .reset(reset), .next_out(next_10),
.X0(t9_0), .Y0(t10_0),
.X1(t9_1), .Y1(t10_1),
.X2(t9_2), .Y2(t10_2),
.X3(t9_3), .Y3(t10_3));
// latency=2, gap=32
codeBlock83277 stage10(.clk(clk), .reset(reset), .next_in(next_10), .next_out(next_11),
.X0_in(t10_0), .Y0(t11_0),
.X1_in(t10_1), .Y1(t11_1),
.X2_in(t10_2), .Y2(t11_2),
.X3_in(t10_3), .Y3(t11_3));
// latency=36, gap=32
rc83359 stage11(.clk(clk), .reset(reset), .next(next_11), .next_out(next_12),
.X0(t11_0), .Y0(t12_0),
.X1(t11_1), .Y1(t12_1),
.X2(t11_2), .Y2(t12_2),
.X3(t11_3), .Y3(t12_3));
// latency=8, gap=32
DirSum_83596 stage12(.next(next_12), .clk(clk), .reset(reset), .next_out(next_13),
.X0(t12_0), .Y0(t13_0),
.X1(t12_1), .Y1(t13_1),
.X2(t12_2), .Y2(t13_2),
.X3(t12_3), .Y3(t13_3));
// latency=2, gap=32
codeBlock83599 stage13(.clk(clk), .reset(reset), .next_in(next_13), .next_out(next_14),
.X0_in(t13_0), .Y0(t14_0),
.X1_in(t13_1), .Y1(t14_1),
.X2_in(t13_2), .Y2(t14_2),
.X3_in(t13_3), .Y3(t14_3));
// latency=68, gap=32
rc83681 stage14(.clk(clk), .reset(reset), .next(next_14), .next_out(next_15),
.X0(t14_0), .Y0(t15_0),
.X1(t14_1), .Y1(t15_1),
.X2(t14_2), .Y2(t15_2),
.X3(t14_3), .Y3(t15_3));
// latency=8, gap=32
DirSum_83981 stage15(.next(next_15), .clk(clk), .reset(reset), .next_out(next_16),
.X0(t15_0), .Y0(t16_0),
.X1(t15_1), .Y1(t16_1),
.X2(t15_2), .Y2(t16_2),
.X3(t15_3), .Y3(t16_3));
// latency=2, gap=32
codeBlock83984 stage16(.clk(clk), .reset(reset), .next_in(next_16), .next_out(next_17),
.X0_in(t16_0), .Y0(t17_0),
.X1_in(t16_1), .Y1(t17_1),
.X2_in(t16_2), .Y2(t17_2),
.X3_in(t16_3), .Y3(t17_3));
// latency=68, gap=32
rc84066 stage17(.clk(clk), .reset(reset), .next(next_17), .next_out(next_18),
.X0(t17_0), .Y0(t18_0),
.X1(t17_1), .Y1(t18_1),
.X2(t17_2), .Y2(t18_2),
.X3(t17_3), .Y3(t18_3));
endmodule
// Latency: 68
// Gap: 32
module rc82445(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm82443 instPerm85011(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet82443(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm82443(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter addrbits = 5;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm0;
assign tm0 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85016(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85017(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(31, 5) nextReg_85028(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85029(.X(next2), .Y(next3), .clk(clk));
nextReg #(32, 5) nextReg_85032(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85033(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(31, 1) shiftFIFO_85036(.X(tm0), .Y(tm0_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85039(.X(tm0_d), .Y(tm0_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 5) shiftFIFO_85044(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm0_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 16;
{1'd0, 5'd1}: s1rd0 <= 24;
{1'd0, 5'd2}: s1rd0 <= 20;
{1'd0, 5'd3}: s1rd0 <= 28;
{1'd0, 5'd4}: s1rd0 <= 18;
{1'd0, 5'd5}: s1rd0 <= 26;
{1'd0, 5'd6}: s1rd0 <= 22;
{1'd0, 5'd7}: s1rd0 <= 30;
{1'd0, 5'd8}: s1rd0 <= 17;
{1'd0, 5'd9}: s1rd0 <= 25;
{1'd0, 5'd10}: s1rd0 <= 21;
{1'd0, 5'd11}: s1rd0 <= 29;
{1'd0, 5'd12}: s1rd0 <= 19;
{1'd0, 5'd13}: s1rd0 <= 27;
{1'd0, 5'd14}: s1rd0 <= 23;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 8;
{1'd0, 5'd18}: s1rd0 <= 4;
{1'd0, 5'd19}: s1rd0 <= 12;
{1'd0, 5'd20}: s1rd0 <= 2;
{1'd0, 5'd21}: s1rd0 <= 10;
{1'd0, 5'd22}: s1rd0 <= 6;
{1'd0, 5'd23}: s1rd0 <= 14;
{1'd0, 5'd24}: s1rd0 <= 1;
{1'd0, 5'd25}: s1rd0 <= 9;
{1'd0, 5'd26}: s1rd0 <= 5;
{1'd0, 5'd27}: s1rd0 <= 13;
{1'd0, 5'd28}: s1rd0 <= 3;
{1'd0, 5'd29}: s1rd0 <= 11;
{1'd0, 5'd30}: s1rd0 <= 7;
{1'd0, 5'd31}: s1rd0 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm0_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 8;
{1'd0, 5'd2}: s1rd1 <= 4;
{1'd0, 5'd3}: s1rd1 <= 12;
{1'd0, 5'd4}: s1rd1 <= 2;
{1'd0, 5'd5}: s1rd1 <= 10;
{1'd0, 5'd6}: s1rd1 <= 6;
{1'd0, 5'd7}: s1rd1 <= 14;
{1'd0, 5'd8}: s1rd1 <= 1;
{1'd0, 5'd9}: s1rd1 <= 9;
{1'd0, 5'd10}: s1rd1 <= 5;
{1'd0, 5'd11}: s1rd1 <= 13;
{1'd0, 5'd12}: s1rd1 <= 3;
{1'd0, 5'd13}: s1rd1 <= 11;
{1'd0, 5'd14}: s1rd1 <= 7;
{1'd0, 5'd15}: s1rd1 <= 15;
{1'd0, 5'd16}: s1rd1 <= 16;
{1'd0, 5'd17}: s1rd1 <= 24;
{1'd0, 5'd18}: s1rd1 <= 20;
{1'd0, 5'd19}: s1rd1 <= 28;
{1'd0, 5'd20}: s1rd1 <= 18;
{1'd0, 5'd21}: s1rd1 <= 26;
{1'd0, 5'd22}: s1rd1 <= 22;
{1'd0, 5'd23}: s1rd1 <= 30;
{1'd0, 5'd24}: s1rd1 <= 17;
{1'd0, 5'd25}: s1rd1 <= 25;
{1'd0, 5'd26}: s1rd1 <= 21;
{1'd0, 5'd27}: s1rd1 <= 29;
{1'd0, 5'd28}: s1rd1 <= 19;
{1'd0, 5'd29}: s1rd1 <= 27;
{1'd0, 5'd30}: s1rd1 <= 23;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet82443 sw(tm0_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm0_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm0_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
module memMod(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is block
reg [width-1:0] mem[depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule
module memMod_dist(in, out, inAddr, outAddr, writeSel, clk);
parameter depth=1024, width=16, logDepth=10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is distributed
reg [width-1:0] mem[depth-1:0];
always @(posedge clk) begin
out <= mem[outAddr];
if (writeSel)
mem[inAddr] <= in;
end
endmodule
module shiftRegFIFO(X, Y, clk);
parameter depth=1, width=1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @ (posedge clk) begin
for(index=1;index<depth;index=index+1) begin
mem[index] <= mem[index-1];
end
mem[0]<=X;
end
endmodule
module nextReg(X, Y, reset, clk);
parameter depth=2, logDepth=1;
output Y;
input X;
input clk, reset;
reg [logDepth:0] count;
reg active;
assign Y = (count == depth) ? 1 : 0;
always @ (posedge clk) begin
if (reset == 1) begin
count <= 0;
active <= 0;
end
else if (X == 1) begin
active <= 1;
count <= 1;
end
else if (count == depth) begin
count <= 0;
active <= 0;
end
else if (active)
count <= count+1;
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock82447(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85051(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a309;
wire signed [15:0] a310;
wire signed [15:0] a311;
wire signed [15:0] a312;
wire signed [15:0] t141;
wire signed [15:0] t142;
wire signed [15:0] t143;
wire signed [15:0] t144;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a309 = X0;
assign a310 = X2;
assign a311 = X1;
assign a312 = X3;
assign Y0 = t141;
assign Y1 = t142;
assign Y2 = t143;
assign Y3 = t144;
addfxp #(16, 1) add82459(.a(a309), .b(a310), .clk(clk), .q(t141)); // 0
addfxp #(16, 1) add82474(.a(a311), .b(a312), .clk(clk), .q(t142)); // 0
subfxp #(16, 1) sub82489(.a(a309), .b(a310), .clk(clk), .q(t143)); // 0
subfxp #(16, 1) sub82504(.a(a311), .b(a312), .clk(clk), .q(t144)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 8
// Gap: 2
module rc82529(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm82527 instPerm85052(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet82527(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [0:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
1'd0: control <= 1'b1;
1'd1: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 8
// Gap: 2
module perm82527(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 2;
parameter addrbits = 1;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm1;
assign tm1 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85057(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85058(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
shiftRegFIFO #(1, 1) shiftFIFO_85067(.X(next), .Y(next2), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85068(.X(next2), .Y(next3), .clk(clk));
shiftRegFIFO #(2, 1) shiftFIFO_85069(.X(next3), .Y(next4), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85070(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85073(.X(tm1), .Y(tm1_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85076(.X(tm1_d), .Y(tm1_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 1) shiftFIFO_85081(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm1_d, s1rdloc})
{1'd0, 1'd0}: s1rd0 <= 1;
{1'd0, 1'd1}: s1rd0 <= 0;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm1_d, s1rdloc})
{1'd0, 1'd0}: s1rd1 <= 0;
{1'd0, 1'd1}: s1rd1 <= 1;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet82527 sw(tm1_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm1_dd, writeCycle})
{1'd0, 1'd0}: s2wr0 <= 1;
{1'd0, 1'd1}: s2wr0 <= 0;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm1_dd, writeCycle})
{1'd0, 1'd0}: s2wr1 <= 0;
{1'd0, 1'd1}: s2wr1 <= 1;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 2
module DirSum_82710(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [0:0] i5;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i5 <= 0;
end
else begin
if (next == 1)
i5 <= 0;
else if (i5 == 1)
i5 <= 0;
else
i5 <= i5 + 1;
end
end
codeBlock82532 codeBlockIsnt85082(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i5_in(i5),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D18_82700(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h0;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D20_82708(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hc000;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock82532(clk, reset, next_in, next_out,
i5_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [0:0] i5_in;
reg [0:0] i5;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_85085(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a293;
wire signed [15:0] a282;
wire signed [15:0] a296;
wire signed [15:0] a286;
wire signed [15:0] a297;
wire signed [15:0] a298;
reg signed [15:0] tm137;
reg signed [15:0] tm141;
reg signed [15:0] tm153;
reg signed [15:0] tm160;
reg signed [15:0] tm138;
reg signed [15:0] tm142;
reg signed [15:0] tm154;
reg signed [15:0] tm161;
wire signed [15:0] tm4;
wire signed [15:0] a287;
wire signed [15:0] tm5;
wire signed [15:0] a289;
reg signed [15:0] tm139;
reg signed [15:0] tm143;
reg signed [15:0] tm155;
reg signed [15:0] tm162;
reg signed [15:0] tm31;
reg signed [15:0] tm32;
reg signed [15:0] tm140;
reg signed [15:0] tm144;
reg signed [15:0] tm156;
reg signed [15:0] tm163;
reg signed [15:0] tm157;
reg signed [15:0] tm164;
wire signed [15:0] a288;
wire signed [15:0] a290;
wire signed [15:0] a291;
wire signed [15:0] a292;
reg signed [15:0] tm158;
reg signed [15:0] tm165;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm159;
reg signed [15:0] tm166;
assign a293 = X0;
assign a282 = a293;
assign a296 = X1;
assign a286 = a296;
assign a297 = X2;
assign a298 = X3;
assign a287 = tm4;
assign a289 = tm5;
assign Y0 = tm159;
assign Y1 = tm166;
D18_82700 instD18inst0_82700(.addr(i5[0:0]), .out(tm4), .clk(clk));
D20_82708 instD20inst0_82708(.addr(i5[0:0]), .out(tm5), .clk(clk));
multfix #(16, 2) m82631(.a(tm31), .b(tm140), .clk(clk), .q_sc(a288), .q_unsc(), .rst(reset));
multfix #(16, 2) m82653(.a(tm32), .b(tm144), .clk(clk), .q_sc(a290), .q_unsc(), .rst(reset));
multfix #(16, 2) m82671(.a(tm32), .b(tm140), .clk(clk), .q_sc(a291), .q_unsc(), .rst(reset));
multfix #(16, 2) m82682(.a(tm31), .b(tm144), .clk(clk), .q_sc(a292), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub82660(.a(a288), .b(a290), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add82689(.a(a291), .b(a292), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm31 <= 0;
tm140 <= 0;
tm32 <= 0;
tm144 <= 0;
tm32 <= 0;
tm140 <= 0;
tm31 <= 0;
tm144 <= 0;
end
else begin
i5 <= i5_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm137 <= a297;
tm141 <= a298;
tm153 <= a282;
tm160 <= a286;
tm138 <= tm137;
tm142 <= tm141;
tm154 <= tm153;
tm161 <= tm160;
tm139 <= tm138;
tm143 <= tm142;
tm155 <= tm154;
tm162 <= tm161;
tm31 <= a287;
tm32 <= a289;
tm140 <= tm139;
tm144 <= tm143;
tm156 <= tm155;
tm163 <= tm162;
tm157 <= tm156;
tm164 <= tm163;
tm158 <= tm157;
tm165 <= tm164;
tm159 <= tm158;
tm166 <= tm165;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock82713(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85088(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a249;
wire signed [15:0] a250;
wire signed [15:0] a251;
wire signed [15:0] a252;
wire signed [15:0] t117;
wire signed [15:0] t118;
wire signed [15:0] t119;
wire signed [15:0] t120;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a249 = X0;
assign a250 = X2;
assign a251 = X1;
assign a252 = X3;
assign Y0 = t117;
assign Y1 = t118;
assign Y2 = t119;
assign Y3 = t120;
addfxp #(16, 1) add82725(.a(a249), .b(a250), .clk(clk), .q(t117)); // 0
addfxp #(16, 1) add82740(.a(a251), .b(a252), .clk(clk), .q(t118)); // 0
subfxp #(16, 1) sub82755(.a(a249), .b(a250), .clk(clk), .q(t119)); // 0
subfxp #(16, 1) sub82770(.a(a251), .b(a252), .clk(clk), .q(t120)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 12
// Gap: 4
module rc82795(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm82793 instPerm85089(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet82793(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [1:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
2'd0: control <= 1'b1;
2'd1: control <= 1'b1;
2'd2: control <= 1'b0;
2'd3: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 12
// Gap: 4
module perm82793(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 4;
parameter addrbits = 2;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm6;
assign tm6 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85094(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85095(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
shiftRegFIFO #(3, 1) shiftFIFO_85104(.X(next), .Y(next2), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85105(.X(next2), .Y(next3), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85106(.X(next3), .Y(next4), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85107(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85110(.X(tm6), .Y(tm6_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85113(.X(tm6_d), .Y(tm6_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 2) shiftFIFO_85118(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm6_d, s1rdloc})
{1'd0, 2'd0}: s1rd0 <= 2;
{1'd0, 2'd1}: s1rd0 <= 3;
{1'd0, 2'd2}: s1rd0 <= 0;
{1'd0, 2'd3}: s1rd0 <= 1;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm6_d, s1rdloc})
{1'd0, 2'd0}: s1rd1 <= 0;
{1'd0, 2'd1}: s1rd1 <= 1;
{1'd0, 2'd2}: s1rd1 <= 2;
{1'd0, 2'd3}: s1rd1 <= 3;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet82793 sw(tm6_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm6_dd, writeCycle})
{1'd0, 2'd0}: s2wr0 <= 2;
{1'd0, 2'd1}: s2wr0 <= 3;
{1'd0, 2'd2}: s2wr0 <= 0;
{1'd0, 2'd3}: s2wr0 <= 1;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm6_dd, writeCycle})
{1'd0, 2'd0}: s2wr1 <= 0;
{1'd0, 2'd1}: s2wr1 <= 1;
{1'd0, 2'd2}: s2wr1 <= 2;
{1'd0, 2'd3}: s2wr1 <= 3;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 4
module DirSum_82984(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [1:0] i4;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i4 <= 0;
end
else begin
if (next == 1)
i4 <= 0;
else if (i4 == 3)
i4 <= 0;
else
i4 <= i4 + 1;
end
end
codeBlock82798 codeBlockIsnt85119(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i4_in(i4),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D14_82970(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h2d41;
2: out3 <= 16'h0;
3: out3 <= 16'hd2bf;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D16_82982(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hd2bf;
2: out3 <= 16'hc000;
3: out3 <= 16'hd2bf;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock82798(clk, reset, next_in, next_out,
i4_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [1:0] i4_in;
reg [1:0] i4;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_85122(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a233;
wire signed [15:0] a222;
wire signed [15:0] a236;
wire signed [15:0] a226;
wire signed [15:0] a237;
wire signed [15:0] a238;
reg signed [15:0] tm167;
reg signed [15:0] tm171;
reg signed [15:0] tm183;
reg signed [15:0] tm190;
reg signed [15:0] tm168;
reg signed [15:0] tm172;
reg signed [15:0] tm184;
reg signed [15:0] tm191;
wire signed [15:0] tm9;
wire signed [15:0] a227;
wire signed [15:0] tm10;
wire signed [15:0] a229;
reg signed [15:0] tm169;
reg signed [15:0] tm173;
reg signed [15:0] tm185;
reg signed [15:0] tm192;
reg signed [15:0] tm39;
reg signed [15:0] tm40;
reg signed [15:0] tm170;
reg signed [15:0] tm174;
reg signed [15:0] tm186;
reg signed [15:0] tm193;
reg signed [15:0] tm187;
reg signed [15:0] tm194;
wire signed [15:0] a228;
wire signed [15:0] a230;
wire signed [15:0] a231;
wire signed [15:0] a232;
reg signed [15:0] tm188;
reg signed [15:0] tm195;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm189;
reg signed [15:0] tm196;
assign a233 = X0;
assign a222 = a233;
assign a236 = X1;
assign a226 = a236;
assign a237 = X2;
assign a238 = X3;
assign a227 = tm9;
assign a229 = tm10;
assign Y0 = tm189;
assign Y1 = tm196;
D14_82970 instD14inst0_82970(.addr(i4[1:0]), .out(tm9), .clk(clk));
D16_82982 instD16inst0_82982(.addr(i4[1:0]), .out(tm10), .clk(clk));
multfix #(16, 2) m82897(.a(tm39), .b(tm170), .clk(clk), .q_sc(a228), .q_unsc(), .rst(reset));
multfix #(16, 2) m82919(.a(tm40), .b(tm174), .clk(clk), .q_sc(a230), .q_unsc(), .rst(reset));
multfix #(16, 2) m82937(.a(tm40), .b(tm170), .clk(clk), .q_sc(a231), .q_unsc(), .rst(reset));
multfix #(16, 2) m82948(.a(tm39), .b(tm174), .clk(clk), .q_sc(a232), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub82926(.a(a228), .b(a230), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add82955(.a(a231), .b(a232), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm39 <= 0;
tm170 <= 0;
tm40 <= 0;
tm174 <= 0;
tm40 <= 0;
tm170 <= 0;
tm39 <= 0;
tm174 <= 0;
end
else begin
i4 <= i4_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm167 <= a237;
tm171 <= a238;
tm183 <= a222;
tm190 <= a226;
tm168 <= tm167;
tm172 <= tm171;
tm184 <= tm183;
tm191 <= tm190;
tm169 <= tm168;
tm173 <= tm172;
tm185 <= tm184;
tm192 <= tm191;
tm39 <= a227;
tm40 <= a229;
tm170 <= tm169;
tm174 <= tm173;
tm186 <= tm185;
tm193 <= tm192;
tm187 <= tm186;
tm194 <= tm193;
tm188 <= tm187;
tm195 <= tm194;
tm189 <= tm188;
tm196 <= tm195;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock82987(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85125(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a189;
wire signed [15:0] a190;
wire signed [15:0] a191;
wire signed [15:0] a192;
wire signed [15:0] t93;
wire signed [15:0] t94;
wire signed [15:0] t95;
wire signed [15:0] t96;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a189 = X0;
assign a190 = X2;
assign a191 = X1;
assign a192 = X3;
assign Y0 = t93;
assign Y1 = t94;
assign Y2 = t95;
assign Y3 = t96;
addfxp #(16, 1) add82999(.a(a189), .b(a190), .clk(clk), .q(t93)); // 0
addfxp #(16, 1) add83014(.a(a191), .b(a192), .clk(clk), .q(t94)); // 0
subfxp #(16, 1) sub83029(.a(a189), .b(a190), .clk(clk), .q(t95)); // 0
subfxp #(16, 1) sub83044(.a(a191), .b(a192), .clk(clk), .q(t96)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 20
// Gap: 8
module rc83069(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm83067 instPerm85126(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet83067(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [2:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
3'd0: control <= 1'b1;
3'd1: control <= 1'b1;
3'd2: control <= 1'b1;
3'd3: control <= 1'b1;
3'd4: control <= 1'b0;
3'd5: control <= 1'b0;
3'd6: control <= 1'b0;
3'd7: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 20
// Gap: 8
module perm83067(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 8;
parameter addrbits = 3;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm11;
assign tm11 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85131(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85132(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
shiftRegFIFO #(7, 1) shiftFIFO_85141(.X(next), .Y(next2), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85142(.X(next2), .Y(next3), .clk(clk));
shiftRegFIFO #(8, 1) shiftFIFO_85143(.X(next3), .Y(next4), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85144(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(7, 1) shiftFIFO_85147(.X(tm11), .Y(tm11_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85150(.X(tm11_d), .Y(tm11_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 3) shiftFIFO_85155(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm11_d, s1rdloc})
{1'd0, 3'd0}: s1rd0 <= 4;
{1'd0, 3'd1}: s1rd0 <= 5;
{1'd0, 3'd2}: s1rd0 <= 6;
{1'd0, 3'd3}: s1rd0 <= 7;
{1'd0, 3'd4}: s1rd0 <= 0;
{1'd0, 3'd5}: s1rd0 <= 1;
{1'd0, 3'd6}: s1rd0 <= 2;
{1'd0, 3'd7}: s1rd0 <= 3;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm11_d, s1rdloc})
{1'd0, 3'd0}: s1rd1 <= 0;
{1'd0, 3'd1}: s1rd1 <= 1;
{1'd0, 3'd2}: s1rd1 <= 2;
{1'd0, 3'd3}: s1rd1 <= 3;
{1'd0, 3'd4}: s1rd1 <= 4;
{1'd0, 3'd5}: s1rd1 <= 5;
{1'd0, 3'd6}: s1rd1 <= 6;
{1'd0, 3'd7}: s1rd1 <= 7;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet83067 sw(tm11_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm11_dd, writeCycle})
{1'd0, 3'd0}: s2wr0 <= 4;
{1'd0, 3'd1}: s2wr0 <= 5;
{1'd0, 3'd2}: s2wr0 <= 6;
{1'd0, 3'd3}: s2wr0 <= 7;
{1'd0, 3'd4}: s2wr0 <= 0;
{1'd0, 3'd5}: s2wr0 <= 1;
{1'd0, 3'd6}: s2wr0 <= 2;
{1'd0, 3'd7}: s2wr0 <= 3;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm11_dd, writeCycle})
{1'd0, 3'd0}: s2wr1 <= 0;
{1'd0, 3'd1}: s2wr1 <= 1;
{1'd0, 3'd2}: s2wr1 <= 2;
{1'd0, 3'd3}: s2wr1 <= 3;
{1'd0, 3'd4}: s2wr1 <= 4;
{1'd0, 3'd5}: s2wr1 <= 5;
{1'd0, 3'd6}: s2wr1 <= 6;
{1'd0, 3'd7}: s2wr1 <= 7;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 8
module DirSum_83274(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [2:0] i3;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i3 <= 0;
end
else begin
if (next == 1)
i3 <= 0;
else if (i3 == 7)
i3 <= 0;
else
i3 <= i3 + 1;
end
end
codeBlock83072 codeBlockIsnt85156(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i3_in(i3),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D10_83252(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [2:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3b21;
2: out3 <= 16'h2d41;
3: out3 <= 16'h187e;
4: out3 <= 16'h0;
5: out3 <= 16'he782;
6: out3 <= 16'hd2bf;
7: out3 <= 16'hc4df;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D12_83272(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [2:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'he782;
2: out3 <= 16'hd2bf;
3: out3 <= 16'hc4df;
4: out3 <= 16'hc000;
5: out3 <= 16'hc4df;
6: out3 <= 16'hd2bf;
7: out3 <= 16'he782;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock83072(clk, reset, next_in, next_out,
i3_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [2:0] i3_in;
reg [2:0] i3;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_85159(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a173;
wire signed [15:0] a162;
wire signed [15:0] a176;
wire signed [15:0] a166;
wire signed [15:0] a177;
wire signed [15:0] a178;
reg signed [15:0] tm197;
reg signed [15:0] tm201;
reg signed [15:0] tm213;
reg signed [15:0] tm220;
reg signed [15:0] tm198;
reg signed [15:0] tm202;
reg signed [15:0] tm214;
reg signed [15:0] tm221;
wire signed [15:0] tm14;
wire signed [15:0] a167;
wire signed [15:0] tm15;
wire signed [15:0] a169;
reg signed [15:0] tm199;
reg signed [15:0] tm203;
reg signed [15:0] tm215;
reg signed [15:0] tm222;
reg signed [15:0] tm47;
reg signed [15:0] tm48;
reg signed [15:0] tm200;
reg signed [15:0] tm204;
reg signed [15:0] tm216;
reg signed [15:0] tm223;
reg signed [15:0] tm217;
reg signed [15:0] tm224;
wire signed [15:0] a168;
wire signed [15:0] a170;
wire signed [15:0] a171;
wire signed [15:0] a172;
reg signed [15:0] tm218;
reg signed [15:0] tm225;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm219;
reg signed [15:0] tm226;
assign a173 = X0;
assign a162 = a173;
assign a176 = X1;
assign a166 = a176;
assign a177 = X2;
assign a178 = X3;
assign a167 = tm14;
assign a169 = tm15;
assign Y0 = tm219;
assign Y1 = tm226;
D10_83252 instD10inst0_83252(.addr(i3[2:0]), .out(tm14), .clk(clk));
D12_83272 instD12inst0_83272(.addr(i3[2:0]), .out(tm15), .clk(clk));
multfix #(16, 2) m83171(.a(tm47), .b(tm200), .clk(clk), .q_sc(a168), .q_unsc(), .rst(reset));
multfix #(16, 2) m83193(.a(tm48), .b(tm204), .clk(clk), .q_sc(a170), .q_unsc(), .rst(reset));
multfix #(16, 2) m83211(.a(tm48), .b(tm200), .clk(clk), .q_sc(a171), .q_unsc(), .rst(reset));
multfix #(16, 2) m83222(.a(tm47), .b(tm204), .clk(clk), .q_sc(a172), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub83200(.a(a168), .b(a170), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add83229(.a(a171), .b(a172), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm47 <= 0;
tm200 <= 0;
tm48 <= 0;
tm204 <= 0;
tm48 <= 0;
tm200 <= 0;
tm47 <= 0;
tm204 <= 0;
end
else begin
i3 <= i3_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm197 <= a177;
tm201 <= a178;
tm213 <= a162;
tm220 <= a166;
tm198 <= tm197;
tm202 <= tm201;
tm214 <= tm213;
tm221 <= tm220;
tm199 <= tm198;
tm203 <= tm202;
tm215 <= tm214;
tm222 <= tm221;
tm47 <= a167;
tm48 <= a169;
tm200 <= tm199;
tm204 <= tm203;
tm216 <= tm215;
tm223 <= tm222;
tm217 <= tm216;
tm224 <= tm223;
tm218 <= tm217;
tm225 <= tm224;
tm219 <= tm218;
tm226 <= tm225;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock83277(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85162(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a129;
wire signed [15:0] a130;
wire signed [15:0] a131;
wire signed [15:0] a132;
wire signed [15:0] t69;
wire signed [15:0] t70;
wire signed [15:0] t71;
wire signed [15:0] t72;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a129 = X0;
assign a130 = X2;
assign a131 = X1;
assign a132 = X3;
assign Y0 = t69;
assign Y1 = t70;
assign Y2 = t71;
assign Y3 = t72;
addfxp #(16, 1) add83289(.a(a129), .b(a130), .clk(clk), .q(t69)); // 0
addfxp #(16, 1) add83304(.a(a131), .b(a132), .clk(clk), .q(t70)); // 0
subfxp #(16, 1) sub83319(.a(a129), .b(a130), .clk(clk), .q(t71)); // 0
subfxp #(16, 1) sub83334(.a(a131), .b(a132), .clk(clk), .q(t72)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 36
// Gap: 16
module rc83359(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm83357 instPerm85163(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet83357(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [3:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
4'd0: control <= 1'b1;
4'd1: control <= 1'b1;
4'd2: control <= 1'b1;
4'd3: control <= 1'b1;
4'd4: control <= 1'b1;
4'd5: control <= 1'b1;
4'd6: control <= 1'b1;
4'd7: control <= 1'b1;
4'd8: control <= 1'b0;
4'd9: control <= 1'b0;
4'd10: control <= 1'b0;
4'd11: control <= 1'b0;
4'd12: control <= 1'b0;
4'd13: control <= 1'b0;
4'd14: control <= 1'b0;
4'd15: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 36
// Gap: 16
module perm83357(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 16;
parameter addrbits = 4;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm16;
assign tm16 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85168(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85169(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(15, 4) nextReg_85180(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85181(.X(next2), .Y(next3), .clk(clk));
nextReg #(16, 4) nextReg_85184(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85185(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(15, 1) shiftFIFO_85188(.X(tm16), .Y(tm16_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85191(.X(tm16_d), .Y(tm16_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 4) shiftFIFO_85196(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm16_d, s1rdloc})
{1'd0, 4'd0}: s1rd0 <= 8;
{1'd0, 4'd1}: s1rd0 <= 9;
{1'd0, 4'd2}: s1rd0 <= 10;
{1'd0, 4'd3}: s1rd0 <= 11;
{1'd0, 4'd4}: s1rd0 <= 12;
{1'd0, 4'd5}: s1rd0 <= 13;
{1'd0, 4'd6}: s1rd0 <= 14;
{1'd0, 4'd7}: s1rd0 <= 15;
{1'd0, 4'd8}: s1rd0 <= 0;
{1'd0, 4'd9}: s1rd0 <= 1;
{1'd0, 4'd10}: s1rd0 <= 2;
{1'd0, 4'd11}: s1rd0 <= 3;
{1'd0, 4'd12}: s1rd0 <= 4;
{1'd0, 4'd13}: s1rd0 <= 5;
{1'd0, 4'd14}: s1rd0 <= 6;
{1'd0, 4'd15}: s1rd0 <= 7;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm16_d, s1rdloc})
{1'd0, 4'd0}: s1rd1 <= 0;
{1'd0, 4'd1}: s1rd1 <= 1;
{1'd0, 4'd2}: s1rd1 <= 2;
{1'd0, 4'd3}: s1rd1 <= 3;
{1'd0, 4'd4}: s1rd1 <= 4;
{1'd0, 4'd5}: s1rd1 <= 5;
{1'd0, 4'd6}: s1rd1 <= 6;
{1'd0, 4'd7}: s1rd1 <= 7;
{1'd0, 4'd8}: s1rd1 <= 8;
{1'd0, 4'd9}: s1rd1 <= 9;
{1'd0, 4'd10}: s1rd1 <= 10;
{1'd0, 4'd11}: s1rd1 <= 11;
{1'd0, 4'd12}: s1rd1 <= 12;
{1'd0, 4'd13}: s1rd1 <= 13;
{1'd0, 4'd14}: s1rd1 <= 14;
{1'd0, 4'd15}: s1rd1 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet83357 sw(tm16_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm16_dd, writeCycle})
{1'd0, 4'd0}: s2wr0 <= 8;
{1'd0, 4'd1}: s2wr0 <= 9;
{1'd0, 4'd2}: s2wr0 <= 10;
{1'd0, 4'd3}: s2wr0 <= 11;
{1'd0, 4'd4}: s2wr0 <= 12;
{1'd0, 4'd5}: s2wr0 <= 13;
{1'd0, 4'd6}: s2wr0 <= 14;
{1'd0, 4'd7}: s2wr0 <= 15;
{1'd0, 4'd8}: s2wr0 <= 0;
{1'd0, 4'd9}: s2wr0 <= 1;
{1'd0, 4'd10}: s2wr0 <= 2;
{1'd0, 4'd11}: s2wr0 <= 3;
{1'd0, 4'd12}: s2wr0 <= 4;
{1'd0, 4'd13}: s2wr0 <= 5;
{1'd0, 4'd14}: s2wr0 <= 6;
{1'd0, 4'd15}: s2wr0 <= 7;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm16_dd, writeCycle})
{1'd0, 4'd0}: s2wr1 <= 0;
{1'd0, 4'd1}: s2wr1 <= 1;
{1'd0, 4'd2}: s2wr1 <= 2;
{1'd0, 4'd3}: s2wr1 <= 3;
{1'd0, 4'd4}: s2wr1 <= 4;
{1'd0, 4'd5}: s2wr1 <= 5;
{1'd0, 4'd6}: s2wr1 <= 6;
{1'd0, 4'd7}: s2wr1 <= 7;
{1'd0, 4'd8}: s2wr1 <= 8;
{1'd0, 4'd9}: s2wr1 <= 9;
{1'd0, 4'd10}: s2wr1 <= 10;
{1'd0, 4'd11}: s2wr1 <= 11;
{1'd0, 4'd12}: s2wr1 <= 12;
{1'd0, 4'd13}: s2wr1 <= 13;
{1'd0, 4'd14}: s2wr1 <= 14;
{1'd0, 4'd15}: s2wr1 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 16
module DirSum_83596(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [3:0] i2;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i2 <= 0;
end
else begin
if (next == 1)
i2 <= 0;
else if (i2 == 15)
i2 <= 0;
else
i2 <= i2 + 1;
end
end
codeBlock83362 codeBlockIsnt85201(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i2_in(i2),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D6_83558(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3ec5;
2: out3 <= 16'h3b21;
3: out3 <= 16'h3537;
4: out3 <= 16'h2d41;
5: out3 <= 16'h238e;
6: out3 <= 16'h187e;
7: out3 <= 16'hc7c;
8: out3 <= 16'h0;
9: out3 <= 16'hf384;
10: out3 <= 16'he782;
11: out3 <= 16'hdc72;
12: out3 <= 16'hd2bf;
13: out3 <= 16'hcac9;
14: out3 <= 16'hc4df;
15: out3 <= 16'hc13b;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D8_83594(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [3:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hf384;
2: out3 <= 16'he782;
3: out3 <= 16'hdc72;
4: out3 <= 16'hd2bf;
5: out3 <= 16'hcac9;
6: out3 <= 16'hc4df;
7: out3 <= 16'hc13b;
8: out3 <= 16'hc000;
9: out3 <= 16'hc13b;
10: out3 <= 16'hc4df;
11: out3 <= 16'hcac9;
12: out3 <= 16'hd2bf;
13: out3 <= 16'hdc72;
14: out3 <= 16'he782;
15: out3 <= 16'hf384;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock83362(clk, reset, next_in, next_out,
i2_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [3:0] i2_in;
reg [3:0] i2;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_85204(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a113;
wire signed [15:0] a102;
wire signed [15:0] a116;
wire signed [15:0] a106;
wire signed [15:0] a117;
wire signed [15:0] a118;
reg signed [15:0] tm227;
reg signed [15:0] tm231;
reg signed [15:0] tm243;
reg signed [15:0] tm250;
reg signed [15:0] tm228;
reg signed [15:0] tm232;
reg signed [15:0] tm244;
reg signed [15:0] tm251;
wire signed [15:0] tm19;
wire signed [15:0] a107;
wire signed [15:0] tm20;
wire signed [15:0] a109;
reg signed [15:0] tm229;
reg signed [15:0] tm233;
reg signed [15:0] tm245;
reg signed [15:0] tm252;
reg signed [15:0] tm55;
reg signed [15:0] tm56;
reg signed [15:0] tm230;
reg signed [15:0] tm234;
reg signed [15:0] tm246;
reg signed [15:0] tm253;
reg signed [15:0] tm247;
reg signed [15:0] tm254;
wire signed [15:0] a108;
wire signed [15:0] a110;
wire signed [15:0] a111;
wire signed [15:0] a112;
reg signed [15:0] tm248;
reg signed [15:0] tm255;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm249;
reg signed [15:0] tm256;
assign a113 = X0;
assign a102 = a113;
assign a116 = X1;
assign a106 = a116;
assign a117 = X2;
assign a118 = X3;
assign a107 = tm19;
assign a109 = tm20;
assign Y0 = tm249;
assign Y1 = tm256;
D6_83558 instD6inst0_83558(.addr(i2[3:0]), .out(tm19), .clk(clk));
D8_83594 instD8inst0_83594(.addr(i2[3:0]), .out(tm20), .clk(clk));
multfix #(16, 2) m83461(.a(tm55), .b(tm230), .clk(clk), .q_sc(a108), .q_unsc(), .rst(reset));
multfix #(16, 2) m83483(.a(tm56), .b(tm234), .clk(clk), .q_sc(a110), .q_unsc(), .rst(reset));
multfix #(16, 2) m83501(.a(tm56), .b(tm230), .clk(clk), .q_sc(a111), .q_unsc(), .rst(reset));
multfix #(16, 2) m83512(.a(tm55), .b(tm234), .clk(clk), .q_sc(a112), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub83490(.a(a108), .b(a110), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add83519(.a(a111), .b(a112), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm55 <= 0;
tm230 <= 0;
tm56 <= 0;
tm234 <= 0;
tm56 <= 0;
tm230 <= 0;
tm55 <= 0;
tm234 <= 0;
end
else begin
i2 <= i2_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm227 <= a117;
tm231 <= a118;
tm243 <= a102;
tm250 <= a106;
tm228 <= tm227;
tm232 <= tm231;
tm244 <= tm243;
tm251 <= tm250;
tm229 <= tm228;
tm233 <= tm232;
tm245 <= tm244;
tm252 <= tm251;
tm55 <= a107;
tm56 <= a109;
tm230 <= tm229;
tm234 <= tm233;
tm246 <= tm245;
tm253 <= tm252;
tm247 <= tm246;
tm254 <= tm253;
tm248 <= tm247;
tm255 <= tm254;
tm249 <= tm248;
tm256 <= tm255;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock83599(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85207(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a69;
wire signed [15:0] a70;
wire signed [15:0] a71;
wire signed [15:0] a72;
wire signed [15:0] t45;
wire signed [15:0] t46;
wire signed [15:0] t47;
wire signed [15:0] t48;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a69 = X0;
assign a70 = X2;
assign a71 = X1;
assign a72 = X3;
assign Y0 = t45;
assign Y1 = t46;
assign Y2 = t47;
assign Y3 = t48;
addfxp #(16, 1) add83611(.a(a69), .b(a70), .clk(clk), .q(t45)); // 0
addfxp #(16, 1) add83626(.a(a71), .b(a72), .clk(clk), .q(t46)); // 0
subfxp #(16, 1) sub83641(.a(a69), .b(a70), .clk(clk), .q(t47)); // 0
subfxp #(16, 1) sub83656(.a(a71), .b(a72), .clk(clk), .q(t48)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 68
// Gap: 32
module rc83681(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm83679 instPerm85208(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet83679(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm83679(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter addrbits = 5;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm21;
assign tm21 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85213(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85214(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(31, 5) nextReg_85225(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85226(.X(next2), .Y(next3), .clk(clk));
nextReg #(32, 5) nextReg_85229(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85230(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(31, 1) shiftFIFO_85233(.X(tm21), .Y(tm21_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85236(.X(tm21_d), .Y(tm21_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 5) shiftFIFO_85241(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm21_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 16;
{1'd0, 5'd1}: s1rd0 <= 17;
{1'd0, 5'd2}: s1rd0 <= 18;
{1'd0, 5'd3}: s1rd0 <= 19;
{1'd0, 5'd4}: s1rd0 <= 20;
{1'd0, 5'd5}: s1rd0 <= 21;
{1'd0, 5'd6}: s1rd0 <= 22;
{1'd0, 5'd7}: s1rd0 <= 23;
{1'd0, 5'd8}: s1rd0 <= 24;
{1'd0, 5'd9}: s1rd0 <= 25;
{1'd0, 5'd10}: s1rd0 <= 26;
{1'd0, 5'd11}: s1rd0 <= 27;
{1'd0, 5'd12}: s1rd0 <= 28;
{1'd0, 5'd13}: s1rd0 <= 29;
{1'd0, 5'd14}: s1rd0 <= 30;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 1;
{1'd0, 5'd18}: s1rd0 <= 2;
{1'd0, 5'd19}: s1rd0 <= 3;
{1'd0, 5'd20}: s1rd0 <= 4;
{1'd0, 5'd21}: s1rd0 <= 5;
{1'd0, 5'd22}: s1rd0 <= 6;
{1'd0, 5'd23}: s1rd0 <= 7;
{1'd0, 5'd24}: s1rd0 <= 8;
{1'd0, 5'd25}: s1rd0 <= 9;
{1'd0, 5'd26}: s1rd0 <= 10;
{1'd0, 5'd27}: s1rd0 <= 11;
{1'd0, 5'd28}: s1rd0 <= 12;
{1'd0, 5'd29}: s1rd0 <= 13;
{1'd0, 5'd30}: s1rd0 <= 14;
{1'd0, 5'd31}: s1rd0 <= 15;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm21_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 1;
{1'd0, 5'd2}: s1rd1 <= 2;
{1'd0, 5'd3}: s1rd1 <= 3;
{1'd0, 5'd4}: s1rd1 <= 4;
{1'd0, 5'd5}: s1rd1 <= 5;
{1'd0, 5'd6}: s1rd1 <= 6;
{1'd0, 5'd7}: s1rd1 <= 7;
{1'd0, 5'd8}: s1rd1 <= 8;
{1'd0, 5'd9}: s1rd1 <= 9;
{1'd0, 5'd10}: s1rd1 <= 10;
{1'd0, 5'd11}: s1rd1 <= 11;
{1'd0, 5'd12}: s1rd1 <= 12;
{1'd0, 5'd13}: s1rd1 <= 13;
{1'd0, 5'd14}: s1rd1 <= 14;
{1'd0, 5'd15}: s1rd1 <= 15;
{1'd0, 5'd16}: s1rd1 <= 16;
{1'd0, 5'd17}: s1rd1 <= 17;
{1'd0, 5'd18}: s1rd1 <= 18;
{1'd0, 5'd19}: s1rd1 <= 19;
{1'd0, 5'd20}: s1rd1 <= 20;
{1'd0, 5'd21}: s1rd1 <= 21;
{1'd0, 5'd22}: s1rd1 <= 22;
{1'd0, 5'd23}: s1rd1 <= 23;
{1'd0, 5'd24}: s1rd1 <= 24;
{1'd0, 5'd25}: s1rd1 <= 25;
{1'd0, 5'd26}: s1rd1 <= 26;
{1'd0, 5'd27}: s1rd1 <= 27;
{1'd0, 5'd28}: s1rd1 <= 28;
{1'd0, 5'd29}: s1rd1 <= 29;
{1'd0, 5'd30}: s1rd1 <= 30;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet83679 sw(tm21_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm21_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm21_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
// Latency: 8
// Gap: 32
module DirSum_83981(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
reg [4:0] i1;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
always @(posedge clk) begin
if (reset == 1) begin
i1 <= 0;
end
else begin
if (next == 1)
i1 <= 0;
else if (i1 == 31)
i1 <= 0;
else
i1 <= i1 + 1;
end
end
codeBlock83683 codeBlockIsnt85246(.clk(clk), .reset(reset), .next_in(next), .next_out(next_out),
.i1_in(i1),
.X0_in(X0), .Y0(Y0),
.X1_in(X1), .Y1(Y1),
.X2_in(X2), .Y2(Y2),
.X3_in(X3), .Y3(Y3));
endmodule
module D2_83911(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [4:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h3fb1;
2: out3 <= 16'h3ec5;
3: out3 <= 16'h3d3f;
4: out3 <= 16'h3b21;
5: out3 <= 16'h3871;
6: out3 <= 16'h3537;
7: out3 <= 16'h3179;
8: out3 <= 16'h2d41;
9: out3 <= 16'h289a;
10: out3 <= 16'h238e;
11: out3 <= 16'h1e2b;
12: out3 <= 16'h187e;
13: out3 <= 16'h1294;
14: out3 <= 16'hc7c;
15: out3 <= 16'h646;
16: out3 <= 16'h0;
17: out3 <= 16'hf9ba;
18: out3 <= 16'hf384;
19: out3 <= 16'hed6c;
20: out3 <= 16'he782;
21: out3 <= 16'he1d5;
22: out3 <= 16'hdc72;
23: out3 <= 16'hd766;
24: out3 <= 16'hd2bf;
25: out3 <= 16'hce87;
26: out3 <= 16'hcac9;
27: out3 <= 16'hc78f;
28: out3 <= 16'hc4df;
29: out3 <= 16'hc2c1;
30: out3 <= 16'hc13b;
31: out3 <= 16'hc04f;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
module D4_83979(addr, out, clk);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [4:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case(addr)
0: out3 <= 16'h0;
1: out3 <= 16'hf9ba;
2: out3 <= 16'hf384;
3: out3 <= 16'hed6c;
4: out3 <= 16'he782;
5: out3 <= 16'he1d5;
6: out3 <= 16'hdc72;
7: out3 <= 16'hd766;
8: out3 <= 16'hd2bf;
9: out3 <= 16'hce87;
10: out3 <= 16'hcac9;
11: out3 <= 16'hc78f;
12: out3 <= 16'hc4df;
13: out3 <= 16'hc2c1;
14: out3 <= 16'hc13b;
15: out3 <= 16'hc04f;
16: out3 <= 16'hc000;
17: out3 <= 16'hc04f;
18: out3 <= 16'hc13b;
19: out3 <= 16'hc2c1;
20: out3 <= 16'hc4df;
21: out3 <= 16'hc78f;
22: out3 <= 16'hcac9;
23: out3 <= 16'hce87;
24: out3 <= 16'hd2bf;
25: out3 <= 16'hd766;
26: out3 <= 16'hdc72;
27: out3 <= 16'he1d5;
28: out3 <= 16'he782;
29: out3 <= 16'hed6c;
30: out3 <= 16'hf384;
31: out3 <= 16'hf9ba;
default: out3 <= 0;
endcase
end
// synthesis attribute rom_style of out3 is "block"
endmodule
// Latency: 8
// Gap: 1
module codeBlock83683(clk, reset, next_in, next_out,
i1_in,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [4:0] i1_in;
reg [4:0] i1;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(7, 1) shiftFIFO_85249(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a53;
wire signed [15:0] a42;
wire signed [15:0] a56;
wire signed [15:0] a46;
wire signed [15:0] a57;
wire signed [15:0] a58;
reg signed [15:0] tm257;
reg signed [15:0] tm261;
reg signed [15:0] tm273;
reg signed [15:0] tm280;
reg signed [15:0] tm258;
reg signed [15:0] tm262;
reg signed [15:0] tm274;
reg signed [15:0] tm281;
wire signed [15:0] tm24;
wire signed [15:0] a47;
wire signed [15:0] tm25;
wire signed [15:0] a49;
reg signed [15:0] tm259;
reg signed [15:0] tm263;
reg signed [15:0] tm275;
reg signed [15:0] tm282;
reg signed [15:0] tm63;
reg signed [15:0] tm64;
reg signed [15:0] tm260;
reg signed [15:0] tm264;
reg signed [15:0] tm276;
reg signed [15:0] tm283;
reg signed [15:0] tm277;
reg signed [15:0] tm284;
wire signed [15:0] a48;
wire signed [15:0] a50;
wire signed [15:0] a51;
wire signed [15:0] a52;
reg signed [15:0] tm278;
reg signed [15:0] tm285;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
reg signed [15:0] tm279;
reg signed [15:0] tm286;
assign a53 = X0;
assign a42 = a53;
assign a56 = X1;
assign a46 = a56;
assign a57 = X2;
assign a58 = X3;
assign a47 = tm24;
assign a49 = tm25;
assign Y0 = tm279;
assign Y1 = tm286;
D2_83911 instD2inst0_83911(.addr(i1[4:0]), .out(tm24), .clk(clk));
D4_83979 instD4inst0_83979(.addr(i1[4:0]), .out(tm25), .clk(clk));
multfix #(16, 2) m83782(.a(tm63), .b(tm260), .clk(clk), .q_sc(a48), .q_unsc(), .rst(reset));
multfix #(16, 2) m83804(.a(tm64), .b(tm264), .clk(clk), .q_sc(a50), .q_unsc(), .rst(reset));
multfix #(16, 2) m83822(.a(tm64), .b(tm260), .clk(clk), .q_sc(a51), .q_unsc(), .rst(reset));
multfix #(16, 2) m83833(.a(tm63), .b(tm264), .clk(clk), .q_sc(a52), .q_unsc(), .rst(reset));
subfxp #(16, 1) sub83811(.a(a48), .b(a50), .clk(clk), .q(Y2)); // 6
addfxp #(16, 1) add83840(.a(a51), .b(a52), .clk(clk), .q(Y3)); // 6
always @(posedge clk) begin
if (reset == 1) begin
tm63 <= 0;
tm260 <= 0;
tm64 <= 0;
tm264 <= 0;
tm64 <= 0;
tm260 <= 0;
tm63 <= 0;
tm264 <= 0;
end
else begin
i1 <= i1_in;
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
tm257 <= a57;
tm261 <= a58;
tm273 <= a42;
tm280 <= a46;
tm258 <= tm257;
tm262 <= tm261;
tm274 <= tm273;
tm281 <= tm280;
tm259 <= tm258;
tm263 <= tm262;
tm275 <= tm274;
tm282 <= tm281;
tm63 <= a47;
tm64 <= a49;
tm260 <= tm259;
tm264 <= tm263;
tm276 <= tm275;
tm283 <= tm282;
tm277 <= tm276;
tm284 <= tm283;
tm278 <= tm277;
tm285 <= tm284;
tm279 <= tm278;
tm286 <= tm285;
end
end
endmodule
// Latency: 2
// Gap: 1
module codeBlock83984(clk, reset, next_in, next_out,
X0_in, Y0,
X1_in, Y1,
X2_in, Y2,
X3_in, Y3);
output next_out;
input clk, reset, next_in;
reg next;
input [15:0] X0_in,
X1_in,
X2_in,
X3_in;
reg [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
shiftRegFIFO #(1, 1) shiftFIFO_85252(.X(next), .Y(next_out), .clk(clk));
wire signed [15:0] a9;
wire signed [15:0] a10;
wire signed [15:0] a11;
wire signed [15:0] a12;
wire signed [15:0] t21;
wire signed [15:0] t22;
wire signed [15:0] t23;
wire signed [15:0] t24;
wire signed [15:0] Y0;
wire signed [15:0] Y1;
wire signed [15:0] Y2;
wire signed [15:0] Y3;
assign a9 = X0;
assign a10 = X2;
assign a11 = X1;
assign a12 = X3;
assign Y0 = t21;
assign Y1 = t22;
assign Y2 = t23;
assign Y3 = t24;
addfxp #(16, 1) add83996(.a(a9), .b(a10), .clk(clk), .q(t21)); // 0
addfxp #(16, 1) add84011(.a(a11), .b(a12), .clk(clk), .q(t22)); // 0
subfxp #(16, 1) sub84026(.a(a9), .b(a10), .clk(clk), .q(t23)); // 0
subfxp #(16, 1) sub84041(.a(a11), .b(a12), .clk(clk), .q(t24)); // 0
always @(posedge clk) begin
if (reset == 1) begin
end
else begin
X0 <= X0_in;
X1 <= X1_in;
X2 <= X2_in;
X3 <= X3_in;
next <= next_in;
end
end
endmodule
// Latency: 68
// Gap: 32
module rc84066(clk, reset, next, next_out,
X0, Y0,
X1, Y1,
X2, Y2,
X3, Y3);
output next_out;
input clk, reset, next;
input [15:0] X0,
X1,
X2,
X3;
output [15:0] Y0,
Y1,
Y2,
Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
wire [31:0] s1;
assign t1 = {X2, X3};
assign Y0 = s0[31:16];
assign Y1 = s0[15:0];
assign Y2 = s1[31:16];
assign Y3 = s1[15:0];
perm84064 instPerm85253(.x0(t0), .y0(s0),
.x1(t1), .y1(s1),
.clk(clk), .next(next), .next_out(next_out), .reset(reset)
);
endmodule
module swNet84064(itr, clk, ct
, x0, y0
, x1, y1
);
parameter width = 32;
input [4:0] ct;
input clk;
input [0:0] itr;
input [width-1:0] x0;
output reg [width-1:0] y0;
input [width-1:0] x1;
output reg [width-1:0] y1;
wire [width-1:0] t0_0, t0_1;
reg [width-1:0] t1_0, t1_1;
reg [0:0] control;
always @(posedge clk) begin
case(ct)
5'd0: control <= 1'b1;
5'd1: control <= 1'b1;
5'd2: control <= 1'b1;
5'd3: control <= 1'b1;
5'd4: control <= 1'b1;
5'd5: control <= 1'b1;
5'd6: control <= 1'b1;
5'd7: control <= 1'b1;
5'd8: control <= 1'b1;
5'd9: control <= 1'b1;
5'd10: control <= 1'b1;
5'd11: control <= 1'b1;
5'd12: control <= 1'b1;
5'd13: control <= 1'b1;
5'd14: control <= 1'b1;
5'd15: control <= 1'b1;
5'd16: control <= 1'b0;
5'd17: control <= 1'b0;
5'd18: control <= 1'b0;
5'd19: control <= 1'b0;
5'd20: control <= 1'b0;
5'd21: control <= 1'b0;
5'd22: control <= 1'b0;
5'd23: control <= 1'b0;
5'd24: control <= 1'b0;
5'd25: control <= 1'b0;
5'd26: control <= 1'b0;
5'd27: control <= 1'b0;
5'd28: control <= 1'b0;
5'd29: control <= 1'b0;
5'd30: control <= 1'b0;
5'd31: control <= 1'b0;
endcase
end
// synthesis attribute rom_style of control is "distributed"
reg [0:0] control0;
always @(posedge clk) begin
control0 <= control;
end
assign t0_0 = x0;
assign t0_1 = x1;
always @(posedge clk) begin
t1_0 <= (control0[0] == 0) ? t0_0 : t0_1;
t1_1 <= (control0[0] == 0) ? t0_1 : t0_0;
end
always @(posedge clk) begin
y0 <= t1_0;
y1 <= t1_1;
end
endmodule
// Latency: 68
// Gap: 32
module perm84064(clk, next, reset, next_out,
x0, y0,
x1, y1);
parameter width = 32;
parameter depth = 32;
parameter addrbits = 5;
parameter muxbits = 1;
input [width-1:0] x0;
output [width-1:0] y0;
wire [width-1:0] t0;
wire [width-1:0] s0;
input [width-1:0] x1;
output [width-1:0] y1;
wire [width-1:0] t1;
wire [width-1:0] s1;
input next, reset, clk;
output next_out;
reg [addrbits-1:0] s1rdloc, s2rdloc;
reg [addrbits-1:0] s1wr0;
reg [addrbits-1:0] s1rd0, s2wr0, s2rd0;
reg [addrbits-1:0] s1rd1, s2wr1, s2rd1;
reg s1wr_en, state1, state2, state3;
wire next2, next3, next4;
reg inFlip0, outFlip0_z, outFlip1;
wire inFlip1, outFlip0;
wire [0:0] tm26;
assign tm26 = 0;
shiftRegFIFO #(3, 1) shiftFIFO_85258(.X(outFlip0), .Y(inFlip1), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85259(.X(outFlip0_z), .Y(outFlip0), .clk(clk));
// shiftRegFIFO #(2, 1) inFlip1Reg(outFlip0, inFlip1, clk);
// shiftRegFIFO #(1, 1) outFlip0Reg(outFlip0_z, outFlip0, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem0(x0, t0, {inFlip0, s1wr0}, {outFlip0, s1rd0}, s1wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s1mem1(x1, t1, {inFlip0, s1wr0}, {outFlip0, s1rd1}, s1wr_en, clk);
nextReg #(31, 5) nextReg_85270(.X(next), .Y(next2), .reset(reset), .clk(clk));
shiftRegFIFO #(4, 1) shiftFIFO_85271(.X(next2), .Y(next3), .clk(clk));
nextReg #(32, 5) nextReg_85274(.X(next3), .Y(next4), .reset(reset), .clk(clk));
shiftRegFIFO #(1, 1) shiftFIFO_85275(.X(next4), .Y(next_out), .clk(clk));
shiftRegFIFO #(31, 1) shiftFIFO_85278(.X(tm26), .Y(tm26_d), .clk(clk));
shiftRegFIFO #(3, 1) shiftFIFO_85281(.X(tm26_d), .Y(tm26_dd), .clk(clk));
wire [addrbits-1:0] muxCycle, writeCycle;
assign muxCycle = s1rdloc;
shiftRegFIFO #(3, 5) shiftFIFO_85286(.X(muxCycle), .Y(writeCycle), .clk(clk));
wire readInt, s2wr_en;
assign readInt = (state2 == 1);
shiftRegFIFO #(4, 1) writeIntReg(readInt, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem0(s0, y0, {inFlip1, s2wr0}, {outFlip1, s2rdloc}, s2wr_en, clk);
memMod_dist #(depth*2, width, addrbits+1) s2mem1(s1, y1, {inFlip1, s2wr1}, {outFlip1, s2rdloc}, s2wr_en, clk);
always @(posedge clk) begin
if (reset == 1) begin
state1 <= 0;
inFlip0 <= 0;
s1wr0 <= 0;
end
else if (next == 1) begin
s1wr0 <= 0;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
else begin
case(state1)
0: begin
s1wr0 <= 0;
state1 <= 0;
s1wr_en <= 0;
inFlip0 <= inFlip0;
end
1: begin
s1wr0 <= (s1wr0 == depth-1) ? 0 : s1wr0 + 1;
state1 <= 1;
s1wr_en <= 1;
inFlip0 <= (s1wr0 == depth-1) ? ~inFlip0 : inFlip0;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state2 <= 0;
outFlip0_z <= 0;
end
else if (next2 == 1) begin
s1rdloc <= 0;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
else begin
case(state2)
0: begin
s1rdloc <= 0;
state2 <= 0;
outFlip0_z <= outFlip0_z;
end
1: begin
s1rdloc <= (s1rdloc == depth-1) ? 0 : s1rdloc + 1;
state2 <= 1;
outFlip0_z <= (s1rdloc == depth-1) ? ~outFlip0_z : outFlip0_z;
end
endcase
end
end
always @(posedge clk) begin
if (reset == 1) begin
state3 <= 0;
outFlip1 <= 0;
end
else if (next4 == 1) begin
s2rdloc <= 0;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
else begin
case(state3)
0: begin
s2rdloc <= 0;
state3 <= 0;
outFlip1 <= outFlip1;
end
1: begin
s2rdloc <= (s2rdloc == depth-1) ? 0 : s2rdloc + 1;
state3 <= 1;
outFlip1 <= (s2rdloc == depth-1) ? ~outFlip1 : outFlip1;
end
endcase
end
end
always @(posedge clk) begin
case({tm26_d, s1rdloc})
{1'd0, 5'd0}: s1rd0 <= 1;
{1'd0, 5'd1}: s1rd0 <= 3;
{1'd0, 5'd2}: s1rd0 <= 5;
{1'd0, 5'd3}: s1rd0 <= 7;
{1'd0, 5'd4}: s1rd0 <= 9;
{1'd0, 5'd5}: s1rd0 <= 11;
{1'd0, 5'd6}: s1rd0 <= 13;
{1'd0, 5'd7}: s1rd0 <= 15;
{1'd0, 5'd8}: s1rd0 <= 17;
{1'd0, 5'd9}: s1rd0 <= 19;
{1'd0, 5'd10}: s1rd0 <= 21;
{1'd0, 5'd11}: s1rd0 <= 23;
{1'd0, 5'd12}: s1rd0 <= 25;
{1'd0, 5'd13}: s1rd0 <= 27;
{1'd0, 5'd14}: s1rd0 <= 29;
{1'd0, 5'd15}: s1rd0 <= 31;
{1'd0, 5'd16}: s1rd0 <= 0;
{1'd0, 5'd17}: s1rd0 <= 2;
{1'd0, 5'd18}: s1rd0 <= 4;
{1'd0, 5'd19}: s1rd0 <= 6;
{1'd0, 5'd20}: s1rd0 <= 8;
{1'd0, 5'd21}: s1rd0 <= 10;
{1'd0, 5'd22}: s1rd0 <= 12;
{1'd0, 5'd23}: s1rd0 <= 14;
{1'd0, 5'd24}: s1rd0 <= 16;
{1'd0, 5'd25}: s1rd0 <= 18;
{1'd0, 5'd26}: s1rd0 <= 20;
{1'd0, 5'd27}: s1rd0 <= 22;
{1'd0, 5'd28}: s1rd0 <= 24;
{1'd0, 5'd29}: s1rd0 <= 26;
{1'd0, 5'd30}: s1rd0 <= 28;
{1'd0, 5'd31}: s1rd0 <= 30;
endcase
end
// synthesis attribute rom_style of s1rd0 is "block"
always @(posedge clk) begin
case({tm26_d, s1rdloc})
{1'd0, 5'd0}: s1rd1 <= 0;
{1'd0, 5'd1}: s1rd1 <= 2;
{1'd0, 5'd2}: s1rd1 <= 4;
{1'd0, 5'd3}: s1rd1 <= 6;
{1'd0, 5'd4}: s1rd1 <= 8;
{1'd0, 5'd5}: s1rd1 <= 10;
{1'd0, 5'd6}: s1rd1 <= 12;
{1'd0, 5'd7}: s1rd1 <= 14;
{1'd0, 5'd8}: s1rd1 <= 16;
{1'd0, 5'd9}: s1rd1 <= 18;
{1'd0, 5'd10}: s1rd1 <= 20;
{1'd0, 5'd11}: s1rd1 <= 22;
{1'd0, 5'd12}: s1rd1 <= 24;
{1'd0, 5'd13}: s1rd1 <= 26;
{1'd0, 5'd14}: s1rd1 <= 28;
{1'd0, 5'd15}: s1rd1 <= 30;
{1'd0, 5'd16}: s1rd1 <= 1;
{1'd0, 5'd17}: s1rd1 <= 3;
{1'd0, 5'd18}: s1rd1 <= 5;
{1'd0, 5'd19}: s1rd1 <= 7;
{1'd0, 5'd20}: s1rd1 <= 9;
{1'd0, 5'd21}: s1rd1 <= 11;
{1'd0, 5'd22}: s1rd1 <= 13;
{1'd0, 5'd23}: s1rd1 <= 15;
{1'd0, 5'd24}: s1rd1 <= 17;
{1'd0, 5'd25}: s1rd1 <= 19;
{1'd0, 5'd26}: s1rd1 <= 21;
{1'd0, 5'd27}: s1rd1 <= 23;
{1'd0, 5'd28}: s1rd1 <= 25;
{1'd0, 5'd29}: s1rd1 <= 27;
{1'd0, 5'd30}: s1rd1 <= 29;
{1'd0, 5'd31}: s1rd1 <= 31;
endcase
end
// synthesis attribute rom_style of s1rd1 is "block"
swNet84064 sw(tm26_d, clk, muxCycle, t0, s0, t1, s1);
always @(posedge clk) begin
case({tm26_dd, writeCycle})
{1'd0, 5'd0}: s2wr0 <= 16;
{1'd0, 5'd1}: s2wr0 <= 17;
{1'd0, 5'd2}: s2wr0 <= 18;
{1'd0, 5'd3}: s2wr0 <= 19;
{1'd0, 5'd4}: s2wr0 <= 20;
{1'd0, 5'd5}: s2wr0 <= 21;
{1'd0, 5'd6}: s2wr0 <= 22;
{1'd0, 5'd7}: s2wr0 <= 23;
{1'd0, 5'd8}: s2wr0 <= 24;
{1'd0, 5'd9}: s2wr0 <= 25;
{1'd0, 5'd10}: s2wr0 <= 26;
{1'd0, 5'd11}: s2wr0 <= 27;
{1'd0, 5'd12}: s2wr0 <= 28;
{1'd0, 5'd13}: s2wr0 <= 29;
{1'd0, 5'd14}: s2wr0 <= 30;
{1'd0, 5'd15}: s2wr0 <= 31;
{1'd0, 5'd16}: s2wr0 <= 0;
{1'd0, 5'd17}: s2wr0 <= 1;
{1'd0, 5'd18}: s2wr0 <= 2;
{1'd0, 5'd19}: s2wr0 <= 3;
{1'd0, 5'd20}: s2wr0 <= 4;
{1'd0, 5'd21}: s2wr0 <= 5;
{1'd0, 5'd22}: s2wr0 <= 6;
{1'd0, 5'd23}: s2wr0 <= 7;
{1'd0, 5'd24}: s2wr0 <= 8;
{1'd0, 5'd25}: s2wr0 <= 9;
{1'd0, 5'd26}: s2wr0 <= 10;
{1'd0, 5'd27}: s2wr0 <= 11;
{1'd0, 5'd28}: s2wr0 <= 12;
{1'd0, 5'd29}: s2wr0 <= 13;
{1'd0, 5'd30}: s2wr0 <= 14;
{1'd0, 5'd31}: s2wr0 <= 15;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr0 is "block"
always @(posedge clk) begin
case({tm26_dd, writeCycle})
{1'd0, 5'd0}: s2wr1 <= 0;
{1'd0, 5'd1}: s2wr1 <= 1;
{1'd0, 5'd2}: s2wr1 <= 2;
{1'd0, 5'd3}: s2wr1 <= 3;
{1'd0, 5'd4}: s2wr1 <= 4;
{1'd0, 5'd5}: s2wr1 <= 5;
{1'd0, 5'd6}: s2wr1 <= 6;
{1'd0, 5'd7}: s2wr1 <= 7;
{1'd0, 5'd8}: s2wr1 <= 8;
{1'd0, 5'd9}: s2wr1 <= 9;
{1'd0, 5'd10}: s2wr1 <= 10;
{1'd0, 5'd11}: s2wr1 <= 11;
{1'd0, 5'd12}: s2wr1 <= 12;
{1'd0, 5'd13}: s2wr1 <= 13;
{1'd0, 5'd14}: s2wr1 <= 14;
{1'd0, 5'd15}: s2wr1 <= 15;
{1'd0, 5'd16}: s2wr1 <= 16;
{1'd0, 5'd17}: s2wr1 <= 17;
{1'd0, 5'd18}: s2wr1 <= 18;
{1'd0, 5'd19}: s2wr1 <= 19;
{1'd0, 5'd20}: s2wr1 <= 20;
{1'd0, 5'd21}: s2wr1 <= 21;
{1'd0, 5'd22}: s2wr1 <= 22;
{1'd0, 5'd23}: s2wr1 <= 23;
{1'd0, 5'd24}: s2wr1 <= 24;
{1'd0, 5'd25}: s2wr1 <= 25;
{1'd0, 5'd26}: s2wr1 <= 26;
{1'd0, 5'd27}: s2wr1 <= 27;
{1'd0, 5'd28}: s2wr1 <= 28;
{1'd0, 5'd29}: s2wr1 <= 29;
{1'd0, 5'd30}: s2wr1 <= 30;
{1'd0, 5'd31}: s2wr1 <= 31;
endcase // case(writeCycle)
end // always @ (posedge clk)
// synthesis attribute rom_style of s2wr1 is "block"
endmodule
module multfix(clk, rst, a, b, q_sc, q_unsc);
parameter WIDTH=35, CYCLES=6;
input signed [WIDTH-1:0] a,b;
output [WIDTH-1:0] q_sc;
output [WIDTH-1:0] q_unsc;
input clk, rst;
reg signed [2*WIDTH-1:0] q[CYCLES-1:0];
wire signed [2*WIDTH-1:0] res;
integer i;
assign res = q[CYCLES-1];
assign q_unsc = res[WIDTH-1:0];
assign q_sc = {res[2*WIDTH-1], res[2*WIDTH-4:WIDTH-2]};
always @(posedge clk) begin
q[0] <= a * b;
for (i = 1; i < CYCLES; i=i+1) begin
q[i] <= q[i-1];
end
end
endmodule
module addfxp(a, b, q, clk);
parameter width = 16, cycles=1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a+b;
for (i=1; i < cycles; i = i+1)
res[i] <= res[i-1];
end
endmodule
module subfxp(a, b, q, clk);
parameter width = 16, cycles=1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a-b;
for (i=1; i < cycles; i = i+1)
res[i] <= res[i-1];
end
endmodule |
//
// Copyright (C) 2018 Massachusetts Institute of Technology
//
// File : dft_top_top.v
// Project : Common Evaluation Platform (CEP)
// Description : This file provides a wishbone based-DFT core
//
module dft_top_top(
wb_adr_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
wb_ack_o, wb_err_o, wb_dat_o,
wb_clk_i, wb_rst_i, int_o
);
parameter dw = 32;
parameter aw = 32;
input [aw-1:0] wb_adr_i;
input wb_cyc_i;
input [dw-1:0] wb_dat_i;
input [3:0] wb_sel_i;
input wb_stb_i;
input wb_we_i;
output wb_ack_o;
output wb_err_o;
output reg [dw-1:0] wb_dat_o;
output int_o;
input wb_clk_i;
input wb_rst_i;
assign wb_ack_o = 1'b1;
assign wb_err_o = 1'b0;
assign int_o = 1'b0;
// Internal registers
reg next;
reg [63:0] dataX [0:31];
reg [63:0] dataY [0:31];
reg [5:0] xSel;
reg [5:0] ySel;
wire [63:0] dataIn, dataOut, dataR_Out;
reg [63:0] data_In_data, data_In_addr, data_Out_addr;
reg data_valid, data_In_write;
wire next_out, next_posedge;
// Implement MD5 I/O memory map interface
// Write side
always @(posedge wb_clk_i)
begin
if(wb_rst_i)
begin
next <= 0;
data_In_write <= 0;
data_In_addr <= 0;
data_In_data[31:0] <= 0;
data_In_data[63:32]<= 0;
end
else if(wb_stb_i & wb_we_i)
case(wb_adr_i[5:2])
0:
next <= wb_dat_i[0];
1:
data_In_write <= wb_dat_i[0];
2:
data_In_addr <= wb_dat_i;
3:
data_In_data[31:0] <= wb_dat_i;
4:
data_In_data[63:32]<= wb_dat_i;
5:
data_Out_addr <= wb_dat_i;
default:
;
endcase
end // always @ (posedge wb_clk_i)
// Implement MD5 I/O memory map interface
// Read side
always @(*)
begin
case(wb_adr_i[5:2])
0:
wb_dat_o = {31'b0, next};
1:
wb_dat_o = {31'b0, data_In_write};
2:
wb_dat_o = data_In_addr;
3:
wb_dat_o = data_In_data[31:0];
4:
wb_dat_o = data_In_data[63:32];
5:
wb_dat_o = data_Out_addr;
6:
wb_dat_o = dataR_Out[31:0];
7:
wb_dat_o = dataR_Out[63:32];
8:
wb_dat_o = {31'b0, data_valid};
default:
wb_dat_o = 32'b0;
endcase
end // always @ (*)
dft_top dft_top(
.clk(wb_clk_i),
.reset(wb_rst_i),
.next(next_posedge),
.next_out(next_out),
.X0(dataIn[15:0]),
.X1(dataIn[31:16]),
.X2(dataIn[47:32]),
.X3(dataIn[63:48]),
.Y0(dataOut[15:0]),
.Y1(dataOut[31:16]),
.Y2(dataOut[47:32]),
.Y3(dataOut[63:48]));
reg data_In_write_r;
always @(posedge wb_clk_i)
begin
data_In_write_r <= data_In_write;
end
wire data_In_write_posedge = data_In_write & ~data_In_write_r;
always @ (posedge wb_clk_i)
begin
if(data_In_write_posedge)
begin
dataX[data_In_addr] <= data_In_data;
end
end
assign dataR_Out=dataY[data_Out_addr];
reg next_r;
always @(posedge wb_clk_i)
begin
next_r <= next;
end
assign next_posedge = next & ~next_r;
always @ (posedge wb_clk_i)
begin
if(next_posedge)
begin
xSel <= 6'h00;
end
else if(xSel<6'b100000)
begin
xSel <= xSel +1;
end
end
assign dataIn = dataX[xSel];
reg next_out_r;
always @(posedge wb_clk_i)
begin
next_out_r <= next_out;
end
wire next_out_posedge = next_out & ~next_out_r;
always @ (posedge wb_clk_i)
begin
if(next_out_posedge)
begin
ySel <= 6'h00;
end
else if(ySel<6'b100000)
begin
ySel <= ySel +1;
dataY[ySel] = dataOut;
end
end
always @ (posedge wb_clk_i)
begin
if(next_posedge)
begin
data_valid <= 0;
end
else if(next_out_posedge)
begin
data_valid <= 1;
end
end
endmodule
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