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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity clk_video_clk_wiz is port (-- Clock in ports clk_100MHz : in std_logic; -- Clock out ports clk_193MHz : out std_logic; -- Status and control signals locked : out std_logic ); end clk_video_clk_wiz; architecture xilinx of clk_video_clk_wiz is -- Input clock buffering / unused connectors signal clk_100MHz_clk_video : std_logic; -- Output clock buffering / unused connectors signal clkfbout_clk_video : std_logic; signal clkfbout_buf_clk_video : std_logic; signal clkfboutb_unused : std_logic; signal clk_193MHz_clk_video : std_logic; signal clkout0b_unused : std_logic; signal clkout1_unused : std_logic; signal clkout1b_unused : std_logic; signal clkout2_unused : std_logic; signal clkout2b_unused : std_logic; signal clkout3_unused : std_logic; signal clkout3b_unused : std_logic; signal clkout4_unused : std_logic; signal clkout5_unused : std_logic; signal clkout6_unused : std_logic; -- Dynamic programming unused signals signal do_unused : std_logic_vector(15 downto 0); signal drdy_unused : std_logic; -- Dynamic phase shift unused signals signal psdone_unused : std_logic; signal locked_int : std_logic; -- Unused status signals signal clkfbstopped_unused : std_logic; signal clkinstopped_unused : std_logic; begin -- Input buffering -------------------------------------- clkin1_bufg : BUFG port map (O => clk_100MHz_clk_video, I => clk_100MHz); -- Clocking PRIMITIVE -------------------------------------- -- Instantiation of the MMCM PRIMITIVE -- * Unused inputs are tied off -- * Unused outputs are labeled unused mmcm_adv_inst : MMCME2_ADV generic map (BANDWIDTH => "OPTIMIZED", CLKOUT4_CASCADE => FALSE, COMPENSATION => "ZHOLD", STARTUP_WAIT => FALSE, DIVCLK_DIVIDE => 4, CLKFBOUT_MULT_F => 30.875, CLKFBOUT_PHASE => 0.000, CLKFBOUT_USE_FINE_PS => FALSE, CLKOUT0_DIVIDE_F => 4.000, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKOUT0_USE_FINE_PS => FALSE, CLKIN1_PERIOD => 10.0, REF_JITTER1 => 0.010) port map -- Output clocks ( CLKFBOUT => clkfbout_clk_video, CLKFBOUTB => clkfboutb_unused, CLKOUT0 => clk_193MHz_clk_video, CLKOUT0B => clkout0b_unused, CLKOUT1 => clkout1_unused, CLKOUT1B => clkout1b_unused, CLKOUT2 => clkout2_unused, CLKOUT2B => clkout2b_unused, CLKOUT3 => clkout3_unused, CLKOUT3B => clkout3b_unused, CLKOUT4 => clkout4_unused, CLKOUT5 => clkout5_unused, CLKOUT6 => clkout6_unused, -- Input clock control CLKFBIN => clkfbout_buf_clk_video, CLKIN1 => clk_100MHz_clk_video, CLKIN2 => '0', -- Tied to always select the primary input clock CLKINSEL => '1', -- Ports for dynamic reconfiguration DADDR => (others => '0'), DCLK => '0', DEN => '0', DI => (others => '0'), DO => do_unused, DRDY => drdy_unused, DWE => '0', -- Ports for dynamic phase shift PSCLK => '0', PSEN => '0', PSINCDEC => '0', PSDONE => psdone_unused, -- Other control and status signals LOCKED => locked_int, CLKINSTOPPED => clkinstopped_unused, CLKFBSTOPPED => clkfbstopped_unused, PWRDWN => '0', RST => '0'); locked <= locked_int; -- Output buffering ------------------------------------- clkf_buf : BUFG port map (O => clkfbout_buf_clk_video, I => clkfbout_clk_video); clkout1_buf : BUFG port map (O => clk_193MHz, I => clk_193MHz_clk_video); end xilinx; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.pp_csr.all; entity pp_csr_alu is port( x, y : in std_logic_vector(31 downto 0); result : out std_logic_vector(31 downto 0); immediate : in std_logic_vector(4 downto 0); use_immediate : in std_logic; write_mode : in csr_write_mode ); end entity pp_csr_alu; architecture behaviour of pp_csr_alu is signal a, b : std_logic_vector(31 downto 0); begin a <= x; b <= y when use_immediate = '0' else std_logic_vector(resize(unsigned(immediate), b'length)); calculate: process(a, b, write_mode) begin case write_mode is when CSR_WRITE_NONE => result <= a; when CSR_WRITE_SET => result <= a or b; when CSR_WRITE_CLEAR => result <= a and (not b); when CSR_WRITE_REPLACE => result <= b; end case; end process calculate; end architecture behaviour; |
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.types_pkg.all; package adaptations_pkg is constant C_ALERT_FILE_NAME : string := "_Alert.txt"; constant C_LOG_FILE_NAME : string := "_Log.txt"; constant C_SHOW_UVVM_UTILITY_LIBRARY_INFO : boolean := true; -- Set this to false when you no longer need the initial info constant C_SHOW_UVVM_UTILITY_LIBRARY_RELEASE_INFO : boolean := true; -- Set this to false when you no longer need the release info ------------------------------------------------------------------------------- -- Log format ------------------------------------------------------------------------------- --UVVM: [<ID>] <time> <Scope> Msg --PPPPPPPPIIIIII TTTTTTTT SSSSSSSSSSSSSS MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM constant C_LOG_PREFIX : string := "UVVM: "; -- Note: ': ' is recommended as final characters constant C_LOG_PREFIX_WIDTH : natural := C_LOG_PREFIX'length; constant C_LOG_MSG_ID_WIDTH : natural := 24; constant C_LOG_TIME_WIDTH : natural := 16; -- 3 chars used for unit eg. " ns" constant C_LOG_TIME_BASE : time := ns; -- Unit in which time is shown in log (ns | ps) constant C_LOG_TIME_DECIMALS : natural := 1; -- Decimals to show for given C_LOG_TIME_BASE constant C_LOG_SCOPE_WIDTH : natural := 30; constant C_LOG_LINE_WIDTH : natural := 175; constant C_LOG_INFO_WIDTH : natural := C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH; constant C_USE_BACKSLASH_N_AS_LF : boolean := true; -- If true interprets ' ' as Line feed constant C_USE_BACKSLASH_R_AS_LF : boolean := true; -- If true, inserts an empty line if '\r' -- is the first character of the string. -- All others '\r' will be printed as is. constant C_SINGLE_LINE_ALERT : boolean := false; -- If true prints alerts on a single line. constant C_SINGLE_LINE_LOG : boolean := false; -- If true prints log messages on a single line. constant C_TB_SCOPE_DEFAULT : string := "TB seq."; -- Default scope in test sequencer constant C_LOG_TIME_TRUNC_WARNING : boolean := true; -- Yields a single TB_WARNING if time stamp truncated. Otherwise none constant C_SHOW_LOG_ID : boolean := true; -- This constant has replaced the global_show_log_id constant C_SHOW_LOG_SCOPE : boolean := true; -- This constant has replaced the global_show_log_scope constant C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME : boolean := false; constant C_USE_STD_STOP_ON_ALERT_STOP_LIMIT : boolean := true; -- true: break using std.env.stop, false: break using failure shared variable shared_default_log_destination : t_log_destination := CONSOLE_AND_LOG; ------------------------------------------------------------------------------- -- Verbosity control -- NOTE: Do not enter new IDs without proper evaluation: -- 1. Is it - or could it be covered by an existing ID -- 2. Could it be combined with other needs for a more general new ID -- Feel free to suggest new ID for future versions of UVVM Utility Library (support@bitvis.no) ------------------------------------------------------------------------------- type t_msg_id is ( -- Bitvis utility methods NO_ID, -- Used as default prior to setting actual ID when transfering ID as a field in a record ID_UTIL_BURIED, -- Used for buried log messages where msg and scope cannot be modified from outside ID_BITVIS_DEBUG, -- Bitvis internal ID used for UVVM debugging ID_UTIL_SETUP, -- Used for Utility setup ID_LOG_MSG_CTRL, -- Used inside Utility library only - when enabling/disabling msg IDs. ID_ALERT_CTRL, -- Used inside Utility library only - when setting IGNORE or REGARD on various alerts. ID_NEVER, -- Used for avoiding log entry. Cannot be enabled. ID_FINISH_OR_STOP, -- Used when terminating the complete simulation - independent of why ID_CLOCK_GEN, -- Used for logging when clock generators are enabled or disabled ID_GEN_PULSE, -- Used for logging when a gen_pulse procedure starts pulsing a signal ID_BLOCKING, -- Used for logging when using synchronisation flags -- General ID_POS_ACK, -- To write a positive acknowledge on a check -- Directly inside test sequencers ID_LOG_HDR, -- ONLY allowed in test sequencer, Log section headers ID_LOG_HDR_LARGE, -- ONLY allowed in test sequencer, Large log section headers ID_LOG_HDR_XL, -- ONLY allowed in test sequencer, Extra large log section headers ID_SEQUENCER, -- ONLY allowed in test sequencer, Normal log (not log headers) ID_SEQUENCER_SUB, -- ONLY allowed in test sequencer, Subprograms defined in sequencer -- BFMs ID_BFM, -- Used inside a BFM (to log BFM access) ID_BFM_WAIT, -- Used inside a BFM to indicate that it is waiting for something (e.g. for ready) ID_BFM_POLL, -- Used inside a BFM when polling until reading a given value. I.e. to show all reads until expected value found (e.g. for sbi_poll_until()) ID_BFM_POLL_SUMMARY, -- Used inside a BFM when showing the summary of data that has been received while waiting for expected data. ID_TERMINATE_CMD, -- Typically used inside a loop in a procedure to end the loop (e.g. for sbi_poll_until() or any looped generation of random stimuli -- Packet related data Ids with three levels of granularity, for differentiating between frames, packets and segments. -- Segment Ids, finest granularity of packet data ID_SEGMENT_INITIATE, -- Notify that a packet is about to be transmitted or received ID_SEGMENT_COMPLETE, -- Notify that a packet has been transmitted or received ID_SEGMENT_HDR, -- AS ID_SEGMENT_COMPLETE, but also writes header info ID_SEGMENT_DATA, -- AS ID_SEGMENT_COMPLETE, but also writes packet data (could be huge) -- Packet Ids, medium granularity of packet data ID_PACKET_INITIATE, -- Notify that a packet is about to be transmitted or received ID_PACKET_COMPLETE, -- Notify that a packet has been transmitted or received ID_PACKET_HDR, -- AS ID_PACKET_COMPLETED, but also writes header info ID_PACKET_DATA, -- AS ID_PACKET_COMPLETED, but also writes packet data (could be huge) -- Frame Ids, roughest granularity of packet data ID_FRAME_INITIATE, -- Notify that a packet is about to be transmitted or received ID_FRAME_COMPLETE, -- Notify that a packet has been transmitted or received ID_FRAME_HDR, -- AS ID_FRAME_COMPLETE, but also writes header info ID_FRAME_DATA, -- AS ID_FRAME_COMPLETE, but also writes packet data (could be huge) -- OSVVM Ids ID_COVERAGE_MAKEBIN, -- Log messages from MakeBin (IllegalBin/GenBin/IgnoreBin) ID_COVERAGE_ADDBIN, -- Log messages from AddBin/AddCross ID_COVERAGE_ICOVER, -- ICover logging, NB: Very low level debugging. Can result in large amount of data. ID_COVERAGE_CONFIG, -- Logging of configuration in the coverage package ID_COVERAGE_SUMMARY, -- Report logging : Summary of coverage, with both covered bins and holes ID_COVERAGE_HOLES, -- Report logging : Holes only -- Distributed command systems ID_UVVM_SEND_CMD, ID_UVVM_CMD_ACK, ID_UVVM_CMD_RESULT, ID_CMD_INTERPRETER, -- Message from VVC interpreter about correctly received and queued/issued command ID_CMD_INTERPRETER_WAIT, -- Message from VVC interpreter that it is actively waiting for a command ID_IMMEDIATE_CMD, -- Message from VVC interpreter that an IMMEDIATE command has been executed ID_IMMEDIATE_CMD_WAIT, -- Message from VVC interpreter that an IMMEDIATE command is waiting for command to complete ID_CMD_EXECUTOR, -- Message from VVC executor about correctly received command - prior to actual execution ID_CMD_EXECUTOR_WAIT, -- Message from VVC executor that it is actively waiting for a command ID_INSERTED_DELAY, -- Message from VVC executor that it is waiting a given delay -- Distributed data ID_UVVM_DATA_QUEUE, -- Information about UVVM data FIFO/stack (initialization, put, get, etc) -- VVC system ID_CONSTRUCTOR, -- Constructor message from VVCs (or other components/process when needed) ID_CONSTRUCTOR_SUB, -- Constructor message for lower level constructor messages (like Queue-information and other limitations) -- SB package ID_DATA, ID_CTRL, -- Special purpose - Not really IDs ALL_MESSAGES -- Applies to ALL message ID apart from ID_NEVER ); type t_msg_id_panel is array (t_msg_id'left to t_msg_id'right) of t_enabled; constant C_TB_MSG_ID_DEFAULT : t_msg_id := ID_SEQUENCER; -- msg ID used when calling the log method without any msg ID switch. -- Default message Id panel to be used for all message Id panels, except: -- - VVC message Id panels, see constant C_VVC_MSG_ID_PANEL_DEFAULT constant C_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := ( ID_NEVER => DISABLED, ID_UTIL_BURIED => DISABLED, ID_BITVIS_DEBUG => DISABLED, ID_COVERAGE_MAKEBIN => DISABLED, ID_COVERAGE_ADDBIN => DISABLED, ID_COVERAGE_ICOVER => DISABLED, others => ENABLED ); -- If false, OSVVM uses the default message id panel. If true, it uses a separate message id panel. constant C_USE_LOCAL_OSVVM_MSG_ID_PANELS : boolean := TRUE; type t_msg_id_indent is array (t_msg_id'left to t_msg_id'right) of string(1 to 4); constant C_MSG_ID_INDENT : t_msg_id_indent := ( ID_IMMEDIATE_CMD_WAIT => " ..", ID_CMD_INTERPRETER => " " & NUL & NUL, ID_CMD_INTERPRETER_WAIT => " ..", ID_CMD_EXECUTOR => " " & NUL & NUL, ID_CMD_EXECUTOR_WAIT => " ..", ID_UVVM_SEND_CMD => "->" & NUL & NUL, ID_UVVM_CMD_ACK => " ", others => "" & NUL & NUL & NUL & NUL ); constant C_MSG_DELIMITER : character := '''; ------------------------------------------------------------------------- -- Alert counters ------------------------------------------------------------------------- -- Default values. These can be overwritten in each sequencer by using -- set_alert_attention or set_alert_stop_limit (see quick ref). constant C_DEFAULT_ALERT_ATTENTION : t_alert_attention := (others => REGARD); -- 0 = Never stop constant C_DEFAULT_STOP_LIMIT : t_alert_counters := (note to manual_check => 0, others => 1); ------------------------------------------------------------------------- -- Hierarchical alerts ------------------------------------------------------------------------- constant C_ENABLE_HIERARCHICAL_ALERTS : boolean := false; constant C_BASE_HIERARCHY_LEVEL : string(1 to 5) := "Total"; constant C_EMPTY_NODE : t_hierarchy_node := (" ", (others => (others => 0)), (others => 0), (others => true)); ------------------------------------------------------------------------- -- Deprecate ------------------------------------------------------------------------- -- These values are used to indicate outdated sub-programs constant C_DEPRECATE_SETTING : t_deprecate_setting := DEPRECATE_ONCE; shared variable deprecated_subprogram_list : t_deprecate_list := (others=>(others => ' ')); ------------------------------------------------------------------------ -- UVVM VVC Framework adaptations ------------------------------------------------------------------------ constant C_SCOPE : string := C_TB_SCOPE_DEFAULT & "(uvvm)"; signal global_show_msg_for_uvvm_cmd : boolean := true; constant C_CMD_QUEUE_COUNT_MAX : natural := 20; -- (VVC Command queue) May be overwritten for dedicated VVC constant C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING; constant C_CMD_QUEUE_COUNT_THRESHOLD : natural := 18; constant C_RESULT_QUEUE_COUNT_MAX : natural := 20; -- (VVC Result queue) May be overwritten for dedicated VVC constant C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING; constant C_RESULT_QUEUE_COUNT_THRESHOLD : natural := 18; constant C_MAX_VVC_INSTANCE_NUM : natural := 20; constant C_MAX_NUM_SEQUENCERS : natural := 10; -- Max number of sequencers -- Maximum allowed length of VVC names constant C_MAX_VVC_NAME_LENGTH : positive := 20; -- Minimum width of vvc name and channel displayed in scope. -- These combined + the length of instance + 2 (commas), cannot exceed C_LOG_SCOPE_WIDTH. constant C_MINIMUM_CHANNEL_SCOPE_WIDTH : natural := 10; constant C_MINIMUM_VVC_NAME_SCOPE_WIDTH : natural := 10; constant C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER : natural := 2048; constant C_NUMBER_OF_DATA_BUFFERS : natural := 10; -- Default message Id panel intended for use in the VVCs constant C_VVC_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := ( ID_NEVER => DISABLED, ID_UTIL_BURIED => DISABLED, others => ENABLED ); type t_data_source is ( -- May add more types of random ++ later NA, FROM_BUFFER, RANDOM, RANDOM_TO_BUFFER ); type t_error_injection is ( -- May add more controlled error injection later NA, RANDOM_BIT_ERROR, RANDOM_DATA_ERROR, RANDOM_ADDRESS_ERROR ); constant C_CMD_IDX_PREFIX : string := " ["; constant C_CMD_IDX_SUFFIX : string := "]"; type t_channel is ( -- NOTE: Add more types of channels when needed for a VVC NA, -- When channel is not relevant ALL_CHANNELS, -- When command shall be received by all channels RX, TX); constant C_VVCT_ALL_INSTANCES, ALL_INSTANCES : integer := -2; constant ALL_ENABLED_INSTANCES : integer := -3; constant C_NUM_SEMAPHORE_LOCK_TRIES : natural := 500; ------------------------------------------------------------------------ -- Scoreboard adaptations ------------------------------------------------------------------------ constant C_MAX_QUEUE_INSTANCE_NUM : positive := 100; -- Maximum number of instances constant C_SB_TAG_WIDTH : positive := 128; -- Number of characters in SB tag constant C_SB_SOURCE_WIDTH : positive := 128; -- Number of characters in SB source element constant C_SB_SLV_WIDTH : positive := 8; -- Width of the SLV in the predefined SLV SB -- Default message Id panel intended for use in SB constant C_SB_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := ( ID_CTRL => ENABLED, ID_DATA => DISABLED, others => DISABLED ); end package adaptations_pkg; package body adaptations_pkg is end package body adaptations_pkg; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity arty_mmcm_arty_mmcm_clk_wiz is port ( clk_in : in STD_LOGIC; clk_50m : out STD_LOGIC; resetn : in STD_LOGIC; locked : out STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of arty_mmcm_arty_mmcm_clk_wiz : entity is "arty_mmcm_clk_wiz"; end arty_mmcm_arty_mmcm_clk_wiz; architecture STRUCTURE of arty_mmcm_arty_mmcm_clk_wiz is signal clk_50m_arty_mmcm : STD_LOGIC; signal clk_in_arty_mmcm : STD_LOGIC; signal clkfbout_arty_mmcm : STD_LOGIC; signal clkfbout_buf_arty_mmcm : STD_LOGIC; signal reset_high : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); attribute BOX_TYPE : string; attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE"; attribute CAPACITANCE : string; attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; attribute IBUF_DELAY_VALUE : string; attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; attribute IFD_DELAY_VALUE : string; attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; begin clkf_buf: unisim.vcomponents.BUFG port map ( I => clkfbout_arty_mmcm, O => clkfbout_buf_arty_mmcm ); clkin1_ibufg: unisim.vcomponents.IBUF generic map( IOSTANDARD => "DEFAULT" ) port map ( I => clk_in, O => clk_in_arty_mmcm ); clkout1_buf: unisim.vcomponents.BUFG port map ( I => clk_50m_arty_mmcm, O => clk_50m ); mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV generic map( BANDWIDTH => "OPTIMIZED", CLKFBOUT_MULT_F => 10.000000, CLKFBOUT_PHASE => 0.000000, CLKFBOUT_USE_FINE_PS => false, CLKIN1_PERIOD => 10.000000, CLKIN2_PERIOD => 0.000000, CLKOUT0_DIVIDE_F => 20.000000, CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, CLKOUT0_USE_FINE_PS => false, CLKOUT1_DIVIDE => 1, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, CLKOUT1_USE_FINE_PS => false, CLKOUT2_DIVIDE => 1, CLKOUT2_DUTY_CYCLE => 0.500000, CLKOUT2_PHASE => 0.000000, CLKOUT2_USE_FINE_PS => false, CLKOUT3_DIVIDE => 1, CLKOUT3_DUTY_CYCLE => 0.500000, CLKOUT3_PHASE => 0.000000, CLKOUT3_USE_FINE_PS => false, CLKOUT4_CASCADE => false, CLKOUT4_DIVIDE => 1, CLKOUT4_DUTY_CYCLE => 0.500000, CLKOUT4_PHASE => 0.000000, CLKOUT4_USE_FINE_PS => false, CLKOUT5_DIVIDE => 1, CLKOUT5_DUTY_CYCLE => 0.500000, CLKOUT5_PHASE => 0.000000, CLKOUT5_USE_FINE_PS => false, CLKOUT6_DIVIDE => 1, CLKOUT6_DUTY_CYCLE => 0.500000, CLKOUT6_PHASE => 0.000000, CLKOUT6_USE_FINE_PS => false, COMPENSATION => "ZHOLD", DIVCLK_DIVIDE => 1, IS_CLKINSEL_INVERTED => '0', IS_PSEN_INVERTED => '0', IS_PSINCDEC_INVERTED => '0', IS_PWRDWN_INVERTED => '0', IS_RST_INVERTED => '0', REF_JITTER1 => 0.010000, REF_JITTER2 => 0.010000, SS_EN => "FALSE", SS_MODE => "CENTER_HIGH", SS_MOD_PERIOD => 10000, STARTUP_WAIT => false ) port map ( CLKFBIN => clkfbout_buf_arty_mmcm, CLKFBOUT => clkfbout_arty_mmcm, CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, CLKIN1 => clk_in_arty_mmcm, CLKIN2 => '0', CLKINSEL => '1', CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, CLKOUT0 => clk_50m_arty_mmcm, CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, DADDR(6 downto 0) => B"0000000", DCLK => '0', DEN => '0', DI(15 downto 0) => B"0000000000000000", DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, DWE => '0', LOCKED => locked, PSCLK => '0', PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, PSEN => '0', PSINCDEC => '0', PWRDWN => '0', RST => reset_high ); mmcm_adv_inst_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => resetn, O => reset_high ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity arty_mmcm is port ( clk_in : in STD_LOGIC; clk_50m : out STD_LOGIC; resetn : in STD_LOGIC; locked : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of arty_mmcm : entity is true; attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of arty_mmcm : entity is "arty_mmcm,clk_wiz_v5_2_0,{component_name=arty_mmcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; end arty_mmcm; architecture STRUCTURE of arty_mmcm is begin inst: entity work.arty_mmcm_arty_mmcm_clk_wiz port map ( clk_50m => clk_50m, clk_in => clk_in, locked => locked, resetn => resetn ); end STRUCTURE; |
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity contact_discovery is generic ( C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 6; C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 ); port ( ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; contacts_in_V_TDATA : IN STD_LOGIC_VECTOR (7 downto 0); contacts_in_V_TVALID : IN STD_LOGIC; contacts_in_V_TREADY : OUT STD_LOGIC; database_in_V_TDATA : IN STD_LOGIC_VECTOR (7 downto 0); database_in_V_TVALID : IN STD_LOGIC; database_in_V_TREADY : OUT STD_LOGIC; matched_out_V_TDATA : OUT STD_LOGIC_VECTOR (7 downto 0); matched_out_V_TVALID : OUT STD_LOGIC; matched_out_V_TREADY : IN STD_LOGIC; s_axi_AXILiteS_AWVALID : IN STD_LOGIC; s_axi_AXILiteS_AWREADY : OUT STD_LOGIC; s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0); s_axi_AXILiteS_WVALID : IN STD_LOGIC; s_axi_AXILiteS_WREADY : OUT STD_LOGIC; s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0); s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0); s_axi_AXILiteS_ARVALID : IN STD_LOGIC; s_axi_AXILiteS_ARREADY : OUT STD_LOGIC; s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0); s_axi_AXILiteS_RVALID : OUT STD_LOGIC; s_axi_AXILiteS_RREADY : IN STD_LOGIC; s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0); s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); s_axi_AXILiteS_BVALID : OUT STD_LOGIC; s_axi_AXILiteS_BREADY : IN STD_LOGIC; s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); interrupt : OUT STD_LOGIC ); end; architecture behav of contact_discovery is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "contact_discovery,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xczu9eg-ffvb1156-1-i,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.932500,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=4,HLS_SYN_DSP=0,HLS_SYN_FF=461,HLS_SYN_LUT=838}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001"; constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000010"; constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000100"; constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (14 downto 0) := "000000000001000"; constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (14 downto 0) := "000000000010000"; constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (14 downto 0) := "000000000100000"; constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (14 downto 0) := "000000001000000"; constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (14 downto 0) := "000000010000000"; constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (14 downto 0) := "000000100000000"; constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (14 downto 0) := "000001000000000"; constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (14 downto 0) := "000010000000000"; constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (14 downto 0) := "000100000000000"; constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (14 downto 0) := "001000000000000"; constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (14 downto 0) := "010000000000000"; constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (14 downto 0) := "100000000000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10"; constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11"; constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100"; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_boolean_0 : BOOLEAN := false; constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv8_80 : STD_LOGIC_VECTOR (7 downto 0) := "10000000"; constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001"; constant ap_const_lv7_40 : STD_LOGIC_VECTOR (6 downto 0) := "1000000"; constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001"; constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000"; constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111"; constant ap_const_lv25_0 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000000000000"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant ap_const_boolean_1 : BOOLEAN := true; signal ap_rst_n_inv : STD_LOGIC; signal ap_start : STD_LOGIC; signal ap_done : STD_LOGIC; signal ap_idle : STD_LOGIC; signal ap_CS_fsm : STD_LOGIC_VECTOR (14 downto 0) := "000000000000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_CS_fsm_state1 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none"; signal ap_ready : STD_LOGIC; signal operation : STD_LOGIC_VECTOR (31 downto 0); signal operation_preg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal operation_ap_vld : STD_LOGIC; signal operation_ap_vld_preg : STD_LOGIC := '0'; signal operation_ap_vld_in_sig : STD_LOGIC; signal matched_out_V_1_data_out : STD_LOGIC_VECTOR (7 downto 0); signal matched_out_V_1_vld_in : STD_LOGIC; signal matched_out_V_1_vld_out : STD_LOGIC; signal matched_out_V_1_ack_in : STD_LOGIC; signal matched_out_V_1_ack_out : STD_LOGIC; signal matched_out_V_1_payload_A : STD_LOGIC_VECTOR (7 downto 0); signal matched_out_V_1_payload_B : STD_LOGIC_VECTOR (7 downto 0); signal matched_out_V_1_sel_rd : STD_LOGIC := '0'; signal matched_out_V_1_sel_wr : STD_LOGIC := '0'; signal matched_out_V_1_sel : STD_LOGIC; signal matched_out_V_1_load_A : STD_LOGIC; signal matched_out_V_1_load_B : STD_LOGIC; signal matched_out_V_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal matched_out_V_1_state_cmp_full : STD_LOGIC; signal matched_finished_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal matched_finished_1_data_in : STD_LOGIC_VECTOR (31 downto 0); signal matched_finished_1_vld_reg : STD_LOGIC := '0'; signal matched_finished_1_vld_in : STD_LOGIC; signal matched_finished_1_ack_in : STD_LOGIC; signal error_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal error_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0); signal error_out_1_vld_reg : STD_LOGIC := '0'; signal error_out_1_vld_in : STD_LOGIC; signal error_out_1_ack_in : STD_LOGIC; signal contacts_size_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal contacts_size_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0); signal contacts_size_out_1_vld_reg : STD_LOGIC := '0'; signal contacts_size_out_1_vld_in : STD_LOGIC; signal contacts_size_out_1_ack_in : STD_LOGIC; signal contacts_size : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal contacts_address0 : STD_LOGIC_VECTOR (12 downto 0); signal contacts_ce0 : STD_LOGIC; signal contacts_we0 : STD_LOGIC; signal contacts_d0 : STD_LOGIC_VECTOR (7 downto 0); signal contacts_q0 : STD_LOGIC_VECTOR (7 downto 0); signal current_database_ite_address0 : STD_LOGIC_VECTOR (5 downto 0); signal current_database_ite_ce0 : STD_LOGIC; signal current_database_ite_we0 : STD_LOGIC; signal current_database_ite_q0 : STD_LOGIC_VECTOR (7 downto 0); signal operation_blk_n : STD_LOGIC; signal ap_CS_fsm_state2 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none"; signal contacts_in_V_TDATA_blk_n : STD_LOGIC; signal ap_CS_fsm_state15 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state15 : signal is "none"; signal ap_CS_fsm_state13 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state13 : signal is "none"; signal exitcond9_fu_444_p2 : STD_LOGIC_VECTOR (0 downto 0); signal database_in_V_TDATA_blk_n : STD_LOGIC; signal ap_CS_fsm_state6 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none"; signal exitcond8_fu_329_p2 : STD_LOGIC_VECTOR (0 downto 0); signal matched_out_V_TDATA_blk_n : STD_LOGIC; signal ap_CS_fsm_state7 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none"; signal exitcond7_fu_346_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_state10 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none"; signal grp_read_fu_98_p2 : STD_LOGIC_VECTOR (31 downto 0); signal i_fu_318_p2 : STD_LOGIC_VECTOR (7 downto 0); signal ap_CS_fsm_state4 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none"; signal i_2_fu_335_p2 : STD_LOGIC_VECTOR (6 downto 0); signal ap_block_state6 : BOOLEAN; signal i_5_fu_352_p2 : STD_LOGIC_VECTOR (7 downto 0); signal i_5_reg_512 : STD_LOGIC_VECTOR (7 downto 0); signal ap_block_state7_io : BOOLEAN; signal tmp_i_fu_362_p3 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_i_reg_517 : STD_LOGIC_VECTOR (12 downto 0); signal cast_fu_370_p1 : STD_LOGIC_VECTOR (7 downto 0); signal i_6_fu_385_p2 : STD_LOGIC_VECTOR (6 downto 0); signal i_6_reg_530 : STD_LOGIC_VECTOR (6 downto 0); signal ap_CS_fsm_state8 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none"; signal exitcond_i_fu_379_p2 : STD_LOGIC_VECTOR (0 downto 0); signal found_fu_406_p2 : STD_LOGIC_VECTOR (0 downto 0); signal found_1_fu_418_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_state9 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none"; signal icmp_fu_434_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_state12 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none"; signal tmp_nbreadreq_fu_151_p3 : STD_LOGIC_VECTOR (0 downto 0); signal i_4_fu_450_p2 : STD_LOGIC_VECTOR (6 downto 0); signal ap_block_state13 : BOOLEAN; signal tmp_9_fu_473_p2 : STD_LOGIC_VECTOR (31 downto 0); signal i_3_reg_217 : STD_LOGIC_VECTOR (7 downto 0); signal ap_CS_fsm_state3 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none"; signal exitcond_fu_312_p2 : STD_LOGIC_VECTOR (0 downto 0); signal i_1_reg_228 : STD_LOGIC_VECTOR (6 downto 0); signal ap_CS_fsm_state5 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none"; signal tmp_1_nbreadreq_fu_129_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_10_reg_239 : STD_LOGIC_VECTOR (0 downto 0); signal contact_index_assign_reg_251 : STD_LOGIC_VECTOR (7 downto 0); signal i_i_reg_262 : STD_LOGIC_VECTOR (6 downto 0); signal comp_reg_273 : STD_LOGIC_VECTOR (0 downto 0); signal i1_reg_285 : STD_LOGIC_VECTOR (6 downto 0); signal tmp_3_fu_324_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_7_fu_341_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_i_7_fu_391_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_13_i_fu_401_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_s_fu_468_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_11_fu_358_p1 : STD_LOGIC_VECTOR (6 downto 0); signal i_i_cast7_fu_375_p1 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_12_i_fu_396_p2 : STD_LOGIC_VECTOR (12 downto 0); signal tmp_14_i_fu_412_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_2_fu_424_p4 : STD_LOGIC_VECTOR (24 downto 0); signal tmp_6_fu_456_p2 : STD_LOGIC_VECTOR (31 downto 0); signal i1_cast_fu_440_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_8_fu_462_p2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state11 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none"; signal ap_block_state11 : BOOLEAN; signal ap_NS_fsm : STD_LOGIC_VECTOR (14 downto 0); component contact_discoverybkb IS generic ( DataWidth : INTEGER; AddressRange : INTEGER; AddressWidth : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR (12 downto 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR (7 downto 0); q0 : OUT STD_LOGIC_VECTOR (7 downto 0) ); end component; component contact_discoverycud IS generic ( DataWidth : INTEGER; AddressRange : INTEGER; AddressWidth : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR (5 downto 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR (7 downto 0); q0 : OUT STD_LOGIC_VECTOR (7 downto 0) ); end component; component contact_discovery_AXILiteS_s_axi IS generic ( C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( AWVALID : IN STD_LOGIC; AWREADY : OUT STD_LOGIC; AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); WVALID : IN STD_LOGIC; WREADY : OUT STD_LOGIC; WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0); ARVALID : IN STD_LOGIC; ARREADY : OUT STD_LOGIC; ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); RVALID : OUT STD_LOGIC; RREADY : IN STD_LOGIC; RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); BVALID : OUT STD_LOGIC; BREADY : IN STD_LOGIC; BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; ap_start : OUT STD_LOGIC; interrupt : OUT STD_LOGIC; ap_ready : IN STD_LOGIC; ap_done : IN STD_LOGIC; ap_idle : IN STD_LOGIC; operation : OUT STD_LOGIC_VECTOR (31 downto 0); operation_ap_vld : OUT STD_LOGIC; matched_finished : IN STD_LOGIC_VECTOR (31 downto 0); error_out : IN STD_LOGIC_VECTOR (31 downto 0); contacts_size_out : IN STD_LOGIC_VECTOR (31 downto 0) ); end component; begin contacts_U : component contact_discoverybkb generic map ( DataWidth => 8, AddressRange => 8192, AddressWidth => 13) port map ( clk => ap_clk, reset => ap_rst_n_inv, address0 => contacts_address0, ce0 => contacts_ce0, we0 => contacts_we0, d0 => contacts_d0, q0 => contacts_q0); current_database_ite_U : component contact_discoverycud generic map ( DataWidth => 8, AddressRange => 64, AddressWidth => 6) port map ( clk => ap_clk, reset => ap_rst_n_inv, address0 => current_database_ite_address0, ce0 => current_database_ite_ce0, we0 => current_database_ite_we0, d0 => database_in_V_TDATA, q0 => current_database_ite_q0); contact_discovery_AXILiteS_s_axi_U : component contact_discovery_AXILiteS_s_axi generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH) port map ( AWVALID => s_axi_AXILiteS_AWVALID, AWREADY => s_axi_AXILiteS_AWREADY, AWADDR => s_axi_AXILiteS_AWADDR, WVALID => s_axi_AXILiteS_WVALID, WREADY => s_axi_AXILiteS_WREADY, WDATA => s_axi_AXILiteS_WDATA, WSTRB => s_axi_AXILiteS_WSTRB, ARVALID => s_axi_AXILiteS_ARVALID, ARREADY => s_axi_AXILiteS_ARREADY, ARADDR => s_axi_AXILiteS_ARADDR, RVALID => s_axi_AXILiteS_RVALID, RREADY => s_axi_AXILiteS_RREADY, RDATA => s_axi_AXILiteS_RDATA, RRESP => s_axi_AXILiteS_RRESP, BVALID => s_axi_AXILiteS_BVALID, BREADY => s_axi_AXILiteS_BREADY, BRESP => s_axi_AXILiteS_BRESP, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, ap_start => ap_start, interrupt => interrupt, ap_ready => ap_ready, ap_done => ap_done, ap_idle => ap_idle, operation => operation, operation_ap_vld => operation_ap_vld, matched_finished => matched_finished_1_data_reg, error_out => error_out_1_data_reg, contacts_size_out => contacts_size_out_1_data_reg); ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_CS_fsm <= ap_ST_fsm_state1; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; matched_out_V_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then matched_out_V_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = matched_out_V_1_ack_out) and (ap_const_logic_1 = matched_out_V_1_vld_out))) then matched_out_V_1_sel_rd <= not(matched_out_V_1_sel_rd); end if; end if; end if; end process; matched_out_V_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then matched_out_V_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = matched_out_V_1_vld_in) and (ap_const_logic_1 = matched_out_V_1_ack_in))) then matched_out_V_1_sel_wr <= not(matched_out_V_1_sel_wr); end if; end if; end if; end process; matched_out_V_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then matched_out_V_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = matched_out_V_1_vld_in) and (ap_const_logic_1 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = matched_out_V_1_vld_in) and (matched_out_V_1_state = ap_const_lv2_2)))) then matched_out_V_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = matched_out_V_1_vld_in) and (ap_const_logic_0 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_1)))) then matched_out_V_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = matched_out_V_1_vld_in) and (matched_out_V_1_state = ap_const_lv2_2)) or ((ap_const_logic_1 = matched_out_V_1_ack_out) and (matched_out_V_1_state = ap_const_lv2_1)) or ((matched_out_V_1_state = ap_const_lv2_3) and not(((ap_const_logic_1 = matched_out_V_1_vld_in) and (ap_const_logic_0 = matched_out_V_1_ack_out))) and not(((ap_const_logic_0 = matched_out_V_1_vld_in) and (ap_const_logic_1 = matched_out_V_1_ack_out)))))) then matched_out_V_1_state <= ap_const_lv2_3; else matched_out_V_1_state <= ap_const_lv2_2; end if; end if; end if; end process; operation_ap_vld_preg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then operation_ap_vld_preg <= ap_const_logic_0; else if (((ap_const_logic_1 = operation_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then operation_ap_vld_preg <= operation_ap_vld; elsif (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then operation_ap_vld_preg <= ap_const_logic_0; end if; end if; end if; end process; operation_preg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then operation_preg <= ap_const_lv32_0; else if (((ap_const_logic_1 = operation_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then operation_preg <= operation; end if; end if; end if; end process; comp_reg_273_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state9)) then comp_reg_273 <= found_1_fu_418_p2; elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then comp_reg_273 <= ap_const_lv1_1; end if; end if; end process; contact_index_assign_reg_251_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))) and (ap_const_lv1_1 = exitcond8_fu_329_p2))) then contact_index_assign_reg_251 <= ap_const_lv8_0; elsif (((ap_const_logic_1 = ap_CS_fsm_state8) and (ap_const_lv1_1 = exitcond_i_fu_379_p2))) then contact_index_assign_reg_251 <= i_5_reg_512; end if; end if; end process; contacts_size_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2))) then contacts_size <= tmp_9_fu_473_p2; elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2))) then contacts_size <= ap_const_lv32_0; end if; end if; end process; contacts_size_out_1_vld_reg_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then end if; end process; error_out_1_vld_reg_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then end if; end process; i1_reg_285_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_0 = icmp_fu_434_p2))) then i1_reg_285 <= ap_const_lv7_0; elsif (((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))))) then i1_reg_285 <= i_4_fu_450_p2; end if; end if; end process; i_1_reg_228_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_1 = tmp_1_nbreadreq_fu_129_p3))) then i_1_reg_228 <= ap_const_lv7_0; elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then i_1_reg_228 <= i_2_fu_335_p2; end if; end if; end process; i_3_reg_217_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = exitcond_fu_312_p2))) then i_3_reg_217 <= i_fu_318_p2; elsif (((grp_read_fu_98_p2 = ap_const_lv32_2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then i_3_reg_217 <= ap_const_lv8_0; end if; end if; end process; i_i_reg_262_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state9)) then i_i_reg_262 <= i_6_reg_530; elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then i_i_reg_262 <= ap_const_lv7_0; end if; end if; end process; matched_finished_1_vld_reg_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then end if; end process; tmp_10_reg_239_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))) and (ap_const_lv1_1 = exitcond8_fu_329_p2))) then tmp_10_reg_239 <= ap_const_lv1_0; elsif (((ap_const_logic_1 = ap_CS_fsm_state8) and (ap_const_lv1_1 = exitcond_i_fu_379_p2))) then tmp_10_reg_239 <= found_fu_406_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = contacts_size_out_1_vld_in) and (ap_const_logic_0 = contacts_size_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = contacts_size_out_1_vld_in) and (ap_const_logic_1 = contacts_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then contacts_size_out_1_data_reg <= contacts_size_out_1_data_in; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = error_out_1_vld_in) and (ap_const_logic_0 = error_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = error_out_1_vld_in) and (ap_const_logic_1 = error_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then error_out_1_data_reg <= error_out_1_data_in; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0))) then i_5_reg_512 <= i_5_fu_352_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state8)) then i_6_reg_530 <= i_6_fu_385_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = matched_finished_1_vld_in) and (ap_const_logic_0 = matched_finished_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = matched_finished_1_vld_in) and (ap_const_logic_1 = matched_finished_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then matched_finished_1_data_reg <= matched_finished_1_data_in; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = matched_out_V_1_load_A)) then matched_out_V_1_payload_A <= cast_fu_370_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = matched_out_V_1_load_B)) then matched_out_V_1_payload_B <= cast_fu_370_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then tmp_i_reg_517(12 downto 6) <= tmp_i_fu_362_p3(12 downto 6); end if; end if; end process; tmp_i_reg_517(5 downto 0) <= "000000"; ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, operation_ap_vld_in_sig, contacts_in_V_TVALID, database_in_V_TVALID, matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state2, ap_CS_fsm_state15, ap_CS_fsm_state13, exitcond9_fu_444_p2, ap_CS_fsm_state6, exitcond8_fu_329_p2, ap_CS_fsm_state7, exitcond7_fu_346_p2, ap_CS_fsm_state10, grp_read_fu_98_p2, ap_CS_fsm_state4, ap_block_state7_io, ap_CS_fsm_state8, exitcond_i_fu_379_p2, icmp_fu_434_p2, ap_CS_fsm_state12, tmp_nbreadreq_fu_151_p3, ap_CS_fsm_state3, exitcond_fu_312_p2, ap_CS_fsm_state5, tmp_1_nbreadreq_fu_129_p3, ap_CS_fsm_state11) begin case ap_CS_fsm is when ap_ST_fsm_state1 => if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then ap_NS_fsm <= ap_ST_fsm_state2; else ap_NS_fsm <= ap_ST_fsm_state1; end if; when ap_ST_fsm_state2 => if (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1))) then ap_NS_fsm <= ap_ST_fsm_state3; else ap_NS_fsm <= ap_ST_fsm_state2; end if; when ap_ST_fsm_state3 => if ((not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2)) and (ap_const_logic_1 = ap_CS_fsm_state3))) then ap_NS_fsm <= ap_ST_fsm_state11; elsif (((ap_const_lv32_0 = grp_read_fu_98_p2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then ap_NS_fsm <= ap_ST_fsm_state12; elsif (((ap_const_lv32_1 = grp_read_fu_98_p2) and (ap_const_logic_1 = ap_CS_fsm_state3))) then ap_NS_fsm <= ap_ST_fsm_state5; else ap_NS_fsm <= ap_ST_fsm_state4; end if; when ap_ST_fsm_state4 => if (((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_1 = exitcond_fu_312_p2))) then ap_NS_fsm <= ap_ST_fsm_state11; else ap_NS_fsm <= ap_ST_fsm_state4; end if; when ap_ST_fsm_state5 => if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_1 = tmp_1_nbreadreq_fu_129_p3))) then ap_NS_fsm <= ap_ST_fsm_state6; else ap_NS_fsm <= ap_ST_fsm_state11; end if; when ap_ST_fsm_state6 => if (((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))) and (ap_const_lv1_1 = exitcond8_fu_329_p2))) then ap_NS_fsm <= ap_ST_fsm_state7; elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then ap_NS_fsm <= ap_ST_fsm_state6; else ap_NS_fsm <= ap_ST_fsm_state6; end if; when ap_ST_fsm_state7 => if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_block_state7_io = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond7_fu_346_p2))) then ap_NS_fsm <= ap_ST_fsm_state8; elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_1 = exitcond7_fu_346_p2) and (ap_block_state7_io = ap_const_boolean_0))) then ap_NS_fsm <= ap_ST_fsm_state10; else ap_NS_fsm <= ap_ST_fsm_state7; end if; when ap_ST_fsm_state8 => if (((ap_const_logic_1 = ap_CS_fsm_state8) and (ap_const_lv1_1 = exitcond_i_fu_379_p2))) then ap_NS_fsm <= ap_ST_fsm_state7; else ap_NS_fsm <= ap_ST_fsm_state9; end if; when ap_ST_fsm_state9 => ap_NS_fsm <= ap_ST_fsm_state8; when ap_ST_fsm_state10 => if (((ap_const_logic_1 = ap_CS_fsm_state10) and (matched_out_V_1_ack_in = ap_const_logic_1))) then ap_NS_fsm <= ap_ST_fsm_state5; else ap_NS_fsm <= ap_ST_fsm_state10; end if; when ap_ST_fsm_state11 => if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then ap_NS_fsm <= ap_ST_fsm_state1; else ap_NS_fsm <= ap_ST_fsm_state11; end if; when ap_ST_fsm_state12 => if (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_0 = tmp_nbreadreq_fu_151_p3))) then ap_NS_fsm <= ap_ST_fsm_state11; elsif (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_0 = icmp_fu_434_p2))) then ap_NS_fsm <= ap_ST_fsm_state13; else ap_NS_fsm <= ap_ST_fsm_state15; end if; when ap_ST_fsm_state13 => if (((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))))) then ap_NS_fsm <= ap_ST_fsm_state13; elsif (((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2))) then ap_NS_fsm <= ap_ST_fsm_state14; else ap_NS_fsm <= ap_ST_fsm_state13; end if; when ap_ST_fsm_state14 => ap_NS_fsm <= ap_ST_fsm_state12; when ap_ST_fsm_state15 => if (((ap_const_logic_1 = ap_CS_fsm_state15) and (contacts_in_V_TVALID = ap_const_logic_1))) then ap_NS_fsm <= ap_ST_fsm_state14; else ap_NS_fsm <= ap_ST_fsm_state15; end if; when others => ap_NS_fsm <= "XXXXXXXXXXXXXXX"; end case; end process; ap_CS_fsm_state1 <= ap_CS_fsm(0); ap_CS_fsm_state10 <= ap_CS_fsm(9); ap_CS_fsm_state11 <= ap_CS_fsm(10); ap_CS_fsm_state12 <= ap_CS_fsm(11); ap_CS_fsm_state13 <= ap_CS_fsm(12); ap_CS_fsm_state15 <= ap_CS_fsm(14); ap_CS_fsm_state2 <= ap_CS_fsm(1); ap_CS_fsm_state3 <= ap_CS_fsm(2); ap_CS_fsm_state4 <= ap_CS_fsm(3); ap_CS_fsm_state5 <= ap_CS_fsm(4); ap_CS_fsm_state6 <= ap_CS_fsm(5); ap_CS_fsm_state7 <= ap_CS_fsm(6); ap_CS_fsm_state8 <= ap_CS_fsm(7); ap_CS_fsm_state9 <= ap_CS_fsm(8); ap_block_state11_assign_proc : process(matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in) begin ap_block_state11 <= ((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in)); end process; ap_block_state13_assign_proc : process(contacts_in_V_TVALID, exitcond9_fu_444_p2) begin ap_block_state13 <= ((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID)); end process; ap_block_state6_assign_proc : process(database_in_V_TVALID, exitcond8_fu_329_p2) begin ap_block_state6 <= ((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID)); end process; ap_block_state7_io_assign_proc : process(matched_out_V_1_ack_in, exitcond7_fu_346_p2) begin ap_block_state7_io <= ((ap_const_lv1_1 = exitcond7_fu_346_p2) and (ap_const_logic_0 = matched_out_V_1_ack_in)); end process; ap_done_assign_proc : process(matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state11) begin if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_ready_assign_proc : process(matched_out_V_1_ack_in, matched_finished_1_ack_in, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state11) begin if (((ap_const_logic_1 = ap_CS_fsm_state11) and not(((ap_const_logic_0 = matched_out_V_1_ack_in) or (ap_const_logic_0 = matched_finished_1_ack_in) or (ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_rst_n_inv_assign_proc : process(ap_rst_n) begin ap_rst_n_inv <= not(ap_rst_n); end process; cast_fu_370_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_reg_239),8)); contacts_address0_assign_proc : process(ap_CS_fsm_state13, ap_CS_fsm_state4, ap_CS_fsm_state8, tmp_3_fu_324_p1, tmp_13_i_fu_401_p1, tmp_s_fu_468_p1) begin if ((ap_const_logic_1 = ap_CS_fsm_state13)) then contacts_address0 <= tmp_s_fu_468_p1(13 - 1 downto 0); elsif ((ap_const_logic_1 = ap_CS_fsm_state8)) then contacts_address0 <= tmp_13_i_fu_401_p1(13 - 1 downto 0); elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then contacts_address0 <= tmp_3_fu_324_p1(13 - 1 downto 0); else contacts_address0 <= "XXXXXXXXXXXXX"; end if; end process; contacts_ce0_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state13, exitcond9_fu_444_p2, ap_CS_fsm_state4, ap_CS_fsm_state8) begin if (((ap_const_logic_1 = ap_CS_fsm_state4) or (ap_const_logic_1 = ap_CS_fsm_state8) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID)))))) then contacts_ce0 <= ap_const_logic_1; else contacts_ce0 <= ap_const_logic_0; end if; end process; contacts_d0_assign_proc : process(contacts_in_V_TDATA, ap_CS_fsm_state13, ap_CS_fsm_state4) begin if ((ap_const_logic_1 = ap_CS_fsm_state13)) then contacts_d0 <= contacts_in_V_TDATA; elsif ((ap_const_logic_1 = ap_CS_fsm_state4)) then contacts_d0 <= ap_const_lv8_0; else contacts_d0 <= "XXXXXXXX"; end if; end process; contacts_in_V_TDATA_blk_n_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state15, ap_CS_fsm_state13, exitcond9_fu_444_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state15) or ((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2)))) then contacts_in_V_TDATA_blk_n <= contacts_in_V_TVALID; else contacts_in_V_TDATA_blk_n <= ap_const_logic_1; end if; end process; contacts_in_V_TREADY_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state15, ap_CS_fsm_state13, exitcond9_fu_444_p2) begin if ((((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID)))) or ((ap_const_logic_1 = ap_CS_fsm_state15) and (contacts_in_V_TVALID = ap_const_logic_1)))) then contacts_in_V_TREADY <= ap_const_logic_1; else contacts_in_V_TREADY <= ap_const_logic_0; end if; end process; contacts_size_out_1_ack_in_assign_proc : process(contacts_size_out_1_vld_reg) begin if (((ap_const_logic_0 = contacts_size_out_1_vld_reg) or ((ap_const_logic_1 = contacts_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then contacts_size_out_1_ack_in <= ap_const_logic_1; else contacts_size_out_1_ack_in <= ap_const_logic_0; end if; end process; contacts_size_out_1_data_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, contacts_size, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2, tmp_9_fu_473_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2))) then contacts_size_out_1_data_in <= tmp_9_fu_473_p2; elsif ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))))) then contacts_size_out_1_data_in <= contacts_size; elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2))) then contacts_size_out_1_data_in <= ap_const_lv32_0; else contacts_size_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; contacts_size_out_1_vld_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2) begin if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)))) then contacts_size_out_1_vld_in <= ap_const_logic_1; else contacts_size_out_1_vld_in <= ap_const_logic_0; end if; end process; contacts_we0_assign_proc : process(contacts_in_V_TVALID, ap_CS_fsm_state13, exitcond9_fu_444_p2, ap_CS_fsm_state4, exitcond_fu_312_p2) begin if ((((ap_const_logic_1 = ap_CS_fsm_state4) and (ap_const_lv1_0 = exitcond_fu_312_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state13) and (ap_const_lv1_0 = exitcond9_fu_444_p2) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID)))))) then contacts_we0 <= ap_const_logic_1; else contacts_we0 <= ap_const_logic_0; end if; end process; current_database_ite_address0_assign_proc : process(ap_CS_fsm_state6, ap_CS_fsm_state8, tmp_7_fu_341_p1, tmp_i_7_fu_391_p1) begin if ((ap_const_logic_1 = ap_CS_fsm_state8)) then current_database_ite_address0 <= tmp_i_7_fu_391_p1(6 - 1 downto 0); elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then current_database_ite_address0 <= tmp_7_fu_341_p1(6 - 1 downto 0); else current_database_ite_address0 <= "XXXXXX"; end if; end process; current_database_ite_ce0_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2, ap_CS_fsm_state8) begin if ((((ap_const_logic_1 = ap_CS_fsm_state6) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID)))) or (ap_const_logic_1 = ap_CS_fsm_state8))) then current_database_ite_ce0 <= ap_const_logic_1; else current_database_ite_ce0 <= ap_const_logic_0; end if; end process; current_database_ite_we0_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then current_database_ite_we0 <= ap_const_logic_1; else current_database_ite_we0 <= ap_const_logic_0; end if; end process; database_in_V_TDATA_blk_n_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2))) then database_in_V_TDATA_blk_n <= database_in_V_TVALID; else database_in_V_TDATA_blk_n <= ap_const_logic_1; end if; end process; database_in_V_TREADY_assign_proc : process(database_in_V_TVALID, ap_CS_fsm_state6, exitcond8_fu_329_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = exitcond8_fu_329_p2) and not(((ap_const_lv1_0 = exitcond8_fu_329_p2) and (ap_const_logic_0 = database_in_V_TVALID))))) then database_in_V_TREADY <= ap_const_logic_1; else database_in_V_TREADY <= ap_const_logic_0; end if; end process; error_out_1_ack_in_assign_proc : process(error_out_1_vld_reg) begin if (((ap_const_logic_0 = error_out_1_vld_reg) or ((ap_const_logic_1 = error_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then error_out_1_ack_in <= ap_const_logic_1; else error_out_1_ack_in <= ap_const_logic_0; end if; end process; error_out_1_data_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2, icmp_fu_434_p2, ap_CS_fsm_state12, tmp_nbreadreq_fu_151_p3) begin if (((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_1 = icmp_fu_434_p2))) then error_out_1_data_in <= ap_const_lv32_1; elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2)))) then error_out_1_data_in <= ap_const_lv32_3; elsif ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)))) then error_out_1_data_in <= ap_const_lv32_0; else error_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; error_out_1_vld_in_assign_proc : process(operation_ap_vld_in_sig, contacts_in_V_TVALID, ap_CS_fsm_state2, ap_CS_fsm_state13, exitcond9_fu_444_p2, grp_read_fu_98_p2, icmp_fu_434_p2, ap_CS_fsm_state12, tmp_nbreadreq_fu_151_p3) begin if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_1 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state13) and not(((ap_const_lv1_0 = exitcond9_fu_444_p2) and (ap_const_logic_0 = contacts_in_V_TVALID))) and (ap_const_lv1_1 = exitcond9_fu_444_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state12) and (ap_const_lv1_1 = tmp_nbreadreq_fu_151_p3) and (ap_const_lv1_1 = icmp_fu_434_p2)))) then error_out_1_vld_in <= ap_const_logic_1; else error_out_1_vld_in <= ap_const_logic_0; end if; end process; exitcond7_fu_346_p2 <= "1" when (contact_index_assign_reg_251 = ap_const_lv8_80) else "0"; exitcond8_fu_329_p2 <= "1" when (i_1_reg_228 = ap_const_lv7_40) else "0"; exitcond9_fu_444_p2 <= "1" when (i1_reg_285 = ap_const_lv7_40) else "0"; exitcond_fu_312_p2 <= "1" when (i_3_reg_217 = ap_const_lv8_80) else "0"; exitcond_i_fu_379_p2 <= "1" when (i_i_reg_262 = ap_const_lv7_40) else "0"; found_1_fu_418_p2 <= (tmp_14_i_fu_412_p2 and comp_reg_273); found_fu_406_p2 <= (comp_reg_273 or tmp_10_reg_239); grp_read_fu_98_p2 <= operation_preg; i1_cast_fu_440_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i1_reg_285),32)); i_2_fu_335_p2 <= std_logic_vector(unsigned(i_1_reg_228) + unsigned(ap_const_lv7_1)); i_4_fu_450_p2 <= std_logic_vector(unsigned(i1_reg_285) + unsigned(ap_const_lv7_1)); i_5_fu_352_p2 <= std_logic_vector(unsigned(contact_index_assign_reg_251) + unsigned(ap_const_lv8_1)); i_6_fu_385_p2 <= std_logic_vector(unsigned(i_i_reg_262) + unsigned(ap_const_lv7_1)); i_fu_318_p2 <= std_logic_vector(unsigned(i_3_reg_217) + unsigned(ap_const_lv8_1)); i_i_cast7_fu_375_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_reg_262),13)); icmp_fu_434_p2 <= "1" when (signed(tmp_2_fu_424_p4) > signed(ap_const_lv25_0)) else "0"; matched_finished_1_ack_in_assign_proc : process(matched_finished_1_vld_reg) begin if (((ap_const_logic_0 = matched_finished_1_vld_reg) or ((ap_const_logic_1 = matched_finished_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then matched_finished_1_ack_in <= ap_const_logic_1; else matched_finished_1_ack_in <= ap_const_logic_0; end if; end process; matched_finished_1_data_in_assign_proc : process(operation_ap_vld_in_sig, ap_CS_fsm_state2, grp_read_fu_98_p2, ap_CS_fsm_state5, tmp_1_nbreadreq_fu_129_p3) begin if (((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = tmp_1_nbreadreq_fu_129_p3))) then matched_finished_1_data_in <= ap_const_lv32_1; elsif ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)))) then matched_finished_1_data_in <= ap_const_lv32_0; else matched_finished_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; matched_finished_1_vld_in_assign_proc : process(operation_ap_vld_in_sig, ap_CS_fsm_state2, grp_read_fu_98_p2, ap_CS_fsm_state5, tmp_1_nbreadreq_fu_129_p3) begin if ((((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (ap_const_lv32_0 = grp_read_fu_98_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and not((ap_const_lv32_0 = grp_read_fu_98_p2)) and not((ap_const_lv32_1 = grp_read_fu_98_p2)) and not((grp_read_fu_98_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (operation_ap_vld_in_sig = ap_const_logic_1) and (grp_read_fu_98_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state5) and (ap_const_lv1_0 = tmp_1_nbreadreq_fu_129_p3)))) then matched_finished_1_vld_in <= ap_const_logic_1; else matched_finished_1_vld_in <= ap_const_logic_0; end if; end process; matched_out_V_1_ack_in <= matched_out_V_1_state(1); matched_out_V_1_ack_out <= matched_out_V_TREADY; matched_out_V_1_data_out_assign_proc : process(matched_out_V_1_payload_A, matched_out_V_1_payload_B, matched_out_V_1_sel) begin if ((ap_const_logic_1 = matched_out_V_1_sel)) then matched_out_V_1_data_out <= matched_out_V_1_payload_B; else matched_out_V_1_data_out <= matched_out_V_1_payload_A; end if; end process; matched_out_V_1_load_A <= (matched_out_V_1_state_cmp_full and not(matched_out_V_1_sel_wr)); matched_out_V_1_load_B <= (matched_out_V_1_sel_wr and matched_out_V_1_state_cmp_full); matched_out_V_1_sel <= matched_out_V_1_sel_rd; matched_out_V_1_state_cmp_full <= '0' when (matched_out_V_1_state = ap_const_lv2_1) else '1'; matched_out_V_1_vld_in_assign_proc : process(ap_CS_fsm_state7, exitcond7_fu_346_p2, ap_block_state7_io) begin if (((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_1 = exitcond7_fu_346_p2) and (ap_block_state7_io = ap_const_boolean_0))) then matched_out_V_1_vld_in <= ap_const_logic_1; else matched_out_V_1_vld_in <= ap_const_logic_0; end if; end process; matched_out_V_1_vld_out <= matched_out_V_1_state(0); matched_out_V_TDATA <= matched_out_V_1_data_out; matched_out_V_TDATA_blk_n_assign_proc : process(matched_out_V_1_state, ap_CS_fsm_state7, exitcond7_fu_346_p2, ap_CS_fsm_state10) begin if ((((ap_const_logic_1 = ap_CS_fsm_state7) and (ap_const_lv1_1 = exitcond7_fu_346_p2)) or (ap_const_logic_1 = ap_CS_fsm_state10))) then matched_out_V_TDATA_blk_n <= matched_out_V_1_state(1); else matched_out_V_TDATA_blk_n <= ap_const_logic_1; end if; end process; matched_out_V_TVALID <= matched_out_V_1_state(0); operation_ap_vld_in_sig <= operation_ap_vld_preg; operation_blk_n_assign_proc : process(ap_CS_fsm_state2) begin if ((ap_const_logic_1 = ap_CS_fsm_state2)) then operation_blk_n <= ap_const_logic_0; else operation_blk_n <= ap_const_logic_1; end if; end process; tmp_11_fu_358_p1 <= contact_index_assign_reg_251(7 - 1 downto 0); tmp_12_i_fu_396_p2 <= std_logic_vector(unsigned(i_i_cast7_fu_375_p1) + unsigned(tmp_i_reg_517)); tmp_13_i_fu_401_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_12_i_fu_396_p2),64)); tmp_14_i_fu_412_p2 <= "1" when (current_database_ite_q0 = contacts_q0) else "0"; tmp_1_nbreadreq_fu_129_p3 <= (0=>database_in_V_TVALID, others=>'-'); tmp_2_fu_424_p4 <= contacts_size(31 downto 7); tmp_3_fu_324_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_3_reg_217),64)); tmp_6_fu_456_p2 <= std_logic_vector(shift_left(unsigned(contacts_size),to_integer(unsigned('0' & ap_const_lv32_6(31-1 downto 0))))); tmp_7_fu_341_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_1_reg_228),64)); tmp_8_fu_462_p2 <= std_logic_vector(unsigned(tmp_6_fu_456_p2) + unsigned(i1_cast_fu_440_p1)); tmp_9_fu_473_p2 <= std_logic_vector(unsigned(contacts_size) + unsigned(ap_const_lv32_1)); tmp_i_7_fu_391_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_i_reg_262),64)); tmp_i_fu_362_p3 <= (tmp_11_fu_358_p1 & ap_const_lv6_0); tmp_nbreadreq_fu_151_p3 <= (0=>contacts_in_V_TVALID, others=>'-'); tmp_s_fu_468_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_8_fu_462_p2),64)); end behav; |
library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; use work.ROCACHE_PKG.all; entity ROCACHE is port ( CLK : in std_logic; RST : in std_logic; -- active high ENABLE : in std_logic; ADDRESS : in std_logic_vector(INSTR_SIZE - 1 downto 0); OUT_DATA : out std_logic_vector(INSTR_SIZE - 1 downto 0); STALL : out std_logic; RAM_ISSUE : out std_logic; RAM_ADDRESS : out std_logic_vector(INSTR_SIZE - 1 downto 0); RAM_DATA : in std_logic_vector(2*INSTR_SIZE - 1 downto 0); RAM_READY : in std_logic ); end ROCACHE; architecture Behavioral of ROCACHE is signal ICACHE,ICACHE_REG : ROCACHE_TYPE; signal STATE_CURRENT : state_type; signal STATE_NEXT : state_type; signal INT_ISSUE_RAM_READ : std_logic; signal INT_OUT_DATA : std_logic_vector(INSTR_SIZE -1 downto 0) := (others => '0'); signal INT_STALL : std_logic; begin -- -- FSM Management -- state_update: process(CLK, RST, STATE_NEXT,ICACHE) begin if RST = '1' then STATE_CURRENT <= STATE_FLUSH_MEM; elsif clk'event and clk = '1' then STATE_CURRENT <= STATE_NEXT; ICACHE_REG <= ICACHE; end if; end process; -- -- The MONSTER -- main: process(STATE_CURRENT, ADDRESS, RAM_READY, RAM_DATA, INT_ISSUE_RAM_READ, ENABLE, ICACHE_REG) variable HIT : std_logic:='0'; variable int_mem : std_logic_vector(2*INSTR_SIZE - 1 downto 0); variable currentLine : natural range 0 to 2**ROCACHE_COUNTERSIZE; variable count_miss : natural range 0 to ROCACHE_NUMLINES; variable index : natural range 0 to 2**ROCACHE_INDEXOFFSET - 1; variable lineIndex : natural range 0 to ROCACHE_NUMLINES; variable test : natural; variable address_stall : std_logic_vector(INSTR_SIZE - 1 downto 0); begin count_miss := 0; ICACHE <= ICACHE_REG; case (STATE_CURRENT) is when STATE_FLUSH_MEM => for i in 0 to ROCACHE_NUMSETS - 1 loop for j in 0 to ROCACHE_NUMLINES - 1 loop ICACHE(i)(j).tag( ROCACHE_TAGSIZE - 1 downto 0 ) <= (others => '0'); ICACHE(i)(j).valid <= '0'; -- dirty bit ICACHE(i)(j).counter <= 0; for k in 0 to ROCACHE_WORDS - 1 loop ICACHE(i)(j).words(k) <= (others => '1'); end loop; end loop; end loop; address_stall := (others => '0'); HIT := '0'; INT_ISSUE_RAM_READ <= '0'; STATE_NEXT <= STATE_IDLE; -- IDLE STATE -- Do nothing, assume miss when STATE_IDLE => STATE_NEXT <= STATE_COMPARE_TAGS; -- MISS STATE -- Probe the RAM and wait until RAM_READY when STATE_MISS => -- I gots the data if RAM_READY = '1' then -- Identify line to hold the new data currentLine := GET_REPLACEMENT_LINE(address_stall, ICACHE_REG); -- Store TAG ICACHE(GET_SET(address_stall))(currentLine).tag <= address_stall(INSTR_SIZE - 1 downto ROCACHE_TAGOFFSET); -- Reset LFU counter ICACHE(GET_SET(address_stall))(currentLine).counter <= 0; -- Set valid bit ICACHE(GET_SET(address_stall))(currentLine).valid <= '1'; -- Fetch the line from memory data bus and write it into the cache data for i in 0 to ROCACHE_WORDS - 1 loop ICACHE(GET_SET(address_stall))(currentLine).words(i) <= RAM_DATA(((i+1)*instr_size - 1) downto i*INSTR_SIZE); end loop; -- Write the DATA_OUT if((to_integer(unsigned(address_stall(ROCACHE_INDEXOFFSET - 1 downto 0)))) = 0) then INT_OUT_DATA <= RAM_DATA(Instr_size - 1 downto 0); else INT_OUT_DATA <= RAM_DATA(2*Instr_size - 1 downto Instr_size); end if; STATE_NEXT <= STATE_COMPARE_TAGS; INT_STALL <= '0'; INT_ISSUE_RAM_READ <= '0'; end if; -- Fetch instruction and print it if HIT when STATE_COMPARE_TAGS => if(ENABLE = '1') then INT_STALL <= '1'; -- Look in the ICACHE for i in 0 to ROCACHE_NUMLINES - 1 loop -- Is it a HIT ? HIT := COMPARE_TAGS( ADDRESS(INSTR_SIZE - 1 downto ROCACHE_TAGOFFSET), ICACHE_REG(GET_SET(ADDRESS))(i).tag(ROCACHE_TAGSIZE - 1 downto 0) ); -- HIT! if (HIT = '1') then -- Is the entry valid? if(ICACHE_REG(GET_SET(ADDRESS))(i).valid = '1') then lineIndex:= i; HIT := '0'; -- Reset HIT if ICACHE_REG(GET_SET(ADDRESS))(i).counter /= 256 then ICACHE(GET_SET(ADDRESS))(i).counter <= ICACHE_REG(GET_SET(ADDRESS))(i).counter + 1; end if; -- Print out the instruction INT_OUT_DATA <= ICACHE_REG( GET_SET(ADDRESS))(lineIndex).words( to_integer(unsigned(ADDRESS(ROCACHE_INDEXOFFSET - 1 downto 0)) ) ); INT_STALL <= '0'; -- Next state: the same STATE_NEXT <= STATE_COMPARE_TAGS; count_miss := 0; exit; -- The entry is not valid. Count as miss else count_miss := count_miss + 1; end if; -- Miss :( else count_miss := count_miss + 1; end if; end loop; -- Miss? if (count_miss = ROCACHE_NUMLINES) then address_stall := ADDRESS; INT_ISSUE_RAM_READ <= '1'; STATE_NEXT <= STATE_MISS; end if; -- Reset the counter count_miss := 0; else STATE_NEXT <= STATE_COMPARE_TAGS; end if; when OTHERS => null; end case; end process; STALL <= INT_STALL; RAM_ISSUE <= INT_ISSUE_RAM_READ; RAM_ADDRESS <= ADDRESS(INSTR_SIZE - 1 downto 1) & '0' when INT_ISSUE_RAM_READ = '1' else (others => '0'); OUT_DATA <= INT_OUT_DATA when INT_STALL = '0' else (others =>'0'); end Behavioral; |
library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; use std.textio.all; use work.types_pkg.all; use work.string_methods_pkg.all; use work.methods_pkg.all; use work.adaptations_pkg.all; package bfm_common_pkg is -- General declarations related to BFMs type t_normalization_mode is (ALLOW_WIDER, ALLOW_NARROWER, ALLOW_WIDER_NARROWER, ALLOW_EXACT_ONLY); alias t_normalisation_mode is t_normalization_mode; -- Functions/procedures impure function normalise( constant value : in std_logic_vector; constant target : in std_logic_vector; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "slv" ) return std_logic_vector; impure function normalise( constant value : in unsigned; constant target : in unsigned; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "unsigned" ) return unsigned; impure function normalise( constant value : in signed; constant target : in signed; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "signed" ) return signed; impure function normalise( constant value : in t_slv_array; constant target : in t_slv_array; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "t_slv_array" ) return t_slv_array; impure function normalise( constant value : in t_unsigned_array; constant target : in t_unsigned_array; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "t_unsigned_array" ) return t_unsigned_array; impure function normalise( constant value : in t_signed_array; constant target : in t_signed_array; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "t_signed_array" ) return t_signed_array; -- Functions/procedures impure function normalize_and_check( constant value : in std_logic_vector; constant target : in std_logic_vector; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "slv" ) return std_logic_vector; impure function normalize_and_check( constant value : in unsigned; constant target : in unsigned; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "unsigned" ) return unsigned; impure function normalize_and_check( constant value : in signed; constant target : in signed; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "signed" ) return signed; impure function normalize_and_check( constant value : in t_slv_array; constant target : in t_slv_array; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "t_slv_array" ) return t_slv_array; impure function normalize_and_check( constant value : in t_unsigned_array; constant target : in t_unsigned_array; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "t_unsigned_array" ) return t_unsigned_array; impure function normalize_and_check( constant value : in t_signed_array; constant target : in t_signed_array; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "t_signed_array" ) return t_signed_array; procedure wait_until_given_time_after_rising_edge ( signal clk : in std_logic; constant wait_time : in time ); procedure wait_until_given_time_before_rising_edge ( signal clk : in std_logic; constant time_to_edge : in time; constant clk_period : in time ); procedure wait_num_rising_edge ( signal clk : in std_logic; constant num_rising_edge : in natural ); procedure wait_num_rising_edge_plus_margin ( signal clk : in std_logic; constant num_rising_edge : in natural; constant margin : in time ); end package bfm_common_pkg; package body bfm_common_pkg is constant C_SCOPE : string := "bfm_common"; -- Normalize 'value' to the width given by 'target' and perform sanity check. impure function normalize_and_check( constant value : in std_logic_vector; constant target : in std_logic_vector; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "slv" ) return std_logic_vector is constant name : string := "normalize_and_check(" & val_type & ": " & value_name & "=" & to_string(value, HEX, AS_IS) & ", " & target_name & "=" & to_string(target, HEX, AS_IS) & ")"; alias a_value : std_logic_vector(value'length - 1 downto 0) is value; alias a_target : std_logic_vector(target'length - 1 downto 0) is target; variable v_normalized_value : std_logic_vector(target'length - 1 downto 0); begin -- Verify that value and target are not zero-length vectors if value'length = 0 then tb_error(name & " => Value length is zero! " & add_msg_delimiter(msg), C_SCOPE); return v_normalized_value; elsif target'length = 0 then tb_error(name & " => Target length is zero! " & add_msg_delimiter(msg), C_SCOPE); return v_normalized_value; end if; -- If value'length > target'length, remove leading zeros from value if (a_value'length > a_target'length) then v_normalized_value := a_value(a_target'length - 1 downto 0); -- Sanity checks if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & add_msg_delimiter(msg), C_SCOPE); end if; if not matching_widths(a_value, a_target) then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & add_msg_delimiter(msg), C_SCOPE); end if; -- If value'length = target'length elsif (a_value'length = a_target'length) then v_normalized_value := a_value; -- If value'length < target'length, add padding (leading zeros) to value elsif (a_value'length < a_target'length) then v_normalized_value := (others => '0'); v_normalized_value(a_value'length - 1 downto 0) := a_value; -- Sanity check if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & add_msg_delimiter(msg), C_SCOPE); end if; end if; return v_normalized_value; end; impure function normalize_and_check( constant value : in unsigned; constant target : in unsigned; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "unsigned" ) return unsigned is begin return unsigned(normalize_and_check(std_logic_vector(value), std_logic_vector(target), mode, value_name, target_name, msg, val_type)); end; impure function normalize_and_check( constant value : in signed; constant target : in signed; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "signed" ) return signed is constant name : string := "normalize_and_check(" & val_type & ": " & value_name & "=" & to_string(std_logic_vector(value)) & ", " & target_name & "=" & to_string(std_logic_vector(target)) & ")"; alias a_value : signed(value'length - 1 downto 0) is value; alias a_target : signed(target'length - 1 downto 0) is target; variable v_normalized_value : signed(target'length - 1 downto 0); begin -- Verify that value and target are not zero-length vectors if value'length = 0 then tb_error(name & " => Value length is zero! " & add_msg_delimiter(msg), C_SCOPE); return v_normalized_value; elsif target'length = 0 then tb_error(name & " => Target length is zero! " & add_msg_delimiter(msg), C_SCOPE); return v_normalized_value; end if; -- If value'length > target'length, remove leading zeros/ones from value if a_value'length > a_target'length then v_normalized_value := a_value(a_target'length - 1 downto 0); -- Sanity checks if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & add_msg_delimiter(msg), C_SCOPE); end if; if a_value(a_value'high) = '0' then -- positive value if not matching_widths(a_value, a_target) then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & add_msg_delimiter(msg), C_SCOPE); end if; elsif a_value(a_value'high) = '1' then -- negative value for i in a_value'high downto a_target'length loop if a_value(i) = '0' then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-sign bits in the extended MSB. " & add_msg_delimiter(msg), C_SCOPE); end if; end loop; end if; -- If value'length = target'length elsif a_value'length = a_target'length then v_normalized_value := a_value; -- If value'length < target'length, add padding (leading zeros/ones) to value elsif a_value'length < a_target'length then if a_value(a_value'high) = '0' then -- positive value v_normalized_value := (others => '0'); elsif a_value(a_value'high) = '1' then -- negative value v_normalized_value := (others => '1'); end if; v_normalized_value(a_value'length - 1 downto 0) := a_value; -- Sanity check if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & add_msg_delimiter(msg), C_SCOPE); end if; end if; return v_normalized_value; end; impure function normalize_and_check( constant value : in t_slv_array; constant target : in t_slv_array; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "t_slv_array" ) return t_slv_array is -- Helper variables variable v_slv_array_ascending : t_slv_array(0 to target'length-1)(0 to target(0)'length-1); variable v_slv_array_descending : t_slv_array(target'length-1 downto 0)(target(0)'length-1 downto 0); begin -- check directions if (value'ascending and not(target'ascending)) then tb_error("value instanciated as 'to', target instanciated as 'dowto'." & add_msg_delimiter(msg), C_SCOPE); elsif (not(value'ascending) and target'ascending) then tb_error("value instanciated as 'downto', target instanciated as 'to'." & add_msg_delimiter(msg), C_SCOPE); end if; if (value(0)'ascending and not(target(0)'ascending)) then tb_error("value(n) instanciated as 'to', target(n) instanciated as 'dowto'." & add_msg_delimiter(msg), C_SCOPE); elsif (not(value(0)'ascending) and target(0)'ascending) then tb_error("value(n) instanciated as 'downto', target(n) instanciated as 'to'." & add_msg_delimiter(msg), C_SCOPE); end if; -- return ascending t_slv_array if (value'ascending) then if value'length > target'length then for idx in target'range loop v_slv_array_ascending(idx) := normalize_and_check(value(idx), target(idx), mode, value_name, target_name, msg, val_type); end loop; else for idx in value'range loop v_slv_array_ascending(idx) := normalize_and_check(value(idx), target(idx), mode, value_name, target_name, msg, val_type); end loop; end if; return v_slv_array_ascending; else -- return descending t_slv_array if value'length > target'length then for idx in target'range loop v_slv_array_descending(idx) := normalize_and_check(value(idx), target(idx), mode, value_name, target_name, msg, val_type); end loop; else for idx in value'range loop v_slv_array_descending(idx) := normalize_and_check(value(idx), target(idx), mode, value_name, target_name, msg, val_type); end loop; end if; return v_slv_array_descending; end if; end; impure function normalize_and_check( constant value : in t_signed_array; constant target : in t_signed_array; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "t_signed_array" ) return t_signed_array is -- Helper variables variable v_signed_array : t_signed_array(target'length-1 downto 0)(target(0)'length-1 downto 0); begin -- check directions if (value'ascending and not(target'ascending)) then tb_error("value instanciated as 'to', target instanciated as 'dowto'." & add_msg_delimiter(msg), C_SCOPE); elsif (not(value'ascending) and target'ascending) then tb_error("value instanciated as 'downto', target instanciated as 'to'." & add_msg_delimiter(msg), C_SCOPE); end if; if value'length > target'length then for idx in target'range loop v_signed_array(idx) := normalize_and_check(value(idx), target(idx), mode, value_name, target_name, msg, val_type); end loop; else for idx in value'range loop v_signed_array(idx) := normalize_and_check(value(idx), target(idx), mode, value_name, target_name, msg, val_type); end loop; end if; return v_signed_array; end; impure function normalize_and_check( constant value : in t_unsigned_array; constant target : in t_unsigned_array; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "t_unsigned_array" ) return t_unsigned_array is variable v_unsigned_array : t_unsigned_array(target'length-1 downto 0)(target(0)'length-1 downto 0); begin -- check directions if (value'ascending and not(target'ascending)) then tb_error("value instanciated as 'to', target instanciated as 'dowto'." & add_msg_delimiter(msg), C_SCOPE); elsif (not(value'ascending) and target'ascending) then tb_error("value instanciated as 'downto', target instanciated as 'to'." & add_msg_delimiter(msg), C_SCOPE); end if; if value'length > target'length then for idx in target'range loop v_unsigned_array(idx) := normalize_and_check(value(idx), target(idx), mode, value_name, target_name, msg, val_type); end loop; else for idx in value'range loop v_unsigned_array(idx) := normalize_and_check(value(idx), target(idx), mode, value_name, target_name, msg, val_type); end loop; end if; return v_unsigned_array; end; -- Normalise 'value' to the width given by 'target'. impure function normalise( constant value : in std_logic_vector; constant target : in std_logic_vector; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "slv" ) return std_logic_vector is constant name : string := "normalise(" & val_type & ": " & value_name & "=" & to_string(value, HEX, AS_IS) & ", " & target_name & "=" & to_string(target, HEX, AS_IS) & ")"; alias a_value : std_logic_vector(value'length - 1 downto 0) is value; alias a_target : std_logic_vector(target'length - 1 downto 0) is target; variable v_normalised_value : std_logic_vector(target'length - 1 downto 0); begin deprecate(get_procedure_name_from_instance_name(value'instance_name), "Use normalize_and_check()."); -- Verify that value and target are not zero-length vectors if value'length = 0 then tb_error(name & " => Value length is zero! " & add_msg_delimiter(msg), C_SCOPE); return v_normalised_value; elsif target'length = 0 then tb_error(name & " => Target length is zero! " & add_msg_delimiter(msg), C_SCOPE); return v_normalised_value; end if; -- If value'length > target'length, remove leading zeros from value if (a_value'length > a_target'length) then v_normalised_value := a_value(a_target'length - 1 downto 0); -- Sanity checks if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & add_msg_delimiter(msg), C_SCOPE); end if; if not matching_widths(a_value, a_target) then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & add_msg_delimiter(msg), C_SCOPE); end if; -- If value'length = target'length elsif (a_value'length = a_target'length) then v_normalised_value := a_value; -- If value'length < target'length, add padding (leading zeros) to value elsif (a_value'length < a_target'length) then v_normalised_value := (others => '0'); v_normalised_value(a_value'length - 1 downto 0) := a_value; -- Sanity check if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & add_msg_delimiter(msg), C_SCOPE); end if; end if; return v_normalised_value; end; impure function normalise( constant value : in unsigned; constant target : in unsigned; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "unsigned" ) return unsigned is begin return unsigned(normalise(std_logic_vector(value), std_logic_vector(target), mode, value_name, target_name, msg, val_type)); end; impure function normalise( constant value : in signed; constant target : in signed; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "signed" ) return signed is constant name : string := "normalise(" & val_type & ": " & value_name & "=" & to_string(std_logic_vector(value)) & ", " & target_name & "=" & to_string(std_logic_vector(target)) & ")"; alias a_value : signed(value'length - 1 downto 0) is value; alias a_target : signed(target'length - 1 downto 0) is target; variable v_normalised_value : signed(target'length - 1 downto 0); begin deprecate(get_procedure_name_from_instance_name(value'instance_name), "Use normalize_and_check()."); -- Verify that value and target are not zero-length vectors if value'length = 0 then tb_error(name & " => Value length is zero! " & add_msg_delimiter(msg), C_SCOPE); return v_normalised_value; elsif target'length = 0 then tb_error(name & " => Target length is zero! " & add_msg_delimiter(msg), C_SCOPE); return v_normalised_value; end if; -- If value'length > target'length, remove leading zeros/ones from value if a_value'length > a_target'length then v_normalised_value := a_value(a_target'length - 1 downto 0); -- Sanity checks if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & add_msg_delimiter(msg), C_SCOPE); end if; if a_value(a_value'high) = '0' then -- positive value if not matching_widths(a_value, a_target) then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & add_msg_delimiter(msg), C_SCOPE); end if; elsif a_value(a_value'high) = '1' then -- negative value for i in a_value'high downto a_target'length loop if a_value(i) = '0' then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-sign bits in the extended MSB. " & add_msg_delimiter(msg), C_SCOPE); end if; end loop; end if; -- If value'length = target'length elsif a_value'length = a_target'length then v_normalised_value := a_value; -- If value'length < target'length, add padding (leading zeros/ones) to value elsif a_value'length < a_target'length then if a_value(a_value'high) = '0' then -- positive value v_normalised_value := (others => '0'); elsif a_value(a_value'high) = '1' then -- negative value v_normalised_value := (others => '1'); end if; v_normalised_value(a_value'length - 1 downto 0) := a_value; -- Sanity check if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & add_msg_delimiter(msg), C_SCOPE); end if; end if; return v_normalised_value; end; impure function normalise( constant value : in t_slv_array; constant target : in t_slv_array; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "t_slv_array" ) return t_slv_array is -- Helper variables variable v_slv_array : t_slv_array(target'length-1 downto 0)(target(0)'length-1 downto 0); begin if value'length > target'length then for idx in target'range loop v_slv_array(idx) := normalise(value(idx), target(idx), mode, value_name, target_name, msg, val_type); end loop; else for idx in value'range loop v_slv_array(idx) := normalise(value(idx), target(idx), mode, value_name, target_name, msg, val_type); end loop; end if; return v_slv_array; end; impure function normalise( constant value : in t_signed_array; constant target : in t_signed_array; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "t_signed_array" ) return t_signed_array is -- Helper variables variable v_signed_array : t_signed_array(target'length-1 downto 0)(target(0)'length-1 downto 0); begin if value'length > target'length then for idx in target'range loop v_signed_array(idx) := normalise(value(idx), target(idx), mode, value_name, target_name, msg, val_type); end loop; else for idx in value'range loop v_signed_array(idx) := normalise(value(idx), target(idx), mode, value_name, target_name, msg, val_type); end loop; end if; return v_signed_array; end; impure function normalise( constant value : in t_unsigned_array; constant target : in t_unsigned_array; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "t_unsigned_array" ) return t_unsigned_array is -- Helper variable variable v_unsigned_array : t_unsigned_array(target'length-1 downto 0)(target(0)'length-1 downto 0); begin if value'length > target'length then for idx in target'range loop v_unsigned_array(idx) := normalise(value(idx), target(idx), mode, value_name, target_name, msg, val_type); end loop; else for idx in value'range loop v_unsigned_array(idx) := normalise(value(idx), target(idx), mode, value_name, target_name, msg, val_type); end loop; end if; return v_unsigned_array; end; -- Wait until wait_time after rising_edge(clk) procedure wait_until_given_time_after_rising_edge ( signal clk : in std_logic; constant wait_time : in time ) is variable v_remaining_wait_time : time; begin -- If the time since the previous rising_edge is less than wait_time, -- we don't have to wait until the next rising_edge, -- only wait_time minus the time already passed since rising_edge if (clk'last_event <= wait_time and -- less than wait_time has passed since last event clk'last_value = '0' and clk = '1' -- last event was a rising_edge ) then v_remaining_wait_time := wait_time - clk'last_event; -- Wait until wait_time after rising_edge else wait until rising_edge(clk); v_remaining_wait_time := wait_time; -- Wait until wait_time after rising_edge end if; wait for v_remaining_wait_time; end; -- Wait until time_to_edge before rising_edge(clk) procedure wait_until_given_time_before_rising_edge ( signal clk : in std_logic; constant time_to_edge : in time; constant clk_period : in time ) is variable v_remaining_wait_time : time; begin check_value(clk_period > 2*time_to_edge, TB_ERROR, "time_to_edge must be less than half clk_period", C_SCOPE, ID_NEVER); -- If the time to the next rising edge is greater than time_to_edge and clk is low, -- we don't have to wait until the next falling_edge, -- only wait_time minus the time already passed since falling_edge if (clk'last_event <= clk_period/2 - time_to_edge and clk'last_value = '1' and clk = '0') then v_remaining_wait_time := (clk_period/2 - time_to_edge) - clk'last_event; -- Wait until time_to_edge before rising_edge else wait until falling_edge(clk); v_remaining_wait_time := (clk_period/2 - time_to_edge); -- Wait until time_to_edge before rising_edge end if; wait for v_remaining_wait_time; end; procedure wait_num_rising_edge ( signal clk : in std_logic; constant num_rising_edge : in natural ) is begin wait_num_rising_edge_plus_margin(clk, num_rising_edge, 0 ns); end procedure; procedure wait_num_rising_edge_plus_margin ( signal clk : in std_logic; constant num_rising_edge : in natural; constant margin : in time ) is begin -- Wait for number of rising edges if num_rising_edge /= 0 then for i in 1 to num_rising_edge loop wait until rising_edge(clk); end loop; end if; -- Wait for remaining margin, if any wait for margin; end procedure; end package body bfm_common_pkg; |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY XilinxCoreLib; ENTITY Instr_Mem IS PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END Instr_Mem; ARCHITECTURE Instr_Mem_a OF Instr_Mem IS COMPONENT wrapped_Instr_Mem PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; FOR ALL : wrapped_Instr_Mem USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral) GENERIC MAP ( c_addra_width => 5, c_addrb_width => 5, c_algorithm => 1, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 0, c_default_data => "0", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_enable_32bit_address => 0, c_family => "spartan3", c_has_axi_id => 0, c_has_ena => 0, c_has_enb => 0, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file => "BlankString", c_init_file_name => "Instr_Mem.mif", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 1, c_mem_type => 0, c_mux_pipeline_stages => 0, c_prim_type => 1, c_read_depth_a => 32, c_read_depth_b => 32, c_read_width_a => 16, c_read_width_b => 16, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_bram_block => 0, c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 1, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 32, c_write_depth_b => 32, c_write_mode_a => "READ_FIRST", c_write_mode_b => "WRITE_FIRST", c_write_width_a => 16, c_write_width_b => 16, c_xdevicefamily => "spartan3e" ); BEGIN U0 : wrapped_Instr_Mem PORT MAP ( clka => clka, wea => wea, addra => addra, dina => dina, douta => douta ); END Instr_Mem_a; |
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity KEYCODE_TO_ASCII is port( RST : in STD_LOGIC; CLK : in STD_LOGIC; KEYCODE : in STD_LOGIC_VECTOR(7 downto 0); VALID_SIGNAL : in STD_LOGIC; -- Output COMPLETE: out STD_LOGIC; -- Hit Key sucessfully ASCII : out STD_LOGIC_VECTOR(7 downto 0)--; --KEYBOARD_OUT : out STD_LOGIC_VECTOR(7 downto 0); --WRITE_KEYBOARD: out STD_LOGIC; ); end KEYCODE_TO_ASCII; architecture dataflow of KEYCODE_TO_ASCII is type StateType is (init, idle, READ_BREAKCODE, READ_EXTENDED, READ_KEYCODE,SEND_COMPLETE);--,SEND_CAPS); signal STATE : StateType := init; signal ASCII_LOWER : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0'); signal ASCII_UPPER : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0'); shared variable Shift_Key : boolean := false; shared variable Caps_Lock : boolean := false; shared variable Extended : boolean := false; begin with KEYCODE select ASCII_LOWER <= -- Alphabet x"61" when x"1C", -- a x"62" when x"32", -- b x"63" when x"21", -- c x"64" when x"23", -- d x"65" when x"24", -- e x"66" when x"2B", -- f x"67" when x"34", -- g -- cganged to 67 x"68" when x"33", -- h x"69" when x"43", -- i x"6A" when x"3B", -- j x"6B" when x"42", -- k x"6C" when x"4B", -- l -- changed from 66 to 6c x"6D" when x"3A", -- m x"6E" when x"31", -- n x"6F" when x"44", -- o x"70" when x"4D", -- p x"71" when x"15", -- q x"72" when x"2D", -- r -- changed from 74 x"73" when x"1B", -- s x"74" when x"2C", -- t -- changed from 72 x"75" when x"3C", -- u -- changed from 79 x"76" when x"2A", -- v x"77" when x"1D", -- w x"78" when x"22", -- x x"79" when x"35", -- y -- changed from 75 x"7A" when x"1A", -- z --Top Row x"60" when x"0E", -- ` x"31" when x"16", -- 1 x"32" when x"1E", -- 2 x"33" when x"26", -- 3 x"34" when x"25", -- 4 x"35" when x"2E", -- 5 x"36" when x"36", -- 6 x"37" when x"3D", -- 7 x"38" when x"3E", -- 8 x"39" when x"46", -- 9 x"30" when x"45", -- 0 x"2D" when x"4E", -- - x"3D" when x"55", -- = --Enter Corner x"5B" when x"54", -- [ x"5D" when x"5B", -- ] x"5C" when x"5D", -- \ x"3B" when x"4C", -- ; x"27" when x"52", -- ' x"2C" when x"41", -- , x"2E" when x"49", -- . x"2F" when x"4A", -- / --Function Keys -- Based on the IBM PC Codes x"1B" when x"76", -- Esc (Escape) x"3B" when x"05", -- F1 x"3C" when x"06", -- F2 x"3D" when x"04", -- F3 x"3E" when x"0C", -- F4 x"3F" when x"03", -- F5 x"40" when x"0B", -- F6 x"41" when x"83", -- F7 x"42" when x"0A", -- F8 x"43" when x"01", -- F9 x"44" when x"09", -- F10 x"85" when x"78", -- F11 x"86" when x"07", -- F12 x"09" when x"0D", -- Tab (Horizontal Tab) x"0D" when x"5A", -- Enter (Carriage Return) --special characters -- taking up unneaded ascii codes for simplicity x"05" when x"58", -- Caps Lock x"06" when x"14", -- Ctrl x"07" when x"11", -- Alt x"08" when x"66", -- Back Space x"20" when x"29", -- Space --Direction Keys -- taking up unneaded ascii codes for simplicity x"01" when x"75", -- Up x"02" when x"72", -- Down x"03" when x"6B", -- Left x"04" when x"74", -- Right --Unknown input x"00" when OTHERS; -- Null with KEYCODE select ASCII_UPPER <= -- Alphabet x"41" when x"1C", -- A x"42" when x"32", -- B x"43" when x"21", -- C x"44" when x"23", -- D x"45" when x"24", -- E -- changed from 48 x"46" when x"2B", -- F x"47" when x"34", -- G x"48" when x"33", -- H -- changed from 45 x"49" when x"43", -- I x"4A" when x"3B", -- J x"4B" when x"42", -- K x"4C" when x"4B", -- L x"4D" when x"3A", -- M x"4E" when x"31", -- N x"4F" when x"44", -- O x"50" when x"4D", -- P x"51" when x"15", -- Q x"52" when x"2D", -- R x"53" when x"1B", -- S -- changed from 54 x"54" when x"2C", -- T -- changed from 55 x"55" when x"3C", -- U x"56" when x"2A", -- V x"57" when x"1D", -- W x"58" when x"22", -- X x"59" when x"35", -- Y x"5A" when x"1A", -- Z -- Special Upper case Characters (top left to bottom right) -- Top Row x"7E" when x"0E", -- ~ x"21" when x"16", -- ! x"40" when x"1E", -- @ x"23" when x"26", -- # x"24" when x"25", -- $ x"25" when x"2E", -- % x"5E" when x"36", -- ^ x"26" when x"3D", -- & x"2A" when x"3E", -- * x"28" when x"46", -- ( x"29" when x"45", -- ) x"5F" when x"4E", -- _ x"2B" when x"55", -- + -- Enter Corner x"7B" when x"54", -- { x"7D" when x"5B", -- } x"7C" when x"5D", -- | x"3A" when x"4C", -- : x"22" when x"52", -- " x"3C" when x"41", -- < x"3E" when x"49", -- > x"3F" when x"4A", -- ? -- Unknown Key x"00" when OTHERS; -- Null PROCESS (KEYCODE,CLK, RST) BEGIN if (RST = '1') then STATE <= init; elsif (CLK'event and CLK= '0' ) then case STATE is when init => ascii <= (OTHERS => '0'); COMPLETE <= '0'; state <= idle; when idle => COMPLETE <= '0'; if VALID_SIGNAL= '1' then Extended := false; if keycode=x"E0" then state <= READ_EXTENDED; -- A Key was pressed elsif keycode=x"F0" then state <= READ_KEYCODE; else -- No break code yet state <= idle; end if; -- Shift Key was press (on) if (keycode=x"12" or keycode=x"54") then Shift_Key := true; end if; end if; when READ_EXTENDED => if VALID_SIGNAL= '1' then Extended := true; if keycode=x"F0" then state <= READ_KEYCODE; else state <= idle; end if; end if; when READ_BREAKCODE => if VALID_SIGNAL= '1' then if keycode=x"F0" then state <= READ_KEYCODE; else state <= idle; end if; end if; when READ_KEYCODE => if VALID_SIGNAL= '1' then -- Shift Key was released (off) if (keycode=x"12" or keycode=x"59") then -- 59 changed from 54 Shift_Key := false; elsif (keycode=x"58") then -- changed from 46 (9) if (Caps_Lock = false) then Caps_Lock := true; else Caps_Lock := false; end if; --state <= SEND_CAPS; else if (Shift_Key = true or Caps_Lock = true) then ascii <= ASCII_UPPER; else ascii <= ASCII_LOWER; end if; end if; state <= SEND_COMPLETE; end if; when SEND_COMPLETE => COMPLETE <= '1'; state <= idle; --when SEND_CAPS => when OTHERS => state <= idle; end case; end if; end process; end architecture dataflow; |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY TopLevel_tb IS END TopLevel_tb; ARCHITECTURE behavior OF TopLevel_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ProjLab01 PORT( CLK : IN std_logic; RST : IN std_logic; --instruction : IN std_logic_vector(15 downto 0); ALU_OUT : OUT std_logic_vector(15 downto 0); DST_ADR : OUT std_logic_vector(15 downto 0); STORE_DATA : OUT std_logic_vector(15 downto 0); CCR : OUT std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs signal CLK : std_logic := '0'; signal RST : std_logic := '0'; --signal instruction : std_logic_vector(15 downto 0) := (others => '0'); --Outputs signal ALU_OUT : std_logic_vector(15 downto 0); signal DST_ADR : std_logic_vector(15 downto 0); signal STORE_DATA : std_logic_vector(15 downto 0); signal CCR : std_logic_vector(3 downto 0); -- Clock period definitions constant CLK_period : time := 1 ms; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ProjLab01 PORT MAP ( CLK => CLK, RST => RST, ALU_OUT => ALU_OUT, DST_ADR => DST_ADR, STORE_DATA => STORE_DATA, CCR => CCR ); -- Clock process definitions CLK_process :process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; RST <= '1'; wait for CLK_period*2; wait for CLK_period/2; RST <= '0'; wait for CLK_period*10; wait for CLK_period; -- insert stimulus here wait; end process; END; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.all; entity ALU_Toplevel is Port ( RA : in STD_LOGIC_VECTOR (15 downto 0); RB : in STD_LOGIC_VECTOR (15 downto 0); OP : in STD_LOGIC_VECTOR (3 downto 0); ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0); SREG : out STD_LOGIC_VECTOR (3 downto 0); LDST_DAT : out STD_LOGIC_VECTOR (15 downto 0); LDST_ADR : out STD_LOGIC_VECTOR (15 downto 0)); end ALU_Toplevel; architecture Structural of ALU_Toplevel is signal ARITH : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); signal SREG_AR : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0'); signal LOGIC : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); signal SREG_LG : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0'); signal SHIFT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); signal SREG_SH : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0'); signal LD_MEM : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); begin arith_unit: entity work.arith_unit port map( RA => RA, RB => RB, OP => OP(2 downto 0), AR_OUT => ARITH); logical_unit: entity work.logical_unit port map( RA => RA, RB => RB, OP => OP(2 downto 0), LOG_OUT => LOGIC, SREG_OUT => SREG_LG); shift_unit: entity work.shift_unit port map( RA => RA, SHIFT => RB(7 downto 0), OP => OP(3), SHIFT_OUT => SHIFT, SREG_OUT => SREG_SH); with OP select ALU_OUT <= ARITH when "0000", -- ADD (ARITHMETIC) ARITH when "0001", -- SUB (ARITHMETIC) LOGIC when "0010", -- AND (LOGICAL) LOGIC when "0011", -- OR (LOGICAL) LOGIC when "0100", -- MOV (LOGICAL) ARITH when "0101", -- ADDI (ARITHMETIC) LOGIC when "0110",--, -- ANDI (LOGICAL) SHIFT when "0111", -- SL (SHIFT) SHIFT when "1000",--, -- SR (SHIFT) --"" when "1001", -- LW (WORD) --"" when "1010"; -- SW (WORD) RA when OTHERS; end Structural; |
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.ALL; ENTITY DATAMEM_tb IS END ENTITY; ARCHITECTURE DATAMEM_tb_ARCH OF DATAMEM_tb IS SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL CLK : STD_LOGIC := '1'; SIGNAL RESET : STD_LOGIC; BEGIN CLK_GEN: PROCESS BEGIN CLK <= NOT CLK; WAIT FOR 100 NS; CLK <= NOT CLK; WAIT FOR 100 NS; END PROCESS; RST_GEN: PROCESS BEGIN RESET <= '1'; WAIT FOR 1000 NS; RESET <= '0'; WAIT; END PROCESS; PROCESS BEGIN WAIT UNTIL STATUS(8)='1'; IF( STATUS(7 downto 0)/="0") THEN ASSERT false REPORT "Test Completed Successfully" SEVERITY NOTE; REPORT "Simulation Failed" SEVERITY FAILURE; ELSE ASSERT false REPORT "TEST PASS" SEVERITY NOTE; REPORT "Test Completed Successfully" SEVERITY FAILURE; END IF; END PROCESS; DATAMEM_synth_inst:ENTITY work.DATAMEM_synth PORT MAP( CLK_IN => CLK, RESET_IN => RESET, STATUS => STATUS ); END ARCHITECTURE; |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fir_compiler_v7_1; USE fir_compiler_v7_1.fir_compiler_v7_1; ENTITY fir_lp_15kHz IS PORT ( aclk : IN STD_LOGIC; s_axis_data_tvalid : IN STD_LOGIC; s_axis_data_tready : OUT STD_LOGIC; s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) ); END fir_lp_15kHz; ARCHITECTURE fir_lp_15kHz_arch OF fir_lp_15kHz IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF fir_lp_15kHz_arch: ARCHITECTURE IS "yes"; COMPONENT fir_compiler_v7_1 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_COMPONENT_NAME : STRING; C_COEF_FILE : STRING; C_COEF_FILE_LINES : INTEGER; C_FILTER_TYPE : INTEGER; C_INTERP_RATE : INTEGER; C_DECIM_RATE : INTEGER; C_ZERO_PACKING_FACTOR : INTEGER; C_SYMMETRY : INTEGER; C_NUM_FILTS : INTEGER; C_NUM_TAPS : INTEGER; C_NUM_CHANNELS : INTEGER; C_CHANNEL_PATTERN : STRING; C_ROUND_MODE : INTEGER; C_COEF_RELOAD : INTEGER; C_NUM_RELOAD_SLOTS : INTEGER; C_COL_MODE : INTEGER; C_COL_PIPE_LEN : INTEGER; C_COL_CONFIG : STRING; C_OPTIMIZATION : INTEGER; C_DATA_PATH_WIDTHS : STRING; C_DATA_IP_PATH_WIDTHS : STRING; C_DATA_PX_PATH_WIDTHS : STRING; C_DATA_WIDTH : INTEGER; C_COEF_PATH_WIDTHS : STRING; C_COEF_WIDTH : INTEGER; C_DATA_PATH_SRC : STRING; C_COEF_PATH_SRC : STRING; C_DATA_PATH_SIGN : STRING; C_COEF_PATH_SIGN : STRING; C_ACCUM_PATH_WIDTHS : STRING; C_OUTPUT_WIDTH : INTEGER; C_OUTPUT_PATH_WIDTHS : STRING; C_ACCUM_OP_PATH_WIDTHS : STRING; C_EXT_MULT_CNFG : STRING; C_DATA_PATH_PSAMP_SRC : STRING; C_OP_PATH_PSAMP_SRC : STRING; C_NUM_MADDS : INTEGER; C_OPT_MADDS : STRING; C_OVERSAMPLING_RATE : INTEGER; C_INPUT_RATE : INTEGER; C_OUTPUT_RATE : INTEGER; C_DATA_MEMTYPE : INTEGER; C_COEF_MEMTYPE : INTEGER; C_IPBUFF_MEMTYPE : INTEGER; C_OPBUFF_MEMTYPE : INTEGER; C_DATAPATH_MEMTYPE : INTEGER; C_MEM_ARRANGEMENT : INTEGER; C_DATA_MEM_PACKING : INTEGER; C_COEF_MEM_PACKING : INTEGER; C_FILTS_PACKED : INTEGER; C_LATENCY : INTEGER; C_HAS_ARESETn : INTEGER; C_HAS_ACLKEN : INTEGER; C_DATA_HAS_TLAST : INTEGER; C_S_DATA_HAS_FIFO : INTEGER; C_S_DATA_HAS_TUSER : INTEGER; C_S_DATA_TDATA_WIDTH : INTEGER; C_S_DATA_TUSER_WIDTH : INTEGER; C_M_DATA_HAS_TREADY : INTEGER; C_M_DATA_HAS_TUSER : INTEGER; C_M_DATA_TDATA_WIDTH : INTEGER; C_M_DATA_TUSER_WIDTH : INTEGER; C_HAS_CONFIG_CHANNEL : INTEGER; C_CONFIG_SYNC_MODE : INTEGER; C_CONFIG_PACKET_SIZE : INTEGER; C_CONFIG_TDATA_WIDTH : INTEGER; C_RELOAD_TDATA_WIDTH : INTEGER ); PORT ( aresetn : IN STD_LOGIC; aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_data_tvalid : IN STD_LOGIC; s_axis_data_tready : OUT STD_LOGIC; s_axis_data_tlast : IN STD_LOGIC; s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s_axis_config_tvalid : IN STD_LOGIC; s_axis_config_tready : OUT STD_LOGIC; s_axis_config_tlast : IN STD_LOGIC; s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_reload_tvalid : IN STD_LOGIC; s_axis_reload_tready : OUT STD_LOGIC; s_axis_reload_tlast : IN STD_LOGIC; s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tready : IN STD_LOGIC; m_axis_data_tlast : OUT STD_LOGIC; m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_data_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); event_s_data_tlast_missing : OUT STD_LOGIC; event_s_data_tlast_unexpected : OUT STD_LOGIC; event_s_data_chanid_incorrect : OUT STD_LOGIC; event_s_config_tlast_missing : OUT STD_LOGIC; event_s_config_tlast_unexpected : OUT STD_LOGIC; event_s_reload_tlast_missing : OUT STD_LOGIC; event_s_reload_tlast_unexpected : OUT STD_LOGIC ); END COMPONENT fir_compiler_v7_1; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF fir_lp_15kHz_arch: ARCHITECTURE IS "fir_compiler_v7_1,Vivado 2014.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF fir_lp_15kHz_arch : ARCHITECTURE IS "fir_lp_15kHz,fir_compiler_v7_1,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF fir_lp_15kHz_arch: ARCHITECTURE IS "fir_lp_15kHz,fir_compiler_v7_1,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fir_compiler,x_ipVersion=7.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_COMPONENT_NAME=fir_lp_15kHz,C_COEF_FILE=fir_lp_15kHz.mif,C_COEF_FILE_LINES=1024,C_FILTER_TYPE=1,C_INTERP_RATE=1,C_DECIM_RATE=4,C_ZERO_PACKING_FACTOR=1,C_SYMMETRY=1,C_NUM_FILTS=1,C_NUM_TAPS=2048,C_NUM_CHANNELS=1,C_CHANNEL_PATTERN=fixed,C_ROUND_MODE=0,C_COEF_RELOAD=0,C_NUM_RELOAD_SLOTS=1,C_COL_MODE=1,C_COL_PIPE_LEN=4,C_COL_CONFIG=16,C_OPTIMIZATION=2046,C_DATA_PATH_WIDTHS=16,C_DATA_IP_PATH_WIDTHS=16,C_DATA_PX_PATH_WIDTHS=16,C_DATA_WIDTH=16,C_COEF_PATH_WIDTHS=24,C_COEF_WIDTH=24,C_DATA_PATH_SRC=0,C_COEF_PATH_SRC=0,C_DATA_PATH_SIGN=0,C_COEF_PATH_SIGN=0,C_ACCUM_PATH_WIDTHS=44,C_OUTPUT_WIDTH=44,C_OUTPUT_PATH_WIDTHS=44,C_ACCUM_OP_PATH_WIDTHS=44,C_EXT_MULT_CNFG=none,C_DATA_PATH_PSAMP_SRC=0,C_OP_PATH_PSAMP_SRC=0,C_NUM_MADDS=16,C_OPT_MADDS=none,C_OVERSAMPLING_RATE=16,C_INPUT_RATE=16,C_OUTPUT_RATE=64,C_DATA_MEMTYPE=0,C_COEF_MEMTYPE=2,C_IPBUFF_MEMTYPE=0,C_OPBUFF_MEMTYPE=0,C_DATAPATH_MEMTYPE=2,C_MEM_ARRANGEMENT=1,C_DATA_MEM_PACKING=0,C_COEF_MEM_PACKING=0,C_FILTS_PACKED=0,C_LATENCY=40,C_HAS_ARESETn=0,C_HAS_ACLKEN=0,C_DATA_HAS_TLAST=0,C_S_DATA_HAS_FIFO=1,C_S_DATA_HAS_TUSER=0,C_S_DATA_TDATA_WIDTH=16,C_S_DATA_TUSER_WIDTH=1,C_M_DATA_HAS_TREADY=0,C_M_DATA_HAS_TUSER=0,C_M_DATA_TDATA_WIDTH=48,C_M_DATA_TUSER_WIDTH=1,C_HAS_CONFIG_CHANNEL=0,C_CONFIG_SYNC_MODE=0,C_CONFIG_PACKET_SIZE=0,C_CONFIG_TDATA_WIDTH=1,C_RELOAD_TDATA_WIDTH=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA"; BEGIN U0 : fir_compiler_v7_1 GENERIC MAP ( C_XDEVICEFAMILY => "zynq", C_ELABORATION_DIR => "./", C_COMPONENT_NAME => "fir_lp_15kHz", C_COEF_FILE => "fir_lp_15kHz.mif", C_COEF_FILE_LINES => 1024, C_FILTER_TYPE => 1, C_INTERP_RATE => 1, C_DECIM_RATE => 4, C_ZERO_PACKING_FACTOR => 1, C_SYMMETRY => 1, C_NUM_FILTS => 1, C_NUM_TAPS => 2048, C_NUM_CHANNELS => 1, C_CHANNEL_PATTERN => "fixed", C_ROUND_MODE => 0, C_COEF_RELOAD => 0, C_NUM_RELOAD_SLOTS => 1, C_COL_MODE => 1, C_COL_PIPE_LEN => 4, C_COL_CONFIG => "16", C_OPTIMIZATION => 2046, C_DATA_PATH_WIDTHS => "16", C_DATA_IP_PATH_WIDTHS => "16", C_DATA_PX_PATH_WIDTHS => "16", C_DATA_WIDTH => 16, C_COEF_PATH_WIDTHS => "24", C_COEF_WIDTH => 24, C_DATA_PATH_SRC => "0", C_COEF_PATH_SRC => "0", C_DATA_PATH_SIGN => "0", C_COEF_PATH_SIGN => "0", C_ACCUM_PATH_WIDTHS => "44", C_OUTPUT_WIDTH => 44, C_OUTPUT_PATH_WIDTHS => "44", C_ACCUM_OP_PATH_WIDTHS => "44", C_EXT_MULT_CNFG => "none", C_DATA_PATH_PSAMP_SRC => "0", C_OP_PATH_PSAMP_SRC => "0", C_NUM_MADDS => 16, C_OPT_MADDS => "none", C_OVERSAMPLING_RATE => 16, C_INPUT_RATE => 16, C_OUTPUT_RATE => 64, C_DATA_MEMTYPE => 0, C_COEF_MEMTYPE => 2, C_IPBUFF_MEMTYPE => 0, C_OPBUFF_MEMTYPE => 0, C_DATAPATH_MEMTYPE => 2, C_MEM_ARRANGEMENT => 1, C_DATA_MEM_PACKING => 0, C_COEF_MEM_PACKING => 0, C_FILTS_PACKED => 0, C_LATENCY => 40, C_HAS_ARESETn => 0, C_HAS_ACLKEN => 0, C_DATA_HAS_TLAST => 0, C_S_DATA_HAS_FIFO => 1, C_S_DATA_HAS_TUSER => 0, C_S_DATA_TDATA_WIDTH => 16, C_S_DATA_TUSER_WIDTH => 1, C_M_DATA_HAS_TREADY => 0, C_M_DATA_HAS_TUSER => 0, C_M_DATA_TDATA_WIDTH => 48, C_M_DATA_TUSER_WIDTH => 1, C_HAS_CONFIG_CHANNEL => 0, C_CONFIG_SYNC_MODE => 0, C_CONFIG_PACKET_SIZE => 0, C_CONFIG_TDATA_WIDTH => 1, C_RELOAD_TDATA_WIDTH => 1 ) PORT MAP ( aresetn => '1', aclk => aclk, aclken => '1', s_axis_data_tvalid => s_axis_data_tvalid, s_axis_data_tready => s_axis_data_tready, s_axis_data_tlast => '0', s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_data_tdata => s_axis_data_tdata, s_axis_config_tvalid => '0', s_axis_config_tlast => '0', s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_reload_tvalid => '0', s_axis_reload_tlast => '0', s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tready => '1', m_axis_data_tdata => m_axis_data_tdata ); END fir_lp_15kHz_arch; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.types_pkg.all; use work.adaptations_pkg.all; use work.methods_pkg.all; use work.string_methods_pkg.all; package generic_queue_pkg is generic (type t_generic_element; scope : string := C_SCOPE; GC_QUEUE_COUNT_MAX : natural := 1000; GC_QUEUE_COUNT_THRESHOLD : natural := 950); -- When find_* doesn't find a match, they return C_NO_MATCH. constant C_NO_MATCH : integer := -1; -- A generic queue for verification type t_generic_queue is protected procedure add( constant instance : in integer; constant element : in t_generic_element); procedure add( constant element : in t_generic_element); procedure put( constant instance : in integer; constant element : in t_generic_element); procedure put( constant element : in t_generic_element); impure function get( constant instance : in integer) return t_generic_element; impure function get( constant dummy : in t_void) return t_generic_element; impure function is_empty( constant instance : in integer) return boolean; impure function is_empty( constant dummy : in t_void) return boolean; procedure set_scope( constant instance : in integer; constant scope : in string); procedure set_scope( constant scope : in string); procedure set_name( constant name : in string); impure function get_scope( constant instance : in integer) return string; impure function get_scope( constant dummy : in t_void) return string; impure function get_count( constant instance : in integer) return natural; impure function get_count( constant dummy : in t_void) return natural; procedure set_queue_count_threshold( constant instance : in integer; constant queue_count_alert_level : in natural); procedure set_queue_count_threshold( constant queue_count_alert_level : in natural); impure function get_queue_count_threshold( constant instance : in integer) return natural; impure function get_queue_count_threshold( constant dummy : in t_void) return natural; impure function get_queue_count_threshold_severity( constant dummy : in t_void) return t_alert_level; procedure set_queue_count_threshold_severity( constant alert_level : in t_alert_level); impure function get_queue_count_max( constant instance : in integer) return natural; impure function get_queue_count_max( constant dummy : in t_void) return natural; procedure set_queue_count_max( constant instance : in integer; constant queue_count_max : in natural); procedure set_queue_count_max( constant queue_count_max : in natural); procedure flush( constant instance : in integer); procedure flush( constant dummy : in t_void); procedure reset( constant instance : in integer); procedure reset( constant dummy : in t_void); procedure insert( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier : in positive; constant element : in t_generic_element); procedure insert( constant identifier_option : in t_identifier_option; constant identifier : in positive; constant element : in t_generic_element); procedure delete( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier_min : in positive; constant identifier_max : in positive); procedure delete( constant identifier_option : in t_identifier_option; constant identifier_min : in positive; constant identifier_max : in positive); procedure delete( constant instance : in integer; constant element : in t_generic_element ); procedure delete( constant element : in t_generic_element ); procedure delete( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier : in positive; constant range_option : in t_range_option ); procedure delete( constant identifier_option : in t_identifier_option; constant identifier : in positive; constant range_option : in t_range_option ); impure function peek( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier : in positive ) return t_generic_element; impure function peek( constant identifier_option : in t_identifier_option; constant identifier : in positive ) return t_generic_element; impure function peek( constant instance : in integer ) return t_generic_element; impure function peek( constant dummy : in t_void ) return t_generic_element; impure function fetch( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier : in positive ) return t_generic_element; impure function fetch( constant identifier_option : in t_identifier_option; constant identifier : in positive ) return t_generic_element; impure function fetch( constant instance : in integer ) return t_generic_element; impure function fetch( constant dummy : in t_void ) return t_generic_element; impure function find_position( constant element : in t_generic_element) return integer; impure function find_position( constant instance : in integer; constant element : in t_generic_element) return integer; impure function find_entry_num( constant element : in t_generic_element) return integer; impure function find_entry_num( constant instance : in integer; constant element : in t_generic_element) return integer; impure function exists( constant instance : in integer; constant element : in t_generic_element ) return boolean; impure function exists( constant element : in t_generic_element ) return boolean; impure function get_entry_num( constant instance : in integer; constant position_val : in positive) return integer; impure function get_entry_num( constant position_val : in positive) return integer; procedure print_queue( constant instance : in integer); procedure print_queue( constant dummy : in t_void); end protected; end package generic_queue_pkg; package body generic_queue_pkg is type t_generic_queue is protected body -- Types and control variables for the linked list implementation type t_element; type t_element_ptr is access t_element; type t_element is record entry_num : natural; next_element : t_element_ptr; element_data : t_generic_element; end record; type t_element_ptr_array is array(integer range 0 to C_MAX_QUEUE_INSTANCE_NUM) of t_element_ptr; type t_string_array is array(integer range 0 to C_MAX_QUEUE_INSTANCE_NUM) of string(1 to C_LOG_SCOPE_WIDTH); variable vr_last_element : t_element_ptr_array := (others => null); -- Back entry variable vr_first_element : t_element_ptr_array := (others => null); -- Front entry variable vr_num_elements_in_queue : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => 0); -- Scope variables variable vr_scope : t_string_array := (others => (others => NUL)); variable vr_scope_is_defined : boolean_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false); -- Name variables variable vr_name : string(1 to C_LOG_SCOPE_WIDTH) := (others => NUL); variable vr_name_is_defined : boolean := false; variable vr_queue_count_max : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => GC_QUEUE_COUNT_MAX); variable vr_queue_count_threshold : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => GC_QUEUE_COUNT_THRESHOLD); variable vr_queue_count_threshold_severity : t_alert_level := TB_WARNING; variable vr_entry_num : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => 0); -- Incremented before first insert -- Fill level alert type t_queue_count_threshold_alert_frequency is (ALWAYS, FIRST_TIME_ONLY); constant C_ALERT_FREQUENCY : t_queue_count_threshold_alert_frequency := FIRST_TIME_ONLY; variable vr_queue_count_threshold_triggered : boolean_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false); ------------------------------------------------------------------------------------------------------ -- -- Helper methods (not visible from outside) -- ------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------ -- Helper method: Check if an Alert shall be triggered (to be called before adding another entry) ------------------------------------------------------------------------------------------------------ procedure perform_pre_add_checks ( constant instance : in integer ) is begin if((vr_queue_count_threshold(instance) /= 0) and (vr_num_elements_in_queue(instance) >= vr_queue_count_threshold(instance))) then if((C_ALERT_FREQUENCY = ALWAYS) or (C_ALERT_FREQUENCY = FIRST_TIME_ONLY and not vr_queue_count_threshold_triggered(instance))) then alert(vr_queue_count_threshold_severity, "Queue is now at " & to_string(vr_queue_count_threshold(instance)) & " of " & to_string(vr_queue_count_max(instance)) & " elements.", vr_scope(instance)); vr_queue_count_threshold_triggered(instance) := true; end if; end if; end procedure; ------------------------------------------------------------------------------------------------------ -- Helper method: Iterate through all entries, and match the one with element_data = element -- This also works if the element is a record or array, whereas all entries/indexes must match ------------------------------------------------------------------------------------------------------ procedure match_element_data ( instance : in integer; -- Queue instance element : in t_generic_element; -- Element to search for found_match : out boolean; -- True if a match was found. matched_position : out integer; -- valid if found_match=true matched_element_ptr : out t_element_ptr -- valid if found_match=true ) is variable v_position_ctr : integer := 1; -- Keep track of POSITION when traversing the linked list variable v_element_ptr : t_element_ptr; -- Entry currently being checked for match begin -- Default found_match := false; matched_position := C_NO_MATCH; matched_element_ptr := null; if vr_num_elements_in_queue(instance) > 0 then -- Search from front to back element v_element_ptr := vr_first_element(instance); loop if v_element_ptr.element_data = element then -- Element matched entry found_match := true; matched_position := v_position_ctr; matched_element_ptr := v_element_ptr; exit; else -- No match. if v_element_ptr.next_element = null then exit; -- Last entry. All queue entries have been searched through. end if; v_element_ptr := v_element_ptr.next_element; -- next queue entry v_position_ctr := v_position_ctr + 1; end if; end loop; end if; end procedure; -- Find and return entry that matches the identifier procedure match_identifier ( instance : in integer; -- Queue instance identifier_option : in t_identifier_option; -- Determines what 'identifier' means identifier : in positive; -- Identifier value to search for found_match : out boolean; -- True if a match was found. matched_position : out integer; -- valid if found_match=true matched_element_ptr : out t_element_ptr; -- valid if found_match=true preceding_element_ptr : out t_element_ptr -- valid if found_match=true. Element at position-1, pointing to elemnt_ptr ) is -- Search from front to back element. Init pointers/counters to the first entry: variable v_element_ptr : t_element_ptr := vr_first_element(instance); -- Entry currently being checked for match variable v_position_ctr : integer := 1; -- Keep track of POSITION when traversing the linked list begin -- Default found_match := false; matched_position := C_NO_MATCH; matched_element_ptr := null; preceding_element_ptr := null; -- If queue is not empty and indentifier in valid range if (vr_num_elements_in_queue(instance) > 0) and ((identifier_option = POSITION and identifier <= vr_num_elements_in_queue(instance)) or (identifier_option = ENTRY_NUM and identifier <= vr_entry_num(instance))) then loop -- For each element in queue: -- Check if POSITION or ENTRY_NUM matches v_element_ptr if (identifier_option = POSITION) and (v_position_ctr = identifier) then found_match := true; end if; if (identifier_option = ENTRY_NUM) and (v_element_ptr.entry_num = identifier) then found_match := true; end if; if found_match then -- This element matched. Done searching. matched_position := v_position_ctr; matched_element_ptr := v_element_ptr; exit; else -- No match. if v_element_ptr.next_element = null then -- report "last v_position_ctr = " & to_string(v_position_ctr); exit; -- Last entry. All queue entries have been searched through. end if; preceding_element_ptr := v_element_ptr; -- the entry at the postition before element_ptr v_element_ptr := v_element_ptr.next_element; -- next queue entry v_position_ctr := v_position_ctr + 1; end if; end loop; -- for each element in queue end if; -- Not empty end procedure; ------------------------------------------------------------------------------------------------------ -- -- Public methods, visible from outside -- ------------------------------------------------------------------------------------------------------ -- add : Insert element in the back of queue, i.e. at the highest position procedure add( constant instance : in integer; constant element : in t_generic_element ) is constant proc_name : string := "add"; variable v_previous_ptr : t_element_ptr; begin check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER); perform_pre_add_checks(instance); check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, proc_name & "() into generic queue (of size " & to_string(vr_queue_count_max(instance)) & ") when full", vr_scope(instance), ID_NEVER); -- Increment vr_entry_num vr_entry_num(instance) := vr_entry_num(instance)+1; -- Set read and write pointers when appending element to existing list if vr_num_elements_in_queue(instance) > 0 then v_previous_ptr := vr_last_element(instance); vr_last_element(instance) := new t_element'(entry_num => vr_entry_num(instance), next_element => null, element_data => element); v_previous_ptr.next_element := vr_last_element(instance); -- Insert the new element into the linked list else -- List is empty vr_last_element(instance) := new t_element'(entry_num => vr_entry_num(instance), next_element => null, element_data => element); vr_first_element(instance) := vr_last_element(instance); -- Update read pointer, since this is the first and only element in the list. end if; -- Increment number of elements vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) + 1; end procedure; procedure add( constant element : in t_generic_element ) is begin add(1, element); end procedure; procedure put( constant instance : in integer; constant element : in t_generic_element ) is begin add(instance, element); end procedure; procedure put( constant element : in t_generic_element ) is begin put(1, element); end procedure; impure function get( constant instance : in integer ) return t_generic_element is begin return fetch(instance); end function; impure function get( constant dummy : in t_void ) return t_generic_element is begin return get(1); end function; procedure flush( constant instance : in integer ) is variable v_to_be_deallocated_ptr : t_element_ptr; begin check_value(vr_scope_is_defined(instance), TB_WARNING, "Scope name must be defined for this generic queue " &to_string(instance), "???", ID_NEVER); -- Deallocate all entries in the list -- Setting the last element to null and iterating over the queue until finding the null element vr_last_element(instance) := null; while vr_first_element(instance) /= null loop v_to_be_deallocated_ptr := vr_first_element(instance); vr_first_element(instance) := vr_first_element(instance).next_element; DEALLOCATE(v_to_be_deallocated_ptr); end loop; -- Reset the queue counter vr_num_elements_in_queue(instance) := 0; vr_queue_count_threshold_triggered(instance) := false; end procedure; procedure flush( constant dummy : in t_void ) is begin flush(1); end procedure; procedure reset( constant instance : in integer) is begin flush(instance); vr_entry_num(instance) := 0; -- Incremented before first insert end procedure; procedure reset( constant dummy : in t_void) is begin reset(1); end procedure; impure function is_empty( constant instance : in integer ) return boolean is begin if vr_num_elements_in_queue(instance) = 0 then return true; else return false; end if; end function; impure function is_empty( constant dummy : in t_void ) return boolean is begin return is_empty(1); end function; procedure set_scope( constant instance : in integer; constant scope : in string) is begin if instance = ALL_INSTANCES then if scope'length > C_LOG_SCOPE_WIDTH then vr_scope := (others => scope(1 to C_LOG_SCOPE_WIDTH)); else for idx in vr_scope'range loop vr_scope(idx) := (others => NUL); vr_scope(idx)(1 to scope'length) := scope; end loop; end if; vr_scope_is_defined := (others => true); else if scope'length > C_LOG_SCOPE_WIDTH then vr_scope(instance) := scope(1 to C_LOG_SCOPE_WIDTH); else vr_scope(instance) := (others => NUL); vr_scope(instance)(1 to scope'length) := scope; end if; vr_scope_is_defined(instance) := true; end if; end procedure; procedure set_scope( constant scope : in string) is begin set_scope(1, scope); end procedure; procedure set_name( constant name : in string) is begin vr_name(1 to name'length) := name; vr_name_is_defined := true; end procedure; impure function get_scope( constant instance : in integer ) return string is begin return to_string(vr_scope(instance)); end function; impure function get_scope( constant dummy : in t_void ) return string is begin return get_scope(1); end function; impure function get_count( constant instance : in integer ) return natural is begin return vr_num_elements_in_queue(instance); end function; impure function get_count( constant dummy : in t_void ) return natural is begin return get_count(1); end function; impure function get_queue_count_max( constant instance : in integer ) return natural is begin return vr_queue_count_max(instance); end function; impure function get_queue_count_max( constant dummy : in t_void ) return natural is begin return get_queue_count_max(1); end function; procedure set_queue_count_max( constant instance : in integer; constant queue_count_max : in natural ) is begin vr_queue_count_max(instance) := queue_count_max; check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, "set_queue_count_max() new queue max count (" & to_string(vr_queue_count_max(instance)) & ") is less than current queue count(" & to_string(vr_num_elements_in_queue(instance)) & ").", vr_scope(instance), ID_NEVER); end procedure; procedure set_queue_count_max( constant queue_count_max : in natural ) is begin set_queue_count_max(1, queue_count_max); end procedure; procedure set_queue_count_threshold( constant instance : in integer; constant queue_count_alert_level : in natural ) is begin vr_queue_count_threshold(instance) := queue_count_alert_level; end procedure; procedure set_queue_count_threshold( constant queue_count_alert_level : in natural ) is begin set_queue_count_threshold(1, queue_count_alert_level); end procedure; impure function get_queue_count_threshold( constant instance : in integer ) return natural is begin return vr_queue_count_threshold(instance); end function; impure function get_queue_count_threshold( constant dummy : in t_void ) return natural is begin return get_queue_count_threshold(1); end function; impure function get_queue_count_threshold_severity( constant dummy : in t_void ) return t_alert_level is begin return vr_queue_count_threshold_severity; end function; procedure set_queue_count_threshold_severity( constant alert_level : in t_alert_level) is begin vr_queue_count_threshold_severity := alert_level; end procedure; ---------------------------------------------------- -- Insert: ---------------------------------------------------- -- Inserts element into the queue after the matching entry with specified identifier: -- -- When identifier_option = POSITION: -- identifier = position in queue, counting from 1 -- -- When identifier_option = ENTRY_NUM: -- identifier = entry number, counting from 1 procedure insert( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier : in positive; constant element : in t_generic_element) is constant proc_name : string := "insert"; variable v_element_ptr : t_element_ptr; -- The element currently being processed variable v_new_element_ptr : t_element_ptr; -- Used when creating a new element variable v_preceding_element_ptr : t_element_ptr; -- Used when creating a new element variable v_found_match : boolean; variable v_matched_position : integer; begin -- pre insert checks check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER); perform_pre_add_checks(instance); check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, proc_name & "() into generic queue (of size " & to_string(vr_queue_count_max(instance)) & ") when full", vr_scope(instance), ID_NEVER); if (identifier /= 1) then if (identifier_option = POSITION) then check_value(vr_num_elements_in_queue(instance) >= identifier, TB_ERROR, proc_name & "() into position larger than number of elements in queue. Use add() instead when inserting at the back of the queue", vr_scope(instance), ID_NEVER); else -- identifier_option /= POSITION check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() into empty queue isn't supported. Use add() instead", vr_scope(instance), ID_NEVER); end if; end if; -- Search from front to back element. match_identifier( instance => instance , identifier_option => identifier_option , identifier => identifier , found_match => v_found_match , matched_position => v_matched_position , matched_element_ptr => v_element_ptr , preceding_element_ptr => v_preceding_element_ptr ); if v_found_match then -- Make new element vr_entry_num(instance) := vr_entry_num(instance)+1; -- Increment vr_entry_num -- POSITION: insert at matched position if identifier_option = POSITION then v_new_element_ptr := new t_element'(entry_num => vr_entry_num(instance), next_element => v_element_ptr, element_data => element); -- if match is first element if v_preceding_element_ptr = null then vr_first_element(instance) := v_new_element_ptr; -- Insert the new element into the front of the linked list else v_preceding_element_ptr.next_element := v_new_element_ptr; -- Insert the new element into the linked list end if; --ENTRY_NUM: insert at position after match else v_new_element_ptr := new t_element'(entry_num => vr_entry_num(instance), next_element => v_element_ptr.next_element, element_data => element); v_element_ptr.next_element := v_new_element_ptr; -- Insert the new element into the linked list end if; vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) + 1; -- Increment number of elements elsif identifier_option = POSITION then -- v_found_match = false if identifier = 1 then add(instance, element); end if; elsif identifier_option = ENTRY_NUM then if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " & "instance=" & to_string(instance) & ", identifier_option=" & t_identifier_option'image(identifier_option) & ", identifier=" & to_string(identifier) & ", element...", scope); end if; end if; end procedure; procedure insert( constant identifier_option : in t_identifier_option; constant identifier : in positive; constant element : in t_generic_element) is begin insert(1, identifier_option, identifier, element); end procedure; ---------------------------------------------------- -- delete: ---------------------------------------------------- -- Read and remove the entry matching the identifier -- -- When identifier_option = POSITION: -- identifier = position in queue, counting from 1 -- -- When identifier_option = ENTRY_NUM: -- identifier = entry number, counting from 1 procedure delete( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier_min : in positive; constant identifier_max : in positive ) is constant proc_name : string := "delete"; variable v_matched_element_ptr : t_element_ptr; -- The element being deleted variable v_element_to_delete_ptr : t_element_ptr; -- The element being deleted variable v_matched_element_data : t_generic_element; -- Return value variable v_preceding_element_ptr : t_element_ptr; variable v_matched_position : integer; variable v_found_match : boolean; variable v_deletes_remaining : integer; begin check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER); if(vr_num_elements_in_queue(instance) < vr_queue_count_threshold(instance)) then -- reset alert trigger if set vr_queue_count_threshold_triggered(instance) := false; end if; -- delete based on POSITION : -- Note that when deleting the first position, all above positions are decremented by one. -- Find the identifier_min, delete it, and following next_element until we reach number of positions to delete if (identifier_option = POSITION) then check_value(vr_num_elements_in_queue(instance) >= identifier_max, TB_ERROR, proc_name & " where identifier_max > generic queue size", vr_scope(instance), ID_NEVER); check_value(identifier_max >= identifier_min, TB_ERROR, "Check that identifier_max >= identifier_min", vr_scope(instance), ID_NEVER); v_deletes_remaining := 1 + identifier_max - identifier_min; -- Find min position match_identifier( instance => instance , identifier_option => identifier_option , identifier => identifier_min, found_match => v_found_match , matched_position => v_matched_position , matched_element_ptr => v_matched_element_ptr , preceding_element_ptr => v_preceding_element_ptr ); if v_found_match then v_element_to_delete_ptr := v_matched_element_ptr; -- Delete element at identifier_min first while v_deletes_remaining > 0 loop -- Update pointer to the element about to be removed. if (v_preceding_element_ptr = null) then -- Removing the first entry, vr_first_element(instance) := vr_first_element(instance).next_element; else -- Removing an intermediate or last entry v_preceding_element_ptr.next_element := v_element_to_delete_ptr.next_element; -- If the element is the last entry, update vr_last_element if v_element_to_delete_ptr.next_element = null then vr_last_element(instance) := v_preceding_element_ptr; end if; end if; -- Decrement number of elements vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1; -- Memory management DEALLOCATE(v_element_to_delete_ptr); v_deletes_remaining := v_deletes_remaining - 1; -- Prepare next iteration: -- Next element to delete: if v_deletes_remaining > 0 then if (v_preceding_element_ptr = null) then -- We just removed the first entry, so there's no pointer from a preceding entry. Next to delete is the first entry. v_element_to_delete_ptr := vr_first_element(instance); else -- Removed an intermediate or last entry. Next to delete is the pointer from the preceding element v_element_to_delete_ptr := v_preceding_element_ptr.next_element; end if; end if; end loop; else -- v_found_match if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " & "instance=" & to_string(instance) & ", identifier_option=" & t_identifier_option'image(identifier_option) & ", identifier_min=" & to_string(identifier_min) & ", identifier_max=" & to_string(identifier_max) & ", non-matching identifier=" & to_string(identifier_min), scope); end if; end if; -- v_found_match -- delete based on ENTRY_NUM : -- Unlike position, an entry's Entry_num is stable when deleting other entries -- Entry_num is not necessarily increasing as we follow next_element pointers. -- This means that we must do a complete search for each entry we want to delete elsif (identifier_option = ENTRY_NUM) then check_value(vr_entry_num(instance) >= identifier_max, TB_ERROR, proc_name & " where identifier_max > highest entry number", vr_scope(instance), ID_NEVER); check_value(identifier_max >= identifier_min, TB_ERROR, "Check that identifier_max >= identifier_min", vr_scope(instance), ID_NEVER); v_deletes_remaining := 1 + identifier_max - identifier_min; -- For each entry to delete, find it based on entry_num , then delete it for identifier in identifier_min to identifier_max loop match_identifier( instance => instance , identifier_option => identifier_option , identifier => identifier, found_match => v_found_match , matched_position => v_matched_position , matched_element_ptr => v_matched_element_ptr , preceding_element_ptr => v_preceding_element_ptr ); if v_found_match then v_element_to_delete_ptr := v_matched_element_ptr; -- Update pointer to the element about to be removed. if (v_preceding_element_ptr = null) then -- Removing the first entry, vr_first_element(instance) := vr_first_element(instance).next_element; else -- Removing an intermediate or last entry v_preceding_element_ptr.next_element := v_element_to_delete_ptr.next_element; -- If the element is the last entry, update vr_last_element if v_element_to_delete_ptr.next_element = null then vr_last_element(instance) := v_preceding_element_ptr; end if; end if; -- Decrement number of elements vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1; -- Memory management DEALLOCATE(v_element_to_delete_ptr); else -- v_found_match if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " & "instance=" & to_string(instance) & ", identifier_option=" & t_identifier_option'image(identifier_option) & ", identifier_min=" & to_string(identifier_min) & ", identifier_max=" & to_string(identifier_max) & ", non-matching identifier=" & to_string(identifier), scope); end if; end if; -- v_found_match end loop; end if; -- identifier_option end procedure; procedure delete( constant identifier_option : in t_identifier_option; constant identifier_min : in positive; constant identifier_max : in positive ) is begin delete(1, identifier_option, identifier_min, identifier_max); end procedure; procedure delete( constant instance : in integer; constant element : in t_generic_element ) is variable v_entry_num : integer:= find_entry_num(element); begin delete(instance, ENTRY_NUM, v_entry_num, v_entry_num); end procedure; procedure delete( constant element : in t_generic_element ) is begin delete(1, element); end procedure; procedure delete( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier : in positive; constant range_option : in t_range_option ) is begin case range_option is when SINGLE => delete(instance, identifier_option, identifier, identifier); when AND_LOWER => delete(instance, identifier_option, 1, identifier); when AND_HIGHER => if identifier_option = POSITION then delete(instance, identifier_option, identifier, vr_num_elements_in_queue(instance)); elsif identifier_option = ENTRY_NUM then delete(instance, identifier_option, identifier, vr_entry_num(instance)); end if; end case; end procedure; procedure delete( constant identifier_option : in t_identifier_option; constant identifier : in positive; constant range_option : in t_range_option ) is begin delete(1, identifier_option, identifier, range_option); end procedure; ---------------------------------------------------- -- peek: ---------------------------------------------------- -- Read the entry matching the identifier, but don't remove it. -- -- When identifier_option = POSITION: -- identifier = position in queue, counting from 1 -- -- When identifier_option = ENTRY_NUM: -- identifier = entry number, counting from 1 impure function peek( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier : in positive ) return t_generic_element is constant proc_name : string := "peek"; variable v_matched_element_data : t_generic_element; -- Return value variable v_matched_element_ptr : t_element_ptr; -- The element currently being processed variable v_preceding_element_ptr : t_element_ptr; variable v_matched_position : integer; -- Keep track of POSITION when traversing the linked list variable v_found_match : boolean := false; begin check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER); check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() from generic queue when empty", vr_scope(instance), ID_NEVER); match_identifier( instance => instance , identifier_option => identifier_option , identifier => identifier , found_match => v_found_match , matched_position => v_matched_position , matched_element_ptr => v_matched_element_ptr , preceding_element_ptr => v_preceding_element_ptr ); if v_found_match then v_matched_element_data := v_matched_element_ptr.element_data; else if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " & "instance=" & to_string(instance) & ", identifier_option=" & t_identifier_option'image(identifier_option) & ", identifier=" & to_string(identifier), scope); end if; end if; return v_matched_element_data; end function; impure function peek( constant identifier_option : in t_identifier_option; constant identifier : in positive ) return t_generic_element is begin return peek(1, identifier_option, identifier); end function; -- If no identifier is specified, return the oldest entry (first position) impure function peek( constant instance : in integer ) return t_generic_element is begin return peek(instance, POSITION, 1); end function; impure function peek( constant dummy : in t_void ) return t_generic_element is begin return peek(1); end function; ---------------------------------------------------- -- Fetch: ---------------------------------------------------- -- Read and remove the entry matching the identifier -- -- When identifier_option = POSITION: -- identifier = position in queue, counting from 1 -- -- When identifier_option = ENTRY_NUM: -- identifier = entry number, counting from 1 impure function fetch( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier : in positive ) return t_generic_element is constant proc_name : string := "fetch"; variable v_matched_element_ptr : t_element_ptr; -- The element being fetched variable v_matched_element_data : t_generic_element; -- Return value variable v_preceding_element_ptr : t_element_ptr; variable v_matched_position : integer; variable v_found_match : boolean; begin check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER); check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() from generic queue when empty", vr_scope(instance), ID_NEVER); if(vr_num_elements_in_queue(instance) < vr_queue_count_threshold(instance)) then -- reset alert trigger if set vr_queue_count_threshold_triggered(instance) := false; end if; match_identifier( instance => instance , identifier_option => identifier_option , identifier => identifier , found_match => v_found_match , matched_position => v_matched_position , matched_element_ptr => v_matched_element_ptr , preceding_element_ptr => v_preceding_element_ptr ); if v_found_match then -- Keep info about element before removing it from queue v_matched_element_data := v_matched_element_ptr.element_data; -- Update pointer to the element about to be removed. if (v_preceding_element_ptr = null) then -- Removing the first entry, vr_first_element(instance) := vr_first_element(instance).next_element; else -- Removing an intermediate or last entry v_preceding_element_ptr.next_element := v_matched_element_ptr.next_element; -- If the element is the last entry, update vr_last_element if v_matched_element_ptr.next_element = null then vr_last_element(instance) := v_preceding_element_ptr; end if; end if; -- Decrement number of elements vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1; -- Memory management DEALLOCATE(v_matched_element_ptr); else if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " & "instance=" & to_string(instance) & ", identifier_option=" & t_identifier_option'image(identifier_option) & ", identifier=" & to_string(identifier), scope); end if; end if; return v_matched_element_data; end function; impure function fetch( constant identifier_option : in t_identifier_option; constant identifier : in positive ) return t_generic_element is begin return fetch(1, identifier_option, identifier); end function; -- If no identifier is specified, return the oldest entry (first position) impure function fetch( constant instance : in integer ) return t_generic_element is begin return fetch(instance, POSITION, 1); end function; impure function fetch( constant dummy : in t_void ) return t_generic_element is begin return fetch(1); end function; -- Returns position of entry if found, else C_NO_MATCH. impure function find_position( constant instance : in integer; constant element : in t_generic_element -- ) return integer is variable v_element_ptr : t_element_ptr; variable v_matched_position : integer; variable v_found_match : boolean; begin check_value(vr_scope_is_defined(instance), TB_WARNING, "find_position: Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER); -- Don't include this check, because we may want to use exists() on an empty queue. -- check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "find_position() from generic queue when empty", vr_scope(instance), ID_NEVER); match_element_data( instance => instance, element => element, found_match => v_found_match, matched_position => v_matched_position, matched_element_ptr => v_element_ptr ); if v_found_match then return v_matched_position; else return C_NO_MATCH; end if; end function; impure function find_position( constant element : in t_generic_element ) return integer is begin return find_position(1, element); end function; impure function exists( constant instance : in integer; constant element : in t_generic_element ) return boolean is begin return (find_position(instance, element) /= C_NO_MATCH); end function; impure function exists( constant element : in t_generic_element ) return boolean is begin return exists(1, element); end function; -- Returns entry number or position to entry if found, else C_NO_MATCH. impure function find_entry_num( constant instance : in integer; constant element : in t_generic_element ) return integer is variable v_element_ptr : t_element_ptr; variable v_matched_position : integer; variable v_found_match : boolean; begin check_value(vr_scope_is_defined(instance), TB_WARNING, "find_entry_num(): Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER); check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "find_entry_num() from generic queue when empty", vr_scope(instance), ID_NEVER); match_element_data( instance => instance, element => element, found_match => v_found_match, matched_position => v_matched_position, matched_element_ptr => v_element_ptr ); if v_found_match then return v_element_ptr.entry_num; else return C_NO_MATCH; end if; end function; impure function find_entry_num( constant element : in t_generic_element ) return integer is begin return find_entry_num(1, element); end function; impure function get_entry_num( constant instance : in integer; constant position_val : in positive ) return integer is variable v_found_match : boolean; variable v_matched_position : integer; variable v_matched_element_ptr : t_element_ptr; variable v_preceding_element_ptr : t_element_ptr; begin check_value(vr_scope_is_defined(instance), TB_WARNING, "get_entry_num(): Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER); check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "get_entry_num() from generic queue when empty", vr_scope(instance), ID_NEVER); match_identifier( instance => instance , identifier_option => POSITION , identifier => position_val, found_match => v_found_match , matched_position => v_matched_position , matched_element_ptr => v_matched_element_ptr , preceding_element_ptr => v_preceding_element_ptr ); if v_found_match then return v_matched_element_ptr.entry_num; else return -1; end if; end function get_entry_num; impure function get_entry_num( constant position_val : in positive ) return integer is begin return get_entry_num(1, position_val); end function get_entry_num; -- for debugging: -- print each entry's position and entry_num procedure print_queue( constant instance : in integer ) is variable v_element_ptr : t_element_ptr; -- The element currently being processed variable v_new_element_ptr : t_element_ptr; -- Used when creating a new element variable v_position_ctr : natural := 1; -- Keep track of POSITION when traversing the linked list variable v_found_match : boolean := false; begin -- Search from front to back element. Initalise pointers/counters to the first entry: v_element_ptr := vr_first_element(instance); if v_element_ptr = NULL then return; -- Return if queue is empty end if; loop log(ID_UVVM_DATA_QUEUE, "Pos=" & to_string(v_position_ctr) & ", entry_num=" & to_string(v_element_ptr.entry_num) , scope); if v_element_ptr.next_element = null then exit; -- Last entry. All queue entries have been searched through. end if; v_element_ptr := v_element_ptr.next_element; -- next queue entry v_position_ctr := v_position_ctr + 1; end loop; end procedure; procedure print_queue( constant dummy : in t_void) is begin print_queue(1); end procedure; end protected body; end package body generic_queue_pkg; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library std; use std.textio.all; library work; use work.all; use work.procedures.all; entity tb_shift is end tb_shift; architecture behav of tb_shift is signal a : t_data := (others => '0'); signal b : t_data := (others => '0'); signal logic : t_data := (others => '0'); signal arith : t_data := (others => '0'); begin process variable l : line; begin wait for 20 ns; a <= X"00"; for i in 0 to 10 loop b <= std_logic_vector(to_unsigned(i, t_data'length)); wait for 20 ns; end loop; a <= X"AA"; for i in 0 to 10 loop b <= std_logic_vector(to_unsigned(i, t_data'length)); wait for 20 ns; end loop; a <= X"55"; for i in 0 to 10 loop b <= std_logic_vector(to_unsigned(i, t_data'length)); wait for 20 ns; end loop; a <= X"FF"; for i in 0 to 10 loop b <= std_logic_vector(to_unsigned(i, t_data'length)); wait for 20 ns; end loop; a <= X"7F"; for i in 0 to 10 loop b <= std_logic_vector(to_unsigned(i, t_data'length)); wait for 20 ns; end loop; assert false report "stop" severity failure; end process; ashift: entity work.shift_ra port map( a => a, b => b, c => arith ); lshift: entity work.shift_rl port map( a => a, b => b, c => logic ); end behav; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library uvvm_util; context uvvm_util.uvvm_util_context; library uvvm_vvc_framework; use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all; use work.transaction_pkg.all; package vvc_cmd_pkg is alias t_operation is work.transaction_pkg.t_operation; --=============================================================================================== -- t_vvc_cmd_record -- - Record type used for communication with the VVC --=============================================================================================== type t_vvc_cmd_record is record -- VVC dedicated fields data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0); data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0); num_words : natural; word_length : natural; when_to_start_transfer : t_when_to_start_transfer; action_when_transfer_is_done : t_action_when_transfer_is_done; action_between_words : t_action_between_words; -- Common VVC fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory) operation : t_operation; proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH); msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH); data_routing : t_data_routing; cmd_idx : natural; command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE msg_id : t_msg_id; gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed gen_boolean : boolean; -- Generic boolean timeout : time; alert_level : t_alert_level; delay : time; quietness : t_quietness; parent_msg_id_panel : t_msg_id_panel; end record; constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := ( data => (others => (others => '0')), data_exp => (others => (others => '0')), num_words => 0, word_length => 0, when_to_start_transfer => START_TRANSFER_IMMEDIATE, action_when_transfer_is_done => RELEASE_LINE_AFTER_TRANSFER, action_between_words => HOLD_LINE_BETWEEN_WORDS, -- Common VVC fields operation => NO_OPERATION, proc_call => (others => NUL), msg => (others => NUL), data_routing => NA, cmd_idx => 0, command_type => NO_COMMAND_TYPE, msg_id => NO_ID, gen_integer_array => (others => -1), gen_boolean => false, timeout => 0 ns, alert_level => failure, delay => 0 ns, quietness => NON_QUIET, parent_msg_id_panel => C_UNUSED_MSG_ID_PANEL ); --=============================================================================================== -- shared_vvc_cmd -- - Shared variable used for transmitting VVC commands --=============================================================================================== shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT; --=============================================================================================== -- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response : -- -- - Used for storing the result of a BFM procedure called by the VVC, -- so that the result can be transported from the VVC to for example a sequencer via -- fetch_result() as described in VVC_Framework_common_methods_QuickRef -- -- - t_vvc_result includes the return value of the procedure in the BFM. -- It can also be defined as a record if multiple values shall be transported from the BFM --=============================================================================================== subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0); type t_vvc_result_queue_element is record cmd_idx : natural; -- from UVVM handshake mechanism result : t_vvc_result; end record; type t_vvc_response is record fetch_is_accepted : boolean; transaction_result : t_transaction_result; result : t_vvc_result; end record; shared variable shared_vvc_response : t_vvc_response; --=============================================================================================== -- t_last_received_cmd_idx : -- - Used to store the last queued cmd in vvc interpreter. --=============================================================================================== type t_last_received_cmd_idx is array (t_channel range <>, natural range <>) of integer; --=============================================================================================== -- shared_vvc_last_received_cmd_idx -- - Shared variable used to get last queued index from vvc to sequencer --=============================================================================================== shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => (others => -1)); end package vvc_cmd_pkg; package body vvc_cmd_pkg is end package body vvc_cmd_pkg; |
library IEEE; use IEEE.std_logic_1164.all; use WORK.alu_types.all; entity MUX4TO1 is generic ( N: integer := NSUMG -- Number of bits ); port ( A: in std_logic_vector(N-1 downto 0); B: in std_logic_vector(N-1 downto 0); C: in std_logic_vector(N-1 downto 0); D: in std_logic_vector(N-1 downto 0); SEL: in std_logic_vector(1 downto 0); Y: out std_logic_vector(N-1 downto 0) ); end MUX4TO1; architecture behavioral of MUX4TO1 is signal Y_int: std_logic_vector(N-1 downto 0); begin MUX : process (SEL,A,B,C,D) begin case SEL is when "00" => Y_int <= A; when "01" => Y_int <= B; when "10" => Y_int <= C; when "11" => Y_int <= D; when others => Y_int <= (others => 'Z'); end case; end process; Y <= Y_int; end behavioral; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library uvvm_util; context uvvm_util.uvvm_util_context; library uvvm_vvc_framework; use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all; package vvc_cmd_pkg is --=============================================================================================== -- t_operation -- - Bitvis defined BFM operations --=============================================================================================== type t_operation is ( -- UVVM common NO_OPERATION, AWAIT_COMPLETION, AWAIT_ANY_COMPLETION, ENABLE_LOG_MSG, DISABLE_LOG_MSG, FLUSH_COMMAND_QUEUE, FETCH_RESULT, INSERT_DELAY, TERMINATE_CURRENT_COMMAND, -- VVC local MASTER_TRANSMIT_AND_RECEIVE, MASTER_TRANSMIT_AND_CHECK, MASTER_TRANSMIT_ONLY, MASTER_RECEIVE_ONLY, MASTER_CHECK_ONLY, SLAVE_TRANSMIT_AND_RECEIVE, SLAVE_TRANSMIT_AND_CHECK, SLAVE_TRANSMIT_ONLY, SLAVE_RECEIVE_ONLY, SLAVE_CHECK_ONLY); constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300; constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 32; constant C_VVC_CMD_MAX_WORDS : natural := 8; --=============================================================================================== -- t_vvc_cmd_record -- - Record type used for communication with the VVC --=============================================================================================== type t_vvc_cmd_record is record -- VVC dedicated fields data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0); data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0); num_words : natural; word_length : natural; when_to_start_transfer : t_when_to_start_transfer; action_when_transfer_is_done : t_action_when_transfer_is_done; action_between_words : t_action_between_words; -- Common VVC fields (Used by td_vvc_framework_common_methods_pkg procedures, and thus mandatory) operation : t_operation; proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH); msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH); cmd_idx : natural; command_type : t_immediate_or_queued; -- QUEUED/IMMEDIATE msg_id : t_msg_id; gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed gen_boolean : boolean; -- Generic boolean timeout : time; alert_level : t_alert_level; delay : time; quietness : t_quietness; end record; constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := ( data => (others => (others => '0')), data_exp => (others => (others => '0')), num_words => 0, word_length => 0, when_to_start_transfer => START_TRANSFER_IMMEDIATE, action_when_transfer_is_done => RELEASE_LINE_AFTER_TRANSFER, action_between_words => HOLD_LINE_BETWEEN_WORDS, -- Common VVC fields operation => NO_OPERATION, proc_call => (others => NUL), msg => (others => NUL), cmd_idx => 0, command_type => NO_COMMAND_TYPE, msg_id => NO_ID, gen_integer_array => (others => -1), gen_boolean => false, timeout => 0 ns, alert_level => failure, delay => 0 ns, quietness => NON_QUIET ); --=============================================================================================== -- shared_vvc_cmd -- - Shared variable used for transmitting VVC commands --=============================================================================================== shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT; --=============================================================================================== -- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response : -- -- - Used for storing the result of a BFM procedure called by the VVC, -- so that the result can be transported from the VVC to for example a sequencer via -- fetch_result() as described in VVC_Framework_common_methods_QuickRef -- -- - t_vvc_result includes the return value of the procedure in the BFM. -- It can also be defined as a record if multiple values shall be transported from the BFM --=============================================================================================== subtype t_vvc_result is std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0); type t_vvc_result_queue_element is record cmd_idx : natural; -- from UVVM handshake mechanism result : t_vvc_result; end record; type t_vvc_response is record fetch_is_accepted : boolean; transaction_result : t_transaction_result; result : t_vvc_result; end record; shared variable shared_vvc_response : t_vvc_response; --=============================================================================================== -- t_last_received_cmd_idx : -- - Used to store the last queued cmd in vvc interpreter. --=============================================================================================== type t_last_received_cmd_idx is array (t_channel range <>, natural range <>) of integer; --=============================================================================================== -- shared_vvc_last_received_cmd_idx -- - Shared variable used to get last queued index from vvc to sequencer --=============================================================================================== shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM) := (others => (others => -1)); end package vvc_cmd_pkg; package body vvc_cmd_pkg is end package body vvc_cmd_pkg; |
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.std_logic_misc.all; use work.CONSTANTS.all; use work.ROCACHE_PKG.all; use work.RWCACHE_PKG.all; use work.alu_types.all; use work.cu.all; entity DLX is port ( -- Inputs CLK : in std_logic; -- Clock RST : in std_logic; -- Reset:Active-High IRAM_ADDRESS : out std_logic_vector(Instr_size - 1 downto 0); IRAM_ISSUE : out std_logic; IRAM_READY : in std_logic; IRAM_DATA : in std_logic_vector(2*Data_size-1 downto 0); DRAM_ADDRESS : out std_logic_vector(Instr_size-1 downto 0); DRAM_ISSUE : out std_logic; DRAM_READNOTWRITE : out std_logic; DRAM_READY : in std_logic; DRAM_DATA : inout std_logic_vector(2*Data_size-1 downto 0) ); end DLX; architecture structural of DLX is component CU_UP is port ( -- Inputs CLK : in std_logic; -- Clock RST : in std_logic; -- Reset:Active-High IR : in std_logic_vector(31 downto 0); JMP_PREDICT : in std_logic; -- Jump Prediction ICACHE_STALL: in std_logic; -- The instruction cache is in stall DCACHE_STALL: in std_logic; -- The rwcache is busy ISZERO : in std_logic; -- Needed for condizional jumps JMP_ADDRESS : in std_logic_vector(31 downto 0); NPC_ADDRESS : in std_logic_vector(31 downto 0); PC : out std_logic_vector(31 downto 0); -- Outputs JUMP: out std_logic; LATCHER: out std_logic; MUXIMMEDIATE_CTR: out std_logic; MUXJMPADDRESS_CTR: out std_logic; MUXRD0_CTR: out std_logic; MUXRD_CTR: out std_logic; WRF_ENABLE: out std_logic; WRF_CALL: out std_logic; WRF_RET: out std_logic; WRF_RS1_ENABLE: out std_logic; WRF_RS2_ENABLE: out std_logic; MUXALUOUT_CTR: out std_logic; MUXALU_CTR: out std_logic; ALU_FUNC: out std_logic_vector(4 downto 0); MEMORY_ENABLE: out std_logic; MEMORY_RNOTW: out std_logic; WRF_RD_ENABLE: out std_logic; ID_STALL: out std_logic; EXE_STALL: out std_logic; MEM_STALL: out std_logic; WB_STALL: out std_logic ); end component; component ROCACHE is port ( CLK : in std_logic; RST : in std_logic; -- active high ENABLE : in std_logic; ADDRESS : in std_logic_vector(Instr_size - 1 downto 0); OUT_DATA : out std_logic_vector(Instr_size - 1 downto 0); STALL : out std_logic; RAM_ISSUE : out std_logic; RAM_ADDRESS : out std_logic_vector(Instr_size - 1 downto 0); RAM_DATA : in std_logic_vector(2*Instr_size - 1 downto 0); RAM_READY : in std_logic ); end component; component INCREMENTER is generic ( N: integer := 32 ); port ( A: in std_logic_vector (N-1 downto 0); Y: out std_logic_vector(N-1 downto 0) ); end component; component RCA_GENERIC is generic ( NBIT : integer := 32 ); port ( A : in std_logic_vector(NBIT-1 downto 0); B : in std_logic_vector(NBIT-1 downto 0); Ci : in std_logic; S : out std_logic_vector(NBIT-1 downto 0); Co : out std_logic ); end component; component SGNEXT is generic ( INBITS: integer; OUTBITS: integer ); port( DIN : in std_logic_vector (INBITS-1 downto 0); DOUT : out std_logic_vector (OUTBITS-1 downto 0) ); end component; component LATCH is generic ( N: integer := 1 ); port ( DIN: in std_logic_vector(N-1 downto 0); -- Data in EN: in std_logic; RESET: in std_logic; DOUT: out std_logic_vector(N-1 downto 0) -- Data out ); end component; component REGISTER_FDL is generic ( N: integer := 32 ); port ( DIN: in std_logic_vector(N-1 downto 0); -- Data in ENABLE: in std_logic; -- Enable CLK: in std_logic; -- Clock RESET: in std_logic; -- Reset DOUT: out std_logic_vector(N-1 downto 0) -- Data out ); end component; component MUX is generic ( N: integer := 1 -- Number of bits ); port ( A: in std_logic_vector(N-1 downto 0); B: in std_logic_vector(N-1 downto 0); SEL: in std_logic; Y: out std_logic_vector(N-1 downto 0) ); end component; component MUX4TO1 is generic ( N: integer := NSUMG -- Number of bits ); port ( A: in std_logic_vector(N-1 downto 0); B: in std_logic_vector(N-1 downto 0); C: in std_logic_vector(N-1 downto 0); D: in std_logic_vector(N-1 downto 0); SEL: in std_logic_vector(1 downto 0); Y: out std_logic_vector(N-1 downto 0) ); end component; component WRF is generic ( NBIT: integer; numWindows: integer; numRegsPerWin: integer; logNumWindows: integer; logNumRegsPerWin: integer ); port ( CLK: IN std_logic; RESET: IN std_logic; ENABLE: IN std_logic; CALL: IN std_logic; -- Call -> Next context RET: IN std_logic; -- Return -> Previous context RD1: IN std_logic; -- Read 1 RD2: IN std_logic; -- Read 2 WR: IN std_logic; -- Write ADDR_RD1: IN std_logic_vector(logNumRegsPerWin+1 downto 0); -- Read Address 1 ADDR_RD2: IN std_logic_vector(logNumRegsPerWin+1 downto 0); -- Read Address 2 ADDR_WRC: IN std_logic_vector(logNumRegsPerWin+1 downto 0); -- Write Address ADDR_WR: IN std_logic_vector(logNumWindows+logNumRegsPerWin+1 downto 0); -- Write Address REAL_ADDR_RD1: OUT std_logic_vector(logNumWindows+logNumRegsPerWin+1 downto 0); -- Read Address 1 REAL_ADDR_RD2: OUT std_logic_vector(logNumWindows+logNumRegsPerWin+1 downto 0); -- Read Address 2 REAL_ADDR_WR: OUT std_logic_vector(logNumWindows+logNumRegsPerWin+1 downto 0); -- Write Address OUT1: OUT std_logic_vector(NBIT-1 downto 0); -- Read data 1 OUT2: OUT std_logic_vector(NBIT-1 downto 0); -- Read data 2 DATAIN: IN std_logic_vector(NBIT-1 downto 0) -- Write data ); end component; component ALU generic ( N : integer := NSUMG ); port ( FUNC: in TYPE_OP; A, B: in std_logic_vector(N-1 downto 0); CLK: in std_logic; RESET: in std_logic; OUTALU: out std_logic_vector(N-1 downto 0) ); end component; component RWCACHE is generic ( regaddrsize : integer ); port ( CLK : in std_logic; RST : in std_logic; -- active high ENABLE_EX : in std_logic; READNOTWRITE_EX : in std_logic; ALU_OUT_REAL : in std_logic_vector(DATA_SIZE - 1 downto 0); RS2_DATA_EX : in std_logic_vector(DATA_SIZE - 1 downto 0); RS2_EX : in std_logic_vector(regaddrsize-1 downto 0); RD_MEM : in std_logic_vector(regaddrsize-1 downto 0); MEM_STALL : in std_logic; LATCHER : in std_logic; MEM_DATA : out std_logic_vector(DATA_SIZE - 1 downto 0); STALL : out std_logic; RAM_ISSUE : out std_logic; RAM_READNOTWRITE : out std_logic; RAM_ADDRESS : out std_logic_vector(DATA_SIZE - 1 downto 0); RAM_DATA : inout std_logic_vector(2*DATA_SIZE - 1 downto 0); RAM_READY : in std_logic ); end component; signal IPC, PC, NPC : std_logic_vector(Instr_size-1 downto 0) := (others => '0'); signal IR, IR_RF, ICACHE_IR : std_logic_vector(Instr_size-1 downto 0) := (others => '0'); signal ICACHE_STALL, ICACHE_STALL_NOT : std_logic := '1'; signal JMP_PREDICT : std_logic; -- Jump Prediction signal DCACHE_STALL : std_logic; -- The WRF is busy signal DCACHE_STALL_NOT : std_logic; -- The WRF is busy signal ICACHE_ENABLE : std_logic; signal MUXRD_CTR : std_logic; signal WRF_ENABLE : std_logic; signal WRF_CALL : std_logic; signal WRF_CALL_NS : std_logic; signal WRF_RET : std_logic; signal WRF_RET_R31 : std_logic; signal WRF_RS1_ENABLE : std_logic; signal WRF_RS2_ENABLE : std_logic; signal WRF_RD_ENABLE : std_logic; signal MUXALU_CTR : std_logic; signal ALU_FUNC : std_logic_vector(4 downto 0); signal MEMORY_ENABLE : std_logic; signal MEMORY_RNOTW : std_logic; signal JUMP : std_logic; signal LATCHER : std_logic; signal ID_STALL : std_logic; signal EXE_STALL : std_logic; signal MEM_STALL : std_logic; signal WB_STALL : std_logic; -- STAGE TWO signal MUXIMMEDIATE_CTR : std_logic; signal MUXJMPADDRESS_CTR : std_logic; signal MUXRD0_CTR : std_logic; signal IMMEDIATE : std_logic_vector(31 downto 0) := (others => '0'); signal IMMEDIATE_IR : std_logic_vector(31 downto 0) := (others => '0'); signal JMP_ADDRESS : std_logic_vector(31 downto 0) := (others => '0'); signal JMP_RELATIVE_ADDRESS : std_logic_vector(31 downto 0) := (others => '0'); signal JMP_REGISTER_ADDRESS : std_logic_vector(31 downto 0) := (others => '0'); signal JMP_CARRYOUT : std_logic; signal RD_TEMP : std_logic_vector(wrfLogNumRegsPerWin+1 downto 0); -- Write Address signal RD : std_logic_vector(wrfLogNumRegsPerWin+1 downto 0); -- Write Address signal RD0 : std_logic_vector(wrfLogNumRegsPerWin+1 downto 0); signal RS1 : std_logic_vector(wrfLogNumRegsPerWin+1 downto 0); -- Read Address 1 signal RS2 : std_logic_vector(wrfLogNumRegsPerWin+1 downto 0); -- Read Address 2 signal RS1_DATA : std_logic_vector(wrfNumBit-1 downto 0); -- Read data 1 signal RS1_DATA_ISZERO : std_logic; signal RS2_DATA : std_logic_vector(wrfNumBit-1 downto 0); -- Read data 2 signal RS1_EX : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0); -- Read Address 1 signal RS2_EX : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0); -- Read Address 1 signal RS1_DATA_EX : std_logic_vector(wrfNumBit-1 downto 0); signal RS2_DATA_EX : std_logic_vector(wrfNumBit-1 downto 0); signal RD_EX : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0); signal IMMEDIATE_EX : std_logic_vector(INSTR_SIZE-1 downto 0); -- STAGE THREE signal MUXALUOUT_CTR : std_logic; signal FWDJ0 : std_logic_vector(WORD_SIZE-1 downto 0); signal FWDJ : std_logic_vector(WORD_SIZE-1 downto 0); signal FWDA0 : std_logic_vector(WORD_SIZE-1 downto 0); signal FWDA1 : std_logic_vector(WORD_SIZE-1 downto 0); signal FWDB0 : std_logic_vector(WORD_SIZE-1 downto 0); signal FWDB1 : std_logic_vector(WORD_SIZE-1 downto 0); signal ALU_IN1 : std_logic_vector(WORD_SIZE-1 downto 0); signal ALU_IN2 : std_logic_vector(WORD_SIZE-1 downto 0); signal ALU_OUT : std_logic_vector(WORD_SIZE-1 downto 0); signal ALU_OUT_REAL : std_logic_vector(DATA_SIZE-1 downto 0); signal RS2_MEM : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0); -- Read Address 1 signal RS2_DATA_MEM : std_logic_vector(wrfNumBit-1 downto 0); signal ALU_OUT_MEM : std_logic_vector(WORD_SIZE-1 downto 0); signal RD_MEM : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0); signal IMMEDIATE_MEM : std_logic_vector(wrfNumBit-1 downto 0); -- STAGE FOUR signal MEM_ADDRESS : std_logic_vector(WORD_SIZE-1 downto 0); signal RS2_DATA_MEM1 : std_logic_vector(WORD_SIZE-1 downto 0); signal MEM_DATA : std_logic_vector(WORD_SIZE-1 downto 0); signal RD_WB : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0); signal MEM_DATA_WB : std_logic_vector(WORD_SIZE-1 downto 0); signal RD_DATA_WB : std_logic_vector(wrfNumBit-1 downto 0); signal REAL_ADDR_RS1 : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0); signal REAL_ADDR_RS2 : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0); signal REAL_ADDR_WR : std_logic_vector(wrfLogNumWindows+wrfLogNumRegsPerWin+1 downto 0); signal RS1_EQ_RD_EX : std_logic; signal RS1_EQ_RD_MEM : std_logic; signal RS1_EQ_RD_WB : std_logic; signal RS1_EX_EQ_RD_MEM : std_logic; signal RS1_EX_EQ_RD_WB : std_logic; signal RS2_EX_EQ_RD_MEM : std_logic; signal RS2_EX_EQ_RD_WB : std_logic; signal RS2_MEM_EQ_RD_WB : std_logic; begin ICACHE_ENABLE <= not JUMP; ICACHE_STALL_NOT <= not ICACHE_STALL; JMP_PREDICT <= '0'; -- Always predict not taken DCACHE_STALL_NOT <= not DCACHE_STALL; -- Control Unit CONTROL_UNIT : CU_UP port map (CLK, RST, IR, JMP_PREDICT, ICACHE_STALL, DCACHE_STALL, RS1_DATA_ISZERO, JMP_ADDRESS, IPC, PC, JUMP, LATCHER, MUXIMMEDIATE_CTR, MUXJMPADDRESS_CTR, MUXRD0_CTR, MUXRD_CTR, WRF_ENABLE, WRF_CALL, WRF_RET, WRF_RS1_ENABLE, WRF_RS2_ENABLE, MUXALUOUT_CTR, MUXALU_CTR, ALU_FUNC, MEMORY_ENABLE, MEMORY_RNOTW, WRF_RD_ENABLE, ID_STALL, EXE_STALL, MEM_STALL, WB_STALL); ICACHE : ROCACHE port map (CLK, RST, '1', PC, ICACHE_IR, ICACHE_STALL, IRAM_ISSUE, IRAM_ADDRESS, IRAM_DATA, IRAM_READY); MUX_IR : MUX generic map ( 32 ) port map( (others => '0'), ICACHE_IR, ICACHE_STALL_NOT, IR ); NPCEVAL: INCREMENTER generic map (32) port map (PC, IPC); PROPAGATE_NPC: REGISTER_FDL generic map (32) port map(IPC, LATCHER, CLK, RST, NPC); PROPAGATE_PC_IF_RF: REGISTER_FDL generic map (32) port map (IR, LATCHER, CLK, RST, IR_RF); -- -- STAGE TWO -- EXTENDER: SGNEXT generic map (16, 32) port map (IR_RF(15 downto 0), IMMEDIATE_IR); MUX_IMMEDIATE : MUX generic map ( DATA_SIZE ) port map ( IMMEDIATE_IR, NPC, MUXIMMEDIATE_CTR, IMMEDIATE ); JMP_ADDER: RCA_GENERIC generic map (32) port map(NPC, IMMEDIATE_IR, '0', JMP_RELATIVE_ADDRESS, JMP_CARRYOUT); JMP_REGISTER_ADDRESS <= FWDJ; MUX_JMP : MUX generic map ( DATA_SIZE ) port map ( JMP_RELATIVE_ADDRESS, JMP_REGISTER_ADDRESS, MUXJMPADDRESS_CTR, JMP_ADDRESS ); -- WRF RS1 <= IR_RF(25 downto 21); RS2 <= IR_RF(20 downto 16); RD_TEMP <= IR_RF(15 downto 11); WRF_RET_R31 <= WRF_RET and ( not or_reduce( RS1 xor "11111" ) ) and ( not ID_STALL ); WRF_CALL_NS <= WRF_CALL and ( not ID_STALL ); REGISTERFILE: WRF generic map (wrfNumBit, wrfNumWindows, wrfNumRegsPerWin, wrfLogNumWindows, wrfLogNumRegsPerWin) port map (CLK, RST, WRF_ENABLE, WRF_CALL_NS, WRF_RET_R31, WRF_RS1_ENABLE, WRF_RS2_ENABLE, WRF_RD_ENABLE, RS1, RS2, RD, RD_WB, REAL_ADDR_RS1, REAL_ADDR_RS2, REAL_ADDR_WR, RS1_DATA, RS2_DATA, RD_DATA_WB); MUX_RD: MUX generic map (5) port map (RD0, RD_TEMP, MUXRD_CTR, RD); MUX_RD0: MUX generic map (5) port map (RS2, "11111", MUXRD0_CTR, RD0); RS1_EQ_RD_EX <= not or_reduce( REAL_ADDR_RS1 xor RD_EX ); RS1_EQ_RD_MEM <= not or_reduce( REAL_ADDR_RS1 xor RD_MEM ); RS1_EQ_RD_WB <= not or_reduce( REAL_ADDR_RS1 xor RD_WB ); -- JUMPER forward logic MUX_FWDJ1 : MUX generic map ( WORD_SIZE ) port map ( FWDJ0, MEM_DATA, RS1_EQ_RD_MEM, FWDJ ); MUX_FWDJ0 : MUX generic map ( WORD_SIZE ) port map ( RS1_DATA, RD_DATA_WB, RS1_EQ_RD_WB, FWDJ0 ); -- Comparator RS1_DATA_ISZERO <= not or_reduce(FWDJ); -- PIPES PIPEREG_RD: REGISTER_FDL generic map (wrfLogNumWindows+wrfLogNumRegsPerWin+2) port map(REAL_ADDR_WR, LATCHER, CLK, RST, RD_EX); PROPAGATE_RS1_ID_EX: REGISTER_FDL generic map (wrfLogNumWindows+wrfLogNumRegsPerWin+2) port map (REAL_ADDR_RS1, LATCHER, CLK, RST, RS1_EX); PROPAGATE_RS2_ID_EX: REGISTER_FDL generic map (wrfLogNumWindows+wrfLogNumRegsPerWin+2) port map (REAL_ADDR_RS2, LATCHER, CLK, RST, RS2_EX); PIPEREG_RS1_DATA: REGISTER_FDL generic map (32) port map(RS1_DATA, LATCHER, CLK, RST, RS1_DATA_EX); PIPEREG_RS2_DATA: REGISTER_FDL generic map (32) port map(RS2_DATA, LATCHER, CLK, RST, RS2_DATA_EX); PIPEREG_IMMEDIATE: REGISTER_FDL generic map (32) port map(IMMEDIATE, LATCHER, CLK, RST, IMMEDIATE_EX); -- STAGE 3 RS1_EX_EQ_RD_MEM <= ( not or_reduce( RS1_EX xor RD_MEM )) and ( not MEM_STALL ); RS1_EX_EQ_RD_WB <= ( not or_reduce( RS1_EX xor RD_WB ) ) and ( not WB_STALL ); RS2_EX_EQ_RD_MEM <= ( not or_reduce( RS2_EX xor RD_MEM )) and ( not MEM_STALL ); RS2_EX_EQ_RD_WB <= ( not or_reduce( RS2_EX xor RD_WB ) ) and ( not WB_STALL ); -- ALU forward logic MUX_FWDA1 : MUX generic map ( WORD_SIZE ) port map ( FWDA0, MEM_DATA, RS1_EX_EQ_RD_MEM, FWDA1 ); MUX_FWDA0 : MUX generic map ( WORD_SIZE ) port map ( RS1_DATA_EX, MEM_DATA_WB, RS1_EX_EQ_RD_WB, FWDA0 ); MUX_FWDB1 : MUX generic map ( WORD_SIZE ) port map ( FWDB0, MEM_DATA, RS2_EX_EQ_RD_MEM, FWDB1 ); MUX_FWDB0 : MUX generic map ( WORD_SIZE ) port map ( RS2_DATA_EX, MEM_DATA_WB, RS2_EX_EQ_RD_WB, FWDB0 ); -- ALU input muxes MUX_ALU2 : MUX generic map ( WORD_SIZE ) port map ( IMMEDIATE_EX, FWDB1, MUXALU_CTR, ALU_IN2 ); ALU_IN1 <= FWDA1; -- ALU EXECUTER : ALU generic map ( WORD_SIZE ) port map ( ALU_FUNC, ALU_IN1, ALU_IN2, CLK, RST, ALU_OUT ); MUX_ALU_OUT : MUX generic map ( DATA_SIZE ) port map ( ALU_OUT, IMMEDIATE_EX, MUXALUOUT_CTR, ALU_OUT_REAL ); PIPEREG_IMMEDIATE_EX: REGISTER_FDL generic map (32) port map(IMMEDIATE_EX, LATCHER, CLK, RST, IMMEDIATE_MEM); PIPEREG_RD_EX: REGISTER_FDL generic map (wrfLogNumWindows+wrfLogNumRegsPerWin+2) port map(RD_EX, LATCHER, CLK, RST, RD_MEM); PIPEREG_RS2_DATA_EX: REGISTER_FDL generic map (32) port map(RS2_DATA_EX, LATCHER, CLK, RST, RS2_DATA_MEM); PIPEREG_RS2_EX: REGISTER_FDL generic map (wrfLogNumWindows+wrfLogNumRegsPerWin+2) port map(RS2_EX, LATCHER, CLK, RST, RS2_MEM); -- STAGE FOUR DCACHE : RWCACHE generic map ( wrfLogNumWindows+wrfLogNumRegsPerWin+2 ) port map ( CLK, RST, MEMORY_ENABLE, MEMORY_RNOTW, ALU_OUT_REAL, RS2_DATA_EX, RS2_EX, RD_MEM, MEM_STALL, LATCHER, MEM_DATA, DCACHE_STALL, DRAM_ISSUE, DRAM_READNOTWRITE, DRAM_ADDRESS, DRAM_DATA, DRAM_READY ); PIPEREG_RD_MEM: REGISTER_FDL generic map (wrfLogNumWindows+wrfLogNumRegsPerWin+2) port map(RD_MEM, '1', CLK, RST, RD_WB); PIPEREG_MEM_DATA: REGISTER_FDL generic map (32) port map(MEM_DATA, '1', CLK, RST, MEM_DATA_WB); -- STAGE FIVE RD_DATA_WB <= MEM_DATA_WB; -- Nothing -- GO! end structural; |
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY Instr_Mem1_synth IS PORT( CLK_IN : IN STD_LOGIC; RESET_IN : IN STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA ); END ENTITY; ARCHITECTURE Instr_Mem1_synth_ARCH OF Instr_Mem1_synth IS COMPONENT Instr_Mem1_exdes PORT ( --Inputs - Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); CLKA : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA: STD_LOGIC := '0'; SIGNAL RSTA: STD_LOGIC := '0'; SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA_R: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL CHECKER_EN : STD_LOGIC:='0'; SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); SIGNAL clk_in_i: STD_LOGIC; SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; SIGNAL ITER_R0 : STD_LOGIC := '0'; SIGNAL ITER_R1 : STD_LOGIC := '0'; SIGNAL ITER_R2 : STD_LOGIC := '0'; SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); BEGIN clk_in_i <= CLK_IN; CLKA <= clk_in_i; RSTA <= RESET_SYNC_R3 AFTER 50 ns; PROCESS(clk_in_i) BEGIN IF(RISING_EDGE(clk_in_i)) THEN RESET_SYNC_R1 <= RESET_IN; RESET_SYNC_R2 <= RESET_SYNC_R1; RESET_SYNC_R3 <= RESET_SYNC_R2; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ISSUE_FLAG_STATUS<= (OTHERS => '0'); ELSE ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; END IF; END IF; END PROCESS; STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; BMG_DATA_CHECKER_INST: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 16, READ_WIDTH => 16 ) PORT MAP ( CLK => CLKA, RST => RSTA, EN => CHECKER_EN_R, DATA_IN => DOUTA, STATUS => ISSUE_FLAG(0) ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RSTA='1') THEN CHECKER_EN_R <= '0'; ELSE CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; END IF; END IF; END PROCESS; BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN PORT MAP( CLK => clk_in_i, RST => RSTA, ADDRA => ADDRA, DINA => DINA, WEA => WEA, CHECK_DATA => CHECKER_EN ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STATUS(8) <= '0'; iter_r2 <= '0'; iter_r1 <= '0'; iter_r0 <= '0'; ELSE STATUS(8) <= iter_r2; iter_r2 <= iter_r1; iter_r1 <= iter_r0; iter_r0 <= STIMULUS_FLOW(8); END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STIMULUS_FLOW <= (OTHERS => '0'); ELSIF(WEA(0)='1') THEN STIMULUS_FLOW <= STIMULUS_FLOW+1; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN WEA_R <= (OTHERS=>'0') AFTER 50 ns; DINA_R <= (OTHERS=>'0') AFTER 50 ns; ELSE WEA_R <= WEA AFTER 50 ns; DINA_R <= DINA AFTER 50 ns; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; ELSE ADDRA_R <= ADDRA AFTER 50 ns; END IF; END IF; END PROCESS; BMG_PORT: Instr_Mem1_exdes PORT MAP ( --Port A WEA => WEA_R, ADDRA => ADDRA_R, DINA => DINA_R, DOUTA => DOUTA, CLKA => CLKA ); END ARCHITECTURE; |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity contact_discovery_AXILiteS_s_axi is generic ( C_S_AXI_ADDR_WIDTH : INTEGER := 11; C_S_AXI_DATA_WIDTH : INTEGER := 32); port ( -- axi4 lite slave signals ACLK :in STD_LOGIC; ARESET :in STD_LOGIC; ACLK_EN :in STD_LOGIC; AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0); AWVALID :in STD_LOGIC; AWREADY :out STD_LOGIC; WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0); WVALID :in STD_LOGIC; WREADY :out STD_LOGIC; BRESP :out STD_LOGIC_VECTOR(1 downto 0); BVALID :out STD_LOGIC; BREADY :in STD_LOGIC; ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0); ARVALID :in STD_LOGIC; ARREADY :out STD_LOGIC; RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0); RRESP :out STD_LOGIC_VECTOR(1 downto 0); RVALID :out STD_LOGIC; RREADY :in STD_LOGIC; interrupt :out STD_LOGIC; -- user signals ap_start :out STD_LOGIC; ap_done :in STD_LOGIC; ap_ready :in STD_LOGIC; ap_idle :in STD_LOGIC; operation :out STD_LOGIC_VECTOR(31 downto 0); operation_ap_vld :out STD_LOGIC; contact_in_address0 :in STD_LOGIC_VECTOR(5 downto 0); contact_in_ce0 :in STD_LOGIC; contact_in_q0 :out STD_LOGIC_VECTOR(7 downto 0); database_in_address0 :in STD_LOGIC_VECTOR(5 downto 0); database_in_ce0 :in STD_LOGIC; database_in_q0 :out STD_LOGIC_VECTOR(7 downto 0); matched_out_address0 :in STD_LOGIC_VECTOR(8 downto 0); matched_out_ce0 :in STD_LOGIC; matched_out_we0 :in STD_LOGIC; matched_out_d0 :in STD_LOGIC_VECTOR(0 downto 0); matched_finished :in STD_LOGIC_VECTOR(31 downto 0); error_out :in STD_LOGIC_VECTOR(31 downto 0); database_size_out :in STD_LOGIC_VECTOR(31 downto 0); contacts_size_out :in STD_LOGIC_VECTOR(31 downto 0) ); end entity contact_discovery_AXILiteS_s_axi; architecture behave of contact_discovery_AXILiteS_s_axi is type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states signal wstate : states := wrreset; signal rstate : states := rdreset; signal wnext, rnext: states; constant ADDR_AP_CTRL : INTEGER := 16#000#; constant ADDR_GIE : INTEGER := 16#004#; constant ADDR_IER : INTEGER := 16#008#; constant ADDR_ISR : INTEGER := 16#00c#; constant ADDR_OPERATION_DATA_0 : INTEGER := 16#010#; constant ADDR_OPERATION_CTRL : INTEGER := 16#014#; constant ADDR_MATCHED_FINISHED_DATA_0 : INTEGER := 16#400#; constant ADDR_MATCHED_FINISHED_CTRL : INTEGER := 16#404#; constant ADDR_ERROR_OUT_DATA_0 : INTEGER := 16#408#; constant ADDR_ERROR_OUT_CTRL : INTEGER := 16#40c#; constant ADDR_DATABASE_SIZE_OUT_DATA_0 : INTEGER := 16#410#; constant ADDR_DATABASE_SIZE_OUT_CTRL : INTEGER := 16#414#; constant ADDR_CONTACTS_SIZE_OUT_DATA_0 : INTEGER := 16#418#; constant ADDR_CONTACTS_SIZE_OUT_CTRL : INTEGER := 16#41c#; constant ADDR_CONTACT_IN_BASE : INTEGER := 16#040#; constant ADDR_CONTACT_IN_HIGH : INTEGER := 16#07f#; constant ADDR_DATABASE_IN_BASE : INTEGER := 16#080#; constant ADDR_DATABASE_IN_HIGH : INTEGER := 16#0bf#; constant ADDR_MATCHED_OUT_BASE : INTEGER := 16#200#; constant ADDR_MATCHED_OUT_HIGH : INTEGER := 16#3ff#; constant ADDR_BITS : INTEGER := 11; signal waddr : UNSIGNED(ADDR_BITS-1 downto 0); signal wmask : UNSIGNED(31 downto 0); signal aw_hs : STD_LOGIC; signal w_hs : STD_LOGIC; signal rdata_data : UNSIGNED(31 downto 0); signal ar_hs : STD_LOGIC; signal raddr : UNSIGNED(ADDR_BITS-1 downto 0); signal AWREADY_t : STD_LOGIC; signal WREADY_t : STD_LOGIC; signal ARREADY_t : STD_LOGIC; signal RVALID_t : STD_LOGIC; -- internal registers signal int_ap_idle : STD_LOGIC; signal int_ap_ready : STD_LOGIC; signal int_ap_done : STD_LOGIC := '0'; signal int_ap_start : STD_LOGIC := '0'; signal int_auto_restart : STD_LOGIC := '0'; signal int_gie : STD_LOGIC := '0'; signal int_ier : UNSIGNED(1 downto 0) := (others => '0'); signal int_isr : UNSIGNED(1 downto 0) := (others => '0'); signal int_operation : UNSIGNED(31 downto 0) := (others => '0'); signal int_operation_ap_vld : STD_LOGIC := '0'; signal int_matched_finished : UNSIGNED(31 downto 0) := (others => '0'); signal int_error_out : UNSIGNED(31 downto 0) := (others => '0'); signal int_database_size_out : UNSIGNED(31 downto 0) := (others => '0'); signal int_contacts_size_out : UNSIGNED(31 downto 0) := (others => '0'); -- memory signals signal int_contact_in_address0 : UNSIGNED(3 downto 0); signal int_contact_in_ce0 : STD_LOGIC; signal int_contact_in_we0 : STD_LOGIC; signal int_contact_in_be0 : UNSIGNED(3 downto 0); signal int_contact_in_d0 : UNSIGNED(31 downto 0); signal int_contact_in_q0 : UNSIGNED(31 downto 0); signal int_contact_in_address1 : UNSIGNED(3 downto 0); signal int_contact_in_ce1 : STD_LOGIC; signal int_contact_in_we1 : STD_LOGIC; signal int_contact_in_be1 : UNSIGNED(3 downto 0); signal int_contact_in_d1 : UNSIGNED(31 downto 0); signal int_contact_in_q1 : UNSIGNED(31 downto 0); signal int_contact_in_read : STD_LOGIC; signal int_contact_in_write : STD_LOGIC; signal int_contact_in_shift : UNSIGNED(1 downto 0); signal int_database_in_address0 : UNSIGNED(3 downto 0); signal int_database_in_ce0 : STD_LOGIC; signal int_database_in_we0 : STD_LOGIC; signal int_database_in_be0 : UNSIGNED(3 downto 0); signal int_database_in_d0 : UNSIGNED(31 downto 0); signal int_database_in_q0 : UNSIGNED(31 downto 0); signal int_database_in_address1 : UNSIGNED(3 downto 0); signal int_database_in_ce1 : STD_LOGIC; signal int_database_in_we1 : STD_LOGIC; signal int_database_in_be1 : UNSIGNED(3 downto 0); signal int_database_in_d1 : UNSIGNED(31 downto 0); signal int_database_in_q1 : UNSIGNED(31 downto 0); signal int_database_in_read : STD_LOGIC; signal int_database_in_write : STD_LOGIC; signal int_database_in_shift : UNSIGNED(1 downto 0); signal int_matched_out_address0 : UNSIGNED(6 downto 0); signal int_matched_out_ce0 : STD_LOGIC; signal int_matched_out_we0 : STD_LOGIC; signal int_matched_out_be0 : UNSIGNED(3 downto 0); signal int_matched_out_d0 : UNSIGNED(31 downto 0); signal int_matched_out_q0 : UNSIGNED(31 downto 0); signal int_matched_out_address1 : UNSIGNED(6 downto 0); signal int_matched_out_ce1 : STD_LOGIC; signal int_matched_out_we1 : STD_LOGIC; signal int_matched_out_be1 : UNSIGNED(3 downto 0); signal int_matched_out_d1 : UNSIGNED(31 downto 0); signal int_matched_out_q1 : UNSIGNED(31 downto 0); signal int_matched_out_read : STD_LOGIC; signal int_matched_out_write : STD_LOGIC; signal int_matched_out_shift : UNSIGNED(1 downto 0); component contact_discovery_AXILiteS_s_axi_ram is generic ( BYTES : INTEGER :=4; DEPTH : INTEGER :=256; AWIDTH : INTEGER :=8); port ( clk0 : in STD_LOGIC; address0: in UNSIGNED(AWIDTH-1 downto 0); ce0 : in STD_LOGIC; we0 : in STD_LOGIC; be0 : in UNSIGNED(BYTES-1 downto 0); d0 : in UNSIGNED(BYTES*8-1 downto 0); q0 : out UNSIGNED(BYTES*8-1 downto 0); clk1 : in STD_LOGIC; address1: in UNSIGNED(AWIDTH-1 downto 0); ce1 : in STD_LOGIC; we1 : in STD_LOGIC; be1 : in UNSIGNED(BYTES-1 downto 0); d1 : in UNSIGNED(BYTES*8-1 downto 0); q1 : out UNSIGNED(BYTES*8-1 downto 0)); end component contact_discovery_AXILiteS_s_axi_ram; function log2 (x : INTEGER) return INTEGER is variable n, m : INTEGER; begin n := 1; m := 2; while m < x loop n := n + 1; m := m * 2; end loop; return n; end function log2; begin int_contact_in : contact_discovery_AXILiteS_s_axi_ram generic map ( BYTES => 4, DEPTH => 16, AWIDTH => log2(16)) port map ( clk0 => ACLK, address0 => int_contact_in_address0, ce0 => int_contact_in_ce0, we0 => int_contact_in_we0, be0 => int_contact_in_be0, d0 => int_contact_in_d0, q0 => int_contact_in_q0, clk1 => ACLK, address1 => int_contact_in_address1, ce1 => int_contact_in_ce1, we1 => int_contact_in_we1, be1 => int_contact_in_be1, d1 => int_contact_in_d1, q1 => int_contact_in_q1); int_database_in : contact_discovery_AXILiteS_s_axi_ram generic map ( BYTES => 4, DEPTH => 16, AWIDTH => log2(16)) port map ( clk0 => ACLK, address0 => int_database_in_address0, ce0 => int_database_in_ce0, we0 => int_database_in_we0, be0 => int_database_in_be0, d0 => int_database_in_d0, q0 => int_database_in_q0, clk1 => ACLK, address1 => int_database_in_address1, ce1 => int_database_in_ce1, we1 => int_database_in_we1, be1 => int_database_in_be1, d1 => int_database_in_d1, q1 => int_database_in_q1); int_matched_out : contact_discovery_AXILiteS_s_axi_ram generic map ( BYTES => 4, DEPTH => 75, AWIDTH => log2(75)) port map ( clk0 => ACLK, address0 => int_matched_out_address0, ce0 => int_matched_out_ce0, we0 => int_matched_out_we0, be0 => int_matched_out_be0, d0 => int_matched_out_d0, q0 => int_matched_out_q0, clk1 => ACLK, address1 => int_matched_out_address1, ce1 => int_matched_out_ce1, we1 => int_matched_out_we1, be1 => int_matched_out_be1, d1 => int_matched_out_d1, q1 => int_matched_out_q1); AWREADY_t <= '1' when wstate = wridle else '0'; AWREADY <= AWREADY_t; WREADY_t <= '1' when wstate = wrdata else '0'; WREADY <= WREADY_t; BRESP <= "00"; -- OKAY BVALID <= '1' when wstate = wrresp else '0'; wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0)); aw_hs <= AWVALID and AWREADY_t; w_hs <= WVALID and WREADY_t; -- write FSM process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then wstate <= wrreset; elsif (ACLK_EN = '1') then wstate <= wnext; end if; end if; end process; process (wstate, AWVALID, WVALID, BREADY) begin case (wstate) is when wridle => if (AWVALID = '1') then wnext <= wrdata; else wnext <= wridle; end if; when wrdata => if (WVALID = '1') then wnext <= wrresp; else wnext <= wrdata; end if; when wrresp => if (BREADY = '1') then wnext <= wridle; else wnext <= wrresp; end if; when others => wnext <= wridle; end case; end process; waddr_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (aw_hs = '1') then waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)); end if; end if; end if; end process; ARREADY_t <= '1' when (rstate = rdidle) else '0'; ARREADY <= ARREADY_t; RDATA <= STD_LOGIC_VECTOR(rdata_data); RRESP <= "00"; -- OKAY RVALID_t <= '1' when (rstate = rddata) and (int_contact_in_read = '0') and (int_database_in_read = '0') and (int_matched_out_read = '0') else '0'; RVALID <= RVALID_t; ar_hs <= ARVALID and ARREADY_t; raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0)); -- read FSM process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then rstate <= rdreset; elsif (ACLK_EN = '1') then rstate <= rnext; end if; end if; end process; process (rstate, ARVALID, RREADY, RVALID_t) begin case (rstate) is when rdidle => if (ARVALID = '1') then rnext <= rddata; else rnext <= rdidle; end if; when rddata => if (RREADY = '1' and RVALID_t = '1') then rnext <= rdidle; else rnext <= rddata; end if; when others => rnext <= rdidle; end case; end process; rdata_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (ar_hs = '1') then case (TO_INTEGER(raddr)) is when ADDR_AP_CTRL => rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0'); when ADDR_GIE => rdata_data <= (0 => int_gie, others => '0'); when ADDR_IER => rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0'); when ADDR_ISR => rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0'); when ADDR_OPERATION_DATA_0 => rdata_data <= RESIZE(int_operation(31 downto 0), 32); when ADDR_OPERATION_CTRL => rdata_data <= (0 => int_operation_ap_vld, others => '0'); when ADDR_MATCHED_FINISHED_DATA_0 => rdata_data <= RESIZE(int_matched_finished(31 downto 0), 32); when ADDR_ERROR_OUT_DATA_0 => rdata_data <= RESIZE(int_error_out(31 downto 0), 32); when ADDR_DATABASE_SIZE_OUT_DATA_0 => rdata_data <= RESIZE(int_database_size_out(31 downto 0), 32); when ADDR_CONTACTS_SIZE_OUT_DATA_0 => rdata_data <= RESIZE(int_contacts_size_out(31 downto 0), 32); when others => rdata_data <= (others => '0'); end case; elsif (int_contact_in_read = '1') then rdata_data <= int_contact_in_q1; elsif (int_database_in_read = '1') then rdata_data <= int_database_in_q1; elsif (int_matched_out_read = '1') then rdata_data <= int_matched_out_q1; end if; end if; end if; end process; interrupt <= int_gie and (int_isr(0) or int_isr(1)); ap_start <= int_ap_start; int_ap_idle <= ap_idle; int_ap_ready <= ap_ready; operation <= STD_LOGIC_VECTOR(int_operation); operation_ap_vld <= int_operation_ap_vld; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_start <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then int_ap_start <= '1'; elsif (int_ap_ready = '1') then int_ap_start <= int_auto_restart; -- clear on handshake/auto restart end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_done <= '0'; elsif (ACLK_EN = '1') then if (ap_done = '1') then int_ap_done <= '1'; elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then int_ap_done <= '0'; -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_auto_restart <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then int_auto_restart <= WDATA(7); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_gie <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then int_gie <= WDATA(0); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ier <= "00"; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then int_ier <= UNSIGNED(WDATA(1 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_isr(0) <= '0'; elsif (ACLK_EN = '1') then if (int_ier(0) = '1' and ap_done = '1') then int_isr(0) <= '1'; elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_isr(1) <= '0'; elsif (ACLK_EN = '1') then if (int_ier(1) = '1' and ap_ready = '1') then int_isr(1) <= '1'; elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_OPERATION_DATA_0) then int_operation(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_operation(31 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_operation_ap_vld <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_OPERATION_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then int_operation_ap_vld <= '1'; else int_operation_ap_vld <= '0'; -- self clear end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_matched_finished <= (others => '0'); elsif (ACLK_EN = '1') then if (true) then int_matched_finished <= UNSIGNED(matched_finished); -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_error_out <= (others => '0'); elsif (ACLK_EN = '1') then if (true) then int_error_out <= UNSIGNED(error_out); -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_database_size_out <= (others => '0'); elsif (ACLK_EN = '1') then if (true) then int_database_size_out <= UNSIGNED(database_size_out); -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_contacts_size_out <= (others => '0'); elsif (ACLK_EN = '1') then if (true) then int_contacts_size_out <= UNSIGNED(contacts_size_out); -- clear on read end if; end if; end if; end process; -- contact_in int_contact_in_address0 <= SHIFT_RIGHT(UNSIGNED(contact_in_address0), 2)(3 downto 0); int_contact_in_ce0 <= contact_in_ce0; int_contact_in_we0 <= '0'; int_contact_in_be0 <= (others => '0'); int_contact_in_d0 <= (others => '0'); contact_in_q0 <= STD_LOGIC_VECTOR(SHIFT_RIGHT(int_contact_in_q0, TO_INTEGER(int_contact_in_shift) * 8)(7 downto 0)); int_contact_in_address1 <= raddr(5 downto 2) when ar_hs = '1' else waddr(5 downto 2); int_contact_in_ce1 <= '1' when ar_hs = '1' or (int_contact_in_write = '1' and WVALID = '1') else '0'; int_contact_in_we1 <= '1' when int_contact_in_write = '1' and WVALID = '1' else '0'; int_contact_in_be1 <= UNSIGNED(WSTRB); int_contact_in_d1 <= UNSIGNED(WDATA); -- database_in int_database_in_address0 <= SHIFT_RIGHT(UNSIGNED(database_in_address0), 2)(3 downto 0); int_database_in_ce0 <= database_in_ce0; int_database_in_we0 <= '0'; int_database_in_be0 <= (others => '0'); int_database_in_d0 <= (others => '0'); database_in_q0 <= STD_LOGIC_VECTOR(SHIFT_RIGHT(int_database_in_q0, TO_INTEGER(int_database_in_shift) * 8)(7 downto 0)); int_database_in_address1 <= raddr(5 downto 2) when ar_hs = '1' else waddr(5 downto 2); int_database_in_ce1 <= '1' when ar_hs = '1' or (int_database_in_write = '1' and WVALID = '1') else '0'; int_database_in_we1 <= '1' when int_database_in_write = '1' and WVALID = '1' else '0'; int_database_in_be1 <= UNSIGNED(WSTRB); int_database_in_d1 <= UNSIGNED(WDATA); -- matched_out int_matched_out_address0 <= SHIFT_RIGHT(UNSIGNED(matched_out_address0), 2)(6 downto 0); int_matched_out_ce0 <= matched_out_ce0; int_matched_out_we0 <= matched_out_we0; int_matched_out_be0 <= SHIFT_LEFT(TO_UNSIGNED(1, 4), TO_INTEGER(UNSIGNED(matched_out_address0(1 downto 0)))); int_matched_out_d0 <= UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)) & UNSIGNED(RESIZE(UNSIGNED(matched_out_d0), 8)); int_matched_out_address1 <= raddr(8 downto 2) when ar_hs = '1' else waddr(8 downto 2); int_matched_out_ce1 <= '1' when ar_hs = '1' or (int_matched_out_write = '1' and WVALID = '1') else '0'; int_matched_out_we1 <= '1' when int_matched_out_write = '1' and WVALID = '1' else '0'; int_matched_out_be1 <= UNSIGNED(WSTRB); int_matched_out_d1 <= UNSIGNED(WDATA); process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_contact_in_read <= '0'; elsif (ACLK_EN = '1') then if (ar_hs = '1' and raddr >= ADDR_CONTACT_IN_BASE and raddr <= ADDR_CONTACT_IN_HIGH) then int_contact_in_read <= '1'; else int_contact_in_read <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_contact_in_write <= '0'; elsif (ACLK_EN = '1') then if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_CONTACT_IN_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_CONTACT_IN_HIGH) then int_contact_in_write <= '1'; elsif (WVALID = '1') then int_contact_in_write <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (contact_in_ce0 = '1') then int_contact_in_shift <= UNSIGNED(contact_in_address0(1 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_database_in_read <= '0'; elsif (ACLK_EN = '1') then if (ar_hs = '1' and raddr >= ADDR_DATABASE_IN_BASE and raddr <= ADDR_DATABASE_IN_HIGH) then int_database_in_read <= '1'; else int_database_in_read <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_database_in_write <= '0'; elsif (ACLK_EN = '1') then if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_DATABASE_IN_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_DATABASE_IN_HIGH) then int_database_in_write <= '1'; elsif (WVALID = '1') then int_database_in_write <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (database_in_ce0 = '1') then int_database_in_shift <= UNSIGNED(database_in_address0(1 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_matched_out_read <= '0'; elsif (ACLK_EN = '1') then if (ar_hs = '1' and raddr >= ADDR_MATCHED_OUT_BASE and raddr <= ADDR_MATCHED_OUT_HIGH) then int_matched_out_read <= '1'; else int_matched_out_read <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_matched_out_write <= '0'; elsif (ACLK_EN = '1') then if (aw_hs = '1' and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) >= ADDR_MATCHED_OUT_BASE and UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)) <= ADDR_MATCHED_OUT_HIGH) then int_matched_out_write <= '1'; elsif (WVALID = '1') then int_matched_out_write <= '0'; end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (matched_out_ce0 = '1') then int_matched_out_shift <= UNSIGNED(matched_out_address0(1 downto 0)); end if; end if; end if; end process; end architecture behave; library IEEE; USE IEEE.std_logic_1164.all; USE IEEE.numeric_std.all; entity contact_discovery_AXILiteS_s_axi_ram is generic ( BYTES : INTEGER :=4; DEPTH : INTEGER :=256; AWIDTH : INTEGER :=8); port ( clk0 : in STD_LOGIC; address0: in UNSIGNED(AWIDTH-1 downto 0); ce0 : in STD_LOGIC; we0 : in STD_LOGIC; be0 : in UNSIGNED(BYTES-1 downto 0); d0 : in UNSIGNED(BYTES*8-1 downto 0); q0 : out UNSIGNED(BYTES*8-1 downto 0); clk1 : in STD_LOGIC; address1: in UNSIGNED(AWIDTH-1 downto 0); ce1 : in STD_LOGIC; we1 : in STD_LOGIC; be1 : in UNSIGNED(BYTES-1 downto 0); d1 : in UNSIGNED(BYTES*8-1 downto 0); q1 : out UNSIGNED(BYTES*8-1 downto 0)); end entity contact_discovery_AXILiteS_s_axi_ram; architecture behave of contact_discovery_AXILiteS_s_axi_ram is signal address0_tmp : UNSIGNED(AWIDTH-1 downto 0); signal address1_tmp : UNSIGNED(AWIDTH-1 downto 0); type RAM_T is array (0 to DEPTH - 1) of UNSIGNED(BYTES*8 - 1 downto 0); shared variable mem : RAM_T := (others => (others => '0')); begin process (address0) begin address0_tmp <= address0; --synthesis translate_off if (address0 > DEPTH-1) then address0_tmp <= (others => '0'); else address0_tmp <= address0; end if; --synthesis translate_on end process; process (address1) begin address1_tmp <= address1; --synthesis translate_off if (address1 > DEPTH-1) then address1_tmp <= (others => '0'); else address1_tmp <= address1; end if; --synthesis translate_on end process; --read port 0 process (clk0) begin if (clk0'event and clk0 = '1') then if (ce0 = '1') then q0 <= mem(to_integer(address0_tmp)); end if; end if; end process; --read port 1 process (clk1) begin if (clk1'event and clk1 = '1') then if (ce1 = '1') then q1 <= mem(to_integer(address1_tmp)); end if; end if; end process; gen_write : for i in 0 to BYTES - 1 generate begin --write port 0 process (clk0) begin if (clk0'event and clk0 = '1') then if (ce0 = '1' and we0 = '1' and be0(i) = '1') then mem(to_integer(address0_tmp))(8*i+7 downto 8*i) := d0(8*i+7 downto 8*i); end if; end if; end process; --write port 1 process (clk1) begin if (clk1'event and clk1 = '1') then if (ce1 = '1' and we1 = '1' and be1(i) = '1') then mem(to_integer(address1_tmp))(8*i+7 downto 8*i) := d1(8*i+7 downto 8*i); end if; end if; end process; end generate; end architecture behave; |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY proc_sys_reset_v5_0; USE proc_sys_reset_v5_0.proc_sys_reset; ENTITY system_rst_processing_system7_0_100M_0 IS PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END system_rst_processing_system7_0_100M_0; ARCHITECTURE system_rst_processing_system7_0_100M_0_arch OF system_rst_processing_system7_0_100M_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes"; COMPONENT proc_sys_reset IS GENERIC ( C_FAMILY : STRING; C_EXT_RST_WIDTH : INTEGER; C_AUX_RST_WIDTH : INTEGER; C_EXT_RESET_HIGH : STD_LOGIC; C_AUX_RESET_HIGH : STD_LOGIC; C_NUM_BUS_RST : INTEGER; C_NUM_PERP_RST : INTEGER; C_NUM_INTERCONNECT_ARESETN : INTEGER; C_NUM_PERP_ARESETN : INTEGER ); PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT proc_sys_reset; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; BEGIN U0 : proc_sys_reset GENERIC MAP ( C_FAMILY => "zynq", C_EXT_RST_WIDTH => 4, C_AUX_RST_WIDTH => 4, C_EXT_RESET_HIGH => '0', C_AUX_RESET_HIGH => '0', C_NUM_BUS_RST => 1, C_NUM_PERP_RST => 1, C_NUM_INTERCONNECT_ARESETN => 1, C_NUM_PERP_ARESETN => 1 ) PORT MAP ( slowest_sync_clk => slowest_sync_clk, ext_reset_in => ext_reset_in, aux_reset_in => aux_reset_in, mb_debug_sys_rst => mb_debug_sys_rst, dcm_locked => dcm_locked, mb_reset => mb_reset, bus_struct_reset => bus_struct_reset, peripheral_reset => peripheral_reset, interconnect_aresetn => interconnect_aresetn, peripheral_aresetn => peripheral_aresetn ); END system_rst_processing_system7_0_100M_0_arch; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity vga_display is Port ( char : out STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); char_we : out STD_LOGIC := '0'; clk : in STD_LOGIC; ram_enable : out STD_LOGIC := '1'; ram_output : in STD_LOGIC_VECTOR(7 downto 0); start : in STD_LOGIC; reset : in STD_LOGIC); end vga_display; architecture Behavioral of vga_display is type state_type is (IDLE, GET_DATA, LATCH_DATA, START_RISING_EDGE, KEEP_RISING_EDGE, START_FALLING_EDGE); signal state, next_state : state_type; signal busy_in : STD_LOGIC := '0'; begin process (clk) begin if rising_edge(clk) then if reset='1' then busy_in <= '0'; elsif start = '1' then busy_in <= '1'; elsif state = IDLE then busy_in <= '0'; else busy_in <= busy_in; end if; end if; end process; SYNC_PROC: process (clk) begin if rising_edge(clk) then if (reset = '1') then state <= IDLE; else state <= next_state; end if; end if; end process; OUTPUT_DECODE: process (state, ram_output) begin if state = IDLE then char <= (others=>'0'); char_we <= '0'; ram_enable <= '0'; elsif state = GET_DATA then char <= (others=>'0'); char_we <= '0'; ram_enable <= '1'; elsif state = START_RISING_EDGE then ram_enable <= '0'; char_we <= '1'; case (ram_output(7 downto 4)) is when "0000" => char <= x"30"; when "0001" => char <= x"31"; when "0010" => char <= x"32"; when "0011" => char <= x"33"; when "0100" => char <= x"34"; when "0101" => char <= x"35"; when "0110" => char <= x"36"; when "0111" => char <= x"37"; when "1000" => char <= x"38"; when "1001" => char <= x"39"; when "1010" => char <= x"61"; when "1011" => char <= x"62"; when "1100" => char <= x"63"; when "1101" => char <= x"64"; when "1110" => char <= x"65"; when "1111" => char <= x"66"; when others => char <= x"00"; end case; elsif state = KEEP_RISING_EDGE then ram_enable <= '0'; char_we <= '1'; case (ram_output(3 downto 0)) is when "0000" => char <= x"30"; when "0001" => char <= x"31"; when "0010" => char <= x"32"; when "0011" => char <= x"33"; when "0100" => char <= x"34"; when "0101" => char <= x"35"; when "0110" => char <= x"36"; when "0111" => char <= x"37"; when "1000" => char <= x"38"; when "1001" => char <= x"39"; when "1010" => char <= x"61"; when "1011" => char <= x"62"; when "1100" => char <= x"63"; when "1101" => char <= x"64"; when "1110" => char <= x"65"; when "1111" => char <= x"66"; when others => char <= x"00"; end case; elsif state = START_FALLING_EDGE then ram_enable <= '0'; char_we <= '0'; char <= x"00"; end if; end process; NEXT_STATE_DECODE: process (state, start, clk) begin next_state <= state; case (state) is when IDLE => if start = '1' then next_state <= GET_DATA; end if; when GET_DATA => next_state <= START_RISING_EDGE; when START_RISING_EDGE => next_state <= KEEP_RISING_EDGE; when KEEP_RISING_EDGE => next_state <= START_FALLING_EDGE; when START_FALLING_EDGE => next_state <= IDLE; when others => next_state <= IDLE; end case; end process; end Behavioral; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity rs232_tx is port ( clk : in std_logic; reset : in std_logic; rdy : out std_logic; load : in std_logic; data_i : in std_logic_vector(7 downto 0); txd : out std_logic); end rs232_tx; architecture demo of rs232_tx is signal counter : integer; signal data : std_logic_vector(10 downto 0); signal ctr_bit : std_logic_vector(3 downto 0); signal tx : std_logic; begin process(clk) begin if clk'event and clk='1' then if reset='1' then data <= "10111111111"; tx <= '0'; ctr_bit <= "0000"; counter <= 0; elsif load='1' and tx='0' then data <= "1"&data_i&"01"; tx <= '1'; else if tx='1' then if counter = 5200 then counter <= 0; data(9 downto 0) <= data(10 downto 1); data(10) <= '1'; if ctr_bit = "1010" then tx <= '0'; ctr_bit <= "0000"; else ctr_bit <= ctr_bit + 1; end if; else counter <= counter + 1; end if; end if; end if; end if; end process; rdy <= not tx; txd <= data(0); end demo; |
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY UNISIM; USE UNISIM.VCOMPONENTS.ALL; ENTITY Instr_Mem_prod IS PORT ( --Port A CLKA : IN STD_LOGIC; RSTA : IN STD_LOGIC; --opt port ENA : IN STD_LOGIC; --optional port REGCEA : IN STD_LOGIC; --optional port WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --Port B CLKB : IN STD_LOGIC; RSTB : IN STD_LOGIC; --opt port ENB : IN STD_LOGIC; --optional port REGCEB : IN STD_LOGIC; --optional port WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0); DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --ECC INJECTSBITERR : IN STD_LOGIC; --optional port INJECTDBITERR : IN STD_LOGIC; --optional port SBITERR : OUT STD_LOGIC; --optional port DBITERR : OUT STD_LOGIC; --optional port RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port -- AXI BMG Input and Output Port Declarations -- AXI Global Signals S_ACLK : IN STD_LOGIC; S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_AWVALID : IN STD_LOGIC; S_AXI_AWREADY : OUT STD_LOGIC; S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); S_AXI_WLAST : IN STD_LOGIC; S_AXI_WVALID : IN STD_LOGIC; S_AXI_WREADY : OUT STD_LOGIC; S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_BVALID : OUT STD_LOGIC; S_AXI_BREADY : IN STD_LOGIC; -- AXI Full/Lite Slave Read (Write side) S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_ARVALID : IN STD_LOGIC; S_AXI_ARREADY : OUT STD_LOGIC; S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_RLAST : OUT STD_LOGIC; S_AXI_RVALID : OUT STD_LOGIC; S_AXI_RREADY : IN STD_LOGIC; -- AXI Full/Lite Sideband Signals S_AXI_INJECTSBITERR : IN STD_LOGIC; S_AXI_INJECTDBITERR : IN STD_LOGIC; S_AXI_SBITERR : OUT STD_LOGIC; S_AXI_DBITERR : OUT STD_LOGIC; S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); S_ARESETN : IN STD_LOGIC ); END Instr_Mem_prod; ARCHITECTURE xilinx OF Instr_Mem_prod IS COMPONENT Instr_Mem_exdes IS PORT ( --Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); CLKA : IN STD_LOGIC ); END COMPONENT; BEGIN bmg0 : Instr_Mem_exdes PORT MAP ( --Port A WEA => WEA, ADDRA => ADDRA, DINA => DINA, DOUTA => DOUTA, CLKA => CLKA ); END xilinx; |
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library ieee; use ieee.std_logic_1164.all; use std.textio.all; use ieee.math_real.all; use work.types_pkg.all; use work.adaptations_pkg.all; package string_methods_pkg is -- Need a low level "alert" in the form of a simple assertion (as string handling may also fail) procedure bitvis_assert( val : boolean; severeness : severity_level; msg : string; scope : string ); function justify( val : string; justified : side; width : natural; format_spaces : t_format_spaces; truncate : t_truncate_string ) return string; -- DEPRECATED. -- Function will be removed in future versions of UVVM-Util function justify( val : string; width : natural := 0; justified : side := RIGHT; format: t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio ) return string; function justify( val : string; justified : t_justify_center; width : natural; format_spaces : t_format_spaces; truncate : t_truncate_string ) return string; function pos_of_leftmost( target : character; vector : string; result_if_not_found : natural := 1 ) return natural; function pos_of_rightmost( target : character; vector : string; result_if_not_found : natural := 1 ) return natural; function pos_of_leftmost_non_zero( vector : string; result_if_not_found : natural := 1 ) return natural; function pos_of_rightmost_non_whitespace( vector : string; result_if_not_found : natural := 1 ) return natural; function valid_length( -- of string excluding trailing NULs vector : string ) return natural; function get_string_between_delimiters( val : string; delim_left : character; delim_right: character; start_from : SIDE; -- search from left or right (Only RIGHT implemented so far) occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence ) return string; function get_procedure_name_from_instance_name( val : string ) return string; function get_process_name_from_instance_name( val : string ) return string; function get_entity_name_from_instance_name( val : string ) return string; function return_string_if_true( val : string; return_val : boolean ) return string; function return_string1_if_true_otherwise_string2( val1 : string; val2 : string; return_val : boolean ) return string; function to_upper( val : string ) return string; function fill_string( val : character; width : natural ) return string; function pad_string( val : string; char : character; width : natural; side : side := LEFT ) return string; function replace_backslash_n_with_lf( source : string ) return string; function remove_initial_chars( source : string; num : natural ) return string; function wrap_lines( constant text_string : string; constant alignment_pos1 : natural; -- Line position of first aligned character in line 1 constant alignment_pos2 : natural; -- Line position of first aligned character in line 2, etc... constant line_width : natural ) return string; procedure wrap_lines( variable text_lines : inout line; constant alignment_pos1 : natural; -- Line position prior to first aligned character (incl. Prefix) constant alignment_pos2 : natural; constant line_width : natural ); procedure prefix_lines( variable text_lines : inout line; constant prefix : string := C_LOG_PREFIX ); function replace( val : string; target_char : character; exchange_char : character ) return string; procedure replace( variable text_line : inout line; target_char : character; exchange_char : character ); --======================================================== -- Handle missing overloads from 'standard_additions' --======================================================== function to_string( val : boolean; width : natural; justified : side; format_spaces : t_format_spaces; truncate : t_truncate_string := DISALLOW_TRUNCATE ) return string; function to_string( val : integer; width : natural; justified : side; format_spaces : t_format_spaces; truncate : t_truncate_string := DISALLOW_TRUNCATE ) return string; -- This function has been deprecated and will be removed in the next major release -- DEPRECATED function to_string( val : boolean; width : natural; justified : side := right; format: t_format_string := AS_IS ) return string; -- This function has been deprecated and will be removed in the next major release -- DEPRECATED function to_string( val : integer; width : natural; justified : side := right; format : t_format_string := AS_IS ) return string; function to_string( val : std_logic_vector; radix : t_radix; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string; function to_string( val : unsigned; radix : t_radix; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string; function to_string( val : signed; radix : t_radix; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string; function to_string( val : t_byte_array; radix : t_radix := HEX_BIN_IF_INVALID; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string; function to_string( val : t_slv_array; radix : t_radix := HEX_BIN_IF_INVALID; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string; function to_string( val : t_signed_array; radix : t_radix := HEX_BIN_IF_INVALID; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string; function to_string( val : t_unsigned_array; radix : t_radix := HEX_BIN_IF_INVALID; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string; --======================================================== -- Handle types defined at lower levels --======================================================== function to_string( val : t_alert_level; width : natural; justified : side := right ) return string; function to_string( val : t_msg_id; width : natural; justified : side := right ) return string; function to_string( val : t_attention; width : natural; justified : side := right ) return string; procedure to_string( val : t_alert_attention_counters; order : t_order := FINAL ); function ascii_to_char( ascii_pos : integer range 0 to 255; ascii_allow : t_ascii_allow := ALLOW_ALL ) return character; function char_to_ascii( char : character ) return integer; -- return string with only valid ascii characters function to_string( val : string ) return string; function add_msg_delimiter( msg : string ) return string; end package string_methods_pkg; package body string_methods_pkg is -- Need a low level "alert" in the form of a simple assertion (as string handling may also fail) procedure bitvis_assert( val : boolean; severeness : severity_level; msg : string; scope : string ) is begin assert val report LF & C_LOG_PREFIX & " *** " & to_string(severeness) & "*** caused by Bitvis Util > string handling > " & scope & LF & C_LOG_PREFIX & " " & add_msg_delimiter(msg) & LF severity severeness; end; function to_upper( val : string ) return string is variable v_result : string (val'range) := val; variable char : character; begin for i in val'range loop -- NOTE: Illegal characters are allowed and will pass through (check Mentor's std_developers_kit) if ( v_result(i) >= 'a' and v_result(i) <= 'z') then v_result(i) := character'val( character'pos(v_result(i)) - character'pos('a') + character'pos('A') ); end if; end loop; return v_result; end to_upper; function fill_string( val : character; width : natural ) return string is variable v_result : string (1 to maximum(1, width)); begin if (width = 0) then return ""; else for i in 1 to width loop v_result(i) := val; end loop; end if; return v_result; end fill_string; function pad_string( val : string; char : character; width : natural; side : side := LEFT ) return string is variable v_result : string (1 to maximum(1, width)); begin if (width = 0) then return ""; elsif (width <= val'length) then return val(1 to width); else v_result := (others => char); if side = LEFT then v_result(1 to val'length) := val; else v_result(v_result'length-val'length+1 to v_result'length) := val; end if; end if; return v_result; end pad_string; -- This procedure has been deprecated, and will be removed in the near future. function justify( val : string; width : natural := 0; justified : side := RIGHT; format : t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio ) return string is constant val_length : natural := val'length; variable result : string(1 to width) := (others => ' '); begin -- return val if width is too small if val_length >= width then if (format = TRUNCATE) then return val(1 to width); else return val; end if; end if; if justified = left then result(1 to val_length) := val; elsif justified = right then result(width - val_length + 1 to width) := val; end if; return result; end function; function justify( val : string; justified : side; width : natural; format_spaces : t_format_spaces; truncate : t_truncate_string ) return string is variable v_val_length : natural := val'length; variable v_formatted_val : string (1 to val'length); variable v_num_leading_space : natural := 0; variable v_result : string(1 to width) := (others => ' '); begin -- Remove leading space if format_spaces is SKIP_LEADING_SPACE if format_spaces = SKIP_LEADING_SPACE then -- Find how many leading spaces there are while( (val(v_num_leading_space+1) = ' ') and (v_num_leading_space < v_val_length)) loop v_num_leading_space := v_num_leading_space + 1; end loop; -- Remove leading space if any v_formatted_val := remove_initial_chars(val,v_num_leading_space); v_val_length := v_formatted_val'length; else v_formatted_val := val; end if; -- Truncate and return if the string is wider that allowed if v_val_length >= width then if (truncate = ALLOW_TRUNCATE) then return v_formatted_val(1 to width); else return v_formatted_val; end if; end if; -- Justify if string is within the width specifications if justified = left then v_result(1 to v_val_length) := v_formatted_val; elsif justified = right then v_result(width - v_val_length + 1 to width) := v_formatted_val; end if; return v_result; end function; function justify( val : string; justified : t_justify_center; width : natural; format_spaces : t_format_spaces; truncate : t_truncate_string ) return string is variable v_val_length : natural := val'length; variable v_start_pos : natural; variable v_formatted_val : string (1 to val'length); variable v_num_leading_space : natural := 0; variable v_result : string(1 to width) := (others => ' '); begin -- Remove leading space if format_spaces is SKIP_LEADING_SPACE if format_spaces = SKIP_LEADING_SPACE then -- Find how many leading spaces there are while( (val(v_num_leading_space+1) = ' ') and (v_num_leading_space < v_val_length)) loop v_num_leading_space := v_num_leading_space + 1; end loop; -- Remove leading space if any v_formatted_val := remove_initial_chars(val,v_num_leading_space); v_val_length := v_formatted_val'length; else v_formatted_val := val; end if; -- Truncate and return if the string is wider that allowed if v_val_length >= width then if (truncate = ALLOW_TRUNCATE) then return v_formatted_val(1 to width); else return v_formatted_val; end if; end if; -- Justify if string is within the width specifications v_start_pos := natural(ceil((real(width)-real(v_val_length))/real(2))) + 1; v_result(v_start_pos to v_start_pos + v_val_length-1) := v_formatted_val; return v_result; end function; function pos_of_leftmost( target : character; vector : string; result_if_not_found : natural := 1 ) return natural is alias a_vector : string(1 to vector'length) is vector; begin bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost()"); bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_leftmost()"); for i in a_vector'left to a_vector'right loop if (a_vector(i) = target) then return i; end if; end loop; return result_if_not_found; end; function pos_of_rightmost( target : character; vector : string; result_if_not_found : natural := 1 ) return natural is alias a_vector : string(1 to vector'length) is vector; begin bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_rightmost()"); bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_rightmost()"); for i in a_vector'right downto a_vector'left loop if (a_vector(i) = target) then return i; end if; end loop; return result_if_not_found; end; function pos_of_leftmost_non_zero( vector : string; result_if_not_found : natural := 1 ) return natural is alias a_vector : string(1 to vector'length) is vector; begin bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost_non_zero()"); for i in a_vector'left to a_vector'right loop if (a_vector(i) /= '0' and a_vector(i) /= ' ') then return i; end if; end loop; return result_if_not_found; end; function pos_of_rightmost_non_whitespace( vector : string; result_if_not_found : natural := 1 ) return natural is alias a_vector : string(1 to vector'length) is vector; begin bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_rightmost_non_whitespace()"); for i in a_vector'right downto a_vector'left loop if a_vector(i) /= ' ' then return i; end if; end loop; return result_if_not_found; end; function valid_length( -- of string excluding trailing NULs vector : string ) return natural is begin return pos_of_leftmost(NUL, vector, vector'length) - 1; end; function string_contains_char( val : string; char : character ) return boolean is alias a_val : string(1 to val'length) is val; begin if (val'length = 0) then return false; else for i in val'left to val'right loop if (val(i) = char) then return true; end if; end loop; -- falls through only if not found return false; end if; end; -- get_*_name -- Note: for sub-programs the following is given: library:package:procedure:object -- Note: for design hierachy the following is given: complete hierarchy from sim-object down to process object -- e.g. 'sbi_tb:i_test_harness:i2_sbi_vvc:p_constructor:v_msg' -- Attribute instance_name also gives [procedure signature] or @entity-name(architecture name) function get_string_between_delimiters( val : string; delim_left : character; delim_right: character; start_from : SIDE; -- search from left or right (Only RIGHT implemented so far) occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence ) return string is variable v_left : natural := 0; variable v_right : natural := 0; variable v_start : natural := val'length; variable v_occurrence : natural := 0; alias a_val : string(1 to val'length) is val; begin bitvis_assert(a_val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_string_between_delimiters()"); bitvis_assert(start_from = RIGHT, FAILURE, "Only search from RIGHT is implemented so far", "get_string_between_delimiters()"); loop v_left := 0; -- default v_right := pos_of_rightmost(delim_right, a_val(1 to v_start), 0); if v_right > 0 then -- i.e. found L1: for i in v_right-1 downto 1 loop -- searching backwards for delimeter if (a_val(i) = delim_left) then v_left := i; v_start := i; -- Previous end delimeter could also be a start delimeter for next section v_occurrence := v_occurrence + 1; exit L1; end if; end loop; -- searching backwards end if; if v_right = 0 or v_left = 0 then return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between) end if; if v_occurrence = occurrence then -- Match if (v_right - v_left) < 2 then return ""; -- no chars in between delimeters else return a_val(v_left+1 to v_right-1); end if; end if; if v_start < 3 then return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between) end if; end loop; -- Will continue until match or not found end; function get_procedure_name_from_instance_name( val : string ) return string is variable v_line : line; variable v_msg_line : line; begin bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_procedure_name_from_instance_name()"); write(v_line, get_string_between_delimiters(val, ':', '[', RIGHT)); if (string_contains_char(val, '@')) then write(v_msg_line, string'("Must be called with <sub-program object>'instance_name")); else write(v_msg_line, string'(" ")); end if; bitvis_assert(v_line'length > 0, ERROR, "No procedure name found. " & v_msg_line.all, "get_procedure_name_from_instance_name()"); return v_line.all; end; function get_process_name_from_instance_name( val : string ) return string is variable v_line : line; variable v_msg_line : line; begin bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_process_name_from_instance_name()"); write(v_line, get_string_between_delimiters(val, ':', ':', RIGHT)); if (string_contains_char(val, '[')) then write(v_msg_line, string'("Must be called with <process-local object>'instance_name")); else write(v_msg_line, string'(" ")); end if; bitvis_assert(v_line'length > 0, ERROR, "No process name found", "get_process_name_from_instance_name()"); return v_line.all; end; function get_entity_name_from_instance_name( val : string ) return string is variable v_line : line; variable v_msg_line : line; begin bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_entity_name_from_instance_name()"); if string_contains_char(val, '@') then -- for path with instantiations write(v_line, get_string_between_delimiters(val, '@', '(', RIGHT)); else -- for path with only a single entity write(v_line, get_string_between_delimiters(val, ':', '(', RIGHT)); end if; if (string_contains_char(val, '[')) then write(v_msg_line, string'("Must be called with <Entity/arch-local object>'instance_name")); else write(v_msg_line, string'(" ")); end if; bitvis_assert(v_line'length > 0, ERROR, "No entity name found", "get_entity_name_from_instance_name()"); return v_line.all; end; function adjust_leading_0( val : string; format : t_format_zeros := SKIP_LEADING_0 ) return string is alias a_val : string(1 to val'length) is val; constant leftmost_non_zero : natural := pos_of_leftmost_non_zero(a_val, 1); begin if val'length <= 1 then return val; end if; if format = SKIP_LEADING_0 then return a_val(leftmost_non_zero to val'length); else return a_val; end if; end function; function return_string_if_true( val : string; return_val : boolean ) return string is begin if return_val then return val; else return ""; end if; end function; function return_string1_if_true_otherwise_string2( val1 : string; val2 : string; return_val : boolean ) return string is begin if return_val then return val1; else return val2; end if; end function; function replace_backslash_n_with_lf( source : string ) return string is variable v_source_idx : natural := 0; variable v_dest_idx : natural := 0; variable v_dest : string(1 to source'length); begin if source'length = 0 then return ""; else if C_USE_BACKSLASH_N_AS_LF then loop v_source_idx := v_source_idx + 1; v_dest_idx := v_dest_idx + 1; if (v_source_idx < source'length) then if (source(v_source_idx to v_source_idx +1) /= " ") then v_dest(v_dest_idx) := source(v_source_idx); else v_dest(v_dest_idx) := LF; v_source_idx := v_source_idx + 1; -- Additional increment as two chars ( ) are consumed if (v_source_idx = source'length) then exit; end if; end if; else -- Final character in string v_dest(v_dest_idx) := source(v_source_idx); exit; end if; end loop; else v_dest := source; v_dest_idx := source'length; end if; return v_dest(1 to v_dest_idx); end if; end; function remove_initial_chars( source : string; num : natural ) return string is begin if source'length <= num then return ""; else return source(1 + num to source'right); end if; end; function wrap_lines( constant text_string : string; constant alignment_pos1 : natural; -- Line position of first aligned character in line 1 constant alignment_pos2 : natural; -- Line position of first aligned character in line 2 constant line_width : natural ) return string is variable v_text_lines : line; variable v_result : string(1 to 2 * text_string'length + alignment_pos1 + 100); -- Margin for aligns and LF insertions variable v_result_width : natural; begin write(v_text_lines, text_string); wrap_lines(v_text_lines, alignment_pos1, alignment_pos2, line_width); v_result_width := v_text_lines'length; bitvis_assert(v_result_width <= v_result'length, FAILURE, " String is too long after wrapping. Increase v_result string size.", "wrap_lines()"); v_result(1 to v_result_width) := v_text_lines.all; deallocate(v_text_lines); return v_result(1 to v_result_width); end; procedure wrap_lines( variable text_lines : inout line; constant alignment_pos1 : natural; -- Line position of first aligned character in line 1 constant alignment_pos2 : natural; -- Line position of first aligned character in line 2 constant line_width : natural ) is variable v_string : string(1 to text_lines'length) := text_lines.all; variable v_string_width : natural := text_lines'length; variable v_line_no : natural := 0; variable v_last_string_wrap : natural := 0; variable v_min_string_wrap : natural; variable v_max_string_wrap : natural; begin deallocate(text_lines); -- empty the line prior to filling it up again l_line: loop -- For every tekstline found in text_lines v_line_no := v_line_no + 1; -- Find position to wrap in v_string if (v_line_no = 1) then v_min_string_wrap := 1; -- Minimum 1 character of input line v_max_string_wrap := minimum(line_width - alignment_pos1 + 1, v_string_width); write(text_lines, fill_string(' ', alignment_pos1 - 1)); else v_min_string_wrap := v_last_string_wrap + 1; -- Minimum 1 character further into the inpit line v_max_string_wrap := minimum(v_last_string_wrap + (line_width - alignment_pos2 + 1), v_string_width); write(text_lines, fill_string(' ', alignment_pos2 - 1)); end if; -- 1. First handle any potential explicit line feed in the current maximum text line -- Search forward for potential LF for i in (v_last_string_wrap + 1) to minimum(v_max_string_wrap + 1, v_string_width) loop if (character(v_string(i)) = LF) then write(text_lines, v_string((v_last_string_wrap + 1) to i)); -- LF now terminates this part v_last_string_wrap := i; next l_line; -- next line end if; end loop; -- 2. Then check if remaining text fits into a single text line if (v_string_width <= v_max_string_wrap) then -- No (more) wrapping required write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width)); exit; -- No more lines end if; -- 3. Search for blanks from char after max msg width and downwards (in the left direction) for i in v_max_string_wrap + 1 downto (v_last_string_wrap + 1) loop if (character(v_string(i)) = ' ') then write(text_lines, v_string((v_last_string_wrap + 1) to i-1)); -- Exchange last blank with LF v_last_string_wrap := i; if (i = v_string_width ) then exit l_line; end if; -- Skip any potential extra blanks in the string for j in (i+1) to v_string_width loop if (v_string(j) = ' ') then v_last_string_wrap := j; if (j = v_string_width ) then exit l_line; end if; else write(text_lines, LF); -- Exchange last blanks with LF, provided not at the end of the string exit; end if; end loop; next l_line; -- next line end if; end loop; -- 4. At this point no LF or blank is found in the searched section of the string. -- Hence just break the string - and continue. write(text_lines, v_string((v_last_string_wrap + 1) to v_max_string_wrap) & LF); -- Added LF termination v_last_string_wrap := v_max_string_wrap; end loop; end; procedure prefix_lines( variable text_lines : inout line; constant prefix : string := C_LOG_PREFIX ) is variable v_string : string(1 to text_lines'length) := text_lines.all; variable v_string_width : natural := text_lines'length; constant prefix_width : natural := prefix'length; variable v_last_string_wrap : natural := 0; variable i : natural := 0; -- for indexing v_string begin deallocate(text_lines); -- empty the line prior to filling it up again l_line : loop -- 1. Write prefix write(text_lines, prefix); -- 2. Write rest of text line (or rest of input line if no LF) l_char: loop i := i + 1; if (i < v_string_width) then if (character(v_string(i)) = LF) then write(text_lines, v_string((v_last_string_wrap + 1) to i)); v_last_string_wrap := i; exit l_char; end if; else -- 3. Reached end of string. Hence just write the rest. write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width)); -- But ensure new line with prefix if ending with LF if (v_string(i) = LF) then write(text_lines, prefix); end if; exit l_char; end if; end loop; if (i = v_string_width) then exit; end if; end loop; end; function replace( val : string; target_char : character; exchange_char : character ) return string is variable result : string(1 to val'length) := val; begin for i in val'range loop if val(i) = target_char then result(i) := exchange_char; end if; end loop; return result; end; procedure replace( variable text_line : inout line; target_char : character; exchange_char : character ) is variable v_string : string(1 to text_line'length) := text_line.all; variable v_string_width : natural := text_line'length; variable i : natural := 0; -- for indexing v_string begin if v_string_width > 0 then deallocate(text_line); -- empty the line prior to filling it up again -- 1. Loop through string and replace characters l_char: loop i := i + 1; if (i < v_string_width) then if (character(v_string(i)) = target_char) then v_string(i) := exchange_char; end if; else -- 2. Reached end of string. Hence just write the new string. write(text_line, v_string); exit l_char; end if; end loop; end if; end; --======================================================== -- Handle missing overloads from 'standard_additions' + advanced overloads --======================================================== function to_string( val : boolean; width : natural; justified : side; format_spaces : t_format_spaces; truncate : t_truncate_string := DISALLOW_TRUNCATE ) return string is begin return justify(to_string(val), justified, width, format_spaces, truncate); end; function to_string( val : integer; width : natural; justified : side; format_spaces : t_format_spaces; truncate : t_truncate_string := DISALLOW_TRUNCATE ) return string is begin return justify(to_string(val), justified, width, format_spaces, truncate); end; -- This function has been deprecated and will be removed in the next major release function to_string( val : boolean; width : natural; justified : side := right; format : t_format_string := AS_IS ) return string is begin return justify(to_string(val), width, justified, format); end; -- This function has been deprecated and will be removed in the next major release function to_string( val : integer; width : natural; justified : side := right; format : t_format_string := AS_IS ) return string is begin return justify(to_string(val), width, justified, format); end; function to_string( val : std_logic_vector; radix : t_radix; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string is variable v_line : line; alias a_val : std_logic_vector(val'length - 1 downto 0) is val; variable v_result : string(1 to 10 + 2 * val'length); -- variable v_width : natural; variable v_use_end_char : boolean := false; begin if val'length = 0 then -- Value length is zero, -- return empty string. return ""; end if; if radix = BIN then if prefix = INCL_RADIX then write(v_line, string'("b""")); v_use_end_char := true; end if; write(v_line, adjust_leading_0(to_string(val), format)); elsif radix = HEX then if prefix = INCL_RADIX then write(v_line, string'("x""")); v_use_end_char := true; end if; write(v_line, adjust_leading_0(to_hstring(val), format)); elsif radix = DEC then if prefix = INCL_RADIX then write(v_line, string'("d""")); v_use_end_char := true; end if; -- Assuming that val is not signed if (val'length > 31) then write(v_line, to_hstring(val) & " (too wide to be converted to integer)" ); else write(v_line, adjust_leading_0(to_string(to_integer(unsigned(val))), format)); end if; elsif radix = HEX_BIN_IF_INVALID then if prefix = INCL_RADIX then write(v_line, string'("x""")); end if; if is_x(val) then write(v_line, adjust_leading_0(to_hstring(val), format)); if prefix = INCL_RADIX then write(v_line, string'("""")); -- terminate hex value end if; write(v_line, string'(" (b""")); write(v_line, adjust_leading_0(to_string(val), format)); write(v_line, string'("""")); write(v_line, string'(")")); else write(v_line, adjust_leading_0(to_hstring(val), format)); if prefix = INCL_RADIX then write(v_line, string'("""")); end if; end if; end if; if v_use_end_char then write(v_line, string'("""")); end if; v_width := v_line'length; v_result(1 to v_width) := v_line.all; deallocate(v_line); return v_result(1 to v_width); end; function to_string( val : unsigned; radix : t_radix; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string is begin return to_string(std_logic_vector(val), radix, format, prefix); end; function to_string( val : signed; radix : t_radix; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string is variable v_line : line; variable v_result : string(1 to 10 + 2 * val'length); -- variable v_width : natural; variable v_use_end_char : boolean := false; begin -- Support negative numbers by _not_ using the slv overload when converting to decimal if radix = DEC then if val'length = 0 then -- Value length is zero, -- return empty string. return ""; end if; if prefix = INCL_RADIX then write(v_line, string'("d""")); v_use_end_char := true; end if; if (val'length > 32) then write(v_line, to_string(std_logic_vector(val),radix, format, prefix) & " (too wide to be converted to integer)" ); else write(v_line, adjust_leading_0(to_string(to_integer(signed(val))), format)); end if; if v_use_end_char then write(v_line, string'("""")); end if; v_width := v_line'length; v_result(1 to v_width) := v_line.all; deallocate(v_line); return v_result(1 to v_width); else -- No decimal convertion: May be treated as slv, so use the slv overload return to_string(std_logic_vector(val), radix, format, prefix); end if; end; function to_string( val : t_byte_array; radix : t_radix := HEX_BIN_IF_INVALID; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string is variable v_line : line; variable v_result : string(1 to 2 + -- parentheses 2*(val'length - 1) + -- commas 26 * val'length); -- 26 is max length of returned value from slv to_string() variable v_width : natural; begin if val'length = 0 then -- Value length is zero, -- return empty string. return ""; elsif val'length = 1 then -- Value length is 1 -- Return the single value it contains return to_string(val(val'low), radix, format, prefix); else -- Value length more than 1 -- Comma-separate all array members and return write(v_line, string'("(")); for i in val'range loop write(v_line, to_string(val(i), radix, format, prefix)); if i < val'right and val'ascending then write(v_line, string'(", ")); elsif i > val'right and not val'ascending then write(v_line, string'(", ")); end if; end loop; write(v_line, string'(")")); v_width := v_line'length; v_result(1 to v_width) := v_line.all; deallocate(v_line); return v_result(1 to v_width); end if; end; function to_string( val : t_slv_array; radix : t_radix := HEX_BIN_IF_INVALID; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string is variable v_line : line; variable v_result : string(1 to 2 + -- parentheses 2*(val'length - 1) + -- commas 26*val'length); -- 26 is max length of returned value from slv to_string() variable v_width : natural; begin if val'length = 0 then return ""; else -- Comma-separate all array members and return write(v_line, string'("(")); for idx in val'range loop write(v_line, to_string(val(idx), radix, format, prefix)); if (idx < val'right) and (val'ascending) then write(v_line, string'(", ")); elsif (idx > val'right) and not(val'ascending) then write(v_line, string'(", ")); end if; end loop; write(v_line, string'(")")); v_width := v_line'length; v_result(1 to v_width) := v_line.all; deallocate(v_line); return v_result(1 to v_width); end if; end function; function to_string( val : t_signed_array; radix : t_radix := HEX_BIN_IF_INVALID; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string is variable v_line : line; variable v_result : string(1 to 2 + -- parentheses 2*(val'length - 1) + -- commas 26*val'length); -- 26 is max length of returned value from slv to_string() variable v_width : natural; begin if val'length = 0 then return ""; else -- Comma-separate all array members and return write(v_line, string'("(")); for idx in val'range loop write(v_line, to_string(val(idx), radix, format, prefix)); if (idx < val'right) and (val'ascending) then write(v_line, string'(", ")); elsif (idx > val'right) and not(val'ascending) then write(v_line, string'(", ")); end if; end loop; write(v_line, string'(")")); v_width := v_line'length; v_result(1 to v_width) := v_line.all; deallocate(v_line); return v_result(1 to v_width); end if; end function; function to_string( val : t_unsigned_array; radix : t_radix := HEX_BIN_IF_INVALID; format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0 prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string? ) return string is variable v_line : line; variable v_result : string(1 to 2 + -- parentheses 2*(val'length - 1) + -- commas 26*val'length); -- 26 is max length of returned value from slv to_string() variable v_width : natural; begin if val'length = 0 then return ""; else -- Comma-separate all array members and return write(v_line, string'("(")); for idx in val'range loop write(v_line, to_string(val(idx), radix, format, prefix)); if (idx < val'right) and (val'ascending) then write(v_line, string'(", ")); elsif (idx > val'right) and not(val'ascending) then write(v_line, string'(", ")); end if; end loop; write(v_line, string'(")")); v_width := v_line'length; v_result(1 to v_width) := v_line.all; deallocate(v_line); return v_result(1 to v_width); end if; end function; --======================================================== -- Handle types defined at lower levels --======================================================== function to_string( val : t_alert_level; width : natural; justified : side := right ) return string is constant inner_string : string := t_alert_level'image(val); begin return to_upper(justify(inner_string, justified, width)); end function; function to_string( val : t_msg_id; width : natural; justified : side := right ) return string is constant inner_string : string := t_msg_id'image(val); begin return to_upper(justify(inner_string, justified, width)); end function; function to_string( val : t_attention; width : natural; justified : side := right ) return string is begin return to_upper(justify(t_attention'image(val), justified, width)); end; -- function to_string( -- dummy : t_void -- ) return string is -- begin -- return "VOID"; -- end function; procedure to_string( val : t_alert_attention_counters; order : t_order := FINAL ) is variable v_line : line; variable v_line_copy : line; variable v_more_than_expected_alerts : boolean := false; variable v_less_than_expected_alerts : boolean := false; variable v_header : string(1 to 42); constant prefix : string := C_LOG_PREFIX & " "; begin if order = INTERMEDIATE then v_header := "*** INTERMEDIATE SUMMARY OF ALL ALERTS ***"; else -- order=FINAL v_header := "*** FINAL SUMMARY OF ALL ALERTS *** "; end if; write(v_line, LF & fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & v_header & LF & fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & " REGARDED EXPECTED IGNORED Comment?" & LF); for i in NOTE to t_alert_level'right loop write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity for j in t_attention'left to t_attention'right loop write(v_line, to_string(integer'(val(i)(j)), 6, RIGHT, KEEP_LEADING_SPACE) & " "); end loop; if (val(i)(REGARD) = val(i)(EXPECT)) then write(v_line, " ok " & LF); else write(v_line, " *** " & to_string(i,0) & " *** " & LF); if (i > MANUAL_CHECK) then if (val(i)(REGARD) < val(i)(EXPECT)) then v_less_than_expected_alerts := true; else v_more_than_expected_alerts := true; end if; end if; end if; end loop; write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF); -- Print a conclusion when called from the FINAL part of the test sequencer -- but not when called from in the middle of the test sequence (order=INTERMEDIATE) if order = FINAL then if v_more_than_expected_alerts then write(v_line, ">> Simulation FAILED, with unexpected serious alert(s)" & LF); elsif v_less_than_expected_alerts then write(v_line, ">> Simulation FAILED: Mismatch between counted and expected serious alerts" & LF); else write(v_line, ">> Simulation SUCCESS: No mismatch between counted and expected serious alerts" & LF); end if; write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & LF); end if; wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length); prefix_lines(v_line, prefix); -- Write the info string to the target file write (v_line_copy, v_line.all & lf); -- copy line writeline(OUTPUT, v_line); writeline(LOG_FILE, v_line_copy); end; -- Convert from ASCII to character -- Inputs: -- ascii_pos (integer) : ASCII number input -- ascii_allow (t_ascii_allow) : Decide what to do with invisible control characters: -- - If ascii_allow = ALLOW_ALL (default) : return the character for any ascii_pos -- - If ascii_allow = ALLOW_PRINTABLE_ONLY : return the character only if it is printable function ascii_to_char( ascii_pos : integer range 0 to 255; -- Supporting Extended ASCII ascii_allow : t_ascii_allow := ALLOW_ALL ) return character is variable v_printable : boolean := true; begin if ascii_pos < 32 or -- NUL, SOH, STX etc (ascii_pos >= 128 and ascii_pos < 160) then -- C128 to C159 v_printable := false; end if; if ascii_allow = ALLOW_ALL or (ascii_allow = ALLOW_PRINTABLE_ONLY and v_printable) then return character'val(ascii_pos); else return ' '; -- Must return something when invisible control signals end if; end; -- Convert from character to ASCII integer function char_to_ascii( char : character ) return integer is begin return character'pos(char); end; -- return string with only valid ascii characters function to_string( val : string ) return string is variable v_new_string : string(1 to val'length); variable v_char_idx : natural := 0; variable v_ascii_pos : natural; begin for i in val'range loop v_ascii_pos := character'pos(val(i)); if (v_ascii_pos < 32 and v_ascii_pos /= 10) or -- NUL, SOH, STX etc, LF(10) is not removed. (v_ascii_pos >= 128 and v_ascii_pos < 160) then -- C128 to C159 -- illegal char null; else -- legal char v_char_idx := v_char_idx + 1; v_new_string(v_char_idx) := val(i); end if; end loop; if v_char_idx = 0 then return ""; else return v_new_string(1 to v_char_idx); end if; end; function add_msg_delimiter( msg : string ) return string is begin if msg'length /= 0 then if valid_length(msg) /= 1 then if msg(1) = C_MSG_DELIMITER then return msg; else return C_MSG_DELIMITER & msg & C_MSG_DELIMITER; end if; end if; end if; return ""; end; end package body string_methods_pkg; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library std; use std.textio.all; library uvvm_util; context uvvm_util.uvvm_util_context; package spi_bfm_pkg is --=============================================================================================== -- Types and constants for SPI BFMs --=============================================================================================== constant C_SCOPE : string := "SPI BFM"; type t_spi_if is record ss_n : std_logic; -- master to slave sclk : std_logic; -- master to slave mosi : std_logic; -- master to slave miso : std_logic; -- slave to master end record; -- Configuration record to be assigned in the test harness. type t_spi_bfm_config is record CPOL : std_logic; -- sclk polarity, i.e. the base value of the clock. -- If CPOL is '0', the clock will be set to '0' when inactive, i.e., ordinary positive polarity. CPHA : std_logic; -- sclk phase, i.e. when data is sampled and transmitted w.r.t. sclk. -- If '0', sampling occurs on the first sclk edge and data is transmitted on the sclk active to idle state. -- If '1', data is sampled on the second sclk edge and transmitted on sclk idle to active state. spi_bit_time : time; -- Used in master for dictating sclk period ss_n_to_sclk : time; -- Time from SS active until SCLK active sclk_to_ss_n : time; -- Last SCLK until SS off inter_word_delay : time; -- Minimum time between words, from ss_n inactive to ss_n active match_strictness : t_match_strictness; -- Matching strictness for std_logic values in check procedures. id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the SPI BFM id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the SPI BFM id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the SPI BFM end record; constant C_SPI_BFM_CONFIG_DEFAULT : t_spi_bfm_config := ( CPOL => '0', CPHA => '0', spi_bit_time => -1 ns, -- Make sure we notice if we forget to set bit time. ss_n_to_sclk => 20 ns, sclk_to_ss_n => 20 ns, inter_word_delay => 0 ns, match_strictness => MATCH_EXACT, id_for_bfm => ID_BFM, id_for_bfm_wait => ID_BFM_WAIT, id_for_bfm_poll => ID_BFM_POLL ); --=============================================================================================== -- BFM procedures --=============================================================================================== ------------------------------------------ -- init_spi_if_signals ------------------------------------------ -- - This function returns an SPI interface with initialized signals. -- - master_mode = true: -- - ss_n initialized to 'H' -- - if config.CPOL = '1', sclk initialized to 'H', -- otherwise sclk initialized to 'L' -- - miso and mosi initialized to 'Z' -- - master_mode = false: -- - all signals initialized to 'Z' function init_spi_if_signals ( constant config : in t_spi_bfm_config; constant master_mode : in boolean := true ) return t_spi_if; ------------------------------------------ -- spi_master_transmit_and_receive ------------------------------------------ -- This procedure transmits data 'tx_data' to the SPI slave DUT -- and receives 'rx_data' from the SPI slave DUT. procedure spi_master_transmit_and_receive ( constant tx_data : in std_logic_vector; variable rx_data : out std_logic_vector; constant msg : in string; signal sclk : inout std_logic; signal ss_n : inout std_logic; signal mosi : inout std_logic; signal miso : inout std_logic; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT; constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure ); ------------------------------------------ -- spi_master_transmit_and_receive ------------------------------------------ -- This procedure transmits data 'tx_data' to the SPI slave DUT -- and receives 'rx_data' from the SPI slave DUT. -- The SPI interface in this procedure is given as a t_spi_if signal record procedure spi_master_transmit_and_receive ( constant tx_data : in std_logic_vector; variable rx_data : out std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT; constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure ); -- Multi-word procedure spi_master_transmit_and_receive ( constant tx_data : in t_slv_array; variable rx_data : out t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT; constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure ); ------------------------------------------ -- spi_master_transmit_and_check ------------------------------------------ -- This procedure ... -- The SPI interface in this procedure is given as a t_spi_if signal record procedure spi_master_transmit_and_check( constant tx_data : in std_logic_vector; constant data_exp : in std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant alert_level : in t_alert_level := error; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ); -- Multi-word procedure spi_master_transmit_and_check( constant tx_data : in t_slv_array; constant data_exp : in t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant alert_level : in t_alert_level := error; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ); ------------------------------------------ -- spi_master_transmit ------------------------------------------ -- This procedure transmits data 'tx_data' to the SPI DUT -- The SPI interface in this procedure is given as a t_spi_if signal record procedure spi_master_transmit( constant tx_data : in std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ); -- Multi-word procedure spi_master_transmit( constant tx_data : in t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ); ------------------------------------------ -- spi_master_receive ------------------------------------------ -- This procedure receives data 'rx_data' from the SPI DUT -- The SPI interface in this procedure is given as a t_spi_if signal record procedure spi_master_receive( variable rx_data : out std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ); -- Multi-word procedure spi_master_receive( variable rx_data : out t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ); ------------------------------------------ -- spi_master_check ------------------------------------------ -- This procedure receives an SPI transaction, and compares the read data -- to the expected data in 'data_exp'. -- If the read data is inconsistent with the expected data, an alert with -- severity 'alert_level' is triggered. -- The SPI interface in this procedure is given as a t_spi_if signal record procedure spi_master_check( constant data_exp : in std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant alert_level : in t_alert_level := error; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ); -- Multi-word procedure spi_master_check( constant data_exp : in t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant alert_level : in t_alert_level := error; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ); ------------------------------------------ -- spi_slave_transmit_and_receive ------------------------------------------ -- This procedure transmits data 'tx_data' to the SPI master DUT -- and receives 'rx_data' from the SPI master DUT. procedure spi_slave_transmit_and_receive ( constant tx_data : in std_logic_vector; variable rx_data : out std_logic_vector; constant msg : in string; signal sclk : inout std_logic; signal ss_n : inout std_logic; signal mosi : inout std_logic; signal miso : inout std_logic; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT; constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure ); ------------------------------------------ -- spi_slave_transmit_and_receive ------------------------------------------ -- This procedure transmits data 'tx_data' to the SPI master DUT -- and receives 'rx_data' from the SPI master DUT. -- The SPI interface in this procedure is given as a t_spi_if signal record procedure spi_slave_transmit_and_receive ( constant tx_data : in std_logic_vector; variable rx_data : out std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT; constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure ); -- Multi-word procedure spi_slave_transmit_and_receive ( constant tx_data : in t_slv_array; variable rx_data : out t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT; constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure ); ------------------------------------------ -- spi_slave_transmit_and_check ------------------------------------------ -- This procedure ... -- The SPI interface in this procedure is given as a t_spi_if signal record procedure spi_slave_transmit_and_check( constant tx_data : in std_logic_vector; constant data_exp : in std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant alert_level : in t_alert_level := error; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ); -- Multi-word procedure spi_slave_transmit_and_check( constant tx_data : in t_slv_array; constant data_exp : in t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant alert_level : in t_alert_level := error; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ); ------------------------------------------ -- spi_slave_transmit ------------------------------------------ -- This procedure transmits data 'tx_data' to the SPI DUT -- The SPI interface in this procedure is given as a t_spi_if signal record procedure spi_slave_transmit ( constant tx_data : in std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ); -- Multi-word procedure spi_slave_transmit ( constant tx_data : in t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ); ------------------------------------------ -- spi_slave_receive ------------------------------------------ -- This procedure receives data 'rx_data' from the SPI DUT -- The SPI interface in this procedure is given as a t_spi_if signal record procedure spi_slave_receive ( variable rx_data : out std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ); -- Multi-word procedure spi_slave_receive ( variable rx_data : out t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ); ------------------------------------------ -- spi_slave_check ------------------------------------------ -- This procedure receives an SPI transaction, and compares the read data -- to the expected data in 'data_exp'. -- If the read data is inconsistent with the expected data, an alert with -- severity 'alert_level' is triggered. -- The SPI interface in this procedure is given as a t_spi_if signal record procedure spi_slave_check ( constant data_exp : in std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant alert_level : in t_alert_level := error; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ); -- Multi-word procedure spi_slave_check ( constant data_exp : in t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant alert_level : in t_alert_level := error; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ); end package spi_bfm_pkg; package body spi_bfm_pkg is --------------------------------------------------------------------------------- -- initialize spi to dut signals --------------------------------------------------------------------------------- function init_spi_if_signals ( constant config : in t_spi_bfm_config; constant master_mode : in boolean := true ) return t_spi_if is variable result : t_spi_if; begin if master_mode then result.ss_n := 'H'; if (config.CPOL) then result.sclk := 'H'; else result.sclk := 'L'; end if; else result.ss_n := 'Z'; result.sclk := 'Z'; end if; result.mosi := 'Z'; result.miso := 'Z'; return result; end function; --------------------------------------------------------------------------------- -- spi_master_transmit_and_receive -- -- alert if size of tx_data or rx_data doesn't -- match with how long ss_n is kept low --------------------------------------------------------------------------------- procedure spi_master_transmit_and_receive ( constant tx_data : in std_logic_vector; variable rx_data : out std_logic_vector; constant msg : in string; signal sclk : inout std_logic; signal ss_n : inout std_logic; signal mosi : inout std_logic; signal miso : inout std_logic; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT; constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure ) is constant local_proc_name : string := "spi_master_transmit_and_receive"; constant local_proc_call : string := local_proc_name; constant C_ACCESS_SIZE : integer := tx_data'length; -- Helper variables variable v_access_done : boolean := false; variable v_tx_count : integer := 0; variable v_tx_data : std_logic_vector(tx_data'length-1 downto 0) := tx_data; variable v_rx_data : std_logic_vector(rx_data'length-1 downto 0) := (others => 'X'); variable v_rx_count : integer := 1; variable v_proc_call : line; variable v_multi_word_transfer_in_progress : boolean := false; begin -- check whether config.spi_bit_time was set check_value(config.spi_bit_time /= -1 ns, TB_ERROR, "SPI Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel); if ext_proc_call = "" then -- Called directly from sequencer/VVC, log 'spi_master_transmit_and_receive...' write(v_proc_call, local_proc_call); else -- Called from another BFM procedure, log 'ext_proc_call while executing spi_master_transmit_and_receive...' write(v_proc_call, ext_proc_call & " while executing " & local_proc_name); end if; -- Detect if we have an ongoing multi-word transfer if ss_n = '0' then v_multi_word_transfer_in_progress := true; end if; sclk <= config.CPOL; ss_n <= '0'; wait for 0 ns; -- wait a delta cycle if ss_n = '0' then -- set MOSI together with SS_N when CPHA=0 if not config.CPHA then mosi <= v_tx_data(C_ACCESS_SIZE- v_tx_count - 1); v_tx_count := v_tx_count + 1; end if; -- Decide delay before initial SCLK edge if not v_multi_word_transfer_in_progress then wait for config.ss_n_to_sclk; else wait for config.spi_bit_time/2; end if; sclk <= not config.CPOL; -- serially shift out v_tx_data to mosi -- serially shift in v_rx_data from miso while ss_n = '0' and not v_access_done loop if not config.CPHA then v_rx_data(C_ACCESS_SIZE-v_rx_count) := miso; wait for config.spi_bit_time/2; sclk <= config.CPOL; mosi <= v_tx_data(C_ACCESS_SIZE-v_tx_count-1); else -- config.CPHA mosi <= v_tx_data(C_ACCESS_SIZE-v_tx_count-1); wait for config.spi_bit_time/2; sclk <= config.CPOL; v_rx_data(C_ACCESS_SIZE-v_rx_count) := miso; end if; if v_tx_count < C_ACCESS_SIZE-1 then -- Not done v_rx_count := v_rx_count + 1; v_tx_count := v_tx_count + 1; wait for config.spi_bit_time/2; sclk <= not config.CPOL; else -- Final bit if not config.CPHA then v_rx_count := v_rx_count + 1; -- Sample Last bit on the second to last edge of SCLK (CPOL=0: last rising. CPOL=1: last falling) wait for config.spi_bit_time/2; v_rx_data(C_ACCESS_SIZE-v_rx_count) := miso; sclk <= not config.CPOL; end if; log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(v_tx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel); v_access_done := true; end if; end loop; -- Clock the last bit if not config.CPHA then wait for config.spi_bit_time/2; sclk <= config.CPOL; end if; -- Determine if single- or multi-word transfer if action_when_transfer_is_done = RELEASE_LINE_AFTER_TRANSFER then wait for config.sclk_to_ss_n; mosi <= 'Z'; ss_n <= '1'; wait for config.inter_word_delay; else -- action_when_transfer_is_done = HOLD_LINE_AFTER_TRANSFER ss_n <= '0'; end if; wait for 0 ns; -- delta cycle if (v_tx_count /= C_ACCESS_SIZE-1) or (v_rx_count /= C_ACCESS_SIZE) then alert(note, " v_tx_count /= C_ACCESS_SIZE-1 or v_rx_count /= C_ACCESS_SIZE then"); alert(note, to_string(v_tx_count) & " /= " & to_string(C_ACCESS_SIZE-1) & " or" &to_string(v_rx_count) & " /= " & to_string(C_ACCESS_SIZE)); alert(note, local_proc_name & " ss_n not kept low for v_tx_data size duration"); else rx_data := v_rx_data; end if; else alert(error, local_proc_name & " ss_n not low when expected."); end if; if ext_proc_call = "" then log(config.id_for_bfm, v_proc_call.all & "=> Transmitted: " & to_string(v_tx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". Received: " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel); else -- Log will be handled by calling procedure (e.g. spi_master_transmit_and_check) end if; DEALLOCATE(v_proc_call); end procedure; -- Single-word procedure spi_master_transmit_and_receive ( constant tx_data : in std_logic_vector; variable rx_data : out std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT; constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure ) is begin spi_master_transmit_and_receive(tx_data, rx_data, msg, spi_if.sclk, spi_if.ss_n, spi_if.mosi, spi_if.miso, action_when_transfer_is_done, scope, msg_id_panel, config, ext_proc_call); end procedure; -- Multi-word procedure spi_master_transmit_and_receive ( constant tx_data : in t_slv_array; variable rx_data : out t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT; constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure ) is variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer begin -- Check length of tx_data and rx_data if tx_data'length /= rx_data'length then alert(error, ext_proc_call & " tx_data and rx_data have different sizes."); end if; for idx in 0 to (tx_data'length-1) loop case action_between_words is when RELEASE_LINE_BETWEEN_WORDS => if idx < tx_data'length-1 then v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; else v_action_when_transfer_is_done := action_when_transfer_is_done; end if; when others => -- HOLD_LINE_BETWEEN_WORDS if idx < tx_data'length-1 then v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER; else v_action_when_transfer_is_done := action_when_transfer_is_done; end if; end case; -- call single-word procedure spi_master_transmit_and_receive(tx_data(idx), rx_data(idx), msg, spi_if, v_action_when_transfer_is_done, scope, msg_id_panel, config, ext_proc_call); end loop; end procedure; --------------------------------------------------------------------------------- -- spi_master_transmit_and_check --------------------------------------------------------------------------------- procedure spi_master_transmit_and_check( constant tx_data : in std_logic_vector; constant data_exp : in std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant alert_level : in t_alert_level := error; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ) is constant local_proc_name : string := "spi_master_transmit_and_check"; constant local_proc_call : string := local_proc_name; -- Helper variables variable v_rx_data : std_logic_vector(data_exp'length-1 downto 0); variable v_check_ok : boolean := true; variable v_alert_radix : t_radix; begin spi_master_transmit_and_receive(tx_data, v_rx_data, msg, spi_if, action_when_transfer_is_done, scope, msg_id_panel, config, local_proc_call); for i in data_exp'range loop -- Allow don't care in expected value and use match strictness from config for comparison if data_exp(i) = '-' or check_value(v_rx_data(i), data_exp(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then v_check_ok := true; else v_check_ok := false; exit; end if; end loop; if not v_check_ok then -- Use binary representation when mismatch is due to weak signals v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_data, data_exp, MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX; alert(alert_level, local_proc_call & "=> Failed. Was " & to_string(v_rx_data, v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " & to_string(data_exp, v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope); else log(config.id_for_bfm, local_proc_call & "=> OK, read data = " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel); end if; end procedure; -- Multi-word procedure spi_master_transmit_and_check( constant tx_data : in t_slv_array; constant data_exp : in t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant alert_level : in t_alert_level := error; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ) is constant local_proc_name : string := "spi_master_transmit_and_check"; constant local_proc_call : string := local_proc_name; variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer begin -- Check length of tx_data and data_exp if tx_data'length /= data_exp'length then alert(error, local_proc_call & " tx_data and data_exp have different sizes."); end if; for idx in 0 to (tx_data'length-1) loop case action_between_words is when RELEASE_LINE_BETWEEN_WORDS => if idx < tx_data'length-1 then v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; else v_action_when_transfer_is_done := action_when_transfer_is_done; end if; when others => -- HOLD_LINE_BETWEEN_WORDS if idx < tx_data'length-1 then v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER; else v_action_when_transfer_is_done := action_when_transfer_is_done; end if; end case; -- call single-word procedure spi_master_transmit_and_check(tx_data(idx), data_exp(idx), msg, spi_if, alert_level, v_action_when_transfer_is_done, scope, msg_id_panel, config); end loop; end procedure; --------------------------------------------------------------------------------- -- spi_master_transmit --------------------------------------------------------------------------------- procedure spi_master_transmit( constant tx_data : in std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ) is constant local_proc_name : string := "spi_master_transmit"; constant local_proc_call : string := local_proc_name; -- Helper variables variable v_rx_data : std_logic_vector(tx_data'length - 1 downto 0); begin spi_master_transmit_and_receive(tx_data, v_rx_data, msg, spi_if, action_when_transfer_is_done, scope, msg_id_panel, config, local_proc_call); end procedure; -- Multi-word procedure spi_master_transmit( constant tx_data : in t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ) is variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer begin for idx in 0 to (tx_data'length-1) loop case action_between_words is when RELEASE_LINE_BETWEEN_WORDS => if idx < tx_data'length-1 then v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; else v_action_when_transfer_is_done := action_when_transfer_is_done; end if; when others => -- HOLD_LINE_BETWEEN_WORDS if idx < tx_data'length-1 then v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER; else v_action_when_transfer_is_done := action_when_transfer_is_done; end if; end case; -- call single-word procedure spi_master_transmit(tx_data(idx), msg, spi_if, v_action_when_transfer_is_done, scope, msg_id_panel, config); end loop; end procedure; --------------------------------------------------------------------------------- -- spi_master_receive --------------------------------------------------------------------------------- procedure spi_master_receive( variable rx_data : out std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ) is constant local_proc_name : string := "spi_master_receive"; constant local_proc_call : string := local_proc_name; -- Helper variables variable v_tx_data : std_logic_vector(rx_data'length - 1 downto 0) := (others => '0'); begin spi_master_transmit_and_receive(v_tx_data, rx_data, msg, spi_if, action_when_transfer_is_done, scope, msg_id_panel, config, local_proc_call); end procedure; -- Multi-word procedure spi_master_receive( variable rx_data : out t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ) is variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer begin for idx in 0 to (rx_data'length-1) loop case action_between_words is when RELEASE_LINE_BETWEEN_WORDS => if idx < rx_data'length-1 then v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; else v_action_when_transfer_is_done := action_when_transfer_is_done; end if; when others => -- HOLD_LINE_BETWEEN_WORDS if idx < rx_data'length-1 then v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER; else v_action_when_transfer_is_done := action_when_transfer_is_done; end if; end case; -- call single-word procedure spi_master_receive(rx_data(idx), msg, spi_if, v_action_when_transfer_is_done, scope, msg_id_panel, config); end loop; end procedure; --------------------------------------------------------------------------------- -- spi_master_check --------------------------------------------------------------------------------- procedure spi_master_check( constant data_exp : in std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant alert_level : in t_alert_level := error; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ) is constant local_proc_name : string := "spi_master_check"; constant local_proc_call : string := local_proc_name; -- Helper variables variable v_tx_data : std_logic_vector(data_exp'length - 1 downto 0) := (others => '0'); variable v_rx_data : std_logic_vector(data_exp'length-1 downto 0); variable v_check_ok : boolean := true; variable v_alert_radix : t_radix; begin spi_master_transmit_and_receive(v_tx_data, v_rx_data, msg, spi_if, action_when_transfer_is_done, scope, msg_id_panel, config, local_proc_call); for i in data_exp'range loop -- Allow don't care in expected value and use match strictness from config for comparison if data_exp(i) = '-' or check_value(v_rx_data(i), data_exp(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then v_check_ok := true; else v_check_ok := false; exit; end if; end loop; if not v_check_ok then -- Use binary representation when mismatch is due to weak signals v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_data, data_exp, MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX; alert(alert_level, local_proc_call & "=> Failed. Was " & to_string(v_rx_data, v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " & to_string(data_exp, v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope); else log(config.id_for_bfm, local_proc_call & "=> OK, read data = " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel); end if; end procedure; -- Multi-word procedure spi_master_check( constant data_exp : in t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant alert_level : in t_alert_level := error; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ) is variable v_action_when_transfer_is_done : t_action_when_transfer_is_done; -- between words and after transfer begin for idx in 0 to (data_exp'length-1) loop case action_between_words is when RELEASE_LINE_BETWEEN_WORDS => if idx < data_exp'length-1 then v_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; else v_action_when_transfer_is_done := action_when_transfer_is_done; end if; when others => -- HOLD_LINE_BETWEEN_WORDS if idx < data_exp'length-1 then v_action_when_transfer_is_done := HOLD_LINE_AFTER_TRANSFER; else v_action_when_transfer_is_done := action_when_transfer_is_done; end if; end case; -- call single-word procedure spi_master_check(data_exp(idx), msg, spi_if, alert_level, v_action_when_transfer_is_done, scope, msg_id_panel, config); end loop; end procedure; --------------------------------------------------------------------------------- -- spi_slave_transmit_and_receive -- --------------------------------------------------------------------------------- procedure spi_slave_transmit_and_receive ( constant tx_data : in std_logic_vector; variable rx_data : out std_logic_vector; constant msg : in string; signal sclk : inout std_logic; signal ss_n : inout std_logic; signal mosi : inout std_logic; signal miso : inout std_logic; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT; constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure ) is -- Local_proc_name/call used if called from sequencer or VVC constant local_proc_name : string := "spi_slave_transmit_and_receive"; constant local_proc_call : string := local_proc_name; constant C_ACCESS_SIZE : integer := rx_data'length; -- Helper variables variable v_rx_data : std_logic_vector(rx_data'range) := (others => 'X'); variable bfm_tx_data : std_logic_vector(tx_data'length-1 downto 0) := tx_data; variable v_access_done : boolean := false; variable v_tx_count : integer := 0; variable v_rx_count : integer := 1; variable v_proc_call : line; begin -- check whether config.spi_bit_time was set check_value(config.spi_bit_time /= -1 ns, TB_ERROR, "SPI Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel); if ext_proc_call = "" then -- Called directly from sequencer/VVC, log 'spi_slave_transmit_and_receive...' write(v_proc_call, local_proc_call); else -- Called from another BFM procedure, log 'ext_proc_call while executing spi_slave_transmit_and_receive...' write(v_proc_call, ext_proc_call & " while executing " & local_proc_name); end if; -- Await for master to drive SS_N and SCLK if (ss_n /= '0') then -- master not acvtive wait until (ss_n = '0'); elsif (ss_n = '0') then -- master active case when_to_start_transfer is when START_TRANSFER_ON_NEXT_SS => if (ss_n = '0') and (ss_n'last_active > 0 ns) then wait until (ss_n = '0') and (ss_n'last_active <= 0 ns); end if; when others => -- START_TRANSFER_IMMEDIATE null; end case; end if; if ss_n = '0' then -- set MISO together with SS_N when CPHA=0 if not config.CPHA then miso <= bfm_tx_data(C_ACCESS_SIZE - v_tx_count - 1); v_tx_count := v_tx_count + 1; end if; -- Await first clock edge if sclk = config.CPOL then wait until sclk = not(config.CPOL); end if; -- Receive bits while (ss_n = '0') and not(v_access_done) loop if not config.CPHA then v_rx_data(C_ACCESS_SIZE - v_rx_count) := mosi; wait until sclk'event and sclk = config.CPOL; miso <= bfm_tx_data(C_ACCESS_SIZE - v_tx_count - 1); else -- config.CPHA miso <= bfm_tx_data(C_ACCESS_SIZE - v_tx_count - 1); wait until sclk'event and sclk = config.CPOL; v_rx_data(C_ACCESS_SIZE - v_rx_count) := mosi; end if; if (v_tx_count < (C_ACCESS_SIZE-1)) and (v_rx_count < C_ACCESS_SIZE) then wait until sclk'event and sclk = not(config.CPOL); v_tx_count := v_tx_count + 1; v_rx_count := v_rx_count + 1; else if not config.CPHA then wait until sclk'event and sclk = not(config.CPOL); end if; v_access_done := true; end if; end loop; end if; -- Sample last bit if not config.CPHA then v_rx_count := v_rx_count + 1; v_rx_data(C_ACCESS_SIZE - v_rx_count) := mosi; wait until sclk'event and sclk = config.CPOL; end if; if (v_tx_count < C_ACCESS_SIZE-1) then alert(error, v_proc_call.all & " ss_n not kept active for tx_data size duration " & add_msg_delimiter(msg), scope); elsif (v_rx_count < C_ACCESS_SIZE) then alert(error, v_proc_call.all & " ss_n not kept active for rx_data size duration " & add_msg_delimiter(msg), scope); else rx_data := v_rx_data; end if; -- Await for master to finish wait until (mosi = 'Z') for config.ss_n_to_sclk; miso <= 'Z'; if ext_proc_call = "" then log(config.id_for_bfm, local_proc_call & "=> " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & " rx completed. " & add_msg_delimiter(msg), scope, msg_id_panel); log(config.id_for_bfm, local_proc_call & "=> " & to_string(bfm_tx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & " tx completed. " & add_msg_delimiter(msg), scope, msg_id_panel); else -- Log will be handled by calling procedure (e.g. spi_master_transmit_and_check) end if; DEALLOCATE(v_proc_call); end procedure; procedure spi_slave_transmit_and_receive ( constant tx_data : in std_logic_vector; variable rx_data : out std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT; constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure ) is begin spi_slave_transmit_and_receive(tx_data, rx_data, msg, spi_if.sclk, spi_if.ss_n, spi_if.mosi, spi_if.miso, when_to_start_transfer, scope, msg_id_panel, config, ext_proc_call); end procedure; -- Multi-word procedure spi_slave_transmit_and_receive ( constant tx_data : in t_slv_array; variable rx_data : out t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT; constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure ) is begin -- Check length of tx_data and rx_data if tx_data'length /= rx_data'length then alert(error, ext_proc_call & "tx_data and rx_data have different sizes."); end if; for idx in 0 to (tx_data'length-1) loop spi_slave_transmit_and_receive(tx_data(idx), rx_data(idx), msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, ext_proc_call); end loop; end procedure; ------------------------------------------ -- spi_slave_transmit_and_check ------------------------------------------ procedure spi_slave_transmit_and_check( constant tx_data : in std_logic_vector; constant data_exp : in std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant alert_level : in t_alert_level := error; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ) is constant local_proc_name : string := "spi_slave_transmit_and_check"; constant local_proc_call : string := local_proc_name & "(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")"; -- Helper variables variable v_rx_data : std_logic_vector(data_exp'length-1 downto 0); variable v_check_ok : boolean := true; variable v_alert_radix : t_radix; begin spi_slave_transmit_and_receive(tx_data, v_rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call); for i in data_exp'range loop -- Allow don't care in expected value and use match strictness from config for comparison if data_exp(i) = '-' or check_value(v_rx_data(i), data_exp(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then v_check_ok := true; else v_check_ok := false; exit; end if; end loop; if not v_check_ok then -- Use binary representation when mismatch is due to weak signals v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_data, data_exp, MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX; alert(alert_level, local_proc_call & "=> Failed. Was " & to_string(v_rx_data, v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " & to_string(data_exp, v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope); else log(config.id_for_bfm, local_proc_call & "=> OK, read data = " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel); end if; end; -- Multi-word procedure spi_slave_transmit_and_check( constant tx_data : in t_slv_array; constant data_exp : in t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant alert_level : in t_alert_level := error; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ) is constant loc_proc_call : string := "spi_slave_transmit_and_check"; -- External proc_call; overwrite if called from other BFM procedure like spi_*_check begin -- Check length of tx_data and rx_data if tx_data'length /= data_exp'length then alert(error, loc_proc_call & " tx_data and data_exp have different sizes."); end if; for idx in 0 to (tx_data'length-1) loop -- call single-word procedure - will handle error checking spi_slave_transmit_and_check(tx_data(idx), data_exp(idx), msg, spi_if, alert_level, when_to_start_transfer, scope, msg_id_panel, config); end loop; end; --------------------------------------------------------------------------------- -- spi_slave_transmit --------------------------------------------------------------------------------- procedure spi_slave_transmit( constant tx_data : in std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ) is constant local_proc_name : string := "spi_slave_transmit"; constant local_proc_call : string := local_proc_name & "(" & to_string(tx_data, HEX, AS_IS, INCL_RADIX) & ")"; -- Helper variables variable v_rx_data : std_logic_vector(tx_data'length-1 downto 0); -- := (others => '0'); begin spi_slave_transmit_and_receive(tx_data, v_rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call); end procedure; -- Multi-word procedure spi_slave_transmit( constant tx_data : in t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ) is constant local_proc_name : string := "spi_slave_transmit"; constant local_proc_call : string := local_proc_name & "(" & to_string(tx_data, HEX, AS_IS, INCL_RADIX) & ")"; -- Helper variables variable v_tx_data : t_slv_array(tx_data'length-1 downto 0)(tx_data(0)'length-1 downto 0) := (others => (others => '0')); begin -- call multi-word procedure spi_slave_transmit_and_receive(tx_data, v_tx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call); end procedure; --------------------------------------------------------------------------------- -- spi_slave_receive --------------------------------------------------------------------------------- procedure spi_slave_receive ( variable rx_data : out std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ) is constant local_proc_name : string := "spi_slave_receive"; constant local_proc_call : string := local_proc_name & "(" & to_string(rx_data, HEX, AS_IS, INCL_RADIX) & ")"; -- Helper variables variable v_tx_data : std_logic_vector(rx_data'length-1 downto 0) := (others => '0'); begin spi_slave_transmit_and_receive(v_tx_data, rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call); end; -- Multi-word procedure spi_slave_receive ( variable rx_data : out t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ) is constant local_proc_name : string := "spi_slave_receive"; constant local_proc_call : string := local_proc_name & "(" & to_string(rx_data, HEX, AS_IS, INCL_RADIX) & ")"; -- Helper variables variable v_rx_data : t_slv_array(rx_data'length-1 downto 0)(rx_data(0)'length-1 downto 0) := (others => (others => '0')); begin -- call multi-word procedure spi_slave_transmit_and_receive(v_rx_data, rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call); end; --------------------------------------------------------------------------------- -- spi_slave_check --------------------------------------------------------------------------------- procedure spi_slave_check ( constant data_exp : in std_logic_vector; constant msg : in string; signal spi_if : inout t_spi_if; constant alert_level : in t_alert_level := error; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ) is constant local_proc_name : string := "spi_slave_check"; constant local_proc_call : string := local_proc_name & "(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")"; -- Helper variables variable v_rx_data : std_logic_vector(data_exp'length-1 downto 0) := (others => 'X'); variable v_tx_data : std_logic_vector(data_exp'length-1 downto 0) := (others => '0'); variable v_check_ok : boolean := true; variable v_alert_radix : t_radix; begin spi_slave_transmit_and_receive(v_tx_data, v_rx_data, msg, spi_if, when_to_start_transfer, scope, msg_id_panel, config, local_proc_call); for i in data_exp'range loop -- Allow don't care in expected value and use match strictness from config for comparison if data_exp(i) = '-' or check_value(v_rx_data(i), data_exp(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then v_check_ok := true; else v_check_ok := false; exit; end if; end loop; if not v_check_ok then -- Use binary representation when mismatch is due to weak signals v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_data, data_exp, MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX; alert(alert_level, local_proc_call & "=> Failed. Was " & to_string(v_rx_data, v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " & to_string(data_exp, v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope); else log(config.id_for_bfm, local_proc_call & "=> OK, read data = " & to_string(v_rx_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel); end if; end procedure; -- Multi-word procedure spi_slave_check ( constant data_exp : in t_slv_array; constant msg : in string; signal spi_if : inout t_spi_if; constant alert_level : in t_alert_level := error; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS; constant scope : in string := C_SCOPE; constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel; constant config : in t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT ) is begin for idx in 0 to (data_exp'length-1) loop -- call singl-word procedure - will handle error check spi_slave_check(data_exp(idx), msg, spi_if, alert_level, when_to_start_transfer, scope, msg_id_panel, config); end loop; end procedure; end package body spi_bfm_pkg; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library uvvm_util; context uvvm_util.uvvm_util_context; library uvvm_vvc_framework; use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all; use work.spi_bfm_pkg.all; use work.vvc_cmd_pkg.all; use work.td_vvc_framework_common_methods_pkg.all; use work.td_target_support_pkg.all; package vvc_methods_pkg is --=============================================================================================== -- Types and constants for the SPI VVC --=============================================================================================== constant C_VVC_NAME : string := "SPI_VVC"; signal SPI_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME); alias THIS_VVCT : t_vvc_target_record is SPI_VVCT; alias t_bfm_config is t_spi_bfm_config; constant C_SPI_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := ( delay_type => NO_DELAY, delay_in_time => 0 ns, inter_bfm_delay_violation_severity => warning ); type t_vvc_config is record inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay. cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR. cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if command queue is almost full. Will be ignored if set to 0. cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full. result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if result queue is almost full. Will be ignored if set to 0. result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold bfm_config : t_spi_bfm_config; -- Configuration for the BFM. See BFM quick reference msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel end record; type t_vvc_config_array is array (natural range <>) of t_vvc_config; constant C_SPI_VVC_CONFIG_DEFAULT : t_vvc_config := ( inter_bfm_delay => C_SPI_INTER_BFM_DELAY_DEFAULT, cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX, cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY, cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD, result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX, result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY, result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD, bfm_config => C_SPI_BFM_CONFIG_DEFAULT, msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT ); type t_vvc_status is record current_cmd_idx : natural; previous_cmd_idx : natural; pending_cmd_cnt : natural; end record; type t_vvc_status_array is array (natural range <>) of t_vvc_status; constant C_VVC_STATUS_DEFAULT : t_vvc_status := ( current_cmd_idx => 0, previous_cmd_idx => 0, pending_cmd_cnt => 0 ); -- Transaction information for the wave view during simulation type t_transaction_info is record operation : t_operation; msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH); tx_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0); rx_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0); data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0); num_words : natural; word_length : natural; end record; type t_transaction_info_array is array (natural range <>) of t_transaction_info; constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := ( tx_data => (others => (others => '0')), rx_data => (others => (others => '0')), data_exp => (others => (others => '0')), num_words => 0, word_length => 0, operation => NO_OPERATION, msg => (others => ' ') ); shared variable shared_spi_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_SPI_VVC_CONFIG_DEFAULT); shared variable shared_spi_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_VVC_STATUS_DEFAULT); shared variable shared_spi_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM) := (others => C_TRANSACTION_INFO_DEFAULT); --============================================================================== -- Methods dedicated to this VVC -- - These procedures are called from the testbench in order to queue BFM calls -- in the VVC command queue. The VVC will store and forward these calls to the -- SPI BFM when the command is at the from of the VVC command queue. -- - For details on how the BFM procedures work, see spi_bfm_pkg.vhd or the -- quickref. --============================================================================== ---------------------------------------------------------- -- SPI_MASTER ---------------------------------------------------------- -- Single-word procedure spi_master_transmit_and_receive( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in std_logic_vector; constant msg : in string; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER ); -- Multi-word procedure spi_master_transmit_and_receive( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in t_slv_array; constant msg : in string; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS ); -- Single-word procedure spi_master_transmit_and_check( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in std_logic_vector; constant data_exp : in std_logic_vector; constant msg : in string; constant alert_level : in t_alert_level := error; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER ); -- Multi-word procedure spi_master_transmit_and_check( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in t_slv_array; constant data_exp : in t_slv_array; constant msg : in string; constant alert_level : in t_alert_level := error; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS ); -- Single-word procedure spi_master_transmit_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in std_logic_vector; constant msg : in string; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER ); -- Multi-word procedure spi_master_transmit_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in t_slv_array; constant msg : in string; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS ); procedure spi_master_receive_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant msg : in string; constant num_words : in positive := 1; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS ); -- Single-word procedure spi_master_check_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data_exp : in std_logic_vector; constant msg : in string; constant alert_level : in t_alert_level := error; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER ); -- Multi-word procedure spi_master_check_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data_exp : in t_slv_array; constant msg : in string; constant alert_level : in t_alert_level := error; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS ); ---------------------------------------------------------- -- SPI_SLAVE ---------------------------------------------------------- -- Single-word procedure spi_slave_transmit_and_receive( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in std_logic_vector; constant msg : in string; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ); -- Multi-word procedure spi_slave_transmit_and_receive( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in t_slv_array; constant msg : in string; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ); -- Single-word procedure spi_slave_transmit_and_check( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in std_logic_vector; constant data_exp : in std_logic_vector; constant msg : in string; constant alert_level : in t_alert_level := error; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ); -- Multi-word procedure spi_slave_transmit_and_check( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in t_slv_array; constant data_exp : in t_slv_array; constant msg : in string; constant alert_level : in t_alert_level := error; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ); -- Single-word procedure spi_slave_transmit_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in std_logic_vector; constant msg : in string; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ); -- Multi-word procedure spi_slave_transmit_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in t_slv_array; constant msg : in string; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ); procedure spi_slave_receive_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant msg : in string; constant num_words : in positive := 1; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ); -- Single-word procedure spi_slave_check_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data_exp : in std_logic_vector; constant msg : in string; constant alert_level : in t_alert_level := error; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ); -- Multi-word procedure spi_slave_check_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data_exp : in t_slv_array; constant msg : in string; constant alert_level : in t_alert_level := error; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ); end package vvc_methods_pkg; package body vvc_methods_pkg is --============================================================================== -- Methods dedicated to this VVC -- Notes: -- - shared_vvc_cmd is initialised to C_VVC_CMD_DEFAULT, and also reset to this after every command --============================================================================== ---------------------------------------------------------- -- SPI_MASTER ---------------------------------------------------------- -- Single-word procedure spi_master_transmit_and_receive( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in std_logic_vector; constant msg : in string; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; -- Helper variable variable v_word_length : natural := data'length; variable v_num_words : natural := 1; variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); begin -- normalize v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_AND_RECEIVE); shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0); shared_vvc_cmd.num_words := v_num_words; shared_vvc_cmd.word_length := v_word_length; shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done; shared_vvc_cmd.action_between_words := RELEASE_LINE_BETWEEN_WORDS; send_command_to_vvc(VVCT); end procedure; -- Multi-word procedure spi_master_transmit_and_receive( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in t_slv_array; constant msg : in string; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; -- Helper variable variable v_word_length : natural := data(0)'length; variable v_num_words : natural := data'length; variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); begin -- normalize v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_AND_RECEIVE); shared_vvc_cmd.data := v_normalized_data; shared_vvc_cmd.num_words := v_num_words; shared_vvc_cmd.word_length := v_word_length; shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done; shared_vvc_cmd.action_between_words := action_between_words; send_command_to_vvc(VVCT); end procedure; -- Single-word procedure spi_master_transmit_and_check( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in std_logic_vector; constant data_exp : in std_logic_vector; constant msg : in string; constant alert_level : in t_alert_level := error; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; -- Helper variable variable v_word_length : natural := data'length; variable v_num_words : natural := 1; variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); begin -- normalize to t_slv_array v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); v_normalized_data_exp(0) := normalize_and_check(data_exp, shared_vvc_cmd.data_exp(0), ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_AND_CHECK); shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0); shared_vvc_cmd.data_exp(0)(v_word_length-1 downto 0) := v_normalized_data_exp(0)(v_word_length-1 downto 0); shared_vvc_cmd.num_words := v_num_words; shared_vvc_cmd.word_length := v_word_length; shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done; shared_vvc_cmd.alert_level := alert_level; send_command_to_vvc(VVCT); end procedure; -- Multi-word procedure spi_master_transmit_and_check( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in t_slv_array; constant data_exp : in t_slv_array; constant msg : in string; constant alert_level : in t_alert_level := error; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; -- Helper variable variable v_word_length : natural := data(0)'length; variable v_num_words : natural := data'length; variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); begin -- normalize v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); v_normalized_data_exp := normalize_and_check(data_exp, shared_vvc_cmd.data_exp, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_AND_CHECK); shared_vvc_cmd.data := v_normalized_data; shared_vvc_cmd.data_exp := v_normalized_data_exp; shared_vvc_cmd.num_words := v_num_words; shared_vvc_cmd.word_length := v_word_length; shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done; shared_vvc_cmd.action_between_words := action_between_words; shared_vvc_cmd.alert_level := alert_level; send_command_to_vvc(VVCT); end procedure; -- Single-word procedure spi_master_transmit_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in std_logic_vector; constant msg : in string; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; -- Helper variable variable v_word_length : natural := data'length; variable v_num_words : natural := 1; variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); begin -- normalize to t_slv_array v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_ONLY); shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0); shared_vvc_cmd.num_words := v_num_words; shared_vvc_cmd.word_length := v_word_length; shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done; send_command_to_vvc(VVCT); end procedure; -- Multi-word procedure spi_master_transmit_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in t_slv_array; constant msg : in string; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; -- Helper variable variable v_word_length : natural := data(0)'length; variable v_num_words : natural := data'length; variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); begin -- normalize v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_TRANSMIT_ONLY); shared_vvc_cmd.data := v_normalized_data; shared_vvc_cmd.num_words := v_num_words; shared_vvc_cmd.word_length := v_word_length; shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done; shared_vvc_cmd.action_between_words := action_between_words; send_command_to_vvc(VVCT); end procedure; -- Single-word procedure spi_master_receive_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant msg : in string; constant num_words : in positive := 1; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- Locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_RECEIVE_ONLY); shared_vvc_cmd.num_words := num_words; shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done; shared_vvc_cmd.action_between_words := action_between_words; send_command_to_vvc(VVCT); end procedure; -- Single-word procedure spi_master_check_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data_exp : in std_logic_vector; constant msg : in string; constant alert_level : in t_alert_level := error; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; -- Helper variable variable v_word_length : natural := data_exp'length; variable v_num_words : natural := 1; variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); begin -- normalize to t_slv_array v_normalized_data_exp(0) := normalize_and_check(data_exp, shared_vvc_cmd.data_exp(0), ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_CHECK_ONLY); shared_vvc_cmd.data_exp(0)(v_word_length-1 downto 0) := v_normalized_data_exp(0)(v_word_length-1 downto 0); shared_vvc_cmd.num_words := v_num_words; shared_vvc_cmd.word_length := v_word_length; shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done; shared_vvc_cmd.alert_level := alert_level; send_command_to_vvc(VVCT); end procedure; -- Multi-word procedure spi_master_check_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data_exp : in t_slv_array; constant msg : in string; constant alert_level : in t_alert_level := error; constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER; constant action_between_words : in t_action_between_words := HOLD_LINE_BETWEEN_WORDS ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; -- Helper variable variable v_word_length : natural := data_exp(0)'length; variable v_num_words : natural := data_exp'length; variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); begin -- normalize v_normalized_data_exp := normalize_and_check(data_exp, shared_vvc_cmd.data_exp, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, MASTER_CHECK_ONLY); shared_vvc_cmd.data_exp := v_normalized_data_exp; shared_vvc_cmd.num_words := v_num_words; shared_vvc_cmd.word_length := v_word_length; shared_vvc_cmd.action_when_transfer_is_done := action_when_transfer_is_done; shared_vvc_cmd.action_between_words := action_between_words; shared_vvc_cmd.alert_level := alert_level; send_command_to_vvc(VVCT); end procedure; ---------------------------------------------------------- -- SPI_SLAVE ---------------------------------------------------------- -- Single-word procedure spi_slave_transmit_and_receive( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in std_logic_vector; constant msg : in string; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; -- Helper variable variable v_word_length : natural := data'length; variable v_num_words : natural := 1; variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); begin -- normalize to t_slv_array v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_AND_RECEIVE); shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0); shared_vvc_cmd.num_words := v_num_words; shared_vvc_cmd.word_length := v_word_length; shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer; send_command_to_vvc(VVCT); end procedure; -- Multi-word procedure spi_slave_transmit_and_receive( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in t_slv_array; constant msg : in string; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; -- Helper variable variable v_word_length : natural := data(0)'length; variable v_num_words : natural := data'length; variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); begin -- normalize v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_AND_RECEIVE); shared_vvc_cmd.data := v_normalized_data; shared_vvc_cmd.num_words := v_num_words; shared_vvc_cmd.word_length := v_word_length; shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer; send_command_to_vvc(VVCT); end procedure; -- Single-word procedure spi_slave_transmit_and_check( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in std_logic_vector; constant data_exp : in std_logic_vector; constant msg : in string; constant alert_level : in t_alert_level := error; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; -- Helper variable variable v_word_length : natural := data'length; variable v_num_words : natural := 1; variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); begin -- normalize to t_slv_array v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); v_normalized_data_exp(0) := normalize_and_check(data_exp, shared_vvc_cmd.data_exp(0), ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_AND_CHECK); shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0); shared_vvc_cmd.data_exp(0)(v_word_length-1 downto 0) := v_normalized_data_exp(0)(v_word_length-1 downto 0); shared_vvc_cmd.num_words := v_num_words; shared_vvc_cmd.word_length := v_word_length; shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer; shared_vvc_cmd.alert_level := alert_level; send_command_to_vvc(VVCT); end procedure; -- Multi-word procedure spi_slave_transmit_and_check( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in t_slv_array; constant data_exp : in t_slv_array; constant msg : in string; constant alert_level : in t_alert_level := error; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; -- Helper variable variable v_word_length : natural := data(0)'length; variable v_num_words : natural := data'length; variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); begin -- normalize v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); v_normalized_data_exp := normalize_and_check(data_exp, shared_vvc_cmd.data_exp, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_AND_CHECK); shared_vvc_cmd.data := v_normalized_data; shared_vvc_cmd.data_exp := v_normalized_data_exp; shared_vvc_cmd.num_words := v_num_words; shared_vvc_cmd.word_length := v_word_length; shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer; shared_vvc_cmd.alert_level := alert_level; send_command_to_vvc(VVCT); end procedure; -- Single-word procedure spi_slave_transmit_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in std_logic_vector; constant msg : in string; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; -- Helper variable variable v_word_length : natural := data'length; variable v_num_words : natural := 1; variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); begin -- normalize to t_slv_array v_normalized_data(0) := normalize_and_check(data, shared_vvc_cmd.data(0), ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_ONLY); shared_vvc_cmd.data(0)(v_word_length-1 downto 0) := v_normalized_data(0)(v_word_length-1 downto 0); shared_vvc_cmd.num_words := v_num_words; shared_vvc_cmd.word_length := v_word_length; shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer; send_command_to_vvc(VVCT); end procedure; -- Multi-word procedure spi_slave_transmit_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data : in t_slv_array; constant msg : in string; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; -- Helper variable variable v_word_length : natural := data(0)'length; variable v_num_words : natural := data'length; variable v_normalized_data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); begin -- normalize v_normalized_data := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_TRANSMIT_ONLY); shared_vvc_cmd.data := v_normalized_data; shared_vvc_cmd.num_words := v_num_words; shared_vvc_cmd.word_length := v_word_length; shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer; send_command_to_vvc(VVCT); end procedure; -- Single-word procedure spi_slave_receive_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant msg : in string; constant num_words : in positive := 1; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_RECEIVE_ONLY); shared_vvc_cmd.num_words := num_words; shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer; send_command_to_vvc(VVCT); end procedure; -- Single-word procedure spi_slave_check_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data_exp : in std_logic_vector; constant msg : in string; constant alert_level : in t_alert_level := error; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; -- Helper variable variable v_word_length : natural := data_exp'length; variable v_num_words : natural := 1; variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); begin -- normalize to t_slv_array v_normalized_data_exp(0) := normalize_and_check(data_exp, shared_vvc_cmd.data_exp(0), ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_CHECK_ONLY); --shared_vvc_cmd.data_exp := v_normalized_data_exp; shared_vvc_cmd.data_exp(0)(v_word_length-1 downto 0) := v_normalized_data_exp(0)(v_word_length-1 downto 0); shared_vvc_cmd.num_words := v_num_words; shared_vvc_cmd.word_length := v_word_length; shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer; shared_vvc_cmd.alert_level := alert_level; send_command_to_vvc(VVCT); end procedure; -- Multi-word procedure spi_slave_check_only( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data_exp : in t_slv_array; constant msg : in string; constant alert_level : in t_alert_level := error; constant when_to_start_transfer : in t_when_to_start_transfer := START_TRANSFER_ON_NEXT_SS ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) & ")"; -- Helper variable variable v_word_length : natural := data_exp(0)'length; variable v_num_words : natural := data_exp'length; variable v_normalized_data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0) := (others => (others => '0')); begin -- normalize v_normalized_data_exp := normalize_and_check(data_exp, shared_vvc_cmd.data_exp, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record shared_vvc_cmd := C_VVC_CMD_DEFAULT; -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SLAVE_CHECK_ONLY); shared_vvc_cmd.data_exp := v_normalized_data_exp; shared_vvc_cmd.num_words := v_num_words; shared_vvc_cmd.word_length := v_word_length; shared_vvc_cmd.when_to_start_transfer := when_to_start_transfer; shared_vvc_cmd.alert_level := alert_level; send_command_to_vvc(VVCT); end procedure; end package body vvc_methods_pkg; |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY XilinxCoreLib; ENTITY Instr_Mem IS PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END Instr_Mem; ARCHITECTURE Instr_Mem_a OF Instr_Mem IS COMPONENT wrapped_Instr_Mem PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; FOR ALL : wrapped_Instr_Mem USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral) GENERIC MAP ( c_addra_width => 5, c_addrb_width => 5, c_algorithm => 1, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 0, c_default_data => "0", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_enable_32bit_address => 0, c_family => "spartan3", c_has_axi_id => 0, c_has_ena => 0, c_has_enb => 0, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file => "BlankString", c_init_file_name => "Instr_Mem.mif", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 1, c_mem_type => 0, c_mux_pipeline_stages => 0, c_prim_type => 1, c_read_depth_a => 32, c_read_depth_b => 32, c_read_width_a => 16, c_read_width_b => 16, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_bram_block => 0, c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 0, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 32, c_write_depth_b => 32, c_write_mode_a => "WRITE_FIRST", c_write_mode_b => "WRITE_FIRST", c_write_width_a => 16, c_write_width_b => 16, c_xdevicefamily => "spartan3e" ); BEGIN U0 : wrapped_Instr_Mem PORT MAP ( clka => clka, wea => wea, addra => addra, dina => dina, douta => douta ); END Instr_Mem_a; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity SSegDriver is port ( CLK : in STD_LOGIC; -- 50 MHz input RST : in STD_LOGIC; EN : in STD_LOGIC; SEG_0 : in STD_LOGIC_VECTOR (3 downto 0); SEG_1 : in STD_LOGIC_VECTOR (3 downto 0); SEG_2 : in STD_LOGIC_VECTOR (3 downto 0); SEG_3 : in STD_LOGIC_VECTOR (3 downto 0); DP_CTRL : in STD_LOGIC_VECTOR (3 downto 0); COL_EN : in STD_LOGIC; SEG_OUT : out STD_LOGIC_VECTOR (6 downto 0); DP_OUT : out STD_LOGIC; AN_OUT : out STD_LOGIC_VECTOR (3 downto 0) ); end SSegDriver; architecture Behavioral of SSegDriver is signal hexnum : STD_LOGIC_VECTOR (3 downto 0); signal segnum : STD_LOGIC_VECTOR (6 downto 0); signal clk240hz : STD_LOGIC :='0'; -- 240Hz clock line ~= 4ms CONSTANT wait240hz : integer := 104166; -- (50E6/240)/2 = 104166.66 signal count240hz : integer range 0 to wait240hz := 0; signal pos : STD_LOGIC_VECTOR (1 downto 0); begin SEG_OUT <= segnum; with hexnum select segnum <= "1000000" when "0000", -- 0 "1111001" when "0001", -- 1 "0100100" when "0010", -- 2 "0110000" when "0011", -- 3 "0011001" when "0100", -- 4 "0010010" when "0101", -- 5 "0000010" when "0110", -- 6 "1111000" when "0111", -- 7 "0000000" when "1000", -- 8 "0010000" when "1001", -- 9 "0001000" when "1010", -- A "0000011" when "1011", -- B "1000110" when "1100", -- C "0100001" when "1101", -- D "0000110" when "1110", -- E "0001110" when "1111", -- F "1111111" when others; -- Invalid number clk_div_240hz: process (RST, CLK, EN) begin if (RST = '1') then clk240hz <= '0'; count240hz <= 0; elsif (rising_edge(CLK) and EN = '1') then if (count240hz = wait240hz) then if(clk240hz='0') then clk240hz <= '1'; else clk240hz <= '0'; end if; count240hz <= 0; else count240hz <= count240hz + 1; end if; end if; end process; disp_driver: process (RST, CLK) begin if (RST = '1') then pos <= "00"; hexnum <= (others => '0'); DP_OUT <= '1'; AN_OUT <= (others => '0'); elsif rising_edge(clk240hz) then pos <= pos + 1; if (pos = "11") then pos <= "00"; end if; case (pos) is when "00" => hexnum <= SEG_0; AN_OUT <= "0111"; DP_OUT <= DP_CTRL(0); when "01" => hexnum <= SEG_1; AN_OUT <= "1011"; DP_OUT <= DP_CTRL(1); when "10" => hexnum <= SEG_2; AN_OUT <= "1101"; DP_OUT <= DP_CTRL(2); when "11" => hexnum <= SEG_3; AN_OUT <= "1110"; DP_OUT <= DP_CTRL(3); when others => hexnum <= (others => '0'); AN_OUT <= (others => '0'); end case; end if; end process; end Behavioral; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.pp_types.all; use work.pp_csr.all; use work.pp_utilities.all; entity pp_execute is port( clk : in std_logic; reset : in std_logic; stall, flush : in std_logic; -- Interrupt inputs: irq : in std_logic_vector(7 downto 0); software_interrupt, timer_interrupt : in std_logic; -- Data memory outputs: dmem_address : out std_logic_vector(31 downto 0); dmem_data_out : out std_logic_vector(31 downto 0); dmem_data_size : out std_logic_vector( 1 downto 0); dmem_read_req : out std_logic; dmem_write_req : out std_logic; -- Register addresses: rs1_addr_in, rs2_addr_in, rd_addr_in : in register_address; rd_addr_out : out register_address; -- Register values: rs1_data_in, rs2_data_in : in std_logic_vector(31 downto 0); rd_data_out : out std_logic_vector(31 downto 0); -- Constant values: shamt_in : in std_logic_vector(4 downto 0); immediate_in : in std_logic_vector(31 downto 0); -- Instruction address: pc_in : in std_logic_vector(31 downto 0); pc_out : out std_logic_vector(31 downto 0); -- Funct3 value from the instruction, used to choose which comparison -- is used when branching: funct3_in : in std_logic_vector(2 downto 0); -- CSR signals: csr_addr_in : in csr_address; csr_addr_out : out csr_address; csr_write_in : in csr_write_mode; csr_write_out : out csr_write_mode; csr_value_in : in std_logic_vector(31 downto 0); csr_value_out : out std_logic_vector(31 downto 0); csr_use_immediate_in : in std_logic; -- Control signals: alu_op_in : in alu_operation; alu_x_src_in : in alu_operand_source; alu_y_src_in : in alu_operand_source; rd_write_in : in std_logic; rd_write_out : out std_logic; branch_in : in branch_type; branch_out : out branch_type; -- Memory control signals: mem_op_in : in memory_operation_type; mem_op_out : out memory_operation_type; mem_size_in : in memory_operation_size; mem_size_out : out memory_operation_size; -- Whether the instruction should be counted: count_instruction_in : in std_logic; count_instruction_out : out std_logic; -- Exception control registers: ie_in, ie1_in : in std_logic; mie_in : in std_logic_vector(31 downto 0); mtvec_in : in std_logic_vector(31 downto 0); mtvec_out : out std_logic_vector(31 downto 0); --mepc_in : in std_logic_vector(31 downto 0); -- Exception signals: decode_exception_in : in std_logic; decode_exception_cause_in : in csr_exception_cause; -- Exception outputs: exception_out : out std_logic; exception_context_out : out csr_exception_context; -- Control outputs: jump_out : out std_logic; jump_target_out : out std_logic_vector(31 downto 0); -- Inputs to the forwarding logic from the MEM stage: mem_rd_write : in std_logic; mem_rd_addr : in register_address; mem_rd_value : in std_logic_vector(31 downto 0); mem_csr_addr : in csr_address; mem_csr_write : in csr_write_mode; mem_exception : in std_logic; -- Inputs to the forwarding logic from the WB stage: wb_rd_write : in std_logic; wb_rd_addr : in register_address; wb_rd_value : in std_logic_vector(31 downto 0); wb_csr_addr : in csr_address; wb_csr_write : in csr_write_mode; wb_exception : in std_logic; -- Hazard detection unit signals: mem_mem_op : in memory_operation_type; hazard_detected : out std_logic ); end entity pp_execute; architecture behaviour of pp_execute is signal alu_op : alu_operation; signal alu_x_src, alu_y_src : alu_operand_source; signal alu_x, alu_y, alu_result : std_logic_vector(31 downto 0); signal rs1_addr, rs2_addr : register_address; signal rs1_data, rs2_data : std_logic_vector(31 downto 0); signal mem_op : memory_operation_type; signal mem_size : memory_operation_size; signal pc : std_logic_vector(31 downto 0); signal immediate : std_logic_vector(31 downto 0); signal shamt : std_logic_vector( 4 downto 0); signal funct3 : std_logic_vector( 2 downto 0); signal rs1_forwarded, rs2_forwarded : std_logic_vector(31 downto 0); signal branch : branch_type; signal branch_condition : std_logic; signal do_jump : std_logic; signal jump_target : std_logic_vector(31 downto 0); signal mie, mtvec : std_logic_vector(31 downto 0); signal csr_write : csr_write_mode; signal csr_addr : csr_address; signal csr_use_immediate : std_logic; signal csr_value : std_logic_vector(31 downto 0); signal decode_exception : std_logic; signal decode_exception_cause : csr_exception_cause; signal exception_taken : std_logic; signal exception_cause : csr_exception_cause; signal exception_addr : std_logic_vector(31 downto 0); signal data_misaligned, instr_misaligned : std_logic; signal irq_asserted : std_logic; signal irq_asserted_num : std_logic_vector(3 downto 0); signal load_hazard_detected, csr_hazard_detected : std_logic; begin -- Register values should not be latched in by a clocked process, -- this is already done in the register files. csr_value <= csr_value_in; rd_data_out <= alu_result; branch_out <= branch; mem_op_out <= mem_op; mem_size_out <= mem_size; csr_write_out <= csr_write; csr_addr_out <= csr_addr; pc_out <= pc; hazard_detected <= load_hazard_detected or csr_hazard_detected; exception_out <= exception_taken; exception_context_out <= ( ie => ie_in, ie1 => ie1_in, cause => exception_cause, badaddr => exception_addr); do_jump <= (to_std_logic(branch = BRANCH_JUMP or branch = BRANCH_JUMP_INDIRECT) or (to_std_logic(branch = BRANCH_CONDITIONAL) and branch_condition) or to_std_logic(branch = BRANCH_SRET)) and not stall; jump_out <= do_jump; jump_target_out <= jump_target; mtvec_out <= std_logic_vector(unsigned(mtvec)); exception_taken <= not stall and (decode_exception or to_std_logic(exception_cause /= CSR_CAUSE_NONE)); irq_asserted <= to_std_logic(ie_in = '1' and (irq and mie(31 downto 24)) /= x"00"); rs1_data <= rs1_data_in; rs2_data <= rs2_data_in; dmem_address <= alu_result when (mem_op /= MEMOP_TYPE_NONE and mem_op /= MEMOP_TYPE_INVALID) and exception_taken = '0' else (others => '0'); dmem_data_out <= rs2_forwarded; dmem_write_req <= '1' when mem_op = MEMOP_TYPE_STORE and exception_taken = '0' else '0'; dmem_read_req <= '1' when memop_is_load(mem_op) and exception_taken = '0' else '0'; pipeline_register: process(clk) begin if rising_edge(clk) then if reset = '1' or flush = '1' then rd_write_out <= '0'; branch <= BRANCH_NONE; csr_write <= CSR_WRITE_NONE; mem_op <= MEMOP_TYPE_NONE; decode_exception <= '0'; count_instruction_out <= '0'; elsif stall = '1' then csr_write <= CSR_WRITE_NONE; elsif stall = '0' then pc <= pc_in; count_instruction_out <= count_instruction_in; -- Register signals: rd_write_out <= rd_write_in; rd_addr_out <= rd_addr_in; rs1_addr <= rs1_addr_in; rs2_addr <= rs2_addr_in; -- ALU signals: alu_op <= alu_op_in; alu_x_src <= alu_x_src_in; alu_y_src <= alu_y_src_in; -- Control signals: branch <= branch_in; mem_op <= mem_op_in; mem_size <= mem_size_in; -- Constant values: immediate <= immediate_in; shamt <= shamt_in; funct3 <= funct3_in; -- CSR signals: csr_write <= csr_write_in; csr_addr <= csr_addr_in; csr_use_immediate <= csr_use_immediate_in; -- Exception vector base: mtvec <= mtvec_in; mie <= mie_in; -- Instruction decoder exceptions: decode_exception <= decode_exception_in; decode_exception_cause <= decode_exception_cause_in; end if; end if; end process pipeline_register; set_data_size: process(mem_size) begin case mem_size is when MEMOP_SIZE_BYTE => dmem_data_size <= b"01"; when MEMOP_SIZE_HALFWORD => dmem_data_size <= b"10"; when MEMOP_SIZE_WORD => dmem_data_size <= b"00"; when others => dmem_data_size <= b"11"; end case; end process set_data_size; get_irq_num: process(irq, mie) variable temp : std_logic_vector(3 downto 0); begin temp := (others => '0'); for i in 0 to 7 loop if irq(i) = '1' and mie(24 + i) = '1' then temp := std_logic_vector(to_unsigned(i, temp'length)); exit; end if; end loop; irq_asserted_num <= temp; end process get_irq_num; data_misalign_check: process(mem_size, alu_result) begin case mem_size is when MEMOP_SIZE_HALFWORD => if alu_result(0) /= '0' then data_misaligned <= '1'; else data_misaligned <= '0'; end if; when MEMOP_SIZE_WORD => if alu_result(1 downto 0) /= b"00" then data_misaligned <= '1'; else data_misaligned <= '0'; end if; when others => data_misaligned <= '0'; end case; end process data_misalign_check; instr_misalign_check: process(jump_target, branch, branch_condition, do_jump) begin if jump_target(1 downto 0) /= b"00" and do_jump = '1' then instr_misaligned <= '1'; else instr_misaligned <= '0'; end if; end process instr_misalign_check; find_exception_cause: process(decode_exception, decode_exception_cause, mem_op, data_misaligned, instr_misaligned, irq_asserted, irq_asserted_num, mie, software_interrupt, timer_interrupt, ie_in) begin if irq_asserted = '1' then exception_cause <= std_logic_vector(unsigned(CSR_CAUSE_IRQ_BASE) + unsigned(irq_asserted_num)); elsif software_interrupt = '1' and mie(CSR_MIE_MSIE) = '1' and ie_in = '1' then exception_cause <= CSR_CAUSE_SOFTWARE_INT; elsif timer_interrupt = '1' and mie(CSR_MIE_MTIE) = '1' and ie_in = '1' then exception_cause <= CSR_CAUSE_TIMER_INT; elsif decode_exception = '1' then exception_cause <= decode_exception_cause; elsif mem_op = MEMOP_TYPE_INVALID then exception_cause <= CSR_CAUSE_INVALID_INSTR; elsif instr_misaligned = '1' then exception_cause <= CSR_CAUSE_INSTR_MISALIGN; elsif data_misaligned = '1' and mem_op = MEMOP_TYPE_STORE then exception_cause <= CSR_CAUSE_STORE_MISALIGN; elsif data_misaligned = '1' and memop_is_load(mem_op) then exception_cause <= CSR_CAUSE_LOAD_MISALIGN; else exception_cause <= CSR_CAUSE_NONE; end if; end process find_exception_cause; find_exception_addr: process(instr_misaligned, data_misaligned, jump_target, alu_result) begin if instr_misaligned = '1' then exception_addr <= jump_target; elsif data_misaligned = '1' then exception_addr <= alu_result; else exception_addr <= (others => '0'); end if; end process find_exception_addr; calc_jump_tgt: process(branch, pc, rs1_forwarded, immediate, csr_value) begin case branch is when BRANCH_JUMP | BRANCH_CONDITIONAL => jump_target <= std_logic_vector(unsigned(pc) + unsigned(immediate)); when BRANCH_JUMP_INDIRECT => jump_target <= std_logic_vector(unsigned(rs1_forwarded) + unsigned(immediate)); when BRANCH_SRET => jump_target <= csr_value; when others => jump_target <= (others => '0'); end case; end process calc_jump_tgt; alu_x_mux: entity work.pp_alu_mux port map( source => alu_x_src, register_value => rs1_forwarded, immediate_value => immediate, shamt_value => shamt, pc_value => pc, csr_value => csr_value, output => alu_x ); alu_y_mux: entity work.pp_alu_mux port map( source => alu_y_src, register_value => rs2_forwarded, immediate_value => immediate, shamt_value => shamt, pc_value => pc, csr_value => csr_value, output => alu_y ); alu_x_forward: process(mem_rd_write, mem_rd_value, mem_rd_addr, rs1_addr, rs1_data, wb_rd_write, wb_rd_addr, wb_rd_value) begin if mem_rd_write = '1' and mem_rd_addr = rs1_addr and mem_rd_addr /= b"00000" then rs1_forwarded <= mem_rd_value; elsif wb_rd_write = '1' and wb_rd_addr = rs1_addr and wb_rd_addr /= b"00000" then rs1_forwarded <= wb_rd_value; else rs1_forwarded <= rs1_data; end if; end process alu_x_forward; alu_y_forward: process(mem_rd_write, mem_rd_value, mem_rd_addr, rs2_addr, rs2_data, wb_rd_write, wb_rd_addr, wb_rd_value) begin if mem_rd_write = '1' and mem_rd_addr = rs2_addr and mem_rd_addr /= b"00000" then rs2_forwarded <= mem_rd_value; elsif wb_rd_write = '1' and wb_rd_addr = rs2_addr and wb_rd_addr /= b"00000" then rs2_forwarded <= wb_rd_value; else rs2_forwarded <= rs2_data; end if; end process alu_y_forward; detect_csr_hazard: process(mem_csr_write, wb_csr_write, mem_exception, wb_exception) begin if mem_csr_write /= CSR_WRITE_NONE or wb_csr_write /= CSR_WRITE_NONE or mem_exception = '1' or wb_exception = '1' then csr_hazard_detected <= '1'; else csr_hazard_detected <= '0'; end if; end process detect_csr_hazard; detect_load_hazard: process(mem_mem_op, mem_rd_addr, rs1_addr, rs2_addr, alu_x_src, alu_y_src) begin if (mem_mem_op = MEMOP_TYPE_LOAD or mem_mem_op = MEMOP_TYPE_LOAD_UNSIGNED) and ((alu_x_src = ALU_SRC_REG and mem_rd_addr = rs1_addr and rs1_addr /= b"00000") or (alu_y_src = ALU_SRC_REG and mem_rd_addr = rs2_addr and rs2_addr /= b"00000")) then load_hazard_detected <= '1'; else load_hazard_detected <= '0'; end if; end process detect_load_hazard; branch_comparator: entity work.pp_comparator port map( funct3 => funct3, rs1 => rs1_forwarded, rs2 => rs2_forwarded, result => branch_condition ); alu_instance: entity work.pp_alu port map( result => alu_result, x => alu_x, y => alu_y, operation => alu_op ); csr_alu_instance: entity work.pp_csr_alu port map( x => csr_value, y => rs1_forwarded, result => csr_value_out, immediate => rs1_addr, use_immediate => csr_use_immediate, write_mode => csr_write ); end architecture behaviour; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library std; use std.textio.all; library work; use work.all; use work.procedures.all; entity tb_mp is end tb_mp; architecture behav of tb_mp is signal rst : std_logic := '1'; signal clk : std_logic := '0'; signal pdata : t_data2 := (others => '0'); signal pdata_rd : std_logic := '0'; signal start : std_logic := '0'; signal busy : std_logic := '0'; signal mem_addra : std_logic_vector(9 downto 0) := (others => '0'); signal mem_ena : std_logic := '0'; signal mem_doa : t_data := (others => '0'); signal mem_addrb : std_logic_vector(9 downto 0) := (others => '0'); signal mem_enb : std_logic := '0'; signal mem_dob : t_data := (others => '0'); signal reg_addra: t_data := (others => '0'); signal reg_ena : std_logic := '0'; signal reg_doa : t_data := (others => '0'); signal reg_addrb: t_data := (others => '0'); signal reg_enb : std_logic := '0'; signal reg_dob : t_data := (others => '0'); signal clk2x : std_logic := '0'; procedure prog_cmd(cmd : in t_vliw; which : in natural; signal start : out std_logic; signal pdata : out t_data2) is variable tmp : std_logic_vector(VLIW_HIGH downto 0); begin tmp := vliw2slv(cmd); start <= '1'; pdata <= "1111111111111" & std_logic_vector(to_unsigned(which, 3)); wait for 20 ns; start <= '0'; for i in 0 to VLIW_HIGH/16-1 loop pdata <= tmp((i+1)*16-1 downto i*16); wait for 20 ns; end loop; pdata(VLIW_HIGH mod 16 downto 0) <= tmp(VLIW_HIGH downto (VLIW_HIGH/16)*16); wait for 40 ns; end procedure; type int_arr is array(natural range <>) of integer; signal sine_wave : int_arr(0 to 255) := (0, 26, 52, 75, 95, 110, 121, 127, 127, 121, 110, 95, 75, 52, 26, 0, -26, -52, -75, -95, -110, -121, -127, -127, -121, -110, -95, -75, -52, -26, 0, 26, 52, 75, 95, 110, 121, 127, 127, 121, 110, 95, 75, 52, 26, 0, -26, -52, -75, -95, -110, -121, -127, -127, -121, -110, -95, -75, -52, -26, 0, 26, 52, 75, 95, 110, 121, 127, 127, 121, 110, 95, 75, 52, 26, 0, -26, -52, -75, -95, -110, -121, -127, -127, -121, -110, -95, -75, -52, -26, 0, 26, 52, 75, 95, 110, 121, 127, 127, 121, 110, 95, 75, 52, 26, 0, -26, -52, -75, -95, -110, -121, -127, -127, -121, -110, -95, -75, -52, -26, 0, 26, 52, 75, 95, 110, 121, 127, 127, 121, 110, 95, 75, 52, 26, 0, -26, -52, -75, -95, -110, -121, -127, -127, -121, -110, -95, -75, -52, -26, 0, 26, 52, 75, 95, 110, 121, 127, 127, 121, 110, 95, 75, 52, 26, 0, -26, -52, -75, -95, -110, -121, -127, -127, -121, -110, -95, -75, -52, -26, 0, 26, 52, 75, 95, 110, 121, 127, 127, 121, 110, 95, 75, 52, 26, 0, -26, -52, -75, -95, -110, -121, -127, -127, -121, -110, -95, -75, -52, -26, 0, 26, 52, 75, 95, 110, 121, 127, 127, 121, 110, 95, 75, 52, 26, 0, -26, -52, -75, -95, -110, -121, -127, -127, -121, -110, -95, -75, -52, -26, 0, 26, 52, 75, 95, 110, 121, 127, 127, 121, 110, 95, 75, 52, 26, 0); type int_arr_arr is array(natural range <>) of int_arr(0 to 3); signal bflys : int_arr_arr(0 to 1023) := ( (0, 1, 64, 0), (2, 3, 64, 0), (4, 5, 64, 0), (6, 7, 64, 0), (8, 9, 64, 0), (10, 11, 64, 0), (12, 13, 64, 0), (14, 15, 64, 0), (16, 17, 64, 0), (18, 19, 64, 0), (20, 21, 64, 0), (22, 23, 64, 0), (24, 25, 64, 0), (26, 27, 64, 0), (28, 29, 64, 0), (30, 31, 64, 0), (32, 33, 64, 0), (34, 35, 64, 0), (36, 37, 64, 0), (38, 39, 64, 0), (40, 41, 64, 0), (42, 43, 64, 0), (44, 45, 64, 0), (46, 47, 64, 0), (48, 49, 64, 0), (50, 51, 64, 0), (52, 53, 64, 0), (54, 55, 64, 0), (56, 57, 64, 0), (58, 59, 64, 0), (60, 61, 64, 0), (62, 63, 64, 0), (64, 65, 64, 0), (66, 67, 64, 0), (68, 69, 64, 0), (70, 71, 64, 0), (72, 73, 64, 0), (74, 75, 64, 0), (76, 77, 64, 0), (78, 79, 64, 0), (80, 81, 64, 0), (82, 83, 64, 0), (84, 85, 64, 0), (86, 87, 64, 0), (88, 89, 64, 0), (90, 91, 64, 0), (92, 93, 64, 0), (94, 95, 64, 0), (96, 97, 64, 0), (98, 99, 64, 0), (100, 101, 64, 0), (102, 103, 64, 0), (104, 105, 64, 0), (106, 107, 64, 0), (108, 109, 64, 0), (110, 111, 64, 0), (112, 113, 64, 0), (114, 115, 64, 0), (116, 117, 64, 0), (118, 119, 64, 0), (120, 121, 64, 0), (122, 123, 64, 0), (124, 125, 64, 0), (126, 127, 64, 0), (128, 129, 64, 0), (130, 131, 64, 0), (132, 133, 64, 0), (134, 135, 64, 0), (136, 137, 64, 0), (138, 139, 64, 0), (140, 141, 64, 0), (142, 143, 64, 0), (144, 145, 64, 0), (146, 147, 64, 0), (148, 149, 64, 0), (150, 151, 64, 0), (152, 153, 64, 0), (154, 155, 64, 0), (156, 157, 64, 0), (158, 159, 64, 0), (160, 161, 64, 0), (162, 163, 64, 0), (164, 165, 64, 0), (166, 167, 64, 0), (168, 169, 64, 0), (170, 171, 64, 0), (172, 173, 64, 0), (174, 175, 64, 0), (176, 177, 64, 0), (178, 179, 64, 0), (180, 181, 64, 0), (182, 183, 64, 0), (184, 185, 64, 0), (186, 187, 64, 0), (188, 189, 64, 0), (190, 191, 64, 0), (192, 193, 64, 0), (194, 195, 64, 0), (196, 197, 64, 0), (198, 199, 64, 0), (200, 201, 64, 0), (202, 203, 64, 0), (204, 205, 64, 0), (206, 207, 64, 0), (208, 209, 64, 0), (210, 211, 64, 0), (212, 213, 64, 0), (214, 215, 64, 0), (216, 217, 64, 0), (218, 219, 64, 0), (220, 221, 64, 0), (222, 223, 64, 0), (224, 225, 64, 0), (226, 227, 64, 0), (228, 229, 64, 0), (230, 231, 64, 0), (232, 233, 64, 0), (234, 235, 64, 0), (236, 237, 64, 0), (238, 239, 64, 0), (240, 241, 64, 0), (242, 243, 64, 0), (244, 245, 64, 0), (246, 247, 64, 0), (248, 249, 64, 0), (250, 251, 64, 0), (252, 253, 64, 0), (254, 255, 64, 0), (0, 2, 64, 0), (4, 6, 64, 0), (8, 10, 64, 0), (12, 14, 64, 0), (16, 18, 64, 0), (20, 22, 64, 0), (24, 26, 64, 0), (28, 30, 64, 0), (32, 34, 64, 0), (36, 38, 64, 0), (40, 42, 64, 0), (44, 46, 64, 0), (48, 50, 64, 0), (52, 54, 64, 0), (56, 58, 64, 0), (60, 62, 64, 0), (64, 66, 64, 0), (68, 70, 64, 0), (72, 74, 64, 0), (76, 78, 64, 0), (80, 82, 64, 0), (84, 86, 64, 0), (88, 90, 64, 0), (92, 94, 64, 0), (96, 98, 64, 0), (100, 102, 64, 0), (104, 106, 64, 0), (108, 110, 64, 0), (112, 114, 64, 0), (116, 118, 64, 0), (120, 122, 64, 0), (124, 126, 64, 0), (128, 130, 64, 0), (132, 134, 64, 0), (136, 138, 64, 0), (140, 142, 64, 0), (144, 146, 64, 0), (148, 150, 64, 0), (152, 154, 64, 0), (156, 158, 64, 0), (160, 162, 64, 0), (164, 166, 64, 0), (168, 170, 64, 0), (172, 174, 64, 0), (176, 178, 64, 0), (180, 182, 64, 0), (184, 186, 64, 0), (188, 190, 64, 0), (192, 194, 64, 0), (196, 198, 64, 0), (200, 202, 64, 0), (204, 206, 64, 0), (208, 210, 64, 0), (212, 214, 64, 0), (216, 218, 64, 0), (220, 222, 64, 0), (224, 226, 64, 0), (228, 230, 64, 0), (232, 234, 64, 0), (236, 238, 64, 0), (240, 242, 64, 0), (244, 246, 64, 0), (248, 250, 64, 0), (252, 254, 64, 0), (1, 3, 0, -64), (5, 7, 0, -64), (9, 11, 0, -64), (13, 15, 0, -64), (17, 19, 0, -64), (21, 23, 0, -64), (25, 27, 0, -64), (29, 31, 0, -64), (33, 35, 0, -64), (37, 39, 0, -64), (41, 43, 0, -64), (45, 47, 0, -64), (49, 51, 0, -64), (53, 55, 0, -64), (57, 59, 0, -64), (61, 63, 0, -64), (65, 67, 0, -64), (69, 71, 0, -64), (73, 75, 0, -64), (77, 79, 0, -64), (81, 83, 0, -64), (85, 87, 0, -64), (89, 91, 0, -64), (93, 95, 0, -64), (97, 99, 0, -64), (101, 103, 0, -64), (105, 107, 0, -64), (109, 111, 0, -64), (113, 115, 0, -64), (117, 119, 0, -64), (121, 123, 0, -64), (125, 127, 0, -64), (129, 131, 0, -64), (133, 135, 0, -64), (137, 139, 0, -64), (141, 143, 0, -64), (145, 147, 0, -64), (149, 151, 0, -64), (153, 155, 0, -64), (157, 159, 0, -64), (161, 163, 0, -64), (165, 167, 0, -64), (169, 171, 0, -64), (173, 175, 0, -64), (177, 179, 0, -64), (181, 183, 0, -64), (185, 187, 0, -64), (189, 191, 0, -64), (193, 195, 0, -64), (197, 199, 0, -64), (201, 203, 0, -64), (205, 207, 0, -64), (209, 211, 0, -64), (213, 215, 0, -64), (217, 219, 0, -64), (221, 223, 0, -64), (225, 227, 0, -64), (229, 231, 0, -64), (233, 235, 0, -64), (237, 239, 0, -64), (241, 243, 0, -64), (245, 247, 0, -64), (249, 251, 0, -64), (253, 255, 0, -64), (0, 4, 64, 0), (8, 12, 64, 0), (16, 20, 64, 0), (24, 28, 64, 0), (32, 36, 64, 0), (40, 44, 64, 0), (48, 52, 64, 0), (56, 60, 64, 0), (64, 68, 64, 0), (72, 76, 64, 0), (80, 84, 64, 0), (88, 92, 64, 0), (96, 100, 64, 0), (104, 108, 64, 0), (112, 116, 64, 0), (120, 124, 64, 0), (128, 132, 64, 0), (136, 140, 64, 0), (144, 148, 64, 0), (152, 156, 64, 0), (160, 164, 64, 0), (168, 172, 64, 0), (176, 180, 64, 0), (184, 188, 64, 0), (192, 196, 64, 0), (200, 204, 64, 0), (208, 212, 64, 0), (216, 220, 64, 0), (224, 228, 64, 0), (232, 236, 64, 0), (240, 244, 64, 0), (248, 252, 64, 0), (1, 5, 45, -45), (9, 13, 45, -45), (17, 21, 45, -45), (25, 29, 45, -45), (33, 37, 45, -45), (41, 45, 45, -45), (49, 53, 45, -45), (57, 61, 45, -45), (65, 69, 45, -45), (73, 77, 45, -45), (81, 85, 45, -45), (89, 93, 45, -45), (97, 101, 45, -45), (105, 109, 45, -45), (113, 117, 45, -45), (121, 125, 45, -45), (129, 133, 45, -45), (137, 141, 45, -45), (145, 149, 45, -45), (153, 157, 45, -45), (161, 165, 45, -45), (169, 173, 45, -45), (177, 181, 45, -45), (185, 189, 45, -45), (193, 197, 45, -45), (201, 205, 45, -45), (209, 213, 45, -45), (217, 221, 45, -45), (225, 229, 45, -45), (233, 237, 45, -45), (241, 245, 45, -45), (249, 253, 45, -45), (2, 6, 0, -64), (10, 14, 0, -64), (18, 22, 0, -64), (26, 30, 0, -64), (34, 38, 0, -64), (42, 46, 0, -64), (50, 54, 0, -64), (58, 62, 0, -64), (66, 70, 0, -64), (74, 78, 0, -64), (82, 86, 0, -64), (90, 94, 0, -64), (98, 102, 0, -64), (106, 110, 0, -64), (114, 118, 0, -64), (122, 126, 0, -64), (130, 134, 0, -64), (138, 142, 0, -64), (146, 150, 0, -64), (154, 158, 0, -64), (162, 166, 0, -64), (170, 174, 0, -64), (178, 182, 0, -64), (186, 190, 0, -64), (194, 198, 0, -64), (202, 206, 0, -64), (210, 214, 0, -64), (218, 222, 0, -64), (226, 230, 0, -64), (234, 238, 0, -64), (242, 246, 0, -64), (250, 254, 0, -64), (3, 7, -45, -45), (11, 15, -45, -45), (19, 23, -45, -45), (27, 31, -45, -45), (35, 39, -45, -45), (43, 47, -45, -45), (51, 55, -45, -45), (59, 63, -45, -45), (67, 71, -45, -45), (75, 79, -45, -45), (83, 87, -45, -45), (91, 95, -45, -45), (99, 103, -45, -45), (107, 111, -45, -45), (115, 119, -45, -45), (123, 127, -45, -45), (131, 135, -45, -45), (139, 143, -45, -45), (147, 151, -45, -45), (155, 159, -45, -45), (163, 167, -45, -45), (171, 175, -45, -45), (179, 183, -45, -45), (187, 191, -45, -45), (195, 199, -45, -45), (203, 207, -45, -45), (211, 215, -45, -45), (219, 223, -45, -45), (227, 231, -45, -45), (235, 239, -45, -45), (243, 247, -45, -45), (251, 255, -45, -45), (0, 8, 64, 0), (16, 24, 64, 0), (32, 40, 64, 0), (48, 56, 64, 0), (64, 72, 64, 0), (80, 88, 64, 0), (96, 104, 64, 0), (112, 120, 64, 0), (128, 136, 64, 0), (144, 152, 64, 0), (160, 168, 64, 0), (176, 184, 64, 0), (192, 200, 64, 0), (208, 216, 64, 0), (224, 232, 64, 0), (240, 248, 64, 0), (1, 9, 59, -24), (17, 25, 59, -24), (33, 41, 59, -24), (49, 57, 59, -24), (65, 73, 59, -24), (81, 89, 59, -24), (97, 105, 59, -24), (113, 121, 59, -24), (129, 137, 59, -24), (145, 153, 59, -24), (161, 169, 59, -24), (177, 185, 59, -24), (193, 201, 59, -24), (209, 217, 59, -24), (225, 233, 59, -24), (241, 249, 59, -24), (2, 10, 45, -45), (18, 26, 45, -45), (34, 42, 45, -45), (50, 58, 45, -45), (66, 74, 45, -45), (82, 90, 45, -45), (98, 106, 45, -45), (114, 122, 45, -45), (130, 138, 45, -45), (146, 154, 45, -45), (162, 170, 45, -45), (178, 186, 45, -45), (194, 202, 45, -45), (210, 218, 45, -45), (226, 234, 45, -45), (242, 250, 45, -45), (3, 11, 24, -59), (19, 27, 24, -59), (35, 43, 24, -59), (51, 59, 24, -59), (67, 75, 24, -59), (83, 91, 24, -59), (99, 107, 24, -59), (115, 123, 24, -59), (131, 139, 24, -59), (147, 155, 24, -59), (163, 171, 24, -59), (179, 187, 24, -59), (195, 203, 24, -59), (211, 219, 24, -59), (227, 235, 24, -59), (243, 251, 24, -59), (4, 12, 0, -64), (20, 28, 0, -64), (36, 44, 0, -64), (52, 60, 0, -64), (68, 76, 0, -64), (84, 92, 0, -64), (100, 108, 0, -64), (116, 124, 0, -64), (132, 140, 0, -64), (148, 156, 0, -64), (164, 172, 0, -64), (180, 188, 0, -64), (196, 204, 0, -64), (212, 220, 0, -64), (228, 236, 0, -64), (244, 252, 0, -64), (5, 13, -24, -59), (21, 29, -24, -59), (37, 45, -24, -59), (53, 61, -24, -59), (69, 77, -24, -59), (85, 93, -24, -59), (101, 109, -24, -59), (117, 125, -24, -59), (133, 141, -24, -59), (149, 157, -24, -59), (165, 173, -24, -59), (181, 189, -24, -59), (197, 205, -24, -59), (213, 221, -24, -59), (229, 237, -24, -59), (245, 253, -24, -59), (6, 14, -45, -45), (22, 30, -45, -45), (38, 46, -45, -45), (54, 62, -45, -45), (70, 78, -45, -45), (86, 94, -45, -45), (102, 110, -45, -45), (118, 126, -45, -45), (134, 142, -45, -45), (150, 158, -45, -45), (166, 174, -45, -45), (182, 190, -45, -45), (198, 206, -45, -45), (214, 222, -45, -45), (230, 238, -45, -45), (246, 254, -45, -45), (7, 15, -59, -24), (23, 31, -59, -24), (39, 47, -59, -24), (55, 63, -59, -24), (71, 79, -59, -24), (87, 95, -59, -24), (103, 111, -59, -24), (119, 127, -59, -24), (135, 143, -59, -24), (151, 159, -59, -24), (167, 175, -59, -24), (183, 191, -59, -24), (199, 207, -59, -24), (215, 223, -59, -24), (231, 239, -59, -24), (247, 255, -59, -24), (0, 16, 64, 0), (32, 48, 64, 0), (64, 80, 64, 0), (96, 112, 64, 0), (128, 144, 64, 0), (160, 176, 64, 0), (192, 208, 64, 0), (224, 240, 64, 0), (1, 17, 62, -12), (33, 49, 62, -12), (65, 81, 62, -12), (97, 113, 62, -12), (129, 145, 62, -12), (161, 177, 62, -12), (193, 209, 62, -12), (225, 241, 62, -12), (2, 18, 59, -24), (34, 50, 59, -24), (66, 82, 59, -24), (98, 114, 59, -24), (130, 146, 59, -24), (162, 178, 59, -24), (194, 210, 59, -24), (226, 242, 59, -24), (3, 19, 53, -36), (35, 51, 53, -36), (67, 83, 53, -36), (99, 115, 53, -36), (131, 147, 53, -36), (163, 179, 53, -36), (195, 211, 53, -36), (227, 243, 53, -36), (4, 20, 45, -45), (36, 52, 45, -45), (68, 84, 45, -45), (100, 116, 45, -45), (132, 148, 45, -45), (164, 180, 45, -45), (196, 212, 45, -45), (228, 244, 45, -45), (5, 21, 35, -53), (37, 53, 35, -53), (69, 85, 35, -53), (101, 117, 35, -53), (133, 149, 35, -53), (165, 181, 35, -53), (197, 213, 35, -53), (229, 245, 35, -53), (6, 22, 24, -59), (38, 54, 24, -59), (70, 86, 24, -59), (102, 118, 24, -59), (134, 150, 24, -59), (166, 182, 24, -59), (198, 214, 24, -59), (230, 246, 24, -59), (7, 23, 12, -63), (39, 55, 12, -63), (71, 87, 12, -63), (103, 119, 12, -63), (135, 151, 12, -63), (167, 183, 12, -63), (199, 215, 12, -63), (231, 247, 12, -63), (8, 24, 0, -64), (40, 56, 0, -64), (72, 88, 0, -64), (104, 120, 0, -64), (136, 152, 0, -64), (168, 184, 0, -64), (200, 216, 0, -64), (232, 248, 0, -64), (9, 25, -12, -63), (41, 57, -12, -63), (73, 89, -12, -63), (105, 121, -12, -63), (137, 153, -12, -63), (169, 185, -12, -63), (201, 217, -12, -63), (233, 249, -12, -63), (10, 26, -24, -59), (42, 58, -24, -59), (74, 90, -24, -59), (106, 122, -24, -59), (138, 154, -24, -59), (170, 186, -24, -59), (202, 218, -24, -59), (234, 250, -24, -59), (11, 27, -36, -53), (43, 59, -36, -53), (75, 91, -36, -53), (107, 123, -36, -53), (139, 155, -36, -53), (171, 187, -36, -53), (203, 219, -36, -53), (235, 251, -36, -53), (12, 28, -45, -45), (44, 60, -45, -45), (76, 92, -45, -45), (108, 124, -45, -45), (140, 156, -45, -45), (172, 188, -45, -45), (204, 220, -45, -45), (236, 252, -45, -45), (13, 29, -53, -36), (45, 61, -53, -36), (77, 93, -53, -36), (109, 125, -53, -36), (141, 157, -53, -36), (173, 189, -53, -36), (205, 221, -53, -36), (237, 253, -53, -36), (14, 30, -59, -24), (46, 62, -59, -24), (78, 94, -59, -24), (110, 126, -59, -24), (142, 158, -59, -24), (174, 190, -59, -24), (206, 222, -59, -24), (238, 254, -59, -24), (15, 31, -63, -12), (47, 63, -63, -12), (79, 95, -63, -12), (111, 127, -63, -12), (143, 159, -63, -12), (175, 191, -63, -12), (207, 223, -63, -12), (239, 255, -63, -12), (0, 32, 64, 0), (64, 96, 64, 0), (128, 160, 64, 0), (192, 224, 64, 0), (1, 33, 63, -6), (65, 97, 63, -6), (129, 161, 63, -6), (193, 225, 63, -6), (2, 34, 62, -12), (66, 98, 62, -12), (130, 162, 62, -12), (194, 226, 62, -12), (3, 35, 61, -19), (67, 99, 61, -19), (131, 163, 61, -19), (195, 227, 61, -19), (4, 36, 59, -24), (68, 100, 59, -24), (132, 164, 59, -24), (196, 228, 59, -24), (5, 37, 56, -30), (69, 101, 56, -30), (133, 165, 56, -30), (197, 229, 56, -30), (6, 38, 53, -36), (70, 102, 53, -36), (134, 166, 53, -36), (198, 230, 53, -36), (7, 39, 49, -41), (71, 103, 49, -41), (135, 167, 49, -41), (199, 231, 49, -41), (8, 40, 45, -45), (72, 104, 45, -45), (136, 168, 45, -45), (200, 232, 45, -45), (9, 41, 40, -49), (73, 105, 40, -49), (137, 169, 40, -49), (201, 233, 40, -49), (10, 42, 35, -53), (74, 106, 35, -53), (138, 170, 35, -53), (202, 234, 35, -53), (11, 43, 30, -56), (75, 107, 30, -56), (139, 171, 30, -56), (203, 235, 30, -56), (12, 44, 24, -59), (76, 108, 24, -59), (140, 172, 24, -59), (204, 236, 24, -59), (13, 45, 18, -61), (77, 109, 18, -61), (141, 173, 18, -61), (205, 237, 18, -61), (14, 46, 12, -63), (78, 110, 12, -63), (142, 174, 12, -63), (206, 238, 12, -63), (15, 47, 6, -64), (79, 111, 6, -64), (143, 175, 6, -64), (207, 239, 6, -64), (16, 48, 0, -64), (80, 112, 0, -64), (144, 176, 0, -64), (208, 240, 0, -64), (17, 49, -6, -64), (81, 113, -6, -64), (145, 177, -6, -64), (209, 241, -6, -64), (18, 50, -12, -63), (82, 114, -12, -63), (146, 178, -12, -63), (210, 242, -12, -63), (19, 51, -19, -61), (83, 115, -19, -61), (147, 179, -19, -61), (211, 243, -19, -61), (20, 52, -24, -59), (84, 116, -24, -59), (148, 180, -24, -59), (212, 244, -24, -59), (21, 53, -30, -56), (85, 117, -30, -56), (149, 181, -30, -56), (213, 245, -30, -56), (22, 54, -36, -53), (86, 118, -36, -53), (150, 182, -36, -53), (214, 246, -36, -53), (23, 55, -41, -49), (87, 119, -41, -49), (151, 183, -41, -49), (215, 247, -41, -49), (24, 56, -45, -45), (88, 120, -45, -45), (152, 184, -45, -45), (216, 248, -45, -45), (25, 57, -49, -41), (89, 121, -49, -41), (153, 185, -49, -41), (217, 249, -49, -41), (26, 58, -53, -36), (90, 122, -53, -36), (154, 186, -53, -36), (218, 250, -53, -36), (27, 59, -56, -30), (91, 123, -56, -30), (155, 187, -56, -30), (219, 251, -56, -30), (28, 60, -59, -24), (92, 124, -59, -24), (156, 188, -59, -24), (220, 252, -59, -24), (29, 61, -61, -19), (93, 125, -61, -19), (157, 189, -61, -19), (221, 253, -61, -19), (30, 62, -63, -12), (94, 126, -63, -12), (158, 190, -63, -12), (222, 254, -63, -12), (31, 63, -64, -6), (95, 127, -64, -6), (159, 191, -64, -6), (223, 255, -64, -6), (0, 64, 64, 0), (128, 192, 64, 0), (1, 65, 63, -3), (129, 193, 63, -3), (2, 66, 63, -6), (130, 194, 63, -6), (3, 67, 63, -9), (131, 195, 63, -9), (4, 68, 62, -12), (132, 196, 62, -12), (5, 69, 62, -16), (133, 197, 62, -16), (6, 70, 61, -19), (134, 198, 61, -19), (7, 71, 60, -22), (135, 199, 60, -22), (8, 72, 59, -24), (136, 200, 59, -24), (9, 73, 57, -27), (137, 201, 57, -27), (10, 74, 56, -30), (138, 202, 56, -30), (11, 75, 54, -33), (139, 203, 54, -33), (12, 76, 53, -36), (140, 204, 53, -36), (13, 77, 51, -38), (141, 205, 51, -38), (14, 78, 49, -41), (142, 206, 49, -41), (15, 79, 47, -43), (143, 207, 47, -43), (16, 80, 45, -45), (144, 208, 45, -45), (17, 81, 42, -47), (145, 209, 42, -47), (18, 82, 40, -49), (146, 210, 40, -49), (19, 83, 38, -51), (147, 211, 38, -51), (20, 84, 35, -53), (148, 212, 35, -53), (21, 85, 32, -55), (149, 213, 32, -55), (22, 86, 30, -56), (150, 214, 30, -56), (23, 87, 27, -58), (151, 215, 27, -58), (24, 88, 24, -59), (152, 216, 24, -59), (25, 89, 21, -60), (153, 217, 21, -60), (26, 90, 18, -61), (154, 218, 18, -61), (27, 91, 15, -62), (155, 219, 15, -62), (28, 92, 12, -63), (156, 220, 12, -63), (29, 93, 9, -63), (157, 221, 9, -63), (30, 94, 6, -64), (158, 222, 6, -64), (31, 95, 3, -64), (159, 223, 3, -64), (32, 96, 0, -64), (160, 224, 0, -64), (33, 97, -3, -64), (161, 225, -3, -64), (34, 98, -6, -64), (162, 226, -6, -64), (35, 99, -9, -63), (163, 227, -9, -63), (36, 100, -12, -63), (164, 228, -12, -63), (37, 101, -16, -62), (165, 229, -16, -62), (38, 102, -19, -61), (166, 230, -19, -61), (39, 103, -22, -60), (167, 231, -22, -60), (40, 104, -24, -59), (168, 232, -24, -59), (41, 105, -27, -58), (169, 233, -27, -58), (42, 106, -30, -56), (170, 234, -30, -56), (43, 107, -33, -55), (171, 235, -33, -55), (44, 108, -36, -53), (172, 236, -36, -53), (45, 109, -38, -51), (173, 237, -38, -51), (46, 110, -41, -49), (174, 238, -41, -49), (47, 111, -43, -47), (175, 239, -43, -47), (48, 112, -45, -45), (176, 240, -45, -45), (49, 113, -47, -43), (177, 241, -47, -43), (50, 114, -49, -41), (178, 242, -49, -41), (51, 115, -51, -38), (179, 243, -51, -38), (52, 116, -53, -36), (180, 244, -53, -36), (53, 117, -55, -33), (181, 245, -55, -33), (54, 118, -56, -30), (182, 246, -56, -30), (55, 119, -58, -27), (183, 247, -58, -27), (56, 120, -59, -24), (184, 248, -59, -24), (57, 121, -60, -22), (185, 249, -60, -22), (58, 122, -61, -19), (186, 250, -61, -19), (59, 123, -62, -16), (187, 251, -62, -16), (60, 124, -63, -12), (188, 252, -63, -12), (61, 125, -63, -9), (189, 253, -63, -9), (62, 126, -64, -6), (190, 254, -64, -6), (63, 127, -64, -3), (191, 255, -64, -3), (0, 128, 64, 0), (1, 129, 63, -2), (2, 130, 63, -3), (3, 131, 63, -5), (4, 132, 63, -6), (5, 133, 63, -8), (6, 134, 63, -9), (7, 135, 63, -11), (8, 136, 62, -12), (9, 137, 62, -14), (10, 138, 62, -16), (11, 139, 61, -17), (12, 140, 61, -19), (13, 141, 60, -20), (14, 142, 60, -22), (15, 143, 59, -23), (16, 144, 59, -24), (17, 145, 58, -26), (18, 146, 57, -27), (19, 147, 57, -29), (20, 148, 56, -30), (21, 149, 55, -32), (22, 150, 54, -33), (23, 151, 54, -34), (24, 152, 53, -36), (25, 153, 52, -37), (26, 154, 51, -38), (27, 155, 50, -39), (28, 156, 49, -41), (29, 157, 48, -42), (30, 158, 47, -43), (31, 159, 46, -44), (32, 160, 45, -45), (33, 161, 44, -46), (34, 162, 42, -47), (35, 163, 41, -48), (36, 164, 40, -49), (37, 165, 39, -50), (38, 166, 38, -51), (39, 167, 36, -52), (40, 168, 35, -53), (41, 169, 34, -54), (42, 170, 32, -55), (43, 171, 31, -56), (44, 172, 30, -56), (45, 173, 28, -57), (46, 174, 27, -58), (47, 175, 25, -59), (48, 176, 24, -59), (49, 177, 23, -60), (50, 178, 21, -60), (51, 179, 20, -61), (52, 180, 18, -61), (53, 181, 17, -62), (54, 182, 15, -62), (55, 183, 14, -62), (56, 184, 12, -63), (57, 185, 10, -63), (58, 186, 9, -63), (59, 187, 7, -64), (60, 188, 6, -64), (61, 189, 4, -64), (62, 190, 3, -64), (63, 191, 1, -64), (64, 192, 0, -64), (65, 193, -2, -64), (66, 194, -3, -64), (67, 195, -5, -64), (68, 196, -6, -64), (69, 197, -8, -64), (70, 198, -9, -63), (71, 199, -11, -63), (72, 200, -12, -63), (73, 201, -14, -62), (74, 202, -16, -62), (75, 203, -17, -62), (76, 204, -19, -61), (77, 205, -20, -61), (78, 206, -22, -60), (79, 207, -23, -60), (80, 208, -24, -59), (81, 209, -26, -59), (82, 210, -27, -58), (83, 211, -29, -57), (84, 212, -30, -56), (85, 213, -32, -56), (86, 214, -33, -55), (87, 215, -34, -54), (88, 216, -36, -53), (89, 217, -37, -52), (90, 218, -38, -51), (91, 219, -39, -50), (92, 220, -41, -49), (93, 221, -42, -48), (94, 222, -43, -47), (95, 223, -44, -46), (96, 224, -45, -45), (97, 225, -46, -44), (98, 226, -47, -43), (99, 227, -48, -42), (100, 228, -49, -41), (101, 229, -50, -39), (102, 230, -51, -38), (103, 231, -52, -37), (104, 232, -53, -36), (105, 233, -54, -34), (106, 234, -55, -33), (107, 235, -56, -32), (108, 236, -56, -30), (109, 237, -57, -29), (110, 238, -58, -27), (111, 239, -59, -26), (112, 240, -59, -24), (113, 241, -60, -23), (114, 242, -60, -22), (115, 243, -61, -20), (116, 244, -61, -19), (117, 245, -62, -17), (118, 246, -62, -16), (119, 247, -62, -14), (120, 248, -63, -12), (121, 249, -63, -11), (122, 250, -63, -9), (123, 251, -64, -8), (124, 252, -64, -6), (125, 253, -64, -5), (126, 254, -64, -3), (127, 255, -64, -2)); signal reg_file : t_data_array(15 downto 0) := (others => (others => '0')); signal load_cycles : integer := 0; signal run_cycles : integer := 0; signal cnt_load : std_logic := '0'; signal cnt_run : std_logic := '0'; begin clock: process begin clk <= '0'; clk2x <= '1'; wait for 5 ns; clk2x <= '0'; wait for 5 ns; clk <= '1'; clk2x <= '1'; wait for 5 ns; clk2x <= '0'; wait for 5 ns; end process clock; cnt: process(clk) begin if rising_edge(clk) then if cnt_load = '1' then load_cycles <= load_cycles + 1; end if; if cnt_run = '1' then run_cycles <= run_cycles + 1; end if; end if; end process cnt; process(clk) begin if rising_edge(clk) then if rst = '0' then if reg_ena = '1' then reg_doa <= reg_file(to_integer(unsigned(reg_addra))); end if; if reg_enb = '1' then reg_dob <= reg_file(to_integer(unsigned(reg_addrb))); end if; end if; end if; end process; process variable l : line; begin wait for 10 ns; wait for 1 ps; wait for 40 ns; rst <= '0'; wait for 40 ns; prog_cmd( ( arg_type => ( 0 => ARG_IMM, 1 => ARG_IMM, 2 => ARG_IMM, 3 => ARG_IMM, 4 => ARG_NONE, 5 => ARG_NONE ), arg_memchunk => (others => (others => '0')), arg_val => (others => '1'), arg_assign => ( 0 => "000", -- r 1 => "001", -- i 2 => "010", -- addr r 3 => "011", -- addr i 4 => "100", 5 => "101" ), mem_fetch => ( 0 => '0', 1 => '0', 2 => '0', 3 => '0', 4 => '0', 5 => '0'), mem_memchunk => ( 0 => "00", 1 => "00", 2 => "00", 3 => "00", 4 => "00", 5 => "00" ), s1_in1a => "000", s1_in1b => "000", s1_op1 => CALU_NOOP, s1_point1 => "000", s1_out1 => "000", s1_in2a => "000", s1_in2b => "000", s1_op2 => CALU_NOOP, s1_point2 => "000", s1_out2 => "000", s2_in1a => "000", s2_in1b => "000", s2_op1 => SALU_NOOP, s2_out1 => "000", s2_in2a => "000", s2_in2b => "000", s2_op2 => SALU_NOOP, s2_out2 => "000", s3_in1a => "000", s3_in1b => "000", s3_op1 => SALU_NOOP, s3_out1 => "000", s3_in2a => "000", s3_in2b => "000", s3_op2 => SALU_NOOP, s3_out2 => "000", wb => ( 0 => '1', 1 => '1', 2 => '0', 3 => '0', 4 => '0', 5 => '0'), wb_memchunk => ( 0 => "10", -- R 1 => "10", -- I 2 => "00", 3 => "00", 4 => "00", 5 => "00"), wb_bitrev => ( 0 => "111", 1 => "111", others => (others => '0')), wb_assign => ( 0 => "0010", 1 => "0011", 2 => "0000", 3 => "0000", 4 => "0000", 5 => "0000"), noop => '0' ), 0, start, pdata); prog_cmd( ( arg_type => ( 0 => ARG_REG, -- i 1 => ARG_REG, -- j 2 => ARG_REG, -- r_lut 3 => ARG_REG, -- i_lut 4 => ARG_NONE, 5 => ARG_NONE ), arg_memchunk => (others => (others => '0')), arg_val => ( 0 => '0', 1 => '0', 2 => '0', 3 => '1', -- r_lut 4 => '1', -- i_lut 5 => '0'), arg_assign => ( 0 => "000", -- i 1 => "001", -- j 2 => "001", -- j 3 => "010", -- r_lut 4 => "011", -- i_lut 5 => "101"), mem_fetch => ( 0 => '1', 1 => '1', 2 => '1', 3 => '0', 4 => '0', 5 => '0'), mem_memchunk => ( 0 => "10", -- R 1 => "10", -- R 2 => "11", -- I 3 => "00", 4 => "00", 5 => "00" ), s1_in1a => "011", -- r_lut s1_in1b => "001", -- R[j] s1_op1 => CALU_SMUL, s1_point1 => "111", s1_out1 => "001", s1_in2a => "100", -- i_lut s1_in2b => "010", -- I[j] s1_op2 => CALU_SMUL, s1_point2 => "111", s1_out2 => "010", s2_in1a => "001", s2_in1b => "010", s2_op1 => SALU_SUB, s2_out1 => "001", -- tr s2_in2a => "000", -- R[i] s2_in2b => ALUIN_1, -- 1 s2_op2 => SALU_SAR, s2_out2 => "000", s3_in1a => "000", s3_in1b => "001", s3_op1 => SALU_SUB, s3_out1 => "001", s3_in2a => "000", s3_in2b => "001", s3_op2 => SALU_ADD, s3_out2 => "000", wb => ( 0 => '1', 1 => '1', 2 => '0', 3 => '0', 4 => '0', 5 => '0'), wb_memchunk => ( 0 => "10", -- R 1 => "10", -- R 2 => "00", 3 => "00", 4 => "00", 5 => "00"), wb_bitrev => (others => (others => '0')), wb_assign => ( 0 => "0000", 1 => "0001", 2 => "0010", 3 => "0011", 4 => "0100", 5 => "0101"), noop => '0' ), 1, start, pdata); prog_cmd( ( arg_type => ( 0 => ARG_NONE, 1 => ARG_NONE, 2 => ARG_NONE, 3 => ARG_NONE, 4 => ARG_NONE, 5 => ARG_NONE ), arg_memchunk => (others => (others => '0')), arg_val => (others => '0'), arg_assign => ( 0 => "000", -- i 1 => "001", -- j 2 => "001", -- j 3 => "010", -- r_lut 4 => "011", -- i_lut 5 => "101" ), mem_fetch => ( 0 => '1', 1 => '1', 2 => '1', 3 => '0', 4 => '0', 5 => '0'), mem_memchunk => ( 0 => "11", -- I 1 => "10", -- R 2 => "11", -- I 3 => "00", 4 => "00", 5 => "00" ), s1_in1a => "011", -- r_lut s1_in1b => "010", -- I[j] s1_op1 => CALU_SMUL, s1_point1 => "111", s1_out1 => "001", s1_in2a => "100", -- i_lut s1_in2b => "001", -- R[j] s1_op2 => CALU_SMUL, s1_point2 => "111", s1_out2 => "010", s2_in1a => "001", s2_in1b => "010", s2_op1 => SALU_ADD, s2_out1 => "001", -- ti s2_in2a => "000", -- I[i] s2_in2b => ALUIN_1, -- 1 s2_op2 => SALU_SAR, s2_out2 => "000", s3_in1a => "000", s3_in1b => "001", s3_op1 => SALU_SUB, s3_out1 => "001", s3_in2a => "000", s3_in2b => "001", s3_op2 => SALU_ADD, s3_out2 => "000", wb => ( 0 => '1', 1 => '1', 2 => '0', 3 => '0', 4 => '0', 5 => '0'), wb_memchunk => ( 0 => "11", -- I 1 => "11", -- I 2 => "00", 3 => "00", 4 => "00", 5 => "00"), wb_bitrev => (others => (others => '0')), wb_assign => ( 0 => "0000", 1 => "0001", 2 => "0010", 3 => "0011", 4 => "0100", 5 => "0101"), noop => '0' ), 2, start, pdata); cnt_load <= '1'; for i in 0 to 127 loop pdata <= "1111111111100000"; start <= '1'; wait for 20 ns; start <= '0'; pdata(7 downto 0) <= std_logic_vector(to_signed(sine_wave(i*2), 8)); pdata(15 downto 8) <= std_logic_vector(to_signed(sine_wave(i*2+1), 8)); wait for 20 ns; pdata(7 downto 0) <= std_logic_vector(to_signed(i*2, 8)); pdata(15 downto 8) <= std_logic_vector(to_signed(i*2+1, 8)); wait for 40 ns; end loop; cnt_load <= '0'; cnt_run <= '1'; for i in 0 to 1023 loop pdata <= "1111111111100001"; start <= '1'; reg_file(0) <= std_logic_vector(to_unsigned(bflys(i)(0), 8)); reg_file(1) <= std_logic_vector(to_unsigned(bflys(i)(1), 8)); reg_file(2) <= std_logic_vector(to_signed(bflys(i)(2), 8)); reg_file(3) <= std_logic_vector(to_signed(bflys(i)(3), 8)); wait for 20 ns; start <= '0'; pdata(7 downto 0) <= "00000000"; pdata(15 downto 8) <= "00000001"; wait for 20 ns; pdata(7 downto 0) <= "00000010"; pdata(15 downto 8) <= "00000011"; wait for 200 ns; pdata <= "1111111111100010"; start <= '1'; wait for 20 ns; start <= '0'; wait for 20 ns; end loop; cnt_run <= '0'; wait for 140 ns; mem_ena <= '1'; mem_enb <= '1'; for i in 0 to 255 loop mem_addra <= "10" & std_logic_vector(to_unsigned(i, 8)); mem_addrb <= "11" & std_logic_vector(to_unsigned(i, 8)); wait for 20 ns; assert false report integer'image(to_integer(signed(mem_doa))) & ", " & integer'image(to_integer(signed(mem_dob))) severity note; end loop; mem_ena <= '0'; mem_enb <= '0'; wait for 60 ns; assert false report "stop load: " & integer'image(load_cycles) & " run: " & integer'image(run_cycles) severity failure; end process; mp_i: entity work.mp port map( rst => rst, clk => clk, clk2x => clk2x, pdata => pdata, pdata_rd => pdata_rd, start => start, busy => busy, mem_addra => mem_addra, mem_ena => mem_ena, mem_doa => mem_doa, mem_addrb => mem_addrb, mem_enb => mem_enb, mem_dob => mem_dob, reg_addra => reg_addra, reg_ena => reg_ena, reg_doa => reg_doa, reg_addrb => reg_addrb, reg_enb => reg_enb, reg_dob => reg_dob ); end behav; |
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use WORK.alu_types.all; entity BOOTHMUL is generic ( N : integer := NSUMG ); port ( A : in std_logic_vector(N-1 downto 0); B : in std_logic_vector(N-1 downto 0); P : out std_logic_vector(2*N-1 downto 0) ); end BOOTHMUL; architecture mixed of BOOTHMUL is -- Internal signals type SignalVector is array (N/2-1 downto 0) of std_logic_vector(2*N-1 downto 0); signal encoder: std_logic_vector(N downto 0); signal A_in: std_logic_vector(2*N - 1 downto 0):=(others => '0'); -- Outputs of each MUX or ADDER block step signal mux_out:SignalVector; signal sum_internal:SignalVector; -- Allows signed multiplication by implementing 2's complement without an adder. signal Cin: std_logic_vector(N/2-1 downto 0); -- Sign extension wires signal signext: std_logic_vector(N-1 downto 0); -- Dummy RCA cout connection signal cout: std_logic; component MUX3B generic( N:integer := NSUMG; OFFSET:integer:=0 ); port ( A : in std_logic_vector(N-1 downto 0); CTRL : in std_logic_vector(2 downto 0); Y : out std_logic_vector(N-1 downto 0); Cin : out std_logic ); end component; component RCA_GENERIC generic ( NBIT:integer := NSUMG ); port ( A: in std_logic_vector(NBIT-1 downto 0); B: in std_logic_vector(NBIT-1 downto 0); Ci: in std_logic; S: out std_logic_vector(NBIT-1 downto 0); Co: out std_logic); end component; begin -- The first bit of the encoder vector is a 0 encoder <= B & '0'; -- Sign extension: A_in is the sign extension representation of A signext <= (others => A(N-1)); A_in <= signext & A; SUM_N: for i in 0 to N/2 - 1 generate -- Create the MUX/encoder coupled component N_MUX: MUX3B generic map(2*N,2*i) port map (A_in, encoder((2*i+2) downto 2*i), mux_out(i), Cin(i)); -- Create the RCA blocks -- The first RCA has only a the first mux_out( and its Cin ) as an input. -- Because if the first value of "encoder" is "101","110" or "100" the -- the output of this RCA is negative(naturally if A_in has a positive value). SUM_0: if i = 0 generate S0:RCA_GENERIC generic map(2*N) port map(mux_out(i), (others =>'0'), Cin(i), sum_internal(i), cout); end generate; -- The other RCAs take the output of the mux, its Cin, and the output of the previous RCA block -- and generate the sum. SUM: if i /= 0 generate SN:RCA_GENERIC generic map(2*N) port map(sum_internal(i-1), mux_out(i), Cin(i), sum_internal(i), cout); end generate; end generate; -- Output P <= sum_internal(N/2 - 1); end mixed; |
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; library work; use work.i2s_controller; library work; use work.axi_streaming_dma_rx_fifo; use work.axi_streaming_dma_tx_fifo; use work.pl330_dma_fifo; use work.axi_ctrlif; entity axi_i2s_adi is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- C_SLOT_WIDTH : integer := 24; C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge) C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge) -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_FAMILY : string := "virtex6"; -- DO NOT EDIT ABOVE THIS LINE --------------------- C_DMA_TYPE : integer := 0; C_NUM_CH : integer := 1; C_HAS_TX : integer := 1; C_HAS_RX : integer := 1 ); port ( -- Serial Data interface DATA_CLK_I : in std_logic; BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0); SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0); -- AXI Streaming DMA TX interface S_AXIS_ACLK : in std_logic; S_AXIS_ARESETN : in std_logic; S_AXIS_TREADY : out std_logic; S_AXIS_TDATA : in std_logic_vector(31 downto 0); S_AXIS_TLAST : in std_logic; S_AXIS_TVALID : in std_logic; -- AXI Streaming DMA RX interface M_AXIS_ACLK : in std_logic; M_AXIS_TREADY : in std_logic; M_AXIS_TDATA : out std_logic_vector(31 downto 0); M_AXIS_TLAST : out std_logic; M_AXIS_TVALID : out std_logic; M_AXIS_TKEEP : out std_logic_vector(3 downto 0); --PL330 DMA TX interface DMA_REQ_TX_ACLK : in std_logic; DMA_REQ_TX_RSTN : in std_logic; DMA_REQ_TX_DAVALID : in std_logic; DMA_REQ_TX_DATYPE : in std_logic_vector(1 downto 0); DMA_REQ_TX_DAREADY : out std_logic; DMA_REQ_TX_DRVALID : out std_logic; DMA_REQ_TX_DRTYPE : out std_logic_vector(1 downto 0); DMA_REQ_TX_DRLAST : out std_logic; DMA_REQ_TX_DRREADY : in std_logic; -- PL330 DMA RX interface DMA_REQ_RX_ACLK : in std_logic; DMA_REQ_RX_RSTN : in std_logic; DMA_REQ_RX_DAVALID : in std_logic; DMA_REQ_RX_DATYPE : in std_logic_vector(1 downto 0); DMA_REQ_RX_DAREADY : out std_logic; DMA_REQ_RX_DRVALID : out std_logic; DMA_REQ_RX_DRTYPE : out std_logic_vector(1 downto 0); DMA_REQ_RX_DRLAST : out std_logic; DMA_REQ_RX_DRREADY : in std_logic; -- AXI bus interface S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_RREADY : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_AWREADY : out std_logic ); end entity axi_i2s_adi; architecture Behavioral of axi_i2s_adi is signal i2s_reset : std_logic; signal tx_fifo_reset : std_logic; signal tx_enable : Boolean; signal tx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0); signal tx_ack : std_logic; signal tx_stb : std_logic; signal rx_enable : Boolean; signal rx_fifo_reset : std_logic; signal rx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0); signal rx_ack : std_logic; signal rx_stb : std_logic; signal const_1 : std_logic; signal bclk_div_rate : natural range 0 to 255; signal lrclk_div_rate : natural range 0 to 255; signal period_len : integer range 0 to 65535; signal I2S_RESET_REG : std_logic_vector(31 downto 0); signal I2S_CONTROL_REG : std_logic_vector(31 downto 0); signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0); signal PERIOD_LEN_REG : std_logic_vector(31 downto 0); constant FIFO_AWIDTH : integer := integer(ceil(log2(real(C_NUM_CH * 8)))); constant RAM_ADDR_WIDTH : integer := 7; type RAM_TYPE is array (0 to (2**RAM_ADDR_WIDTH - 1)) of std_logic_vector(31 downto 0); signal audio_fifo_rx : RAM_TYPE; signal audio_fifo_rx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1; signal audio_fifo_rx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1; signal tvalid : std_logic := '0'; signal rx_tlast : std_logic; signal drain_tx_dma : std_logic; signal rx_sample : std_logic_vector(23 downto 0); signal wr_data : std_logic_vector(31 downto 0); signal rd_data : std_logic_vector(31 downto 0); signal wr_addr : integer range 0 to 11; signal rd_addr : integer range 0 to 11; signal wr_stb : std_logic; signal rd_ack : std_logic; signal tx_fifo_stb : std_logic; signal rx_fifo_ack : std_logic; signal cnt : integer range 0 to 2**16-1; begin const_1 <= '1'; process (S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then cnt <= 0; else cnt <= (cnt + 1) mod 2**16; end if; end if; end process; streaming_dma_tx_gen: if C_DMA_TYPE = 0 and C_HAS_TX = 1 generate tx_fifo : entity axi_streaming_dma_tx_fifo generic map( RAM_ADDR_WIDTH => FIFO_AWIDTH, FIFO_DWIDTH => 24 ) port map( clk => S_AXI_ACLK, resetn => S_AXI_ARESETN, fifo_reset => tx_fifo_reset, enable => tx_enable, S_AXIS_ACLK => S_AXIS_ACLK, S_AXIS_TREADY => S_AXIS_TREADY, S_AXIS_TDATA => S_AXIS_TDATA(31 downto 8), S_AXIS_TLAST => S_AXIS_TLAST, S_AXIS_TVALID => S_AXIS_TVALID, out_stb => tx_stb, out_ack => tx_ack, out_data => tx_data ); end generate; no_streaming_dma_tx_gen: if C_DMA_TYPE /= 0 or C_HAS_TX /= 1 generate S_AXIS_TREADY <= '0'; end generate; streaming_dma_rx_gen: if C_DMA_TYPE = 0 and C_HAS_RX = 1 generate rx_fifo : entity axi_streaming_dma_rx_fifo generic map( RAM_ADDR_WIDTH => FIFO_AWIDTH, FIFO_DWIDTH => 24 ) port map( clk => S_AXI_ACLK, resetn => S_AXI_ARESETN, fifo_reset => tx_fifo_reset, enable => tx_enable, period_len => period_len, in_stb => rx_stb, in_ack => rx_ack, in_data => rx_data, M_AXIS_ACLK => M_AXIS_ACLK, M_AXIS_TREADY => M_AXIS_TREADY, M_AXIS_TDATA => M_AXIS_TDATA(31 downto 8), M_AXIS_TLAST => M_AXIS_TLAST, M_AXIS_TVALID => M_AXIS_TVALID, M_AXIS_TKEEP => M_AXIS_TKEEP ); M_AXIS_TDATA(7 downto 0) <= (others => '0'); end generate; no_streaming_dma_rx_gen: if C_DMA_TYPE /= 0 or C_HAS_RX /= 1 generate M_AXIS_TDATA <= (others => '0'); M_AXIS_TLAST <= '0'; M_AXIS_TVALID <= '0'; M_AXIS_TKEEP <= (others => '0'); end generate; pl330_dma_tx_gen: if C_DMA_TYPE = 1 and C_HAS_TX = 1 generate tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0'; tx_fifo: entity pl330_dma_fifo generic map( RAM_ADDR_WIDTH => FIFO_AWIDTH, FIFO_DWIDTH => 24, FIFO_DIRECTION => 0 ) port map ( clk => S_AXI_ACLK, resetn => S_AXI_ARESETN, fifo_reset => tx_fifo_reset, enable => tx_enable, in_data => wr_data(31 downto 8), in_stb => tx_fifo_stb, out_ack => tx_ack, out_stb => tx_stb, out_data => tx_data, dclk => DMA_REQ_TX_ACLK, dresetn => DMA_REQ_TX_RSTN, davalid => DMA_REQ_TX_DAVALID, daready => DMA_REQ_TX_DAREADY, datype => DMA_REQ_TX_DATYPE, drvalid => DMA_REQ_TX_DRVALID, drready => DMA_REQ_TX_DRREADY, drtype => DMA_REQ_TX_DRTYPE, drlast => DMA_REQ_TX_DRLAST ); end generate; no_pl330_dma_tx_gen: if C_DMA_TYPE /= 1 or C_HAS_TX /= 1 generate DMA_REQ_TX_DAREADY <= '0'; DMA_REQ_TX_DRVALID <= '0'; DMA_REQ_TX_DRTYPE <= (others => '0'); DMA_REQ_TX_DRLAST <= '0'; end generate; pl330_dma_rx_gen: if C_DMA_TYPE = 1 and C_HAS_RX = 1 generate rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0'; rx_fifo: entity pl330_dma_fifo generic map( RAM_ADDR_WIDTH => FIFO_AWIDTH, FIFO_DWIDTH => 24, FIFO_DIRECTION => 1 ) port map ( clk => S_AXI_ACLK, resetn => S_AXI_ARESETN, fifo_reset => rx_fifo_reset, enable => rx_enable, in_ack => rx_ack, in_stb => rx_stb, in_data => rx_data, out_data => rx_sample, out_ack => rx_fifo_ack, dclk => DMA_REQ_RX_ACLK, dresetn => DMA_REQ_RX_RSTN, davalid => DMA_REQ_RX_DAVALID, daready => DMA_REQ_RX_DAREADY, datype => DMA_REQ_RX_DATYPE, drvalid => DMA_REQ_RX_DRVALID, drready => DMA_REQ_RX_DRREADY, drtype => DMA_REQ_RX_DRTYPE, drlast => DMA_REQ_RX_DRLAST ); end generate; no_pl330_dma_rx_gen: if C_DMA_TYPE /= 1 or C_HAS_RX /= 1 generate DMA_REQ_RX_DAREADY <= '0'; DMA_REQ_RX_DRVALID <= '0'; DMA_REQ_RX_DRTYPE <= (others => '0'); DMA_REQ_RX_DRLAST <= '0'; end generate; ctrl : entity i2s_controller generic map ( C_SLOT_WIDTH => C_SLOT_WIDTH, C_BCLK_POL => C_BCLK_POL, C_LRCLK_POL => C_LRCLK_POL, C_NUM_CH => C_NUM_CH, C_HAS_TX => C_HAS_TX, C_HAS_RX => C_HAS_RX ) port map ( clk => S_AXI_ACLK, resetn => S_AXI_ARESETN, data_clk => DATA_CLK_I, BCLK_O => BCLK_O, LRCLK_O => LRCLK_O, SDATA_O => SDATA_O, SDATA_I => SDATA_I, tx_enable => tx_enable, tx_ack => tx_ack, tx_stb => tx_stb, tx_data => tx_data, rx_enable => rx_enable, rx_ack => rx_ack, rx_stb => rx_stb, rx_data => rx_data, bclk_div_rate => bclk_div_rate, lrclk_div_rate => lrclk_div_rate ); i2s_reset <= I2S_RESET_REG(0); tx_fifo_reset <= I2S_RESET_REG(1); rx_fifo_reset <= I2S_RESET_REG(2); tx_enable <= I2S_CONTROL_REG(0) = '1'; rx_enable <= I2S_CONTROL_REG(1) = '1'; bclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(7 downto 0))); lrclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(23 downto 16))); period_len <= to_integer(unsigned(PERIOD_LEN_REG(15 downto 0))); ctrlif: entity axi_ctrlif generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, C_NUM_REG => 12 ) port map( S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_AWADDR => S_AXI_AWADDR, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_WDATA => S_AXI_WDATA, S_AXI_WSTRB => S_AXI_WSTRB, S_AXI_WVALID => S_AXI_WVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_ARADDR => S_AXI_ARADDR, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_RREADY => S_AXI_RREADY, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RDATA => S_AXI_RDATA, S_AXI_RRESP => S_AXI_RRESP, S_AXI_RVALID => S_AXI_RVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BRESP => S_AXI_BRESP, S_AXI_BVALID => S_AXI_BVALID, S_AXI_AWREADY => S_AXI_AWREADY, rd_addr => rd_addr, rd_data => rd_data, rd_ack => rd_ack, rd_stb => const_1, wr_addr => wr_addr, wr_data => wr_data, wr_ack => const_1, wr_stb => wr_stb ); process(rd_addr, I2S_CONTROL_REG, I2S_CLK_CONTROL_REG, PERIOD_LEN_REG, rx_sample, cnt) begin case rd_addr is when 1 => rd_data <= I2S_CONTROL_REG and x"00000003"; when 2 => rd_data <= I2S_CLK_CONTROL_REG and x"00ff00ff"; when 6 => rd_data <= PERIOD_LEN_REG and x"0000ffff"; when 10 => rd_data <= rx_sample & std_logic_vector(to_unsigned(cnt, 8)); when others => rd_data <= (others => '0'); end case; end process; process(S_AXI_ACLK) is begin if rising_edge(S_AXI_ACLK) then if S_AXI_ARESETN = '0' then I2S_RESET_REG <= (others => '0'); I2S_CONTROL_REG <= (others => '0'); I2S_CLK_CONTROL_REG <= (others => '0'); PERIOD_LEN_REG <= (others => '0'); else -- Auto-clear the Reset Register bits I2S_RESET_REG(0) <= '0'; I2S_RESET_REG(1) <= '0'; I2S_RESET_REG(2) <= '0'; if wr_stb = '1' then case wr_addr is when 0 => I2S_RESET_REG <= wr_data; when 1 => I2S_CONTROL_REG <= wr_data; when 2 => I2S_CLK_CONTROL_REG <= wr_data; when 6 => PERIOD_LEN_REG <= wr_data; when others => null; end case; end if; end if; end if; end process; end Behavioral; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity IPv4_destination is port( data_in : in std_logic_vector(7 downto 0); enable : in std_logic; reset : in std_logic; clk : in std_logic; destination : out std_logic_vector(31 downto 0) ); end IPv4_destination; architecture Behavioral of IPv4_destination is signal address_counter : std_logic_vector(10 downto 0) := (others=>'0'); begin process (clk) begin if rising_edge(clk) then if reset = '1' then address_counter <= (others=>'0'); elsif enable = '1' then address_counter <= address_counter+1; end if; end if; end process; process (clk) begin if rising_edge(clk) then if reset = '1' then destination <= (others=>'0'); elsif address_counter = 31 then destination(31 downto 24) <= data_in; elsif address_counter = 32 then destination(23 downto 16) <= data_in; elsif address_counter = 33 then destination(15 downto 8) <= data_in; elsif address_counter = 34 then destination(7 downto 0) <= data_in; end if; end if; end process; end Behavioral; |
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity contact_discovery is generic ( C_M_AXI_DB_MEM_V_ADDR_WIDTH : INTEGER := 64; C_M_AXI_DB_MEM_V_ID_WIDTH : INTEGER := 1; C_M_AXI_DB_MEM_V_AWUSER_WIDTH : INTEGER := 1; C_M_AXI_DB_MEM_V_DATA_WIDTH : INTEGER := 512; C_M_AXI_DB_MEM_V_WUSER_WIDTH : INTEGER := 1; C_M_AXI_DB_MEM_V_ARUSER_WIDTH : INTEGER := 1; C_M_AXI_DB_MEM_V_RUSER_WIDTH : INTEGER := 1; C_M_AXI_DB_MEM_V_BUSER_WIDTH : INTEGER := 1; C_M_AXI_RESULTS_OUT_ADDR_WIDTH : INTEGER := 64; C_M_AXI_RESULTS_OUT_ID_WIDTH : INTEGER := 1; C_M_AXI_RESULTS_OUT_AWUSER_WIDTH : INTEGER := 1; C_M_AXI_RESULTS_OUT_DATA_WIDTH : INTEGER := 32; C_M_AXI_RESULTS_OUT_WUSER_WIDTH : INTEGER := 1; C_M_AXI_RESULTS_OUT_ARUSER_WIDTH : INTEGER := 1; C_M_AXI_RESULTS_OUT_RUSER_WIDTH : INTEGER := 1; C_M_AXI_RESULTS_OUT_BUSER_WIDTH : INTEGER := 1; C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 7; C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32; C_M_AXI_RESULTS_OUT_TARGET_ADDR : INTEGER := 0; C_M_AXI_DB_MEM_V_USER_VALUE : INTEGER := 0; C_M_AXI_RESULTS_OUT_PROT_VALUE : INTEGER := 0; C_M_AXI_DB_MEM_V_TARGET_ADDR : INTEGER := 0; C_M_AXI_DB_MEM_V_PROT_VALUE : INTEGER := 0; C_M_AXI_DB_MEM_V_CACHE_VALUE : INTEGER := 3; C_M_AXI_RESULTS_OUT_CACHE_VALUE : INTEGER := 3; C_M_AXI_RESULTS_OUT_USER_VALUE : INTEGER := 0 ); port ( ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; m_axi_db_mem_V_AWVALID : OUT STD_LOGIC; m_axi_db_mem_V_AWREADY : IN STD_LOGIC; m_axi_db_mem_V_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_ADDR_WIDTH-1 downto 0); m_axi_db_mem_V_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_ID_WIDTH-1 downto 0); m_axi_db_mem_V_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0); m_axi_db_mem_V_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0); m_axi_db_mem_V_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0); m_axi_db_mem_V_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0); m_axi_db_mem_V_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_db_mem_V_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0); m_axi_db_mem_V_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_db_mem_V_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_db_mem_V_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_AWUSER_WIDTH-1 downto 0); m_axi_db_mem_V_WVALID : OUT STD_LOGIC; m_axi_db_mem_V_WREADY : IN STD_LOGIC; m_axi_db_mem_V_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_DATA_WIDTH-1 downto 0); m_axi_db_mem_V_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_DATA_WIDTH/8-1 downto 0); m_axi_db_mem_V_WLAST : OUT STD_LOGIC; m_axi_db_mem_V_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_ID_WIDTH-1 downto 0); m_axi_db_mem_V_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_WUSER_WIDTH-1 downto 0); m_axi_db_mem_V_ARVALID : OUT STD_LOGIC; m_axi_db_mem_V_ARREADY : IN STD_LOGIC; m_axi_db_mem_V_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_ADDR_WIDTH-1 downto 0); m_axi_db_mem_V_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_ID_WIDTH-1 downto 0); m_axi_db_mem_V_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0); m_axi_db_mem_V_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0); m_axi_db_mem_V_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0); m_axi_db_mem_V_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0); m_axi_db_mem_V_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_db_mem_V_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0); m_axi_db_mem_V_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_db_mem_V_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_db_mem_V_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_ARUSER_WIDTH-1 downto 0); m_axi_db_mem_V_RVALID : IN STD_LOGIC; m_axi_db_mem_V_RREADY : OUT STD_LOGIC; m_axi_db_mem_V_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_DATA_WIDTH-1 downto 0); m_axi_db_mem_V_RLAST : IN STD_LOGIC; m_axi_db_mem_V_RID : IN STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_ID_WIDTH-1 downto 0); m_axi_db_mem_V_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_RUSER_WIDTH-1 downto 0); m_axi_db_mem_V_RRESP : IN STD_LOGIC_VECTOR (1 downto 0); m_axi_db_mem_V_BVALID : IN STD_LOGIC; m_axi_db_mem_V_BREADY : OUT STD_LOGIC; m_axi_db_mem_V_BRESP : IN STD_LOGIC_VECTOR (1 downto 0); m_axi_db_mem_V_BID : IN STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_ID_WIDTH-1 downto 0); m_axi_db_mem_V_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_DB_MEM_V_BUSER_WIDTH-1 downto 0); m_axi_results_out_AWVALID : OUT STD_LOGIC; m_axi_results_out_AWREADY : IN STD_LOGIC; m_axi_results_out_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_ADDR_WIDTH-1 downto 0); m_axi_results_out_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_ID_WIDTH-1 downto 0); m_axi_results_out_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0); m_axi_results_out_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0); m_axi_results_out_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0); m_axi_results_out_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0); m_axi_results_out_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_results_out_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0); m_axi_results_out_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_results_out_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_results_out_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_AWUSER_WIDTH-1 downto 0); m_axi_results_out_WVALID : OUT STD_LOGIC; m_axi_results_out_WREADY : IN STD_LOGIC; m_axi_results_out_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_DATA_WIDTH-1 downto 0); m_axi_results_out_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_DATA_WIDTH/8-1 downto 0); m_axi_results_out_WLAST : OUT STD_LOGIC; m_axi_results_out_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_ID_WIDTH-1 downto 0); m_axi_results_out_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_WUSER_WIDTH-1 downto 0); m_axi_results_out_ARVALID : OUT STD_LOGIC; m_axi_results_out_ARREADY : IN STD_LOGIC; m_axi_results_out_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_ADDR_WIDTH-1 downto 0); m_axi_results_out_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_ID_WIDTH-1 downto 0); m_axi_results_out_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0); m_axi_results_out_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0); m_axi_results_out_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0); m_axi_results_out_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0); m_axi_results_out_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_results_out_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0); m_axi_results_out_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_results_out_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0); m_axi_results_out_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_ARUSER_WIDTH-1 downto 0); m_axi_results_out_RVALID : IN STD_LOGIC; m_axi_results_out_RREADY : OUT STD_LOGIC; m_axi_results_out_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_DATA_WIDTH-1 downto 0); m_axi_results_out_RLAST : IN STD_LOGIC; m_axi_results_out_RID : IN STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_ID_WIDTH-1 downto 0); m_axi_results_out_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_RUSER_WIDTH-1 downto 0); m_axi_results_out_RRESP : IN STD_LOGIC_VECTOR (1 downto 0); m_axi_results_out_BVALID : IN STD_LOGIC; m_axi_results_out_BREADY : OUT STD_LOGIC; m_axi_results_out_BRESP : IN STD_LOGIC_VECTOR (1 downto 0); m_axi_results_out_BID : IN STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_ID_WIDTH-1 downto 0); m_axi_results_out_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RESULTS_OUT_BUSER_WIDTH-1 downto 0); s_axi_AXILiteS_AWVALID : IN STD_LOGIC; s_axi_AXILiteS_AWREADY : OUT STD_LOGIC; s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0); s_axi_AXILiteS_WVALID : IN STD_LOGIC; s_axi_AXILiteS_WREADY : OUT STD_LOGIC; s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0); s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0); s_axi_AXILiteS_ARVALID : IN STD_LOGIC; s_axi_AXILiteS_ARREADY : OUT STD_LOGIC; s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0); s_axi_AXILiteS_RVALID : OUT STD_LOGIC; s_axi_AXILiteS_RREADY : IN STD_LOGIC; s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0); s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); s_axi_AXILiteS_BVALID : OUT STD_LOGIC; s_axi_AXILiteS_BREADY : IN STD_LOGIC; s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); interrupt : OUT STD_LOGIC ); end; architecture behav of contact_discovery is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "contact_discovery,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xczu9eg-ffvb1156-1-i,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.750000,HLS_SYN_LAT=67108871,HLS_SYN_TPT=none,HLS_SYN_MEM=33,HLS_SYN_DSP=0,HLS_SYN_FF=4501,HLS_SYN_LUT=5277}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000001"; constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000010"; constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000100"; constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000001000"; constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000010000"; constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000100000"; constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001000000"; constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010000000"; constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100000000"; constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000000000"; constant ap_ST_fsm_pp0_stage8 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000000000"; constant ap_ST_fsm_pp0_stage9 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000000000"; constant ap_ST_fsm_pp0_stage10 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000001000000000000"; constant ap_ST_fsm_pp0_stage11 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000010000000000000"; constant ap_ST_fsm_pp0_stage12 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000100000000000000"; constant ap_ST_fsm_pp0_stage13 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000001000000000000000"; constant ap_ST_fsm_pp0_stage14 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000010000000000000000"; constant ap_ST_fsm_pp0_stage15 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000100000000000000000"; constant ap_ST_fsm_pp0_stage16 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000001000000000000000000"; constant ap_ST_fsm_pp0_stage17 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000010000000000000000000"; constant ap_ST_fsm_pp0_stage18 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000100000000000000000000"; constant ap_ST_fsm_pp0_stage19 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000001000000000000000000000"; constant ap_ST_fsm_pp0_stage20 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000010000000000000000000000"; constant ap_ST_fsm_pp0_stage21 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000100000000000000000000000"; constant ap_ST_fsm_pp0_stage22 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000001000000000000000000000000"; constant ap_ST_fsm_pp0_stage23 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000010000000000000000000000000"; constant ap_ST_fsm_pp0_stage24 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000100000000000000000000000000"; constant ap_ST_fsm_pp0_stage25 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000001000000000000000000000000000"; constant ap_ST_fsm_pp0_stage26 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000010000000000000000000000000000"; constant ap_ST_fsm_pp0_stage27 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000100000000000000000000000000000"; constant ap_ST_fsm_pp0_stage28 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000001000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage29 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000010000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage30 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000100000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage31 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000001000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage32 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000010000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage33 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000100000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage34 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000001000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage35 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000010000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage36 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000100000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage37 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000001000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage38 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000010000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage39 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000100000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage40 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000001000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage41 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000010000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage42 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000100000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage43 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000001000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage44 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000010000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage45 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000100000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage46 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000001000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage47 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000010000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage48 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000100000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage49 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000001000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage50 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000010000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage51 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000100000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage52 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000001000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage53 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000010000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage54 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000100000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage55 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000001000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage56 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000010000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage57 : STD_LOGIC_VECTOR (69 downto 0) := "0000000000100000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage58 : STD_LOGIC_VECTOR (69 downto 0) := "0000000001000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage59 : STD_LOGIC_VECTOR (69 downto 0) := "0000000010000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage60 : STD_LOGIC_VECTOR (69 downto 0) := "0000000100000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage61 : STD_LOGIC_VECTOR (69 downto 0) := "0000001000000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage62 : STD_LOGIC_VECTOR (69 downto 0) := "0000010000000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_pp0_stage63 : STD_LOGIC_VECTOR (69 downto 0) := "0000100000000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_state83 : STD_LOGIC_VECTOR (69 downto 0) := "0001000000000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_state84 : STD_LOGIC_VECTOR (69 downto 0) := "0010000000000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_state85 : STD_LOGIC_VECTOR (69 downto 0) := "0100000000000000000000000000000000000000000000000000000000000000000000"; constant ap_ST_fsm_state86 : STD_LOGIC_VECTOR (69 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_boolean_1 : BOOLEAN := true; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_boolean_0 : BOOLEAN := false; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011"; constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100"; constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001"; constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20; constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv32_41 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000001"; constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101"; constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111"; constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010"; constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011"; constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100"; constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101"; constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110"; constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111"; constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000"; constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001"; constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010"; constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011"; constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100"; constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101"; constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110"; constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111"; constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000"; constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001"; constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010"; constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011"; constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100"; constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101"; constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110"; constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111"; constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000"; constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001"; constant ap_const_lv32_2A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101010"; constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011"; constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100"; constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101"; constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110"; constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111"; constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000"; constant ap_const_lv32_31 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110001"; constant ap_const_lv32_32 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110010"; constant ap_const_lv32_33 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110011"; constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100"; constant ap_const_lv32_35 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110101"; constant ap_const_lv32_36 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110110"; constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111"; constant ap_const_lv32_38 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111000"; constant ap_const_lv32_39 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111001"; constant ap_const_lv32_3A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111010"; constant ap_const_lv32_3B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111011"; constant ap_const_lv32_3C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111100"; constant ap_const_lv32_3D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111101"; constant ap_const_lv32_3E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111110"; constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111"; constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101"; constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110"; constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant ap_const_lv24_0 : STD_LOGIC_VECTOR (23 downto 0) := "000000000000000000000000"; constant ap_const_lv32_43 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000011"; constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000"; constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000"; constant ap_const_lv32_44 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000100"; constant ap_const_lv25_0 : STD_LOGIC_VECTOR (24 downto 0) := "0000000000000000000000000"; constant ap_const_lv24_1 : STD_LOGIC_VECTOR (23 downto 0) := "000000000000000000000001"; constant ap_const_lv32_45 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000101"; constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000"; constant ap_const_lv512_lc_1 : STD_LOGIC_VECTOR (511 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"; signal ap_rst_n_inv : STD_LOGIC; signal ap_start : STD_LOGIC; signal ap_done : STD_LOGIC; signal ap_idle : STD_LOGIC; signal ap_CS_fsm : STD_LOGIC_VECTOR (69 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_CS_fsm_state1 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none"; signal ap_ready : STD_LOGIC; signal operation : STD_LOGIC_VECTOR (31 downto 0); signal operation_preg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal operation_ap_vld : STD_LOGIC; signal operation_in_sig : STD_LOGIC_VECTOR (31 downto 0); signal operation_ap_vld_preg : STD_LOGIC := '0'; signal operation_ap_vld_in_sig : STD_LOGIC; signal contact_in_V : STD_LOGIC_VECTOR (511 downto 0); signal offset : STD_LOGIC_VECTOR (63 downto 0); signal db_size_in : STD_LOGIC_VECTOR (31 downto 0); signal error_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal error_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0); signal error_out_1_vld_reg : STD_LOGIC := '0'; signal error_out_1_vld_in : STD_LOGIC; signal error_out_1_ack_in : STD_LOGIC; signal contacts_size_out_1_data_reg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal contacts_size_out_1_data_in : STD_LOGIC_VECTOR (31 downto 0); signal contacts_size_out_1_vld_reg : STD_LOGIC := '0'; signal contacts_size_out_1_vld_in : STD_LOGIC; signal contacts_size_out_1_ack_in : STD_LOGIC; signal contacts_size : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal contacts_V_address0 : STD_LOGIC_VECTOR (6 downto 0); signal contacts_V_ce0 : STD_LOGIC; signal contacts_V_we0 : STD_LOGIC; signal contacts_V_q0 : STD_LOGIC_VECTOR (511 downto 0); signal contacts_V_ce1 : STD_LOGIC; signal contacts_V_q1 : STD_LOGIC_VECTOR (511 downto 0); signal operation_blk_n : STD_LOGIC; signal db_mem_V_blk_n_AR : STD_LOGIC; signal ap_CS_fsm_pp0_stage1 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none"; signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0'; signal ap_block_pp0_stage1_flag00000000 : BOOLEAN; signal tmp_127_reg_356 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_8_reg_365 : STD_LOGIC_VECTOR (0 downto 0); signal db_mem_V_blk_n_R : STD_LOGIC; signal ap_CS_fsm_pp0_stage8 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage8 : signal is "none"; signal ap_block_pp0_stage8_flag00000000 : BOOLEAN; signal results_out_blk_n_AW : STD_LOGIC; signal ap_CS_fsm_pp0_stage9 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage9 : signal is "none"; signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0'; signal ap_block_pp0_stage9_flag00000000 : BOOLEAN; signal ap_reg_pp0_iter1_tmp_127_reg_356 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_pp0_iter1_tmp_8_reg_365 : STD_LOGIC_VECTOR (0 downto 0); signal results_out_blk_n_W : STD_LOGIC; signal ap_CS_fsm_pp0_stage10 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage10 : signal is "none"; signal ap_block_pp0_stage10_flag00000000 : BOOLEAN; signal results_out_blk_n_B : STD_LOGIC; signal ap_CS_fsm_pp0_stage15 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage15 : signal is "none"; signal ap_block_pp0_stage15_flag00000000 : BOOLEAN; signal db_mem_V_AWREADY : STD_LOGIC; signal db_mem_V_WREADY : STD_LOGIC; signal db_mem_V_ARVALID : STD_LOGIC; signal db_mem_V_ARREADY : STD_LOGIC; signal db_mem_V_RVALID : STD_LOGIC; signal db_mem_V_RREADY : STD_LOGIC; signal db_mem_V_RDATA : STD_LOGIC_VECTOR (511 downto 0); signal db_mem_V_RLAST : STD_LOGIC; signal db_mem_V_RID : STD_LOGIC_VECTOR (0 downto 0); signal db_mem_V_RUSER : STD_LOGIC_VECTOR (0 downto 0); signal db_mem_V_RRESP : STD_LOGIC_VECTOR (1 downto 0); signal db_mem_V_BVALID : STD_LOGIC; signal db_mem_V_BRESP : STD_LOGIC_VECTOR (1 downto 0); signal db_mem_V_BID : STD_LOGIC_VECTOR (0 downto 0); signal db_mem_V_BUSER : STD_LOGIC_VECTOR (0 downto 0); signal results_out_AWVALID : STD_LOGIC; signal results_out_AWREADY : STD_LOGIC; signal results_out_WVALID : STD_LOGIC; signal results_out_WREADY : STD_LOGIC; signal results_out_WDATA : STD_LOGIC_VECTOR (7 downto 0); signal results_out_ARREADY : STD_LOGIC; signal results_out_RVALID : STD_LOGIC; signal results_out_RDATA : STD_LOGIC_VECTOR (7 downto 0); signal results_out_RLAST : STD_LOGIC; signal results_out_RID : STD_LOGIC_VECTOR (0 downto 0); signal results_out_RUSER : STD_LOGIC_VECTOR (0 downto 0); signal results_out_RRESP : STD_LOGIC_VECTOR (1 downto 0); signal results_out_BVALID : STD_LOGIC; signal results_out_BREADY : STD_LOGIC; signal results_out_BRESP : STD_LOGIC_VECTOR (1 downto 0); signal results_out_BID : STD_LOGIC_VECTOR (0 downto 0); signal results_out_BUSER : STD_LOGIC_VECTOR (0 downto 0); signal database_index_reg_189 : STD_LOGIC_VECTOR (23 downto 0); signal ap_block_state1 : BOOLEAN; signal contact_in_V_read_reg_325 : STD_LOGIC_VECTOR (511 downto 0); signal operation_read_read_fu_130_p2 : STD_LOGIC_VECTOR (31 downto 0); signal contacts_size_load_reg_334 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_126_fu_230_p1 : STD_LOGIC_VECTOR (24 downto 0); signal tmp_126_reg_343 : STD_LOGIC_VECTOR (24 downto 0); signal tmp_5_fu_253_p2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state2 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none"; signal icmp_fu_243_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_127_fu_264_p3 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage0 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none"; signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN; signal ap_block_state67_pp0_stage0_iter1 : BOOLEAN; signal ap_block_pp0_stage0_flag00011001 : BOOLEAN; signal database_index_1_fu_272_p2 : STD_LOGIC_VECTOR (23 downto 0); signal database_index_1_reg_360 : STD_LOGIC_VECTOR (23 downto 0); signal tmp_8_fu_290_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sum_fu_295_p2 : STD_LOGIC_VECTOR (24 downto 0); signal sum_reg_369 : STD_LOGIC_VECTOR (24 downto 0); signal results_out_addr_reg_374 : STD_LOGIC_VECTOR (63 downto 0); signal ap_reg_pp0_iter1_results_out_addr_reg_374 : STD_LOGIC_VECTOR (63 downto 0); signal ap_block_state4_pp0_stage1_iter0 : BOOLEAN; signal ap_sig_ioackin_db_mem_V_ARREADY : STD_LOGIC; signal ap_predicate_op161_readreq_state4 : BOOLEAN; signal ap_block_state4_io : BOOLEAN; signal ap_block_state68_pp0_stage1_iter1 : BOOLEAN; signal ap_block_pp0_stage1_flag00011001 : BOOLEAN; signal db_mem_V_addr_read_reg_385 : STD_LOGIC_VECTOR (511 downto 0); signal ap_predicate_op168_read_state11 : BOOLEAN; signal ap_block_state11_pp0_stage8_iter0 : BOOLEAN; signal ap_block_state75_pp0_stage8_iter1 : BOOLEAN; signal ap_block_pp0_stage8_flag00011001 : BOOLEAN; signal grp_match_db_contact_fu_212_ap_return : STD_LOGIC_VECTOR (0 downto 0); signal tmp_s_reg_390 : STD_LOGIC_VECTOR (0 downto 0); signal ap_block_state12_pp0_stage9_iter0 : BOOLEAN; signal ap_block_state76_pp0_stage9_iter1 : BOOLEAN; signal ap_sig_ioackin_results_out_AWREADY : STD_LOGIC; signal ap_predicate_op234_writereq_state76 : BOOLEAN; signal ap_block_state76_io : BOOLEAN; signal ap_block_pp0_stage9_flag00011001 : BOOLEAN; signal ap_block_pp0_stage0_flag00011011 : BOOLEAN; signal ap_predicate_tran3to83_state3 : BOOLEAN; signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC; signal ap_block_state66_pp0_stage63_iter0 : BOOLEAN; signal ap_block_pp0_stage63_flag00011011 : BOOLEAN; signal ap_CS_fsm_pp0_stage63 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage63 : signal is "none"; signal ap_block_state18_pp0_stage15_iter0 : BOOLEAN; signal ap_predicate_op241_writeresp_state82 : BOOLEAN; signal ap_block_state82_pp0_stage15_iter1 : BOOLEAN; signal ap_block_pp0_stage15_flag00011011 : BOOLEAN; signal grp_match_db_contact_fu_212_ap_start : STD_LOGIC; signal grp_match_db_contact_fu_212_ap_done : STD_LOGIC; signal grp_match_db_contact_fu_212_ap_idle : STD_LOGIC; signal grp_match_db_contact_fu_212_ap_ready : STD_LOGIC; signal grp_match_db_contact_fu_212_ap_ce : STD_LOGIC; signal grp_match_db_contact_fu_212_contacts_V_address0 : STD_LOGIC_VECTOR (6 downto 0); signal grp_match_db_contact_fu_212_contacts_V_ce0 : STD_LOGIC; signal grp_match_db_contact_fu_212_contacts_V_address1 : STD_LOGIC_VECTOR (6 downto 0); signal grp_match_db_contact_fu_212_contacts_V_ce1 : STD_LOGIC; signal ap_predicate_op169_call_state12 : BOOLEAN; signal ap_predicate_op170_call_state13 : BOOLEAN; signal ap_predicate_op171_call_state14 : BOOLEAN; signal ap_predicate_op172_call_state15 : BOOLEAN; signal ap_predicate_op173_call_state16 : BOOLEAN; signal ap_predicate_op174_call_state17 : BOOLEAN; signal ap_predicate_op175_call_state18 : BOOLEAN; signal ap_predicate_op176_call_state19 : BOOLEAN; signal ap_predicate_op177_call_state20 : BOOLEAN; signal ap_predicate_op178_call_state21 : BOOLEAN; signal ap_predicate_op179_call_state22 : BOOLEAN; signal ap_predicate_op180_call_state23 : BOOLEAN; signal ap_predicate_op181_call_state24 : BOOLEAN; signal ap_predicate_op182_call_state25 : BOOLEAN; signal ap_predicate_op183_call_state26 : BOOLEAN; signal ap_predicate_op184_call_state27 : BOOLEAN; signal ap_predicate_op185_call_state28 : BOOLEAN; signal ap_predicate_op186_call_state29 : BOOLEAN; signal ap_predicate_op187_call_state30 : BOOLEAN; signal ap_predicate_op188_call_state31 : BOOLEAN; signal ap_predicate_op189_call_state32 : BOOLEAN; signal ap_predicate_op190_call_state33 : BOOLEAN; signal ap_predicate_op191_call_state34 : BOOLEAN; signal ap_predicate_op192_call_state35 : BOOLEAN; signal ap_predicate_op193_call_state36 : BOOLEAN; signal ap_predicate_op194_call_state37 : BOOLEAN; signal ap_predicate_op195_call_state38 : BOOLEAN; signal ap_predicate_op196_call_state39 : BOOLEAN; signal ap_predicate_op197_call_state40 : BOOLEAN; signal ap_predicate_op198_call_state41 : BOOLEAN; signal ap_predicate_op199_call_state42 : BOOLEAN; signal ap_predicate_op200_call_state43 : BOOLEAN; signal ap_predicate_op201_call_state44 : BOOLEAN; signal ap_predicate_op202_call_state45 : BOOLEAN; signal ap_predicate_op203_call_state46 : BOOLEAN; signal ap_predicate_op204_call_state47 : BOOLEAN; signal ap_predicate_op205_call_state48 : BOOLEAN; signal ap_predicate_op206_call_state49 : BOOLEAN; signal ap_predicate_op207_call_state50 : BOOLEAN; signal ap_predicate_op208_call_state51 : BOOLEAN; signal ap_predicate_op209_call_state52 : BOOLEAN; signal ap_predicate_op210_call_state53 : BOOLEAN; signal ap_predicate_op211_call_state54 : BOOLEAN; signal ap_predicate_op212_call_state55 : BOOLEAN; signal ap_predicate_op213_call_state56 : BOOLEAN; signal ap_predicate_op214_call_state57 : BOOLEAN; signal ap_predicate_op215_call_state58 : BOOLEAN; signal ap_predicate_op216_call_state59 : BOOLEAN; signal ap_predicate_op217_call_state60 : BOOLEAN; signal ap_predicate_op218_call_state61 : BOOLEAN; signal ap_predicate_op219_call_state62 : BOOLEAN; signal ap_predicate_op220_call_state63 : BOOLEAN; signal ap_predicate_op221_call_state64 : BOOLEAN; signal ap_predicate_op222_call_state65 : BOOLEAN; signal ap_predicate_op223_call_state66 : BOOLEAN; signal ap_predicate_op224_call_state67 : BOOLEAN; signal ap_predicate_op225_call_state68 : BOOLEAN; signal ap_predicate_op226_call_state69 : BOOLEAN; signal ap_predicate_op227_call_state70 : BOOLEAN; signal ap_predicate_op228_call_state71 : BOOLEAN; signal ap_predicate_op229_call_state72 : BOOLEAN; signal ap_predicate_op230_call_state73 : BOOLEAN; signal ap_predicate_op231_call_state74 : BOOLEAN; signal ap_predicate_op232_call_state75 : BOOLEAN; signal ap_block_state13_pp0_stage10_iter0_ignore_call5 : BOOLEAN; signal ap_block_state77_pp0_stage10_iter1_ignore_call5 : BOOLEAN; signal ap_sig_ioackin_results_out_WREADY : STD_LOGIC; signal ap_predicate_op236_write_state77 : BOOLEAN; signal ap_block_state77_io : BOOLEAN; signal ap_block_pp0_stage10_flag00011001 : BOOLEAN; signal ap_block_state14_pp0_stage11_iter0_ignore_call5 : BOOLEAN; signal ap_block_state78_pp0_stage11_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage11_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage11 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage11 : signal is "none"; signal ap_block_state15_pp0_stage12_iter0_ignore_call5 : BOOLEAN; signal ap_block_state79_pp0_stage12_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage12_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage12 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage12 : signal is "none"; signal ap_block_state16_pp0_stage13_iter0_ignore_call5 : BOOLEAN; signal ap_block_state80_pp0_stage13_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage13_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage13 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage13 : signal is "none"; signal ap_block_state17_pp0_stage14_iter0_ignore_call5 : BOOLEAN; signal ap_block_state81_pp0_stage14_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage14_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage14 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage14 : signal is "none"; signal ap_block_state18_pp0_stage15_iter0_ignore_call5 : BOOLEAN; signal ap_block_state82_pp0_stage15_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage15_flag00011001 : BOOLEAN; signal ap_block_state19_pp0_stage16_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage16_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage16 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage16 : signal is "none"; signal ap_block_state20_pp0_stage17_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage17_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage17 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage17 : signal is "none"; signal ap_block_state21_pp0_stage18_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage18_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage18 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage18 : signal is "none"; signal ap_block_state22_pp0_stage19_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage19_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage19 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage19 : signal is "none"; signal ap_block_state23_pp0_stage20_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage20_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage20 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage20 : signal is "none"; signal ap_block_state24_pp0_stage21_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage21_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage21 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage21 : signal is "none"; signal ap_block_state25_pp0_stage22_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage22_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage22 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage22 : signal is "none"; signal ap_block_state26_pp0_stage23_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage23_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage23 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage23 : signal is "none"; signal ap_block_state27_pp0_stage24_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage24_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage24 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage24 : signal is "none"; signal ap_block_state28_pp0_stage25_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage25_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage25 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage25 : signal is "none"; signal ap_block_state29_pp0_stage26_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage26_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage26 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage26 : signal is "none"; signal ap_block_state30_pp0_stage27_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage27_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage27 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage27 : signal is "none"; signal ap_block_state31_pp0_stage28_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage28_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage28 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage28 : signal is "none"; signal ap_block_state32_pp0_stage29_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage29_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage29 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage29 : signal is "none"; signal ap_block_state33_pp0_stage30_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage30_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage30 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage30 : signal is "none"; signal ap_block_state34_pp0_stage31_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage31_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage31 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage31 : signal is "none"; signal ap_block_state35_pp0_stage32_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage32_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage32 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage32 : signal is "none"; signal ap_block_state36_pp0_stage33_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage33_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage33 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage33 : signal is "none"; signal ap_block_state37_pp0_stage34_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage34_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage34 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage34 : signal is "none"; signal ap_block_state38_pp0_stage35_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage35_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage35 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage35 : signal is "none"; signal ap_block_state39_pp0_stage36_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage36_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage36 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage36 : signal is "none"; signal ap_block_state40_pp0_stage37_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage37_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage37 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage37 : signal is "none"; signal ap_block_state41_pp0_stage38_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage38_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage38 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage38 : signal is "none"; signal ap_block_state42_pp0_stage39_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage39_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage39 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage39 : signal is "none"; signal ap_block_state43_pp0_stage40_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage40_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage40 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage40 : signal is "none"; signal ap_block_state44_pp0_stage41_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage41_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage41 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage41 : signal is "none"; signal ap_block_state45_pp0_stage42_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage42_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage42 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage42 : signal is "none"; signal ap_block_state46_pp0_stage43_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage43_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage43 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage43 : signal is "none"; signal ap_block_state47_pp0_stage44_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage44_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage44 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage44 : signal is "none"; signal ap_block_state48_pp0_stage45_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage45_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage45 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage45 : signal is "none"; signal ap_block_state49_pp0_stage46_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage46_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage46 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage46 : signal is "none"; signal ap_block_state50_pp0_stage47_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage47_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage47 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage47 : signal is "none"; signal ap_block_state51_pp0_stage48_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage48_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage48 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage48 : signal is "none"; signal ap_block_state52_pp0_stage49_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage49_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage49 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage49 : signal is "none"; signal ap_block_state53_pp0_stage50_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage50_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage50 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage50 : signal is "none"; signal ap_block_state54_pp0_stage51_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage51_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage51 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage51 : signal is "none"; signal ap_block_state55_pp0_stage52_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage52_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage52 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage52 : signal is "none"; signal ap_block_state56_pp0_stage53_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage53_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage53 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage53 : signal is "none"; signal ap_block_state57_pp0_stage54_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage54_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage54 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage54 : signal is "none"; signal ap_block_state58_pp0_stage55_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage55_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage55 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage55 : signal is "none"; signal ap_block_state59_pp0_stage56_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage56_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage56 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage56 : signal is "none"; signal ap_block_state60_pp0_stage57_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage57_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage57 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage57 : signal is "none"; signal ap_block_state61_pp0_stage58_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage58_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage58 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage58 : signal is "none"; signal ap_block_state62_pp0_stage59_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage59_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage59 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage59 : signal is "none"; signal ap_block_state63_pp0_stage60_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage60_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage60 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage60 : signal is "none"; signal ap_block_state64_pp0_stage61_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage61_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage61 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage61 : signal is "none"; signal ap_block_state65_pp0_stage62_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage62_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage62 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage62 : signal is "none"; signal ap_block_state66_pp0_stage63_iter0_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage63_flag00011001 : BOOLEAN; signal ap_block_state5_pp0_stage2_iter0_ignore_call5 : BOOLEAN; signal ap_block_state69_pp0_stage2_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage2_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage2 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none"; signal ap_block_state6_pp0_stage3_iter0_ignore_call5 : BOOLEAN; signal ap_block_state70_pp0_stage3_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage3_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage3 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none"; signal ap_block_state7_pp0_stage4_iter0_ignore_call5 : BOOLEAN; signal ap_block_state71_pp0_stage4_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage4_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage4 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none"; signal ap_block_state8_pp0_stage5_iter0_ignore_call5 : BOOLEAN; signal ap_block_state72_pp0_stage5_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage5_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage5 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none"; signal ap_block_state9_pp0_stage6_iter0_ignore_call5 : BOOLEAN; signal ap_block_state73_pp0_stage6_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage6_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage6 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none"; signal ap_block_state10_pp0_stage7_iter0_ignore_call5 : BOOLEAN; signal ap_block_state74_pp0_stage7_iter1_ignore_call5 : BOOLEAN; signal ap_block_pp0_stage7_flag00011001 : BOOLEAN; signal ap_CS_fsm_pp0_stage7 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none"; signal database_index_phi_fu_193_p4 : STD_LOGIC_VECTOR (23 downto 0); signal ap_block_pp0_stage0_flag00000000 : BOOLEAN; signal storemerge_reg_200 : STD_LOGIC_VECTOR (31 downto 0); signal ap_CS_fsm_state84 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state84 : signal is "none"; signal ap_reg_grp_match_db_contact_fu_212_ap_start : STD_LOGIC := '0'; signal ap_predicate_op169_call_state12_state11 : BOOLEAN; signal ap_block_pp0_stage11_flag00000000 : BOOLEAN; signal ap_block_pp0_stage12_flag00000000 : BOOLEAN; signal ap_block_pp0_stage13_flag00000000 : BOOLEAN; signal ap_block_pp0_stage14_flag00000000 : BOOLEAN; signal ap_block_pp0_stage16_flag00000000 : BOOLEAN; signal ap_block_pp0_stage17_flag00000000 : BOOLEAN; signal ap_block_pp0_stage18_flag00000000 : BOOLEAN; signal ap_block_pp0_stage19_flag00000000 : BOOLEAN; signal ap_block_pp0_stage20_flag00000000 : BOOLEAN; signal ap_block_pp0_stage21_flag00000000 : BOOLEAN; signal ap_block_pp0_stage22_flag00000000 : BOOLEAN; signal ap_block_pp0_stage23_flag00000000 : BOOLEAN; signal ap_block_pp0_stage24_flag00000000 : BOOLEAN; signal ap_block_pp0_stage25_flag00000000 : BOOLEAN; signal ap_block_pp0_stage26_flag00000000 : BOOLEAN; signal ap_block_pp0_stage27_flag00000000 : BOOLEAN; signal ap_block_pp0_stage28_flag00000000 : BOOLEAN; signal ap_block_pp0_stage29_flag00000000 : BOOLEAN; signal ap_block_pp0_stage30_flag00000000 : BOOLEAN; signal ap_block_pp0_stage31_flag00000000 : BOOLEAN; signal ap_block_pp0_stage32_flag00000000 : BOOLEAN; signal ap_block_pp0_stage33_flag00000000 : BOOLEAN; signal ap_block_pp0_stage34_flag00000000 : BOOLEAN; signal ap_block_pp0_stage35_flag00000000 : BOOLEAN; signal ap_block_pp0_stage36_flag00000000 : BOOLEAN; signal ap_block_pp0_stage37_flag00000000 : BOOLEAN; signal ap_block_pp0_stage38_flag00000000 : BOOLEAN; signal ap_block_pp0_stage39_flag00000000 : BOOLEAN; signal ap_block_pp0_stage40_flag00000000 : BOOLEAN; signal ap_block_pp0_stage41_flag00000000 : BOOLEAN; signal ap_block_pp0_stage42_flag00000000 : BOOLEAN; signal ap_block_pp0_stage43_flag00000000 : BOOLEAN; signal ap_block_pp0_stage44_flag00000000 : BOOLEAN; signal ap_block_pp0_stage45_flag00000000 : BOOLEAN; signal ap_block_pp0_stage46_flag00000000 : BOOLEAN; signal ap_block_pp0_stage47_flag00000000 : BOOLEAN; signal ap_block_pp0_stage48_flag00000000 : BOOLEAN; signal ap_block_pp0_stage49_flag00000000 : BOOLEAN; signal ap_block_pp0_stage50_flag00000000 : BOOLEAN; signal ap_block_pp0_stage51_flag00000000 : BOOLEAN; signal ap_block_pp0_stage52_flag00000000 : BOOLEAN; signal ap_block_pp0_stage53_flag00000000 : BOOLEAN; signal ap_block_pp0_stage54_flag00000000 : BOOLEAN; signal ap_block_pp0_stage55_flag00000000 : BOOLEAN; signal ap_block_pp0_stage56_flag00000000 : BOOLEAN; signal ap_block_pp0_stage57_flag00000000 : BOOLEAN; signal ap_block_pp0_stage58_flag00000000 : BOOLEAN; signal ap_block_pp0_stage59_flag00000000 : BOOLEAN; signal ap_block_pp0_stage60_flag00000000 : BOOLEAN; signal ap_block_pp0_stage61_flag00000000 : BOOLEAN; signal ap_block_pp0_stage62_flag00000000 : BOOLEAN; signal ap_block_pp0_stage63_flag00000000 : BOOLEAN; signal ap_block_pp0_stage2_flag00000000 : BOOLEAN; signal ap_block_pp0_stage3_flag00000000 : BOOLEAN; signal ap_block_pp0_stage4_flag00000000 : BOOLEAN; signal ap_block_pp0_stage5_flag00000000 : BOOLEAN; signal ap_block_pp0_stage6_flag00000000 : BOOLEAN; signal ap_block_pp0_stage7_flag00000000 : BOOLEAN; signal tmp_4_fu_249_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_7_fu_282_p1 : STD_LOGIC_VECTOR (63 downto 0); signal sum_cast_fu_306_p1 : STD_LOGIC_VECTOR (63 downto 0); signal ap_reg_ioackin_db_mem_V_ARREADY : STD_LOGIC := '0'; signal ap_block_pp0_stage1_flag00001001 : BOOLEAN; signal ap_reg_ioackin_results_out_AWREADY : STD_LOGIC := '0'; signal ap_block_pp0_stage9_flag00001001 : BOOLEAN; signal ap_reg_ioackin_results_out_WREADY : STD_LOGIC := '0'; signal ap_block_state13_pp0_stage10_iter0 : BOOLEAN; signal ap_block_state77_pp0_stage10_iter1 : BOOLEAN; signal ap_block_pp0_stage10_flag00001001 : BOOLEAN; signal ap_CS_fsm_state85 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state85 : signal is "none"; signal tmp_fu_234_p4 : STD_LOGIC_VECTOR (24 downto 0); signal database_index_cast1_fu_278_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_7_cast_fu_286_p1 : STD_LOGIC_VECTOR (24 downto 0); signal ap_CS_fsm_state86 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state86 : signal is "none"; signal ap_block_state86 : BOOLEAN; signal ap_NS_fsm : STD_LOGIC_VECTOR (69 downto 0); signal ap_block_pp0_stage1_flag00011011 : BOOLEAN; signal ap_block_state5_pp0_stage2_iter0 : BOOLEAN; signal ap_block_state69_pp0_stage2_iter1 : BOOLEAN; signal ap_block_pp0_stage2_flag00011011 : BOOLEAN; signal ap_block_state6_pp0_stage3_iter0 : BOOLEAN; signal ap_block_state70_pp0_stage3_iter1 : BOOLEAN; signal ap_block_pp0_stage3_flag00011011 : BOOLEAN; signal ap_block_state7_pp0_stage4_iter0 : BOOLEAN; signal ap_block_state71_pp0_stage4_iter1 : BOOLEAN; signal ap_block_pp0_stage4_flag00011011 : BOOLEAN; signal ap_block_state8_pp0_stage5_iter0 : BOOLEAN; signal ap_block_state72_pp0_stage5_iter1 : BOOLEAN; signal ap_block_pp0_stage5_flag00011011 : BOOLEAN; signal ap_block_state9_pp0_stage6_iter0 : BOOLEAN; signal ap_block_state73_pp0_stage6_iter1 : BOOLEAN; signal ap_block_pp0_stage6_flag00011011 : BOOLEAN; signal ap_block_state10_pp0_stage7_iter0 : BOOLEAN; signal ap_block_state74_pp0_stage7_iter1 : BOOLEAN; signal ap_block_pp0_stage7_flag00011011 : BOOLEAN; signal ap_block_pp0_stage8_flag00011011 : BOOLEAN; signal ap_block_pp0_stage9_flag00011011 : BOOLEAN; signal ap_block_pp0_stage10_flag00011011 : BOOLEAN; signal ap_block_state14_pp0_stage11_iter0 : BOOLEAN; signal ap_block_state78_pp0_stage11_iter1 : BOOLEAN; signal ap_block_pp0_stage11_flag00011011 : BOOLEAN; signal ap_block_state15_pp0_stage12_iter0 : BOOLEAN; signal ap_block_state79_pp0_stage12_iter1 : BOOLEAN; signal ap_block_pp0_stage12_flag00011011 : BOOLEAN; signal ap_block_state16_pp0_stage13_iter0 : BOOLEAN; signal ap_block_state80_pp0_stage13_iter1 : BOOLEAN; signal ap_block_pp0_stage13_flag00011011 : BOOLEAN; signal ap_block_state17_pp0_stage14_iter0 : BOOLEAN; signal ap_block_state81_pp0_stage14_iter1 : BOOLEAN; signal ap_block_pp0_stage14_flag00011011 : BOOLEAN; signal ap_block_state19_pp0_stage16_iter0 : BOOLEAN; signal ap_block_pp0_stage16_flag00011011 : BOOLEAN; signal ap_block_state20_pp0_stage17_iter0 : BOOLEAN; signal ap_block_pp0_stage17_flag00011011 : BOOLEAN; signal ap_block_state21_pp0_stage18_iter0 : BOOLEAN; signal ap_block_pp0_stage18_flag00011011 : BOOLEAN; signal ap_block_state22_pp0_stage19_iter0 : BOOLEAN; signal ap_block_pp0_stage19_flag00011011 : BOOLEAN; signal ap_block_state23_pp0_stage20_iter0 : BOOLEAN; signal ap_block_pp0_stage20_flag00011011 : BOOLEAN; signal ap_block_state24_pp0_stage21_iter0 : BOOLEAN; signal ap_block_pp0_stage21_flag00011011 : BOOLEAN; signal ap_block_state25_pp0_stage22_iter0 : BOOLEAN; signal ap_block_pp0_stage22_flag00011011 : BOOLEAN; signal ap_block_state26_pp0_stage23_iter0 : BOOLEAN; signal ap_block_pp0_stage23_flag00011011 : BOOLEAN; signal ap_block_state27_pp0_stage24_iter0 : BOOLEAN; signal ap_block_pp0_stage24_flag00011011 : BOOLEAN; signal ap_block_state28_pp0_stage25_iter0 : BOOLEAN; signal ap_block_pp0_stage25_flag00011011 : BOOLEAN; signal ap_block_state29_pp0_stage26_iter0 : BOOLEAN; signal ap_block_pp0_stage26_flag00011011 : BOOLEAN; signal ap_block_state30_pp0_stage27_iter0 : BOOLEAN; signal ap_block_pp0_stage27_flag00011011 : BOOLEAN; signal ap_block_state31_pp0_stage28_iter0 : BOOLEAN; signal ap_block_pp0_stage28_flag00011011 : BOOLEAN; signal ap_block_state32_pp0_stage29_iter0 : BOOLEAN; signal ap_block_pp0_stage29_flag00011011 : BOOLEAN; signal ap_block_state33_pp0_stage30_iter0 : BOOLEAN; signal ap_block_pp0_stage30_flag00011011 : BOOLEAN; signal ap_block_state34_pp0_stage31_iter0 : BOOLEAN; signal ap_block_pp0_stage31_flag00011011 : BOOLEAN; signal ap_block_state35_pp0_stage32_iter0 : BOOLEAN; signal ap_block_pp0_stage32_flag00011011 : BOOLEAN; signal ap_block_state36_pp0_stage33_iter0 : BOOLEAN; signal ap_block_pp0_stage33_flag00011011 : BOOLEAN; signal ap_block_state37_pp0_stage34_iter0 : BOOLEAN; signal ap_block_pp0_stage34_flag00011011 : BOOLEAN; signal ap_block_state38_pp0_stage35_iter0 : BOOLEAN; signal ap_block_pp0_stage35_flag00011011 : BOOLEAN; signal ap_block_state39_pp0_stage36_iter0 : BOOLEAN; signal ap_block_pp0_stage36_flag00011011 : BOOLEAN; signal ap_block_state40_pp0_stage37_iter0 : BOOLEAN; signal ap_block_pp0_stage37_flag00011011 : BOOLEAN; signal ap_block_state41_pp0_stage38_iter0 : BOOLEAN; signal ap_block_pp0_stage38_flag00011011 : BOOLEAN; signal ap_block_state42_pp0_stage39_iter0 : BOOLEAN; signal ap_block_pp0_stage39_flag00011011 : BOOLEAN; signal ap_block_state43_pp0_stage40_iter0 : BOOLEAN; signal ap_block_pp0_stage40_flag00011011 : BOOLEAN; signal ap_block_state44_pp0_stage41_iter0 : BOOLEAN; signal ap_block_pp0_stage41_flag00011011 : BOOLEAN; signal ap_block_state45_pp0_stage42_iter0 : BOOLEAN; signal ap_block_pp0_stage42_flag00011011 : BOOLEAN; signal ap_block_state46_pp0_stage43_iter0 : BOOLEAN; signal ap_block_pp0_stage43_flag00011011 : BOOLEAN; signal ap_block_state47_pp0_stage44_iter0 : BOOLEAN; signal ap_block_pp0_stage44_flag00011011 : BOOLEAN; signal ap_block_state48_pp0_stage45_iter0 : BOOLEAN; signal ap_block_pp0_stage45_flag00011011 : BOOLEAN; signal ap_block_state49_pp0_stage46_iter0 : BOOLEAN; signal ap_block_pp0_stage46_flag00011011 : BOOLEAN; signal ap_block_state50_pp0_stage47_iter0 : BOOLEAN; signal ap_block_pp0_stage47_flag00011011 : BOOLEAN; signal ap_block_state51_pp0_stage48_iter0 : BOOLEAN; signal ap_block_pp0_stage48_flag00011011 : BOOLEAN; signal ap_block_state52_pp0_stage49_iter0 : BOOLEAN; signal ap_block_pp0_stage49_flag00011011 : BOOLEAN; signal ap_block_state53_pp0_stage50_iter0 : BOOLEAN; signal ap_block_pp0_stage50_flag00011011 : BOOLEAN; signal ap_block_state54_pp0_stage51_iter0 : BOOLEAN; signal ap_block_pp0_stage51_flag00011011 : BOOLEAN; signal ap_block_state55_pp0_stage52_iter0 : BOOLEAN; signal ap_block_pp0_stage52_flag00011011 : BOOLEAN; signal ap_block_state56_pp0_stage53_iter0 : BOOLEAN; signal ap_block_pp0_stage53_flag00011011 : BOOLEAN; signal ap_block_state57_pp0_stage54_iter0 : BOOLEAN; signal ap_block_pp0_stage54_flag00011011 : BOOLEAN; signal ap_block_state58_pp0_stage55_iter0 : BOOLEAN; signal ap_block_pp0_stage55_flag00011011 : BOOLEAN; signal ap_block_state59_pp0_stage56_iter0 : BOOLEAN; signal ap_block_pp0_stage56_flag00011011 : BOOLEAN; signal ap_block_state60_pp0_stage57_iter0 : BOOLEAN; signal ap_block_pp0_stage57_flag00011011 : BOOLEAN; signal ap_block_state61_pp0_stage58_iter0 : BOOLEAN; signal ap_block_pp0_stage58_flag00011011 : BOOLEAN; signal ap_block_state62_pp0_stage59_iter0 : BOOLEAN; signal ap_block_pp0_stage59_flag00011011 : BOOLEAN; signal ap_block_state63_pp0_stage60_iter0 : BOOLEAN; signal ap_block_pp0_stage60_flag00011011 : BOOLEAN; signal ap_block_state64_pp0_stage61_iter0 : BOOLEAN; signal ap_block_pp0_stage61_flag00011011 : BOOLEAN; signal ap_block_state65_pp0_stage62_iter0 : BOOLEAN; signal ap_block_pp0_stage62_flag00011011 : BOOLEAN; signal ap_idle_pp0 : STD_LOGIC; signal ap_enable_pp0 : STD_LOGIC; signal ap_condition_2628 : BOOLEAN; signal ap_condition_2632 : BOOLEAN; signal ap_condition_2636 : BOOLEAN; component match_db_contact IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; ap_ce : IN STD_LOGIC; db_item_V : IN STD_LOGIC_VECTOR (511 downto 0); contacts_V_address0 : OUT STD_LOGIC_VECTOR (6 downto 0); contacts_V_ce0 : OUT STD_LOGIC; contacts_V_q0 : IN STD_LOGIC_VECTOR (511 downto 0); contacts_V_address1 : OUT STD_LOGIC_VECTOR (6 downto 0); contacts_V_ce1 : OUT STD_LOGIC; contacts_V_q1 : IN STD_LOGIC_VECTOR (511 downto 0); ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) ); end component; component contact_discoverybkb IS generic ( DataWidth : INTEGER; AddressRange : INTEGER; AddressWidth : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR (6 downto 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR (511 downto 0); q0 : OUT STD_LOGIC_VECTOR (511 downto 0); address1 : IN STD_LOGIC_VECTOR (6 downto 0); ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR (511 downto 0) ); end component; component contact_discovery_AXILiteS_s_axi IS generic ( C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( AWVALID : IN STD_LOGIC; AWREADY : OUT STD_LOGIC; AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); WVALID : IN STD_LOGIC; WREADY : OUT STD_LOGIC; WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0); ARVALID : IN STD_LOGIC; ARREADY : OUT STD_LOGIC; ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); RVALID : OUT STD_LOGIC; RREADY : IN STD_LOGIC; RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); BVALID : OUT STD_LOGIC; BREADY : IN STD_LOGIC; BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; ap_start : OUT STD_LOGIC; interrupt : OUT STD_LOGIC; ap_ready : IN STD_LOGIC; ap_done : IN STD_LOGIC; ap_idle : IN STD_LOGIC; operation : OUT STD_LOGIC_VECTOR (31 downto 0); operation_ap_vld : OUT STD_LOGIC; contact_in_V : OUT STD_LOGIC_VECTOR (511 downto 0); offset : OUT STD_LOGIC_VECTOR (63 downto 0); db_size_in : OUT STD_LOGIC_VECTOR (31 downto 0); error_out : IN STD_LOGIC_VECTOR (31 downto 0); contacts_size_out : IN STD_LOGIC_VECTOR (31 downto 0) ); end component; component contact_discovery_db_mem_V_m_axi IS generic ( USER_DW : INTEGER; USER_AW : INTEGER; USER_MAXREQS : INTEGER; NUM_READ_OUTSTANDING : INTEGER; NUM_WRITE_OUTSTANDING : INTEGER; MAX_READ_BURST_LENGTH : INTEGER; MAX_WRITE_BURST_LENGTH : INTEGER; C_M_AXI_ID_WIDTH : INTEGER; C_M_AXI_ADDR_WIDTH : INTEGER; C_M_AXI_DATA_WIDTH : INTEGER; C_M_AXI_AWUSER_WIDTH : INTEGER; C_M_AXI_ARUSER_WIDTH : INTEGER; C_M_AXI_WUSER_WIDTH : INTEGER; C_M_AXI_RUSER_WIDTH : INTEGER; C_M_AXI_BUSER_WIDTH : INTEGER; C_TARGET_ADDR : INTEGER; C_USER_VALUE : INTEGER; C_PROT_VALUE : INTEGER; C_CACHE_VALUE : INTEGER ); port ( AWVALID : OUT STD_LOGIC; AWREADY : IN STD_LOGIC; AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0); AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0); AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0); AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0); AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0); AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0); AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0); AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0); AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0); AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0); WVALID : OUT STD_LOGIC; WREADY : IN STD_LOGIC; WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0); WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0); WLAST : OUT STD_LOGIC; WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0); ARVALID : OUT STD_LOGIC; ARREADY : IN STD_LOGIC; ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0); ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0); ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0); ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0); ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0); ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0); ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0); ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0); ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0); ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0); RVALID : IN STD_LOGIC; RREADY : OUT STD_LOGIC; RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0); RLAST : IN STD_LOGIC; RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0); RRESP : IN STD_LOGIC_VECTOR (1 downto 0); BVALID : IN STD_LOGIC; BREADY : OUT STD_LOGIC; BRESP : IN STD_LOGIC_VECTOR (1 downto 0); BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; I_ARVALID : IN STD_LOGIC; I_ARREADY : OUT STD_LOGIC; I_ARADDR : IN STD_LOGIC_VECTOR (63 downto 0); I_ARID : IN STD_LOGIC_VECTOR (0 downto 0); I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0); I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0); I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0); I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0); I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0); I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0); I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0); I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0); I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0); I_RVALID : OUT STD_LOGIC; I_RREADY : IN STD_LOGIC; I_RDATA : OUT STD_LOGIC_VECTOR (511 downto 0); I_RID : OUT STD_LOGIC_VECTOR (0 downto 0); I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0); I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); I_RLAST : OUT STD_LOGIC; I_AWVALID : IN STD_LOGIC; I_AWREADY : OUT STD_LOGIC; I_AWADDR : IN STD_LOGIC_VECTOR (63 downto 0); I_AWID : IN STD_LOGIC_VECTOR (0 downto 0); I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0); I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0); I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0); I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0); I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0); I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0); I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0); I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0); I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0); I_WVALID : IN STD_LOGIC; I_WREADY : OUT STD_LOGIC; I_WDATA : IN STD_LOGIC_VECTOR (511 downto 0); I_WID : IN STD_LOGIC_VECTOR (0 downto 0); I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0); I_WLAST : IN STD_LOGIC; I_WSTRB : IN STD_LOGIC_VECTOR (63 downto 0); I_BVALID : OUT STD_LOGIC; I_BREADY : IN STD_LOGIC; I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); I_BID : OUT STD_LOGIC_VECTOR (0 downto 0); I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) ); end component; component contact_discovery_results_out_m_axi IS generic ( USER_DW : INTEGER; USER_AW : INTEGER; USER_MAXREQS : INTEGER; NUM_READ_OUTSTANDING : INTEGER; NUM_WRITE_OUTSTANDING : INTEGER; MAX_READ_BURST_LENGTH : INTEGER; MAX_WRITE_BURST_LENGTH : INTEGER; C_M_AXI_ID_WIDTH : INTEGER; C_M_AXI_ADDR_WIDTH : INTEGER; C_M_AXI_DATA_WIDTH : INTEGER; C_M_AXI_AWUSER_WIDTH : INTEGER; C_M_AXI_ARUSER_WIDTH : INTEGER; C_M_AXI_WUSER_WIDTH : INTEGER; C_M_AXI_RUSER_WIDTH : INTEGER; C_M_AXI_BUSER_WIDTH : INTEGER; C_TARGET_ADDR : INTEGER; C_USER_VALUE : INTEGER; C_PROT_VALUE : INTEGER; C_CACHE_VALUE : INTEGER ); port ( AWVALID : OUT STD_LOGIC; AWREADY : IN STD_LOGIC; AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0); AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0); AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0); AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0); AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0); AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0); AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0); AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0); AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0); AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0); WVALID : OUT STD_LOGIC; WREADY : IN STD_LOGIC; WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0); WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0); WLAST : OUT STD_LOGIC; WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0); ARVALID : OUT STD_LOGIC; ARREADY : IN STD_LOGIC; ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0); ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0); ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0); ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0); ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0); ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0); ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0); ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0); ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0); ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0); RVALID : IN STD_LOGIC; RREADY : OUT STD_LOGIC; RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0); RLAST : IN STD_LOGIC; RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0); RRESP : IN STD_LOGIC_VECTOR (1 downto 0); BVALID : IN STD_LOGIC; BREADY : OUT STD_LOGIC; BRESP : IN STD_LOGIC_VECTOR (1 downto 0); BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0); BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; I_ARVALID : IN STD_LOGIC; I_ARREADY : OUT STD_LOGIC; I_ARADDR : IN STD_LOGIC_VECTOR (63 downto 0); I_ARID : IN STD_LOGIC_VECTOR (0 downto 0); I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0); I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0); I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0); I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0); I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0); I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0); I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0); I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0); I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0); I_RVALID : OUT STD_LOGIC; I_RREADY : IN STD_LOGIC; I_RDATA : OUT STD_LOGIC_VECTOR (7 downto 0); I_RID : OUT STD_LOGIC_VECTOR (0 downto 0); I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0); I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); I_RLAST : OUT STD_LOGIC; I_AWVALID : IN STD_LOGIC; I_AWREADY : OUT STD_LOGIC; I_AWADDR : IN STD_LOGIC_VECTOR (63 downto 0); I_AWID : IN STD_LOGIC_VECTOR (0 downto 0); I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0); I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0); I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0); I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0); I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0); I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0); I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0); I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0); I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0); I_WVALID : IN STD_LOGIC; I_WREADY : OUT STD_LOGIC; I_WDATA : IN STD_LOGIC_VECTOR (7 downto 0); I_WID : IN STD_LOGIC_VECTOR (0 downto 0); I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0); I_WLAST : IN STD_LOGIC; I_WSTRB : IN STD_LOGIC_VECTOR (0 downto 0); I_BVALID : OUT STD_LOGIC; I_BREADY : IN STD_LOGIC; I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); I_BID : OUT STD_LOGIC_VECTOR (0 downto 0); I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) ); end component; begin contacts_V_U : component contact_discoverybkb generic map ( DataWidth => 512, AddressRange => 128, AddressWidth => 7) port map ( clk => ap_clk, reset => ap_rst_n_inv, address0 => contacts_V_address0, ce0 => contacts_V_ce0, we0 => contacts_V_we0, d0 => contact_in_V_read_reg_325, q0 => contacts_V_q0, address1 => grp_match_db_contact_fu_212_contacts_V_address1, ce1 => contacts_V_ce1, q1 => contacts_V_q1); contact_discovery_AXILiteS_s_axi_U : component contact_discovery_AXILiteS_s_axi generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH) port map ( AWVALID => s_axi_AXILiteS_AWVALID, AWREADY => s_axi_AXILiteS_AWREADY, AWADDR => s_axi_AXILiteS_AWADDR, WVALID => s_axi_AXILiteS_WVALID, WREADY => s_axi_AXILiteS_WREADY, WDATA => s_axi_AXILiteS_WDATA, WSTRB => s_axi_AXILiteS_WSTRB, ARVALID => s_axi_AXILiteS_ARVALID, ARREADY => s_axi_AXILiteS_ARREADY, ARADDR => s_axi_AXILiteS_ARADDR, RVALID => s_axi_AXILiteS_RVALID, RREADY => s_axi_AXILiteS_RREADY, RDATA => s_axi_AXILiteS_RDATA, RRESP => s_axi_AXILiteS_RRESP, BVALID => s_axi_AXILiteS_BVALID, BREADY => s_axi_AXILiteS_BREADY, BRESP => s_axi_AXILiteS_BRESP, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, ap_start => ap_start, interrupt => interrupt, ap_ready => ap_ready, ap_done => ap_done, ap_idle => ap_idle, operation => operation, operation_ap_vld => operation_ap_vld, contact_in_V => contact_in_V, offset => offset, db_size_in => db_size_in, error_out => error_out_1_data_reg, contacts_size_out => contacts_size_out_1_data_reg); contact_discovery_db_mem_V_m_axi_U : component contact_discovery_db_mem_V_m_axi generic map ( USER_DW => 512, USER_AW => 64, USER_MAXREQS => 5, NUM_READ_OUTSTANDING => 16, NUM_WRITE_OUTSTANDING => 16, MAX_READ_BURST_LENGTH => 16, MAX_WRITE_BURST_LENGTH => 16, C_M_AXI_ID_WIDTH => C_M_AXI_DB_MEM_V_ID_WIDTH, C_M_AXI_ADDR_WIDTH => C_M_AXI_DB_MEM_V_ADDR_WIDTH, C_M_AXI_DATA_WIDTH => C_M_AXI_DB_MEM_V_DATA_WIDTH, C_M_AXI_AWUSER_WIDTH => C_M_AXI_DB_MEM_V_AWUSER_WIDTH, C_M_AXI_ARUSER_WIDTH => C_M_AXI_DB_MEM_V_ARUSER_WIDTH, C_M_AXI_WUSER_WIDTH => C_M_AXI_DB_MEM_V_WUSER_WIDTH, C_M_AXI_RUSER_WIDTH => C_M_AXI_DB_MEM_V_RUSER_WIDTH, C_M_AXI_BUSER_WIDTH => C_M_AXI_DB_MEM_V_BUSER_WIDTH, C_TARGET_ADDR => C_M_AXI_DB_MEM_V_TARGET_ADDR, C_USER_VALUE => C_M_AXI_DB_MEM_V_USER_VALUE, C_PROT_VALUE => C_M_AXI_DB_MEM_V_PROT_VALUE, C_CACHE_VALUE => C_M_AXI_DB_MEM_V_CACHE_VALUE) port map ( AWVALID => m_axi_db_mem_V_AWVALID, AWREADY => m_axi_db_mem_V_AWREADY, AWADDR => m_axi_db_mem_V_AWADDR, AWID => m_axi_db_mem_V_AWID, AWLEN => m_axi_db_mem_V_AWLEN, AWSIZE => m_axi_db_mem_V_AWSIZE, AWBURST => m_axi_db_mem_V_AWBURST, AWLOCK => m_axi_db_mem_V_AWLOCK, AWCACHE => m_axi_db_mem_V_AWCACHE, AWPROT => m_axi_db_mem_V_AWPROT, AWQOS => m_axi_db_mem_V_AWQOS, AWREGION => m_axi_db_mem_V_AWREGION, AWUSER => m_axi_db_mem_V_AWUSER, WVALID => m_axi_db_mem_V_WVALID, WREADY => m_axi_db_mem_V_WREADY, WDATA => m_axi_db_mem_V_WDATA, WSTRB => m_axi_db_mem_V_WSTRB, WLAST => m_axi_db_mem_V_WLAST, WID => m_axi_db_mem_V_WID, WUSER => m_axi_db_mem_V_WUSER, ARVALID => m_axi_db_mem_V_ARVALID, ARREADY => m_axi_db_mem_V_ARREADY, ARADDR => m_axi_db_mem_V_ARADDR, ARID => m_axi_db_mem_V_ARID, ARLEN => m_axi_db_mem_V_ARLEN, ARSIZE => m_axi_db_mem_V_ARSIZE, ARBURST => m_axi_db_mem_V_ARBURST, ARLOCK => m_axi_db_mem_V_ARLOCK, ARCACHE => m_axi_db_mem_V_ARCACHE, ARPROT => m_axi_db_mem_V_ARPROT, ARQOS => m_axi_db_mem_V_ARQOS, ARREGION => m_axi_db_mem_V_ARREGION, ARUSER => m_axi_db_mem_V_ARUSER, RVALID => m_axi_db_mem_V_RVALID, RREADY => m_axi_db_mem_V_RREADY, RDATA => m_axi_db_mem_V_RDATA, RLAST => m_axi_db_mem_V_RLAST, RID => m_axi_db_mem_V_RID, RUSER => m_axi_db_mem_V_RUSER, RRESP => m_axi_db_mem_V_RRESP, BVALID => m_axi_db_mem_V_BVALID, BREADY => m_axi_db_mem_V_BREADY, BRESP => m_axi_db_mem_V_BRESP, BID => m_axi_db_mem_V_BID, BUSER => m_axi_db_mem_V_BUSER, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, I_ARVALID => db_mem_V_ARVALID, I_ARREADY => db_mem_V_ARREADY, I_ARADDR => sum_cast_fu_306_p1, I_ARID => ap_const_lv1_0, I_ARLEN => ap_const_lv32_1, I_ARSIZE => ap_const_lv3_0, I_ARLOCK => ap_const_lv2_0, I_ARCACHE => ap_const_lv4_0, I_ARQOS => ap_const_lv4_0, I_ARPROT => ap_const_lv3_0, I_ARUSER => ap_const_lv1_0, I_ARBURST => ap_const_lv2_0, I_ARREGION => ap_const_lv4_0, I_RVALID => db_mem_V_RVALID, I_RREADY => db_mem_V_RREADY, I_RDATA => db_mem_V_RDATA, I_RID => db_mem_V_RID, I_RUSER => db_mem_V_RUSER, I_RRESP => db_mem_V_RRESP, I_RLAST => db_mem_V_RLAST, I_AWVALID => ap_const_logic_0, I_AWREADY => db_mem_V_AWREADY, I_AWADDR => ap_const_lv64_0, I_AWID => ap_const_lv1_0, I_AWLEN => ap_const_lv32_0, I_AWSIZE => ap_const_lv3_0, I_AWLOCK => ap_const_lv2_0, I_AWCACHE => ap_const_lv4_0, I_AWQOS => ap_const_lv4_0, I_AWPROT => ap_const_lv3_0, I_AWUSER => ap_const_lv1_0, I_AWBURST => ap_const_lv2_0, I_AWREGION => ap_const_lv4_0, I_WVALID => ap_const_logic_0, I_WREADY => db_mem_V_WREADY, I_WDATA => ap_const_lv512_lc_1, I_WID => ap_const_lv1_0, I_WUSER => ap_const_lv1_0, I_WLAST => ap_const_logic_0, I_WSTRB => ap_const_lv64_0, I_BVALID => db_mem_V_BVALID, I_BREADY => ap_const_logic_0, I_BRESP => db_mem_V_BRESP, I_BID => db_mem_V_BID, I_BUSER => db_mem_V_BUSER); contact_discovery_results_out_m_axi_U : component contact_discovery_results_out_m_axi generic map ( USER_DW => 8, USER_AW => 64, USER_MAXREQS => 5, NUM_READ_OUTSTANDING => 16, NUM_WRITE_OUTSTANDING => 16, MAX_READ_BURST_LENGTH => 16, MAX_WRITE_BURST_LENGTH => 16, C_M_AXI_ID_WIDTH => C_M_AXI_RESULTS_OUT_ID_WIDTH, C_M_AXI_ADDR_WIDTH => C_M_AXI_RESULTS_OUT_ADDR_WIDTH, C_M_AXI_DATA_WIDTH => C_M_AXI_RESULTS_OUT_DATA_WIDTH, C_M_AXI_AWUSER_WIDTH => C_M_AXI_RESULTS_OUT_AWUSER_WIDTH, C_M_AXI_ARUSER_WIDTH => C_M_AXI_RESULTS_OUT_ARUSER_WIDTH, C_M_AXI_WUSER_WIDTH => C_M_AXI_RESULTS_OUT_WUSER_WIDTH, C_M_AXI_RUSER_WIDTH => C_M_AXI_RESULTS_OUT_RUSER_WIDTH, C_M_AXI_BUSER_WIDTH => C_M_AXI_RESULTS_OUT_BUSER_WIDTH, C_TARGET_ADDR => C_M_AXI_RESULTS_OUT_TARGET_ADDR, C_USER_VALUE => C_M_AXI_RESULTS_OUT_USER_VALUE, C_PROT_VALUE => C_M_AXI_RESULTS_OUT_PROT_VALUE, C_CACHE_VALUE => C_M_AXI_RESULTS_OUT_CACHE_VALUE) port map ( AWVALID => m_axi_results_out_AWVALID, AWREADY => m_axi_results_out_AWREADY, AWADDR => m_axi_results_out_AWADDR, AWID => m_axi_results_out_AWID, AWLEN => m_axi_results_out_AWLEN, AWSIZE => m_axi_results_out_AWSIZE, AWBURST => m_axi_results_out_AWBURST, AWLOCK => m_axi_results_out_AWLOCK, AWCACHE => m_axi_results_out_AWCACHE, AWPROT => m_axi_results_out_AWPROT, AWQOS => m_axi_results_out_AWQOS, AWREGION => m_axi_results_out_AWREGION, AWUSER => m_axi_results_out_AWUSER, WVALID => m_axi_results_out_WVALID, WREADY => m_axi_results_out_WREADY, WDATA => m_axi_results_out_WDATA, WSTRB => m_axi_results_out_WSTRB, WLAST => m_axi_results_out_WLAST, WID => m_axi_results_out_WID, WUSER => m_axi_results_out_WUSER, ARVALID => m_axi_results_out_ARVALID, ARREADY => m_axi_results_out_ARREADY, ARADDR => m_axi_results_out_ARADDR, ARID => m_axi_results_out_ARID, ARLEN => m_axi_results_out_ARLEN, ARSIZE => m_axi_results_out_ARSIZE, ARBURST => m_axi_results_out_ARBURST, ARLOCK => m_axi_results_out_ARLOCK, ARCACHE => m_axi_results_out_ARCACHE, ARPROT => m_axi_results_out_ARPROT, ARQOS => m_axi_results_out_ARQOS, ARREGION => m_axi_results_out_ARREGION, ARUSER => m_axi_results_out_ARUSER, RVALID => m_axi_results_out_RVALID, RREADY => m_axi_results_out_RREADY, RDATA => m_axi_results_out_RDATA, RLAST => m_axi_results_out_RLAST, RID => m_axi_results_out_RID, RUSER => m_axi_results_out_RUSER, RRESP => m_axi_results_out_RRESP, BVALID => m_axi_results_out_BVALID, BREADY => m_axi_results_out_BREADY, BRESP => m_axi_results_out_BRESP, BID => m_axi_results_out_BID, BUSER => m_axi_results_out_BUSER, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, I_ARVALID => ap_const_logic_0, I_ARREADY => results_out_ARREADY, I_ARADDR => ap_const_lv64_0, I_ARID => ap_const_lv1_0, I_ARLEN => ap_const_lv32_0, I_ARSIZE => ap_const_lv3_0, I_ARLOCK => ap_const_lv2_0, I_ARCACHE => ap_const_lv4_0, I_ARQOS => ap_const_lv4_0, I_ARPROT => ap_const_lv3_0, I_ARUSER => ap_const_lv1_0, I_ARBURST => ap_const_lv2_0, I_ARREGION => ap_const_lv4_0, I_RVALID => results_out_RVALID, I_RREADY => ap_const_logic_0, I_RDATA => results_out_RDATA, I_RID => results_out_RID, I_RUSER => results_out_RUSER, I_RRESP => results_out_RRESP, I_RLAST => results_out_RLAST, I_AWVALID => results_out_AWVALID, I_AWREADY => results_out_AWREADY, I_AWADDR => ap_reg_pp0_iter1_results_out_addr_reg_374, I_AWID => ap_const_lv1_0, I_AWLEN => ap_const_lv32_1, I_AWSIZE => ap_const_lv3_0, I_AWLOCK => ap_const_lv2_0, I_AWCACHE => ap_const_lv4_0, I_AWQOS => ap_const_lv4_0, I_AWPROT => ap_const_lv3_0, I_AWUSER => ap_const_lv1_0, I_AWBURST => ap_const_lv2_0, I_AWREGION => ap_const_lv4_0, I_WVALID => results_out_WVALID, I_WREADY => results_out_WREADY, I_WDATA => results_out_WDATA, I_WID => ap_const_lv1_0, I_WUSER => ap_const_lv1_0, I_WLAST => ap_const_logic_0, I_WSTRB => ap_const_lv1_1, I_BVALID => results_out_BVALID, I_BREADY => results_out_BREADY, I_BRESP => results_out_BRESP, I_BID => results_out_BID, I_BUSER => results_out_BUSER); grp_match_db_contact_fu_212 : component match_db_contact port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => grp_match_db_contact_fu_212_ap_start, ap_done => grp_match_db_contact_fu_212_ap_done, ap_idle => grp_match_db_contact_fu_212_ap_idle, ap_ready => grp_match_db_contact_fu_212_ap_ready, ap_ce => grp_match_db_contact_fu_212_ap_ce, db_item_V => db_mem_V_addr_read_reg_385, contacts_V_address0 => grp_match_db_contact_fu_212_contacts_V_address0, contacts_V_ce0 => grp_match_db_contact_fu_212_contacts_V_ce0, contacts_V_q0 => contacts_V_q0, contacts_V_address1 => grp_match_db_contact_fu_212_contacts_V_address1, contacts_V_ce1 => grp_match_db_contact_fu_212_contacts_V_ce1, contacts_V_q1 => contacts_V_q1, ap_return => grp_match_db_contact_fu_212_ap_return); ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_CS_fsm <= ap_ST_fsm_state1; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_enable_reg_pp0_iter0 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3))) then ap_enable_reg_pp0_iter0 <= ap_const_logic_0; elsif (((operation_read_read_fu_130_p2 = ap_const_lv32_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then ap_enable_reg_pp0_iter0 <= ap_const_logic_1; end if; end if; end if; end process; ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_enable_reg_pp0_iter1 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3) and (((ap_block_pp0_stage63_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0))))) then ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state3 xor ap_const_logic_1); elsif ((((ap_block_pp0_stage63_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0)))) then ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0; elsif (((operation_read_read_fu_130_p2 = ap_const_lv32_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then ap_enable_reg_pp0_iter1 <= ap_const_logic_0; end if; end if; end if; end process; ap_reg_grp_match_db_contact_fu_212_ap_start_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_grp_match_db_contact_fu_212_ap_start <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op169_call_state12_state11))) then ap_reg_grp_match_db_contact_fu_212_ap_start <= ap_const_logic_1; elsif ((ap_const_logic_1 = grp_match_db_contact_fu_212_ap_ready)) then ap_reg_grp_match_db_contact_fu_212_ap_start <= ap_const_logic_0; end if; end if; end if; end process; ap_reg_ioackin_db_mem_V_ARREADY_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ioackin_db_mem_V_ARREADY <= ap_const_logic_0; else if ((ap_condition_2628 = ap_const_boolean_1)) then if ((ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) then ap_reg_ioackin_db_mem_V_ARREADY <= ap_const_logic_0; elsif (((ap_const_logic_1 = db_mem_V_ARREADY) and (ap_block_pp0_stage1_flag00001001 = ap_const_boolean_0))) then ap_reg_ioackin_db_mem_V_ARREADY <= ap_const_logic_1; end if; end if; end if; end if; end process; ap_reg_ioackin_results_out_AWREADY_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ioackin_results_out_AWREADY <= ap_const_logic_0; else if ((ap_condition_2632 = ap_const_boolean_1)) then if ((ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) then ap_reg_ioackin_results_out_AWREADY <= ap_const_logic_0; elsif (((ap_const_logic_1 = results_out_AWREADY) and (ap_block_pp0_stage9_flag00001001 = ap_const_boolean_0))) then ap_reg_ioackin_results_out_AWREADY <= ap_const_logic_1; end if; end if; end if; end if; end process; ap_reg_ioackin_results_out_WREADY_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ioackin_results_out_WREADY <= ap_const_logic_0; else if ((ap_condition_2636 = ap_const_boolean_1)) then if ((ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) then ap_reg_ioackin_results_out_WREADY <= ap_const_logic_0; elsif (((ap_const_logic_1 = results_out_WREADY) and (ap_block_pp0_stage10_flag00001001 = ap_const_boolean_0))) then ap_reg_ioackin_results_out_WREADY <= ap_const_logic_1; end if; end if; end if; end if; end process; operation_ap_vld_preg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then operation_ap_vld_preg <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_CS_fsm_state86) and not(((ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then operation_ap_vld_preg <= ap_const_logic_0; elsif (((ap_const_logic_1 = operation_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then operation_ap_vld_preg <= operation_ap_vld; end if; end if; end if; end process; operation_preg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then operation_preg <= ap_const_lv32_0; else if (((ap_const_logic_1 = operation_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then operation_preg <= operation; end if; end if; end if; end process; contacts_size_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_130_p2) and (ap_const_lv1_0 = icmp_fu_243_p2))) then contacts_size <= tmp_5_fu_253_p2; elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_2))) then contacts_size <= ap_const_lv32_0; end if; end if; end process; contacts_size_out_1_vld_reg_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then end if; end process; database_index_reg_189_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then database_index_reg_189 <= database_index_1_reg_360; elsif (((operation_read_read_fu_130_p2 = ap_const_lv32_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then database_index_reg_189 <= ap_const_lv24_0; end if; end if; end process; error_out_1_vld_reg_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then end if; end process; storemerge_reg_200_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_CS_fsm_state84)) then storemerge_reg_200 <= contacts_size_load_reg_334; elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_130_p2) and (ap_const_lv1_0 = icmp_fu_243_p2))) then storemerge_reg_200 <= tmp_5_fu_253_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then ap_reg_pp0_iter1_results_out_addr_reg_374(23 downto 0) <= results_out_addr_reg_374(23 downto 0); ap_reg_pp0_iter1_tmp_127_reg_356 <= tmp_127_reg_356; ap_reg_pp0_iter1_tmp_8_reg_365 <= tmp_8_reg_365; tmp_127_reg_356 <= database_index_phi_fu_193_p4(23 downto 23); end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))))) then contact_in_V_read_reg_325 <= contact_in_V; contacts_size_load_reg_334 <= contacts_size; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = contacts_size_out_1_vld_in) and (ap_const_logic_0 = contacts_size_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = contacts_size_out_1_vld_in) and (ap_const_logic_1 = contacts_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then contacts_size_out_1_data_reg <= contacts_size_out_1_data_in; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then database_index_1_reg_360 <= database_index_1_fu_272_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_boolean_1 = ap_predicate_op168_read_state11) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then db_mem_V_addr_read_reg_385 <= db_mem_V_RDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = error_out_1_vld_in) and (ap_const_logic_0 = error_out_1_vld_reg)) or (not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) and (ap_const_logic_1 = error_out_1_vld_in) and (ap_const_logic_1 = error_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then error_out_1_data_reg <= error_out_1_data_in; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = tmp_127_fu_264_p3) and (ap_const_lv1_1 = tmp_8_fu_290_p2))) then results_out_addr_reg_374(23 downto 0) <= tmp_7_fu_282_p1(23 downto 0); sum_reg_369 <= sum_fu_295_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_1))) then tmp_126_reg_343 <= tmp_126_fu_230_p1; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = tmp_127_fu_264_p3))) then tmp_8_reg_365 <= tmp_8_fu_290_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_boolean_1 = ap_predicate_op234_writereq_state76) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then tmp_s_reg_390 <= grp_match_db_contact_fu_212_ap_return; end if; end if; end process; results_out_addr_reg_374(63 downto 24) <= "0000000000000000000000000000000000000000"; ap_reg_pp0_iter1_results_out_addr_reg_374(63 downto 24) <= "0000000000000000000000000000000000000000"; ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, operation_ap_vld_in_sig, error_out_1_ack_in, contacts_size_out_1_ack_in, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage15, operation_read_read_fu_130_p2, ap_CS_fsm_state2, icmp_fu_243_p2, ap_block_pp0_stage0_flag00011011, ap_predicate_tran3to83_state3, ap_block_pp0_stage63_flag00011011, ap_block_pp0_stage15_flag00011011, ap_CS_fsm_state86, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage6_flag00011011, ap_block_pp0_stage7_flag00011011, ap_block_pp0_stage8_flag00011011, ap_block_pp0_stage9_flag00011011, ap_block_pp0_stage10_flag00011011, ap_block_pp0_stage11_flag00011011, ap_block_pp0_stage12_flag00011011, ap_block_pp0_stage13_flag00011011, ap_block_pp0_stage14_flag00011011, ap_block_pp0_stage16_flag00011011, ap_block_pp0_stage17_flag00011011, ap_block_pp0_stage18_flag00011011, ap_block_pp0_stage19_flag00011011, ap_block_pp0_stage20_flag00011011, ap_block_pp0_stage21_flag00011011, ap_block_pp0_stage22_flag00011011, ap_block_pp0_stage23_flag00011011, ap_block_pp0_stage24_flag00011011, ap_block_pp0_stage25_flag00011011, ap_block_pp0_stage26_flag00011011, ap_block_pp0_stage27_flag00011011, ap_block_pp0_stage28_flag00011011, ap_block_pp0_stage29_flag00011011, ap_block_pp0_stage30_flag00011011, ap_block_pp0_stage31_flag00011011, ap_block_pp0_stage32_flag00011011, ap_block_pp0_stage33_flag00011011, ap_block_pp0_stage34_flag00011011, ap_block_pp0_stage35_flag00011011, ap_block_pp0_stage36_flag00011011, ap_block_pp0_stage37_flag00011011, ap_block_pp0_stage38_flag00011011, ap_block_pp0_stage39_flag00011011, ap_block_pp0_stage40_flag00011011, ap_block_pp0_stage41_flag00011011, ap_block_pp0_stage42_flag00011011, ap_block_pp0_stage43_flag00011011, ap_block_pp0_stage44_flag00011011, ap_block_pp0_stage45_flag00011011, ap_block_pp0_stage46_flag00011011, ap_block_pp0_stage47_flag00011011, ap_block_pp0_stage48_flag00011011, ap_block_pp0_stage49_flag00011011, ap_block_pp0_stage50_flag00011011, ap_block_pp0_stage51_flag00011011, ap_block_pp0_stage52_flag00011011, ap_block_pp0_stage53_flag00011011, ap_block_pp0_stage54_flag00011011, ap_block_pp0_stage55_flag00011011, ap_block_pp0_stage56_flag00011011, ap_block_pp0_stage57_flag00011011, ap_block_pp0_stage58_flag00011011, ap_block_pp0_stage59_flag00011011, ap_block_pp0_stage60_flag00011011, ap_block_pp0_stage61_flag00011011, ap_block_pp0_stage62_flag00011011) begin case ap_CS_fsm is when ap_ST_fsm_state1 => if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))))) then ap_NS_fsm <= ap_ST_fsm_state2; else ap_NS_fsm <= ap_ST_fsm_state1; end if; when ap_ST_fsm_state2 => if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_130_p2) and (ap_const_lv1_0 = icmp_fu_243_p2))) then ap_NS_fsm <= ap_ST_fsm_state85; elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_130_p2) and (ap_const_lv1_1 = icmp_fu_243_p2))) then ap_NS_fsm <= ap_ST_fsm_state84; elsif (((operation_read_read_fu_130_p2 = ap_const_lv32_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then ap_NS_fsm <= ap_ST_fsm_pp0_stage0; else ap_NS_fsm <= ap_ST_fsm_state86; end if; when ap_ST_fsm_pp0_stage0 => if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_tran3to83_state3) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then ap_NS_fsm <= ap_ST_fsm_pp0_stage1; elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_tran3to83_state3) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_fsm_state83; else ap_NS_fsm <= ap_ST_fsm_pp0_stage0; end if; when ap_ST_fsm_pp0_stage1 => if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage2; else ap_NS_fsm <= ap_ST_fsm_pp0_stage1; end if; when ap_ST_fsm_pp0_stage2 => if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage3; else ap_NS_fsm <= ap_ST_fsm_pp0_stage2; end if; when ap_ST_fsm_pp0_stage3 => if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage4; else ap_NS_fsm <= ap_ST_fsm_pp0_stage3; end if; when ap_ST_fsm_pp0_stage4 => if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage5; else ap_NS_fsm <= ap_ST_fsm_pp0_stage4; end if; when ap_ST_fsm_pp0_stage5 => if ((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage6; else ap_NS_fsm <= ap_ST_fsm_pp0_stage5; end if; when ap_ST_fsm_pp0_stage6 => if ((ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage7; else ap_NS_fsm <= ap_ST_fsm_pp0_stage6; end if; when ap_ST_fsm_pp0_stage7 => if ((ap_block_pp0_stage7_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage8; else ap_NS_fsm <= ap_ST_fsm_pp0_stage7; end if; when ap_ST_fsm_pp0_stage8 => if ((ap_block_pp0_stage8_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage9; else ap_NS_fsm <= ap_ST_fsm_pp0_stage8; end if; when ap_ST_fsm_pp0_stage9 => if ((ap_block_pp0_stage9_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage10; else ap_NS_fsm <= ap_ST_fsm_pp0_stage9; end if; when ap_ST_fsm_pp0_stage10 => if ((ap_block_pp0_stage10_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage11; else ap_NS_fsm <= ap_ST_fsm_pp0_stage10; end if; when ap_ST_fsm_pp0_stage11 => if ((ap_block_pp0_stage11_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage12; else ap_NS_fsm <= ap_ST_fsm_pp0_stage11; end if; when ap_ST_fsm_pp0_stage12 => if ((ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage13; else ap_NS_fsm <= ap_ST_fsm_pp0_stage12; end if; when ap_ST_fsm_pp0_stage13 => if ((ap_block_pp0_stage13_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage14; else ap_NS_fsm <= ap_ST_fsm_pp0_stage13; end if; when ap_ST_fsm_pp0_stage14 => if ((ap_block_pp0_stage14_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage15; else ap_NS_fsm <= ap_ST_fsm_pp0_stage14; end if; when ap_ST_fsm_pp0_stage15 => if (((ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))))) then ap_NS_fsm <= ap_ST_fsm_pp0_stage16; elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then ap_NS_fsm <= ap_ST_fsm_state83; else ap_NS_fsm <= ap_ST_fsm_pp0_stage15; end if; when ap_ST_fsm_pp0_stage16 => if ((ap_block_pp0_stage16_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage17; else ap_NS_fsm <= ap_ST_fsm_pp0_stage16; end if; when ap_ST_fsm_pp0_stage17 => if ((ap_block_pp0_stage17_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage18; else ap_NS_fsm <= ap_ST_fsm_pp0_stage17; end if; when ap_ST_fsm_pp0_stage18 => if ((ap_block_pp0_stage18_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage19; else ap_NS_fsm <= ap_ST_fsm_pp0_stage18; end if; when ap_ST_fsm_pp0_stage19 => if ((ap_block_pp0_stage19_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage20; else ap_NS_fsm <= ap_ST_fsm_pp0_stage19; end if; when ap_ST_fsm_pp0_stage20 => if ((ap_block_pp0_stage20_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage21; else ap_NS_fsm <= ap_ST_fsm_pp0_stage20; end if; when ap_ST_fsm_pp0_stage21 => if ((ap_block_pp0_stage21_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage22; else ap_NS_fsm <= ap_ST_fsm_pp0_stage21; end if; when ap_ST_fsm_pp0_stage22 => if ((ap_block_pp0_stage22_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage23; else ap_NS_fsm <= ap_ST_fsm_pp0_stage22; end if; when ap_ST_fsm_pp0_stage23 => if ((ap_block_pp0_stage23_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage24; else ap_NS_fsm <= ap_ST_fsm_pp0_stage23; end if; when ap_ST_fsm_pp0_stage24 => if ((ap_block_pp0_stage24_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage25; else ap_NS_fsm <= ap_ST_fsm_pp0_stage24; end if; when ap_ST_fsm_pp0_stage25 => if ((ap_block_pp0_stage25_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage26; else ap_NS_fsm <= ap_ST_fsm_pp0_stage25; end if; when ap_ST_fsm_pp0_stage26 => if ((ap_block_pp0_stage26_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage27; else ap_NS_fsm <= ap_ST_fsm_pp0_stage26; end if; when ap_ST_fsm_pp0_stage27 => if ((ap_block_pp0_stage27_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage28; else ap_NS_fsm <= ap_ST_fsm_pp0_stage27; end if; when ap_ST_fsm_pp0_stage28 => if ((ap_block_pp0_stage28_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage29; else ap_NS_fsm <= ap_ST_fsm_pp0_stage28; end if; when ap_ST_fsm_pp0_stage29 => if ((ap_block_pp0_stage29_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage30; else ap_NS_fsm <= ap_ST_fsm_pp0_stage29; end if; when ap_ST_fsm_pp0_stage30 => if ((ap_block_pp0_stage30_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage31; else ap_NS_fsm <= ap_ST_fsm_pp0_stage30; end if; when ap_ST_fsm_pp0_stage31 => if ((ap_block_pp0_stage31_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage32; else ap_NS_fsm <= ap_ST_fsm_pp0_stage31; end if; when ap_ST_fsm_pp0_stage32 => if ((ap_block_pp0_stage32_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage33; else ap_NS_fsm <= ap_ST_fsm_pp0_stage32; end if; when ap_ST_fsm_pp0_stage33 => if ((ap_block_pp0_stage33_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage34; else ap_NS_fsm <= ap_ST_fsm_pp0_stage33; end if; when ap_ST_fsm_pp0_stage34 => if ((ap_block_pp0_stage34_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage35; else ap_NS_fsm <= ap_ST_fsm_pp0_stage34; end if; when ap_ST_fsm_pp0_stage35 => if ((ap_block_pp0_stage35_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage36; else ap_NS_fsm <= ap_ST_fsm_pp0_stage35; end if; when ap_ST_fsm_pp0_stage36 => if ((ap_block_pp0_stage36_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage37; else ap_NS_fsm <= ap_ST_fsm_pp0_stage36; end if; when ap_ST_fsm_pp0_stage37 => if ((ap_block_pp0_stage37_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage38; else ap_NS_fsm <= ap_ST_fsm_pp0_stage37; end if; when ap_ST_fsm_pp0_stage38 => if ((ap_block_pp0_stage38_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage39; else ap_NS_fsm <= ap_ST_fsm_pp0_stage38; end if; when ap_ST_fsm_pp0_stage39 => if ((ap_block_pp0_stage39_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage40; else ap_NS_fsm <= ap_ST_fsm_pp0_stage39; end if; when ap_ST_fsm_pp0_stage40 => if ((ap_block_pp0_stage40_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage41; else ap_NS_fsm <= ap_ST_fsm_pp0_stage40; end if; when ap_ST_fsm_pp0_stage41 => if ((ap_block_pp0_stage41_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage42; else ap_NS_fsm <= ap_ST_fsm_pp0_stage41; end if; when ap_ST_fsm_pp0_stage42 => if ((ap_block_pp0_stage42_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage43; else ap_NS_fsm <= ap_ST_fsm_pp0_stage42; end if; when ap_ST_fsm_pp0_stage43 => if ((ap_block_pp0_stage43_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage44; else ap_NS_fsm <= ap_ST_fsm_pp0_stage43; end if; when ap_ST_fsm_pp0_stage44 => if ((ap_block_pp0_stage44_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage45; else ap_NS_fsm <= ap_ST_fsm_pp0_stage44; end if; when ap_ST_fsm_pp0_stage45 => if ((ap_block_pp0_stage45_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage46; else ap_NS_fsm <= ap_ST_fsm_pp0_stage45; end if; when ap_ST_fsm_pp0_stage46 => if ((ap_block_pp0_stage46_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage47; else ap_NS_fsm <= ap_ST_fsm_pp0_stage46; end if; when ap_ST_fsm_pp0_stage47 => if ((ap_block_pp0_stage47_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage48; else ap_NS_fsm <= ap_ST_fsm_pp0_stage47; end if; when ap_ST_fsm_pp0_stage48 => if ((ap_block_pp0_stage48_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage49; else ap_NS_fsm <= ap_ST_fsm_pp0_stage48; end if; when ap_ST_fsm_pp0_stage49 => if ((ap_block_pp0_stage49_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage50; else ap_NS_fsm <= ap_ST_fsm_pp0_stage49; end if; when ap_ST_fsm_pp0_stage50 => if ((ap_block_pp0_stage50_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage51; else ap_NS_fsm <= ap_ST_fsm_pp0_stage50; end if; when ap_ST_fsm_pp0_stage51 => if ((ap_block_pp0_stage51_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage52; else ap_NS_fsm <= ap_ST_fsm_pp0_stage51; end if; when ap_ST_fsm_pp0_stage52 => if ((ap_block_pp0_stage52_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage53; else ap_NS_fsm <= ap_ST_fsm_pp0_stage52; end if; when ap_ST_fsm_pp0_stage53 => if ((ap_block_pp0_stage53_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage54; else ap_NS_fsm <= ap_ST_fsm_pp0_stage53; end if; when ap_ST_fsm_pp0_stage54 => if ((ap_block_pp0_stage54_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage55; else ap_NS_fsm <= ap_ST_fsm_pp0_stage54; end if; when ap_ST_fsm_pp0_stage55 => if ((ap_block_pp0_stage55_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage56; else ap_NS_fsm <= ap_ST_fsm_pp0_stage55; end if; when ap_ST_fsm_pp0_stage56 => if ((ap_block_pp0_stage56_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage57; else ap_NS_fsm <= ap_ST_fsm_pp0_stage56; end if; when ap_ST_fsm_pp0_stage57 => if ((ap_block_pp0_stage57_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage58; else ap_NS_fsm <= ap_ST_fsm_pp0_stage57; end if; when ap_ST_fsm_pp0_stage58 => if ((ap_block_pp0_stage58_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage59; else ap_NS_fsm <= ap_ST_fsm_pp0_stage58; end if; when ap_ST_fsm_pp0_stage59 => if ((ap_block_pp0_stage59_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage60; else ap_NS_fsm <= ap_ST_fsm_pp0_stage59; end if; when ap_ST_fsm_pp0_stage60 => if ((ap_block_pp0_stage60_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage61; else ap_NS_fsm <= ap_ST_fsm_pp0_stage60; end if; when ap_ST_fsm_pp0_stage61 => if ((ap_block_pp0_stage61_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage62; else ap_NS_fsm <= ap_ST_fsm_pp0_stage61; end if; when ap_ST_fsm_pp0_stage62 => if ((ap_block_pp0_stage62_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage63; else ap_NS_fsm <= ap_ST_fsm_pp0_stage62; end if; when ap_ST_fsm_pp0_stage63 => if ((ap_block_pp0_stage63_flag00011011 = ap_const_boolean_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage0; else ap_NS_fsm <= ap_ST_fsm_pp0_stage63; end if; when ap_ST_fsm_state83 => ap_NS_fsm <= ap_ST_fsm_state86; when ap_ST_fsm_state84 => ap_NS_fsm <= ap_ST_fsm_state85; when ap_ST_fsm_state85 => ap_NS_fsm <= ap_ST_fsm_state86; when ap_ST_fsm_state86 => if (((ap_const_logic_1 = ap_CS_fsm_state86) and not(((ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then ap_NS_fsm <= ap_ST_fsm_state1; else ap_NS_fsm <= ap_ST_fsm_state86; end if; when others => ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end case; end process; ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2); ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(3); ap_CS_fsm_pp0_stage10 <= ap_CS_fsm(12); ap_CS_fsm_pp0_stage11 <= ap_CS_fsm(13); ap_CS_fsm_pp0_stage12 <= ap_CS_fsm(14); ap_CS_fsm_pp0_stage13 <= ap_CS_fsm(15); ap_CS_fsm_pp0_stage14 <= ap_CS_fsm(16); ap_CS_fsm_pp0_stage15 <= ap_CS_fsm(17); ap_CS_fsm_pp0_stage16 <= ap_CS_fsm(18); ap_CS_fsm_pp0_stage17 <= ap_CS_fsm(19); ap_CS_fsm_pp0_stage18 <= ap_CS_fsm(20); ap_CS_fsm_pp0_stage19 <= ap_CS_fsm(21); ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(4); ap_CS_fsm_pp0_stage20 <= ap_CS_fsm(22); ap_CS_fsm_pp0_stage21 <= ap_CS_fsm(23); ap_CS_fsm_pp0_stage22 <= ap_CS_fsm(24); ap_CS_fsm_pp0_stage23 <= ap_CS_fsm(25); ap_CS_fsm_pp0_stage24 <= ap_CS_fsm(26); ap_CS_fsm_pp0_stage25 <= ap_CS_fsm(27); ap_CS_fsm_pp0_stage26 <= ap_CS_fsm(28); ap_CS_fsm_pp0_stage27 <= ap_CS_fsm(29); ap_CS_fsm_pp0_stage28 <= ap_CS_fsm(30); ap_CS_fsm_pp0_stage29 <= ap_CS_fsm(31); ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(5); ap_CS_fsm_pp0_stage30 <= ap_CS_fsm(32); ap_CS_fsm_pp0_stage31 <= ap_CS_fsm(33); ap_CS_fsm_pp0_stage32 <= ap_CS_fsm(34); ap_CS_fsm_pp0_stage33 <= ap_CS_fsm(35); ap_CS_fsm_pp0_stage34 <= ap_CS_fsm(36); ap_CS_fsm_pp0_stage35 <= ap_CS_fsm(37); ap_CS_fsm_pp0_stage36 <= ap_CS_fsm(38); ap_CS_fsm_pp0_stage37 <= ap_CS_fsm(39); ap_CS_fsm_pp0_stage38 <= ap_CS_fsm(40); ap_CS_fsm_pp0_stage39 <= ap_CS_fsm(41); ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(6); ap_CS_fsm_pp0_stage40 <= ap_CS_fsm(42); ap_CS_fsm_pp0_stage41 <= ap_CS_fsm(43); ap_CS_fsm_pp0_stage42 <= ap_CS_fsm(44); ap_CS_fsm_pp0_stage43 <= ap_CS_fsm(45); ap_CS_fsm_pp0_stage44 <= ap_CS_fsm(46); ap_CS_fsm_pp0_stage45 <= ap_CS_fsm(47); ap_CS_fsm_pp0_stage46 <= ap_CS_fsm(48); ap_CS_fsm_pp0_stage47 <= ap_CS_fsm(49); ap_CS_fsm_pp0_stage48 <= ap_CS_fsm(50); ap_CS_fsm_pp0_stage49 <= ap_CS_fsm(51); ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(7); ap_CS_fsm_pp0_stage50 <= ap_CS_fsm(52); ap_CS_fsm_pp0_stage51 <= ap_CS_fsm(53); ap_CS_fsm_pp0_stage52 <= ap_CS_fsm(54); ap_CS_fsm_pp0_stage53 <= ap_CS_fsm(55); ap_CS_fsm_pp0_stage54 <= ap_CS_fsm(56); ap_CS_fsm_pp0_stage55 <= ap_CS_fsm(57); ap_CS_fsm_pp0_stage56 <= ap_CS_fsm(58); ap_CS_fsm_pp0_stage57 <= ap_CS_fsm(59); ap_CS_fsm_pp0_stage58 <= ap_CS_fsm(60); ap_CS_fsm_pp0_stage59 <= ap_CS_fsm(61); ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(8); ap_CS_fsm_pp0_stage60 <= ap_CS_fsm(62); ap_CS_fsm_pp0_stage61 <= ap_CS_fsm(63); ap_CS_fsm_pp0_stage62 <= ap_CS_fsm(64); ap_CS_fsm_pp0_stage63 <= ap_CS_fsm(65); ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(9); ap_CS_fsm_pp0_stage8 <= ap_CS_fsm(10); ap_CS_fsm_pp0_stage9 <= ap_CS_fsm(11); ap_CS_fsm_state1 <= ap_CS_fsm(0); ap_CS_fsm_state2 <= ap_CS_fsm(1); ap_CS_fsm_state84 <= ap_CS_fsm(67); ap_CS_fsm_state85 <= ap_CS_fsm(68); ap_CS_fsm_state86 <= ap_CS_fsm(69); ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage10_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage10_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage10_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter1, ap_block_state77_io) begin ap_block_pp0_stage10_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_block_state77_io)); end process; ap_block_pp0_stage10_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter1, ap_block_state77_io) begin ap_block_pp0_stage10_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_block_state77_io)); end process; ap_block_pp0_stage11_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage11_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage11_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage12_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage12_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage12_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage13_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage13_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage13_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage14_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage14_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage14_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage15_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage15_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter1, results_out_BVALID, ap_predicate_op241_writeresp_state82) begin ap_block_pp0_stage15_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = results_out_BVALID) and (ap_const_boolean_1 = ap_predicate_op241_writeresp_state82)); end process; ap_block_pp0_stage15_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter1, results_out_BVALID, ap_predicate_op241_writeresp_state82) begin ap_block_pp0_stage15_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = results_out_BVALID) and (ap_const_boolean_1 = ap_predicate_op241_writeresp_state82)); end process; ap_block_pp0_stage16_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage16_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage16_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage17_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage17_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage17_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage18_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage18_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage18_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage19_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage19_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage19_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage1_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage1_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage1_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state4_io) begin ap_block_pp0_stage1_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state4_io)); end process; ap_block_pp0_stage1_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, ap_block_state4_io) begin ap_block_pp0_stage1_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_block_state4_io)); end process; ap_block_pp0_stage20_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage20_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage20_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage21_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage21_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage21_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage22_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage22_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage22_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage23_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage23_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage23_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage24_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage24_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage24_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage25_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage25_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage25_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage26_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage26_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage26_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage27_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage27_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage27_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage28_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage28_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage28_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage29_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage29_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage29_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage2_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage2_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage2_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage30_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage30_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage30_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage31_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage31_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage31_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage32_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage32_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage32_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage33_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage33_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage33_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage34_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage34_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage34_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage35_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage35_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage35_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage36_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage36_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage36_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage37_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage37_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage37_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage38_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage38_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage38_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage39_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage39_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage39_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage3_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage3_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage3_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage40_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage40_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage40_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage41_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage41_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage41_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage42_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage42_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage42_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage43_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage43_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage43_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage44_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage44_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage44_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage45_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage45_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage45_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage46_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage46_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage46_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage47_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage47_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage47_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage48_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage48_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage48_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage49_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage49_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage49_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage4_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage4_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage4_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage50_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage50_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage50_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage51_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage51_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage51_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage52_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage52_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage52_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage53_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage53_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage53_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage54_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage54_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage54_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage55_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage55_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage55_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage56_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage56_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage56_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage57_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage57_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage57_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage58_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage58_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage58_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage59_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage59_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage59_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage5_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage5_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage60_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage60_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage60_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage61_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage61_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage61_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage62_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage62_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage62_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage63_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage63_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage63_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage6_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage6_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage6_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage7_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage7_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage7_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage8_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage8_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter0, db_mem_V_RVALID, ap_predicate_op168_read_state11) begin ap_block_pp0_stage8_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = db_mem_V_RVALID) and (ap_const_boolean_1 = ap_predicate_op168_read_state11)); end process; ap_block_pp0_stage8_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter0, db_mem_V_RVALID, ap_predicate_op168_read_state11) begin ap_block_pp0_stage8_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = db_mem_V_RVALID) and (ap_const_boolean_1 = ap_predicate_op168_read_state11)); end process; ap_block_pp0_stage9_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage9_flag00001001 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage9_flag00011001_assign_proc : process(ap_enable_reg_pp0_iter1, ap_block_state76_io) begin ap_block_pp0_stage9_flag00011001 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_block_state76_io)); end process; ap_block_pp0_stage9_flag00011011_assign_proc : process(ap_enable_reg_pp0_iter1, ap_block_state76_io) begin ap_block_pp0_stage9_flag00011011 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_block_state76_io)); end process; ap_block_state1_assign_proc : process(ap_start, operation_ap_vld_in_sig) begin ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig)); end process; ap_block_state10_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state10_pp0_stage7_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state11_pp0_stage8_iter0_assign_proc : process(db_mem_V_RVALID, ap_predicate_op168_read_state11) begin ap_block_state11_pp0_stage8_iter0 <= ((ap_const_logic_0 = db_mem_V_RVALID) and (ap_const_boolean_1 = ap_predicate_op168_read_state11)); end process; ap_block_state12_pp0_stage9_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state13_pp0_stage10_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state13_pp0_stage10_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state14_pp0_stage11_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state14_pp0_stage11_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state15_pp0_stage12_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state15_pp0_stage12_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state16_pp0_stage13_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state16_pp0_stage13_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state17_pp0_stage14_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state17_pp0_stage14_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state18_pp0_stage15_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state18_pp0_stage15_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state19_pp0_stage16_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state19_pp0_stage16_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state20_pp0_stage17_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state20_pp0_stage17_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state21_pp0_stage18_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state21_pp0_stage18_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state22_pp0_stage19_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state22_pp0_stage19_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state23_pp0_stage20_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state23_pp0_stage20_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state24_pp0_stage21_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state24_pp0_stage21_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state25_pp0_stage22_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state25_pp0_stage22_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state26_pp0_stage23_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state26_pp0_stage23_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state27_pp0_stage24_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state27_pp0_stage24_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state28_pp0_stage25_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state28_pp0_stage25_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state29_pp0_stage26_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state29_pp0_stage26_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state30_pp0_stage27_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state30_pp0_stage27_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state31_pp0_stage28_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state31_pp0_stage28_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state32_pp0_stage29_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state32_pp0_stage29_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state33_pp0_stage30_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state33_pp0_stage30_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state34_pp0_stage31_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state34_pp0_stage31_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state35_pp0_stage32_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state35_pp0_stage32_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state36_pp0_stage33_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state36_pp0_stage33_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state37_pp0_stage34_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state37_pp0_stage34_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state38_pp0_stage35_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state38_pp0_stage35_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state39_pp0_stage36_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state39_pp0_stage36_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state40_pp0_stage37_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state40_pp0_stage37_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state41_pp0_stage38_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state41_pp0_stage38_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state42_pp0_stage39_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state42_pp0_stage39_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state43_pp0_stage40_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state43_pp0_stage40_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state44_pp0_stage41_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state44_pp0_stage41_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state45_pp0_stage42_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state45_pp0_stage42_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state46_pp0_stage43_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state46_pp0_stage43_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state47_pp0_stage44_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state47_pp0_stage44_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state48_pp0_stage45_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state48_pp0_stage45_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state49_pp0_stage46_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state49_pp0_stage46_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state4_io_assign_proc : process(ap_sig_ioackin_db_mem_V_ARREADY, ap_predicate_op161_readreq_state4) begin ap_block_state4_io <= ((ap_const_logic_0 = ap_sig_ioackin_db_mem_V_ARREADY) and (ap_const_boolean_1 = ap_predicate_op161_readreq_state4)); end process; ap_block_state4_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state50_pp0_stage47_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state50_pp0_stage47_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state51_pp0_stage48_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state51_pp0_stage48_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state52_pp0_stage49_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state52_pp0_stage49_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state53_pp0_stage50_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state53_pp0_stage50_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state54_pp0_stage51_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state54_pp0_stage51_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state55_pp0_stage52_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state55_pp0_stage52_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state56_pp0_stage53_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state56_pp0_stage53_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state57_pp0_stage54_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state57_pp0_stage54_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state58_pp0_stage55_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state58_pp0_stage55_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state59_pp0_stage56_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state59_pp0_stage56_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state5_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state5_pp0_stage2_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state60_pp0_stage57_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state60_pp0_stage57_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state61_pp0_stage58_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state61_pp0_stage58_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state62_pp0_stage59_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state62_pp0_stage59_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state63_pp0_stage60_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state63_pp0_stage60_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state64_pp0_stage61_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state64_pp0_stage61_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state65_pp0_stage62_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state65_pp0_stage62_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state66_pp0_stage63_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state66_pp0_stage63_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state67_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state68_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state69_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state69_pp0_stage2_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state6_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state6_pp0_stage3_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state70_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state70_pp0_stage3_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state71_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state71_pp0_stage4_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state72_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state72_pp0_stage5_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state73_pp0_stage6_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state73_pp0_stage6_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state74_pp0_stage7_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state74_pp0_stage7_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state75_pp0_stage8_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state76_io_assign_proc : process(ap_sig_ioackin_results_out_AWREADY, ap_predicate_op234_writereq_state76) begin ap_block_state76_io <= ((ap_const_logic_0 = ap_sig_ioackin_results_out_AWREADY) and (ap_const_boolean_1 = ap_predicate_op234_writereq_state76)); end process; ap_block_state76_pp0_stage9_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state77_io_assign_proc : process(ap_sig_ioackin_results_out_WREADY, ap_predicate_op236_write_state77) begin ap_block_state77_io <= ((ap_const_logic_0 = ap_sig_ioackin_results_out_WREADY) and (ap_const_boolean_1 = ap_predicate_op236_write_state77)); end process; ap_block_state77_pp0_stage10_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state77_pp0_stage10_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state78_pp0_stage11_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state78_pp0_stage11_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state79_pp0_stage12_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state79_pp0_stage12_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state7_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state7_pp0_stage4_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state80_pp0_stage13_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state80_pp0_stage13_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state81_pp0_stage14_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state81_pp0_stage14_iter1_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state82_pp0_stage15_iter1_assign_proc : process(results_out_BVALID, ap_predicate_op241_writeresp_state82) begin ap_block_state82_pp0_stage15_iter1 <= ((ap_const_logic_0 = results_out_BVALID) and (ap_const_boolean_1 = ap_predicate_op241_writeresp_state82)); end process; ap_block_state82_pp0_stage15_iter1_ignore_call5_assign_proc : process(results_out_BVALID, ap_predicate_op241_writeresp_state82) begin ap_block_state82_pp0_stage15_iter1_ignore_call5 <= ((ap_const_logic_0 = results_out_BVALID) and (ap_const_boolean_1 = ap_predicate_op241_writeresp_state82)); end process; ap_block_state86_assign_proc : process(error_out_1_ack_in, contacts_size_out_1_ack_in) begin ap_block_state86 <= ((ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in)); end process; ap_block_state8_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state8_pp0_stage5_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state9_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state9_pp0_stage6_iter0_ignore_call5 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_condition_2628_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_predicate_op161_readreq_state4) begin ap_condition_2628 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op161_readreq_state4)); end process; ap_condition_2632_assign_proc : process(ap_CS_fsm_pp0_stage9, ap_enable_reg_pp0_iter1, ap_predicate_op234_writereq_state76) begin ap_condition_2632 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op234_writereq_state76)); end process; ap_condition_2636_assign_proc : process(ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage10, ap_predicate_op236_write_state77) begin ap_condition_2636 <= ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_boolean_1 = ap_predicate_op236_write_state77)); end process; ap_condition_pp0_exit_iter0_state3_assign_proc : process(ap_predicate_tran3to83_state3) begin if ((ap_const_boolean_1 = ap_predicate_tran3to83_state3)) then ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1; else ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0; end if; end process; ap_done_assign_proc : process(error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state86) begin if (((ap_const_logic_1 = ap_CS_fsm_state86) and not(((ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1); ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1) begin if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then ap_idle_pp0 <= ap_const_logic_1; else ap_idle_pp0 <= ap_const_logic_0; end if; end process; ap_predicate_op161_readreq_state4_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op161_readreq_state4 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op168_read_state11_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op168_read_state11 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op169_call_state12_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op169_call_state12 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op169_call_state12_state11_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op169_call_state12_state11 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op170_call_state13_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op170_call_state13 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op171_call_state14_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op171_call_state14 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op172_call_state15_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op172_call_state15 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op173_call_state16_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op173_call_state16 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op174_call_state17_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op174_call_state17 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op175_call_state18_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op175_call_state18 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op176_call_state19_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op176_call_state19 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op177_call_state20_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op177_call_state20 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op178_call_state21_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op178_call_state21 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op179_call_state22_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op179_call_state22 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op180_call_state23_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op180_call_state23 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op181_call_state24_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op181_call_state24 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op182_call_state25_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op182_call_state25 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op183_call_state26_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op183_call_state26 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op184_call_state27_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op184_call_state27 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op185_call_state28_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op185_call_state28 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op186_call_state29_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op186_call_state29 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op187_call_state30_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op187_call_state30 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op188_call_state31_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op188_call_state31 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op189_call_state32_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op189_call_state32 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op190_call_state33_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op190_call_state33 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op191_call_state34_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op191_call_state34 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op192_call_state35_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op192_call_state35 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op193_call_state36_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op193_call_state36 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op194_call_state37_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op194_call_state37 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op195_call_state38_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op195_call_state38 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op196_call_state39_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op196_call_state39 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op197_call_state40_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op197_call_state40 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op198_call_state41_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op198_call_state41 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op199_call_state42_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op199_call_state42 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op200_call_state43_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op200_call_state43 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op201_call_state44_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op201_call_state44 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op202_call_state45_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op202_call_state45 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op203_call_state46_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op203_call_state46 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op204_call_state47_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op204_call_state47 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op205_call_state48_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op205_call_state48 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op206_call_state49_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op206_call_state49 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op207_call_state50_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op207_call_state50 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op208_call_state51_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op208_call_state51 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op209_call_state52_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op209_call_state52 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op210_call_state53_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op210_call_state53 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op211_call_state54_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op211_call_state54 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op212_call_state55_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op212_call_state55 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op213_call_state56_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op213_call_state56 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op214_call_state57_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op214_call_state57 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op215_call_state58_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op215_call_state58 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op216_call_state59_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op216_call_state59 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op217_call_state60_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op217_call_state60 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op218_call_state61_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op218_call_state61 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op219_call_state62_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op219_call_state62 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op220_call_state63_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op220_call_state63 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op221_call_state64_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op221_call_state64 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op222_call_state65_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op222_call_state65 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op223_call_state66_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op223_call_state66 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op224_call_state67_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365) begin ap_predicate_op224_call_state67 <= ((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1)); end process; ap_predicate_op225_call_state68_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op225_call_state68 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op226_call_state69_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op226_call_state69 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op227_call_state70_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op227_call_state70 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op228_call_state71_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op228_call_state71 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op229_call_state72_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op229_call_state72 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op230_call_state73_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op230_call_state73 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op231_call_state74_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op231_call_state74 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op232_call_state75_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op232_call_state75 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op234_writereq_state76_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op234_writereq_state76 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op236_write_state77_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op236_write_state77 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_op241_writeresp_state82_assign_proc : process(ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin ap_predicate_op241_writeresp_state82 <= ((ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365)); end process; ap_predicate_tran3to83_state3_assign_proc : process(tmp_127_fu_264_p3, tmp_8_fu_290_p2) begin ap_predicate_tran3to83_state3 <= ((ap_const_lv1_1 = tmp_127_fu_264_p3) or ((ap_const_lv1_0 = tmp_127_fu_264_p3) and (ap_const_lv1_0 = tmp_8_fu_290_p2))); end process; ap_ready_assign_proc : process(error_out_1_ack_in, contacts_size_out_1_ack_in, ap_CS_fsm_state86) begin if (((ap_const_logic_1 = ap_CS_fsm_state86) and not(((ap_const_logic_0 = error_out_1_ack_in) or (ap_const_logic_0 = contacts_size_out_1_ack_in))))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_rst_n_inv_assign_proc : process(ap_rst_n) begin ap_rst_n_inv <= not(ap_rst_n); end process; ap_sig_ioackin_db_mem_V_ARREADY_assign_proc : process(db_mem_V_ARREADY, ap_reg_ioackin_db_mem_V_ARREADY) begin if ((ap_const_logic_0 = ap_reg_ioackin_db_mem_V_ARREADY)) then ap_sig_ioackin_db_mem_V_ARREADY <= db_mem_V_ARREADY; else ap_sig_ioackin_db_mem_V_ARREADY <= ap_const_logic_1; end if; end process; ap_sig_ioackin_results_out_AWREADY_assign_proc : process(results_out_AWREADY, ap_reg_ioackin_results_out_AWREADY) begin if ((ap_const_logic_0 = ap_reg_ioackin_results_out_AWREADY)) then ap_sig_ioackin_results_out_AWREADY <= results_out_AWREADY; else ap_sig_ioackin_results_out_AWREADY <= ap_const_logic_1; end if; end process; ap_sig_ioackin_results_out_WREADY_assign_proc : process(results_out_WREADY, ap_reg_ioackin_results_out_WREADY) begin if ((ap_const_logic_0 = ap_reg_ioackin_results_out_WREADY)) then ap_sig_ioackin_results_out_WREADY <= results_out_WREADY; else ap_sig_ioackin_results_out_WREADY <= ap_const_logic_1; end if; end process; contacts_V_address0_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_block_pp0_stage1_flag00000000, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00000000, ap_CS_fsm_pp0_stage9, ap_enable_reg_pp0_iter1, ap_block_pp0_stage9_flag00000000, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00000000, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00000000, ap_CS_fsm_state2, ap_CS_fsm_pp0_stage0, ap_predicate_op234_writereq_state76, ap_CS_fsm_pp0_stage63, grp_match_db_contact_fu_212_contacts_V_address0, ap_predicate_op169_call_state12, ap_predicate_op170_call_state13, ap_predicate_op171_call_state14, ap_predicate_op172_call_state15, ap_predicate_op173_call_state16, ap_predicate_op174_call_state17, ap_predicate_op175_call_state18, ap_predicate_op176_call_state19, ap_predicate_op177_call_state20, ap_predicate_op178_call_state21, ap_predicate_op179_call_state22, ap_predicate_op180_call_state23, ap_predicate_op181_call_state24, ap_predicate_op182_call_state25, ap_predicate_op183_call_state26, ap_predicate_op184_call_state27, ap_predicate_op185_call_state28, ap_predicate_op186_call_state29, ap_predicate_op187_call_state30, ap_predicate_op188_call_state31, ap_predicate_op189_call_state32, ap_predicate_op190_call_state33, ap_predicate_op191_call_state34, ap_predicate_op192_call_state35, ap_predicate_op193_call_state36, ap_predicate_op194_call_state37, ap_predicate_op195_call_state38, ap_predicate_op196_call_state39, ap_predicate_op197_call_state40, ap_predicate_op198_call_state41, ap_predicate_op199_call_state42, ap_predicate_op200_call_state43, ap_predicate_op201_call_state44, ap_predicate_op202_call_state45, ap_predicate_op203_call_state46, ap_predicate_op204_call_state47, ap_predicate_op205_call_state48, ap_predicate_op206_call_state49, ap_predicate_op207_call_state50, ap_predicate_op208_call_state51, ap_predicate_op209_call_state52, ap_predicate_op210_call_state53, ap_predicate_op211_call_state54, ap_predicate_op212_call_state55, ap_predicate_op213_call_state56, ap_predicate_op214_call_state57, ap_predicate_op215_call_state58, ap_predicate_op216_call_state59, ap_predicate_op217_call_state60, ap_predicate_op218_call_state61, ap_predicate_op219_call_state62, ap_predicate_op220_call_state63, ap_predicate_op221_call_state64, ap_predicate_op222_call_state65, ap_predicate_op223_call_state66, ap_predicate_op224_call_state67, ap_predicate_op225_call_state68, ap_predicate_op226_call_state69, ap_predicate_op227_call_state70, ap_predicate_op228_call_state71, ap_predicate_op229_call_state72, ap_predicate_op230_call_state73, ap_predicate_op231_call_state74, ap_predicate_op232_call_state75, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, tmp_4_fu_249_p1) begin if ((ap_const_logic_1 = ap_CS_fsm_state2)) then contacts_V_address0 <= tmp_4_fu_249_p1(7 - 1 downto 0); elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op169_call_state12)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op170_call_state13)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op171_call_state14) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op172_call_state15) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op173_call_state16) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op174_call_state17) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op175_call_state18)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op176_call_state19) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op177_call_state20) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op178_call_state21) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op179_call_state22) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op180_call_state23) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op181_call_state24) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op182_call_state25) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op183_call_state26) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op184_call_state27) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op185_call_state28) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op186_call_state29) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op187_call_state30) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op188_call_state31) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op189_call_state32) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op190_call_state33) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op191_call_state34) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op192_call_state35) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op193_call_state36) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op194_call_state37) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op195_call_state38) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op196_call_state39) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op197_call_state40) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op198_call_state41) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op199_call_state42) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op200_call_state43) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op201_call_state44) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op202_call_state45) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op203_call_state46) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op204_call_state47) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op205_call_state48) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op206_call_state49) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op207_call_state50) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op208_call_state51) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op209_call_state52) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op210_call_state53) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op211_call_state54) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op212_call_state55) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op213_call_state56) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op214_call_state57) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op215_call_state58) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op216_call_state59) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op217_call_state60) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op218_call_state61) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op219_call_state62) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op220_call_state63) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op221_call_state64) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op222_call_state65) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_const_boolean_1 = ap_predicate_op223_call_state66) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_boolean_1 = ap_predicate_op224_call_state67) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op225_call_state68)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op226_call_state69) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op227_call_state70) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op228_call_state71) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op229_call_state72) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op230_call_state73) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op231_call_state74) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op232_call_state75)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op234_writereq_state76)))) then contacts_V_address0 <= grp_match_db_contact_fu_212_contacts_V_address0; else contacts_V_address0 <= "XXXXXXX"; end if; end process; contacts_V_ce0_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage15, ap_CS_fsm_state2, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_block_pp0_stage1_flag00011001, ap_block_pp0_stage8_flag00011001, ap_predicate_op234_writereq_state76, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage63, grp_match_db_contact_fu_212_contacts_V_ce0, ap_predicate_op169_call_state12, ap_predicate_op170_call_state13, ap_predicate_op171_call_state14, ap_predicate_op172_call_state15, ap_predicate_op173_call_state16, ap_predicate_op174_call_state17, ap_predicate_op175_call_state18, ap_predicate_op176_call_state19, ap_predicate_op177_call_state20, ap_predicate_op178_call_state21, ap_predicate_op179_call_state22, ap_predicate_op180_call_state23, ap_predicate_op181_call_state24, ap_predicate_op182_call_state25, ap_predicate_op183_call_state26, ap_predicate_op184_call_state27, ap_predicate_op185_call_state28, ap_predicate_op186_call_state29, ap_predicate_op187_call_state30, ap_predicate_op188_call_state31, ap_predicate_op189_call_state32, ap_predicate_op190_call_state33, ap_predicate_op191_call_state34, ap_predicate_op192_call_state35, ap_predicate_op193_call_state36, ap_predicate_op194_call_state37, ap_predicate_op195_call_state38, ap_predicate_op196_call_state39, ap_predicate_op197_call_state40, ap_predicate_op198_call_state41, ap_predicate_op199_call_state42, ap_predicate_op200_call_state43, ap_predicate_op201_call_state44, ap_predicate_op202_call_state45, ap_predicate_op203_call_state46, ap_predicate_op204_call_state47, ap_predicate_op205_call_state48, ap_predicate_op206_call_state49, ap_predicate_op207_call_state50, ap_predicate_op208_call_state51, ap_predicate_op209_call_state52, ap_predicate_op210_call_state53, ap_predicate_op211_call_state54, ap_predicate_op212_call_state55, ap_predicate_op213_call_state56, ap_predicate_op214_call_state57, ap_predicate_op215_call_state58, ap_predicate_op216_call_state59, ap_predicate_op217_call_state60, ap_predicate_op218_call_state61, ap_predicate_op219_call_state62, ap_predicate_op220_call_state63, ap_predicate_op221_call_state64, ap_predicate_op222_call_state65, ap_predicate_op223_call_state66, ap_predicate_op224_call_state67, ap_predicate_op225_call_state68, ap_predicate_op226_call_state69, ap_predicate_op227_call_state70, ap_predicate_op228_call_state71, ap_predicate_op229_call_state72, ap_predicate_op230_call_state73, ap_predicate_op231_call_state74, ap_predicate_op232_call_state75, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage15_flag00011001, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage30_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage31_flag00011001, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage32_flag00011001, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage33_flag00011001, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage34_flag00011001, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage35_flag00011001, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage36_flag00011001, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage37_flag00011001, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage38_flag00011001, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage39_flag00011001, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage40_flag00011001, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage41_flag00011001, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage42_flag00011001, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage43_flag00011001, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage44_flag00011001, ap_CS_fsm_pp0_stage44, ap_block_pp0_stage45_flag00011001, ap_CS_fsm_pp0_stage45, ap_block_pp0_stage46_flag00011001, ap_CS_fsm_pp0_stage46, ap_block_pp0_stage47_flag00011001, ap_CS_fsm_pp0_stage47, ap_block_pp0_stage48_flag00011001, ap_CS_fsm_pp0_stage48, ap_block_pp0_stage49_flag00011001, ap_CS_fsm_pp0_stage49, ap_block_pp0_stage50_flag00011001, ap_CS_fsm_pp0_stage50, ap_block_pp0_stage51_flag00011001, ap_CS_fsm_pp0_stage51, ap_block_pp0_stage52_flag00011001, ap_CS_fsm_pp0_stage52, ap_block_pp0_stage53_flag00011001, ap_CS_fsm_pp0_stage53, ap_block_pp0_stage54_flag00011001, ap_CS_fsm_pp0_stage54, ap_block_pp0_stage55_flag00011001, ap_CS_fsm_pp0_stage55, ap_block_pp0_stage56_flag00011001, ap_CS_fsm_pp0_stage56, ap_block_pp0_stage57_flag00011001, ap_CS_fsm_pp0_stage57, ap_block_pp0_stage58_flag00011001, ap_CS_fsm_pp0_stage58, ap_block_pp0_stage59_flag00011001, ap_CS_fsm_pp0_stage59, ap_block_pp0_stage60_flag00011001, ap_CS_fsm_pp0_stage60, ap_block_pp0_stage61_flag00011001, ap_CS_fsm_pp0_stage61, ap_block_pp0_stage62_flag00011001, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage63_flag00011001, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage7) begin if ((ap_const_logic_1 = ap_CS_fsm_state2)) then contacts_V_ce0 <= ap_const_logic_1; elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op169_call_state12)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_boolean_1 = ap_predicate_op170_call_state13) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op171_call_state14) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op172_call_state15) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op173_call_state16) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op174_call_state17) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_boolean_1 = ap_predicate_op175_call_state18) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op176_call_state19) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op177_call_state20) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op178_call_state21) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op179_call_state22) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op180_call_state23) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op181_call_state24) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op182_call_state25) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op183_call_state26) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op184_call_state27) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op185_call_state28) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op186_call_state29) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op187_call_state30) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op188_call_state31) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op189_call_state32) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op190_call_state33) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op191_call_state34) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op192_call_state35) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op193_call_state36) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op194_call_state37) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op195_call_state38) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op196_call_state39) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op197_call_state40) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op198_call_state41) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op199_call_state42) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op200_call_state43) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op201_call_state44) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op202_call_state45) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op203_call_state46) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op204_call_state47) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op205_call_state48) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op206_call_state49) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op207_call_state50) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op208_call_state51) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op209_call_state52) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op210_call_state53) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op211_call_state54) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op212_call_state55) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op213_call_state56) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op214_call_state57) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op215_call_state58) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op216_call_state59) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op217_call_state60) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op218_call_state61) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op219_call_state62) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op220_call_state63) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op221_call_state64) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op222_call_state65) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_const_boolean_1 = ap_predicate_op223_call_state66) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op224_call_state67)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op225_call_state68)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op226_call_state69) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op227_call_state70) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op228_call_state71) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op229_call_state72) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op230_call_state73) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op231_call_state74) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op232_call_state75)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op234_writereq_state76) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)))) then contacts_V_ce0 <= grp_match_db_contact_fu_212_contacts_V_ce0; else contacts_V_ce0 <= ap_const_logic_0; end if; end process; contacts_V_ce1_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_block_pp0_stage1_flag00011001, ap_block_pp0_stage8_flag00011001, ap_predicate_op234_writereq_state76, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage63, grp_match_db_contact_fu_212_contacts_V_ce1, ap_predicate_op169_call_state12, ap_predicate_op170_call_state13, ap_predicate_op171_call_state14, ap_predicate_op172_call_state15, ap_predicate_op173_call_state16, ap_predicate_op174_call_state17, ap_predicate_op175_call_state18, ap_predicate_op176_call_state19, ap_predicate_op177_call_state20, ap_predicate_op178_call_state21, ap_predicate_op179_call_state22, ap_predicate_op180_call_state23, ap_predicate_op181_call_state24, ap_predicate_op182_call_state25, ap_predicate_op183_call_state26, ap_predicate_op184_call_state27, ap_predicate_op185_call_state28, ap_predicate_op186_call_state29, ap_predicate_op187_call_state30, ap_predicate_op188_call_state31, ap_predicate_op189_call_state32, ap_predicate_op190_call_state33, ap_predicate_op191_call_state34, ap_predicate_op192_call_state35, ap_predicate_op193_call_state36, ap_predicate_op194_call_state37, ap_predicate_op195_call_state38, ap_predicate_op196_call_state39, ap_predicate_op197_call_state40, ap_predicate_op198_call_state41, ap_predicate_op199_call_state42, ap_predicate_op200_call_state43, ap_predicate_op201_call_state44, ap_predicate_op202_call_state45, ap_predicate_op203_call_state46, ap_predicate_op204_call_state47, ap_predicate_op205_call_state48, ap_predicate_op206_call_state49, ap_predicate_op207_call_state50, ap_predicate_op208_call_state51, ap_predicate_op209_call_state52, ap_predicate_op210_call_state53, ap_predicate_op211_call_state54, ap_predicate_op212_call_state55, ap_predicate_op213_call_state56, ap_predicate_op214_call_state57, ap_predicate_op215_call_state58, ap_predicate_op216_call_state59, ap_predicate_op217_call_state60, ap_predicate_op218_call_state61, ap_predicate_op219_call_state62, ap_predicate_op220_call_state63, ap_predicate_op221_call_state64, ap_predicate_op222_call_state65, ap_predicate_op223_call_state66, ap_predicate_op224_call_state67, ap_predicate_op225_call_state68, ap_predicate_op226_call_state69, ap_predicate_op227_call_state70, ap_predicate_op228_call_state71, ap_predicate_op229_call_state72, ap_predicate_op230_call_state73, ap_predicate_op231_call_state74, ap_predicate_op232_call_state75, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage15_flag00011001, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage30_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage31_flag00011001, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage32_flag00011001, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage33_flag00011001, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage34_flag00011001, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage35_flag00011001, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage36_flag00011001, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage37_flag00011001, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage38_flag00011001, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage39_flag00011001, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage40_flag00011001, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage41_flag00011001, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage42_flag00011001, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage43_flag00011001, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage44_flag00011001, ap_CS_fsm_pp0_stage44, ap_block_pp0_stage45_flag00011001, ap_CS_fsm_pp0_stage45, ap_block_pp0_stage46_flag00011001, ap_CS_fsm_pp0_stage46, ap_block_pp0_stage47_flag00011001, ap_CS_fsm_pp0_stage47, ap_block_pp0_stage48_flag00011001, ap_CS_fsm_pp0_stage48, ap_block_pp0_stage49_flag00011001, ap_CS_fsm_pp0_stage49, ap_block_pp0_stage50_flag00011001, ap_CS_fsm_pp0_stage50, ap_block_pp0_stage51_flag00011001, ap_CS_fsm_pp0_stage51, ap_block_pp0_stage52_flag00011001, ap_CS_fsm_pp0_stage52, ap_block_pp0_stage53_flag00011001, ap_CS_fsm_pp0_stage53, ap_block_pp0_stage54_flag00011001, ap_CS_fsm_pp0_stage54, ap_block_pp0_stage55_flag00011001, ap_CS_fsm_pp0_stage55, ap_block_pp0_stage56_flag00011001, ap_CS_fsm_pp0_stage56, ap_block_pp0_stage57_flag00011001, ap_CS_fsm_pp0_stage57, ap_block_pp0_stage58_flag00011001, ap_CS_fsm_pp0_stage58, ap_block_pp0_stage59_flag00011001, ap_CS_fsm_pp0_stage59, ap_block_pp0_stage60_flag00011001, ap_CS_fsm_pp0_stage60, ap_block_pp0_stage61_flag00011001, ap_CS_fsm_pp0_stage61, ap_block_pp0_stage62_flag00011001, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage63_flag00011001, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage7) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op169_call_state12)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_boolean_1 = ap_predicate_op170_call_state13) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op171_call_state14) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op172_call_state15) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op173_call_state16) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op174_call_state17) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_boolean_1 = ap_predicate_op175_call_state18) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op176_call_state19) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op177_call_state20) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op178_call_state21) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op179_call_state22) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op180_call_state23) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op181_call_state24) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op182_call_state25) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op183_call_state26) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op184_call_state27) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op185_call_state28) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op186_call_state29) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op187_call_state30) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op188_call_state31) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op189_call_state32) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op190_call_state33) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op191_call_state34) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op192_call_state35) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op193_call_state36) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op194_call_state37) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op195_call_state38) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op196_call_state39) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op197_call_state40) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op198_call_state41) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op199_call_state42) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op200_call_state43) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op201_call_state44) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op202_call_state45) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op203_call_state46) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op204_call_state47) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op205_call_state48) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op206_call_state49) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op207_call_state50) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op208_call_state51) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op209_call_state52) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op210_call_state53) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op211_call_state54) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op212_call_state55) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op213_call_state56) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op214_call_state57) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op215_call_state58) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op216_call_state59) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op217_call_state60) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op218_call_state61) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op219_call_state62) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op220_call_state63) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op221_call_state64) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op222_call_state65) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_const_boolean_1 = ap_predicate_op223_call_state66) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op224_call_state67)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op225_call_state68)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op226_call_state69) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op227_call_state70) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op228_call_state71) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op229_call_state72) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op230_call_state73) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op231_call_state74) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_boolean_1 = ap_predicate_op232_call_state75)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op234_writereq_state76) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)))) then contacts_V_ce1 <= grp_match_db_contact_fu_212_contacts_V_ce1; else contacts_V_ce1 <= ap_const_logic_0; end if; end process; contacts_V_we0_assign_proc : process(operation_read_read_fu_130_p2, ap_CS_fsm_state2, icmp_fu_243_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_130_p2) and (ap_const_lv1_0 = icmp_fu_243_p2))) then contacts_V_we0 <= ap_const_logic_1; else contacts_V_we0 <= ap_const_logic_0; end if; end process; contacts_size_out_1_ack_in_assign_proc : process(contacts_size_out_1_vld_reg) begin if (((ap_const_logic_0 = contacts_size_out_1_vld_reg) or ((ap_const_logic_1 = contacts_size_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then contacts_size_out_1_ack_in <= ap_const_logic_1; else contacts_size_out_1_ack_in <= ap_const_logic_0; end if; end process; contacts_size_out_1_data_in_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld_in_sig, contacts_size, operation_read_read_fu_130_p2, storemerge_reg_200, ap_CS_fsm_state85) begin if ((ap_const_logic_1 = ap_CS_fsm_state85)) then contacts_size_out_1_data_in <= storemerge_reg_200; elsif ((((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_1)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and not((ap_const_lv32_0 = operation_read_read_fu_130_p2)) and not((operation_read_read_fu_130_p2 = ap_const_lv32_1)) and not((operation_read_read_fu_130_p2 = ap_const_lv32_2))))) then contacts_size_out_1_data_in <= contacts_size; elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_2))) then contacts_size_out_1_data_in <= ap_const_lv32_0; else contacts_size_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; contacts_size_out_1_vld_in_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld_in_sig, operation_read_read_fu_130_p2, ap_CS_fsm_state85) begin if ((((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_1)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and not((ap_const_lv32_0 = operation_read_read_fu_130_p2)) and not((operation_read_read_fu_130_p2 = ap_const_lv32_1)) and not((operation_read_read_fu_130_p2 = ap_const_lv32_2))) or (ap_const_logic_1 = ap_CS_fsm_state85))) then contacts_size_out_1_vld_in <= ap_const_logic_1; else contacts_size_out_1_vld_in <= ap_const_logic_0; end if; end process; database_index_1_fu_272_p2 <= std_logic_vector(unsigned(database_index_phi_fu_193_p4) + unsigned(ap_const_lv24_1)); database_index_cast1_fu_278_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(database_index_phi_fu_193_p4),32)); database_index_phi_fu_193_p4_assign_proc : process(tmp_127_reg_356, tmp_8_reg_365, ap_enable_reg_pp0_iter1, database_index_reg_189, ap_CS_fsm_pp0_stage0, database_index_1_reg_360, ap_block_pp0_stage0_flag00000000) begin if (((tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then database_index_phi_fu_193_p4 <= database_index_1_reg_360; else database_index_phi_fu_193_p4 <= database_index_reg_189; end if; end process; db_mem_V_ARVALID_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_predicate_op161_readreq_state4, ap_reg_ioackin_db_mem_V_ARREADY, ap_block_pp0_stage1_flag00001001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_boolean_1 = ap_predicate_op161_readreq_state4) and (ap_block_pp0_stage1_flag00001001 = ap_const_boolean_0) and (ap_const_logic_0 = ap_reg_ioackin_db_mem_V_ARREADY))) then db_mem_V_ARVALID <= ap_const_logic_1; else db_mem_V_ARVALID <= ap_const_logic_0; end if; end process; db_mem_V_RREADY_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage8, ap_predicate_op168_read_state11, ap_block_pp0_stage8_flag00011001) begin if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_boolean_1 = ap_predicate_op168_read_state11) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then db_mem_V_RREADY <= ap_const_logic_1; else db_mem_V_RREADY <= ap_const_logic_0; end if; end process; db_mem_V_blk_n_AR_assign_proc : process(m_axi_db_mem_V_ARREADY, ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter0, ap_block_pp0_stage1_flag00000000, tmp_127_reg_356, tmp_8_reg_365) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1))) then db_mem_V_blk_n_AR <= m_axi_db_mem_V_ARREADY; else db_mem_V_blk_n_AR <= ap_const_logic_1; end if; end process; db_mem_V_blk_n_R_assign_proc : process(m_axi_db_mem_V_RVALID, ap_enable_reg_pp0_iter0, tmp_127_reg_356, tmp_8_reg_365, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00000000) begin if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (tmp_127_reg_356 = ap_const_lv1_0) and (tmp_8_reg_365 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then db_mem_V_blk_n_R <= m_axi_db_mem_V_RVALID; else db_mem_V_blk_n_R <= ap_const_logic_1; end if; end process; error_out_1_ack_in_assign_proc : process(error_out_1_vld_reg) begin if (((ap_const_logic_0 = error_out_1_vld_reg) or ((ap_const_logic_1 = error_out_1_vld_reg) and (ap_const_logic_1 = ap_const_logic_1)))) then error_out_1_ack_in <= ap_const_logic_1; else error_out_1_ack_in <= ap_const_logic_0; end if; end process; error_out_1_data_in_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld_in_sig, operation_read_read_fu_130_p2, ap_CS_fsm_state2, icmp_fu_243_p2) begin if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_130_p2) and (ap_const_lv1_1 = icmp_fu_243_p2))) then error_out_1_data_in <= ap_const_lv32_1; elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and not((ap_const_lv32_0 = operation_read_read_fu_130_p2)) and not((operation_read_read_fu_130_p2 = ap_const_lv32_1)) and not((operation_read_read_fu_130_p2 = ap_const_lv32_2)))) then error_out_1_data_in <= ap_const_lv32_3; elsif ((((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_1)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (ap_const_lv32_0 = operation_read_read_fu_130_p2)))) then error_out_1_data_in <= ap_const_lv32_0; else error_out_1_data_in <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; end if; end process; error_out_1_vld_in_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld_in_sig, operation_read_read_fu_130_p2, ap_CS_fsm_state2, icmp_fu_243_p2) begin if ((((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_1)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (operation_read_read_fu_130_p2 = ap_const_lv32_2)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and (ap_const_lv32_0 = operation_read_read_fu_130_p2)) or ((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = operation_ap_vld_in_sig))) and not((ap_const_lv32_0 = operation_read_read_fu_130_p2)) and not((operation_read_read_fu_130_p2 = ap_const_lv32_1)) and not((operation_read_read_fu_130_p2 = ap_const_lv32_2))) or ((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv32_0 = operation_read_read_fu_130_p2) and (ap_const_lv1_1 = icmp_fu_243_p2)))) then error_out_1_vld_in <= ap_const_logic_1; else error_out_1_vld_in <= ap_const_logic_0; end if; end process; grp_match_db_contact_fu_212_ap_ce_assign_proc : process(ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_block_pp0_stage1_flag00011001, ap_block_pp0_stage8_flag00011001, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage63, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage15_flag00011001, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage30_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage31_flag00011001, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage32_flag00011001, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage33_flag00011001, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage34_flag00011001, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage35_flag00011001, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage36_flag00011001, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage37_flag00011001, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage38_flag00011001, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage39_flag00011001, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage40_flag00011001, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage41_flag00011001, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage42_flag00011001, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage43_flag00011001, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage44_flag00011001, ap_CS_fsm_pp0_stage44, ap_block_pp0_stage45_flag00011001, ap_CS_fsm_pp0_stage45, ap_block_pp0_stage46_flag00011001, ap_CS_fsm_pp0_stage46, ap_block_pp0_stage47_flag00011001, ap_CS_fsm_pp0_stage47, ap_block_pp0_stage48_flag00011001, ap_CS_fsm_pp0_stage48, ap_block_pp0_stage49_flag00011001, ap_CS_fsm_pp0_stage49, ap_block_pp0_stage50_flag00011001, ap_CS_fsm_pp0_stage50, ap_block_pp0_stage51_flag00011001, ap_CS_fsm_pp0_stage51, ap_block_pp0_stage52_flag00011001, ap_CS_fsm_pp0_stage52, ap_block_pp0_stage53_flag00011001, ap_CS_fsm_pp0_stage53, ap_block_pp0_stage54_flag00011001, ap_CS_fsm_pp0_stage54, ap_block_pp0_stage55_flag00011001, ap_CS_fsm_pp0_stage55, ap_block_pp0_stage56_flag00011001, ap_CS_fsm_pp0_stage56, ap_block_pp0_stage57_flag00011001, ap_CS_fsm_pp0_stage57, ap_block_pp0_stage58_flag00011001, ap_CS_fsm_pp0_stage58, ap_block_pp0_stage59_flag00011001, ap_CS_fsm_pp0_stage59, ap_block_pp0_stage60_flag00011001, ap_CS_fsm_pp0_stage60, ap_block_pp0_stage61_flag00011001, ap_CS_fsm_pp0_stage61, ap_block_pp0_stage62_flag00011001, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage63_flag00011001, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage7) begin if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)))) then grp_match_db_contact_fu_212_ap_ce <= ap_const_logic_1; else grp_match_db_contact_fu_212_ap_ce <= ap_const_logic_0; end if; end process; grp_match_db_contact_fu_212_ap_start <= ap_reg_grp_match_db_contact_fu_212_ap_start; icmp_fu_243_p2 <= "1" when (signed(tmp_fu_234_p4) > signed(ap_const_lv25_0)) else "0"; operation_ap_vld_in_sig_assign_proc : process(operation_ap_vld, operation_ap_vld_preg) begin if ((ap_const_logic_1 = operation_ap_vld)) then operation_ap_vld_in_sig <= operation_ap_vld; else operation_ap_vld_in_sig <= operation_ap_vld_preg; end if; end process; operation_blk_n_assign_proc : process(ap_start, ap_CS_fsm_state1, operation_ap_vld) begin if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then operation_blk_n <= operation_ap_vld; else operation_blk_n <= ap_const_logic_1; end if; end process; operation_in_sig_assign_proc : process(operation, operation_preg, operation_ap_vld) begin if ((ap_const_logic_1 = operation_ap_vld)) then operation_in_sig <= operation; else operation_in_sig <= operation_preg; end if; end process; operation_read_read_fu_130_p2 <= operation_in_sig; results_out_AWVALID_assign_proc : process(ap_CS_fsm_pp0_stage9, ap_enable_reg_pp0_iter1, ap_predicate_op234_writereq_state76, ap_reg_ioackin_results_out_AWREADY, ap_block_pp0_stage9_flag00001001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_boolean_1 = ap_predicate_op234_writereq_state76) and (ap_block_pp0_stage9_flag00001001 = ap_const_boolean_0) and (ap_const_logic_0 = ap_reg_ioackin_results_out_AWREADY))) then results_out_AWVALID <= ap_const_logic_1; else results_out_AWVALID <= ap_const_logic_0; end if; end process; results_out_BREADY_assign_proc : process(ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage15, ap_predicate_op241_writeresp_state82, ap_block_pp0_stage15_flag00011001) begin if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_const_boolean_1 = ap_predicate_op241_writeresp_state82) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0))) then results_out_BREADY <= ap_const_logic_1; else results_out_BREADY <= ap_const_logic_0; end if; end process; results_out_WDATA <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_s_reg_390),8)); results_out_WVALID_assign_proc : process(ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage10, ap_predicate_op236_write_state77, ap_reg_ioackin_results_out_WREADY, ap_block_pp0_stage10_flag00001001) begin if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_boolean_1 = ap_predicate_op236_write_state77) and (ap_block_pp0_stage10_flag00001001 = ap_const_boolean_0) and (ap_const_logic_0 = ap_reg_ioackin_results_out_WREADY))) then results_out_WVALID <= ap_const_logic_1; else results_out_WVALID <= ap_const_logic_0; end if; end process; results_out_blk_n_AW_assign_proc : process(m_axi_results_out_AWREADY, ap_CS_fsm_pp0_stage9, ap_enable_reg_pp0_iter1, ap_block_pp0_stage9_flag00000000, ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0) and (ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365))) then results_out_blk_n_AW <= m_axi_results_out_AWREADY; else results_out_blk_n_AW <= ap_const_logic_1; end if; end process; results_out_blk_n_B_assign_proc : process(m_axi_results_out_BVALID, ap_enable_reg_pp0_iter1, ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00000000) begin if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then results_out_blk_n_B <= m_axi_results_out_BVALID; else results_out_blk_n_B <= ap_const_logic_1; end if; end process; results_out_blk_n_W_assign_proc : process(m_axi_results_out_WREADY, ap_enable_reg_pp0_iter1, ap_reg_pp0_iter1_tmp_127_reg_356, ap_reg_pp0_iter1_tmp_8_reg_365, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00000000) begin if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_lv1_0 = ap_reg_pp0_iter1_tmp_127_reg_356) and (ap_const_lv1_1 = ap_reg_pp0_iter1_tmp_8_reg_365) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then results_out_blk_n_W <= m_axi_results_out_WREADY; else results_out_blk_n_W <= ap_const_logic_1; end if; end process; sum_cast_fu_306_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(sum_reg_369),64)); sum_fu_295_p2 <= std_logic_vector(unsigned(tmp_7_cast_fu_286_p1) + unsigned(tmp_126_reg_343)); tmp_126_fu_230_p1 <= offset(25 - 1 downto 0); tmp_127_fu_264_p3 <= database_index_phi_fu_193_p4(23 downto 23); tmp_4_fu_249_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(contacts_size_load_reg_334),64)); tmp_5_fu_253_p2 <= std_logic_vector(unsigned(contacts_size_load_reg_334) + unsigned(ap_const_lv32_1)); tmp_7_cast_fu_286_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(database_index_phi_fu_193_p4),25)); tmp_7_fu_282_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(database_index_phi_fu_193_p4),64)); tmp_8_fu_290_p2 <= "1" when (unsigned(database_index_cast1_fu_278_p1) < unsigned(db_size_in)) else "0"; tmp_fu_234_p4 <= contacts_size_load_reg_334(31 downto 7); end behav; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.procedures.all; entity soc is port( rst : in std_logic; clk : in std_logic; clk2x : in std_logic; pc : out std_logic_vector(7 downto 0); rx : in std_logic; tx : out std_logic ); end soc; architecture Structural of soc is signal mem_enb : std_logic; signal mem_enb_1 : std_logic; signal mem_dob : t_data2; signal serial_ena : std_logic; signal serial_ena_1 : std_logic; signal serial_wea : std_logic; signal serial_doa : std_logic_vector(7 downto 0); signal serial_dib : std_logic_vector(7 downto 0); signal serial_busy : std_logic; signal ena : std_logic; signal addra : t_data2; signal doa : t_data2; signal enb : std_logic; signal addrb : t_data2; signal dob : t_data2; signal web : std_logic_vector(1 downto 0); signal dib : t_data2; signal bbusy : std_logic; begin pc <= addra(7 downto 0); mem_enb <= enb when addrb(15 downto 12) = "0000" else '0'; mem_i: entity work.progmem port map( clk => clk, addra => addra(11 downto 0), ena => ena, doa => doa, dib => dib, addrb => addrb(11 downto 0), enb => mem_enb, web => web, dob => mem_dob ); serial_ena <= enb when addrb(15 downto 0) = X"FFFF" else '0'; serial_dib <= dib(7 downto 0) when web(0) = '1' else dib(15 downto 8); serial_wea <= web(1) or web(0); bbusy <= serial_busy when serial_ena = '1' else '0'; serial_i: entity work.serial port map( rst => rst, clk => clk, rx => rx, tx => tx, ena => serial_ena, wea => serial_wea, dia => serial_dib, doa => serial_doa, busy => serial_busy ); process(clk) begin if rising_edge(clk) then mem_enb_1 <= mem_enb; serial_ena_1 <= serial_ena; end if; end process; dob <= mem_dob when mem_enb_1 = '1' else serial_doa & serial_doa when serial_ena_1 = '1' else (others => '0'); cpu_i: entity work.cpu port map( rst => rst, clk => clk, clk2x => clk2x, ena => ena, addra => addra, doa => doa, enb => enb, addrb => addrb, dob => dob, web => web, dib => dib, bbusy => bbusy ); end Structural; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.all; entity ALU_Toplevel is Port ( RA : in STD_LOGIC_VECTOR (15 downto 0); RB : in STD_LOGIC_VECTOR (15 downto 0); OP : in STD_LOGIC_VECTOR (3 downto 0); CLK : IN STD_LOGIC; ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0); SREG : out STD_LOGIC_VECTOR (3 downto 0); LDST_DAT : out STD_LOGIC_VECTOR (15 downto 0); LDST_ADR : out STD_LOGIC_VECTOR (15 downto 0)); end ALU_Toplevel; architecture Structural of ALU_Toplevel is signal ARITH : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); signal SREG_AR : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0'); signal LOGIC : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); signal SREG_LG : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0'); signal SHIFT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); signal SREG_SH : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0'); signal LD_MEM : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); signal WORD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); signal LDST_ADR_8 : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0'); signal BR : STD_LOGIC := '0'; signal CCR : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0'); begin LDST_ADR <= X"00" & LDST_ADR_8; arith_unit: entity work.arith_unit port map( RA => RA, RB => RB, OP => OP(2 downto 0), AR_OUT => ARITH, SREG_OUT => SREG_AR); logical_unit: entity work.logical_unit port map( RA => RA, RB => RB, OP => OP(2 downto 0), LOG_OUT => LOGIC, SREG_OUT => SREG_LG); shift_unit: entity work.shift_unit port map( RA => RA, SHIFT => RB(7 downto 0), OP => OP(3), SHIFT_OUT => SHIFT, SREG_OUT => SREG_SH); word_unit: entity work.word_unit port map( DATAIN => RA, IMMAddr => RB(7 downto 0), CLK => CLK, OP => OP, RESULT => WORD_OUT, DST_ADR => LDST_ADR_8, STORE_DATA => LDST_DAT); jump_unit: entity work.jump_unit port map( CLK => CLK, OP => OP, CCR => CCR, MASK => RA(3 downto 0), IMMD => RB, BRSIG => BR); with OP select ALU_OUT <= ARITH when "0000", -- ADD (ARITHMETIC) ARITH when "0001", -- SUB (ARITHMETIC) LOGIC when "0010", -- AND (LOGICAL) LOGIC when "0011", -- OR (LOGICAL) LOGIC when "0100", -- MOV (LOGICAL) ARITH when "0101", -- ADDI (ARITHMETIC) LOGIC when "0110", -- ANDI (LOGICAL) SHIFT when "0111", -- SL (SHIFT) SHIFT when "1000", -- SR (SHIFT) WORD_OUT when "1001", -- LW (WORD) RA when "1010", -- SW (WORD) X"0000" when OTHERS; with OP select CCR <= SREG_AR when "0000", -- ADD (ARITHMETIC) SREG_AR when "0001", -- SUB (ARITHMETIC) SREG_LG when "0010", -- AND (LOGICAL) SREG_LG when "0011", -- OR (LOGICAL) SREG_LG when "0100", -- MOV (LOGICAL) SREG_AR when "0101", -- ADDI (ARITHMETIC) SREG_LG when "0110", -- ANDI (LOGICAL) SREG_SH when "0111", -- SL (SHIFT) SREG_SH when "1000", -- SR (SHIFT) X"0" when OTHERS; SREG <= CCR; end Structural; |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY xfft_v9_0; USE xfft_v9_0.xfft_v9_0; ENTITY fft IS PORT ( aclk : IN STD_LOGIC; s_axis_config_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_config_tvalid : IN STD_LOGIC; s_axis_config_tready : OUT STD_LOGIC; s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_data_tvalid : IN STD_LOGIC; s_axis_data_tready : OUT STD_LOGIC; s_axis_data_tlast : IN STD_LOGIC; m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tready : IN STD_LOGIC; m_axis_data_tlast : OUT STD_LOGIC; event_frame_started : OUT STD_LOGIC; event_tlast_unexpected : OUT STD_LOGIC; event_tlast_missing : OUT STD_LOGIC; event_status_channel_halt : OUT STD_LOGIC; event_data_in_channel_halt : OUT STD_LOGIC; event_data_out_channel_halt : OUT STD_LOGIC ); END fft; ARCHITECTURE fft_arch OF fft IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF fft_arch: ARCHITECTURE IS "yes"; COMPONENT xfft_v9_0 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER; C_S_AXIS_DATA_TDATA_WIDTH : INTEGER; C_M_AXIS_DATA_TDATA_WIDTH : INTEGER; C_M_AXIS_DATA_TUSER_WIDTH : INTEGER; C_M_AXIS_STATUS_TDATA_WIDTH : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_CHANNELS : INTEGER; C_NFFT_MAX : INTEGER; C_ARCH : INTEGER; C_HAS_NFFT : INTEGER; C_USE_FLT_PT : INTEGER; C_INPUT_WIDTH : INTEGER; C_TWIDDLE_WIDTH : INTEGER; C_OUTPUT_WIDTH : INTEGER; C_HAS_SCALING : INTEGER; C_HAS_BFP : INTEGER; C_HAS_ROUNDING : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_HAS_OVFLO : INTEGER; C_HAS_NATURAL_INPUT : INTEGER; C_HAS_NATURAL_OUTPUT : INTEGER; C_HAS_CYCLIC_PREFIX : INTEGER; C_HAS_XK_INDEX : INTEGER; C_DATA_MEM_TYPE : INTEGER; C_TWIDDLE_MEM_TYPE : INTEGER; C_BRAM_STAGES : INTEGER; C_REORDER_MEM_TYPE : INTEGER; C_USE_HYBRID_RAM : INTEGER; C_OPTIMIZE_GOAL : INTEGER; C_CMPY_TYPE : INTEGER; C_BFLY_TYPE : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_config_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_config_tvalid : IN STD_LOGIC; s_axis_config_tready : OUT STD_LOGIC; s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_data_tvalid : IN STD_LOGIC; s_axis_data_tready : OUT STD_LOGIC; s_axis_data_tlast : IN STD_LOGIC; m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tready : IN STD_LOGIC; m_axis_data_tlast : OUT STD_LOGIC; m_axis_status_tdata : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_status_tvalid : OUT STD_LOGIC; m_axis_status_tready : IN STD_LOGIC; event_frame_started : OUT STD_LOGIC; event_tlast_unexpected : OUT STD_LOGIC; event_tlast_missing : OUT STD_LOGIC; event_fft_overflow : OUT STD_LOGIC; event_status_channel_halt : OUT STD_LOGIC; event_data_in_channel_halt : OUT STD_LOGIC; event_data_out_channel_halt : OUT STD_LOGIC ); END COMPONENT xfft_v9_0; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TLAST"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TUSER"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TREADY"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TLAST"; ATTRIBUTE X_INTERFACE_INFO OF event_frame_started: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_frame_started_intf INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF event_tlast_unexpected: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_tlast_unexpected_intf INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF event_tlast_missing: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_tlast_missing_intf INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF event_status_channel_halt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_status_channel_halt_intf INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF event_data_in_channel_halt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_data_in_channel_halt_intf INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF event_data_out_channel_halt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_data_out_channel_halt_intf INTERRUPT"; BEGIN U0 : xfft_v9_0 GENERIC MAP ( C_XDEVICEFAMILY => "zynq", C_S_AXIS_CONFIG_TDATA_WIDTH => 8, C_S_AXIS_DATA_TDATA_WIDTH => 32, C_M_AXIS_DATA_TDATA_WIDTH => 64, C_M_AXIS_DATA_TUSER_WIDTH => 16, C_M_AXIS_STATUS_TDATA_WIDTH => 1, C_THROTTLE_SCHEME => 1, C_CHANNELS => 1, C_NFFT_MAX => 12, C_ARCH => 1, C_HAS_NFFT => 0, C_USE_FLT_PT => 0, C_INPUT_WIDTH => 16, C_TWIDDLE_WIDTH => 16, C_OUTPUT_WIDTH => 29, C_HAS_SCALING => 0, C_HAS_BFP => 0, C_HAS_ROUNDING => 0, C_HAS_ACLKEN => 0, C_HAS_ARESETN => 0, C_HAS_OVFLO => 0, C_HAS_NATURAL_INPUT => 1, C_HAS_NATURAL_OUTPUT => 1, C_HAS_CYCLIC_PREFIX => 0, C_HAS_XK_INDEX => 1, C_DATA_MEM_TYPE => 1, C_TWIDDLE_MEM_TYPE => 1, C_BRAM_STAGES => 0, C_REORDER_MEM_TYPE => 1, C_USE_HYBRID_RAM => 0, C_OPTIMIZE_GOAL => 0, C_CMPY_TYPE => 1, C_BFLY_TYPE => 0 ) PORT MAP ( aclk => aclk, aclken => '1', aresetn => '1', s_axis_config_tdata => s_axis_config_tdata, s_axis_config_tvalid => s_axis_config_tvalid, s_axis_config_tready => s_axis_config_tready, s_axis_data_tdata => s_axis_data_tdata, s_axis_data_tvalid => s_axis_data_tvalid, s_axis_data_tready => s_axis_data_tready, s_axis_data_tlast => s_axis_data_tlast, m_axis_data_tdata => m_axis_data_tdata, m_axis_data_tuser => m_axis_data_tuser, m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tready => m_axis_data_tready, m_axis_data_tlast => m_axis_data_tlast, m_axis_status_tready => '1', event_frame_started => event_frame_started, event_tlast_unexpected => event_tlast_unexpected, event_tlast_missing => event_tlast_missing, event_status_channel_halt => event_status_channel_halt, event_data_in_channel_halt => event_data_in_channel_halt, event_data_out_channel_halt => event_data_out_channel_halt ); END fft_arch; |
context vvc_context is library bitvis_vip_axistream; use bitvis_vip_axistream.axistream_bfm_pkg.all; use bitvis_vip_axistream.vvc_cmd_pkg.all; use bitvis_vip_axistream.vvc_methods_pkg.all; use bitvis_vip_axistream.td_vvc_framework_common_methods_pkg.all; end context; |
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity contact_discoverycud_ram is generic( mem_type : string := "block"; dwidth : integer := 8; awidth : integer := 19; mem_size : integer := 480000 ); port ( addr0 : in std_logic_vector(awidth-1 downto 0); ce0 : in std_logic; d0 : in std_logic_vector(dwidth-1 downto 0); we0 : in std_logic; q0 : out std_logic_vector(dwidth-1 downto 0); addr1 : in std_logic_vector(awidth-1 downto 0); ce1 : in std_logic; q1 : out std_logic_vector(dwidth-1 downto 0); clk : in std_logic ); end entity; architecture rtl of contact_discoverycud_ram is signal addr0_tmp : std_logic_vector(awidth-1 downto 0); signal addr1_tmp : std_logic_vector(awidth-1 downto 0); type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0); shared variable ram : mem_array := (others=>(others=>'0')); attribute syn_ramstyle : string; attribute syn_ramstyle of ram : variable is "block_ram"; attribute ram_style : string; attribute ram_style of ram : variable is mem_type; attribute EQUIVALENT_REGISTER_REMOVAL : string; begin memory_access_guard_0: process (addr0) begin addr0_tmp <= addr0; if (CONV_INTEGER(addr0) > mem_size-1) then addr0_tmp <= (others => '0'); else addr0_tmp <= addr0; end if; end process; p_memory_access_0: process (clk) begin if (clk'event and clk = '1') then if (ce0 = '1') then if (we0 = '1') then ram(CONV_INTEGER(addr0_tmp)) := d0; end if; q0 <= ram(CONV_INTEGER(addr0_tmp)); end if; end if; end process; memory_access_guard_1: process (addr1) begin addr1_tmp <= addr1; if (CONV_INTEGER(addr1) > mem_size-1) then addr1_tmp <= (others => '0'); else addr1_tmp <= addr1; end if; end process; p_memory_access_1: process (clk) begin if (clk'event and clk = '1') then if (ce1 = '1') then q1 <= ram(CONV_INTEGER(addr1_tmp)); end if; end if; end process; end rtl; Library IEEE; use IEEE.std_logic_1164.all; entity contact_discoverycud is generic ( DataWidth : INTEGER := 8; AddressRange : INTEGER := 480000; AddressWidth : INTEGER := 19); port ( reset : IN STD_LOGIC; clk : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0)); end entity; architecture arch of contact_discoverycud is component contact_discoverycud_ram is port ( clk : IN STD_LOGIC; addr0 : IN STD_LOGIC_VECTOR; ce0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR; we0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR; addr1 : IN STD_LOGIC_VECTOR; ce1 : IN STD_LOGIC; q1 : OUT STD_LOGIC_VECTOR); end component; begin contact_discoverycud_ram_U : component contact_discoverycud_ram port map ( clk => clk, addr0 => address0, ce0 => ce0, d0 => d0, we0 => we0, q0 => q0, addr1 => address1, ce1 => ce1, q1 => q1); end architecture; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package cu is -- Control unit input sizes constant OPCODE_SIZE : integer := 6; -- OPCODE field size constant FUNC_SIZE : integer := 11; -- FUNC field size subtype OPCODE_TYPE is std_logic_vector(OPCODE_SIZE - 1 downto 0); -- I-Type instructions constant ITYPE_ADD : OPCODE_TYPE := "001000"; constant ITYPE_AND : OPCODE_TYPE := "001100"; constant ITYPE_OR : OPCODE_TYPE := "001101"; constant ITYPE_SUB : OPCODE_TYPE := "001010"; constant ITYPE_XOR : OPCODE_TYPE := "001110"; constant ITYPE_SLL : OPCODE_TYPE := "010100"; constant ITYPE_SRL : OPCODE_TYPE := "010110"; constant ITYPE_SRA : OPCODE_TYPE := "010111"; constant ITYPE_SEQ : OPCODE_TYPE := "011000"; constant ITYPE_SNE : OPCODE_TYPE := "011001"; constant ITYPE_SGE : OPCODE_TYPE := "011101"; constant ITYPE_SGT : OPCODE_TYPE := "011011"; constant ITYPE_SLE : OPCODE_TYPE := "011100"; constant ITYPE_SLT : OPCODE_TYPE := "011010"; constant ITYPE_SGEU : OPCODE_TYPE := "111101"; constant ITYPE_SGTU : OPCODE_TYPE := "111011"; constant ITYPE_SLEU : OPCODE_TYPE := "111100"; constant ITYPE_SLTU : OPCODE_TYPE := "111010"; constant NOP : OPCODE_TYPE := "010101"; -- Jump [ OPCODE(6) - PCOFFSET(26) ] constant JTYPE_J : OPCODE_TYPE := "000010"; constant JTYPE_JAL : OPCODE_TYPE := "000011"; constant JTYPE_JR : OPCODE_TYPE := "010010"; -- Branch [ OPCODE(6) - REG(5) - PCOFFSET(21) ] constant BTYPE_BEQZ : OPCODE_TYPE := "000100"; constant BTYPE_BNEZ : OPCODE_TYPE := "000101"; -- Memory [ OPCODE(6) - RDISPLACEMENT(5) - REG(5) - DISPLACEMENT(16) ] constant MTYPE_LW : OPCODE_TYPE := "100011"; constant MTYPE_SW : OPCODE_TYPE := "101011"; -- R-Type instruction -> OPCODE field constant RTYPE : OPCODE_TYPE := "000000"; subtype FUNC_TYPE is std_logic_vector(FUNC_SIZE - 1 downto 0); -- R-Type instruction -> FUNC field constant RTYPE_ADD : FUNC_TYPE := "00000100000"; constant RTYPE_AND : FUNC_TYPE := "00000100100"; constant RTYPE_OR : FUNC_TYPE := "00000100101"; constant RTYPE_SUB : FUNC_TYPE := "00000100010"; constant RTYPE_XOR : FUNC_TYPE := "00000100110"; constant RTYPE_SLL : FUNC_TYPE := "00000000100"; constant RTYPE_SRL : FUNC_TYPE := "00000000110"; constant RTYPE_SRA : FUNC_TYPE := "00000000111"; constant RTYPE_SEQ : FUNC_TYPE := "00000101000"; constant RTYPE_SNE : FUNC_TYPE := "00000101001"; constant RTYPE_SGE : FUNC_TYPE := "00000101101"; constant RTYPE_SGT : FUNC_TYPE := "00000101011"; constant RTYPE_SLE : FUNC_TYPE := "00000101100"; constant RTYPE_SLT : FUNC_TYPE := "00000101010"; constant RTYPE_SGEU : FUNC_TYPE := "00000111101"; constant RTYPE_SGTU : FUNC_TYPE := "00000111011"; constant RTYPE_SLEU : FUNC_TYPE := "00000111100"; constant RTYPE_SLTU : FUNC_TYPE := "00000111010"; constant RTYPE_NOP : FUNC_TYPE := "00000000000"; end cu; |
context uvvm_util_context is library uvvm_util; use uvvm_util.types_pkg.all; use uvvm_util.global_signals_and_shared_variables_pkg.all; use uvvm_util.hierarchy_linked_list_pkg.all; use uvvm_util.string_methods_pkg.all; use uvvm_util.adaptations_pkg.all; use uvvm_util.methods_pkg.all; use uvvm_util.bfm_common_pkg.all; use uvvm_util.alert_hierarchy_pkg.all; use uvvm_util.license_pkg.all; use uvvm_util.protected_types_pkg.all; use uvvm_util.rand_pkg.all; use uvvm_util.func_cov_pkg.all; end context; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity clk_108MHzclk_108MHz_clk_wiz is port ( clk_100MHz : in STD_LOGIC; clk_108MHz : out STD_LOGIC; locked : out STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of clk_108MHzclk_108MHz_clk_wiz : entity is "clk_108MHz_clk_wiz"; end clk_108MHzclk_108MHz_clk_wiz; architecture STRUCTURE of clk_108MHzclk_108MHz_clk_wiz is signal clk_100MHz_clk_108MHz : STD_LOGIC; signal clk_108MHz_clk_108MHz : STD_LOGIC; signal clkfbout_buf_clk_108MHz : STD_LOGIC; signal clkfbout_clk_108MHz : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); attribute box_type : string; attribute box_type of clkf_buf : label is "PRIMITIVE"; attribute CAPACITANCE : string; attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; attribute IBUF_DELAY_VALUE : string; attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; attribute IFD_DELAY_VALUE : string; attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; attribute box_type of clkin1_ibufg : label is "PRIMITIVE"; attribute box_type of clkout1_buf : label is "PRIMITIVE"; attribute box_type of mmcm_adv_inst : label is "PRIMITIVE"; begin clkf_buf: unisim.vcomponents.BUFG port map ( I => clkfbout_clk_108MHz, O => clkfbout_buf_clk_108MHz ); clkin1_ibufg: unisim.vcomponents.IBUF generic map( IOSTANDARD => "DEFAULT" ) port map ( I => clk_100MHz, O => clk_100MHz_clk_108MHz ); clkout1_buf: unisim.vcomponents.BUFG port map ( I => clk_108MHz_clk_108MHz, O => clk_108MHz ); mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV generic map( BANDWIDTH => "OPTIMIZED", CLKFBOUT_MULT_F => 10.125000, CLKFBOUT_PHASE => 0.000000, CLKFBOUT_USE_FINE_PS => false, CLKIN1_PERIOD => 10.000000, CLKIN2_PERIOD => 0.000000, CLKOUT0_DIVIDE_F => 9.375000, CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, CLKOUT0_USE_FINE_PS => false, CLKOUT1_DIVIDE => 1, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, CLKOUT1_USE_FINE_PS => false, CLKOUT2_DIVIDE => 1, CLKOUT2_DUTY_CYCLE => 0.500000, CLKOUT2_PHASE => 0.000000, CLKOUT2_USE_FINE_PS => false, CLKOUT3_DIVIDE => 1, CLKOUT3_DUTY_CYCLE => 0.500000, CLKOUT3_PHASE => 0.000000, CLKOUT3_USE_FINE_PS => false, CLKOUT4_CASCADE => false, CLKOUT4_DIVIDE => 1, CLKOUT4_DUTY_CYCLE => 0.500000, CLKOUT4_PHASE => 0.000000, CLKOUT4_USE_FINE_PS => false, CLKOUT5_DIVIDE => 1, CLKOUT5_DUTY_CYCLE => 0.500000, CLKOUT5_PHASE => 0.000000, CLKOUT5_USE_FINE_PS => false, CLKOUT6_DIVIDE => 1, CLKOUT6_DUTY_CYCLE => 0.500000, CLKOUT6_PHASE => 0.000000, CLKOUT6_USE_FINE_PS => false, COMPENSATION => "ZHOLD", DIVCLK_DIVIDE => 1, IS_CLKINSEL_INVERTED => '0', IS_PSEN_INVERTED => '0', IS_PSINCDEC_INVERTED => '0', IS_PWRDWN_INVERTED => '0', IS_RST_INVERTED => '0', REF_JITTER1 => 0.010000, REF_JITTER2 => 0.000000, SS_EN => "FALSE", SS_MODE => "CENTER_HIGH", SS_MOD_PERIOD => 10000, STARTUP_WAIT => false ) port map ( CLKFBIN => clkfbout_buf_clk_108MHz, CLKFBOUT => clkfbout_clk_108MHz, CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, CLKIN1 => clk_100MHz_clk_108MHz, CLKIN2 => '0', CLKINSEL => '1', CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, CLKOUT0 => clk_108MHz_clk_108MHz, CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, DADDR(6) => '0', DADDR(5) => '0', DADDR(4) => '0', DADDR(3) => '0', DADDR(2) => '0', DADDR(1) => '0', DADDR(0) => '0', DCLK => '0', DEN => '0', DI(15) => '0', DI(14) => '0', DI(13) => '0', DI(12) => '0', DI(11) => '0', DI(10) => '0', DI(9) => '0', DI(8) => '0', DI(7) => '0', DI(6) => '0', DI(5) => '0', DI(4) => '0', DI(3) => '0', DI(2) => '0', DI(1) => '0', DI(0) => '0', DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, DWE => '0', LOCKED => locked, PSCLK => '0', PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, PSEN => '0', PSINCDEC => '0', PWRDWN => '0', RST => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity clk_108MHz is port ( clk_100MHz : in STD_LOGIC; clk_108MHz : out STD_LOGIC; locked : out STD_LOGIC ); end clk_108MHz; architecture STRUCTURE of clk_108MHz is attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of STRUCTURE : architecture is true; begin U0: entity work.clk_108MHzclk_108MHz_clk_wiz port map ( clk_100MHz => clk_100MHz, clk_108MHz => clk_108MHz, locked => locked ); end STRUCTURE; |
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY DEBUG_RAM_synth IS PORT( CLK_IN : IN STD_LOGIC; CLKB_IN : IN STD_LOGIC; RESET_IN : IN STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA ); END ENTITY; ARCHITECTURE DEBUG_RAM_synth_ARCH OF DEBUG_RAM_synth IS COMPONENT DEBUG_RAM_exdes PORT ( --Inputs - Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0); CLKA : IN STD_LOGIC; --Inputs - Port B ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CLKB : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA: STD_LOGIC := '0'; SIGNAL RSTA: STD_LOGIC := '0'; SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA: STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA_R: STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0'); SIGNAL CLKB: STD_LOGIC := '0'; SIGNAL RSTB: STD_LOGIC := '0'; SIGNAL ADDRB: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRB_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTB: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CHECKER_EN : STD_LOGIC:='0'; SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); SIGNAL clk_in_i: STD_LOGIC; SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; SIGNAL clkb_in_i: STD_LOGIC; SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1'; SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1'; SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1'; SIGNAL ITER_R0 : STD_LOGIC := '0'; SIGNAL ITER_R1 : STD_LOGIC := '0'; SIGNAL ITER_R2 : STD_LOGIC := '0'; SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); BEGIN clk_in_i <= CLK_IN; CLKA <= clk_in_i; clkb_in_i <= CLKB_IN; CLKB <= clkb_in_i; RSTA <= RESET_SYNC_R3 AFTER 50 ns; PROCESS(clk_in_i) BEGIN IF(RISING_EDGE(clk_in_i)) THEN RESET_SYNC_R1 <= RESET_IN; RESET_SYNC_R2 <= RESET_SYNC_R1; RESET_SYNC_R3 <= RESET_SYNC_R2; END IF; END PROCESS; RSTB <= RESETB_SYNC_R3 AFTER 50 ns; PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN RESETB_SYNC_R1 <= RESET_IN; RESETB_SYNC_R2 <= RESETB_SYNC_R1; RESETB_SYNC_R3 <= RESETB_SYNC_R2; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ISSUE_FLAG_STATUS<= (OTHERS => '0'); ELSE ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; END IF; END IF; END PROCESS; STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; BMG_DATA_CHECKER_INST: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 64, READ_WIDTH => 4 ) PORT MAP ( CLK => clkb_in_i, RST => RSTB, EN => CHECKER_EN_R, DATA_IN => DOUTB, STATUS => ISSUE_FLAG(0) ); PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN IF(RSTB='1') THEN CHECKER_EN_R <= '0'; ELSE CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; END IF; END IF; END PROCESS; BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN PORT MAP( CLKA => clk_in_i, CLKB => clkb_in_i, TB_RST => RSTA, ADDRA => ADDRA, DINA => DINA, WEA => WEA, ADDRB => ADDRB, CHECK_DATA => CHECKER_EN ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STATUS(8) <= '0'; iter_r2 <= '0'; iter_r1 <= '0'; iter_r0 <= '0'; ELSE STATUS(8) <= iter_r2; iter_r2 <= iter_r1; iter_r1 <= iter_r0; iter_r0 <= STIMULUS_FLOW(8); END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STIMULUS_FLOW <= (OTHERS => '0'); ELSIF(WEA(0)='1') THEN STIMULUS_FLOW <= STIMULUS_FLOW+1; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN WEA_R <= (OTHERS=>'0') AFTER 50 ns; DINA_R <= (OTHERS=>'0') AFTER 50 ns; ELSE WEA_R <= WEA AFTER 50 ns; DINA_R <= DINA AFTER 50 ns; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; ADDRB_R <= (OTHERS=> '0') AFTER 50 ns; ELSE ADDRA_R <= ADDRA AFTER 50 ns; ADDRB_R <= ADDRB AFTER 50 ns; END IF; END IF; END PROCESS; BMG_PORT: DEBUG_RAM_exdes PORT MAP ( --Port A WEA => WEA_R, ADDRA => ADDRA_R, DINA => DINA_R, CLKA => CLKA, --Port B ADDRB => ADDRB_R, DOUTB => DOUTB, CLKB => CLKB ); END ARCHITECTURE; |
etgen\par owyRXTX_timesim.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; library SIMPRIM; use SIMPRIM.VCOMPONENTS.ALL; use SIMPRIM.VPACKAGE.ALL; entity nowyRXTX is port ( MDIO : inout STD_LOGIC; clk : in STD_LOGIC := 'X'; MDC : out STD_LOGIC; strt : in STD_LOGIC := 'X'; reset : in STD_LOGIC := 'X'; busy : out STD_LOGIC; write_read : in STD_LOGIC := 'X'; data_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); phy_addr : in STD_LOGIC_VECTOR ( 4 downto 0 ); data_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); reg_addr : in STD_LOGIC_VECTOR ( 4 downto 0 ) ); end nowyRXTX; architecture Structure of nowyRXTX is signal write_send_data_not0001_0 : STD_LOGIC; signal clk_div_1313 : STD_LOGIC; signal reset_IBUF_1314 : STD_LOGIC; signal read_receive_data_0_cmp_gt00001_1316 : STD_LOGIC; signal N3 : STD_LOGIC; signal read_send_data_10_or0000_0 : STD_LOGIC; signal read_send_data_11_not0001_inv : STD_LOGIC; signal clk_BUFGP : STD_LOGIC; signal latched_write_read_1343 : STD_LOGIC; signal Mtridata_MDIO_and0000135 : STD_LOGIC; signal Mtridata_MDIO_1348 : STD_LOGIC; signal read_send_data_10_and0000_0 : STD_LOGIC; signal N6_0 : STD_LOGIC; signal read_send_data_0_cmp_lt0000 : STD_LOGIC; signal read_send_data_0_not0001_0 : STD_LOGIC; signal Mtrien_MDIO_1353 : STD_LOGIC; signal read_receive_data_0_and0000_0 : STD_LOGIC; signal reg_addr_1_IBUF_1360 : STD_LOGIC; signal reg_addr_0_IBUF_1361 : STD_LOGIC; signal strt_IBUF_1362 : STD_LOGIC; signal reg_addr_3_IBUF_1365 : STD_LOGIC; signal reg_addr_2_IBUF_1366 : STD_LOGIC; signal reg_addr_4_IBUF_1369 : STD_LOGIC; signal read_receive_data_0_cmp_gt000011_0 : STD_LOGIC; signal read_send_data_0_cmp_lt0000112_0 : STD_LOGIC; signal read_send_data_0_cmp_lt0000134_0 : STD_LOGIC; signal N10_0 : STD_LOGIC; signal N8_0 : STD_LOGIC; signal Mtridata_MDIO_and000028 : STD_LOGIC; signal N20_0 : STD_LOGIC; signal N4_0 : STD_LOGIC; signal phy_addr_1_IBUF_1386 : STD_LOGIC; signal phy_addr_0_IBUF_1387 : STD_LOGIC; signal phy_addr_3_IBUF_1390 : STD_LOGIC; signal phy_addr_2_IBUF_1391 : STD_LOGIC; signal phy_addr_4_IBUF_1394 : STD_LOGIC; signal clk_div1 : STD_LOGIC; signal Mtridata_MDC_1397 : STD_LOGIC; signal bit_counter_6_1_1403 : STD_LOGIC; signal busy_in_cmp_eq0000_1409 : STD_LOGIC; signal busy_in_1448 : STD_LOGIC; signal counter_cmp_eq000010_0 : STD_LOGIC; signal N18_0 : STD_LOGIC; signal counter_cmp_eq000023_1460 : STD_LOGIC; signal Mcount_bit_counter_cy_1_Q : STD_LOGIC; signal Mcount_bit_counter_cy_3_Q : STD_LOGIC; signal counter_or0000 : STD_LOGIC; signal Mcount_counter_cy_1_Q : STD_LOGIC; signal Mcount_counter_cy_3_Q : STD_LOGIC; signal write_send_data_and0000_0 : STD_LOGIC; signal read_receive_data_0_and0000_SW2_O : STD_LOGIC; signal write_send_data_59_DXMUX_1578 : STD_LOGIC; signal write_send_data_mux0005 : STD_LOGIC; signal write_send_data_59_DYMUX_1565 : STD_LOGIC; signal write_send_data_mux0006 : STD_LOGIC; signal write_send_data_59_SRINV_1557 : STD_LOGIC; signal write_send_data_59_CLKINVNOT : STD_LOGIC; signal write_send_data_59_CEINV_1555 : STD_LOGIC; signal read_send_data_10_or0000 : STD_LOGIC; signal write_send_data_0_DYMUX_1607 : STD_LOGIC; signal write_send_data_mux0062 : STD_LOGIC; signal write_send_data_0_SRINV_1599 : STD_LOGIC; signal write_send_data_0_CLKINVNOT : STD_LOGIC; signal write_send_data_0_CEINV_1597 : STD_LOGIC; signal write_send_data_3_DXMUX_1656 : STD_LOGIC; signal write_send_data_mux0059 : STD_LOGIC; signal write_send_data_3_DYMUX_1642 : STD_LOGIC; signal write_send_data_mux0060 : STD_LOGIC; signal write_send_data_3_SRINV_1633 : STD_LOGIC; signal write_send_data_3_CLKINVNOT : STD_LOGIC; signal write_send_data_3_CEINV_1631 : STD_LOGIC; signal write_send_data_5_DXMUX_1698 : STD_LOGIC; signal write_send_data_mux0057 : STD_LOGIC; signal write_send_data_5_DYMUX_1684 : STD_LOGIC; signal write_send_data_mux0058 : STD_LOGIC; signal write_send_data_5_SRINV_1675 : STD_LOGIC; signal write_send_data_5_CLKINVNOT : STD_LOGIC; signal write_send_data_5_CEINV_1673 : STD_LOGIC; signal write_send_data_7_DXMUX_1740 : STD_LOGIC; signal write_send_data_mux0055 : STD_LOGIC; signal write_send_data_7_DYMUX_1726 : STD_LOGIC; signal write_send_data_mux0056 : STD_LOGIC; signal write_send_data_7_SRINV_1717 : STD_LOGIC; signal write_send_data_7_CLKINVNOT : STD_LOGIC; signal write_send_data_7_CEINV_1715 : STD_LOGIC; signal write_send_data_9_DXMUX_1782 : STD_LOGIC; signal write_send_data_mux0053 : STD_LOGIC; signal write_send_data_9_DYMUX_1768 : STD_LOGIC; signal write_send_data_mux0054 : STD_LOGIC; signal write_send_data_9_SRINV_1759 : STD_LOGIC; signal write_send_data_9_CLKINVNOT : STD_LOGIC; signal write_send_data_9_CEINV_1757 : STD_LOGIC; signal Mtridata_MDIO_and0000 : STD_LOGIC; signal Mtridata_MDIO_DYMUX_1805 : STD_LOGIC; signal Mtridata_MDIO_mux0000 : STD_LOGIC; signal Mtridata_MDIO_CLKINV_1797 : STD_LOGIC; signal read_send_data_0_not0001 : STD_LOGIC; signal Mtrien_MDIO_DYMUX_1839 : STD_LOGIC; signal Mtrien_MDIO_mux0000_norst_1836 : STD_LOGIC; signal Mtrien_MDIO_SRINV_1831 : STD_LOGIC; signal Mtrien_MDIO_CLKINV_1830 : STD_LOGIC; signal read_receive_data_7_DXMUX_1869 : STD_LOGIC; signal read_receive_data_7_DYMUX_1862 : STD_LOGIC; signal read_receive_data_7_SRINV_1860 : STD_LOGIC; signal read_receive_data_7_CLKINV_1859 : STD_LOGIC; signal read_receive_data_7_CEINV_1858 : STD_LOGIC; signal read_receive_data_9_DXMUX_1893 : STD_LOGIC; signal read_receive_data_9_DYMUX_1886 : STD_LOGIC; signal read_receive_data_9_SRINV_1884 : STD_LOGIC; signal read_receive_data_9_CLKINV_1883 : STD_LOGIC; signal read_receive_data_9_CEINV_1882 : STD_LOGIC; signal latched_reg_addr_1_DXMUX_1914 : STD_LOGIC; signal latched_reg_addr_1_DYMUX_1908 : STD_LOGIC; signal latched_reg_addr_1_CLKINV_1906 : STD_LOGIC; signal latched_reg_addr_1_CEINV_1905 : STD_LOGIC; signal latched_reg_addr_3_DXMUX_1934 : STD_LOGIC; signal latched_reg_addr_3_DYMUX_1928 : STD_LOGIC; signal latched_reg_addr_3_CLKINV_1926 : STD_LOGIC; signal latched_reg_addr_3_CEINV_1925 : STD_LOGIC; signal latched_reg_addr_4_DYMUX_1946 : STD_LOGIC; signal latched_reg_addr_4_CLKINV_1944 : STD_LOGIC; signal latched_reg_addr_4_CEINV_1943 : STD_LOGIC; signal read_receive_data_0_cmp_gt000011 : STD_LOGIC; signal read_send_data_0_cmp_lt0000112_1965 : STD_LOGIC; signal N6 : STD_LOGIC; signal read_send_data_0_cmp_lt0000134_1989 : STD_LOGIC; signal N10 : STD_LOGIC; signal N8 : STD_LOGIC; signal N20 : STD_LOGIC; signal N4 : STD_LOGIC; signal latched_phy_addr_1_DXMUX_2062 : STD_LOGIC; signal latched_phy_addr_1_DYMUX_2056 : STD_LOGIC; signal latched_phy_addr_1_CLKINV_2054 : STD_LOGIC; signal latched_phy_addr_1_CEINV_2053 : STD_LOGIC; signal latched_phy_addr_3_DXMUX_2082 : STD_LOGIC; signal latched_phy_addr_3_DYMUX_2076 : STD_LOGIC; signal latched_phy_addr_3_CLKINV_2074 : STD_LOGIC; signal latched_phy_addr_3_CEINV_2073 : STD_LOGIC; signal latched_phy_addr_4_DYMUX_2094 : STD_LOGIC; signal latched_phy_addr_4_CLKINV_2092 : STD_LOGIC; signal latched_phy_addr_4_CEINV_2091 : STD_LOGIC; signal Mtridata_MDC_DYMUX_2104 : STD_LOGIC; signal Mtridata_MDC_CLKINV_2102 : STD_LOGIC; signal read_receive_data_11_DXMUX_2126 : STD_LOGIC; signal read_receive_data_11_DYMUX_2119 : STD_LOGIC; signal read_receive_data_11_SRINV_2117 : STD_LOGIC; signal read_receive_data_11_CLKINV_2116 : STD_LOGIC; signal read_receive_data_11_CEINV_2115 : STD_LOGIC; signal read_receive_data_13_DXMUX_2150 : STD_LOGIC; signal read_receive_data_13_DYMUX_2143 : STD_LOGIC; signal read_receive_data_13_SRINV_2141 : STD_LOGIC; signal read_receive_data_13_CLKINV_2140 : STD_LOGIC; signal read_receive_data_13_CEINV_2139 : STD_LOGIC; signal bit_counter_6_1_DYMUX_2163 : STD_LOGIC; signal bit_counter_6_1_CLKINVNOT : STD_LOGIC; signal read_receive_data_15_DXMUX_2188 : STD_LOGIC; signal read_receive_data_15_DYMUX_2181 : STD_LOGIC; signal read_receive_data_15_SRINV_2179 : STD_LOGIC; signal read_receive_data_15_CLKINV_2178 : STD_LOGIC; signal read_receive_data_15_CEINV_2177 : STD_LOGIC; signal write_send_data_1_DXMUX_2224 : STD_LOGIC; signal write_send_data_mux0061 : STD_LOGIC; signal read_send_data_11_not0001_inv_pack_1 : STD_LOGIC; signal write_send_data_1_SRINV_2207 : STD_LOGIC; signal write_send_data_1_CLKINVNOT : STD_LOGIC; signal write_send_data_1_CEINV_2205 : STD_LOGIC; signal clk_div1_DYMUX_2239 : STD_LOGIC; signal clk_div1_SRINV_2237 : STD_LOGIC; signal clk_div1_CLKINV_2236 : STD_LOGIC; signal clk_div1_CEINV_2235 : STD_LOGIC; signal clk_div_or0000 : STD_LOGIC; signal busy_in_cmp_eq0000_pack_1 : STD_LOGIC; signal read_send_data_10_DYMUX_2278 : STD_LOGIC; signal read_send_data_10_SRINV_2276 : STD_LOGIC; signal read_send_data_10_CLKINVNOT : STD_LOGIC; signal read_send_data_10_CEINV_2274 : STD_LOGIC; signal read_send_data_11_DXMUX_2296 : STD_LOGIC; signal read_send_data_11_REVUSED_2294 : STD_LOGIC; signal read_send_data_11_SRINV_2292 : STD_LOGIC; signal read_send_data_11_CLKINVNOT : STD_LOGIC; signal read_send_data_11_CEINV_2290 : STD_LOGIC; signal read_send_data_21_DXMUX_2334 : STD_LOGIC; signal read_send_data_21_REVUSED_2326 : STD_LOGIC; signal read_send_data_21_DYMUX_2325 : STD_LOGIC; signal read_send_data_19_rt_2322 : STD_LOGIC; signal read_send_data_21_SRINV_2313 : STD_LOGIC; signal read_send_data_21_CLKINVNOT : STD_LOGIC; signal read_send_data_21_CEINV_2311 : STD_LOGIC; signal read_send_data_12_DXMUX_2353 : STD_LOGIC; signal read_send_data_12_REVUSED_2351 : STD_LOGIC; signal read_send_data_12_SRINV_2349 : STD_LOGIC; signal read_send_data_12_CLKINVNOT : STD_LOGIC; signal read_send_data_12_CEINV_2347 : STD_LOGIC; signal read_send_data_13_DYMUX_2369 : STD_LOGIC; signal read_send_data_13_SRINV_2367 : STD_LOGIC; signal read_send_data_13_CLKINVNOT : STD_LOGIC; signal read_send_data_13_CEINV_2365 : STD_LOGIC; signal read_send_data_31_DXMUX_2406 : STD_LOGIC; signal read_send_data_31_REVUSED_2398 : STD_LOGIC; signal read_send_data_31_DYMUX_2397 : STD_LOGIC; signal read_send_data_29_rt_2394 : STD_LOGIC; signal read_send_data_31_SRINV_2385 : STD_LOGIC; signal read_send_data_31_CLKINVNOT : STD_LOGIC; signal read_send_data_31_CEINV_2383 : STD_LOGIC; signal read_send_data_23_DXMUX_2444 : STD_LOGIC; signal read_send_data_23_REVUSED_2436 : STD_LOGIC; signal read_send_data_23_DYMUX_2435 : STD_LOGIC; signal read_send_data_21_rt_2432 : STD_LOGIC; signal read_send_data_23_SRINV_2423 : STD_LOGIC; signal read_send_data_23_CLKINVNOT : STD_LOGIC; signal read_send_data_23_CEINV_2421 : STD_LOGIC; signal read_send_data_15_DXMUX_2482 : STD_LOGIC; signal read_send_data_15_REVUSED_2474 : STD_LOGIC; signal read_send_data_15_DYMUX_2473 : STD_LOGIC; signal read_send_data_13_rt_2470 : STD_LOGIC; signal read_send_data_15_SRINV_2461 : STD_LOGIC; signal read_send_data_15_CLKINVNOT : STD_LOGIC; signal read_send_data_15_CEINV_2459 : STD_LOGIC; signal latched_write_read_DYMUX_2496 : STD_LOGIC; signal latched_write_read_CLKINV_2494 : STD_LOGIC; signal latched_write_read_CEINV_2493 : STD_LOGIC; signal read_send_data_41_DXMUX_2532 : STD_LOGIC; signal read_send_data_41_REVUSED_2524 : STD_LOGIC; signal read_send_data_41_DYMUX_2523 : STD_LOGIC; signal read_send_data_39_rt_2520 : STD_LOGIC; signal read_send_data_41_SRINV_2511 : STD_LOGIC; signal read_send_data_41_CLKINVNOT : STD_LOGIC; signal read_send_data_41_CEINV_2509 : STD_LOGIC; signal read_send_data_33_DXMUX_2570 : STD_LOGIC; signal read_send_data_33_REVUSED_2562 : STD_LOGIC; signal read_send_data_33_DYMUX_2561 : STD_LOGIC; signal read_send_data_31_rt_2558 : STD_LOGIC; signal read_send_data_33_SRINV_2549 : STD_LOGIC; signal read_send_data_33_CLKINVNOT : STD_LOGIC; signal read_send_data_33_CEINV_2547 : STD_LOGIC; signal read_send_data_25_DXMUX_2608 : STD_LOGIC; signal read_send_data_25_REVUSED_2600 : STD_LOGIC; signal read_send_data_25_DYMUX_2599 : STD_LOGIC; signal read_send_data_23_rt_2596 : STD_LOGIC; signal read_send_data_25_SRINV_2587 : STD_LOGIC; signal read_send_data_25_CLKINVNOT : STD_LOGIC; signal read_send_data_25_CEINV_2585 : STD_LOGIC; signal read_send_data_17_DXMUX_2646 : STD_LOGIC; signal read_send_data_17_REVUSED_2638 : STD_LOGIC; signal read_send_data_17_DYMUX_2637 : STD_LOGIC; signal read_send_data_15_rt_2634 : STD_LOGIC; signal read_send_data_17_SRINV_2625 : STD_LOGIC; signal read_send_data_17_CLKINVNOT : STD_LOGIC; signal read_send_data_17_CEINV_2623 : STD_LOGIC; signal read_send_data_43_DXMUX_2684 : STD_LOGIC; signal read_send_data_43_REVUSED_2676 : STD_LOGIC; signal read_send_data_43_DYMUX_2675 : STD_LOGIC; signal read_send_data_41_rt_2672 : STD_LOGIC; signal read_send_data_43_SRINV_2663 : STD_LOGIC; signal read_send_data_43_CLKINVNOT : STD_LOGIC; signal read_send_data_43_CEINV_2661 : STD_LOGIC; signal read_send_data_35_DXMUX_2722 : STD_LOGIC; signal read_send_data_35_REVUSED_2714 : STD_LOGIC; signal read_send_data_35_DYMUX_2713 : STD_LOGIC; signal read_send_data_33_rt_2710 : STD_LOGIC; signal read_send_data_35_SRINV_2701 : STD_LOGIC; signal read_send_data_35_CLKINVNOT : STD_LOGIC; signal read_send_data_35_CEINV_2699 : STD_LOGIC; signal read_send_data_27_DXMUX_2760 : STD_LOGIC; signal read_send_data_27_REVUSED_2752 : STD_LOGIC; signal read_send_data_27_DYMUX_2751 : STD_LOGIC; signal read_send_data_25_rt_2748 : STD_LOGIC; signal read_send_data_27_SRINV_2739 : STD_LOGIC; signal read_send_data_27_CLKINVNOT : STD_LOGIC; signal read_send_data_27_CEINV_2737 : STD_LOGIC; signal read_send_data_19_DXMUX_2798 : STD_LOGIC; signal read_send_data_19_REVUSED_2790 : STD_LOGIC; signal read_send_data_19_DYMUX_2789 : STD_LOGIC; signal read_send_data_17_rt_2786 : STD_LOGIC; signal read_send_data_19_SRINV_2777 : STD_LOGIC; signal read_send_data_19_CLKINVNOT : STD_LOGIC; signal read_send_data_19_CEINV_2775 : STD_LOGIC; signal read_send_data_45_DXMUX_2836 : STD_LOGIC; signal read_send_data_45_REVUSED_2828 : STD_LOGIC; signal read_send_data_45_DYMUX_2827 : STD_LOGIC; signal read_send_data_43_rt_2824 : STD_LOGIC; signal read_send_data_45_SRINV_2815 : STD_LOGIC; signal read_send_data_45_CLKINVNOT : STD_LOGIC; signal read_send_data_45_CEINV_2813 : STD_LOGIC; signal read_send_data_37_DXMUX_2874 : STD_LOGIC; signal read_send_data_37_REVUSED_2866 : STD_LOGIC; signal read_send_data_37_DYMUX_2865 : STD_LOGIC; signal read_send_data_35_rt_2862 : STD_LOGIC; signal read_send_data_37_SRINV_2853 : STD_LOGIC; signal read_send_data_37_CLKINVNOT : STD_LOGIC; signal read_send_data_37_CEINV_2851 : STD_LOGIC; signal read_send_data_29_DXMUX_2912 : STD_LOGIC; signal read_send_data_29_REVUSED_2904 : STD_LOGIC; signal read_send_data_29_DYMUX_2903 : STD_LOGIC; signal read_send_data_27_rt_2900 : STD_LOGIC; signal read_send_data_29_SRINV_2891 : STD_LOGIC; signal read_send_data_29_CLKINVNOT : STD_LOGIC; signal read_send_data_29_CEINV_2889 : STD_LOGIC; signal read_send_data_39_DXMUX_2950 : STD_LOGIC; signal read_send_data_39_REVUSED_2942 : STD_LOGIC; signal read_send_data_39_DYMUX_2941 : STD_LOGIC; signal read_send_data_37_rt_2938 : STD_LOGIC; signal read_send_data_39_SRINV_2929 : STD_LOGIC; signal read_send_data_39_CLKINVNOT : STD_LOGIC; signal read_send_data_39_CEINV_2927 : STD_LOGIC; signal busy_in_DXMUX_2969 : STD_LOGIC; signal busy_in_BXINV_2968 : STD_LOGIC; signal busy_in_REVUSED_2967 : STD_LOGIC; signal busy_in_SRINV_2965 : STD_LOGIC; signal busy_in_CLKINV_2964 : STD_LOGIC; signal busy_in_CEINV_2963 : STD_LOGIC; signal counter_cmp_eq000010_2985 : STD_LOGIC; signal read_receive_data_1_DXMUX_3006 : STD_LOGIC; signal read_receive_data_1_DYMUX_2999 : STD_LOGIC; signal read_receive_data_1_SRINV_2997 : STD_LOGIC; signal read_receive_data_1_CLKINV_2996 : STD_LOGIC; signal read_receive_data_1_CEINV_2995 : STD_LOGIC; signal N18 : STD_LOGIC; signal read_receive_data_3_DXMUX_3042 : STD_LOGIC; signal read_receive_data_3_DYMUX_3035 : STD_LOGIC; signal read_receive_data_3_SRINV_3033 : STD_LOGIC; signal read_receive_data_3_CLKINV_3032 : STD_LOGIC; signal read_receive_data_3_CEINV_3031 : STD_LOGIC; signal clk_div_not0002 : STD_LOGIC; signal counter_cmp_eq000023_pack_1 : STD_LOGIC; signal read_receive_data_5_DXMUX_3090 : STD_LOGIC; signal read_receive_data_5_DYMUX_3083 : STD_LOGIC; signal read_receive_data_5_SRINV_3081 : STD_LOGIC; signal read_receive_data_5_CLKINV_3080 : STD_LOGIC; signal read_receive_data_5_CEINV_3079 : STD_LOGIC; signal bit_counter_0_DXMUX_3143 : STD_LOGIC; signal bit_counter_0_XORF_3141 : STD_LOGIC; signal bit_counter_0_LOGIC_ONE_3140 : STD_LOGIC; signal bit_counter_0_CYINIT_3139 : STD_LOGIC; signal bit_counter_0_CYSELF_3130 : STD_LOGIC; signal bit_counter_0_BXINV_3128 : STD_LOGIC; signal bit_counter_0_DYMUX_3121 : STD_LOGIC; signal bit_counter_0_XORG_3119 : STD_LOGIC; signal bit_counter_0_CYMUXG_3118 : STD_LOGIC; signal Mcount_bit_counter_cy_0_Q : STD_LOGIC; signal bit_counter_0_LOGIC_ZERO_3116 : STD_LOGIC; signal bit_counter_0_CYSELG_3107 : STD_LOGIC; signal bit_counter_0_G : STD_LOGIC; signal bit_counter_0_SRINV_3105 : STD_LOGIC; signal bit_counter_0_CLKINVNOT : STD_LOGIC; signal bit_counter_2_DXMUX_3199 : STD_LOGIC; signal bit_counter_2_XORF_3197 : STD_LOGIC; signal bit_counter_2_CYINIT_3196 : STD_LOGIC; signal bit_counter_2_F : STD_LOGIC; signal bit_counter_2_DYMUX_3180 : STD_LOGIC; signal bit_counter_2_XORG_3178 : STD_LOGIC; signal Mcount_bit_counter_cy_2_Q : STD_LOGIC; signal bit_counter_2_CYSELF_3176 : STD_LOGIC; signal bit_counter_2_CYMUXFAST_3175 : STD_LOGIC; signal bit_counter_2_CYAND_3174 : STD_LOGIC; signal bit_counter_2_FASTCARRY_3173 : STD_LOGIC; signal bit_counter_2_CYMUXG2_3172 : STD_LOGIC; signal bit_counter_2_CYMUXF2_3171 : STD_LOGIC; signal bit_counter_2_LOGIC_ZERO_3170 : STD_LOGIC; signal bit_counter_2_CYSELG_3161 : STD_LOGIC; signal bit_counter_2_G : STD_LOGIC; signal bit_counter_2_SRINV_3159 : STD_LOGIC; signal bit_counter_2_CLKINVNOT : STD_LOGIC; signal bit_counter_4_DXMUX_3255 : STD_LOGIC; signal bit_counter_4_XORF_3253 : STD_LOGIC; signal bit_counter_4_CYINIT_3252 : STD_LOGIC; signal bit_counter_4_F : STD_LOGIC; signal bit_counter_4_DYMUX_3236 : STD_LOGIC; signal bit_counter_4_XORG_3234 : STD_LOGIC; signal Mcount_bit_counter_cy_4_Q : STD_LOGIC; signal bit_counter_4_CYSELF_3232 : STD_LOGIC; signal bit_counter_4_CYMUXFAST_3231 : STD_LOGIC; signal bit_counter_4_CYAND_3230 : STD_LOGIC; signal bit_counter_4_FASTCARRY_3229 : STD_LOGIC; signal bit_counter_4_CYMUXG2_3228 : STD_LOGIC; signal bit_counter_4_CYMUXF2_3227 : STD_LOGIC; signal bit_counter_4_LOGIC_ZERO_3226 : STD_LOGIC; signal bit_counter_4_CYSELG_3217 : STD_LOGIC; signal bit_counter_4_G : STD_LOGIC; signal bit_counter_4_SRINV_3215 : STD_LOGIC; signal bit_counter_4_CLKINVNOT : STD_LOGIC; signal bit_counter_6_DXMUX_3305 : STD_LOGIC; signal bit_counter_6_FXMUX_3304 : STD_LOGIC; signal bit_counter_6_XORF_3303 : STD_LOGIC; signal bit_counter_6_LOGIC_ZERO_3302 : STD_LOGIC; signal bit_counter_6_CYINIT_3301 : STD_LOGIC; signal bit_counter_6_CYSELF_3292 : STD_LOGIC; signal bit_counter_6_F : STD_LOGIC; signal bit_counter_6_DYMUX_3284 : STD_LOGIC; signal bit_counter_6_XORG_3282 : STD_LOGIC; signal Mcount_bit_counter_cy_6_Q : STD_LOGIC; signal bit_counter_7_rt_3279 : STD_LOGIC; signal bit_counter_6_SRINV_3271 : STD_LOGIC; signal bit_counter_6_CLKINVNOT : STD_LOGIC; signal counter_0_DXMUX_3360 : STD_LOGIC; signal counter_0_XORF_3358 : STD_LOGIC; signal counter_0_LOGIC_ONE_3357 : STD_LOGIC; signal counter_0_CYINIT_3356 : STD_LOGIC; signal counter_0_CYSELF_3347 : STD_LOGIC; signal counter_0_BXINV_3345 : STD_LOGIC; signal counter_0_DYMUX_3339 : STD_LOGIC; signal counter_0_XORG_3337 : STD_LOGIC; signal counter_0_CYMUXG_3336 : STD_LOGIC; signal Mcount_counter_cy_0_Q : STD_LOGIC; signal counter_0_LOGIC_ZERO_3334 : STD_LOGIC; signal counter_0_CYSELG_3325 : STD_LOGIC; signal counter_0_G : STD_LOGIC; signal counter_0_SRINV_3323 : STD_LOGIC; signal counter_0_CLKINV_3322 : STD_LOGIC; signal counter_0_CEINV_3321 : STD_LOGIC; signal counter_2_DXMUX_3416 : STD_LOGIC; signal counter_2_XORF_3414 : STD_LOGIC; signal counter_2_CYINIT_3413 : STD_LOGIC; signal counter_2_F : STD_LOGIC; signal counter_2_DYMUX_3398 : STD_LOGIC; signal counter_2_XORG_3396 : STD_LOGIC; signal Mcount_counter_cy_2_Q : STD_LOGIC; signal counter_2_CYSELF_3394 : STD_LOGIC; signal counter_2_CYMUXFAST_3393 : STD_LOGIC; signal counter_2_CYAND_3392 : STD_LOGIC; signal counter_2_FASTCARRY_3391 : STD_LOGIC; signal counter_2_CYMUXG2_3390 : STD_LOGIC; signal counter_2_CYMUXF2_3389 : STD_LOGIC; signal counter_2_LOGIC_ZERO_3388 : STD_LOGIC; signal counter_2_CYSELG_3379 : STD_LOGIC; signal counter_2_G : STD_LOGIC; signal counter_2_SRINV_3377 : STD_LOGIC; signal counter_2_CLKINV_3376 : STD_LOGIC; signal counter_2_CEINV_3375 : STD_LOGIC; signal counter_4_DXMUX_3472 : STD_LOGIC; signal counter_4_XORF_3470 : STD_LOGIC; signal counter_4_CYINIT_3469 : STD_LOGIC; signal counter_4_F : STD_LOGIC; signal counter_4_DYMUX_3454 : STD_LOGIC; signal counter_4_XORG_3452 : STD_LOGIC; signal Mcount_counter_cy_4_Q : STD_LOGIC; signal counter_4_CYSELF_3450 : STD_LOGIC; signal counter_4_CYMUXFAST_3449 : STD_LOGIC; signal counter_4_CYAND_3448 : STD_LOGIC; signal counter_4_FASTCARRY_3447 : STD_LOGIC; signal counter_4_CYMUXG2_3446 : STD_LOGIC; signal counter_4_CYMUXF2_3445 : STD_LOGIC; signal counter_4_LOGIC_ZERO_3444 : STD_LOGIC; signal counter_4_CYSELG_3435 : STD_LOGIC; signal counter_4_G : STD_LOGIC; signal counter_4_SRINV_3433 : STD_LOGIC; signal counter_4_CLKINV_3432 : STD_LOGIC; signal counter_4_CEINV_3431 : STD_LOGIC; signal counter_6_DXMUX_3521 : STD_LOGIC; signal counter_6_XORF_3519 : STD_LOGIC; signal counter_6_LOGIC_ZERO_3518 : STD_LOGIC; signal counter_6_CYINIT_3517 : STD_LOGIC; signal counter_6_CYSELF_3508 : STD_LOGIC; signal counter_6_F : STD_LOGIC; signal counter_6_DYMUX_3501 : STD_LOGIC; signal counter_6_XORG_3499 : STD_LOGIC; signal Mcount_counter_cy_6_Q : STD_LOGIC; signal counter_7_rt_3496 : STD_LOGIC; signal counter_6_SRINV_3488 : STD_LOGIC; signal counter_6_CLKINV_3487 : STD_LOGIC; signal counter_6_CEINV_3486 : STD_LOGIC; signal MDIO_O : STD_LOGIC; signal MDIO_T : STD_LOGIC; signal MDIO_INBUF : STD_LOGIC; signal MDC_O : STD_LOGIC; signal MDC_T : STD_LOGIC; signal strt_INBUF : STD_LOGIC; signal clk_INBUF : STD_LOGIC; signal reg_addr_0_INBUF : STD_LOGIC; signal reg_addr_1_INBUF : STD_LOGIC; signal reg_addr_2_INBUF : STD_LOGIC; signal reg_addr_3_INBUF : STD_LOGIC; signal reg_addr_4_INBUF : STD_LOGIC; signal data_out_10_O : STD_LOGIC; signal data_out_11_O : STD_LOGIC; signal data_out_12_O : STD_LOGIC; signal data_out_13_O : STD_LOGIC; signal data_out_0_O : STD_LOGIC; signal data_out_1_O : STD_LOGIC; signal data_out_14_O : STD_LOGIC; signal data_out_2_O : STD_LOGIC; signal data_out_15_O : STD_LOGIC; signal data_out_3_O : STD_LOGIC; signal data_out_4_O : STD_LOGIC; signal data_in_0_INBUF : STD_LOGIC; signal data_out_5_O : STD_LOGIC; signal data_in_1_INBUF : STD_LOGIC; signal data_out_6_O : STD_LOGIC; signal data_in_10_INBUF : STD_LOGIC; signal data_in_2_INBUF : STD_LOGIC; signal data_in_2_IFF_ICLK1INV_3797 : STD_LOGIC; signal data_in_2_IFF_ICEINV_3795 : STD_LOGIC; signal data_in_2_IFF_IDDRIN_MUX_3793 : STD_LOGIC; signal data_out_7_O : STD_LOGIC; signal data_in_11_INBUF : STD_LOGIC; signal data_in_11_IFF_ICLK1INV_3825 : STD_LOGIC; signal data_in_11_IFF_ICEINV_3823 : STD_LOGIC; signal data_in_11_IFF_IDDRIN_MUX_3821 : STD_LOGIC; signal data_in_3_INBUF : STD_LOGIC; signal data_in_3_IFF_ICLK1INV_3845 : STD_LOGIC; signal data_in_3_IFF_ICEINV_3843 : STD_LOGIC; signal data_in_3_IFF_IDDRIN_MUX_3841 : STD_LOGIC; signal data_out_8_O : STD_LOGIC; signal data_in_12_INBUF : STD_LOGIC; signal data_in_12_IFF_ICLK1INV_3873 : STD_LOGIC; signal data_in_12_IFF_ICEINV_3871 : STD_LOGIC; signal data_in_12_IFF_IDDRIN_MUX_3869 : STD_LOGIC; signal data_in_4_INBUF : STD_LOGIC; signal data_in_4_IFF_ICLK1INV_3893 : STD_LOGIC; signal data_in_4_IFF_ICEINV_3891 : STD_LOGIC; signal data_in_4_IFF_IDDRIN_MUX_3889 : STD_LOGIC; signal data_out_9_O : STD_LOGIC; signal data_in_13_INBUF : STD_LOGIC; signal data_in_13_IFF_ICLK1INV_3921 : STD_LOGIC; signal data_in_13_IFF_ICEINV_3919 : STD_LOGIC; signal data_in_13_IFF_IDDRIN_MUX_3917 : STD_LOGIC; signal data_in_5_INBUF : STD_LOGIC; signal data_in_5_IFF_ICLK1INV_3941 : STD_LOGIC; signal data_in_5_IFF_ICEINV_3939 : STD_LOGIC; signal data_in_5_IFF_IDDRIN_MUX_3937 : STD_LOGIC; signal write_read_INBUF : STD_LOGIC; signal reset_INBUF : STD_LOGIC; signal data_in_14_INBUF : STD_LOGIC; signal data_in_6_INBUF : STD_LOGIC; signal data_in_6_IFF_ICLK1INV_3993 : STD_LOGIC; signal data_in_6_IFF_ICEINV_3991 : STD_LOGIC; signal data_in_6_IFF_IDDRIN_MUX_3989 : STD_LOGIC; signal phy_addr_0_INBUF : STD_LOGIC; signal data_in_15_INBUF : STD_LOGIC; signal data_in_7_INBUF : STD_LOGIC; signal phy_addr_1_INBUF : STD_LOGIC; signal data_in_8_INBUF : STD_LOGIC; signal phy_addr_2_INBUF : STD_LOGIC; signal data_in_9_INBUF : STD_LOGIC; signal phy_addr_3_INBUF : STD_LOGIC; signal phy_addr_4_INBUF : STD_LOGIC; signal busy_O : STD_LOGIC; signal clk_div_BUFG_S_INVNOT : STD_LOGIC; signal clk_div_BUFG_I0_INV : STD_LOGIC; signal clk_BUFGP_BUFG_S_INVNOT : STD_LOGIC; signal clk_BUFGP_BUFG_I0_INV : STD_LOGIC; signal counter_or0000_F5MUX_4178 : STD_LOGIC; signal counter_or0000_F : STD_LOGIC; signal counter_or0000_BXINV_4167 : STD_LOGIC; signal counter_or00001 : STD_LOGIC; signal Mtridata_MDIO_and0000135_F5MUX_4203 : STD_LOGIC; signal N23 : STD_LOGIC; signal Mtridata_MDIO_and0000135_BXINV_4195 : STD_LOGIC; signal N22 : STD_LOGIC; signal Mtridata_MDIO_and000028_F5MUX_4228 : STD_LOGIC; signal Mtridata_MDIO_and0000281_4226 : STD_LOGIC; signal Mtridata_MDIO_and000028_BXINV_4221 : STD_LOGIC; signal Mtridata_MDIO_and0000282_4219 : STD_LOGIC; signal read_send_data_10_and0000_4251 : STD_LOGIC; signal read_send_data_0_cmp_lt0000_pack_1 : STD_LOGIC; signal read_receive_data_0_and0000_4275 : STD_LOGIC; signal read_receive_data_0_and0000_SW2_O_pack_1 : STD_LOGIC; signal write_send_data_and0000_4299 : STD_LOGIC; signal read_receive_data_0_cmp_gt00001_pack_1 : STD_LOGIC; signal write_send_data_not0001 : STD_LOGIC; signal N3_pack_1 : STD_LOGIC; signal write_send_data_11_DXMUX_4362 : STD_LOGIC; signal write_send_data_mux0051 : STD_LOGIC; signal write_send_data_11_DYMUX_4348 : STD_LOGIC; signal write_send_data_mux0052 : STD_LOGIC; signal write_send_data_11_SRINV_4339 : STD_LOGIC; signal write_send_data_11_CLKINVNOT : STD_LOGIC; signal write_send_data_11_CEINV_4337 : STD_LOGIC; signal write_send_data_21_DXMUX_4404 : STD_LOGIC; signal write_send_data_mux0043 : STD_LOGIC; signal write_send_data_21_DYMUX_4390 : STD_LOGIC; signal write_send_data_mux0044 : STD_LOGIC; signal write_send_data_21_SRINV_4381 : STD_LOGIC; signal write_send_data_21_CLKINVNOT : STD_LOGIC; signal write_send_data_21_CEINV_4379 : STD_LOGIC; signal write_send_data_13_DXMUX_4446 : STD_LOGIC; signal write_send_data_mux0049 : STD_LOGIC; signal write_send_data_13_DYMUX_4432 : STD_LOGIC; signal write_send_data_mux0050 : STD_LOGIC; signal write_send_data_13_SRINV_4423 : STD_LOGIC; signal write_send_data_13_CLKINVNOT : STD_LOGIC; signal write_send_data_13_CEINV_4421 : STD_LOGIC; signal read_send_data_1_DXMUX_4488 : STD_LOGIC; signal read_send_data_1_mux0000 : STD_LOGIC; signal read_send_data_1_DYMUX_4474 : STD_LOGIC; signal read_send_data_0_mux0000 : STD_LOGIC; signal read_send_data_1_SRINV_4466 : STD_LOGIC; signal read_send_data_1_CLKINVNOT : STD_LOGIC; signal read_send_data_1_CEINV_4464 : STD_LOGIC; signal write_send_data_31_DXMUX_4530 : STD_LOGIC; signal write_send_data_mux0033 : STD_LOGIC; signal write_send_data_31_DYMUX_4517 : STD_LOGIC; signal write_send_data_mux0034 : STD_LOGIC; signal write_send_data_31_SRINV_4509 : STD_LOGIC; signal write_send_data_31_CLKINVNOT : STD_LOGIC; signal write_send_data_31_CEINV_4507 : STD_LOGIC; signal write_send_data_23_DXMUX_4572 : STD_LOGIC; signal write_send_data_mux0041 : STD_LOGIC; signal write_send_data_23_DYMUX_4558 : STD_LOGIC; signal write_send_data_mux0042 : STD_LOGIC; signal write_send_data_23_SRINV_4549 : STD_LOGIC; signal write_send_data_23_CLKINVNOT : STD_LOGIC; signal write_send_data_23_CEINV_4547 : STD_LOGIC; signal write_send_data_15_DXMUX_4614 : STD_LOGIC; signal write_send_data_mux0047 : STD_LOGIC; signal write_send_data_15_DYMUX_4600 : STD_LOGIC; signal write_send_data_mux0048 : STD_LOGIC; signal write_send_data_15_SRINV_4591 : STD_LOGIC; signal write_send_data_15_CLKINVNOT : STD_LOGIC; signal write_send_data_15_CEINV_4589 : STD_LOGIC; signal read_send_data_3_DXMUX_4656 : STD_LOGIC; signal read_send_data_3_mux0000 : STD_LOGIC; signal read_send_data_3_DYMUX_4642 : STD_LOGIC; signal read_send_data_2_mux0000 : STD_LOGIC; signal read_send_data_3_SRINV_4633 : STD_LOGIC; signal read_send_data_3_CLKINVNOT : STD_LOGIC; signal read_send_data_3_CEINV_4631 : STD_LOGIC; signal write_send_data_41_DXMUX_4698 : STD_LOGIC; signal write_send_data_mux0023 : STD_LOGIC; signal write_send_data_41_DYMUX_4685 : STD_LOGIC; signal write_send_data_mux0024 : STD_LOGIC; signal write_send_data_41_SRINV_4677 : STD_LOGIC; signal write_send_data_41_CLKINVNOT : STD_LOGIC; signal write_send_data_41_CEINV_4675 : STD_LOGIC; signal write_send_data_33_DXMUX_4740 : STD_LOGIC; signal write_send_data_mux0031 : STD_LOGIC; signal write_send_data_33_DYMUX_4727 : STD_LOGIC; signal write_send_data_mux0032 : STD_LOGIC; signal write_send_data_33_SRINV_4719 : STD_LOGIC; signal write_send_data_33_CLKINVNOT : STD_LOGIC; signal write_send_data_33_CEINV_4717 : STD_LOGIC; signal write_send_data_25_DXMUX_4782 : STD_LOGIC; signal write_send_data_mux0039 : STD_LOGIC; signal write_send_data_25_DYMUX_4768 : STD_LOGIC; signal write_send_data_mux0040 : STD_LOGIC; signal write_send_data_25_SRINV_4759 : STD_LOGIC; signal write_send_data_25_CLKINVNOT : STD_LOGIC; signal write_send_data_25_CEINV_4757 : STD_LOGIC; signal write_send_data_17_DXMUX_4824 : STD_LOGIC; signal write_send_data_index0001 : STD_LOGIC; signal write_send_data_17_DYMUX_4811 : STD_LOGIC; signal write_send_data_index0003 : STD_LOGIC; signal write_send_data_17_SRINV_4803 : STD_LOGIC; signal write_send_data_17_CLKINVNOT : STD_LOGIC; signal write_send_data_17_CEINV_4801 : STD_LOGIC; signal read_send_data_5_DXMUX_4866 : STD_LOGIC; signal read_send_data_5_mux0000 : STD_LOGIC; signal read_send_data_5_DYMUX_4852 : STD_LOGIC; signal read_send_data_4_mux0000 : STD_LOGIC; signal read_send_data_5_SRINV_4843 : STD_LOGIC; signal read_send_data_5_CLKINVNOT : STD_LOGIC; signal read_send_data_5_CEINV_4841 : STD_LOGIC; signal write_send_data_51_DXMUX_4908 : STD_LOGIC; signal write_send_data_mux0013 : STD_LOGIC; signal write_send_data_51_DYMUX_4895 : STD_LOGIC; signal write_send_data_mux0014 : STD_LOGIC; signal write_send_data_51_SRINV_4887 : STD_LOGIC; signal write_send_data_51_CLKINVNOT : STD_LOGIC; signal write_send_data_51_CEINV_4885 : STD_LOGIC; signal write_send_data_43_DXMUX_4950 : STD_LOGIC; signal write_send_data_mux0021 : STD_LOGIC; signal write_send_data_43_DYMUX_4937 : STD_LOGIC; signal write_send_data_mux0022 : STD_LOGIC; signal write_send_data_43_SRINV_4929 : STD_LOGIC; signal write_send_data_43_CLKINVNOT : STD_LOGIC; signal write_send_data_43_CEINV_4927 : STD_LOGIC; signal write_send_data_35_DXMUX_4992 : STD_LOGIC; signal write_send_data_mux0029 : STD_LOGIC; signal write_send_data_35_DYMUX_4979 : STD_LOGIC; signal write_send_data_mux0030 : STD_LOGIC; signal write_send_data_35_SRINV_4971 : STD_LOGIC; signal write_send_data_35_CLKINVNOT : STD_LOGIC; signal write_send_data_35_CEINV_4969 : STD_LOGIC; signal write_send_data_27_DXMUX_5034 : STD_LOGIC; signal write_send_data_mux0037 : STD_LOGIC; signal write_send_data_27_DYMUX_5020 : STD_LOGIC; signal write_send_data_mux0038 : STD_LOGIC; signal write_send_data_27_SRINV_5011 : STD_LOGIC; signal write_send_data_27_CLKINVNOT : STD_LOGIC; signal write_send_data_27_CEINV_5009 : STD_LOGIC; signal write_send_data_19_DXMUX_5076 : STD_LOGIC; signal write_send_data_mux0045 : STD_LOGIC; signal write_send_data_19_DYMUX_5062 : STD_LOGIC; signal write_send_data_mux0046 : STD_LOGIC; signal write_send_data_19_SRINV_5053 : STD_LOGIC; signal write_send_data_19_CLKINVNOT : STD_LOGIC; signal write_send_data_19_CEINV_5051 : STD_LOGIC; signal read_send_data_7_DXMUX_5118 : STD_LOGIC; signal read_send_data_7_mux0000 : STD_LOGIC; signal read_send_data_7_DYMUX_5104 : STD_LOGIC; signal read_send_data_6_mux0000 : STD_LOGIC; signal read_send_data_7_SRINV_5095 : STD_LOGIC; signal read_send_data_7_CLKINVNOT : STD_LOGIC; signal read_send_data_7_CEINV_5093 : STD_LOGIC; signal write_send_data_61_DXMUX_5160 : STD_LOGIC; signal write_send_data_mux0003 : STD_LOGIC; signal write_send_data_61_DYMUX_5147 : STD_LOGIC; signal write_send_data_mux0004 : STD_LOGIC; signal write_send_data_61_SRINV_5139 : STD_LOGIC; signal write_send_data_61_CLKINVNOT : STD_LOGIC; signal write_send_data_61_CEINV_5137 : STD_LOGIC; signal write_send_data_53_DXMUX_5202 : STD_LOGIC; signal write_send_data_mux0011 : STD_LOGIC; signal write_send_data_53_DYMUX_5189 : STD_LOGIC; signal write_send_data_mux0012 : STD_LOGIC; signal write_send_data_53_SRINV_5181 : STD_LOGIC; signal write_send_data_53_CLKINVNOT : STD_LOGIC; signal write_send_data_53_CEINV_5179 : STD_LOGIC; signal write_send_data_45_DXMUX_5244 : STD_LOGIC; signal write_send_data_mux0019 : STD_LOGIC; signal write_send_data_45_DYMUX_5231 : STD_LOGIC; signal write_send_data_mux0020 : STD_LOGIC; signal write_send_data_45_SRINV_5223 : STD_LOGIC; signal write_send_data_45_CLKINVNOT : STD_LOGIC; signal write_send_data_45_CEINV_5221 : STD_LOGIC; signal write_send_data_37_DXMUX_5286 : STD_LOGIC; signal write_send_data_mux0027 : STD_LOGIC; signal write_send_data_37_DYMUX_5273 : STD_LOGIC; signal write_send_data_mux0028 : STD_LOGIC; signal write_send_data_37_SRINV_5265 : STD_LOGIC; signal write_send_data_37_CLKINVNOT : STD_LOGIC; signal write_send_data_37_CEINV_5263 : STD_LOGIC; signal write_send_data_29_DXMUX_5328 : STD_LOGIC; signal write_send_data_mux0035 : STD_LOGIC; signal write_send_data_29_DYMUX_5315 : STD_LOGIC; signal write_send_data_mux0036 : STD_LOGIC; signal write_send_data_29_SRINV_5307 : STD_LOGIC; signal write_send_data_29_CLKINVNOT : STD_LOGIC; signal write_send_data_29_CEINV_5305 : STD_LOGIC; signal read_send_data_9_DXMUX_5370 : STD_LOGIC; signal read_send_data_9_mux0000 : STD_LOGIC; signal read_send_data_9_DYMUX_5356 : STD_LOGIC; signal read_send_data_8_mux0000 : STD_LOGIC; signal read_send_data_9_SRINV_5347 : STD_LOGIC; signal read_send_data_9_CLKINVNOT : STD_LOGIC; signal read_send_data_9_CEINV_5345 : STD_LOGIC; signal write_send_data_63_DXMUX_5412 : STD_LOGIC; signal write_send_data_mux0001 : STD_LOGIC; signal write_send_data_63_DYMUX_5399 : STD_LOGIC; signal write_send_data_mux0002 : STD_LOGIC; signal write_send_data_63_SRINV_5391 : STD_LOGIC; signal write_send_data_63_CLKINVNOT : STD_LOGIC; signal write_send_data_63_CEINV_5389 : STD_LOGIC; signal write_send_data_55_DXMUX_5454 : STD_LOGIC; signal write_send_data_mux0009 : STD_LOGIC; signal write_send_data_55_DYMUX_5441 : STD_LOGIC; signal write_send_data_mux0010 : STD_LOGIC; signal write_send_data_55_SRINV_5433 : STD_LOGIC; signal write_send_data_55_CLKINVNOT : STD_LOGIC; signal write_send_data_55_CEINV_5431 : STD_LOGIC; signal write_send_data_47_DXMUX_5496 : STD_LOGIC; signal write_send_data_mux0017 : STD_LOGIC; signal write_send_data_47_DYMUX_5483 : STD_LOGIC; signal write_send_data_mux0018 : STD_LOGIC; signal write_send_data_47_SRINV_5475 : STD_LOGIC; signal write_send_data_47_CLKINVNOT : STD_LOGIC; signal write_send_data_47_CEINV_5473 : STD_LOGIC; signal write_send_data_39_DXMUX_5538 : STD_LOGIC; signal write_send_data_mux0025 : STD_LOGIC; signal write_send_data_39_DYMUX_5525 : STD_LOGIC; signal write_send_data_mux0026 : STD_LOGIC; signal write_send_data_39_SRINV_5517 : STD_LOGIC; signal write_send_data_39_CLKINVNOT : STD_LOGIC; signal write_send_data_39_CEINV_5515 : STD_LOGIC; signal write_send_data_57_DXMUX_5580 : STD_LOGIC; signal write_send_data_mux0007 : STD_LOGIC; signal write_send_data_57_DYMUX_5567 : STD_LOGIC; signal write_send_data_mux0008 : STD_LOGIC; signal write_send_data_57_SRINV_5559 : STD_LOGIC; signal write_send_data_57_CLKINVNOT : STD_LOGIC; signal write_send_data_57_CEINV_5557 : STD_LOGIC; signal write_send_data_49_DXMUX_5622 : STD_LOGIC; signal write_send_data_mux0015 : STD_LOGIC; signal write_send_data_49_DYMUX_5609 : STD_LOGIC; signal write_send_data_mux0016 : STD_LOGIC; signal write_send_data_49_SRINV_5601 : STD_LOGIC; signal write_send_data_49_CLKINVNOT : STD_LOGIC; signal write_send_data_49_CEINV_5599 : STD_LOGIC; signal data_in_1_IFF_ICLK1INV_3749 : STD_LOGIC; signal data_in_1_IFF_ICEINV_3747 : STD_LOGIC; signal data_in_1_IFF_IDDRIN_MUX_3745 : STD_LOGIC; signal data_in_10_IFF_ICLK1INV_3777 : STD_LOGIC; signal data_in_10_IFF_ICEINV_3775 : STD_LOGIC; signal data_in_10_IFF_IDDRIN_MUX_3773 : STD_LOGIC; signal data_in_14_IFF_ICLK1INV_3973 : STD_LOGIC; signal data_in_14_IFF_ICEINV_3971 : STD_LOGIC; signal data_in_14_IFF_IDDRIN_MUX_3969 : STD_LOGIC; signal bit_counter_6_1_FFY_RSTAND_2168 : STD_LOGIC; signal MDC_OUTPUT_TFF_T1INV_3567 : STD_LOGIC; signal MDC_OUTPUT_TFF_TSR_USED_3570 : STD_LOGIC; signal Mtrien_MDC_3572 : STD_LOGIC; signal MDC_OUTPUT_OTCLK1INV_3563 : STD_LOGIC; signal data_in_0_IFF_ICLK1INV_3721 : STD_LOGIC; signal data_in_0_IFF_ICEINV_3719 : STD_LOGIC; signal data_in_0_IFF_IDDRIN_MUX_3717 : STD_LOGIC; signal data_in_15_IFF_ICLK1INV_4019 : STD_LOGIC; signal data_in_15_IFF_ICEINV_4017 : STD_LOGIC; signal data_in_15_IFF_IDDRIN_MUX_4015 : STD_LOGIC; signal data_in_7_IFF_ICLK1INV_4039 : STD_LOGIC; signal data_in_7_IFF_ICEINV_4037 : STD_LOGIC; signal data_in_7_IFF_IDDRIN_MUX_4035 : STD_LOGIC; signal data_in_8_IFF_ICLK1INV_4065 : STD_LOGIC; signal data_in_8_IFF_ICEINV_4063 : STD_LOGIC; signal data_in_8_IFF_IDDRIN_MUX_4061 : STD_LOGIC; signal data_in_9_IFF_ICLK1INV_4091 : STD_LOGIC; signal data_in_9_IFF_ICEINV_4089 : STD_LOGIC; signal data_in_9_IFF_IDDRIN_MUX_4087 : STD_LOGIC; signal busy_OUTPUT_OFF_ODDRIN1_MUX : STD_LOGIC; signal busy_OUTPUT_OFF_PCICE_MUX_4134 : STD_LOGIC; signal busy_OUTPUT_OFF_OSR_USED_4137 : STD_LOGIC; signal busy_OUTPUT_OFF_OREV_USED_4139 : STD_LOGIC; signal busy_in_1_4141 : STD_LOGIC; signal busy_OUTPUT_OFF_O1INV_4143 : STD_LOGIC; signal busy_OUTPUT_OTCLK1INV_4127 : STD_LOGIC; signal GND : STD_LOGIC; signal VCC : STD_LOGIC; signal bit_counter : STD_LOGIC_VECTOR ( 7 downto 0 ); signal write_send_data : STD_LOGIC_VECTOR ( 63 downto 0 ); signal latched_data : STD_LOGIC_VECTOR ( 15 downto 0 ); signal read_send_data : STD_LOGIC_VECTOR ( 45 downto 0 ); signal read_receive_data : STD_LOGIC_VECTOR ( 15 downto 0 ); signal latched_reg_addr : STD_LOGIC_VECTOR ( 4 downto 0 ); signal latched_phy_addr : STD_LOGIC_VECTOR ( 4 downto 0 ); signal counter : STD_LOGIC_VECTOR ( 7 downto 0 ); signal Mcount_bit_counter_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); signal Mcount_counter_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); begin write_send_data_59_DXMUX : X_BUF generic map( LOC => "SLICE_X19Y47", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0005, O => write_send_data_59_DXMUX_1578 ); write_send_data_59_DYMUX : X_BUF generic map( LOC => "SLICE_X19Y47", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0006, O => write_send_data_59_DYMUX_1565 ); write_send_data_59_SRINV : X_BUF generic map( LOC => "SLICE_X19Y47", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_59_SRINV_1557 ); write_send_data_59_CLKINV : X_INV generic map( LOC => "SLICE_X19Y47", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_59_CLKINVNOT ); write_send_data_59_CEINV : X_BUF generic map( LOC => "SLICE_X19Y47", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_59_CEINV_1555 ); write_send_data_0_XUSED : X_BUF generic map( LOC => "SLICE_X3Y75", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_or0000, O => read_send_data_10_or0000_0 ); write_send_data_0_DYMUX : X_BUF generic map( LOC => "SLICE_X3Y75", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0062, O => write_send_data_0_DYMUX_1607 ); write_send_data_0_SRINV : X_BUF generic map( LOC => "SLICE_X3Y75", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_0_SRINV_1599 ); write_send_data_0_CLKINV : X_INV generic map( LOC => "SLICE_X3Y75", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_0_CLKINVNOT ); write_send_data_0_CEINV : X_BUF generic map( LOC => "SLICE_X3Y75", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_0_CEINV_1597 ); write_send_data_3_DXMUX : X_BUF generic map( LOC => "SLICE_X1Y65", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0059, O => write_send_data_3_DXMUX_1656 ); write_send_data_3_DYMUX : X_BUF generic map( LOC => "SLICE_X1Y65", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0060, O => write_send_data_3_DYMUX_1642 ); write_send_data_3_SRINV : X_BUF generic map( LOC => "SLICE_X1Y65", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_3_SRINV_1633 ); write_send_data_3_CLKINV : X_INV generic map( LOC => "SLICE_X1Y65", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_3_CLKINVNOT ); write_send_data_3_CEINV : X_BUF generic map( LOC => "SLICE_X1Y65", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_3_CEINV_1631 ); write_send_data_5_DXMUX : X_BUF generic map( LOC => "SLICE_X0Y54", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0057, O => write_send_data_5_DXMUX_1698 ); write_send_data_5_DYMUX : X_BUF generic map( LOC => "SLICE_X0Y54", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0058, O => write_send_data_5_DYMUX_1684 ); write_send_data_5_SRINV : X_BUF generic map( LOC => "SLICE_X0Y54", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_5_SRINV_1675 ); write_send_data_5_CLKINV : X_INV generic map( LOC => "SLICE_X0Y54", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_5_CLKINVNOT ); write_send_data_5_CEINV : X_BUF generic map( LOC => "SLICE_X0Y54", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_5_CEINV_1673 ); write_send_data_7_DXMUX : X_BUF generic map( LOC => "SLICE_X0Y51", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0055, O => write_send_data_7_DXMUX_1740 ); write_send_data_7_DYMUX : X_BUF generic map( LOC => "SLICE_X0Y51", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0056, O => write_send_data_7_DYMUX_1726 ); write_send_data_7_SRINV : X_BUF generic map( LOC => "SLICE_X0Y51", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_7_SRINV_1717 ); write_send_data_7_CLKINV : X_INV generic map( LOC => "SLICE_X0Y51", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_7_CLKINVNOT ); write_send_data_7_CEINV : X_BUF generic map( LOC => "SLICE_X0Y51", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_7_CEINV_1715 ); write_send_data_9_DXMUX : X_BUF generic map( LOC => "SLICE_X0Y48", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0053, O => write_send_data_9_DXMUX_1782 ); write_send_data_9_DYMUX : X_BUF generic map( LOC => "SLICE_X0Y48", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0054, O => write_send_data_9_DYMUX_1768 ); write_send_data_9_SRINV : X_BUF generic map( LOC => "SLICE_X0Y48", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_9_SRINV_1759 ); write_send_data_9_CLKINV : X_INV generic map( LOC => "SLICE_X0Y48", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_9_CLKINVNOT ); write_send_data_9_CEINV : X_BUF generic map( LOC => "SLICE_X0Y48", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_9_CEINV_1757 ); Mtridata_MDIO_DYMUX : X_BUF generic map( LOC => "SLICE_X2Y56", PATHPULSE => 638 ps ) port map ( I => Mtridata_MDIO_mux0000, O => Mtridata_MDIO_DYMUX_1805 ); Mtridata_MDIO_CLKINV : X_BUF generic map( LOC => "SLICE_X2Y56", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => Mtridata_MDIO_CLKINV_1797 ); Mtrien_MDIO_XUSED : X_BUF generic map( LOC => "SLICE_X3Y57", PATHPULSE => 638 ps ) port map ( I => read_send_data_0_not0001, O => read_send_data_0_not0001_0 ); Mtrien_MDIO_DYMUX : X_BUF generic map( LOC => "SLICE_X3Y57", PATHPULSE => 638 ps ) port map ( I => Mtrien_MDIO_mux0000_norst_1836, O => Mtrien_MDIO_DYMUX_1839 ); Mtrien_MDIO_SRINV : X_BUF generic map( LOC => "SLICE_X3Y57", PATHPULSE => 638 ps ) port map ( I => Mtridata_MDIO_and0000, O => Mtrien_MDIO_SRINV_1831 ); Mtrien_MDIO_CLKINV : X_BUF generic map( LOC => "SLICE_X3Y57", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => Mtrien_MDIO_CLKINV_1830 ); read_receive_data_7_DXMUX : X_BUF generic map( LOC => "SLICE_X2Y80", PATHPULSE => 638 ps ) port map ( I => read_receive_data(6), O => read_receive_data_7_DXMUX_1869 ); read_receive_data_7_DYMUX : X_BUF generic map( LOC => "SLICE_X2Y80", PATHPULSE => 638 ps ) port map ( I => read_receive_data(5), O => read_receive_data_7_DYMUX_1862 ); read_receive_data_7_SRINV : X_BUF generic map( LOC => "SLICE_X2Y80", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_receive_data_7_SRINV_1860 ); read_receive_data_7_CLKINV : X_BUF generic map( LOC => "SLICE_X2Y80", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_receive_data_7_CLKINV_1859 ); read_receive_data_7_CEINV : X_BUF generic map( LOC => "SLICE_X2Y80", PATHPULSE => 638 ps ) port map ( I => read_receive_data_0_and0000_0, O => read_receive_data_7_CEINV_1858 ); read_receive_data_9 : X_SFF generic map( LOC => "SLICE_X2Y77", INIT => '0' ) port map ( I => read_receive_data_9_DXMUX_1893, CE => read_receive_data_9_CEINV_1882, CLK => read_receive_data_9_CLKINV_1883, SET => GND, RST => GND, SSET => GND, SRST => read_receive_data_9_SRINV_1884, O => read_receive_data(9) ); read_receive_data_9_DXMUX : X_BUF generic map( LOC => "SLICE_X2Y77", PATHPULSE => 638 ps ) port map ( I => read_receive_data(8), O => read_receive_data_9_DXMUX_1893 ); read_receive_data_9_DYMUX : X_BUF generic map( LOC => "SLICE_X2Y77", PATHPULSE => 638 ps ) port map ( I => read_receive_data(7), O => read_receive_data_9_DYMUX_1886 ); read_receive_data_9_SRINV : X_BUF generic map( LOC => "SLICE_X2Y77", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_receive_data_9_SRINV_1884 ); read_receive_data_9_CLKINV : X_BUF generic map( LOC => "SLICE_X2Y77", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_receive_data_9_CLKINV_1883 ); read_receive_data_9_CEINV : X_BUF generic map( LOC => "SLICE_X2Y77", PATHPULSE => 638 ps ) port map ( I => read_receive_data_0_and0000_0, O => read_receive_data_9_CEINV_1882 ); latched_reg_addr_0 : X_FF generic map( LOC => "SLICE_X3Y15", INIT => '0' ) port map ( I => latched_reg_addr_1_DYMUX_1908, CE => latched_reg_addr_1_CEINV_1905, CLK => latched_reg_addr_1_CLKINV_1906, SET => GND, RST => GND, O => latched_reg_addr(0) ); latched_reg_addr_1 : X_FF generic map( LOC => "SLICE_X3Y15", INIT => '0' ) port map ( I => latched_reg_addr_1_DXMUX_1914, CE => latched_reg_addr_1_CEINV_1905, CLK => latched_reg_addr_1_CLKINV_1906, SET => GND, RST => GND, O => latched_reg_addr(1) ); latched_reg_addr_1_DXMUX : X_BUF generic map( LOC => "SLICE_X3Y15", PATHPULSE => 638 ps ) port map ( I => reg_addr_1_IBUF_1360, O => latched_reg_addr_1_DXMUX_1914 ); latched_reg_addr_1_DYMUX : X_BUF generic map( LOC => "SLICE_X3Y15", PATHPULSE => 638 ps ) port map ( I => reg_addr_0_IBUF_1361, O => latched_reg_addr_1_DYMUX_1908 ); latched_reg_addr_1_CLKINV : X_BUF generic map( LOC => "SLICE_X3Y15", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => latched_reg_addr_1_CLKINV_1906 ); latched_reg_addr_1_CEINV : X_BUF generic map( LOC => "SLICE_X3Y15", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => latched_reg_addr_1_CEINV_1905 ); latched_reg_addr_2 : X_FF generic map( LOC => "SLICE_X3Y8", INIT => '0' ) port map ( I => latched_reg_addr_3_DYMUX_1928, CE => latched_reg_addr_3_CEINV_1925, CLK => latched_reg_addr_3_CLKINV_1926, SET => GND, RST => GND, O => latched_reg_addr(2) ); latched_reg_addr_3_DXMUX : X_BUF generic map( LOC => "SLICE_X3Y8", PATHPULSE => 638 ps ) port map ( I => reg_addr_3_IBUF_1365, O => latched_reg_addr_3_DXMUX_1934 ); latched_reg_addr_3_DYMUX : X_BUF generic map( LOC => "SLICE_X3Y8", PATHPULSE => 638 ps ) port map ( I => reg_addr_2_IBUF_1366, O => latched_reg_addr_3_DYMUX_1928 ); latched_reg_addr_3_CLKINV : X_BUF generic map( LOC => "SLICE_X3Y8", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => latched_reg_addr_3_CLKINV_1926 ); latched_reg_addr_3_CEINV : X_BUF generic map( LOC => "SLICE_X3Y8", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => latched_reg_addr_3_CEINV_1925 ); latched_reg_addr_4_DYMUX : X_BUF generic map( LOC => "SLICE_X13Y8", PATHPULSE => 638 ps ) port map ( I => reg_addr_4_IBUF_1369, O => latched_reg_addr_4_DYMUX_1946 ); latched_reg_addr_4_CLKINV : X_BUF generic map( LOC => "SLICE_X13Y8", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => latched_reg_addr_4_CLKINV_1944 ); latched_reg_addr_4_CEINV : X_BUF generic map( LOC => "SLICE_X13Y8", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => latched_reg_addr_4_CEINV_1943 ); read_receive_data_0_cmp_gt000011_XUSED : X_BUF generic map( LOC => "SLICE_X14Y81", PATHPULSE => 638 ps ) port map ( I => read_receive_data_0_cmp_gt000011, O => read_receive_data_0_cmp_gt000011_0 ); read_receive_data_0_cmp_gt000011_YUSED : X_BUF generic map( LOC => "SLICE_X14Y81", PATHPULSE => 638 ps ) port map ( I => read_send_data_0_cmp_lt0000112_1965, O => read_send_data_0_cmp_lt0000112_0 ); read_send_data_0_cmp_lt0000112 : X_LUT4 generic map( INIT => X"7FFF", LOC => "SLICE_X14Y81" ) port map ( ADR0 => bit_counter(2), ADR1 => bit_counter(1), ADR2 => bit_counter(3), ADR3 => bit_counter(0), O => read_send_data_0_cmp_lt0000112_1965 ); N6_XUSED : X_BUF generic map( LOC => "SLICE_X3Y65", PATHPULSE => 638 ps ) port map ( I => N6, O => N6_0 ); N6_YUSED : X_BUF generic map( LOC => "SLICE_X3Y65", PATHPULSE => 638 ps ) port map ( I => read_send_data_0_cmp_lt0000134_1989, O => read_send_data_0_cmp_lt0000134_0 ); N10_XUSED : X_BUF generic map( LOC => "SLICE_X13Y78", PATHPULSE => 638 ps ) port map ( I => N10, O => N10_0 ); N10_YUSED : X_BUF generic map( LOC => "SLICE_X13Y78", PATHPULSE => 638 ps ) port map ( I => N8, O => N8_0 ); N20_XUSED : X_BUF generic map( LOC => "SLICE_X21Y78", PATHPULSE => 638 ps ) port map ( I => N20, O => N20_0 ); N20_YUSED : X_BUF generic map( LOC => "SLICE_X21Y78", PATHPULSE => 638 ps ) port map ( I => N4, O => N4_0 ); latched_phy_addr_1_DXMUX : X_BUF generic map( LOC => "SLICE_X12Y15", PATHPULSE => 638 ps ) port map ( I => phy_addr_1_IBUF_1386, O => latched_phy_addr_1_DXMUX_2062 ); latched_phy_addr_1_DYMUX : X_BUF generic map( LOC => "SLICE_X12Y15", PATHPULSE => 638 ps ) port map ( I => phy_addr_0_IBUF_1387, O => latched_phy_addr_1_DYMUX_2056 ); latched_phy_addr_1_CLKINV : X_BUF generic map( LOC => "SLICE_X12Y15", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => latched_phy_addr_1_CLKINV_2054 ); latched_phy_addr_1_CEINV : X_BUF generic map( LOC => "SLICE_X12Y15", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => latched_phy_addr_1_CEINV_2053 ); latched_phy_addr_3_DXMUX : X_BUF generic map( LOC => "SLICE_X13Y16", PATHPULSE => 638 ps ) port map ( I => phy_addr_3_IBUF_1390, O => latched_phy_addr_3_DXMUX_2082 ); latched_phy_addr_3_DYMUX : X_BUF generic map( LOC => "SLICE_X13Y16", PATHPULSE => 638 ps ) port map ( I => phy_addr_2_IBUF_1391, O => latched_phy_addr_3_DYMUX_2076 ); latched_phy_addr_3_CLKINV : X_BUF generic map( LOC => "SLICE_X13Y16", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => latched_phy_addr_3_CLKINV_2074 ); latched_phy_addr_3_CEINV : X_BUF generic map( LOC => "SLICE_X13Y16", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => latched_phy_addr_3_CEINV_2073 ); latched_phy_addr_4_DYMUX : X_BUF generic map( LOC => "SLICE_X16Y14", PATHPULSE => 638 ps ) port map ( I => phy_addr_4_IBUF_1394, O => latched_phy_addr_4_DYMUX_2094 ); latched_phy_addr_4_CLKINV : X_BUF generic map( LOC => "SLICE_X16Y14", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => latched_phy_addr_4_CLKINV_2092 ); latched_phy_addr_4_CEINV : X_BUF generic map( LOC => "SLICE_X16Y14", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => latched_phy_addr_4_CEINV_2091 ); Mtridata_MDC_DYMUX : X_BUF generic map( LOC => "SLICE_X12Y91", PATHPULSE => 638 ps ) port map ( I => clk_div1, O => Mtridata_MDC_DYMUX_2104 ); Mtridata_MDC_CLKINV : X_BUF generic map( LOC => "SLICE_X12Y91", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => Mtridata_MDC_CLKINV_2102 ); read_receive_data_11_DXMUX : X_BUF generic map( LOC => "SLICE_X2Y73", PATHPULSE => 638 ps ) port map ( I => read_receive_data(10), O => read_receive_data_11_DXMUX_2126 ); read_receive_data_11_DYMUX : X_BUF generic map( LOC => "SLICE_X2Y73", PATHPULSE => 638 ps ) port map ( I => read_receive_data(9), O => read_receive_data_11_DYMUX_2119 ); read_receive_data_11_SRINV : X_BUF generic map( LOC => "SLICE_X2Y73", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_receive_data_11_SRINV_2117 ); read_receive_data_11_CLKINV : X_BUF generic map( LOC => "SLICE_X2Y73", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_receive_data_11_CLKINV_2116 ); read_receive_data_11_CEINV : X_BUF generic map( LOC => "SLICE_X2Y73", PATHPULSE => 638 ps ) port map ( I => read_receive_data_0_and0000_0, O => read_receive_data_11_CEINV_2115 ); read_receive_data_13_DXMUX : X_BUF generic map( LOC => "SLICE_X3Y73", PATHPULSE => 638 ps ) port map ( I => read_receive_data(12), O => read_receive_data_13_DXMUX_2150 ); read_receive_data_13_DYMUX : X_BUF generic map( LOC => "SLICE_X3Y73", PATHPULSE => 638 ps ) port map ( I => read_receive_data(11), O => read_receive_data_13_DYMUX_2143 ); read_receive_data_13_SRINV : X_BUF generic map( LOC => "SLICE_X3Y73", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_receive_data_13_SRINV_2141 ); read_receive_data_13_CLKINV : X_BUF generic map( LOC => "SLICE_X3Y73", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_receive_data_13_CLKINV_2140 ); read_receive_data_13_CEINV : X_BUF generic map( LOC => "SLICE_X3Y73", PATHPULSE => 638 ps ) port map ( I => read_receive_data_0_and0000_0, O => read_receive_data_13_CEINV_2139 ); bit_counter_6_1_DYMUX : X_BUF generic map( LOC => "SLICE_X14Y80", PATHPULSE => 638 ps ) port map ( I => bit_counter_6_FXMUX_3304, O => bit_counter_6_1_DYMUX_2163 ); bit_counter_6_1_CLKINV : X_INV generic map( LOC => "SLICE_X14Y80", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => bit_counter_6_1_CLKINVNOT ); read_receive_data_15_DXMUX : X_BUF generic map( LOC => "SLICE_X3Y72", PATHPULSE => 638 ps ) port map ( I => read_receive_data(14), O => read_receive_data_15_DXMUX_2188 ); read_receive_data_15_DYMUX : X_BUF generic map( LOC => "SLICE_X3Y72", PATHPULSE => 638 ps ) port map ( I => read_receive_data(13), O => read_receive_data_15_DYMUX_2181 ); read_receive_data_15_SRINV : X_BUF generic map( LOC => "SLICE_X3Y72", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_receive_data_15_SRINV_2179 ); read_receive_data_15_CLKINV : X_BUF generic map( LOC => "SLICE_X3Y72", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_receive_data_15_CLKINV_2178 ); read_receive_data_15_CEINV : X_BUF generic map( LOC => "SLICE_X3Y72", PATHPULSE => 638 ps ) port map ( I => read_receive_data_0_and0000_0, O => read_receive_data_15_CEINV_2177 ); write_send_data_1_DXMUX : X_BUF generic map( LOC => "SLICE_X13Y72", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0061, O => write_send_data_1_DXMUX_2224 ); write_send_data_1_YUSED : X_BUF generic map( LOC => "SLICE_X13Y72", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv_pack_1, O => read_send_data_11_not0001_inv ); write_send_data_1_SRINV : X_BUF generic map( LOC => "SLICE_X13Y72", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_1_SRINV_2207 ); write_send_data_1_CLKINV : X_INV generic map( LOC => "SLICE_X13Y72", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_1_CLKINVNOT ); write_send_data_1_CEINV : X_BUF generic map( LOC => "SLICE_X13Y72", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_1_CEINV_2205 ); clk_div1_DYMUX : X_INV generic map( LOC => "SLICE_X45Y84", PATHPULSE => 638 ps ) port map ( I => clk_div1, O => clk_div1_DYMUX_2239 ); clk_div1_SRINV : X_BUF generic map( LOC => "SLICE_X45Y84", PATHPULSE => 638 ps ) port map ( I => clk_div_or0000, O => clk_div1_SRINV_2237 ); clk_div1_CLKINV : X_BUF generic map( LOC => "SLICE_X45Y84", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => clk_div1_CLKINV_2236 ); clk_div1_CEINV : X_BUF generic map( LOC => "SLICE_X45Y84", PATHPULSE => 638 ps ) port map ( I => clk_div_not0002, O => clk_div1_CEINV_2235 ); clk_div_or0000_YUSED : X_BUF generic map( LOC => "SLICE_X25Y79", PATHPULSE => 638 ps ) port map ( I => busy_in_cmp_eq0000_pack_1, O => busy_in_cmp_eq0000_1409 ); read_send_data_10_DYMUX : X_BUF generic map( LOC => "SLICE_X3Y67", PATHPULSE => 638 ps ) port map ( I => read_send_data(9), O => read_send_data_10_DYMUX_2278 ); read_send_data_10_SRINV : X_BUF generic map( LOC => "SLICE_X3Y67", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_or0000_0, O => read_send_data_10_SRINV_2276 ); read_send_data_10_CLKINV : X_INV generic map( LOC => "SLICE_X3Y67", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_10_CLKINVNOT ); read_send_data_10_CEINV : X_BUF generic map( LOC => "SLICE_X3Y67", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_10_CEINV_2274 ); read_send_data_11_DXMUX : X_BUF generic map( LOC => "SLICE_X2Y67", PATHPULSE => 638 ps ) port map ( I => read_send_data(10), O => read_send_data_11_DXMUX_2296 ); read_send_data_11_REVUSED : X_BUF generic map( LOC => "SLICE_X2Y67", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_11_REVUSED_2294 ); read_send_data_11_SRINV : X_BUF generic map( LOC => "SLICE_X2Y67", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_11_SRINV_2292 ); read_send_data_11_CLKINV : X_INV generic map( LOC => "SLICE_X2Y67", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_11_CLKINVNOT ); read_send_data_11_CEINV : X_BUF generic map( LOC => "SLICE_X2Y67", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_11_CEINV_2290 ); read_send_data_21_DXMUX : X_BUF generic map( LOC => "SLICE_X24Y77", PATHPULSE => 638 ps ) port map ( I => read_send_data(20), O => read_send_data_21_DXMUX_2334 ); read_send_data_21_REVUSED : X_BUF generic map( LOC => "SLICE_X24Y77", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_21_REVUSED_2326 ); read_send_data_21_DYMUX : X_BUF generic map( LOC => "SLICE_X24Y77", PATHPULSE => 638 ps ) port map ( I => read_send_data_19_rt_2322, O => read_send_data_21_DYMUX_2325 ); read_send_data_21_SRINV : X_BUF generic map( LOC => "SLICE_X24Y77", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_21_SRINV_2313 ); read_send_data_21_CLKINV : X_INV generic map( LOC => "SLICE_X24Y77", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_21_CLKINVNOT ); read_send_data_21_CEINV : X_BUF generic map( LOC => "SLICE_X24Y77", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_21_CEINV_2311 ); read_send_data_12_DXMUX : X_BUF generic map( LOC => "SLICE_X3Y71", PATHPULSE => 638 ps ) port map ( I => read_send_data(11), O => read_send_data_12_DXMUX_2353 ); read_send_data_12_REVUSED : X_BUF generic map( LOC => "SLICE_X3Y71", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_12_REVUSED_2351 ); read_send_data_12_SRINV : X_BUF generic map( LOC => "SLICE_X3Y71", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_12_SRINV_2349 ); read_send_data_12_CLKINV : X_INV generic map( LOC => "SLICE_X3Y71", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_12_CLKINVNOT ); read_send_data_12_CEINV : X_BUF generic map( LOC => "SLICE_X3Y71", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_12_CEINV_2347 ); read_send_data_13_DYMUX : X_BUF generic map( LOC => "SLICE_X5Y88", PATHPULSE => 638 ps ) port map ( I => read_send_data(12), O => read_send_data_13_DYMUX_2369 ); read_send_data_13_SRINV : X_BUF generic map( LOC => "SLICE_X5Y88", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_or0000_0, O => read_send_data_13_SRINV_2367 ); read_send_data_13_CLKINV : X_INV generic map( LOC => "SLICE_X5Y88", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_13_CLKINVNOT ); read_send_data_13_CEINV : X_BUF generic map( LOC => "SLICE_X5Y88", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_13_CEINV_2365 ); read_send_data_31_DXMUX : X_BUF generic map( LOC => "SLICE_X25Y69", PATHPULSE => 638 ps ) port map ( I => read_send_data(30), O => read_send_data_31_DXMUX_2406 ); read_send_data_31_REVUSED : X_BUF generic map( LOC => "SLICE_X25Y69", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_31_REVUSED_2398 ); read_send_data_31_DYMUX : X_BUF generic map( LOC => "SLICE_X25Y69", PATHPULSE => 638 ps ) port map ( I => read_send_data_29_rt_2394, O => read_send_data_31_DYMUX_2397 ); read_send_data_31_SRINV : X_BUF generic map( LOC => "SLICE_X25Y69", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_31_SRINV_2385 ); read_send_data_31_CLKINV : X_INV generic map( LOC => "SLICE_X25Y69", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_31_CLKINVNOT ); read_send_data_31_CEINV : X_BUF generic map( LOC => "SLICE_X25Y69", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_31_CEINV_2383 ); read_send_data_23_DXMUX : X_BUF generic map( LOC => "SLICE_X26Y75", PATHPULSE => 638 ps ) port map ( I => read_send_data(22), O => read_send_data_23_DXMUX_2444 ); read_send_data_23_REVUSED : X_BUF generic map( LOC => "SLICE_X26Y75", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_23_REVUSED_2436 ); read_send_data_23_DYMUX : X_BUF generic map( LOC => "SLICE_X26Y75", PATHPULSE => 638 ps ) port map ( I => read_send_data_21_rt_2432, O => read_send_data_23_DYMUX_2435 ); read_send_data_23_SRINV : X_BUF generic map( LOC => "SLICE_X26Y75", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_23_SRINV_2423 ); read_send_data_23_CLKINV : X_INV generic map( LOC => "SLICE_X26Y75", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_23_CLKINVNOT ); read_send_data_23_CEINV : X_BUF generic map( LOC => "SLICE_X26Y75", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_23_CEINV_2421 ); read_send_data_15_DXMUX : X_BUF generic map( LOC => "SLICE_X14Y86", PATHPULSE => 638 ps ) port map ( I => read_send_data(14), O => read_send_data_15_DXMUX_2482 ); read_send_data_15_REVUSED : X_BUF generic map( LOC => "SLICE_X14Y86", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_15_REVUSED_2474 ); read_send_data_15_DYMUX : X_BUF generic map( LOC => "SLICE_X14Y86", PATHPULSE => 638 ps ) port map ( I => read_send_data_13_rt_2470, O => read_send_data_15_DYMUX_2473 ); read_send_data_15_SRINV : X_BUF generic map( LOC => "SLICE_X14Y86", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_15_SRINV_2461 ); read_send_data_15_CLKINV : X_INV generic map( LOC => "SLICE_X14Y86", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_15_CLKINVNOT ); read_send_data_15_CEINV : X_BUF generic map( LOC => "SLICE_X14Y86", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_15_CEINV_2459 ); latched_write_read_DYMUX : X_BUF generic map( LOC => "SLICE_X2Y51", PATHPULSE => 638 ps ) port map ( I => write_read_INBUF, O => latched_write_read_DYMUX_2496 ); latched_write_read_CLKINV : X_BUF generic map( LOC => "SLICE_X2Y51", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => latched_write_read_CLKINV_2494 ); latched_write_read_CEINV : X_BUF generic map( LOC => "SLICE_X2Y51", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => latched_write_read_CEINV_2493 ); read_send_data_41_DXMUX : X_BUF generic map( LOC => "SLICE_X17Y56", PATHPULSE => 638 ps ) port map ( I => read_send_data(40), O => read_send_data_41_DXMUX_2532 ); read_send_data_41_REVUSED : X_BUF generic map( LOC => "SLICE_X17Y56", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_41_REVUSED_2524 ); read_send_data_41_DYMUX : X_BUF generic map( LOC => "SLICE_X17Y56", PATHPULSE => 638 ps ) port map ( I => read_send_data_39_rt_2520, O => read_send_data_41_DYMUX_2523 ); read_send_data_41_SRINV : X_BUF generic map( LOC => "SLICE_X17Y56", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_41_SRINV_2511 ); read_send_data_41_CLKINV : X_INV generic map( LOC => "SLICE_X17Y56", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_41_CLKINVNOT ); read_send_data_41_CEINV : X_BUF generic map( LOC => "SLICE_X17Y56", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_41_CEINV_2509 ); read_send_data_33_DXMUX : X_BUF generic map( LOC => "SLICE_X24Y67", PATHPULSE => 638 ps ) port map ( I => read_send_data(32), O => read_send_data_33_DXMUX_2570 ); read_send_data_33_REVUSED : X_BUF generic map( LOC => "SLICE_X24Y67", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_33_REVUSED_2562 ); read_send_data_33_DYMUX : X_BUF generic map( LOC => "SLICE_X24Y67", PATHPULSE => 638 ps ) port map ( I => read_send_data_31_rt_2558, O => read_send_data_33_DYMUX_2561 ); read_send_data_33_SRINV : X_BUF generic map( LOC => "SLICE_X24Y67", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_33_SRINV_2549 ); read_send_data_33_CLKINV : X_INV generic map( LOC => "SLICE_X24Y67", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_33_CLKINVNOT ); read_send_data_33_CEINV : X_BUF generic map( LOC => "SLICE_X24Y67", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_33_CEINV_2547 ); read_send_data_25_DXMUX : X_BUF generic map( LOC => "SLICE_X26Y73", PATHPULSE => 638 ps ) port map ( I => read_send_data(24), O => read_send_data_25_DXMUX_2608 ); read_send_data_25_REVUSED : X_BUF generic map( LOC => "SLICE_X26Y73", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_25_REVUSED_2600 ); read_send_data_25_DYMUX : X_BUF generic map( LOC => "SLICE_X26Y73", PATHPULSE => 638 ps ) port map ( I => read_send_data_23_rt_2596, O => read_send_data_25_DYMUX_2599 ); read_send_data_25_SRINV : X_BUF generic map( LOC => "SLICE_X26Y73", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_25_SRINV_2587 ); read_send_data_25_CLKINV : X_INV generic map( LOC => "SLICE_X26Y73", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_25_CLKINVNOT ); read_send_data_25_CEINV : X_BUF generic map( LOC => "SLICE_X26Y73", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_25_CEINV_2585 ); read_send_data_17_DXMUX : X_BUF generic map( LOC => "SLICE_X16Y87", PATHPULSE => 638 ps ) port map ( I => read_send_data(16), O => read_send_data_17_DXMUX_2646 ); read_send_data_17_REVUSED : X_BUF generic map( LOC => "SLICE_X16Y87", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_17_REVUSED_2638 ); read_send_data_17_DYMUX : X_BUF generic map( LOC => "SLICE_X16Y87", PATHPULSE => 638 ps ) port map ( I => read_send_data_15_rt_2634, O => read_send_data_17_DYMUX_2637 ); read_send_data_17_SRINV : X_BUF generic map( LOC => "SLICE_X16Y87", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_17_SRINV_2625 ); read_send_data_17_CLKINV : X_INV generic map( LOC => "SLICE_X16Y87", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_17_CLKINVNOT ); read_send_data_17_CEINV : X_BUF generic map( LOC => "SLICE_X16Y87", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_17_CEINV_2623 ); read_send_data_43_DXMUX : X_BUF generic map( LOC => "SLICE_X16Y53", PATHPULSE => 638 ps ) port map ( I => read_send_data(42), O => read_send_data_43_DXMUX_2684 ); read_send_data_43_REVUSED : X_BUF generic map( LOC => "SLICE_X16Y53", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_43_REVUSED_2676 ); read_send_data_43_DYMUX : X_BUF generic map( LOC => "SLICE_X16Y53", PATHPULSE => 638 ps ) port map ( I => read_send_data_41_rt_2672, O => read_send_data_43_DYMUX_2675 ); read_send_data_43_SRINV : X_BUF generic map( LOC => "SLICE_X16Y53", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_43_SRINV_2663 ); read_send_data_43_CLKINV : X_INV generic map( LOC => "SLICE_X16Y53", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_43_CLKINVNOT ); read_send_data_43_CEINV : X_BUF generic map( LOC => "SLICE_X16Y53", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_43_CEINV_2661 ); read_send_data_35_DXMUX : X_BUF generic map( LOC => "SLICE_X20Y65", PATHPULSE => 638 ps ) port map ( I => read_send_data(34), O => read_send_data_35_DXMUX_2722 ); read_send_data_35_REVUSED : X_BUF generic map( LOC => "SLICE_X20Y65", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_35_REVUSED_2714 ); read_send_data_35_DYMUX : X_BUF generic map( LOC => "SLICE_X20Y65", PATHPULSE => 638 ps ) port map ( I => read_send_data_33_rt_2710, O => read_send_data_35_DYMUX_2713 ); read_send_data_35_SRINV : X_BUF generic map( LOC => "SLICE_X20Y65", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_35_SRINV_2701 ); read_send_data_35_CLKINV : X_INV generic map( LOC => "SLICE_X20Y65", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_35_CLKINVNOT ); read_send_data_35_CEINV : X_BUF generic map( LOC => "SLICE_X20Y65", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_35_CEINV_2699 ); read_send_data_27_DXMUX : X_BUF generic map( LOC => "SLICE_X24Y70", PATHPULSE => 638 ps ) port map ( I => read_send_data(26), O => read_send_data_27_DXMUX_2760 ); read_send_data_27_REVUSED : X_BUF generic map( LOC => "SLICE_X24Y70", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_27_REVUSED_2752 ); read_send_data_27_DYMUX : X_BUF generic map( LOC => "SLICE_X24Y70", PATHPULSE => 638 ps ) port map ( I => read_send_data_25_rt_2748, O => read_send_data_27_DYMUX_2751 ); read_send_data_27_SRINV : X_BUF generic map( LOC => "SLICE_X24Y70", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_27_SRINV_2739 ); read_send_data_27_CLKINV : X_INV generic map( LOC => "SLICE_X24Y70", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_27_CLKINVNOT ); read_send_data_27_CEINV : X_BUF generic map( LOC => "SLICE_X24Y70", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_27_CEINV_2737 ); read_send_data_19_DXMUX : X_BUF generic map( LOC => "SLICE_X19Y81", PATHPULSE => 638 ps ) port map ( I => read_send_data(18), O => read_send_data_19_DXMUX_2798 ); read_send_data_19_REVUSED : X_BUF generic map( LOC => "SLICE_X19Y81", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_19_REVUSED_2790 ); read_send_data_19_DYMUX : X_BUF generic map( LOC => "SLICE_X19Y81", PATHPULSE => 638 ps ) port map ( I => read_send_data_17_rt_2786, O => read_send_data_19_DYMUX_2789 ); read_send_data_19_SRINV : X_BUF generic map( LOC => "SLICE_X19Y81", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_19_SRINV_2777 ); read_send_data_19_CLKINV : X_INV generic map( LOC => "SLICE_X19Y81", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_19_CLKINVNOT ); read_send_data_19_CEINV : X_BUF generic map( LOC => "SLICE_X19Y81", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_19_CEINV_2775 ); read_send_data_45_DXMUX : X_BUF generic map( LOC => "SLICE_X16Y52", PATHPULSE => 638 ps ) port map ( I => read_send_data(44), O => read_send_data_45_DXMUX_2836 ); read_send_data_45_REVUSED : X_BUF generic map( LOC => "SLICE_X16Y52", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_45_REVUSED_2828 ); read_send_data_45_DYMUX : X_BUF generic map( LOC => "SLICE_X16Y52", PATHPULSE => 638 ps ) port map ( I => read_send_data_43_rt_2824, O => read_send_data_45_DYMUX_2827 ); read_send_data_45_SRINV : X_BUF generic map( LOC => "SLICE_X16Y52", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_45_SRINV_2815 ); read_send_data_45_CLKINV : X_INV generic map( LOC => "SLICE_X16Y52", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_45_CLKINVNOT ); read_send_data_45_CEINV : X_BUF generic map( LOC => "SLICE_X16Y52", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_45_CEINV_2813 ); read_send_data_37_DXMUX : X_BUF generic map( LOC => "SLICE_X18Y62", PATHPULSE => 638 ps ) port map ( I => read_send_data(36), O => read_send_data_37_DXMUX_2874 ); read_send_data_37_REVUSED : X_BUF generic map( LOC => "SLICE_X18Y62", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_37_REVUSED_2866 ); read_send_data_37_DYMUX : X_BUF generic map( LOC => "SLICE_X18Y62", PATHPULSE => 638 ps ) port map ( I => read_send_data_35_rt_2862, O => read_send_data_37_DYMUX_2865 ); read_send_data_37_SRINV : X_BUF generic map( LOC => "SLICE_X18Y62", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_37_SRINV_2853 ); read_send_data_37_CLKINV : X_INV generic map( LOC => "SLICE_X18Y62", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_37_CLKINVNOT ); read_send_data_37_CEINV : X_BUF generic map( LOC => "SLICE_X18Y62", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_37_CEINV_2851 ); read_send_data_28 : X_SFF generic map( LOC => "SLICE_X25Y70", INIT => '0' ) port map ( I => read_send_data_29_DYMUX_2903, CE => read_send_data_29_CEINV_2889, CLK => read_send_data_29_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_29_REVUSED_2904, SRST => read_send_data_29_SRINV_2891, O => read_send_data(28) ); read_send_data_29 : X_SFF generic map( LOC => "SLICE_X25Y70", INIT => '0' ) port map ( I => read_send_data_29_DXMUX_2912, CE => read_send_data_29_CEINV_2889, CLK => read_send_data_29_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_29_REVUSED_2904, SRST => read_send_data_29_SRINV_2891, O => read_send_data(29) ); read_send_data_29_DXMUX : X_BUF generic map( LOC => "SLICE_X25Y70", PATHPULSE => 638 ps ) port map ( I => read_send_data(28), O => read_send_data_29_DXMUX_2912 ); read_send_data_29_REVUSED : X_BUF generic map( LOC => "SLICE_X25Y70", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_29_REVUSED_2904 ); read_send_data_29_DYMUX : X_BUF generic map( LOC => "SLICE_X25Y70", PATHPULSE => 638 ps ) port map ( I => read_send_data_27_rt_2900, O => read_send_data_29_DYMUX_2903 ); read_send_data_29_SRINV : X_BUF generic map( LOC => "SLICE_X25Y70", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_29_SRINV_2891 ); read_send_data_29_CLKINV : X_INV generic map( LOC => "SLICE_X25Y70", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_29_CLKINVNOT ); read_send_data_29_CEINV : X_BUF generic map( LOC => "SLICE_X25Y70", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_29_CEINV_2889 ); read_send_data_37_rt : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X17Y59" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => read_send_data(37), O => read_send_data_37_rt_2938 ); read_send_data_38 : X_SFF generic map( LOC => "SLICE_X17Y59", INIT => '0' ) port map ( I => read_send_data_39_DYMUX_2941, CE => read_send_data_39_CEINV_2927, CLK => read_send_data_39_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_39_REVUSED_2942, SRST => read_send_data_39_SRINV_2929, O => read_send_data(38) ); read_send_data_39 : X_SFF generic map( LOC => "SLICE_X17Y59", INIT => '0' ) port map ( I => read_send_data_39_DXMUX_2950, CE => read_send_data_39_CEINV_2927, CLK => read_send_data_39_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_39_REVUSED_2942, SRST => read_send_data_39_SRINV_2929, O => read_send_data(39) ); read_send_data_39_DXMUX : X_BUF generic map( LOC => "SLICE_X17Y59", PATHPULSE => 638 ps ) port map ( I => read_send_data(38), O => read_send_data_39_DXMUX_2950 ); read_send_data_39_REVUSED : X_BUF generic map( LOC => "SLICE_X17Y59", PATHPULSE => 638 ps ) port map ( I => read_send_data_11_not0001_inv, O => read_send_data_39_REVUSED_2942 ); read_send_data_39_DYMUX : X_BUF generic map( LOC => "SLICE_X17Y59", PATHPULSE => 638 ps ) port map ( I => read_send_data_37_rt_2938, O => read_send_data_39_DYMUX_2941 ); read_send_data_39_SRINV : X_BUF generic map( LOC => "SLICE_X17Y59", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_39_SRINV_2929 ); read_send_data_39_CLKINV : X_INV generic map( LOC => "SLICE_X17Y59", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_39_CLKINVNOT ); read_send_data_39_CEINV : X_BUF generic map( LOC => "SLICE_X17Y59", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_0, O => read_send_data_39_CEINV_2927 ); busy_in : X_SFF generic map( LOC => "SLICE_X46Y82", INIT => '0' ) port map ( I => busy_in_DXMUX_2969, CE => busy_in_CEINV_2963, CLK => busy_in_CLKINV_2964, SET => GND, RST => GND, SSET => busy_in_REVUSED_2967, SRST => busy_in_SRINV_2965, O => busy_in_1448 ); busy_in_DXMUX : X_BUF generic map( LOC => "SLICE_X46Y82", PATHPULSE => 638 ps ) port map ( I => busy_in_BXINV_2968, O => busy_in_DXMUX_2969 ); busy_in_BXINV : X_BUF generic map( LOC => "SLICE_X46Y82", PATHPULSE => 638 ps ) port map ( I => '0', O => busy_in_BXINV_2968 ); busy_in_REVUSED : X_BUF generic map( LOC => "SLICE_X46Y82", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => busy_in_REVUSED_2967 ); busy_in_SRINV : X_BUF generic map( LOC => "SLICE_X46Y82", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => busy_in_SRINV_2965 ); busy_in_CLKINV : X_BUF generic map( LOC => "SLICE_X46Y82", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => busy_in_CLKINV_2964 ); busy_in_CEINV : X_BUF generic map( LOC => "SLICE_X46Y82", PATHPULSE => 638 ps ) port map ( I => busy_in_cmp_eq0000_1409, O => busy_in_CEINV_2963 ); counter_cmp_eq000010 : X_LUT4 generic map( INIT => X"0020", LOC => "SLICE_X48Y82" ) port map ( ADR0 => counter(0), ADR1 => counter(2), ADR2 => counter(3), ADR3 => counter(1), O => counter_cmp_eq000010_2985 ); counter_cmp_eq000010_XUSED : X_BUF generic map( LOC => "SLICE_X48Y82", PATHPULSE => 638 ps ) port map ( I => counter_cmp_eq000010_2985, O => counter_cmp_eq000010_0 ); read_receive_data_0 : X_SFF generic map( LOC => "SLICE_X1Y84", INIT => '0' ) port map ( I => read_receive_data_1_DYMUX_2999, CE => read_receive_data_1_CEINV_2995, CLK => read_receive_data_1_CLKINV_2996, SET => GND, RST => GND, SSET => GND, SRST => read_receive_data_1_SRINV_2997, O => read_receive_data(0) ); read_receive_data_1 : X_SFF generic map( LOC => "SLICE_X1Y84", INIT => '0' ) port map ( I => read_receive_data_1_DXMUX_3006, CE => read_receive_data_1_CEINV_2995, CLK => read_receive_data_1_CLKINV_2996, SET => GND, RST => GND, SSET => GND, SRST => read_receive_data_1_SRINV_2997, O => read_receive_data(1) ); read_receive_data_1_DXMUX : X_BUF generic map( LOC => "SLICE_X1Y84", PATHPULSE => 638 ps ) port map ( I => read_receive_data(0), O => read_receive_data_1_DXMUX_3006 ); read_receive_data_1_DYMUX : X_BUF generic map( LOC => "SLICE_X1Y84", PATHPULSE => 638 ps ) port map ( I => MDIO_INBUF, O => read_receive_data_1_DYMUX_2999 ); read_receive_data_1_SRINV : X_BUF generic map( LOC => "SLICE_X1Y84", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_receive_data_1_SRINV_2997 ); read_receive_data_1_CLKINV : X_BUF generic map( LOC => "SLICE_X1Y84", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_receive_data_1_CLKINV_2996 ); read_receive_data_1_CEINV : X_BUF generic map( LOC => "SLICE_X1Y84", PATHPULSE => 638 ps ) port map ( I => read_receive_data_0_and0000_0, O => read_receive_data_1_CEINV_2995 ); N18_XUSED : X_BUF generic map( LOC => "SLICE_X12Y80", PATHPULSE => 638 ps ) port map ( I => N18, O => N18_0 ); read_receive_data_3_DXMUX : X_BUF generic map( LOC => "SLICE_X0Y85", PATHPULSE => 638 ps ) port map ( I => read_receive_data(2), O => read_receive_data_3_DXMUX_3042 ); read_receive_data_3_DYMUX : X_BUF generic map( LOC => "SLICE_X0Y85", PATHPULSE => 638 ps ) port map ( I => read_receive_data(1), O => read_receive_data_3_DYMUX_3035 ); read_receive_data_3_SRINV : X_BUF generic map( LOC => "SLICE_X0Y85", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_receive_data_3_SRINV_3033 ); read_receive_data_3_CLKINV : X_BUF generic map( LOC => "SLICE_X0Y85", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_receive_data_3_CLKINV_3032 ); read_receive_data_3_CEINV : X_BUF generic map( LOC => "SLICE_X0Y85", PATHPULSE => 638 ps ) port map ( I => read_receive_data_0_and0000_0, O => read_receive_data_3_CEINV_3031 ); clk_div_not0002_YUSED : X_BUF generic map( LOC => "SLICE_X48Y85", PATHPULSE => 638 ps ) port map ( I => counter_cmp_eq000023_pack_1, O => counter_cmp_eq000023_1460 ); read_receive_data_5_DXMUX : X_BUF generic map( LOC => "SLICE_X3Y83", PATHPULSE => 638 ps ) port map ( I => read_receive_data(4), O => read_receive_data_5_DXMUX_3090 ); read_receive_data_5_DYMUX : X_BUF generic map( LOC => "SLICE_X3Y83", PATHPULSE => 638 ps ) port map ( I => read_receive_data(3), O => read_receive_data_5_DYMUX_3083 ); read_receive_data_5_SRINV : X_BUF generic map( LOC => "SLICE_X3Y83", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_receive_data_5_SRINV_3081 ); read_receive_data_5_CLKINV : X_BUF generic map( LOC => "SLICE_X3Y83", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_receive_data_5_CLKINV_3080 ); read_receive_data_5_CEINV : X_BUF generic map( LOC => "SLICE_X3Y83", PATHPULSE => 638 ps ) port map ( I => read_receive_data_0_and0000_0, O => read_receive_data_5_CEINV_3079 ); bit_counter_0_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X15Y78" ) port map ( O => bit_counter_0_LOGIC_ZERO_3116 ); bit_counter_0_LOGIC_ONE : X_ONE generic map( LOC => "SLICE_X15Y78" ) port map ( O => bit_counter_0_LOGIC_ONE_3140 ); bit_counter_0_DXMUX : X_BUF generic map( LOC => "SLICE_X15Y78", PATHPULSE => 638 ps ) port map ( I => bit_counter_0_XORF_3141, O => bit_counter_0_DXMUX_3143 ); bit_counter_0_XORF : X_XOR2 generic map( LOC => "SLICE_X15Y78" ) port map ( I0 => bit_counter_0_CYINIT_3139, I1 => Mcount_bit_counter_lut(0), O => bit_counter_0_XORF_3141 ); bit_counter_0_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X15Y78" ) port map ( IA => bit_counter_0_LOGIC_ONE_3140, IB => bit_counter_0_CYINIT_3139, SEL => bit_counter_0_CYSELF_3130, O => Mcount_bit_counter_cy_0_Q ); bit_counter_0_CYINIT : X_BUF generic map( LOC => "SLICE_X15Y78", PATHPULSE => 638 ps ) port map ( I => bit_counter_0_BXINV_3128, O => bit_counter_0_CYINIT_3139 ); bit_counter_0_CYSELF : X_BUF generic map( LOC => "SLICE_X15Y78", PATHPULSE => 638 ps ) port map ( I => Mcount_bit_counter_lut(0), O => bit_counter_0_CYSELF_3130 ); bit_counter_0_BXINV : X_BUF generic map( LOC => "SLICE_X15Y78", PATHPULSE => 638 ps ) port map ( I => '0', O => bit_counter_0_BXINV_3128 ); bit_counter_0_DYMUX : X_BUF generic map( LOC => "SLICE_X15Y78", PATHPULSE => 638 ps ) port map ( I => bit_counter_0_XORG_3119, O => bit_counter_0_DYMUX_3121 ); bit_counter_0_XORG : X_XOR2 generic map( LOC => "SLICE_X15Y78" ) port map ( I0 => Mcount_bit_counter_cy_0_Q, I1 => bit_counter_0_G, O => bit_counter_0_XORG_3119 ); bit_counter_0_COUTUSED : X_BUF generic map( LOC => "SLICE_X15Y78", PATHPULSE => 638 ps ) port map ( I => bit_counter_0_CYMUXG_3118, O => Mcount_bit_counter_cy_1_Q ); bit_counter_0_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X15Y78" ) port map ( IA => bit_counter_0_LOGIC_ZERO_3116, IB => Mcount_bit_counter_cy_0_Q, SEL => bit_counter_0_CYSELG_3107, O => bit_counter_0_CYMUXG_3118 ); bit_counter_0_CYSELG : X_BUF generic map( LOC => "SLICE_X15Y78", PATHPULSE => 638 ps ) port map ( I => bit_counter_0_G, O => bit_counter_0_CYSELG_3107 ); bit_counter_0_SRINV : X_BUF generic map( LOC => "SLICE_X15Y78", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => bit_counter_0_SRINV_3105 ); bit_counter_0_CLKINV : X_INV generic map( LOC => "SLICE_X15Y78", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => bit_counter_0_CLKINVNOT ); bit_counter_2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X15Y79" ) port map ( O => bit_counter_2_LOGIC_ZERO_3170 ); bit_counter_2_DXMUX : X_BUF generic map( LOC => "SLICE_X15Y79", PATHPULSE => 638 ps ) port map ( I => bit_counter_2_XORF_3197, O => bit_counter_2_DXMUX_3199 ); bit_counter_2_XORF : X_XOR2 generic map( LOC => "SLICE_X15Y79" ) port map ( I0 => bit_counter_2_CYINIT_3196, I1 => bit_counter_2_F, O => bit_counter_2_XORF_3197 ); bit_counter_2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X15Y79" ) port map ( IA => bit_counter_2_LOGIC_ZERO_3170, IB => bit_counter_2_CYINIT_3196, SEL => bit_counter_2_CYSELF_3176, O => Mcount_bit_counter_cy_2_Q ); bit_counter_2_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X15Y79" ) port map ( IA => bit_counter_2_LOGIC_ZERO_3170, IB => bit_counter_2_LOGIC_ZERO_3170, SEL => bit_counter_2_CYSELF_3176, O => bit_counter_2_CYMUXF2_3171 ); bit_counter_2_CYINIT : X_BUF generic map( LOC => "SLICE_X15Y79", PATHPULSE => 638 ps ) port map ( I => Mcount_bit_counter_cy_1_Q, O => bit_counter_2_CYINIT_3196 ); bit_counter_2_CYSELF : X_BUF generic map( LOC => "SLICE_X15Y79", PATHPULSE => 638 ps ) port map ( I => bit_counter_2_F, O => bit_counter_2_CYSELF_3176 ); bit_counter_2_DYMUX : X_BUF generic map( LOC => "SLICE_X15Y79", PATHPULSE => 638 ps ) port map ( I => bit_counter_2_XORG_3178, O => bit_counter_2_DYMUX_3180 ); bit_counter_2_XORG : X_XOR2 generic map( LOC => "SLICE_X15Y79" ) port map ( I0 => Mcount_bit_counter_cy_2_Q, I1 => bit_counter_2_G, O => bit_counter_2_XORG_3178 ); bit_counter_2_COUTUSED : X_BUF generic map( LOC => "SLICE_X15Y79", PATHPULSE => 638 ps ) port map ( I => bit_counter_2_CYMUXFAST_3175, O => Mcount_bit_counter_cy_3_Q ); bit_counter_2_FASTCARRY : X_BUF generic map( LOC => "SLICE_X15Y79", PATHPULSE => 638 ps ) port map ( I => Mcount_bit_counter_cy_1_Q, O => bit_counter_2_FASTCARRY_3173 ); bit_counter_2_CYAND : X_AND2 generic map( LOC => "SLICE_X15Y79" ) port map ( I0 => bit_counter_2_CYSELG_3161, I1 => bit_counter_2_CYSELF_3176, O => bit_counter_2_CYAND_3174 ); bit_counter_2_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X15Y79" ) port map ( IA => bit_counter_2_CYMUXG2_3172, IB => bit_counter_2_FASTCARRY_3173, SEL => bit_counter_2_CYAND_3174, O => bit_counter_2_CYMUXFAST_3175 ); bit_counter_2_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X15Y79" ) port map ( IA => bit_counter_2_LOGIC_ZERO_3170, IB => bit_counter_2_CYMUXF2_3171, SEL => bit_counter_2_CYSELG_3161, O => bit_counter_2_CYMUXG2_3172 ); bit_counter_2_CYSELG : X_BUF generic map( LOC => "SLICE_X15Y79", PATHPULSE => 638 ps ) port map ( I => bit_counter_2_G, O => bit_counter_2_CYSELG_3161 ); bit_counter_2_SRINV : X_BUF generic map( LOC => "SLICE_X15Y79", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => bit_counter_2_SRINV_3159 ); bit_counter_2_CLKINV : X_INV generic map( LOC => "SLICE_X15Y79", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => bit_counter_2_CLKINVNOT ); bit_counter_4_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X15Y80" ) port map ( O => bit_counter_4_LOGIC_ZERO_3226 ); bit_counter_4_DXMUX : X_BUF generic map( LOC => "SLICE_X15Y80", PATHPULSE => 638 ps ) port map ( I => bit_counter_4_XORF_3253, O => bit_counter_4_DXMUX_3255 ); bit_counter_4_XORF : X_XOR2 generic map( LOC => "SLICE_X15Y80" ) port map ( I0 => bit_counter_4_CYINIT_3252, I1 => bit_counter_4_F, O => bit_counter_4_XORF_3253 ); bit_counter_4_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X15Y80" ) port map ( IA => bit_counter_4_LOGIC_ZERO_3226, IB => bit_counter_4_CYINIT_3252, SEL => bit_counter_4_CYSELF_3232, O => Mcount_bit_counter_cy_4_Q ); bit_counter_4_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X15Y80" ) port map ( IA => bit_counter_4_LOGIC_ZERO_3226, IB => bit_counter_4_LOGIC_ZERO_3226, SEL => bit_counter_4_CYSELF_3232, O => bit_counter_4_CYMUXF2_3227 ); bit_counter_4_CYINIT : X_BUF generic map( LOC => "SLICE_X15Y80", PATHPULSE => 638 ps ) port map ( I => Mcount_bit_counter_cy_3_Q, O => bit_counter_4_CYINIT_3252 ); bit_counter_4_CYSELF : X_BUF generic map( LOC => "SLICE_X15Y80", PATHPULSE => 638 ps ) port map ( I => bit_counter_4_F, O => bit_counter_4_CYSELF_3232 ); bit_counter_4_DYMUX : X_BUF generic map( LOC => "SLICE_X15Y80", PATHPULSE => 638 ps ) port map ( I => bit_counter_4_XORG_3234, O => bit_counter_4_DYMUX_3236 ); bit_counter_4_XORG : X_XOR2 generic map( LOC => "SLICE_X15Y80" ) port map ( I0 => Mcount_bit_counter_cy_4_Q, I1 => bit_counter_4_G, O => bit_counter_4_XORG_3234 ); bit_counter_4_FASTCARRY : X_BUF generic map( LOC => "SLICE_X15Y80", PATHPULSE => 638 ps ) port map ( I => Mcount_bit_counter_cy_3_Q, O => bit_counter_4_FASTCARRY_3229 ); bit_counter_4_CYAND : X_AND2 generic map( LOC => "SLICE_X15Y80" ) port map ( I0 => bit_counter_4_CYSELG_3217, I1 => bit_counter_4_CYSELF_3232, O => bit_counter_4_CYAND_3230 ); bit_counter_4_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X15Y80" ) port map ( IA => bit_counter_4_CYMUXG2_3228, IB => bit_counter_4_FASTCARRY_3229, SEL => bit_counter_4_CYAND_3230, O => bit_counter_4_CYMUXFAST_3231 ); bit_counter_4_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X15Y80" ) port map ( IA => bit_counter_4_LOGIC_ZERO_3226, IB => bit_counter_4_CYMUXF2_3227, SEL => bit_counter_4_CYSELG_3217, O => bit_counter_4_CYMUXG2_3228 ); bit_counter_4_CYSELG : X_BUF generic map( LOC => "SLICE_X15Y80", PATHPULSE => 638 ps ) port map ( I => bit_counter_4_G, O => bit_counter_4_CYSELG_3217 ); bit_counter_4_SRINV : X_BUF generic map( LOC => "SLICE_X15Y80", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => bit_counter_4_SRINV_3215 ); bit_counter_4_CLKINV : X_INV generic map( LOC => "SLICE_X15Y80", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => bit_counter_4_CLKINVNOT ); bit_counter_6_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X15Y81" ) port map ( O => bit_counter_6_LOGIC_ZERO_3302 ); bit_counter_6_DXMUX : X_BUF generic map( LOC => "SLICE_X15Y81", PATHPULSE => 638 ps ) port map ( I => bit_counter_6_FXMUX_3304, O => bit_counter_6_DXMUX_3305 ); bit_counter_6_FXMUX : X_BUF generic map( LOC => "SLICE_X15Y81", PATHPULSE => 638 ps ) port map ( I => bit_counter_6_XORF_3303, O => bit_counter_6_FXMUX_3304 ); bit_counter_6_XORF : X_XOR2 generic map( LOC => "SLICE_X15Y81" ) port map ( I0 => bit_counter_6_CYINIT_3301, I1 => bit_counter_6_F, O => bit_counter_6_XORF_3303 ); bit_counter_6_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X15Y81" ) port map ( IA => bit_counter_6_LOGIC_ZERO_3302, IB => bit_counter_6_CYINIT_3301, SEL => bit_counter_6_CYSELF_3292, O => Mcount_bit_counter_cy_6_Q ); bit_counter_6_CYINIT : X_BUF generic map( LOC => "SLICE_X15Y81", PATHPULSE => 638 ps ) port map ( I => bit_counter_4_CYMUXFAST_3231, O => bit_counter_6_CYINIT_3301 ); bit_counter_6_CYSELF : X_BUF generic map( LOC => "SLICE_X15Y81", PATHPULSE => 638 ps ) port map ( I => bit_counter_6_F, O => bit_counter_6_CYSELF_3292 ); bit_counter_6_DYMUX : X_BUF generic map( LOC => "SLICE_X15Y81", PATHPULSE => 638 ps ) port map ( I => bit_counter_6_XORG_3282, O => bit_counter_6_DYMUX_3284 ); bit_counter_6_XORG : X_XOR2 generic map( LOC => "SLICE_X15Y81" ) port map ( I0 => Mcount_bit_counter_cy_6_Q, I1 => bit_counter_7_rt_3279, O => bit_counter_6_XORG_3282 ); bit_counter_6_SRINV : X_BUF generic map( LOC => "SLICE_X15Y81", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => bit_counter_6_SRINV_3271 ); bit_counter_6_CLKINV : X_INV generic map( LOC => "SLICE_X15Y81", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => bit_counter_6_CLKINVNOT ); counter_0_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X49Y82" ) port map ( O => counter_0_LOGIC_ZERO_3334 ); counter_0_LOGIC_ONE : X_ONE generic map( LOC => "SLICE_X49Y82" ) port map ( O => counter_0_LOGIC_ONE_3357 ); counter_0_DXMUX : X_BUF generic map( LOC => "SLICE_X49Y82", PATHPULSE => 638 ps ) port map ( I => counter_0_XORF_3358, O => counter_0_DXMUX_3360 ); counter_0_XORF : X_XOR2 generic map( LOC => "SLICE_X49Y82" ) port map ( I0 => counter_0_CYINIT_3356, I1 => Mcount_counter_lut(0), O => counter_0_XORF_3358 ); counter_0_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X49Y82" ) port map ( IA => counter_0_LOGIC_ONE_3357, IB => counter_0_CYINIT_3356, SEL => counter_0_CYSELF_3347, O => Mcount_counter_cy_0_Q ); counter_0_CYINIT : X_BUF generic map( LOC => "SLICE_X49Y82", PATHPULSE => 638 ps ) port map ( I => counter_0_BXINV_3345, O => counter_0_CYINIT_3356 ); counter_0_CYSELF : X_BUF generic map( LOC => "SLICE_X49Y82", PATHPULSE => 638 ps ) port map ( I => Mcount_counter_lut(0), O => counter_0_CYSELF_3347 ); counter_0_BXINV : X_BUF generic map( LOC => "SLICE_X49Y82", PATHPULSE => 638 ps ) port map ( I => '0', O => counter_0_BXINV_3345 ); counter_0_DYMUX : X_BUF generic map( LOC => "SLICE_X49Y82", PATHPULSE => 638 ps ) port map ( I => counter_0_XORG_3337, O => counter_0_DYMUX_3339 ); counter_0_XORG : X_XOR2 generic map( LOC => "SLICE_X49Y82" ) port map ( I0 => Mcount_counter_cy_0_Q, I1 => counter_0_G, O => counter_0_XORG_3337 ); counter_0_COUTUSED : X_BUF generic map( LOC => "SLICE_X49Y82", PATHPULSE => 638 ps ) port map ( I => counter_0_CYMUXG_3336, O => Mcount_counter_cy_1_Q ); counter_0_CYMUXG : X_MUX2 generic map( LOC => "SLICE_X49Y82" ) port map ( IA => counter_0_LOGIC_ZERO_3334, IB => Mcount_counter_cy_0_Q, SEL => counter_0_CYSELG_3325, O => counter_0_CYMUXG_3336 ); counter_0_CYSELG : X_BUF generic map( LOC => "SLICE_X49Y82", PATHPULSE => 638 ps ) port map ( I => counter_0_G, O => counter_0_CYSELG_3325 ); counter_0_SRINV : X_BUF generic map( LOC => "SLICE_X49Y82", PATHPULSE => 638 ps ) port map ( I => counter_or0000, O => counter_0_SRINV_3323 ); counter_0_CLKINV : X_BUF generic map( LOC => "SLICE_X49Y82", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => counter_0_CLKINV_3322 ); counter_0_CEINV : X_BUF generic map( LOC => "SLICE_X49Y82", PATHPULSE => 638 ps ) port map ( I => busy_in_1448, O => counter_0_CEINV_3321 ); counter_2_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X49Y83" ) port map ( O => counter_2_LOGIC_ZERO_3388 ); counter_2_DXMUX : X_BUF generic map( LOC => "SLICE_X49Y83", PATHPULSE => 638 ps ) port map ( I => counter_2_XORF_3414, O => counter_2_DXMUX_3416 ); counter_2_XORF : X_XOR2 generic map( LOC => "SLICE_X49Y83" ) port map ( I0 => counter_2_CYINIT_3413, I1 => counter_2_F, O => counter_2_XORF_3414 ); counter_2_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X49Y83" ) port map ( IA => counter_2_LOGIC_ZERO_3388, IB => counter_2_CYINIT_3413, SEL => counter_2_CYSELF_3394, O => Mcount_counter_cy_2_Q ); counter_2_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X49Y83" ) port map ( IA => counter_2_LOGIC_ZERO_3388, IB => counter_2_LOGIC_ZERO_3388, SEL => counter_2_CYSELF_3394, O => counter_2_CYMUXF2_3389 ); counter_2_CYINIT : X_BUF generic map( LOC => "SLICE_X49Y83", PATHPULSE => 638 ps ) port map ( I => Mcount_counter_cy_1_Q, O => counter_2_CYINIT_3413 ); counter_2_CYSELF : X_BUF generic map( LOC => "SLICE_X49Y83", PATHPULSE => 638 ps ) port map ( I => counter_2_F, O => counter_2_CYSELF_3394 ); counter_2_DYMUX : X_BUF generic map( LOC => "SLICE_X49Y83", PATHPULSE => 638 ps ) port map ( I => counter_2_XORG_3396, O => counter_2_DYMUX_3398 ); counter_2_XORG : X_XOR2 generic map( LOC => "SLICE_X49Y83" ) port map ( I0 => Mcount_counter_cy_2_Q, I1 => counter_2_G, O => counter_2_XORG_3396 ); counter_2_COUTUSED : X_BUF generic map( LOC => "SLICE_X49Y83", PATHPULSE => 638 ps ) port map ( I => counter_2_CYMUXFAST_3393, O => Mcount_counter_cy_3_Q ); counter_2_FASTCARRY : X_BUF generic map( LOC => "SLICE_X49Y83", PATHPULSE => 638 ps ) port map ( I => Mcount_counter_cy_1_Q, O => counter_2_FASTCARRY_3391 ); counter_2_CYAND : X_AND2 generic map( LOC => "SLICE_X49Y83" ) port map ( I0 => counter_2_CYSELG_3379, I1 => counter_2_CYSELF_3394, O => counter_2_CYAND_3392 ); counter_2_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X49Y83" ) port map ( IA => counter_2_CYMUXG2_3390, IB => counter_2_FASTCARRY_3391, SEL => counter_2_CYAND_3392, O => counter_2_CYMUXFAST_3393 ); counter_2_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X49Y83" ) port map ( IA => counter_2_LOGIC_ZERO_3388, IB => counter_2_CYMUXF2_3389, SEL => counter_2_CYSELG_3379, O => counter_2_CYMUXG2_3390 ); counter_2_CYSELG : X_BUF generic map( LOC => "SLICE_X49Y83", PATHPULSE => 638 ps ) port map ( I => counter_2_G, O => counter_2_CYSELG_3379 ); counter_2_SRINV : X_BUF generic map( LOC => "SLICE_X49Y83", PATHPULSE => 638 ps ) port map ( I => counter_or0000, O => counter_2_SRINV_3377 ); counter_2_CLKINV : X_BUF generic map( LOC => "SLICE_X49Y83", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => counter_2_CLKINV_3376 ); counter_2_CEINV : X_BUF generic map( LOC => "SLICE_X49Y83", PATHPULSE => 638 ps ) port map ( I => busy_in_1448, O => counter_2_CEINV_3375 ); counter_4_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X49Y84" ) port map ( O => counter_4_LOGIC_ZERO_3444 ); counter_4_DXMUX : X_BUF generic map( LOC => "SLICE_X49Y84", PATHPULSE => 638 ps ) port map ( I => counter_4_XORF_3470, O => counter_4_DXMUX_3472 ); counter_4_XORF : X_XOR2 generic map( LOC => "SLICE_X49Y84" ) port map ( I0 => counter_4_CYINIT_3469, I1 => counter_4_F, O => counter_4_XORF_3470 ); counter_4_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X49Y84" ) port map ( IA => counter_4_LOGIC_ZERO_3444, IB => counter_4_CYINIT_3469, SEL => counter_4_CYSELF_3450, O => Mcount_counter_cy_4_Q ); counter_4_CYMUXF2 : X_MUX2 generic map( LOC => "SLICE_X49Y84" ) port map ( IA => counter_4_LOGIC_ZERO_3444, IB => counter_4_LOGIC_ZERO_3444, SEL => counter_4_CYSELF_3450, O => counter_4_CYMUXF2_3445 ); counter_4_CYINIT : X_BUF generic map( LOC => "SLICE_X49Y84", PATHPULSE => 638 ps ) port map ( I => Mcount_counter_cy_3_Q, O => counter_4_CYINIT_3469 ); counter_4_CYSELF : X_BUF generic map( LOC => "SLICE_X49Y84", PATHPULSE => 638 ps ) port map ( I => counter_4_F, O => counter_4_CYSELF_3450 ); counter_4_DYMUX : X_BUF generic map( LOC => "SLICE_X49Y84", PATHPULSE => 638 ps ) port map ( I => counter_4_XORG_3452, O => counter_4_DYMUX_3454 ); counter_4_XORG : X_XOR2 generic map( LOC => "SLICE_X49Y84" ) port map ( I0 => Mcount_counter_cy_4_Q, I1 => counter_4_G, O => counter_4_XORG_3452 ); counter_4_FASTCARRY : X_BUF generic map( LOC => "SLICE_X49Y84", PATHPULSE => 638 ps ) port map ( I => Mcount_counter_cy_3_Q, O => counter_4_FASTCARRY_3447 ); counter_4_CYAND : X_AND2 generic map( LOC => "SLICE_X49Y84" ) port map ( I0 => counter_4_CYSELG_3435, I1 => counter_4_CYSELF_3450, O => counter_4_CYAND_3448 ); counter_4_CYMUXFAST : X_MUX2 generic map( LOC => "SLICE_X49Y84" ) port map ( IA => counter_4_CYMUXG2_3446, IB => counter_4_FASTCARRY_3447, SEL => counter_4_CYAND_3448, O => counter_4_CYMUXFAST_3449 ); counter_4_CYMUXG2 : X_MUX2 generic map( LOC => "SLICE_X49Y84" ) port map ( IA => counter_4_LOGIC_ZERO_3444, IB => counter_4_CYMUXF2_3445, SEL => counter_4_CYSELG_3435, O => counter_4_CYMUXG2_3446 ); counter_4_CYSELG : X_BUF generic map( LOC => "SLICE_X49Y84", PATHPULSE => 638 ps ) port map ( I => counter_4_G, O => counter_4_CYSELG_3435 ); counter_4_SRINV : X_BUF generic map( LOC => "SLICE_X49Y84", PATHPULSE => 638 ps ) port map ( I => counter_or0000, O => counter_4_SRINV_3433 ); counter_4_CLKINV : X_BUF generic map( LOC => "SLICE_X49Y84", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => counter_4_CLKINV_3432 ); counter_4_CEINV : X_BUF generic map( LOC => "SLICE_X49Y84", PATHPULSE => 638 ps ) port map ( I => busy_in_1448, O => counter_4_CEINV_3431 ); counter_6_LOGIC_ZERO : X_ZERO generic map( LOC => "SLICE_X49Y85" ) port map ( O => counter_6_LOGIC_ZERO_3518 ); counter_6_DXMUX : X_BUF generic map( LOC => "SLICE_X49Y85", PATHPULSE => 638 ps ) port map ( I => counter_6_XORF_3519, O => counter_6_DXMUX_3521 ); counter_6_XORF : X_XOR2 generic map( LOC => "SLICE_X49Y85" ) port map ( I0 => counter_6_CYINIT_3517, I1 => counter_6_F, O => counter_6_XORF_3519 ); counter_6_CYMUXF : X_MUX2 generic map( LOC => "SLICE_X49Y85" ) port map ( IA => counter_6_LOGIC_ZERO_3518, IB => counter_6_CYINIT_3517, SEL => counter_6_CYSELF_3508, O => Mcount_counter_cy_6_Q ); counter_6_CYINIT : X_BUF generic map( LOC => "SLICE_X49Y85", PATHPULSE => 638 ps ) port map ( I => counter_4_CYMUXFAST_3449, O => counter_6_CYINIT_3517 ); counter_6_CYSELF : X_BUF generic map( LOC => "SLICE_X49Y85", PATHPULSE => 638 ps ) port map ( I => counter_6_F, O => counter_6_CYSELF_3508 ); counter_6_DYMUX : X_BUF generic map( LOC => "SLICE_X49Y85", PATHPULSE => 638 ps ) port map ( I => counter_6_XORG_3499, O => counter_6_DYMUX_3501 ); counter_6_XORG : X_XOR2 generic map( LOC => "SLICE_X49Y85" ) port map ( I0 => Mcount_counter_cy_6_Q, I1 => counter_7_rt_3496, O => counter_6_XORG_3499 ); counter_6_SRINV : X_BUF generic map( LOC => "SLICE_X49Y85", PATHPULSE => 638 ps ) port map ( I => counter_or0000, O => counter_6_SRINV_3488 ); counter_6_CLKINV : X_BUF generic map( LOC => "SLICE_X49Y85", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => counter_6_CLKINV_3487 ); counter_6_CEINV : X_BUF generic map( LOC => "SLICE_X49Y85", PATHPULSE => 638 ps ) port map ( I => busy_in_1448, O => counter_6_CEINV_3486 ); MDIO_IOBUF_OBUFT : X_OBUFT generic map( LOC => "PAD210" ) port map ( I => MDIO_O, CTL => MDIO_T, O => MDIO ); MDIO_IOBUF_IBUF : X_BUF generic map( LOC => "PAD210", PATHPULSE => 638 ps ) port map ( I => MDIO, O => MDIO_INBUF ); MDC_OBUFT : X_OBUFT generic map( LOC => "PAD12" ) port map ( I => MDC_O, CTL => MDC_T, O => MDC ); strt_IBUF : X_BUF generic map( LOC => "PAD195", PATHPULSE => 638 ps ) port map ( I => strt, O => strt_INBUF ); clk_BUFGP_IBUFG : X_BUF generic map( LOC => "IPAD28", PATHPULSE => 638 ps ) port map ( I => clk, O => clk_INBUF ); reg_addr_0_IBUF : X_BUF generic map( LOC => "IPAD189", PATHPULSE => 638 ps ) port map ( I => reg_addr(0), O => reg_addr_0_INBUF ); reg_addr_1_IBUF : X_BUF generic map( LOC => "PAD188", PATHPULSE => 638 ps ) port map ( I => reg_addr(1), O => reg_addr_1_INBUF ); reg_addr_2_IBUF : X_BUF generic map( LOC => "PAD187", PATHPULSE => 638 ps ) port map ( I => reg_addr(2), O => reg_addr_2_INBUF ); reg_addr_3_IBUF : X_BUF generic map( LOC => "PAD186", PATHPULSE => 638 ps ) port map ( I => reg_addr(3), O => reg_addr_3_INBUF ); reg_addr_4_IBUF : X_BUF generic map( LOC => "PAD185", PATHPULSE => 638 ps ) port map ( I => reg_addr(4), O => reg_addr_4_INBUF ); data_out_10_OBUF : X_OBUF generic map( LOC => "PAD220" ) port map ( I => data_out_10_O, O => data_out(10) ); data_out_11_OBUF : X_OBUF generic map( LOC => "PAD218" ) port map ( I => data_out_11_O, O => data_out(11) ); data_out_12_OBUF : X_OBUF generic map( LOC => "PAD217" ) port map ( I => data_out_12_O, O => data_out(12) ); data_out_13_OBUF : X_OBUF generic map( LOC => "PAD216" ) port map ( I => data_out_13_O, O => data_out(13) ); data_out_0_OBUF : X_OBUF generic map( LOC => "PAD232" ) port map ( I => data_out_0_O, O => data_out(0) ); data_out_1_OBUF : X_OBUF generic map( LOC => "PAD227" ) port map ( I => data_out_1_O, O => data_out(1) ); data_out_14_OBUF : X_OBUF generic map( LOC => "PAD215" ) port map ( I => data_out_14_O, O => data_out(14) ); data_out_2_OBUF : X_OBUF generic map( LOC => "PAD230" ) port map ( I => data_out_2_O, O => data_out(2) ); data_out_15_OBUF : X_OBUF generic map( LOC => "PAD213" ) port map ( I => data_out_15_O, O => data_out(15) ); data_out_3_OBUF : X_OBUF generic map( LOC => "PAD229" ) port map ( I => data_out_3_O, O => data_out(3) ); data_out_4_OBUF : X_OBUF generic map( LOC => "PAD5" ) port map ( I => data_out_4_O, O => data_out(4) ); data_in_0_IBUF : X_BUF generic map( LOC => "IPAD228", PATHPULSE => 638 ps ) port map ( I => data_in(0), O => data_in_0_INBUF ); data_out_5_OBUF : X_OBUF generic map( LOC => "PAD226" ) port map ( I => data_out_5_O, O => data_out(5) ); data_in_1_IBUF : X_BUF generic map( LOC => "IPAD224", PATHPULSE => 638 ps ) port map ( I => data_in(1), O => data_in_1_INBUF ); data_out_6_OBUF : X_OBUF generic map( LOC => "PAD225" ) port map ( I => data_out_6_O, O => data_out(6) ); data_in_10_IBUF : X_BUF generic map( LOC => "PAD203", PATHPULSE => 638 ps ) port map ( I => data_in(10), O => data_in_10_INBUF ); data_in_2_IBUF : X_BUF generic map( LOC => "IPAD219", PATHPULSE => 638 ps ) port map ( I => data_in(2), O => data_in_2_INBUF ); latched_data_2 : X_FF generic map( LOC => "IPAD219", INIT => '0' ) port map ( I => data_in_2_IFF_IDDRIN_MUX_3793, CE => data_in_2_IFF_ICEINV_3795, CLK => data_in_2_IFF_ICLK1INV_3797, SET => GND, RST => GND, O => latched_data(2) ); data_in_2_IFF_IDDRIN_MUX : X_BUF generic map( LOC => "IPAD219", PATHPULSE => 638 ps ) port map ( I => data_in_2_INBUF, O => data_in_2_IFF_IDDRIN_MUX_3793 ); data_in_2_IFF_ICLK1INV : X_BUF generic map( LOC => "IPAD219", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => data_in_2_IFF_ICLK1INV_3797 ); data_in_2_IFF_ICEINV : X_BUF generic map( LOC => "IPAD219", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => data_in_2_IFF_ICEINV_3795 ); data_out_7_OBUF : X_OBUF generic map( LOC => "PAD223" ) port map ( I => data_out_7_O, O => data_out(7) ); data_in_11_IBUF : X_BUF generic map( LOC => "PAD202", PATHPULSE => 638 ps ) port map ( I => data_in(11), O => data_in_11_INBUF ); latched_data_11 : X_FF generic map( LOC => "PAD202", INIT => '0' ) port map ( I => data_in_11_IFF_IDDRIN_MUX_3821, CE => data_in_11_IFF_ICEINV_3823, CLK => data_in_11_IFF_ICLK1INV_3825, SET => GND, RST => GND, O => latched_data(11) ); data_in_11_IFF_IDDRIN_MUX : X_BUF generic map( LOC => "PAD202", PATHPULSE => 638 ps ) port map ( I => data_in_11_INBUF, O => data_in_11_IFF_IDDRIN_MUX_3821 ); data_in_11_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD202", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => data_in_11_IFF_ICLK1INV_3825 ); data_in_11_IFF_ICEINV : X_BUF generic map( LOC => "PAD202", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => data_in_11_IFF_ICEINV_3823 ); data_in_3_IBUF : X_BUF generic map( LOC => "IPAD214", PATHPULSE => 638 ps ) port map ( I => data_in(3), O => data_in_3_INBUF ); latched_data_3 : X_FF generic map( LOC => "IPAD214", INIT => '0' ) port map ( I => data_in_3_IFF_IDDRIN_MUX_3841, CE => data_in_3_IFF_ICEINV_3843, CLK => data_in_3_IFF_ICLK1INV_3845, SET => GND, RST => GND, O => latched_data(3) ); data_in_3_IFF_IDDRIN_MUX : X_BUF generic map( LOC => "IPAD214", PATHPULSE => 638 ps ) port map ( I => data_in_3_INBUF, O => data_in_3_IFF_IDDRIN_MUX_3841 ); data_in_3_IFF_ICLK1INV : X_BUF generic map( LOC => "IPAD214", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => data_in_3_IFF_ICLK1INV_3845 ); data_in_3_IFF_ICEINV : X_BUF generic map( LOC => "IPAD214", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => data_in_3_IFF_ICEINV_3843 ); data_out_8_OBUF : X_OBUF generic map( LOC => "PAD222" ) port map ( I => data_out_8_O, O => data_out(8) ); data_in_12_IBUF : X_BUF generic map( LOC => "PAD201", PATHPULSE => 638 ps ) port map ( I => data_in(12), O => data_in_12_INBUF ); latched_data_12 : X_FF generic map( LOC => "PAD201", INIT => '0' ) port map ( I => data_in_12_IFF_IDDRIN_MUX_3869, CE => data_in_12_IFF_ICEINV_3871, CLK => data_in_12_IFF_ICLK1INV_3873, SET => GND, RST => GND, O => latched_data(12) ); data_in_12_IFF_IDDRIN_MUX : X_BUF generic map( LOC => "PAD201", PATHPULSE => 638 ps ) port map ( I => data_in_12_INBUF, O => data_in_12_IFF_IDDRIN_MUX_3869 ); data_in_12_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD201", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => data_in_12_IFF_ICLK1INV_3873 ); data_in_12_IFF_ICEINV : X_BUF generic map( LOC => "PAD201", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => data_in_12_IFF_ICEINV_3871 ); data_in_4_IBUF : X_BUF generic map( LOC => "IPAD209", PATHPULSE => 638 ps ) port map ( I => data_in(4), O => data_in_4_INBUF ); latched_data_4 : X_FF generic map( LOC => "IPAD209", INIT => '0' ) port map ( I => data_in_4_IFF_IDDRIN_MUX_3889, CE => data_in_4_IFF_ICEINV_3891, CLK => data_in_4_IFF_ICLK1INV_3893, SET => GND, RST => GND, O => latched_data(4) ); data_in_4_IFF_IDDRIN_MUX : X_BUF generic map( LOC => "IPAD209", PATHPULSE => 638 ps ) port map ( I => data_in_4_INBUF, O => data_in_4_IFF_IDDRIN_MUX_3889 ); data_in_4_IFF_ICLK1INV : X_BUF generic map( LOC => "IPAD209", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => data_in_4_IFF_ICLK1INV_3893 ); data_in_4_IFF_ICEINV : X_BUF generic map( LOC => "IPAD209", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => data_in_4_IFF_ICEINV_3891 ); data_out_9_OBUF : X_OBUF generic map( LOC => "PAD221" ) port map ( I => data_out_9_O, O => data_out(9) ); data_in_13_IBUF : X_BUF generic map( LOC => "PAD200", PATHPULSE => 638 ps ) port map ( I => data_in(13), O => data_in_13_INBUF ); latched_data_13 : X_FF generic map( LOC => "PAD200", INIT => '0' ) port map ( I => data_in_13_IFF_IDDRIN_MUX_3917, CE => data_in_13_IFF_ICEINV_3919, CLK => data_in_13_IFF_ICLK1INV_3921, SET => GND, RST => GND, O => latched_data(13) ); data_in_13_IFF_IDDRIN_MUX : X_BUF generic map( LOC => "PAD200", PATHPULSE => 638 ps ) port map ( I => data_in_13_INBUF, O => data_in_13_IFF_IDDRIN_MUX_3917 ); data_in_13_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD200", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => data_in_13_IFF_ICLK1INV_3921 ); data_in_13_IFF_ICEINV : X_BUF generic map( LOC => "PAD200", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => data_in_13_IFF_ICEINV_3919 ); data_in_5_IBUF : X_BUF generic map( LOC => "PAD208", PATHPULSE => 638 ps ) port map ( I => data_in(5), O => data_in_5_INBUF ); latched_data_5 : X_FF generic map( LOC => "PAD208", INIT => '0' ) port map ( I => data_in_5_IFF_IDDRIN_MUX_3937, CE => data_in_5_IFF_ICEINV_3939, CLK => data_in_5_IFF_ICLK1INV_3941, SET => GND, RST => GND, O => latched_data(5) ); data_in_5_IFF_IDDRIN_MUX : X_BUF generic map( LOC => "PAD208", PATHPULSE => 638 ps ) port map ( I => data_in_5_INBUF, O => data_in_5_IFF_IDDRIN_MUX_3937 ); data_in_5_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD208", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => data_in_5_IFF_ICLK1INV_3941 ); data_in_5_IFF_ICEINV : X_BUF generic map( LOC => "PAD208", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => data_in_5_IFF_ICEINV_3939 ); write_read_IBUF : X_BUF generic map( LOC => "IPAD199", PATHPULSE => 638 ps ) port map ( I => write_read, O => write_read_INBUF ); reset_IBUF : X_BUF generic map( LOC => "PAD196", PATHPULSE => 638 ps ) port map ( I => reset, O => reset_INBUF ); data_in_14_IBUF : X_BUF generic map( LOC => "PAD197", PATHPULSE => 638 ps ) port map ( I => data_in(14), O => data_in_14_INBUF ); data_in_6_IBUF : X_BUF generic map( LOC => "PAD207", PATHPULSE => 638 ps ) port map ( I => data_in(6), O => data_in_6_INBUF ); latched_data_6 : X_FF generic map( LOC => "PAD207", INIT => '0' ) port map ( I => data_in_6_IFF_IDDRIN_MUX_3989, CE => data_in_6_IFF_ICEINV_3991, CLK => data_in_6_IFF_ICLK1INV_3993, SET => GND, RST => GND, O => latched_data(6) ); data_in_6_IFF_IDDRIN_MUX : X_BUF generic map( LOC => "PAD207", PATHPULSE => 638 ps ) port map ( I => data_in_6_INBUF, O => data_in_6_IFF_IDDRIN_MUX_3989 ); data_in_6_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD207", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => data_in_6_IFF_ICLK1INV_3993 ); data_in_6_IFF_ICEINV : X_BUF generic map( LOC => "PAD207", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => data_in_6_IFF_ICEINV_3991 ); phy_addr_0_IBUF : X_BUF generic map( LOC => "IPAD194", PATHPULSE => 638 ps ) port map ( I => phy_addr(0), O => phy_addr_0_INBUF ); data_in_15_IBUF : X_BUF generic map( LOC => "PAD198", PATHPULSE => 638 ps ) port map ( I => data_in(15), O => data_in_15_INBUF ); data_in_7_IBUF : X_BUF generic map( LOC => "PAD206", PATHPULSE => 638 ps ) port map ( I => data_in(7), O => data_in_7_INBUF ); phy_addr_1_IBUF : X_BUF generic map( LOC => "PAD193", PATHPULSE => 638 ps ) port map ( I => phy_addr(1), O => phy_addr_1_INBUF ); data_in_8_IBUF : X_BUF generic map( LOC => "PAD205", PATHPULSE => 638 ps ) port map ( I => data_in(8), O => data_in_8_INBUF ); phy_addr_2_IBUF : X_BUF generic map( LOC => "PAD192", PATHPULSE => 638 ps ) port map ( I => phy_addr(2), O => phy_addr_2_INBUF ); data_in_9_IBUF : X_BUF generic map( LOC => "IPAD204", PATHPULSE => 638 ps ) port map ( I => data_in(9), O => data_in_9_INBUF ); phy_addr_3_IBUF : X_BUF generic map( LOC => "PAD191", PATHPULSE => 638 ps ) port map ( I => phy_addr(3), O => phy_addr_3_INBUF ); phy_addr_4_IBUF : X_BUF generic map( LOC => "PAD190", PATHPULSE => 638 ps ) port map ( I => phy_addr(4), O => phy_addr_4_INBUF ); busy_OBUF : X_OBUF generic map( LOC => "PAD41" ) port map ( I => busy_O, O => busy ); clk_div_BUFG : X_BUFGMUX generic map( LOC => "BUFGMUX_X1Y10" ) port map ( I0 => clk_div_BUFG_I0_INV, I1 => GND, S => clk_div_BUFG_S_INVNOT, O => clk_div_1313 ); clk_div_BUFG_SINV : X_INV generic map( LOC => "BUFGMUX_X1Y10", PATHPULSE => 638 ps ) port map ( I => '1', O => clk_div_BUFG_S_INVNOT ); clk_div_BUFG_I0_USED : X_BUF generic map( LOC => "BUFGMUX_X1Y10", PATHPULSE => 638 ps ) port map ( I => clk_div1, O => clk_div_BUFG_I0_INV ); clk_BUFGP_BUFG : X_BUFGMUX generic map( LOC => "BUFGMUX_X2Y10" ) port map ( I0 => clk_BUFGP_BUFG_I0_INV, I1 => GND, S => clk_BUFGP_BUFG_S_INVNOT, O => clk_BUFGP ); clk_BUFGP_BUFG_SINV : X_INV generic map( LOC => "BUFGMUX_X2Y10", PATHPULSE => 638 ps ) port map ( I => '1', O => clk_BUFGP_BUFG_S_INVNOT ); clk_BUFGP_BUFG_I0_USED : X_BUF generic map( LOC => "BUFGMUX_X2Y10", PATHPULSE => 638 ps ) port map ( I => clk_INBUF, O => clk_BUFGP_BUFG_I0_INV ); counter_or0000_XUSED : X_BUF generic map( LOC => "SLICE_X48Y83", PATHPULSE => 638 ps ) port map ( I => counter_or0000_F5MUX_4178, O => counter_or0000 ); counter_or0000_F5MUX : X_MUX2 generic map( LOC => "SLICE_X48Y83" ) port map ( IA => counter_or00001, IB => counter_or0000_F, SEL => counter_or0000_BXINV_4167, O => counter_or0000_F5MUX_4178 ); counter_or0000_BXINV : X_BUF generic map( LOC => "SLICE_X48Y83", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => counter_or0000_BXINV_4167 ); Mtridata_MDIO_and0000135_XUSED : X_BUF generic map( LOC => "SLICE_X15Y65", PATHPULSE => 638 ps ) port map ( I => Mtridata_MDIO_and0000135_F5MUX_4203, O => Mtridata_MDIO_and0000135 ); Mtridata_MDIO_and0000135_F5MUX : X_MUX2 generic map( LOC => "SLICE_X15Y65" ) port map ( IA => N22, IB => N23, SEL => Mtridata_MDIO_and0000135_BXINV_4195, O => Mtridata_MDIO_and0000135_F5MUX_4203 ); Mtridata_MDIO_and0000135_BXINV : X_BUF generic map( LOC => "SLICE_X15Y65", PATHPULSE => 638 ps ) port map ( I => bit_counter(5), O => Mtridata_MDIO_and0000135_BXINV_4195 ); Mtridata_MDIO_and000028_XUSED : X_BUF generic map( LOC => "SLICE_X20Y78", PATHPULSE => 638 ps ) port map ( I => Mtridata_MDIO_and000028_F5MUX_4228, O => Mtridata_MDIO_and000028 ); Mtridata_MDIO_and000028_F5MUX : X_MUX2 generic map( LOC => "SLICE_X20Y78" ) port map ( IA => Mtridata_MDIO_and0000282_4219, IB => Mtridata_MDIO_and0000281_4226, SEL => Mtridata_MDIO_and000028_BXINV_4221, O => Mtridata_MDIO_and000028_F5MUX_4228 ); Mtridata_MDIO_and000028_BXINV : X_BUF generic map( LOC => "SLICE_X20Y78", PATHPULSE => 638 ps ) port map ( I => bit_counter(4), O => Mtridata_MDIO_and000028_BXINV_4221 ); read_send_data_10_and0000_XUSED : X_BUF generic map( LOC => "SLICE_X2Y64", PATHPULSE => 638 ps ) port map ( I => read_send_data_10_and0000_4251, O => read_send_data_10_and0000_0 ); read_send_data_10_and0000_YUSED : X_BUF generic map( LOC => "SLICE_X2Y64", PATHPULSE => 638 ps ) port map ( I => read_send_data_0_cmp_lt0000_pack_1, O => read_send_data_0_cmp_lt0000 ); read_receive_data_0_and0000_XUSED : X_BUF generic map( LOC => "SLICE_X3Y82", PATHPULSE => 638 ps ) port map ( I => read_receive_data_0_and0000_4275, O => read_receive_data_0_and0000_0 ); read_receive_data_0_and0000_YUSED : X_BUF generic map( LOC => "SLICE_X3Y82", PATHPULSE => 638 ps ) port map ( I => read_receive_data_0_and0000_SW2_O_pack_1, O => read_receive_data_0_and0000_SW2_O ); write_send_data_and0000_XUSED : X_BUF generic map( LOC => "SLICE_X14Y79", PATHPULSE => 638 ps ) port map ( I => write_send_data_and0000_4299, O => write_send_data_and0000_0 ); write_send_data_and0000_YUSED : X_BUF generic map( LOC => "SLICE_X14Y79", PATHPULSE => 638 ps ) port map ( I => read_receive_data_0_cmp_gt00001_pack_1, O => read_receive_data_0_cmp_gt00001_1316 ); write_send_data_not0001_XUSED : X_BUF generic map( LOC => "SLICE_X12Y78", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001, O => write_send_data_not0001_0 ); write_send_data_not0001_YUSED : X_BUF generic map( LOC => "SLICE_X12Y78", PATHPULSE => 638 ps ) port map ( I => N3_pack_1, O => N3 ); write_send_data_11_DXMUX : X_BUF generic map( LOC => "SLICE_X0Y45", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0051, O => write_send_data_11_DXMUX_4362 ); write_send_data_11_DYMUX : X_BUF generic map( LOC => "SLICE_X0Y45", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0052, O => write_send_data_11_DYMUX_4348 ); write_send_data_11_SRINV : X_BUF generic map( LOC => "SLICE_X0Y45", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_11_SRINV_4339 ); write_send_data_11_CLKINV : X_INV generic map( LOC => "SLICE_X0Y45", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_11_CLKINVNOT ); write_send_data_11_CEINV : X_BUF generic map( LOC => "SLICE_X0Y45", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_11_CEINV_4337 ); write_send_data_21_DXMUX : X_BUF generic map( LOC => "SLICE_X7Y3", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0043, O => write_send_data_21_DXMUX_4404 ); write_send_data_21_DYMUX : X_BUF generic map( LOC => "SLICE_X7Y3", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0044, O => write_send_data_21_DYMUX_4390 ); write_send_data_21_SRINV : X_BUF generic map( LOC => "SLICE_X7Y3", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_21_SRINV_4381 ); write_send_data_21_CLKINV : X_INV generic map( LOC => "SLICE_X7Y3", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_21_CLKINVNOT ); write_send_data_21_CEINV : X_BUF generic map( LOC => "SLICE_X7Y3", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_21_CEINV_4379 ); write_send_data_13_DXMUX : X_BUF generic map( LOC => "SLICE_X0Y40", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0049, O => write_send_data_13_DXMUX_4446 ); write_send_data_13_DYMUX : X_BUF generic map( LOC => "SLICE_X0Y40", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0050, O => write_send_data_13_DYMUX_4432 ); write_send_data_13_SRINV : X_BUF generic map( LOC => "SLICE_X0Y40", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_13_SRINV_4423 ); write_send_data_13_CLKINV : X_INV generic map( LOC => "SLICE_X0Y40", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_13_CLKINVNOT ); write_send_data_13_CEINV : X_BUF generic map( LOC => "SLICE_X0Y40", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_13_CEINV_4421 ); read_send_data_1_DXMUX : X_BUF generic map( LOC => "SLICE_X0Y30", PATHPULSE => 638 ps ) port map ( I => read_send_data_1_mux0000, O => read_send_data_1_DXMUX_4488 ); read_send_data_1_DYMUX : X_BUF generic map( LOC => "SLICE_X0Y30", PATHPULSE => 638 ps ) port map ( I => read_send_data_0_mux0000, O => read_send_data_1_DYMUX_4474 ); read_send_data_1_SRINV : X_BUF generic map( LOC => "SLICE_X0Y30", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_1_SRINV_4466 ); read_send_data_1_CLKINV : X_INV generic map( LOC => "SLICE_X0Y30", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_1_CLKINVNOT ); read_send_data_1_CEINV : X_BUF generic map( LOC => "SLICE_X0Y30", PATHPULSE => 638 ps ) port map ( I => read_send_data_0_not0001_0, O => read_send_data_1_CEINV_4464 ); write_send_data_31_DXMUX : X_BUF generic map( LOC => "SLICE_X22Y31", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0033, O => write_send_data_31_DXMUX_4530 ); write_send_data_31_DYMUX : X_BUF generic map( LOC => "SLICE_X22Y31", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0034, O => write_send_data_31_DYMUX_4517 ); write_send_data_31_SRINV : X_BUF generic map( LOC => "SLICE_X22Y31", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_31_SRINV_4509 ); write_send_data_31_CLKINV : X_INV generic map( LOC => "SLICE_X22Y31", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_31_CLKINVNOT ); write_send_data_31_CEINV : X_BUF generic map( LOC => "SLICE_X22Y31", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_31_CEINV_4507 ); write_send_data_23_DXMUX : X_BUF generic map( LOC => "SLICE_X12Y9", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0041, O => write_send_data_23_DXMUX_4572 ); write_send_data_23_DYMUX : X_BUF generic map( LOC => "SLICE_X12Y9", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0042, O => write_send_data_23_DYMUX_4558 ); write_send_data_23_SRINV : X_BUF generic map( LOC => "SLICE_X12Y9", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_23_SRINV_4549 ); write_send_data_23_CLKINV : X_INV generic map( LOC => "SLICE_X12Y9", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_23_CLKINVNOT ); write_send_data_23_CEINV : X_BUF generic map( LOC => "SLICE_X12Y9", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_23_CEINV_4547 ); write_send_data_15_DXMUX : X_BUF generic map( LOC => "SLICE_X1Y37", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0047, O => write_send_data_15_DXMUX_4614 ); write_send_data_15_DYMUX : X_BUF generic map( LOC => "SLICE_X1Y37", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0048, O => write_send_data_15_DYMUX_4600 ); write_send_data_15_SRINV : X_BUF generic map( LOC => "SLICE_X1Y37", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_15_SRINV_4591 ); write_send_data_15_CLKINV : X_INV generic map( LOC => "SLICE_X1Y37", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_15_CLKINVNOT ); write_send_data_15_CEINV : X_BUF generic map( LOC => "SLICE_X1Y37", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_15_CEINV_4589 ); read_send_data_3_DXMUX : X_BUF generic map( LOC => "SLICE_X0Y27", PATHPULSE => 638 ps ) port map ( I => read_send_data_3_mux0000, O => read_send_data_3_DXMUX_4656 ); read_send_data_3_DYMUX : X_BUF generic map( LOC => "SLICE_X0Y27", PATHPULSE => 638 ps ) port map ( I => read_send_data_2_mux0000, O => read_send_data_3_DYMUX_4642 ); read_send_data_3_SRINV : X_BUF generic map( LOC => "SLICE_X0Y27", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_3_SRINV_4633 ); read_send_data_3_CLKINV : X_INV generic map( LOC => "SLICE_X0Y27", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_3_CLKINVNOT ); read_send_data_3_CEINV : X_BUF generic map( LOC => "SLICE_X0Y27", PATHPULSE => 638 ps ) port map ( I => read_send_data_0_not0001_0, O => read_send_data_3_CEINV_4631 ); write_send_data_41_DXMUX : X_BUF generic map( LOC => "SLICE_X22Y48", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0023, O => write_send_data_41_DXMUX_4698 ); write_send_data_41_DYMUX : X_BUF generic map( LOC => "SLICE_X22Y48", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0024, O => write_send_data_41_DYMUX_4685 ); write_send_data_41_SRINV : X_BUF generic map( LOC => "SLICE_X22Y48", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_41_SRINV_4677 ); write_send_data_41_CLKINV : X_INV generic map( LOC => "SLICE_X22Y48", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_41_CLKINVNOT ); write_send_data_41_CEINV : X_BUF generic map( LOC => "SLICE_X22Y48", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_41_CEINV_4675 ); write_send_data_33_DXMUX : X_BUF generic map( LOC => "SLICE_X22Y35", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0031, O => write_send_data_33_DXMUX_4740 ); write_send_data_33_DYMUX : X_BUF generic map( LOC => "SLICE_X22Y35", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0032, O => write_send_data_33_DYMUX_4727 ); write_send_data_33_SRINV : X_BUF generic map( LOC => "SLICE_X22Y35", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_33_SRINV_4719 ); write_send_data_33_CLKINV : X_INV generic map( LOC => "SLICE_X22Y35", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_33_CLKINVNOT ); write_send_data_33_CEINV : X_BUF generic map( LOC => "SLICE_X22Y35", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_33_CEINV_4717 ); write_send_data_25_DXMUX : X_BUF generic map( LOC => "SLICE_X15Y15", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0039, O => write_send_data_25_DXMUX_4782 ); write_send_data_25_DYMUX : X_BUF generic map( LOC => "SLICE_X15Y15", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0040, O => write_send_data_25_DYMUX_4768 ); write_send_data_25_SRINV : X_BUF generic map( LOC => "SLICE_X15Y15", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_25_SRINV_4759 ); write_send_data_25_CLKINV : X_INV generic map( LOC => "SLICE_X15Y15", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_25_CLKINVNOT ); write_send_data_25_CEINV : X_BUF generic map( LOC => "SLICE_X15Y15", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_25_CEINV_4757 ); write_send_data_17_DXMUX : X_BUF generic map( LOC => "SLICE_X12Y31", PATHPULSE => 638 ps ) port map ( I => write_send_data_index0001, O => write_send_data_17_DXMUX_4824 ); write_send_data_17_DYMUX : X_BUF generic map( LOC => "SLICE_X12Y31", PATHPULSE => 638 ps ) port map ( I => write_send_data_index0003, O => write_send_data_17_DYMUX_4811 ); write_send_data_17_SRINV : X_BUF generic map( LOC => "SLICE_X12Y31", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_17_SRINV_4803 ); write_send_data_17_CLKINV : X_INV generic map( LOC => "SLICE_X12Y31", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_17_CLKINVNOT ); write_send_data_17_CEINV : X_BUF generic map( LOC => "SLICE_X12Y31", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_17_CEINV_4801 ); read_send_data_5_DXMUX : X_BUF generic map( LOC => "SLICE_X1Y29", PATHPULSE => 638 ps ) port map ( I => read_send_data_5_mux0000, O => read_send_data_5_DXMUX_4866 ); read_send_data_5_DYMUX : X_BUF generic map( LOC => "SLICE_X1Y29", PATHPULSE => 638 ps ) port map ( I => read_send_data_4_mux0000, O => read_send_data_5_DYMUX_4852 ); read_send_data_5_SRINV : X_BUF generic map( LOC => "SLICE_X1Y29", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_5_SRINV_4843 ); read_send_data_5_CLKINV : X_INV generic map( LOC => "SLICE_X1Y29", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_5_CLKINVNOT ); read_send_data_5_CEINV : X_BUF generic map( LOC => "SLICE_X1Y29", PATHPULSE => 638 ps ) port map ( I => read_send_data_0_not0001_0, O => read_send_data_5_CEINV_4841 ); write_send_data_51_DXMUX : X_BUF generic map( LOC => "SLICE_X21Y54", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0013, O => write_send_data_51_DXMUX_4908 ); write_send_data_51_DYMUX : X_BUF generic map( LOC => "SLICE_X21Y54", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0014, O => write_send_data_51_DYMUX_4895 ); write_send_data_51_SRINV : X_BUF generic map( LOC => "SLICE_X21Y54", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_51_SRINV_4887 ); write_send_data_51_CLKINV : X_INV generic map( LOC => "SLICE_X21Y54", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_51_CLKINVNOT ); write_send_data_51_CEINV : X_BUF generic map( LOC => "SLICE_X21Y54", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_51_CEINV_4885 ); write_send_data_43_DXMUX : X_BUF generic map( LOC => "SLICE_X22Y49", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0021, O => write_send_data_43_DXMUX_4950 ); write_send_data_43_DYMUX : X_BUF generic map( LOC => "SLICE_X22Y49", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0022, O => write_send_data_43_DYMUX_4937 ); write_send_data_43_SRINV : X_BUF generic map( LOC => "SLICE_X22Y49", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_43_SRINV_4929 ); write_send_data_43_CLKINV : X_INV generic map( LOC => "SLICE_X22Y49", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_43_CLKINVNOT ); write_send_data_43_CEINV : X_BUF generic map( LOC => "SLICE_X22Y49", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_43_CEINV_4927 ); write_send_data_35_DXMUX : X_BUF generic map( LOC => "SLICE_X21Y41", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0029, O => write_send_data_35_DXMUX_4992 ); write_send_data_35_DYMUX : X_BUF generic map( LOC => "SLICE_X21Y41", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0030, O => write_send_data_35_DYMUX_4979 ); write_send_data_35_SRINV : X_BUF generic map( LOC => "SLICE_X21Y41", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_35_SRINV_4971 ); write_send_data_35_CLKINV : X_INV generic map( LOC => "SLICE_X21Y41", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_35_CLKINVNOT ); write_send_data_35_CEINV : X_BUF generic map( LOC => "SLICE_X21Y41", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_35_CEINV_4969 ); write_send_data_27_DXMUX : X_BUF generic map( LOC => "SLICE_X19Y15", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0037, O => write_send_data_27_DXMUX_5034 ); write_send_data_27_DYMUX : X_BUF generic map( LOC => "SLICE_X19Y15", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0038, O => write_send_data_27_DYMUX_5020 ); write_send_data_27_SRINV : X_BUF generic map( LOC => "SLICE_X19Y15", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_27_SRINV_5011 ); write_send_data_27_CLKINV : X_INV generic map( LOC => "SLICE_X19Y15", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_27_CLKINVNOT ); write_send_data_27_CEINV : X_BUF generic map( LOC => "SLICE_X19Y15", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_27_CEINV_5009 ); write_send_data_mux00461 : X_LUT4 generic map( INIT => X"ACAC", LOC => "SLICE_X2Y14" ) port map ( ADR0 => latched_reg_addr(0), ADR1 => write_send_data(17), ADR2 => read_send_data_11_not0001_inv, ADR3 => VCC, O => write_send_data_mux0046 ); write_send_data_mux00451 : X_LUT4 generic map( INIT => X"CFC0", LOC => "SLICE_X2Y14" ) port map ( ADR0 => VCC, ADR1 => latched_reg_addr(1), ADR2 => read_send_data_11_not0001_inv, ADR3 => write_send_data(18), O => write_send_data_mux0045 ); write_send_data_19_DXMUX : X_BUF generic map( LOC => "SLICE_X2Y14", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0045, O => write_send_data_19_DXMUX_5076 ); write_send_data_19_DYMUX : X_BUF generic map( LOC => "SLICE_X2Y14", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0046, O => write_send_data_19_DYMUX_5062 ); write_send_data_19_SRINV : X_BUF generic map( LOC => "SLICE_X2Y14", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_19_SRINV_5053 ); write_send_data_19_CLKINV : X_INV generic map( LOC => "SLICE_X2Y14", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_19_CLKINVNOT ); write_send_data_19_CEINV : X_BUF generic map( LOC => "SLICE_X2Y14", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_19_CEINV_5051 ); read_send_data_7_mux00001 : X_LUT4 generic map( INIT => X"F0CC", LOC => "SLICE_X1Y28" ) port map ( ADR0 => VCC, ADR1 => read_send_data(6), ADR2 => phy_addr_2_IBUF_1391, ADR3 => read_send_data_11_not0001_inv, O => read_send_data_7_mux0000 ); read_send_data_6_mux00001 : X_LUT4 generic map( INIT => X"E2E2", LOC => "SLICE_X1Y28" ) port map ( ADR0 => read_send_data(5), ADR1 => read_send_data_11_not0001_inv, ADR2 => phy_addr_1_IBUF_1386, ADR3 => VCC, O => read_send_data_6_mux0000 ); read_send_data_7_DXMUX : X_BUF generic map( LOC => "SLICE_X1Y28", PATHPULSE => 638 ps ) port map ( I => read_send_data_7_mux0000, O => read_send_data_7_DXMUX_5118 ); read_send_data_7_DYMUX : X_BUF generic map( LOC => "SLICE_X1Y28", PATHPULSE => 638 ps ) port map ( I => read_send_data_6_mux0000, O => read_send_data_7_DYMUX_5104 ); read_send_data_7_SRINV : X_BUF generic map( LOC => "SLICE_X1Y28", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_7_SRINV_5095 ); read_send_data_7_CLKINV : X_INV generic map( LOC => "SLICE_X1Y28", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_7_CLKINVNOT ); read_send_data_7_CEINV : X_BUF generic map( LOC => "SLICE_X1Y28", PATHPULSE => 638 ps ) port map ( I => read_send_data_0_not0001_0, O => read_send_data_7_CEINV_5093 ); write_send_data_61_DXMUX : X_BUF generic map( LOC => "SLICE_X17Y43", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0003, O => write_send_data_61_DXMUX_5160 ); write_send_data_61_DYMUX : X_BUF generic map( LOC => "SLICE_X17Y43", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0004, O => write_send_data_61_DYMUX_5147 ); write_send_data_61_SRINV : X_BUF generic map( LOC => "SLICE_X17Y43", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_61_SRINV_5139 ); write_send_data_61_CLKINV : X_INV generic map( LOC => "SLICE_X17Y43", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_61_CLKINVNOT ); write_send_data_61_CEINV : X_BUF generic map( LOC => "SLICE_X17Y43", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_61_CEINV_5137 ); write_send_data_53_DXMUX : X_BUF generic map( LOC => "SLICE_X22Y55", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0011, O => write_send_data_53_DXMUX_5202 ); write_send_data_53_DYMUX : X_BUF generic map( LOC => "SLICE_X22Y55", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0012, O => write_send_data_53_DYMUX_5189 ); write_send_data_53_SRINV : X_BUF generic map( LOC => "SLICE_X22Y55", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_53_SRINV_5181 ); write_send_data_53_CLKINV : X_INV generic map( LOC => "SLICE_X22Y55", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_53_CLKINVNOT ); write_send_data_53_CEINV : X_BUF generic map( LOC => "SLICE_X22Y55", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_53_CEINV_5179 ); write_send_data_mux00201 : X_LUT4 generic map( INIT => X"F0F2", LOC => "SLICE_X21Y53" ) port map ( ADR0 => N3, ADR1 => bit_counter(6), ADR2 => write_send_data(43), ADR3 => read_receive_data_0_cmp_gt00001_1316, O => write_send_data_mux0020 ); write_send_data_44 : X_SFF generic map( LOC => "SLICE_X21Y53", INIT => '0' ) port map ( I => write_send_data_45_DYMUX_5231, CE => write_send_data_45_CEINV_5221, CLK => write_send_data_45_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_45_SRINV_5223, O => write_send_data(44) ); write_send_data_mux00191 : X_LUT4 generic map( INIT => X"FF02", LOC => "SLICE_X21Y53" ) port map ( ADR0 => N3, ADR1 => bit_counter(6), ADR2 => read_receive_data_0_cmp_gt00001_1316, ADR3 => write_send_data(44), O => write_send_data_mux0019 ); write_send_data_45 : X_SFF generic map( LOC => "SLICE_X21Y53", INIT => '0' ) port map ( I => write_send_data_45_DXMUX_5244, CE => write_send_data_45_CEINV_5221, CLK => write_send_data_45_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_45_SRINV_5223, O => write_send_data(45) ); write_send_data_45_DXMUX : X_BUF generic map( LOC => "SLICE_X21Y53", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0019, O => write_send_data_45_DXMUX_5244 ); write_send_data_45_DYMUX : X_BUF generic map( LOC => "SLICE_X21Y53", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0020, O => write_send_data_45_DYMUX_5231 ); write_send_data_45_SRINV : X_BUF generic map( LOC => "SLICE_X21Y53", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_45_SRINV_5223 ); write_send_data_45_CLKINV : X_INV generic map( LOC => "SLICE_X21Y53", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_45_CLKINVNOT ); write_send_data_45_CEINV : X_BUF generic map( LOC => "SLICE_X21Y53", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_45_CEINV_5221 ); write_send_data_mux00281 : X_LUT4 generic map( INIT => X"AAAE", LOC => "SLICE_X20Y47" ) port map ( ADR0 => write_send_data(35), ADR1 => N3, ADR2 => bit_counter(6), ADR3 => read_receive_data_0_cmp_gt00001_1316, O => write_send_data_mux0028 ); write_send_data_36 : X_SFF generic map( LOC => "SLICE_X20Y47", INIT => '0' ) port map ( I => write_send_data_37_DYMUX_5273, CE => write_send_data_37_CEINV_5263, CLK => write_send_data_37_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_37_SRINV_5265, O => write_send_data(36) ); write_send_data_mux00271 : X_LUT4 generic map( INIT => X"FF02", LOC => "SLICE_X20Y47" ) port map ( ADR0 => N3, ADR1 => read_receive_data_0_cmp_gt00001_1316, ADR2 => bit_counter(6), ADR3 => write_send_data(36), O => write_send_data_mux0027 ); write_send_data_37 : X_SFF generic map( LOC => "SLICE_X20Y47", INIT => '0' ) port map ( I => write_send_data_37_DXMUX_5286, CE => write_send_data_37_CEINV_5263, CLK => write_send_data_37_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_37_SRINV_5265, O => write_send_data(37) ); write_send_data_37_DXMUX : X_BUF generic map( LOC => "SLICE_X20Y47", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0027, O => write_send_data_37_DXMUX_5286 ); write_send_data_37_DYMUX : X_BUF generic map( LOC => "SLICE_X20Y47", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0028, O => write_send_data_37_DYMUX_5273 ); write_send_data_37_SRINV : X_BUF generic map( LOC => "SLICE_X20Y47", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_37_SRINV_5265 ); write_send_data_37_CLKINV : X_INV generic map( LOC => "SLICE_X20Y47", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_37_CLKINVNOT ); write_send_data_37_CEINV : X_BUF generic map( LOC => "SLICE_X20Y47", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_37_CEINV_5263 ); write_send_data_mux00361 : X_LUT4 generic map( INIT => X"F1F0", LOC => "SLICE_X22Y30" ) port map ( ADR0 => read_receive_data_0_cmp_gt00001_1316, ADR1 => bit_counter(6), ADR2 => write_send_data(27), ADR3 => N3, O => write_send_data_mux0036 ); write_send_data_28 : X_SFF generic map( LOC => "SLICE_X22Y30", INIT => '0' ) port map ( I => write_send_data_29_DYMUX_5315, CE => write_send_data_29_CEINV_5305, CLK => write_send_data_29_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_29_SRINV_5307, O => write_send_data(28) ); write_send_data_mux00351 : X_LUT4 generic map( INIT => X"FB00", LOC => "SLICE_X22Y30" ) port map ( ADR0 => bit_counter(6), ADR1 => N3, ADR2 => read_receive_data_0_cmp_gt00001_1316, ADR3 => write_send_data(28), O => write_send_data_mux0035 ); write_send_data_29 : X_SFF generic map( LOC => "SLICE_X22Y30", INIT => '0' ) port map ( I => write_send_data_29_DXMUX_5328, CE => write_send_data_29_CEINV_5305, CLK => write_send_data_29_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_29_SRINV_5307, O => write_send_data(29) ); write_send_data_29_DXMUX : X_BUF generic map( LOC => "SLICE_X22Y30", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0035, O => write_send_data_29_DXMUX_5328 ); write_send_data_29_DYMUX : X_BUF generic map( LOC => "SLICE_X22Y30", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0036, O => write_send_data_29_DYMUX_5315 ); write_send_data_29_SRINV : X_BUF generic map( LOC => "SLICE_X22Y30", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_29_SRINV_5307 ); write_send_data_29_CLKINV : X_INV generic map( LOC => "SLICE_X22Y30", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_29_CLKINVNOT ); write_send_data_29_CEINV : X_BUF generic map( LOC => "SLICE_X22Y30", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_29_CEINV_5305 ); read_send_data_8_mux00001 : X_LUT4 generic map( INIT => X"CCAA", LOC => "SLICE_X2Y24" ) port map ( ADR0 => read_send_data(7), ADR1 => phy_addr_3_IBUF_1390, ADR2 => VCC, ADR3 => read_send_data_11_not0001_inv, O => read_send_data_8_mux0000 ); read_send_data_8 : X_SFF generic map( LOC => "SLICE_X2Y24", INIT => '0' ) port map ( I => read_send_data_9_DYMUX_5356, CE => read_send_data_9_CEINV_5345, CLK => read_send_data_9_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => read_send_data_9_SRINV_5347, O => read_send_data(8) ); read_send_data_9_mux00001 : X_LUT4 generic map( INIT => X"F3C0", LOC => "SLICE_X2Y24" ) port map ( ADR0 => VCC, ADR1 => read_send_data_11_not0001_inv, ADR2 => phy_addr_4_IBUF_1394, ADR3 => read_send_data(8), O => read_send_data_9_mux0000 ); read_send_data_9_DXMUX : X_BUF generic map( LOC => "SLICE_X2Y24", PATHPULSE => 638 ps ) port map ( I => read_send_data_9_mux0000, O => read_send_data_9_DXMUX_5370 ); read_send_data_9_DYMUX : X_BUF generic map( LOC => "SLICE_X2Y24", PATHPULSE => 638 ps ) port map ( I => read_send_data_8_mux0000, O => read_send_data_9_DYMUX_5356 ); read_send_data_9_SRINV : X_BUF generic map( LOC => "SLICE_X2Y24", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => read_send_data_9_SRINV_5347 ); read_send_data_9_CLKINV : X_INV generic map( LOC => "SLICE_X2Y24", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => read_send_data_9_CLKINVNOT ); read_send_data_9_CEINV : X_BUF generic map( LOC => "SLICE_X2Y24", PATHPULSE => 638 ps ) port map ( I => read_send_data_0_not0001_0, O => read_send_data_9_CEINV_5345 ); write_send_data_mux00011 : X_LUT4 generic map( INIT => X"AAAE", LOC => "SLICE_X15Y42" ) port map ( ADR0 => write_send_data(62), ADR1 => N3, ADR2 => read_receive_data_0_cmp_gt00001_1316, ADR3 => bit_counter(6), O => write_send_data_mux0001 ); write_send_data_mux00021 : X_LUT4 generic map( INIT => X"CCCE", LOC => "SLICE_X15Y42" ) port map ( ADR0 => N3, ADR1 => write_send_data(61), ADR2 => read_receive_data_0_cmp_gt00001_1316, ADR3 => bit_counter(6), O => write_send_data_mux0002 ); write_send_data_63_DXMUX : X_BUF generic map( LOC => "SLICE_X15Y42", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0001, O => write_send_data_63_DXMUX_5412 ); write_send_data_63_DYMUX : X_BUF generic map( LOC => "SLICE_X15Y42", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0002, O => write_send_data_63_DYMUX_5399 ); write_send_data_63_SRINV : X_BUF generic map( LOC => "SLICE_X15Y42", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_63_SRINV_5391 ); write_send_data_63_CLKINV : X_INV generic map( LOC => "SLICE_X15Y42", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_63_CLKINVNOT ); write_send_data_63_CEINV : X_BUF generic map( LOC => "SLICE_X15Y42", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_63_CEINV_5389 ); write_send_data_55_DXMUX : X_BUF generic map( LOC => "SLICE_X20Y54", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0009, O => write_send_data_55_DXMUX_5454 ); write_send_data_55_DYMUX : X_BUF generic map( LOC => "SLICE_X20Y54", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0010, O => write_send_data_55_DYMUX_5441 ); write_send_data_55_SRINV : X_BUF generic map( LOC => "SLICE_X20Y54", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_55_SRINV_5433 ); write_send_data_55_CLKINV : X_INV generic map( LOC => "SLICE_X20Y54", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_55_CLKINVNOT ); write_send_data_55_CEINV : X_BUF generic map( LOC => "SLICE_X20Y54", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_55_CEINV_5431 ); write_send_data_47_DXMUX : X_BUF generic map( LOC => "SLICE_X21Y55", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0017, O => write_send_data_47_DXMUX_5496 ); write_send_data_47_DYMUX : X_BUF generic map( LOC => "SLICE_X21Y55", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0018, O => write_send_data_47_DYMUX_5483 ); write_send_data_47_SRINV : X_BUF generic map( LOC => "SLICE_X21Y55", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_47_SRINV_5475 ); write_send_data_47_CLKINV : X_INV generic map( LOC => "SLICE_X21Y55", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_47_CLKINVNOT ); write_send_data_47_CEINV : X_BUF generic map( LOC => "SLICE_X21Y55", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_47_CEINV_5473 ); write_send_data_39_DXMUX : X_BUF generic map( LOC => "SLICE_X20Y49", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0025, O => write_send_data_39_DXMUX_5538 ); write_send_data_39_DYMUX : X_BUF generic map( LOC => "SLICE_X20Y49", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0026, O => write_send_data_39_DYMUX_5525 ); write_send_data_39_SRINV : X_BUF generic map( LOC => "SLICE_X20Y49", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_39_SRINV_5517 ); write_send_data_39_CLKINV : X_INV generic map( LOC => "SLICE_X20Y49", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_39_CLKINVNOT ); write_send_data_39_CEINV : X_BUF generic map( LOC => "SLICE_X20Y49", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_39_CEINV_5515 ); write_send_data_57_DXMUX : X_BUF generic map( LOC => "SLICE_X19Y52", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0007, O => write_send_data_57_DXMUX_5580 ); write_send_data_57_DYMUX : X_BUF generic map( LOC => "SLICE_X19Y52", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0008, O => write_send_data_57_DYMUX_5567 ); write_send_data_57_SRINV : X_BUF generic map( LOC => "SLICE_X19Y52", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_57_SRINV_5559 ); write_send_data_57_CLKINV : X_INV generic map( LOC => "SLICE_X19Y52", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_57_CLKINVNOT ); write_send_data_57_CEINV : X_BUF generic map( LOC => "SLICE_X19Y52", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_57_CEINV_5557 ); write_send_data_49_DXMUX : X_BUF generic map( LOC => "SLICE_X20Y55", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0015, O => write_send_data_49_DXMUX_5622 ); write_send_data_49_DYMUX : X_BUF generic map( LOC => "SLICE_X20Y55", PATHPULSE => 638 ps ) port map ( I => write_send_data_mux0016, O => write_send_data_49_DYMUX_5609 ); write_send_data_49_SRINV : X_BUF generic map( LOC => "SLICE_X20Y55", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => write_send_data_49_SRINV_5601 ); write_send_data_49_CLKINV : X_INV generic map( LOC => "SLICE_X20Y55", PATHPULSE => 638 ps ) port map ( I => clk_div_1313, O => write_send_data_49_CLKINVNOT ); write_send_data_49_CEINV : X_BUF generic map( LOC => "SLICE_X20Y55", PATHPULSE => 638 ps ) port map ( I => write_send_data_not0001_0, O => write_send_data_49_CEINV_5599 ); read_receive_data_8 : X_SFF generic map( LOC => "SLICE_X2Y77", INIT => '0' ) port map ( I => read_receive_data_9_DYMUX_1886, CE => read_receive_data_9_CEINV_1882, CLK => read_receive_data_9_CLKINV_1883, SET => GND, RST => GND, SSET => GND, SRST => read_receive_data_9_SRINV_1884, O => read_receive_data(8) ); read_send_data_27_rt : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X25Y70" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => read_send_data(27), O => read_send_data_27_rt_2900 ); latched_data_1 : X_FF generic map( LOC => "IPAD224", INIT => '0' ) port map ( I => data_in_1_IFF_IDDRIN_MUX_3745, CE => data_in_1_IFF_ICEINV_3747, CLK => data_in_1_IFF_ICLK1INV_3749, SET => GND, RST => GND, O => latched_data(1) ); data_in_1_IFF_IDDRIN_MUX : X_BUF generic map( LOC => "IPAD224", PATHPULSE => 638 ps ) port map ( I => data_in_1_INBUF, O => data_in_1_IFF_IDDRIN_MUX_3745 ); data_in_1_IFF_ICLK1INV : X_BUF generic map( LOC => "IPAD224", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => data_in_1_IFF_ICLK1INV_3749 ); data_in_1_IFF_ICEINV : X_BUF generic map( LOC => "IPAD224", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => data_in_1_IFF_ICEINV_3747 ); latched_data_10 : X_FF generic map( LOC => "PAD203", INIT => '0' ) port map ( I => data_in_10_IFF_IDDRIN_MUX_3773, CE => data_in_10_IFF_ICEINV_3775, CLK => data_in_10_IFF_ICLK1INV_3777, SET => GND, RST => GND, O => latched_data(10) ); data_in_10_IFF_IDDRIN_MUX : X_BUF generic map( LOC => "PAD203", PATHPULSE => 638 ps ) port map ( I => data_in_10_INBUF, O => data_in_10_IFF_IDDRIN_MUX_3773 ); data_in_10_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD203", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => data_in_10_IFF_ICLK1INV_3777 ); data_in_10_IFF_ICEINV : X_BUF generic map( LOC => "PAD203", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => data_in_10_IFF_ICEINV_3775 ); latched_data_14 : X_FF generic map( LOC => "PAD197", INIT => '0' ) port map ( I => data_in_14_IFF_IDDRIN_MUX_3969, CE => data_in_14_IFF_ICEINV_3971, CLK => data_in_14_IFF_ICLK1INV_3973, SET => GND, RST => GND, O => latched_data(14) ); data_in_14_IFF_IDDRIN_MUX : X_BUF generic map( LOC => "PAD197", PATHPULSE => 638 ps ) port map ( I => data_in_14_INBUF, O => data_in_14_IFF_IDDRIN_MUX_3969 ); data_in_14_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD197", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => data_in_14_IFF_ICLK1INV_3973 ); data_in_14_IFF_ICEINV : X_BUF generic map( LOC => "PAD197", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => data_in_14_IFF_ICEINV_3971 ); write_send_data_53 : X_SFF generic map( LOC => "SLICE_X22Y55", INIT => '0' ) port map ( I => write_send_data_53_DXMUX_5202, CE => write_send_data_53_CEINV_5179, CLK => write_send_data_53_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_53_SRINV_5181, O => write_send_data(53) ); write_send_data_mux00121 : X_LUT4 generic map( INIT => X"CCCE", LOC => "SLICE_X22Y55" ) port map ( ADR0 => N3, ADR1 => write_send_data(51), ADR2 => bit_counter(6), ADR3 => read_receive_data_0_cmp_gt00001_1316, O => write_send_data_mux0012 ); write_send_data_52 : X_SFF generic map( LOC => "SLICE_X22Y55", INIT => '0' ) port map ( I => write_send_data_53_DYMUX_5189, CE => write_send_data_53_CEINV_5179, CLK => write_send_data_53_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_53_SRINV_5181, O => write_send_data(52) ); write_send_data_mux00111 : X_LUT4 generic map( INIT => X"FF04", LOC => "SLICE_X22Y55" ) port map ( ADR0 => read_receive_data_0_cmp_gt00001_1316, ADR1 => N3, ADR2 => bit_counter(6), ADR3 => write_send_data(52), O => write_send_data_mux0011 ); write_send_data_61 : X_SFF generic map( LOC => "SLICE_X17Y43", INIT => '0' ) port map ( I => write_send_data_61_DXMUX_5160, CE => write_send_data_61_CEINV_5137, CLK => write_send_data_61_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_61_SRINV_5139, O => write_send_data(61) ); write_send_data_mux00041 : X_LUT4 generic map( INIT => X"FF04", LOC => "SLICE_X17Y43" ) port map ( ADR0 => bit_counter(6), ADR1 => N3, ADR2 => read_receive_data_0_cmp_gt00001_1316, ADR3 => write_send_data(59), O => write_send_data_mux0004 ); write_send_data_60 : X_SFF generic map( LOC => "SLICE_X17Y43", INIT => '0' ) port map ( I => write_send_data_61_DYMUX_5147, CE => write_send_data_61_CEINV_5137, CLK => write_send_data_61_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_61_SRINV_5139, O => write_send_data(60) ); write_send_data_mux00031 : X_LUT4 generic map( INIT => X"FF04", LOC => "SLICE_X17Y43" ) port map ( ADR0 => bit_counter(6), ADR1 => N3, ADR2 => read_receive_data_0_cmp_gt00001_1316, ADR3 => write_send_data(60), O => write_send_data_mux0003 ); read_send_data_7 : X_SFF generic map( LOC => "SLICE_X1Y28", INIT => '0' ) port map ( I => read_send_data_7_DXMUX_5118, CE => read_send_data_7_CEINV_5093, CLK => read_send_data_7_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => read_send_data_7_SRINV_5095, O => read_send_data(7) ); read_send_data_6 : X_SFF generic map( LOC => "SLICE_X1Y28", INIT => '0' ) port map ( I => read_send_data_7_DYMUX_5104, CE => read_send_data_7_CEINV_5093, CLK => read_send_data_7_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => read_send_data_7_SRINV_5095, O => read_send_data(6) ); write_send_data_19 : X_SFF generic map( LOC => "SLICE_X2Y14", INIT => '0' ) port map ( I => write_send_data_19_DXMUX_5076, CE => write_send_data_19_CEINV_5051, CLK => write_send_data_19_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_19_SRINV_5053, O => write_send_data(19) ); write_send_data_18 : X_SFF generic map( LOC => "SLICE_X2Y14", INIT => '0' ) port map ( I => write_send_data_19_DYMUX_5062, CE => write_send_data_19_CEINV_5051, CLK => write_send_data_19_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_19_SRINV_5053, O => write_send_data(18) ); write_send_data_mux00101 : X_LUT4 generic map( INIT => X"CDCC", LOC => "SLICE_X20Y54" ) port map ( ADR0 => read_receive_data_0_cmp_gt00001_1316, ADR1 => write_send_data(53), ADR2 => bit_counter(6), ADR3 => N3, O => write_send_data_mux0010 ); write_send_data_63 : X_SFF generic map( LOC => "SLICE_X15Y42", INIT => '0' ) port map ( I => write_send_data_63_DXMUX_5412, CE => write_send_data_63_CEINV_5389, CLK => write_send_data_63_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_63_SRINV_5391, O => write_send_data(63) ); write_send_data_62 : X_SFF generic map( LOC => "SLICE_X15Y42", INIT => '0' ) port map ( I => write_send_data_63_DYMUX_5399, CE => write_send_data_63_CEINV_5389, CLK => write_send_data_63_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_63_SRINV_5391, O => write_send_data(62) ); read_send_data_9 : X_SFF generic map( LOC => "SLICE_X2Y24", INIT => '0' ) port map ( I => read_send_data_9_DXMUX_5370, CE => read_send_data_9_CEINV_5345, CLK => read_send_data_9_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => read_send_data_9_SRINV_5347, O => read_send_data(9) ); latched_reg_addr_3 : X_FF generic map( LOC => "SLICE_X3Y8", INIT => '0' ) port map ( I => latched_reg_addr_3_DXMUX_1934, CE => latched_reg_addr_3_CEINV_1925, CLK => latched_reg_addr_3_CLKINV_1926, SET => GND, RST => GND, O => latched_reg_addr(3) ); latched_reg_addr_4 : X_FF generic map( LOC => "SLICE_X13Y8", INIT => '0' ) port map ( I => latched_reg_addr_4_DYMUX_1946, CE => latched_reg_addr_4_CEINV_1943, CLK => latched_reg_addr_4_CLKINV_1944, SET => GND, RST => GND, O => latched_reg_addr(4) ); write_send_data_mux00061 : X_LUT4 generic map( INIT => X"ABAA", LOC => "SLICE_X19Y47" ) port map ( ADR0 => write_send_data(57), ADR1 => bit_counter(6), ADR2 => read_receive_data_0_cmp_gt00001_1316, ADR3 => N3, O => write_send_data_mux0006 ); write_send_data_58 : X_SFF generic map( LOC => "SLICE_X19Y47", INIT => '0' ) port map ( I => write_send_data_59_DYMUX_1565, CE => write_send_data_59_CEINV_1555, CLK => write_send_data_59_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_59_SRINV_1557, O => write_send_data(58) ); write_send_data_mux00051 : X_LUT4 generic map( INIT => X"FF04", LOC => "SLICE_X19Y47" ) port map ( ADR0 => bit_counter(6), ADR1 => N3, ADR2 => read_receive_data_0_cmp_gt00001_1316, ADR3 => write_send_data(58), O => write_send_data_mux0005 ); write_send_data_59 : X_SFF generic map( LOC => "SLICE_X19Y47", INIT => '0' ) port map ( I => write_send_data_59_DXMUX_1578, CE => write_send_data_59_CEINV_1555, CLK => write_send_data_59_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_59_SRINV_1557, O => write_send_data(59) ); write_send_data_mux00621 : X_LUT4 generic map( INIT => X"1000", LOC => "SLICE_X3Y75" ) port map ( ADR0 => bit_counter(6), ADR1 => read_receive_data_0_cmp_gt00001_1316, ADR2 => latched_data(0), ADR3 => N3, O => write_send_data_mux0062 ); write_send_data_0 : X_SFF generic map( LOC => "SLICE_X3Y75", INIT => '0' ) port map ( I => write_send_data_0_DYMUX_1607, CE => write_send_data_0_CEINV_1597, CLK => write_send_data_0_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_0_SRINV_1599, O => write_send_data(0) ); read_send_data_10_or00001 : X_LUT4 generic map( INIT => X"F0F2", LOC => "SLICE_X3Y75" ) port map ( ADR0 => N3, ADR1 => read_receive_data_0_cmp_gt00001_1316, ADR2 => reset_IBUF_1314, ADR3 => bit_counter(6), O => read_send_data_10_or0000 ); write_send_data_mux00601 : X_LUT4 generic map( INIT => X"CFC0", LOC => "SLICE_X1Y65" ) port map ( ADR0 => VCC, ADR1 => latched_data(2), ADR2 => read_send_data_11_not0001_inv, ADR3 => write_send_data(1), O => write_send_data_mux0060 ); write_send_data_2 : X_SFF generic map( LOC => "SLICE_X1Y65", INIT => '0' ) port map ( I => write_send_data_3_DYMUX_1642, CE => write_send_data_3_CEINV_1631, CLK => write_send_data_3_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_3_SRINV_1633, O => write_send_data(2) ); write_send_data_mux00591 : X_LUT4 generic map( INIT => X"F0AA", LOC => "SLICE_X1Y65" ) port map ( ADR0 => write_send_data(2), ADR1 => VCC, ADR2 => latched_data(3), ADR3 => read_send_data_11_not0001_inv, O => write_send_data_mux0059 ); write_send_data_3 : X_SFF generic map( LOC => "SLICE_X1Y65", INIT => '0' ) port map ( I => write_send_data_3_DXMUX_1656, CE => write_send_data_3_CEINV_1631, CLK => write_send_data_3_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_3_SRINV_1633, O => write_send_data(3) ); write_send_data_mux00581 : X_LUT4 generic map( INIT => X"CFC0", LOC => "SLICE_X0Y54" ) port map ( ADR0 => VCC, ADR1 => latched_data(4), ADR2 => read_send_data_11_not0001_inv, ADR3 => write_send_data(3), O => write_send_data_mux0058 ); write_send_data_4 : X_SFF generic map( LOC => "SLICE_X0Y54", INIT => '0' ) port map ( I => write_send_data_5_DYMUX_1684, CE => write_send_data_5_CEINV_1673, CLK => write_send_data_5_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_5_SRINV_1675, O => write_send_data(4) ); write_send_data_mux00571 : X_LUT4 generic map( INIT => X"CFC0", LOC => "SLICE_X0Y54" ) port map ( ADR0 => VCC, ADR1 => latched_data(5), ADR2 => read_send_data_11_not0001_inv, ADR3 => write_send_data(4), O => write_send_data_mux0057 ); write_send_data_5 : X_SFF generic map( LOC => "SLICE_X0Y54", INIT => '0' ) port map ( I => write_send_data_5_DXMUX_1698, CE => write_send_data_5_CEINV_1673, CLK => write_send_data_5_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_5_SRINV_1675, O => write_send_data(5) ); write_send_data_mux00561 : X_LUT4 generic map( INIT => X"E4E4", LOC => "SLICE_X0Y51" ) port map ( ADR0 => read_send_data_11_not0001_inv, ADR1 => write_send_data(5), ADR2 => latched_data(6), ADR3 => VCC, O => write_send_data_mux0056 ); write_send_data_6 : X_SFF generic map( LOC => "SLICE_X0Y51", INIT => '0' ) port map ( I => write_send_data_7_DYMUX_1726, CE => write_send_data_7_CEINV_1715, CLK => write_send_data_7_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_7_SRINV_1717, O => write_send_data(6) ); write_send_data_mux00551 : X_LUT4 generic map( INIT => X"CFC0", LOC => "SLICE_X0Y51" ) port map ( ADR0 => VCC, ADR1 => latched_data(7), ADR2 => read_send_data_11_not0001_inv, ADR3 => write_send_data(6), O => write_send_data_mux0055 ); write_send_data_7 : X_SFF generic map( LOC => "SLICE_X0Y51", INIT => '0' ) port map ( I => write_send_data_7_DXMUX_1740, CE => write_send_data_7_CEINV_1715, CLK => write_send_data_7_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_7_SRINV_1717, O => write_send_data(7) ); write_send_data_mux00541 : X_LUT4 generic map( INIT => X"FC0C", LOC => "SLICE_X0Y48" ) port map ( ADR0 => VCC, ADR1 => write_send_data(7), ADR2 => read_send_data_11_not0001_inv, ADR3 => latched_data(8), O => write_send_data_mux0054 ); write_send_data_8 : X_SFF generic map( LOC => "SLICE_X0Y48", INIT => '0' ) port map ( I => write_send_data_9_DYMUX_1768, CE => write_send_data_9_CEINV_1757, CLK => write_send_data_9_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_9_SRINV_1759, O => write_send_data(8) ); write_send_data_mux00531 : X_LUT4 generic map( INIT => X"CFC0", LOC => "SLICE_X0Y48" ) port map ( ADR0 => VCC, ADR1 => latched_data(9), ADR2 => read_send_data_11_not0001_inv, ADR3 => write_send_data(8), O => write_send_data_mux0053 ); write_send_data_9 : X_SFF generic map( LOC => "SLICE_X0Y48", INIT => '0' ) port map ( I => write_send_data_9_DXMUX_1782, CE => write_send_data_9_CEINV_1757, CLK => write_send_data_9_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_9_SRINV_1759, O => write_send_data(9) ); Mtridata_MDIO_mux00001 : X_LUT4 generic map( INIT => X"D8F0", LOC => "SLICE_X2Y56" ) port map ( ADR0 => latched_write_read_1343, ADR1 => write_send_data(63), ADR2 => read_send_data(45), ADR3 => Mtridata_MDIO_and0000135, O => Mtridata_MDIO_mux0000 ); Mtridata_MDIO : X_FF generic map( LOC => "SLICE_X2Y56", INIT => '0' ) port map ( I => Mtridata_MDIO_DYMUX_1805, CE => VCC, CLK => Mtridata_MDIO_CLKINV_1797, SET => GND, RST => GND, O => Mtridata_MDIO_1348 ); Mtridata_MDIO_and0000146 : X_LUT4 generic map( INIT => X"8888", LOC => "SLICE_X2Y56" ) port map ( ADR0 => latched_write_read_1343, ADR1 => Mtridata_MDIO_and0000135, ADR2 => VCC, ADR3 => VCC, O => Mtridata_MDIO_and0000 ); Mtrien_MDIO_mux0000_norst : X_LUT4 generic map( INIT => X"F7F5", LOC => "SLICE_X3Y57" ) port map ( ADR0 => read_send_data_0_cmp_lt0000, ADR1 => read_receive_data_0_cmp_gt00001_1316, ADR2 => latched_write_read_1343, ADR3 => N6_0, O => Mtrien_MDIO_mux0000_norst_1836 ); Mtrien_MDIO : X_SFF generic map( LOC => "SLICE_X3Y57", INIT => '0' ) port map ( I => Mtrien_MDIO_DYMUX_1839, CE => VCC, CLK => Mtrien_MDIO_CLKINV_1830, SET => GND, RST => GND, SSET => GND, SRST => Mtrien_MDIO_SRINV_1831, O => Mtrien_MDIO_1353 ); read_send_data_0_not00011 : X_LUT4 generic map( INIT => X"FF02", LOC => "SLICE_X3Y57" ) port map ( ADR0 => N3, ADR1 => read_receive_data_0_cmp_gt00001_1316, ADR2 => bit_counter(6), ADR3 => read_send_data_10_and0000_0, O => read_send_data_0_not0001 ); read_receive_data_6 : X_SFF generic map( LOC => "SLICE_X2Y80", INIT => '0' ) port map ( I => read_receive_data_7_DYMUX_1862, CE => read_receive_data_7_CEINV_1858, CLK => read_receive_data_7_CLKINV_1859, SET => GND, RST => GND, SSET => GND, SRST => read_receive_data_7_SRINV_1860, O => read_receive_data(6) ); read_receive_data_7 : X_SFF generic map( LOC => "SLICE_X2Y80", INIT => '0' ) port map ( I => read_receive_data_7_DXMUX_1869, CE => read_receive_data_7_CEINV_1858, CLK => read_receive_data_7_CLKINV_1859, SET => GND, RST => GND, SSET => GND, SRST => read_receive_data_7_SRINV_1860, O => read_receive_data(7) ); read_receive_data_0_cmp_gt00001_1 : X_LUT4 generic map( INIT => X"FFFE", LOC => "SLICE_X14Y81" ) port map ( ADR0 => bit_counter(2), ADR1 => bit_counter(1), ADR2 => bit_counter(0), ADR3 => bit_counter(3), O => read_receive_data_0_cmp_gt000011 ); read_send_data_0_cmp_lt0000134 : X_LUT4 generic map( INIT => X"0033", LOC => "SLICE_X3Y65" ) port map ( ADR0 => VCC, ADR1 => bit_counter(6), ADR2 => VCC, ADR3 => bit_counter(7), O => read_send_data_0_cmp_lt0000134_1989 ); Mtrien_MDIO_mux0000_norst_SW0 : X_LUT4 generic map( INIT => X"0001", LOC => "SLICE_X3Y65" ) port map ( ADR0 => bit_counter(4), ADR1 => bit_counter(6), ADR2 => bit_counter(5), ADR3 => bit_counter(7), O => N6 ); write_send_data_and0000_SW0 : X_LUT4 generic map( INIT => X"0055", LOC => "SLICE_X13Y78" ) port map ( ADR0 => bit_counter(4), ADR1 => VCC, ADR2 => VCC, ADR3 => bit_counter(5), O => N8 ); read_send_data_10_and0000_SW0 : X_LUT4 generic map( INIT => X"FFEE", LOC => "SLICE_X13Y78" ) port map ( ADR0 => bit_counter(4), ADR1 => bit_counter(5), ADR2 => VCC, ADR3 => bit_counter(7), O => N10 ); busy_in_cmp_eq0000_SW0 : X_LUT4 generic map( INIT => X"7F7F", LOC => "SLICE_X21Y78" ) port map ( ADR0 => bit_counter(6), ADR1 => bit_counter(0), ADR2 => N3, ADR3 => VCC, O => N4 ); Mtridata_MDIO_and000072_SW0 : X_LUT4 generic map( INIT => X"FFC0", LOC => "SLICE_X21Y78" ) port map ( ADR0 => VCC, ADR1 => bit_counter(0), ADR2 => bit_counter(4), ADR3 => Mtridata_MDIO_and000028, O => N20 ); latched_phy_addr_0 : X_FF generic map( LOC => "SLICE_X12Y15", INIT => '0' ) port map ( I => latched_phy_addr_1_DYMUX_2056, CE => latched_phy_addr_1_CEINV_2053, CLK => latched_phy_addr_1_CLKINV_2054, SET => GND, RST => GND, O => latched_phy_addr(0) ); latched_phy_addr_1 : X_FF generic map( LOC => "SLICE_X12Y15", INIT => '0' ) port map ( I => latched_phy_addr_1_DXMUX_2062, CE => latched_phy_addr_1_CEINV_2053, CLK => latched_phy_addr_1_CLKINV_2054, SET => GND, RST => GND, O => latched_phy_addr(1) ); latched_phy_addr_2 : X_FF generic map( LOC => "SLICE_X13Y16", INIT => '0' ) port map ( I => latched_phy_addr_3_DYMUX_2076, CE => latched_phy_addr_3_CEINV_2073, CLK => latched_phy_addr_3_CLKINV_2074, SET => GND, RST => GND, O => latched_phy_addr(2) ); latched_phy_addr_3 : X_FF generic map( LOC => "SLICE_X13Y16", INIT => '0' ) port map ( I => latched_phy_addr_3_DXMUX_2082, CE => latched_phy_addr_3_CEINV_2073, CLK => latched_phy_addr_3_CLKINV_2074, SET => GND, RST => GND, O => latched_phy_addr(3) ); latched_phy_addr_4 : X_FF generic map( LOC => "SLICE_X16Y14", INIT => '0' ) port map ( I => latched_phy_addr_4_DYMUX_2094, CE => latched_phy_addr_4_CEINV_2091, CLK => latched_phy_addr_4_CLKINV_2092, SET => GND, RST => GND, O => latched_phy_addr(4) ); Mtridata_MDC : X_FF generic map( LOC => "SLICE_X12Y91", INIT => '0' ) port map ( I => Mtridata_MDC_DYMUX_2104, CE => VCC, CLK => Mtridata_MDC_CLKINV_2102, SET => GND, RST => GND, O => Mtridata_MDC_1397 ); read_receive_data_10 : X_SFF generic map( LOC => "SLICE_X2Y73", INIT => '0' ) port map ( I => read_receive_data_11_DYMUX_2119, CE => read_receive_data_11_CEINV_2115, CLK => read_receive_data_11_CLKINV_2116, SET => GND, RST => GND, SSET => GND, SRST => read_receive_data_11_SRINV_2117, O => read_receive_data(10) ); read_receive_data_11 : X_SFF generic map( LOC => "SLICE_X2Y73", INIT => '0' ) port map ( I => read_receive_data_11_DXMUX_2126, CE => read_receive_data_11_CEINV_2115, CLK => read_receive_data_11_CLKINV_2116, SET => GND, RST => GND, SSET => GND, SRST => read_receive_data_11_SRINV_2117, O => read_receive_data(11) ); read_receive_data_12 : X_SFF generic map( LOC => "SLICE_X3Y73", INIT => '0' ) port map ( I => read_receive_data_13_DYMUX_2143, CE => read_receive_data_13_CEINV_2139, CLK => read_receive_data_13_CLKINV_2140, SET => GND, RST => GND, SSET => GND, SRST => read_receive_data_13_SRINV_2141, O => read_receive_data(12) ); read_receive_data_13 : X_SFF generic map( LOC => "SLICE_X3Y73", INIT => '0' ) port map ( I => read_receive_data_13_DXMUX_2150, CE => read_receive_data_13_CEINV_2139, CLK => read_receive_data_13_CLKINV_2140, SET => GND, RST => GND, SSET => GND, SRST => read_receive_data_13_SRINV_2141, O => read_receive_data(13) ); bit_counter_6_1 : X_FF generic map( LOC => "SLICE_X14Y80", INIT => '0' ) port map ( I => bit_counter_6_1_DYMUX_2163, CE => VCC, CLK => bit_counter_6_1_CLKINVNOT, SET => GND, RST => bit_counter_6_1_FFY_RSTAND_2168, O => bit_counter_6_1_1403 ); bit_counter_6_1_FFY_RSTAND : X_BUF generic map( LOC => "SLICE_X14Y80", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => bit_counter_6_1_FFY_RSTAND_2168 ); read_receive_data_14 : X_SFF generic map( LOC => "SLICE_X3Y72", INIT => '0' ) port map ( I => read_receive_data_15_DYMUX_2181, CE => read_receive_data_15_CEINV_2177, CLK => read_receive_data_15_CLKINV_2178, SET => GND, RST => GND, SSET => GND, SRST => read_receive_data_15_SRINV_2179, O => read_receive_data(14) ); read_receive_data_15 : X_SFF generic map( LOC => "SLICE_X3Y72", INIT => '0' ) port map ( I => read_receive_data_15_DXMUX_2188, CE => read_receive_data_15_CEINV_2177, CLK => read_receive_data_15_CLKINV_2178, SET => GND, RST => GND, SSET => GND, SRST => read_receive_data_15_SRINV_2179, O => read_receive_data(15) ); read_send_data_0_cmp_eq00001 : X_LUT4 generic map( INIT => X"0300", LOC => "SLICE_X13Y72" ) port map ( ADR0 => VCC, ADR1 => read_receive_data_0_cmp_gt00001_1316, ADR2 => bit_counter(6), ADR3 => N3, O => read_send_data_11_not0001_inv_pack_1 ); write_send_data_mux00611 : X_LUT4 generic map( INIT => X"AFA0", LOC => "SLICE_X13Y72" ) port map ( ADR0 => latched_data(1), ADR1 => VCC, ADR2 => read_send_data_11_not0001_inv, ADR3 => write_send_data(0), O => write_send_data_mux0061 ); write_send_data_1 : X_SFF generic map( LOC => "SLICE_X13Y72", INIT => '0' ) port map ( I => write_send_data_1_DXMUX_2224, CE => write_send_data_1_CEINV_2205, CLK => write_send_data_1_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_1_SRINV_2207, O => write_send_data(1) ); clk_div : X_SFF generic map( LOC => "SLICE_X45Y84", INIT => '0' ) port map ( I => clk_div1_DYMUX_2239, CE => clk_div1_CEINV_2235, CLK => clk_div1_CLKINV_2236, SET => GND, RST => GND, SSET => GND, SRST => clk_div1_SRINV_2237, O => clk_div1 ); busy_in_cmp_eq0000 : X_LUT4 generic map( INIT => X"0001", LOC => "SLICE_X25Y79" ) port map ( ADR0 => bit_counter(2), ADR1 => N4_0, ADR2 => bit_counter(1), ADR3 => bit_counter(3), O => busy_in_cmp_eq0000_pack_1 ); clk_div_or00001 : X_LUT4 generic map( INIT => X"FFCC", LOC => "SLICE_X25Y79" ) port map ( ADR0 => VCC, ADR1 => reset_IBUF_1314, ADR2 => VCC, ADR3 => busy_in_cmp_eq0000_1409, O => clk_div_or0000 ); read_send_data_10 : X_SFF generic map( LOC => "SLICE_X3Y67", INIT => '0' ) port map ( I => read_send_data_10_DYMUX_2278, CE => read_send_data_10_CEINV_2274, CLK => read_send_data_10_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => read_send_data_10_SRINV_2276, O => read_send_data(10) ); read_send_data_11 : X_SFF generic map( LOC => "SLICE_X2Y67", INIT => '0' ) port map ( I => read_send_data_11_DXMUX_2296, CE => read_send_data_11_CEINV_2290, CLK => read_send_data_11_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_11_REVUSED_2294, SRST => read_send_data_11_SRINV_2292, O => read_send_data(11) ); read_send_data_19_rt : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X24Y77" ) port map ( ADR0 => VCC, ADR1 => read_send_data(19), ADR2 => VCC, ADR3 => VCC, O => read_send_data_19_rt_2322 ); read_send_data_20 : X_SFF generic map( LOC => "SLICE_X24Y77", INIT => '0' ) port map ( I => read_send_data_21_DYMUX_2325, CE => read_send_data_21_CEINV_2311, CLK => read_send_data_21_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_21_REVUSED_2326, SRST => read_send_data_21_SRINV_2313, O => read_send_data(20) ); read_send_data_21 : X_SFF generic map( LOC => "SLICE_X24Y77", INIT => '0' ) port map ( I => read_send_data_21_DXMUX_2334, CE => read_send_data_21_CEINV_2311, CLK => read_send_data_21_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_21_REVUSED_2326, SRST => read_send_data_21_SRINV_2313, O => read_send_data(21) ); read_send_data_12 : X_SFF generic map( LOC => "SLICE_X3Y71", INIT => '0' ) port map ( I => read_send_data_12_DXMUX_2353, CE => read_send_data_12_CEINV_2347, CLK => read_send_data_12_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_12_REVUSED_2351, SRST => read_send_data_12_SRINV_2349, O => read_send_data(12) ); read_send_data_13 : X_SFF generic map( LOC => "SLICE_X5Y88", INIT => '0' ) port map ( I => read_send_data_13_DYMUX_2369, CE => read_send_data_13_CEINV_2365, CLK => read_send_data_13_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => read_send_data_13_SRINV_2367, O => read_send_data(13) ); read_send_data_29_rt : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X25Y69" ) port map ( ADR0 => read_send_data(29), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => read_send_data_29_rt_2394 ); read_send_data_30 : X_SFF generic map( LOC => "SLICE_X25Y69", INIT => '0' ) port map ( I => read_send_data_31_DYMUX_2397, CE => read_send_data_31_CEINV_2383, CLK => read_send_data_31_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_31_REVUSED_2398, SRST => read_send_data_31_SRINV_2385, O => read_send_data(30) ); read_send_data_31 : X_SFF generic map( LOC => "SLICE_X25Y69", INIT => '0' ) port map ( I => read_send_data_31_DXMUX_2406, CE => read_send_data_31_CEINV_2383, CLK => read_send_data_31_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_31_REVUSED_2398, SRST => read_send_data_31_SRINV_2385, O => read_send_data(31) ); read_send_data_21_rt : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X26Y75" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => read_send_data(21), ADR3 => VCC, O => read_send_data_21_rt_2432 ); read_send_data_22 : X_SFF generic map( LOC => "SLICE_X26Y75", INIT => '0' ) port map ( I => read_send_data_23_DYMUX_2435, CE => read_send_data_23_CEINV_2421, CLK => read_send_data_23_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_23_REVUSED_2436, SRST => read_send_data_23_SRINV_2423, O => read_send_data(22) ); read_send_data_23 : X_SFF generic map( LOC => "SLICE_X26Y75", INIT => '0' ) port map ( I => read_send_data_23_DXMUX_2444, CE => read_send_data_23_CEINV_2421, CLK => read_send_data_23_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_23_REVUSED_2436, SRST => read_send_data_23_SRINV_2423, O => read_send_data(23) ); read_send_data_13_rt : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X14Y86" ) port map ( ADR0 => VCC, ADR1 => read_send_data(13), ADR2 => VCC, ADR3 => VCC, O => read_send_data_13_rt_2470 ); read_send_data_14 : X_SFF generic map( LOC => "SLICE_X14Y86", INIT => '0' ) port map ( I => read_send_data_15_DYMUX_2473, CE => read_send_data_15_CEINV_2459, CLK => read_send_data_15_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_15_REVUSED_2474, SRST => read_send_data_15_SRINV_2461, O => read_send_data(14) ); read_send_data_15 : X_SFF generic map( LOC => "SLICE_X14Y86", INIT => '0' ) port map ( I => read_send_data_15_DXMUX_2482, CE => read_send_data_15_CEINV_2459, CLK => read_send_data_15_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_15_REVUSED_2474, SRST => read_send_data_15_SRINV_2461, O => read_send_data(15) ); latched_write_read : X_FF generic map( LOC => "SLICE_X2Y51", INIT => '1' ) port map ( I => latched_write_read_DYMUX_2496, CE => latched_write_read_CEINV_2493, CLK => latched_write_read_CLKINV_2494, SET => GND, RST => GND, O => latched_write_read_1343 ); read_send_data_39_rt : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X17Y56" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => read_send_data(39), ADR3 => VCC, O => read_send_data_39_rt_2520 ); read_send_data_40 : X_SFF generic map( LOC => "SLICE_X17Y56", INIT => '0' ) port map ( I => read_send_data_41_DYMUX_2523, CE => read_send_data_41_CEINV_2509, CLK => read_send_data_41_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_41_REVUSED_2524, SRST => read_send_data_41_SRINV_2511, O => read_send_data(40) ); read_send_data_41 : X_SFF generic map( LOC => "SLICE_X17Y56", INIT => '0' ) port map ( I => read_send_data_41_DXMUX_2532, CE => read_send_data_41_CEINV_2509, CLK => read_send_data_41_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_41_REVUSED_2524, SRST => read_send_data_41_SRINV_2511, O => read_send_data(41) ); read_send_data_31_rt : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X24Y67" ) port map ( ADR0 => VCC, ADR1 => read_send_data(31), ADR2 => VCC, ADR3 => VCC, O => read_send_data_31_rt_2558 ); read_send_data_32 : X_SFF generic map( LOC => "SLICE_X24Y67", INIT => '0' ) port map ( I => read_send_data_33_DYMUX_2561, CE => read_send_data_33_CEINV_2547, CLK => read_send_data_33_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_33_REVUSED_2562, SRST => read_send_data_33_SRINV_2549, O => read_send_data(32) ); read_send_data_33 : X_SFF generic map( LOC => "SLICE_X24Y67", INIT => '0' ) port map ( I => read_send_data_33_DXMUX_2570, CE => read_send_data_33_CEINV_2547, CLK => read_send_data_33_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_33_REVUSED_2562, SRST => read_send_data_33_SRINV_2549, O => read_send_data(33) ); read_send_data_23_rt : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X26Y73" ) port map ( ADR0 => VCC, ADR1 => read_send_data(23), ADR2 => VCC, ADR3 => VCC, O => read_send_data_23_rt_2596 ); read_send_data_24 : X_SFF generic map( LOC => "SLICE_X26Y73", INIT => '0' ) port map ( I => read_send_data_25_DYMUX_2599, CE => read_send_data_25_CEINV_2585, CLK => read_send_data_25_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_25_REVUSED_2600, SRST => read_send_data_25_SRINV_2587, O => read_send_data(24) ); read_send_data_25 : X_SFF generic map( LOC => "SLICE_X26Y73", INIT => '0' ) port map ( I => read_send_data_25_DXMUX_2608, CE => read_send_data_25_CEINV_2585, CLK => read_send_data_25_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_25_REVUSED_2600, SRST => read_send_data_25_SRINV_2587, O => read_send_data(25) ); read_send_data_15_rt : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X16Y87" ) port map ( ADR0 => VCC, ADR1 => read_send_data(15), ADR2 => VCC, ADR3 => VCC, O => read_send_data_15_rt_2634 ); read_send_data_16 : X_SFF generic map( LOC => "SLICE_X16Y87", INIT => '0' ) port map ( I => read_send_data_17_DYMUX_2637, CE => read_send_data_17_CEINV_2623, CLK => read_send_data_17_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_17_REVUSED_2638, SRST => read_send_data_17_SRINV_2625, O => read_send_data(16) ); read_send_data_17 : X_SFF generic map( LOC => "SLICE_X16Y87", INIT => '0' ) port map ( I => read_send_data_17_DXMUX_2646, CE => read_send_data_17_CEINV_2623, CLK => read_send_data_17_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_17_REVUSED_2638, SRST => read_send_data_17_SRINV_2625, O => read_send_data(17) ); read_send_data_41_rt : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X16Y53" ) port map ( ADR0 => VCC, ADR1 => read_send_data(41), ADR2 => VCC, ADR3 => VCC, O => read_send_data_41_rt_2672 ); read_send_data_42 : X_SFF generic map( LOC => "SLICE_X16Y53", INIT => '0' ) port map ( I => read_send_data_43_DYMUX_2675, CE => read_send_data_43_CEINV_2661, CLK => read_send_data_43_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_43_REVUSED_2676, SRST => read_send_data_43_SRINV_2663, O => read_send_data(42) ); read_send_data_43 : X_SFF generic map( LOC => "SLICE_X16Y53", INIT => '0' ) port map ( I => read_send_data_43_DXMUX_2684, CE => read_send_data_43_CEINV_2661, CLK => read_send_data_43_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_43_REVUSED_2676, SRST => read_send_data_43_SRINV_2663, O => read_send_data(43) ); read_send_data_33_rt : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X20Y65" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => read_send_data(33), ADR3 => VCC, O => read_send_data_33_rt_2710 ); read_send_data_34 : X_SFF generic map( LOC => "SLICE_X20Y65", INIT => '0' ) port map ( I => read_send_data_35_DYMUX_2713, CE => read_send_data_35_CEINV_2699, CLK => read_send_data_35_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_35_REVUSED_2714, SRST => read_send_data_35_SRINV_2701, O => read_send_data(34) ); read_send_data_35 : X_SFF generic map( LOC => "SLICE_X20Y65", INIT => '0' ) port map ( I => read_send_data_35_DXMUX_2722, CE => read_send_data_35_CEINV_2699, CLK => read_send_data_35_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_35_REVUSED_2714, SRST => read_send_data_35_SRINV_2701, O => read_send_data(35) ); read_send_data_25_rt : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X24Y70" ) port map ( ADR0 => read_send_data(25), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => read_send_data_25_rt_2748 ); read_send_data_26 : X_SFF generic map( LOC => "SLICE_X24Y70", INIT => '0' ) port map ( I => read_send_data_27_DYMUX_2751, CE => read_send_data_27_CEINV_2737, CLK => read_send_data_27_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_27_REVUSED_2752, SRST => read_send_data_27_SRINV_2739, O => read_send_data(26) ); read_send_data_27 : X_SFF generic map( LOC => "SLICE_X24Y70", INIT => '0' ) port map ( I => read_send_data_27_DXMUX_2760, CE => read_send_data_27_CEINV_2737, CLK => read_send_data_27_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_27_REVUSED_2752, SRST => read_send_data_27_SRINV_2739, O => read_send_data(27) ); read_send_data_17_rt : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X19Y81" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => read_send_data(17), O => read_send_data_17_rt_2786 ); read_send_data_18 : X_SFF generic map( LOC => "SLICE_X19Y81", INIT => '0' ) port map ( I => read_send_data_19_DYMUX_2789, CE => read_send_data_19_CEINV_2775, CLK => read_send_data_19_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_19_REVUSED_2790, SRST => read_send_data_19_SRINV_2777, O => read_send_data(18) ); read_send_data_19 : X_SFF generic map( LOC => "SLICE_X19Y81", INIT => '0' ) port map ( I => read_send_data_19_DXMUX_2798, CE => read_send_data_19_CEINV_2775, CLK => read_send_data_19_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_19_REVUSED_2790, SRST => read_send_data_19_SRINV_2777, O => read_send_data(19) ); read_send_data_43_rt : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X16Y52" ) port map ( ADR0 => VCC, ADR1 => read_send_data(43), ADR2 => VCC, ADR3 => VCC, O => read_send_data_43_rt_2824 ); read_send_data_44 : X_SFF generic map( LOC => "SLICE_X16Y52", INIT => '0' ) port map ( I => read_send_data_45_DYMUX_2827, CE => read_send_data_45_CEINV_2813, CLK => read_send_data_45_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_45_REVUSED_2828, SRST => read_send_data_45_SRINV_2815, O => read_send_data(44) ); read_send_data_45 : X_SFF generic map( LOC => "SLICE_X16Y52", INIT => '0' ) port map ( I => read_send_data_45_DXMUX_2836, CE => read_send_data_45_CEINV_2813, CLK => read_send_data_45_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_45_REVUSED_2828, SRST => read_send_data_45_SRINV_2815, O => read_send_data(45) ); read_send_data_35_rt : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X18Y62" ) port map ( ADR0 => read_send_data(35), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => read_send_data_35_rt_2862 ); read_send_data_36 : X_SFF generic map( LOC => "SLICE_X18Y62", INIT => '0' ) port map ( I => read_send_data_37_DYMUX_2865, CE => read_send_data_37_CEINV_2851, CLK => read_send_data_37_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_37_REVUSED_2866, SRST => read_send_data_37_SRINV_2853, O => read_send_data(36) ); read_send_data_37 : X_SFF generic map( LOC => "SLICE_X18Y62", INIT => '0' ) port map ( I => read_send_data_37_DXMUX_2874, CE => read_send_data_37_CEINV_2851, CLK => read_send_data_37_CLKINVNOT, SET => GND, RST => GND, SSET => read_send_data_37_REVUSED_2866, SRST => read_send_data_37_SRINV_2853, O => read_send_data(37) ); read_receive_data_0_and0000_SW3 : X_LUT4 generic map( INIT => X"EFFF", LOC => "SLICE_X12Y80" ) port map ( ADR0 => bit_counter_6_1_1403, ADR1 => latched_write_read_1343, ADR2 => bit_counter(5), ADR3 => bit_counter(4), O => N18 ); read_receive_data_2 : X_SFF generic map( LOC => "SLICE_X0Y85", INIT => '0' ) port map ( I => read_receive_data_3_DYMUX_3035, CE => read_receive_data_3_CEINV_3031, CLK => read_receive_data_3_CLKINV_3032, SET => GND, RST => GND, SSET => GND, SRST => read_receive_data_3_SRINV_3033, O => read_receive_data(2) ); read_receive_data_3 : X_SFF generic map( LOC => "SLICE_X0Y85", INIT => '0' ) port map ( I => read_receive_data_3_DXMUX_3042, CE => read_receive_data_3_CEINV_3031, CLK => read_receive_data_3_CLKINV_3032, SET => GND, RST => GND, SSET => GND, SRST => read_receive_data_3_SRINV_3033, O => read_receive_data(3) ); counter_cmp_eq000023 : X_LUT4 generic map( INIT => X"0001", LOC => "SLICE_X48Y85" ) port map ( ADR0 => counter(4), ADR1 => counter(5), ADR2 => counter(6), ADR3 => counter(7), O => counter_cmp_eq000023_pack_1 ); clk_div_not00021 : X_LUT4 generic map( INIT => X"A000", LOC => "SLICE_X48Y85" ) port map ( ADR0 => busy_in_1448, ADR1 => VCC, ADR2 => counter_cmp_eq000023_1460, ADR3 => counter_cmp_eq000010_0, O => clk_div_not0002 ); read_receive_data_4 : X_SFF generic map( LOC => "SLICE_X3Y83", INIT => '0' ) port map ( I => read_receive_data_5_DYMUX_3083, CE => read_receive_data_5_CEINV_3079, CLK => read_receive_data_5_CLKINV_3080, SET => GND, RST => GND, SSET => GND, SRST => read_receive_data_5_SRINV_3081, O => read_receive_data(4) ); read_receive_data_5 : X_SFF generic map( LOC => "SLICE_X3Y83", INIT => '0' ) port map ( I => read_receive_data_5_DXMUX_3090, CE => read_receive_data_5_CEINV_3079, CLK => read_receive_data_5_CLKINV_3080, SET => GND, RST => GND, SSET => GND, SRST => read_receive_data_5_SRINV_3081, O => read_receive_data(5) ); bit_counter_1 : X_FF generic map( LOC => "SLICE_X15Y78", INIT => '0' ) port map ( I => bit_counter_0_DYMUX_3121, CE => VCC, CLK => bit_counter_0_CLKINVNOT, SET => GND, RST => bit_counter_0_SRINV_3105, O => bit_counter(1) ); Mcount_bit_counter_lut_0_INV_0 : X_LUT4 generic map( INIT => X"0F0F", LOC => "SLICE_X15Y78" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => bit_counter(0), ADR3 => VCC, O => Mcount_bit_counter_lut(0) ); bit_counter_0 : X_FF generic map( LOC => "SLICE_X15Y78", INIT => '0' ) port map ( I => bit_counter_0_DXMUX_3143, CE => VCC, CLK => bit_counter_0_CLKINVNOT, SET => GND, RST => bit_counter_0_SRINV_3105, O => bit_counter(0) ); bit_counter_3 : X_FF generic map( LOC => "SLICE_X15Y79", INIT => '0' ) port map ( I => bit_counter_2_DYMUX_3180, CE => VCC, CLK => bit_counter_2_CLKINVNOT, SET => GND, RST => bit_counter_2_SRINV_3159, O => bit_counter(3) ); bit_counter_2 : X_FF generic map( LOC => "SLICE_X15Y79", INIT => '0' ) port map ( I => bit_counter_2_DXMUX_3199, CE => VCC, CLK => bit_counter_2_CLKINVNOT, SET => GND, RST => bit_counter_2_SRINV_3159, O => bit_counter(2) ); bit_counter_5 : X_FF generic map( LOC => "SLICE_X15Y80", INIT => '0' ) port map ( I => bit_counter_4_DYMUX_3236, CE => VCC, CLK => bit_counter_4_CLKINVNOT, SET => GND, RST => bit_counter_4_SRINV_3215, O => bit_counter(5) ); bit_counter_4 : X_FF generic map( LOC => "SLICE_X15Y80", INIT => '0' ) port map ( I => bit_counter_4_DXMUX_3255, CE => VCC, CLK => bit_counter_4_CLKINVNOT, SET => GND, RST => bit_counter_4_SRINV_3215, O => bit_counter(4) ); bit_counter_7_rt : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X15Y81" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => bit_counter(7), O => bit_counter_7_rt_3279 ); bit_counter_7 : X_FF generic map( LOC => "SLICE_X15Y81", INIT => '0' ) port map ( I => bit_counter_6_DYMUX_3284, CE => VCC, CLK => bit_counter_6_CLKINVNOT, SET => GND, RST => bit_counter_6_SRINV_3271, O => bit_counter(7) ); bit_counter_6 : X_FF generic map( LOC => "SLICE_X15Y81", INIT => '0' ) port map ( I => bit_counter_6_DXMUX_3305, CE => VCC, CLK => bit_counter_6_CLKINVNOT, SET => GND, RST => bit_counter_6_SRINV_3271, O => bit_counter(6) ); counter_1 : X_SFF generic map( LOC => "SLICE_X49Y82", INIT => '0' ) port map ( I => counter_0_DYMUX_3339, CE => counter_0_CEINV_3321, CLK => counter_0_CLKINV_3322, SET => GND, RST => GND, SSET => GND, SRST => counter_0_SRINV_3323, O => counter(1) ); Mcount_counter_lut_0_INV_0 : X_LUT4 generic map( INIT => X"00FF", LOC => "SLICE_X49Y82" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => counter(0), O => Mcount_counter_lut(0) ); counter_0 : X_SFF generic map( LOC => "SLICE_X49Y82", INIT => '0' ) port map ( I => counter_0_DXMUX_3360, CE => counter_0_CEINV_3321, CLK => counter_0_CLKINV_3322, SET => GND, RST => GND, SSET => GND, SRST => counter_0_SRINV_3323, O => counter(0) ); counter_3 : X_SFF generic map( LOC => "SLICE_X49Y83", INIT => '0' ) port map ( I => counter_2_DYMUX_3398, CE => counter_2_CEINV_3375, CLK => counter_2_CLKINV_3376, SET => GND, RST => GND, SSET => GND, SRST => counter_2_SRINV_3377, O => counter(3) ); counter_2 : X_SFF generic map( LOC => "SLICE_X49Y83", INIT => '0' ) port map ( I => counter_2_DXMUX_3416, CE => counter_2_CEINV_3375, CLK => counter_2_CLKINV_3376, SET => GND, RST => GND, SSET => GND, SRST => counter_2_SRINV_3377, O => counter(2) ); counter_5 : X_SFF generic map( LOC => "SLICE_X49Y84", INIT => '0' ) port map ( I => counter_4_DYMUX_3454, CE => counter_4_CEINV_3431, CLK => counter_4_CLKINV_3432, SET => GND, RST => GND, SSET => GND, SRST => counter_4_SRINV_3433, O => counter(5) ); counter_4 : X_SFF generic map( LOC => "SLICE_X49Y84", INIT => '0' ) port map ( I => counter_4_DXMUX_3472, CE => counter_4_CEINV_3431, CLK => counter_4_CLKINV_3432, SET => GND, RST => GND, SSET => GND, SRST => counter_4_SRINV_3433, O => counter(4) ); counter_7_rt : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X49Y85" ) port map ( ADR0 => counter(7), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => counter_7_rt_3496 ); counter_7 : X_SFF generic map( LOC => "SLICE_X49Y85", INIT => '0' ) port map ( I => counter_6_DYMUX_3501, CE => counter_6_CEINV_3486, CLK => counter_6_CLKINV_3487, SET => GND, RST => GND, SSET => GND, SRST => counter_6_SRINV_3488, O => counter(7) ); counter_6 : X_SFF generic map( LOC => "SLICE_X49Y85", INIT => '0' ) port map ( I => counter_6_DXMUX_3521, CE => counter_6_CEINV_3486, CLK => counter_6_CLKINV_3487, SET => GND, RST => GND, SSET => GND, SRST => counter_6_SRINV_3488, O => counter(6) ); MDC_OUTPUT_TFF_T1INV : X_BUF generic map( LOC => "PAD12", PATHPULSE => 638 ps ) port map ( I => '1', O => MDC_OUTPUT_TFF_T1INV_3567 ); MDC_OUTPUT_TFF_TSR_USED : X_BUF generic map( LOC => "PAD12", PATHPULSE => 638 ps ) port map ( I => write_send_data_and0000_0, O => MDC_OUTPUT_TFF_TSR_USED_3570 ); MDC_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD12", PATHPULSE => 638 ps ) port map ( I => Mtrien_MDC_3572, O => MDC_T ); Mtrien_MDC : X_SFF generic map( LOC => "PAD12", INIT => '0' ) port map ( I => MDC_OUTPUT_TFF_T1INV_3567, CE => VCC, CLK => MDC_OUTPUT_OTCLK1INV_3563, SET => GND, RST => GND, SSET => GND, SRST => MDC_OUTPUT_TFF_TSR_USED_3570, O => Mtrien_MDC_3572 ); MDC_OUTPUT_OTCLK1INV : X_BUF generic map( LOC => "PAD12", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => MDC_OUTPUT_OTCLK1INV_3563 ); strt_IFF_IMUX : X_BUF generic map( LOC => "PAD195", PATHPULSE => 638 ps ) port map ( I => strt_INBUF, O => strt_IBUF_1362 ); reg_addr_0_IFF_IMUX : X_BUF generic map( LOC => "IPAD189", PATHPULSE => 638 ps ) port map ( I => reg_addr_0_INBUF, O => reg_addr_0_IBUF_1361 ); reg_addr_1_IFF_IMUX : X_BUF generic map( LOC => "PAD188", PATHPULSE => 638 ps ) port map ( I => reg_addr_1_INBUF, O => reg_addr_1_IBUF_1360 ); reg_addr_2_IFF_IMUX : X_BUF generic map( LOC => "PAD187", PATHPULSE => 638 ps ) port map ( I => reg_addr_2_INBUF, O => reg_addr_2_IBUF_1366 ); reg_addr_3_IFF_IMUX : X_BUF generic map( LOC => "PAD186", PATHPULSE => 638 ps ) port map ( I => reg_addr_3_INBUF, O => reg_addr_3_IBUF_1365 ); reg_addr_4_IFF_IMUX : X_BUF generic map( LOC => "PAD185", PATHPULSE => 638 ps ) port map ( I => reg_addr_4_INBUF, O => reg_addr_4_IBUF_1369 ); latched_data_0 : X_FF generic map( LOC => "IPAD228", INIT => '0' ) port map ( I => data_in_0_IFF_IDDRIN_MUX_3717, CE => data_in_0_IFF_ICEINV_3719, CLK => data_in_0_IFF_ICLK1INV_3721, SET => GND, RST => GND, O => latched_data(0) ); data_in_0_IFF_IDDRIN_MUX : X_BUF generic map( LOC => "IPAD228", PATHPULSE => 638 ps ) port map ( I => data_in_0_INBUF, O => data_in_0_IFF_IDDRIN_MUX_3717 ); data_in_0_IFF_ICLK1INV : X_BUF generic map( LOC => "IPAD228", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => data_in_0_IFF_ICLK1INV_3721 ); data_in_0_IFF_ICEINV : X_BUF generic map( LOC => "IPAD228", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => data_in_0_IFF_ICEINV_3719 ); reset_IFF_IMUX : X_BUF generic map( LOC => "PAD196", PATHPULSE => 638 ps ) port map ( I => reset_INBUF, O => reset_IBUF_1314 ); phy_addr_0_IFF_IMUX : X_BUF generic map( LOC => "IPAD194", PATHPULSE => 638 ps ) port map ( I => phy_addr_0_INBUF, O => phy_addr_0_IBUF_1387 ); latched_data_15 : X_FF generic map( LOC => "PAD198", INIT => '0' ) port map ( I => data_in_15_IFF_IDDRIN_MUX_4015, CE => data_in_15_IFF_ICEINV_4017, CLK => data_in_15_IFF_ICLK1INV_4019, SET => GND, RST => GND, O => latched_data(15) ); data_in_15_IFF_IDDRIN_MUX : X_BUF generic map( LOC => "PAD198", PATHPULSE => 638 ps ) port map ( I => data_in_15_INBUF, O => data_in_15_IFF_IDDRIN_MUX_4015 ); data_in_15_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD198", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => data_in_15_IFF_ICLK1INV_4019 ); data_in_15_IFF_ICEINV : X_BUF generic map( LOC => "PAD198", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => data_in_15_IFF_ICEINV_4017 ); latched_data_7 : X_FF generic map( LOC => "PAD206", INIT => '0' ) port map ( I => data_in_7_IFF_IDDRIN_MUX_4035, CE => data_in_7_IFF_ICEINV_4037, CLK => data_in_7_IFF_ICLK1INV_4039, SET => GND, RST => GND, O => latched_data(7) ); data_in_7_IFF_IDDRIN_MUX : X_BUF generic map( LOC => "PAD206", PATHPULSE => 638 ps ) port map ( I => data_in_7_INBUF, O => data_in_7_IFF_IDDRIN_MUX_4035 ); data_in_7_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD206", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => data_in_7_IFF_ICLK1INV_4039 ); data_in_7_IFF_ICEINV : X_BUF generic map( LOC => "PAD206", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => data_in_7_IFF_ICEINV_4037 ); phy_addr_1_IFF_IMUX : X_BUF generic map( LOC => "PAD193", PATHPULSE => 638 ps ) port map ( I => phy_addr_1_INBUF, O => phy_addr_1_IBUF_1386 ); latched_data_8 : X_FF generic map( LOC => "PAD205", INIT => '0' ) port map ( I => data_in_8_IFF_IDDRIN_MUX_4061, CE => data_in_8_IFF_ICEINV_4063, CLK => data_in_8_IFF_ICLK1INV_4065, SET => GND, RST => GND, O => latched_data(8) ); data_in_8_IFF_IDDRIN_MUX : X_BUF generic map( LOC => "PAD205", PATHPULSE => 638 ps ) port map ( I => data_in_8_INBUF, O => data_in_8_IFF_IDDRIN_MUX_4061 ); data_in_8_IFF_ICLK1INV : X_BUF generic map( LOC => "PAD205", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => data_in_8_IFF_ICLK1INV_4065 ); data_in_8_IFF_ICEINV : X_BUF generic map( LOC => "PAD205", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => data_in_8_IFF_ICEINV_4063 ); phy_addr_2_IFF_IMUX : X_BUF generic map( LOC => "PAD192", PATHPULSE => 638 ps ) port map ( I => phy_addr_2_INBUF, O => phy_addr_2_IBUF_1391 ); latched_data_9 : X_FF generic map( LOC => "IPAD204", INIT => '0' ) port map ( I => data_in_9_IFF_IDDRIN_MUX_4087, CE => data_in_9_IFF_ICEINV_4089, CLK => data_in_9_IFF_ICLK1INV_4091, SET => GND, RST => GND, O => latched_data(9) ); data_in_9_IFF_IDDRIN_MUX : X_BUF generic map( LOC => "IPAD204", PATHPULSE => 638 ps ) port map ( I => data_in_9_INBUF, O => data_in_9_IFF_IDDRIN_MUX_4087 ); data_in_9_IFF_ICLK1INV : X_BUF generic map( LOC => "IPAD204", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => data_in_9_IFF_ICLK1INV_4091 ); data_in_9_IFF_ICEINV : X_BUF generic map( LOC => "IPAD204", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => data_in_9_IFF_ICEINV_4089 ); phy_addr_3_IFF_IMUX : X_BUF generic map( LOC => "PAD191", PATHPULSE => 638 ps ) port map ( I => phy_addr_3_INBUF, O => phy_addr_3_IBUF_1390 ); phy_addr_4_IFF_IMUX : X_BUF generic map( LOC => "PAD190", PATHPULSE => 638 ps ) port map ( I => phy_addr_4_INBUF, O => phy_addr_4_IBUF_1394 ); busy_OUTPUT_OFF_O1INV : X_BUF generic map( LOC => "PAD41", PATHPULSE => 638 ps ) port map ( I => '0', O => busy_OUTPUT_OFF_O1INV_4143 ); busy_OUTPUT_OFF_O1_DDRMUX : X_BUF generic map( LOC => "PAD41", PATHPULSE => 638 ps ) port map ( I => busy_OUTPUT_OFF_O1INV_4143, O => busy_OUTPUT_OFF_ODDRIN1_MUX ); busy_OUTPUT_OFF_PCICE_MUX : X_BUF generic map( LOC => "PAD41", PATHPULSE => 638 ps ) port map ( I => busy_in_cmp_eq0000_1409, O => busy_OUTPUT_OFF_PCICE_MUX_4134 ); busy_OUTPUT_OFF_OSR_USED : X_BUF generic map( LOC => "PAD41", PATHPULSE => 638 ps ) port map ( I => reset_IBUF_1314, O => busy_OUTPUT_OFF_OSR_USED_4137 ); busy_OUTPUT_OFF_OREV_USED : X_BUF generic map( LOC => "PAD41", PATHPULSE => 638 ps ) port map ( I => strt_IBUF_1362, O => busy_OUTPUT_OFF_OREV_USED_4139 ); busy_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD41", PATHPULSE => 638 ps ) port map ( I => busy_in_1_4141, O => busy_O ); busy_in_1 : X_SFF generic map( LOC => "PAD41", INIT => '0' ) port map ( I => busy_OUTPUT_OFF_ODDRIN1_MUX, CE => busy_OUTPUT_OFF_PCICE_MUX_4134, CLK => busy_OUTPUT_OTCLK1INV_4127, SET => GND, RST => GND, SSET => busy_OUTPUT_OFF_OREV_USED_4139, SRST => busy_OUTPUT_OFF_OSR_USED_4137, O => busy_in_1_4141 ); busy_OUTPUT_OTCLK1INV : X_BUF generic map( LOC => "PAD41", PATHPULSE => 638 ps ) port map ( I => clk_BUFGP, O => busy_OUTPUT_OTCLK1INV_4127 ); counter_or000011 : X_LUT4 generic map( INIT => X"FF80", LOC => "SLICE_X48Y83" ) port map ( ADR0 => counter_cmp_eq000010_0, ADR1 => busy_in_1448, ADR2 => counter_cmp_eq000023_1460, ADR3 => busy_in_cmp_eq0000_1409, O => counter_or00001 ); Mtridata_MDIO_and0000135_F : X_LUT4 generic map( INIT => X"0036", LOC => "SLICE_X15Y65" ) port map ( ADR0 => read_receive_data_0_cmp_gt00001_1316, ADR1 => bit_counter(6), ADR2 => bit_counter(4), ADR3 => bit_counter(7), O => N22 ); Mtridata_MDIO_and0000135_G : X_LUT4 generic map( INIT => X"1010", LOC => "SLICE_X15Y65" ) port map ( ADR0 => bit_counter(7), ADR1 => bit_counter(6), ADR2 => N20_0, ADR3 => VCC, O => N23 ); Mtridata_MDIO_and0000282 : X_LUT4 generic map( INIT => X"7FFF", LOC => "SLICE_X20Y78" ) port map ( ADR0 => bit_counter(0), ADR1 => bit_counter(1), ADR2 => bit_counter(2), ADR3 => bit_counter(3), O => Mtridata_MDIO_and0000282_4219 ); Mtridata_MDIO_and0000281 : X_LUT4 generic map( INIT => X"7F74", LOC => "SLICE_X20Y78" ) port map ( ADR0 => bit_counter(0), ADR1 => bit_counter(1), ADR2 => bit_counter(2), ADR3 => bit_counter(3), O => Mtridata_MDIO_and0000281_4226 ); read_send_data_0_cmp_lt0000139 : X_LUT4 generic map( INIT => X"22A2", LOC => "SLICE_X2Y64" ) port map ( ADR0 => read_send_data_0_cmp_lt0000134_0, ADR1 => bit_counter(5), ADR2 => read_send_data_0_cmp_lt0000112_0, ADR3 => bit_counter(4), O => read_send_data_0_cmp_lt0000_pack_1 ); read_send_data_10_and0000 : X_LUT4 generic map( INIT => X"FE00", LOC => "SLICE_X2Y64" ) port map ( ADR0 => read_receive_data_0_cmp_gt00001_1316, ADR1 => N10_0, ADR2 => bit_counter(6), ADR3 => read_send_data_0_cmp_lt0000, O => read_send_data_10_and0000_4251 ); read_receive_data_0_and0000_SW2 : X_LUT4 generic map( INIT => X"FFFB", LOC => "SLICE_X3Y82" ) port map ( ADR0 => bit_counter(4), ADR1 => bit_counter_6_1_1403, ADR2 => latched_write_read_1343, ADR3 => bit_counter(5), O => read_receive_data_0_and0000_SW2_O_pack_1 ); read_receive_data_0_and0000 : X_LUT4 generic map( INIT => X"0131", LOC => "SLICE_X3Y82" ) port map ( ADR0 => read_receive_data_0_and0000_SW2_O, ADR1 => bit_counter(7), ADR2 => read_receive_data_0_cmp_gt000011_0, ADR3 => N18_0, O => read_receive_data_0_and0000_4275 ); read_receive_data_0_cmp_gt00001 : X_LUT4 generic map( INIT => X"FFFE", LOC => "SLICE_X14Y79" ) port map ( ADR0 => bit_counter(2), ADR1 => bit_counter(0), ADR2 => bit_counter(1), ADR3 => bit_counter(3), O => read_receive_data_0_cmp_gt00001_pack_1 ); write_send_data_and0000 : X_LUT4 generic map( INIT => X"0451", LOC => "SLICE_X14Y79" ) port map ( ADR0 => bit_counter(7), ADR1 => N8_0, ADR2 => read_receive_data_0_cmp_gt00001_1316, ADR3 => bit_counter(6), O => write_send_data_and0000_4299 ); busy_in_cmp_eq000011 : X_LUT4 generic map( INIT => X"0005", LOC => "SLICE_X12Y78" ) port map ( ADR0 => bit_counter(7), ADR1 => VCC, ADR2 => bit_counter(5), ADR3 => bit_counter(4), O => N3_pack_1 ); write_send_data_not00011 : X_LUT4 generic map( INIT => X"FF10", LOC => "SLICE_X12Y78" ) port map ( ADR0 => read_receive_data_0_cmp_gt00001_1316, ADR1 => bit_counter(6), ADR2 => N3, ADR3 => write_send_data_and0000_0, O => write_send_data_not0001 ); write_send_data_mux00521 : X_LUT4 generic map( INIT => X"CFC0", LOC => "SLICE_X0Y45" ) port map ( ADR0 => VCC, ADR1 => latched_data(10), ADR2 => read_send_data_11_not0001_inv, ADR3 => write_send_data(9), O => write_send_data_mux0052 ); write_send_data_10 : X_SFF generic map( LOC => "SLICE_X0Y45", INIT => '0' ) port map ( I => write_send_data_11_DYMUX_4348, CE => write_send_data_11_CEINV_4337, CLK => write_send_data_11_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_11_SRINV_4339, O => write_send_data(10) ); write_send_data_mux00511 : X_LUT4 generic map( INIT => X"FC0C", LOC => "SLICE_X0Y45" ) port map ( ADR0 => VCC, ADR1 => write_send_data(10), ADR2 => read_send_data_11_not0001_inv, ADR3 => latched_data(11), O => write_send_data_mux0051 ); write_send_data_11 : X_SFF generic map( LOC => "SLICE_X0Y45", INIT => '0' ) port map ( I => write_send_data_11_DXMUX_4362, CE => write_send_data_11_CEINV_4337, CLK => write_send_data_11_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_11_SRINV_4339, O => write_send_data(11) ); write_send_data_mux00441 : X_LUT4 generic map( INIT => X"FC0C", LOC => "SLICE_X7Y3" ) port map ( ADR0 => VCC, ADR1 => write_send_data(19), ADR2 => read_send_data_11_not0001_inv, ADR3 => latched_reg_addr(2), O => write_send_data_mux0044 ); write_send_data_20 : X_SFF generic map( LOC => "SLICE_X7Y3", INIT => '0' ) port map ( I => write_send_data_21_DYMUX_4390, CE => write_send_data_21_CEINV_4379, CLK => write_send_data_21_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_21_SRINV_4381, O => write_send_data(20) ); write_send_data_mux00431 : X_LUT4 generic map( INIT => X"CFC0", LOC => "SLICE_X7Y3" ) port map ( ADR0 => VCC, ADR1 => latched_reg_addr(3), ADR2 => read_send_data_11_not0001_inv, ADR3 => write_send_data(20), O => write_send_data_mux0043 ); write_send_data_21 : X_SFF generic map( LOC => "SLICE_X7Y3", INIT => '0' ) port map ( I => write_send_data_21_DXMUX_4404, CE => write_send_data_21_CEINV_4379, CLK => write_send_data_21_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_21_SRINV_4381, O => write_send_data(21) ); write_send_data_mux00501 : X_LUT4 generic map( INIT => X"CCF0", LOC => "SLICE_X0Y40" ) port map ( ADR0 => VCC, ADR1 => latched_data(12), ADR2 => write_send_data(11), ADR3 => read_send_data_11_not0001_inv, O => write_send_data_mux0050 ); write_send_data_12 : X_SFF generic map( LOC => "SLICE_X0Y40", INIT => '0' ) port map ( I => write_send_data_13_DYMUX_4432, CE => write_send_data_13_CEINV_4421, CLK => write_send_data_13_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_13_SRINV_4423, O => write_send_data(12) ); write_send_data_mux00491 : X_LUT4 generic map( INIT => X"EE44", LOC => "SLICE_X0Y40" ) port map ( ADR0 => read_send_data_11_not0001_inv, ADR1 => write_send_data(12), ADR2 => VCC, ADR3 => latched_data(13), O => write_send_data_mux0049 ); write_send_data_13 : X_SFF generic map( LOC => "SLICE_X0Y40", INIT => '0' ) port map ( I => write_send_data_13_DXMUX_4446, CE => write_send_data_13_CEINV_4421, CLK => write_send_data_13_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_13_SRINV_4423, O => write_send_data(13) ); read_send_data_0_mux00001 : X_LUT4 generic map( INIT => X"0020", LOC => "SLICE_X0Y30" ) port map ( ADR0 => N3, ADR1 => read_receive_data_0_cmp_gt00001_1316, ADR2 => reg_addr_0_IBUF_1361, ADR3 => bit_counter(6), O => read_send_data_0_mux0000 ); read_send_data_0 : X_SFF generic map( LOC => "SLICE_X0Y30", INIT => '0' ) port map ( I => read_send_data_1_DYMUX_4474, CE => read_send_data_1_CEINV_4464, CLK => read_send_data_1_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => read_send_data_1_SRINV_4466, O => read_send_data(0) ); read_send_data_1_mux00001 : X_LUT4 generic map( INIT => X"DD88", LOC => "SLICE_X0Y30" ) port map ( ADR0 => read_send_data_11_not0001_inv, ADR1 => reg_addr_1_IBUF_1360, ADR2 => VCC, ADR3 => read_send_data(0), O => read_send_data_1_mux0000 ); read_send_data_1 : X_SFF generic map( LOC => "SLICE_X0Y30", INIT => '0' ) port map ( I => read_send_data_1_DXMUX_4488, CE => read_send_data_1_CEINV_4464, CLK => read_send_data_1_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => read_send_data_1_SRINV_4466, O => read_send_data(1) ); write_send_data_mux00341 : X_LUT4 generic map( INIT => X"ABAA", LOC => "SLICE_X22Y31" ) port map ( ADR0 => write_send_data(29), ADR1 => bit_counter(6), ADR2 => read_receive_data_0_cmp_gt00001_1316, ADR3 => N3, O => write_send_data_mux0034 ); write_send_data_30 : X_SFF generic map( LOC => "SLICE_X22Y31", INIT => '0' ) port map ( I => write_send_data_31_DYMUX_4517, CE => write_send_data_31_CEINV_4507, CLK => write_send_data_31_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_31_SRINV_4509, O => write_send_data(30) ); write_send_data_mux00331 : X_LUT4 generic map( INIT => X"C8CC", LOC => "SLICE_X22Y31" ) port map ( ADR0 => bit_counter(6), ADR1 => write_send_data(30), ADR2 => read_receive_data_0_cmp_gt00001_1316, ADR3 => N3, O => write_send_data_mux0033 ); write_send_data_31 : X_SFF generic map( LOC => "SLICE_X22Y31", INIT => '0' ) port map ( I => write_send_data_31_DXMUX_4530, CE => write_send_data_31_CEINV_4507, CLK => write_send_data_31_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_31_SRINV_4509, O => write_send_data(31) ); write_send_data_mux00421 : X_LUT4 generic map( INIT => X"ACAC", LOC => "SLICE_X12Y9" ) port map ( ADR0 => latched_reg_addr(4), ADR1 => write_send_data(21), ADR2 => read_send_data_11_not0001_inv, ADR3 => VCC, O => write_send_data_mux0042 ); write_send_data_22 : X_SFF generic map( LOC => "SLICE_X12Y9", INIT => '0' ) port map ( I => write_send_data_23_DYMUX_4558, CE => write_send_data_23_CEINV_4547, CLK => write_send_data_23_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_23_SRINV_4549, O => write_send_data(22) ); write_send_data_mux00411 : X_LUT4 generic map( INIT => X"DD88", LOC => "SLICE_X12Y9" ) port map ( ADR0 => read_send_data_11_not0001_inv, ADR1 => latched_phy_addr(0), ADR2 => VCC, ADR3 => write_send_data(22), O => write_send_data_mux0041 ); write_send_data_23 : X_SFF generic map( LOC => "SLICE_X12Y9", INIT => '0' ) port map ( I => write_send_data_23_DXMUX_4572, CE => write_send_data_23_CEINV_4547, CLK => write_send_data_23_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_23_SRINV_4549, O => write_send_data(23) ); write_send_data_mux00481 : X_LUT4 generic map( INIT => X"CCF0", LOC => "SLICE_X1Y37" ) port map ( ADR0 => VCC, ADR1 => latched_data(14), ADR2 => write_send_data(13), ADR3 => read_send_data_11_not0001_inv, O => write_send_data_mux0048 ); write_send_data_14 : X_SFF generic map( LOC => "SLICE_X1Y37", INIT => '0' ) port map ( I => write_send_data_15_DYMUX_4600, CE => write_send_data_15_CEINV_4589, CLK => write_send_data_15_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_15_SRINV_4591, O => write_send_data(14) ); write_send_data_mux00471 : X_LUT4 generic map( INIT => X"F5A0", LOC => "SLICE_X1Y37" ) port map ( ADR0 => read_send_data_11_not0001_inv, ADR1 => VCC, ADR2 => latched_data(15), ADR3 => write_send_data(14), O => write_send_data_mux0047 ); write_send_data_15 : X_SFF generic map( LOC => "SLICE_X1Y37", INIT => '0' ) port map ( I => write_send_data_15_DXMUX_4614, CE => write_send_data_15_CEINV_4589, CLK => write_send_data_15_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_15_SRINV_4591, O => write_send_data(15) ); read_send_data_2_mux00001 : X_LUT4 generic map( INIT => X"AAF0", LOC => "SLICE_X0Y27" ) port map ( ADR0 => reg_addr_2_IBUF_1366, ADR1 => VCC, ADR2 => read_send_data(1), ADR3 => read_send_data_11_not0001_inv, O => read_send_data_2_mux0000 ); read_send_data_2 : X_SFF generic map( LOC => "SLICE_X0Y27", INIT => '0' ) port map ( I => read_send_data_3_DYMUX_4642, CE => read_send_data_3_CEINV_4631, CLK => read_send_data_3_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => read_send_data_3_SRINV_4633, O => read_send_data(2) ); read_send_data_3_mux00001 : X_LUT4 generic map( INIT => X"CFC0", LOC => "SLICE_X0Y27" ) port map ( ADR0 => VCC, ADR1 => reg_addr_3_IBUF_1365, ADR2 => read_send_data_11_not0001_inv, ADR3 => read_send_data(2), O => read_send_data_3_mux0000 ); read_send_data_3 : X_SFF generic map( LOC => "SLICE_X0Y27", INIT => '0' ) port map ( I => read_send_data_3_DXMUX_4656, CE => read_send_data_3_CEINV_4631, CLK => read_send_data_3_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => read_send_data_3_SRINV_4633, O => read_send_data(3) ); write_send_data_mux00241 : X_LUT4 generic map( INIT => X"CCCE", LOC => "SLICE_X22Y48" ) port map ( ADR0 => N3, ADR1 => write_send_data(39), ADR2 => bit_counter(6), ADR3 => read_receive_data_0_cmp_gt00001_1316, O => write_send_data_mux0024 ); write_send_data_40 : X_SFF generic map( LOC => "SLICE_X22Y48", INIT => '0' ) port map ( I => write_send_data_41_DYMUX_4685, CE => write_send_data_41_CEINV_4675, CLK => write_send_data_41_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_41_SRINV_4677, O => write_send_data(40) ); write_send_data_mux00231 : X_LUT4 generic map( INIT => X"CCCE", LOC => "SLICE_X22Y48" ) port map ( ADR0 => N3, ADR1 => write_send_data(40), ADR2 => bit_counter(6), ADR3 => read_receive_data_0_cmp_gt00001_1316, O => write_send_data_mux0023 ); write_send_data_41 : X_SFF generic map( LOC => "SLICE_X22Y48", INIT => '0' ) port map ( I => write_send_data_41_DXMUX_4698, CE => write_send_data_41_CEINV_4675, CLK => write_send_data_41_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_41_SRINV_4677, O => write_send_data(41) ); write_send_data_mux00321 : X_LUT4 generic map( INIT => X"F1F0", LOC => "SLICE_X22Y35" ) port map ( ADR0 => read_receive_data_0_cmp_gt00001_1316, ADR1 => bit_counter(6), ADR2 => write_send_data(31), ADR3 => N3, O => write_send_data_mux0032 ); write_send_data_32 : X_SFF generic map( LOC => "SLICE_X22Y35", INIT => '0' ) port map ( I => write_send_data_33_DYMUX_4727, CE => write_send_data_33_CEINV_4717, CLK => write_send_data_33_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_33_SRINV_4719, O => write_send_data(32) ); write_send_data_mux00311 : X_LUT4 generic map( INIT => X"FF04", LOC => "SLICE_X22Y35" ) port map ( ADR0 => read_receive_data_0_cmp_gt00001_1316, ADR1 => N3, ADR2 => bit_counter(6), ADR3 => write_send_data(32), O => write_send_data_mux0031 ); write_send_data_33 : X_SFF generic map( LOC => "SLICE_X22Y35", INIT => '0' ) port map ( I => write_send_data_33_DXMUX_4740, CE => write_send_data_33_CEINV_4717, CLK => write_send_data_33_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_33_SRINV_4719, O => write_send_data(33) ); write_send_data_mux00401 : X_LUT4 generic map( INIT => X"FC0C", LOC => "SLICE_X15Y15" ) port map ( ADR0 => VCC, ADR1 => write_send_data(23), ADR2 => read_send_data_11_not0001_inv, ADR3 => latched_phy_addr(1), O => write_send_data_mux0040 ); write_send_data_24 : X_SFF generic map( LOC => "SLICE_X15Y15", INIT => '0' ) port map ( I => write_send_data_25_DYMUX_4768, CE => write_send_data_25_CEINV_4757, CLK => write_send_data_25_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_25_SRINV_4759, O => write_send_data(24) ); write_send_data_mux00391 : X_LUT4 generic map( INIT => X"CFC0", LOC => "SLICE_X15Y15" ) port map ( ADR0 => VCC, ADR1 => latched_phy_addr(2), ADR2 => read_send_data_11_not0001_inv, ADR3 => write_send_data(24), O => write_send_data_mux0039 ); write_send_data_25 : X_SFF generic map( LOC => "SLICE_X15Y15", INIT => '0' ) port map ( I => write_send_data_25_DXMUX_4782, CE => write_send_data_25_CEINV_4757, CLK => write_send_data_25_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_25_SRINV_4759, O => write_send_data(25) ); write_send_data_index0003LogicTrst1 : X_LUT4 generic map( INIT => X"CDCC", LOC => "SLICE_X12Y31" ) port map ( ADR0 => read_receive_data_0_cmp_gt00001_1316, ADR1 => write_send_data(15), ADR2 => bit_counter(6), ADR3 => N3, O => write_send_data_index0003 ); write_send_data_16 : X_SFF generic map( LOC => "SLICE_X12Y31", INIT => '0' ) port map ( I => write_send_data_17_DYMUX_4811, CE => write_send_data_17_CEINV_4801, CLK => write_send_data_17_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_17_SRINV_4803, O => write_send_data(16) ); write_send_data_index0001LogicTrst1 : X_LUT4 generic map( INIT => X"FF04", LOC => "SLICE_X12Y31" ) port map ( ADR0 => read_receive_data_0_cmp_gt00001_1316, ADR1 => N3, ADR2 => bit_counter(6), ADR3 => write_send_data(16), O => write_send_data_index0001 ); write_send_data_17 : X_SFF generic map( LOC => "SLICE_X12Y31", INIT => '0' ) port map ( I => write_send_data_17_DXMUX_4824, CE => write_send_data_17_CEINV_4801, CLK => write_send_data_17_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_17_SRINV_4803, O => write_send_data(17) ); read_send_data_4_mux00001 : X_LUT4 generic map( INIT => X"F5A0", LOC => "SLICE_X1Y29" ) port map ( ADR0 => read_send_data_11_not0001_inv, ADR1 => VCC, ADR2 => reg_addr_4_IBUF_1369, ADR3 => read_send_data(3), O => read_send_data_4_mux0000 ); read_send_data_4 : X_SFF generic map( LOC => "SLICE_X1Y29", INIT => '0' ) port map ( I => read_send_data_5_DYMUX_4852, CE => read_send_data_5_CEINV_4841, CLK => read_send_data_5_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => read_send_data_5_SRINV_4843, O => read_send_data(4) ); read_send_data_5_mux00001 : X_LUT4 generic map( INIT => X"DD88", LOC => "SLICE_X1Y29" ) port map ( ADR0 => read_send_data_11_not0001_inv, ADR1 => phy_addr_0_IBUF_1387, ADR2 => VCC, ADR3 => read_send_data(4), O => read_send_data_5_mux0000 ); read_send_data_5 : X_SFF generic map( LOC => "SLICE_X1Y29", INIT => '0' ) port map ( I => read_send_data_5_DXMUX_4866, CE => read_send_data_5_CEINV_4841, CLK => read_send_data_5_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => read_send_data_5_SRINV_4843, O => read_send_data(5) ); write_send_data_mux00141 : X_LUT4 generic map( INIT => X"FF02", LOC => "SLICE_X21Y54" ) port map ( ADR0 => N3, ADR1 => bit_counter(6), ADR2 => read_receive_data_0_cmp_gt00001_1316, ADR3 => write_send_data(49), O => write_send_data_mux0014 ); write_send_data_50 : X_SFF generic map( LOC => "SLICE_X21Y54", INIT => '0' ) port map ( I => write_send_data_51_DYMUX_4895, CE => write_send_data_51_CEINV_4885, CLK => write_send_data_51_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_51_SRINV_4887, O => write_send_data(50) ); write_send_data_mux00131 : X_LUT4 generic map( INIT => X"AAAE", LOC => "SLICE_X21Y54" ) port map ( ADR0 => write_send_data(50), ADR1 => N3, ADR2 => read_receive_data_0_cmp_gt00001_1316, ADR3 => bit_counter(6), O => write_send_data_mux0013 ); write_send_data_51 : X_SFF generic map( LOC => "SLICE_X21Y54", INIT => '0' ) port map ( I => write_send_data_51_DXMUX_4908, CE => write_send_data_51_CEINV_4885, CLK => write_send_data_51_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_51_SRINV_4887, O => write_send_data(51) ); write_send_data_mux00221 : X_LUT4 generic map( INIT => X"AAAE", LOC => "SLICE_X22Y49" ) port map ( ADR0 => write_send_data(41), ADR1 => N3, ADR2 => bit_counter(6), ADR3 => read_receive_data_0_cmp_gt00001_1316, O => write_send_data_mux0022 ); write_send_data_42 : X_SFF generic map( LOC => "SLICE_X22Y49", INIT => '0' ) port map ( I => write_send_data_43_DYMUX_4937, CE => write_send_data_43_CEINV_4927, CLK => write_send_data_43_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_43_SRINV_4929, O => write_send_data(42) ); write_send_data_mux00211 : X_LUT4 generic map( INIT => X"FF02", LOC => "SLICE_X22Y49" ) port map ( ADR0 => N3, ADR1 => read_receive_data_0_cmp_gt00001_1316, ADR2 => bit_counter(6), ADR3 => write_send_data(42), O => write_send_data_mux0021 ); write_send_data_43 : X_SFF generic map( LOC => "SLICE_X22Y49", INIT => '0' ) port map ( I => write_send_data_43_DXMUX_4950, CE => write_send_data_43_CEINV_4927, CLK => write_send_data_43_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_43_SRINV_4929, O => write_send_data(43) ); write_send_data_mux00301 : X_LUT4 generic map( INIT => X"FF10", LOC => "SLICE_X21Y41" ) port map ( ADR0 => read_receive_data_0_cmp_gt00001_1316, ADR1 => bit_counter(6), ADR2 => N3, ADR3 => write_send_data(33), O => write_send_data_mux0030 ); write_send_data_34 : X_SFF generic map( LOC => "SLICE_X21Y41", INIT => '0' ) port map ( I => write_send_data_35_DYMUX_4979, CE => write_send_data_35_CEINV_4969, CLK => write_send_data_35_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_35_SRINV_4971, O => write_send_data(34) ); write_send_data_mux00291 : X_LUT4 generic map( INIT => X"FF10", LOC => "SLICE_X21Y41" ) port map ( ADR0 => read_receive_data_0_cmp_gt00001_1316, ADR1 => bit_counter(6), ADR2 => N3, ADR3 => write_send_data(34), O => write_send_data_mux0029 ); write_send_data_35 : X_SFF generic map( LOC => "SLICE_X21Y41", INIT => '0' ) port map ( I => write_send_data_35_DXMUX_4992, CE => write_send_data_35_CEINV_4969, CLK => write_send_data_35_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_35_SRINV_4971, O => write_send_data(35) ); write_send_data_mux00381 : X_LUT4 generic map( INIT => X"FC0C", LOC => "SLICE_X19Y15" ) port map ( ADR0 => VCC, ADR1 => write_send_data(25), ADR2 => read_send_data_11_not0001_inv, ADR3 => latched_phy_addr(3), O => write_send_data_mux0038 ); write_send_data_26 : X_SFF generic map( LOC => "SLICE_X19Y15", INIT => '0' ) port map ( I => write_send_data_27_DYMUX_5020, CE => write_send_data_27_CEINV_5009, CLK => write_send_data_27_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_27_SRINV_5011, O => write_send_data(26) ); write_send_data_mux00371 : X_LUT4 generic map( INIT => X"CFC0", LOC => "SLICE_X19Y15" ) port map ( ADR0 => VCC, ADR1 => latched_phy_addr(4), ADR2 => read_send_data_11_not0001_inv, ADR3 => write_send_data(26), O => write_send_data_mux0037 ); write_send_data_27 : X_SFF generic map( LOC => "SLICE_X19Y15", INIT => '0' ) port map ( I => write_send_data_27_DXMUX_5034, CE => write_send_data_27_CEINV_5009, CLK => write_send_data_27_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_27_SRINV_5011, O => write_send_data(27) ); write_send_data_54 : X_SFF generic map( LOC => "SLICE_X20Y54", INIT => '0' ) port map ( I => write_send_data_55_DYMUX_5441, CE => write_send_data_55_CEINV_5431, CLK => write_send_data_55_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_55_SRINV_5433, O => write_send_data(54) ); write_send_data_mux00091 : X_LUT4 generic map( INIT => X"FF04", LOC => "SLICE_X20Y54" ) port map ( ADR0 => read_receive_data_0_cmp_gt00001_1316, ADR1 => N3, ADR2 => bit_counter(6), ADR3 => write_send_data(54), O => write_send_data_mux0009 ); write_send_data_55 : X_SFF generic map( LOC => "SLICE_X20Y54", INIT => '0' ) port map ( I => write_send_data_55_DXMUX_5454, CE => write_send_data_55_CEINV_5431, CLK => write_send_data_55_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_55_SRINV_5433, O => write_send_data(55) ); write_send_data_mux00181 : X_LUT4 generic map( INIT => X"FF02", LOC => "SLICE_X21Y55" ) port map ( ADR0 => N3, ADR1 => bit_counter(6), ADR2 => read_receive_data_0_cmp_gt00001_1316, ADR3 => write_send_data(45), O => write_send_data_mux0018 ); write_send_data_46 : X_SFF generic map( LOC => "SLICE_X21Y55", INIT => '0' ) port map ( I => write_send_data_47_DYMUX_5483, CE => write_send_data_47_CEINV_5473, CLK => write_send_data_47_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_47_SRINV_5475, O => write_send_data(46) ); write_send_data_mux00171 : X_LUT4 generic map( INIT => X"FF02", LOC => "SLICE_X21Y55" ) port map ( ADR0 => N3, ADR1 => bit_counter(6), ADR2 => read_receive_data_0_cmp_gt00001_1316, ADR3 => write_send_data(46), O => write_send_data_mux0017 ); write_send_data_47 : X_SFF generic map( LOC => "SLICE_X21Y55", INIT => '0' ) port map ( I => write_send_data_47_DXMUX_5496, CE => write_send_data_47_CEINV_5473, CLK => write_send_data_47_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_47_SRINV_5475, O => write_send_data(47) ); write_send_data_mux00261 : X_LUT4 generic map( INIT => X"AAAE", LOC => "SLICE_X20Y49" ) port map ( ADR0 => write_send_data(37), ADR1 => N3, ADR2 => bit_counter(6), ADR3 => read_receive_data_0_cmp_gt00001_1316, O => write_send_data_mux0026 ); write_send_data_38 : X_SFF generic map( LOC => "SLICE_X20Y49", INIT => '0' ) port map ( I => write_send_data_39_DYMUX_5525, CE => write_send_data_39_CEINV_5515, CLK => write_send_data_39_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_39_SRINV_5517, O => write_send_data(38) ); write_send_data_mux00251 : X_LUT4 generic map( INIT => X"FF02", LOC => "SLICE_X20Y49" ) port map ( ADR0 => N3, ADR1 => read_receive_data_0_cmp_gt00001_1316, ADR2 => bit_counter(6), ADR3 => write_send_data(38), O => write_send_data_mux0025 ); write_send_data_39 : X_SFF generic map( LOC => "SLICE_X20Y49", INIT => '0' ) port map ( I => write_send_data_39_DXMUX_5538, CE => write_send_data_39_CEINV_5515, CLK => write_send_data_39_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_39_SRINV_5517, O => write_send_data(39) ); write_send_data_mux00081 : X_LUT4 generic map( INIT => X"FF02", LOC => "SLICE_X19Y52" ) port map ( ADR0 => N3, ADR1 => read_receive_data_0_cmp_gt00001_1316, ADR2 => bit_counter(6), ADR3 => write_send_data(55), O => write_send_data_mux0008 ); write_send_data_56 : X_SFF generic map( LOC => "SLICE_X19Y52", INIT => '0' ) port map ( I => write_send_data_57_DYMUX_5567, CE => write_send_data_57_CEINV_5557, CLK => write_send_data_57_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_57_SRINV_5559, O => write_send_data(56) ); write_send_data_mux00071 : X_LUT4 generic map( INIT => X"AAAE", LOC => "SLICE_X19Y52" ) port map ( ADR0 => write_send_data(56), ADR1 => N3, ADR2 => bit_counter(6), ADR3 => read_receive_data_0_cmp_gt00001_1316, O => write_send_data_mux0007 ); write_send_data_57 : X_SFF generic map( LOC => "SLICE_X19Y52", INIT => '0' ) port map ( I => write_send_data_57_DXMUX_5580, CE => write_send_data_57_CEINV_5557, CLK => write_send_data_57_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_57_SRINV_5559, O => write_send_data(57) ); write_send_data_mux00161 : X_LUT4 generic map( INIT => X"F1F0", LOC => "SLICE_X20Y55" ) port map ( ADR0 => bit_counter(6), ADR1 => read_receive_data_0_cmp_gt00001_1316, ADR2 => write_send_data(47), ADR3 => N3, O => write_send_data_mux0016 ); write_send_data_48 : X_SFF generic map( LOC => "SLICE_X20Y55", INIT => '0' ) port map ( I => write_send_data_49_DYMUX_5609, CE => write_send_data_49_CEINV_5599, CLK => write_send_data_49_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_49_SRINV_5601, O => write_send_data(48) ); write_send_data_mux00151 : X_LUT4 generic map( INIT => X"CDCC", LOC => "SLICE_X20Y55" ) port map ( ADR0 => read_receive_data_0_cmp_gt00001_1316, ADR1 => write_send_data(48), ADR2 => bit_counter(6), ADR3 => N3, O => write_send_data_mux0015 ); write_send_data_49 : X_SFF generic map( LOC => "SLICE_X20Y55", INIT => '0' ) port map ( I => write_send_data_49_DXMUX_5622, CE => write_send_data_49_CEINV_5599, CLK => write_send_data_49_CLKINVNOT, SET => GND, RST => GND, SSET => GND, SRST => write_send_data_49_SRINV_5601, O => write_send_data(49) ); bit_counter_0_G_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X15Y78" ) port map ( ADR0 => VCC, ADR1 => bit_counter(1), ADR2 => VCC, ADR3 => VCC, O => bit_counter_0_G ); bit_counter_2_F_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X15Y79" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => bit_counter(2), O => bit_counter_2_F ); bit_counter_2_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X15Y79" ) port map ( ADR0 => bit_counter(3), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => bit_counter_2_G ); bit_counter_4_F_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X15Y80" ) port map ( ADR0 => bit_counter(4), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => bit_counter_4_F ); bit_counter_4_G_X_LUT4 : X_LUT4 generic map( INIT => X"CCCC", LOC => "SLICE_X15Y80" ) port map ( ADR0 => VCC, ADR1 => bit_counter(5), ADR2 => VCC, ADR3 => VCC, O => bit_counter_4_G ); bit_counter_6_F_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X15Y81" ) port map ( ADR0 => bit_counter(6), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => bit_counter_6_F ); counter_0_G_X_LUT4 : X_LUT4 generic map( INIT => X"AAAA", LOC => "SLICE_X49Y82" ) port map ( ADR0 => counter(1), ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => counter_0_G ); counter_2_F_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X49Y83" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => counter(2), ADR3 => VCC, O => counter_2_F ); counter_2_G_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X49Y83" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => counter(3), ADR3 => VCC, O => counter_2_G ); counter_4_F_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X49Y84" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => counter(4), O => counter_4_F ); counter_4_G_X_LUT4 : X_LUT4 generic map( INIT => X"F0F0", LOC => "SLICE_X49Y84" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => counter(5), ADR3 => VCC, O => counter_4_G ); counter_6_F_X_LUT4 : X_LUT4 generic map( INIT => X"FF00", LOC => "SLICE_X49Y85" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => counter(6), O => counter_6_F ); MDIO_OUTPUT_TFF_TMUX : X_BUF generic map( LOC => "PAD210", PATHPULSE => 638 ps ) port map ( I => Mtrien_MDIO_1353, O => MDIO_T ); MDIO_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD210", PATHPULSE => 638 ps ) port map ( I => Mtridata_MDIO_1348, O => MDIO_O ); data_out_10_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD220", PATHPULSE => 638 ps ) port map ( I => read_receive_data(10), O => data_out_10_O ); data_out_11_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD218", PATHPULSE => 638 ps ) port map ( I => read_receive_data(11), O => data_out_11_O ); data_out_12_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD217", PATHPULSE => 638 ps ) port map ( I => read_receive_data(12), O => data_out_12_O ); data_out_13_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD216", PATHPULSE => 638 ps ) port map ( I => read_receive_data(13), O => data_out_13_O ); data_out_0_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD232", PATHPULSE => 638 ps ) port map ( I => read_receive_data(0), O => data_out_0_O ); data_out_1_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD227", PATHPULSE => 638 ps ) port map ( I => read_receive_data(1), O => data_out_1_O ); data_out_14_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD215", PATHPULSE => 638 ps ) port map ( I => read_receive_data(14), O => data_out_14_O ); data_out_2_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD230", PATHPULSE => 638 ps ) port map ( I => read_receive_data(2), O => data_out_2_O ); data_out_15_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD213", PATHPULSE => 638 ps ) port map ( I => read_receive_data(15), O => data_out_15_O ); data_out_3_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD229", PATHPULSE => 638 ps ) port map ( I => read_receive_data(3), O => data_out_3_O ); data_out_4_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD5", PATHPULSE => 638 ps ) port map ( I => read_receive_data(4), O => data_out_4_O ); data_out_5_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD226", PATHPULSE => 638 ps ) port map ( I => read_receive_data(5), O => data_out_5_O ); data_out_6_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD225", PATHPULSE => 638 ps ) port map ( I => read_receive_data(6), O => data_out_6_O ); data_out_7_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD223", PATHPULSE => 638 ps ) port map ( I => read_receive_data(7), O => data_out_7_O ); data_out_8_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD222", PATHPULSE => 638 ps ) port map ( I => read_receive_data(8), O => data_out_8_O ); data_out_9_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD221", PATHPULSE => 638 ps ) port map ( I => read_receive_data(9), O => data_out_9_O ); counter_or0000_F_X_LUT4 : X_LUT4 generic map( INIT => X"FFFF", LOC => "SLICE_X48Y83" ) port map ( ADR0 => VCC, ADR1 => VCC, ADR2 => VCC, ADR3 => VCC, O => counter_or0000_F ); MDC_OUTPUT_OFF_OMUX : X_BUF generic map( LOC => "PAD12", PATHPULSE => 638 ps ) port map ( I => Mtridata_MDC_1397, O => MDC_O ); NlwBlock_nowyRXTX_GND : X_ZERO port map ( O => GND ); NlwBlock_nowyRXTX_VCC : X_ONE port map ( O => VCC ); NlwBlockROC : X_ROC generic map (ROC_WIDTH => 100 ns) port map (O => GSR); NlwBlockTOC : X_TOC port map (O => GTS); end Structure; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity logical_unit is Port ( RA : in STD_LOGIC_VECTOR (15 downto 0); RB : in STD_LOGIC_VECTOR (15 downto 0); OP : in STD_LOGIC_VECTOR (2 downto 0); LOG_OUT : out STD_LOGIC_VECTOR (15 downto 0); SREG_OUT : out STD_LOGIC_VECTOR (3 downto 0)); end logical_unit; architecture Combinational of logical_unit is signal result : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); signal zro : STD_LOGIC := '0'; begin with OP select result <= RA or RB when "011", -- OR RA and RB when "010", -- AND RA and RB when "110", -- ANDI RB when "100", -- MOV RA or RB when OTHERS; -- SAFE (I guess) zro <= '1' when result(15 downto 0) = x"00000000" else '0'; -- Zero LOG_OUT <= result; SREG_OUT <= '0' & zro & "00"; end Combinational; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity and2 is port ( A : in std_logic; B : in std_logic; Y : out std_logic ); end entity; architecture behavior of and2 is begin Y <= A and B; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity and3 is port ( A : in std_logic; B : in std_logic; C : in std_logic; Y : out std_logic ); end entity; architecture behavior of and3 is begin Y <= A and B and C; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity and4 is port ( A : in std_logic; B : in std_logic; C : in std_logic; D : in std_logic; Y : out std_logic ); end entity; architecture behavior of and4 is begin Y <= A and B and C and D; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ao21 is port ( A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; Y : out std_logic ); end entity; architecture behavior of ao21 is begin Y <= (A0 and A1) or B0; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ao22 is port ( A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; B1 : in std_logic; Y : out std_logic ); end entity; architecture behavior of ao22 is begin Y <= (A0 and A1) or (B0 and B1); end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity aoi21 is port ( A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; Y : out std_logic ); end entity; architecture behavior of aoi21 is begin Y <= not ((A0 and A1) or B0); end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity aoi22 is port ( A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; B1 : in std_logic; Y : out std_logic ); end entity; architecture behavior of aoi22 is begin Y <= not ((A0 and A1) or (B0 and B1)); end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity buffer_module is port ( A : in std_logic; Y : out std_logic ); end entity; architecture behavior of buffer_module is begin Y <= A; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity inverter is port ( A : in std_logic; Y : out std_logic ); end entity; architecture behavior of inverter is begin Y <= not A; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mux2 is port ( A : in std_logic; B : in std_logic; S : in std_logic; Y : out std_logic ); end entity; architecture behavior of mux2 is begin Y <= B when S = '1' else A; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity muxi2 is port ( A : in std_logic; B : in std_logic; S : in std_logic; Y : out std_logic ); end entity; begin Y <= not (B when S = '1' else A); end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nand2 is port ( A : in std_logic; B : in std_logic; Y : out std_logic ); end entity; architecture behavior of nand2 is begin Y <= not (A and B); end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nand2b is port ( A : in std_logic; B : in std_logic; Y : out std_logic ); end entity; architecture behavior of nand2b is begin Y <= not (not A and B); end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nand3 is port ( A : in std_logic; B : in std_logic; C : in std_logic; Y : out std_logic ); end entity; architecture behavior of nand3 is begin Y <= not (A and B and C); end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nand4 is port ( A : in std_logic; B : in std_logic; C : in std_logic; D : in std_logic; Y : out std_logic ); end entity; architecture behavior of nand4 is begin Y <= not (A and B and C and D); end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nor2 is port ( A : in std_logic; B : in std_logic; Y : out std_logic ); end entity; architecture behavior of nor2 is begin Y <= not (A or B); end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nor2b is port ( A : in std_logic; B : in std_logic; Y : out std_logic ); end entity; architecture behavior of nor2b is begin Y <= not (not A or B); end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nor3 is port ( A : in std_logic; B : in std_logic; C : in std_logic; Y : out std_logic ); end entity; architecture behavior of nor3 is begin Y <= not (A or B or C); end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity nor4 is port ( A : in std_logic; B : in std_logic; C : in std_logic; D : in std_logic; Y : out std_logic ); end entity; architecture behavior of nor4 is begin Y <= not (A or B or C or D); end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity oa21 is port ( A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; Y : out std_logic ); end entity; architecture behavior of oa21 is begin Y <= (A0 or A1) and B0; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity oa22 is port ( A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; B1 : in std_logic; Y : out std_logic ); end entity; architecture behavior of oa22 is begin Y <= (A0 or A1) and (B0 or B1); end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity oai21 is port ( A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; Y : out std_logic ); end entity; architecture behavior of oai21 is begin Y <= not ((A0 or A1) and B0); end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity oai22 is port ( A0 : in std_logic; A1 : in std_logic; B0 : in std_logic; B1 : in std_logic; Y : out std_logic ); end entity; architecture behavior of oai22 is begin Y <= not (A0 or A1) and (B0 or B1); end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity or2 is port ( A : in std_logic; B : in std_logic; Y : out std_logic ); end entity; architecture behavior of or2 is begin Y <= A or B; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity or3 is port ( A : in std_logic; B : in std_logic; C : in std_logic; Y : out std_logic ); end entity; architecture behavior of or3 is begin Y <= A or B or C; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity or4 is port ( A : in std_logic; B : in std_logic; C : in std_logic; D : in std_logic; Y : out std_logic ); end entity; architecture behavior of or4 is begin Y <= A or B or C or D; end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity xnor2 is port ( A : in std_logic; B : in std_logic; Y : out std_logic ); end entity; architecture behavior of xnor2 is begin Y <= not (A xor B); end architecture; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity xor2 is port ( A : in std_logic; B : in std_logic; Y : out std_logic ); end entity; architecture behavior of xor2 is begin Y <= A xor B; end architecture; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library uvvm_util; context uvvm_util.uvvm_util_context; library uvvm_vvc_framework; use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all; use work.local_adaptations_pkg.all; use work.avalon_st_bfm_pkg.all; use work.vvc_cmd_pkg.all; use work.td_target_support_pkg.all; use work.transaction_pkg.all; package vvc_methods_pkg is --========================================================================================== -- Types and constants for the AVALON_ST VVC --========================================================================================== constant C_VVC_NAME : string := "AVALON_ST_VVC"; signal AVALON_ST_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME); alias THIS_VVCT : t_vvc_target_record is AVALON_ST_VVCT; alias t_bfm_config is t_avalon_st_bfm_config; -- Type found in UVVM-Util types_pkg constant C_AVALON_ST_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := ( delay_type => NO_DELAY, delay_in_time => 0 ns, inter_bfm_delay_violation_severity => WARNING ); type t_vvc_config is record inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay. cmd_queue_count_max : natural; -- Maximum pending number in command executor before executor is full. Adding additional commands will result in an ERROR. cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command executor exceeds this count. Used for early warning if command executor is almost full. Will be ignored if set to 0. cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold. result_queue_count_max : natural; result_queue_count_threshold_severity : t_alert_level; result_queue_count_threshold : natural; bfm_config : t_avalon_st_bfm_config; -- Configuration for the BFM. See BFM quick reference. msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel. parent_msg_id_panel : t_msg_id_panel; --UVVM: temporary fix for HVVC, remove in v3.0 end record; type t_vvc_config_array is array (natural range <>) of t_vvc_config; constant C_AVALON_ST_VVC_CONFIG_DEFAULT : t_vvc_config := ( inter_bfm_delay => C_AVALON_ST_INTER_BFM_DELAY_DEFAULT, cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX, -- from adaptation package cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD, cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY, result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX, result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY, result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD, bfm_config => C_AVALON_ST_BFM_CONFIG_DEFAULT, msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT, parent_msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT ); type t_vvc_status is record current_cmd_idx : natural; previous_cmd_idx : natural; pending_cmd_cnt : natural; end record; type t_vvc_status_array is array (natural range <>) of t_vvc_status; constant C_VVC_STATUS_DEFAULT : t_vvc_status := ( current_cmd_idx => 0, previous_cmd_idx => 0, pending_cmd_cnt => 0 ); shared variable shared_avalon_st_vvc_config : t_vvc_config_array(0 to C_AVALON_ST_MAX_VVC_INSTANCE_NUM-1) := (others => C_AVALON_ST_VVC_CONFIG_DEFAULT); shared variable shared_avalon_st_vvc_status : t_vvc_status_array(0 to C_AVALON_ST_MAX_VVC_INSTANCE_NUM-1) := (others => C_VVC_STATUS_DEFAULT); --========================================================================================== -- Methods dedicated to this VVC -- - These procedures are called from the testbench in order for the VVC to execute -- BFM calls towards the given interface. The VVC interpreter will queue these calls -- and then the VVC executor will fetch the commands from the queue and handle the -- actual BFM execution. --========================================================================================== --------------------------------------------------------------------------------------------- -- Avalon-ST Transmit --------------------------------------------------------------------------------------------- procedure avalon_st_transmit ( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant channel_value : in std_logic_vector; constant data_array : in t_slv_array; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ); procedure avalon_st_transmit ( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data_array : in t_slv_array; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ); --------------------------------------------------------------------------------------------- -- Avalon-ST Receive --------------------------------------------------------------------------------------------- procedure avalon_st_receive ( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data_array_len : in natural; constant data_word_size : in natural; constant data_routing : in t_data_routing; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ); procedure avalon_st_receive ( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data_array_len : in natural; constant data_word_size : in natural; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ); --------------------------------------------------------------------------------------------- -- Avalon-ST Expect --------------------------------------------------------------------------------------------- procedure avalon_st_expect ( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant channel_exp : in std_logic_vector; constant data_exp : in t_slv_array; constant msg : in string; constant alert_level : in t_alert_level := error; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ); procedure avalon_st_expect ( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data_exp : in t_slv_array; constant msg : in string; constant alert_level : in t_alert_level := error; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ); --============================================================================== -- Transaction info methods --============================================================================== procedure set_global_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT); procedure reset_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record); --============================================================================== -- VVC Activity --============================================================================== procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic; variable vvc_status : inout t_vvc_status; constant activity : in t_activity; constant entry_num_in_vvc_activity_register : in integer; constant last_cmd_idx_executed : in natural; constant command_queue_is_empty : in boolean; constant scope : in string := C_VVC_NAME); end package vvc_methods_pkg; package body vvc_methods_pkg is --========================================================================================== -- Methods dedicated to this VVC --========================================================================================== --------------------------------------------------------------------------------------------- -- Avalon-ST Transmit --------------------------------------------------------------------------------------------- procedure avalon_st_transmit ( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant channel_value : in std_logic_vector; constant data_array : in t_slv_array; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ) is constant proc_name : string := "avalon_st_transmit"; constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all & ", " & to_string(data_array'length) & " words, ch:" & to_string(channel_value, DEC, AS_IS) & ")"; constant c_data_word_size : natural := data_array(data_array'low)'length; variable v_normalized_chan : std_logic_vector(C_VVC_CMD_CHAN_MAX_LENGTH-1 downto 0) := normalize_and_check(channel_value, shared_vvc_cmd.channel_value, ALLOW_NARROWER, "channel", "shared_vvc_cmd.channel", proc_call & ". " & msg); variable v_normalized_data : t_slv_array(0 to data_array'length-1)(c_data_word_size-1 downto 0) := data_array; variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, TRANSMIT); shared_vvc_cmd.channel_value := v_normalized_chan; for i in 0 to v_normalized_data'high loop shared_vvc_cmd.data_array(i)(c_data_word_size-1 downto 0) := v_normalized_data(i); end loop; shared_vvc_cmd.data_array_length := v_normalized_data'length; shared_vvc_cmd.data_array_word_size := c_data_word_size; shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then v_msg_id_panel := parent_msg_id_panel; end if; send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel); end procedure; procedure avalon_st_transmit ( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data_array : in t_slv_array; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ) is constant channel_value : std_logic_vector(C_VVC_CMD_CHAN_MAX_LENGTH-1 downto 0) := (others => '0'); begin avalon_st_transmit(VVCT, vvc_instance_idx, channel_value, data_array, msg, scope, parent_msg_id_panel); end procedure; --------------------------------------------------------------------------------------------- -- Avalon-ST Receive --------------------------------------------------------------------------------------------- procedure avalon_st_receive ( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data_array_len : in natural; constant data_word_size : in natural; constant data_routing : in t_data_routing; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ) is constant proc_name : string := "avalon_st_receive"; constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all & ")"; variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, RECEIVE); shared_vvc_cmd.data_array_length := data_array_len; shared_vvc_cmd.data_array_word_size := data_word_size; shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; shared_vvc_cmd.data_routing := data_routing; if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then v_msg_id_panel := parent_msg_id_panel; end if; send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel); end procedure; procedure avalon_st_receive ( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data_array_len : in natural; constant data_word_size : in natural; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ) is begin -- call overloaded procedure avalon_st_receive(VVCT, vvc_instance_idx, data_array_len, data_word_size, TO_BUFFER, msg, scope, parent_msg_id_panel); end procedure; --------------------------------------------------------------------------------------------- -- Avalon-ST Expect --------------------------------------------------------------------------------------------- procedure avalon_st_expect ( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant channel_exp : in std_logic_vector; constant data_exp : in t_slv_array; constant msg : in string; constant alert_level : in t_alert_level := error; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ) is constant proc_name : string := "avalon_st_expect"; constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all & ", " & to_string(data_exp'length) & " words, ch:" & to_string(channel_exp, DEC, AS_IS) & ")"; constant c_data_word_size : natural := data_exp(data_exp'low)'length; variable v_normalized_chan : std_logic_vector(C_VVC_CMD_CHAN_MAX_LENGTH-1 downto 0) := normalize_and_check(channel_exp, shared_vvc_cmd.channel_value, ALLOW_NARROWER, "channel", "shared_vvc_cmd.channel", proc_call & ". " & msg); variable v_normalized_data : t_slv_array(0 to data_exp'length-1)(c_data_word_size-1 downto 0) := data_exp; variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, EXPECT); shared_vvc_cmd.channel_value := v_normalized_chan; for i in 0 to v_normalized_data'high loop shared_vvc_cmd.data_array(i)(c_data_word_size-1 downto 0) := v_normalized_data(i); end loop; shared_vvc_cmd.data_array_length := v_normalized_data'length; shared_vvc_cmd.data_array_word_size := c_data_word_size; shared_vvc_cmd.alert_level := alert_level; shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then v_msg_id_panel := parent_msg_id_panel; end if; send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel); end procedure; procedure avalon_st_expect ( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant data_exp : in t_slv_array; constant msg : in string; constant alert_level : in t_alert_level := error; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ) is constant channel_exp : std_logic_vector(C_VVC_CMD_CHAN_MAX_LENGTH-1 downto 0) := (others => '0'); begin avalon_st_expect(VVCT, vvc_instance_idx, channel_exp, data_exp, msg, alert_level, scope, parent_msg_id_panel); end procedure; --============================================================================== -- Transaction info methods --============================================================================== procedure set_global_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT) is begin case vvc_cmd.operation is when TRANSMIT | RECEIVE | EXPECT => vvc_transaction_info_group.bt.operation := vvc_cmd.operation; vvc_transaction_info_group.bt.channel_value := vvc_cmd.channel_value; vvc_transaction_info_group.bt.data_array := vvc_cmd.data_array; vvc_transaction_info_group.bt.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg; vvc_transaction_info_group.bt.vvc_meta.cmd_idx := vvc_cmd.cmd_idx; vvc_transaction_info_group.bt.transaction_status := IN_PROGRESS; gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER); when others => alert(TB_ERROR, "VVC operation not recognized"); end case; wait for 0 ns; end procedure set_global_vvc_transaction_info; procedure reset_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record) is begin case vvc_cmd.operation is when TRANSMIT | RECEIVE | EXPECT => vvc_transaction_info_group.bt := C_BASE_TRANSACTION_SET_DEFAULT; when others => null; end case; wait for 0 ns; end procedure reset_vvc_transaction_info; --============================================================================== -- VVC Activity --============================================================================== procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic; variable vvc_status : inout t_vvc_status; constant activity : in t_activity; constant entry_num_in_vvc_activity_register : in integer; constant last_cmd_idx_executed : in natural; constant command_queue_is_empty : in boolean; constant scope : in string := C_VVC_NAME) is variable v_activity : t_activity := activity; begin -- Update vvc_status after a command has finished (during same delta cycle the activity register is updated) if activity = INACTIVE then vvc_status.previous_cmd_idx := last_cmd_idx_executed; vvc_status.current_cmd_idx := 0; end if; if v_activity = INACTIVE and not(command_queue_is_empty) then v_activity := ACTIVE; end if; shared_vvc_activity_register.priv_report_vvc_activity(vvc_idx => entry_num_in_vvc_activity_register, activity => v_activity, last_cmd_idx_executed => last_cmd_idx_executed); if global_trigger_vvc_activity_register /= 'L' then wait until global_trigger_vvc_activity_register = 'L'; end if; gen_pulse(global_trigger_vvc_activity_register, 0 ns, "pulsing global trigger for vvc activity register", scope, ID_NEVER); end procedure; end package body vvc_methods_pkg; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity PIXEL_CLK is port(CLK_IN: in std_logic; CLK_OUT: inout std_logic); end PIXEL_CLK; architecture Structural of PIXEL_CLK is signal clk100mhz : STD_LOGIC := '0'; begin CLK_100MHZ: entity work.CLK_100MHZ port map( CLK_IN => CLK_IN, CLK_OUT => clk100mhz); CLK_40MHZ: entity work.CLK_40MHZ port map( CLK_IN => clk100mhz, CLK_OUT => CLK_OUT); end Structural; |
library ieee; use ieee.std_logic_1164.all; entity tb_soc_uart is end entity tb_soc_uart; architecture testbench of tb_soc_uart is -- Clock signal: signal clk : std_logic := '0'; constant clk_period : time := 10 ns; -- Reset signal: signal reset : std_logic := '1'; -- UART ports: signal txd : std_logic; signal rxd : std_logic := '1'; -- interrupt signals: signal irq : std_logic; -- Wishbone ports: signal wb_adr_in : std_logic_vector(11 downto 0) := (others => '0'); signal wb_dat_in : std_logic_vector( 7 downto 0) := (others => '0'); signal wb_dat_out : std_logic_vector( 7 downto 0); signal wb_we_in : std_logic := '0'; signal wb_cyc_in : std_logic := '0'; signal wb_stb_in : std_logic := '0'; signal wb_ack_out : std_logic; begin uut: entity work.pp_soc_uart port map( clk => clk, reset => reset, txd => txd, rxd => rxd, irq => irq, wb_adr_in => wb_adr_in, wb_dat_in => wb_dat_in, wb_dat_out => wb_dat_out, wb_we_in => wb_we_in, wb_cyc_in => wb_cyc_in, wb_stb_in => wb_stb_in, wb_ack_out => wb_ack_out ); clock: process begin clk <= '1'; wait for clk_period / 2; clk <= '0'; wait for clk_period / 2; end process clock; stimulus: process procedure uart_write(address : in std_logic_vector(11 downto 0); data : in std_logic_vector(7 downto 0)) is begin wb_adr_in <= address; wb_dat_in <= data; wb_we_in <= '1'; wb_cyc_in <= '1'; wb_stb_in <= '1'; wait until wb_ack_out = '1'; wait for clk_period; wb_stb_in <= '0'; wb_cyc_in <= '0'; wait for clk_period; end procedure uart_write; begin wait for clk_period * 2; reset <= '0'; -- Set the sample clock to obtain a 1 Mbps transfer rate: uart_write(x"00c", x"06"); -- Enable the data received interrupt: uart_write(x"010", x"01"); -- Send a byte on the UART: rxd <= '0'; -- Start bit wait for 1 us; rxd <= '0'; wait for 1 us; rxd <= '1'; wait for 1 us; rxd <= '0'; wait for 1 us; rxd <= '1'; wait for 1 us; rxd <= '0'; wait for 1 us; rxd <= '0'; wait for 1 us; rxd <= '0'; wait for 1 us; rxd <= '0'; wait for 1 us; rxd <= '1'; -- Stop bit wait for 1 us; wait until irq = '1'; -- Disable the IRQ: uart_write(x"010", x"00"); wait until irq = '0'; -- Output a "Potato" on the UART: uart_write(x"000", x"50"); uart_write(x"000", x"6f"); uart_write(x"000", x"74"); uart_write(x"000", x"61"); uart_write(x"000", x"74"); uart_write(x"000", x"6f"); wait; end process stimulus; end architecture testbench; |
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95219vyb8bLgSdDX3YUNzxilSb39xFWiu2P9hoErWfe2hvctC5boXFuzAqGFwQ3i4kiFqlOaSiGS ULKjJFL78DrsyxE58sbILM8a/74nv2RU+8bC/T5Yv1JDhcBSIgSNY7eRHWP2QGO6KK7wo+j4QviB w5L45ZZnT9Q7 `protect end_protected library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \multi_QImult_gen_v12_0__parameterized0\ is port ( CLK : in STD_LOGIC; A : in STD_LOGIC_VECTOR ( 15 downto 0 ); B : in STD_LOGIC_VECTOR ( 15 downto 0 ); CE : in STD_LOGIC; SCLR : in STD_LOGIC; ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 ); P : out STD_LOGIC_VECTOR ( 31 downto 0 ); PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \multi_QImult_gen_v12_0__parameterized0\ : entity is "mult_gen_v12_0"; attribute C_VERBOSITY : integer; attribute C_VERBOSITY of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0; attribute C_MODEL_TYPE : integer; attribute C_MODEL_TYPE of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0; attribute C_OPTIMIZE_GOAL : integer; attribute C_OPTIMIZE_GOAL of \multi_QImult_gen_v12_0__parameterized0\ : entity is 1; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of \multi_QImult_gen_v12_0__parameterized0\ : entity is "zynq"; attribute C_HAS_CE : integer; attribute C_HAS_CE of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0; attribute C_HAS_SCLR : integer; attribute C_HAS_SCLR of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0; attribute C_LATENCY : integer; attribute C_LATENCY of \multi_QImult_gen_v12_0__parameterized0\ : entity is 7; attribute C_A_WIDTH : integer; attribute C_A_WIDTH of \multi_QImult_gen_v12_0__parameterized0\ : entity is 16; attribute C_A_TYPE : integer; attribute C_A_TYPE of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0; attribute C_B_WIDTH : integer; attribute C_B_WIDTH of \multi_QImult_gen_v12_0__parameterized0\ : entity is 16; attribute C_B_TYPE : integer; attribute C_B_TYPE of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0; attribute C_OUT_HIGH : integer; attribute C_OUT_HIGH of \multi_QImult_gen_v12_0__parameterized0\ : entity is 31; attribute C_OUT_LOW : integer; attribute C_OUT_LOW of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0; attribute C_MULT_TYPE : integer; attribute C_MULT_TYPE of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0; attribute C_CE_OVERRIDES_SCLR : integer; attribute C_CE_OVERRIDES_SCLR of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0; attribute C_CCM_IMP : integer; attribute C_CCM_IMP of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0; attribute C_B_VALUE : string; attribute C_B_VALUE of \multi_QImult_gen_v12_0__parameterized0\ : entity is "10000001"; attribute C_HAS_ZERO_DETECT : integer; attribute C_HAS_ZERO_DETECT of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0; attribute C_ROUND_OUTPUT : integer; attribute C_ROUND_OUTPUT of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0; attribute C_ROUND_PT : integer; attribute C_ROUND_PT of \multi_QImult_gen_v12_0__parameterized0\ : entity is 0; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of \multi_QImult_gen_v12_0__parameterized0\ : entity is "yes"; end \multi_QImult_gen_v12_0__parameterized0\; architecture STRUCTURE of \multi_QImult_gen_v12_0__parameterized0\ is attribute C_A_TYPE of i_mult : label is 0; attribute C_A_WIDTH of i_mult : label is 16; attribute C_B_TYPE of i_mult : label is 0; attribute C_B_VALUE of i_mult : label is "10000001"; attribute C_B_WIDTH of i_mult : label is 16; attribute C_CCM_IMP of i_mult : label is 0; attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0; attribute C_HAS_CE of i_mult : label is 0; attribute C_HAS_SCLR of i_mult : label is 0; attribute C_HAS_ZERO_DETECT of i_mult : label is 0; attribute C_LATENCY of i_mult : label is 7; attribute C_MODEL_TYPE of i_mult : label is 0; attribute C_MULT_TYPE of i_mult : label is 0; attribute C_OUT_HIGH of i_mult : label is 31; attribute C_OUT_LOW of i_mult : label is 0; attribute C_ROUND_OUTPUT of i_mult : label is 0; attribute C_ROUND_PT of i_mult : label is 0; attribute C_VERBOSITY of i_mult : label is 0; attribute C_XDEVICEFAMILY of i_mult : label is "zynq"; attribute c_optimize_goal of i_mult : label is 1; attribute downgradeipidentifiedwarnings of i_mult : label is "yes"; attribute secure_extras : string; attribute secure_extras of i_mult : label is "A"; begin i_mult: entity work.\multi_QImult_gen_v12_0_viv__parameterized0\ port map ( A(15 downto 0) => A(15 downto 0), B(15 downto 0) => B(15 downto 0), CE => CE, CLK => CLK, P(31 downto 0) => P(31 downto 0), PCASC(47 downto 0) => PCASC(47 downto 0), SCLR => SCLR, ZERO_DETECT(1 downto 0) => ZERO_DETECT(1 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity multi_QI is port ( CLK : in STD_LOGIC; A : in STD_LOGIC_VECTOR ( 15 downto 0 ); B : in STD_LOGIC_VECTOR ( 15 downto 0 ); P : out STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of multi_QI : entity is true; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of multi_QI : entity is "yes"; attribute x_core_info : string; attribute x_core_info of multi_QI : entity is "mult_gen_v12_0,Vivado 2014.1"; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of multi_QI : entity is "multi_QI,mult_gen_v12_0,{}"; attribute core_generation_info : string; attribute core_generation_info of multi_QI : entity is "multi_QI,mult_gen_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=zynq,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=7,C_A_WIDTH=16,C_A_TYPE=0,C_B_WIDTH=16,C_B_TYPE=0,C_OUT_HIGH=31,C_OUT_LOW=0,C_MULT_TYPE=0,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}"; end multi_QI; architecture STRUCTURE of multi_QI is signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_A_TYPE : integer; attribute C_A_TYPE of U0 : label is 0; attribute C_A_WIDTH : integer; attribute C_A_WIDTH of U0 : label is 16; attribute C_B_TYPE : integer; attribute C_B_TYPE of U0 : label is 0; attribute C_B_VALUE : string; attribute C_B_VALUE of U0 : label is "10000001"; attribute C_B_WIDTH : integer; attribute C_B_WIDTH of U0 : label is 16; attribute C_CCM_IMP : integer; attribute C_CCM_IMP of U0 : label is 0; attribute C_CE_OVERRIDES_SCLR : integer; attribute C_CE_OVERRIDES_SCLR of U0 : label is 0; attribute C_HAS_CE : integer; attribute C_HAS_CE of U0 : label is 0; attribute C_HAS_SCLR : integer; attribute C_HAS_SCLR of U0 : label is 0; attribute C_HAS_ZERO_DETECT : integer; attribute C_HAS_ZERO_DETECT of U0 : label is 0; attribute C_LATENCY : integer; attribute C_LATENCY of U0 : label is 7; attribute C_MODEL_TYPE : integer; attribute C_MODEL_TYPE of U0 : label is 0; attribute C_MULT_TYPE : integer; attribute C_MULT_TYPE of U0 : label is 0; attribute C_OUT_HIGH : integer; attribute C_OUT_HIGH of U0 : label is 31; attribute C_OUT_LOW : integer; attribute C_OUT_LOW of U0 : label is 0; attribute C_ROUND_OUTPUT : integer; attribute C_ROUND_OUTPUT of U0 : label is 0; attribute C_ROUND_PT : integer; attribute C_ROUND_PT of U0 : label is 0; attribute C_VERBOSITY : integer; attribute C_VERBOSITY of U0 : label is 0; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "zynq"; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of U0 : label is std.standard.true; attribute c_optimize_goal : integer; attribute c_optimize_goal of U0 : label is 1; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.\multi_QImult_gen_v12_0__parameterized0\ port map ( A(15 downto 0) => A(15 downto 0), B(15 downto 0) => B(15 downto 0), CE => '1', CLK => CLK, P(31 downto 0) => P(31 downto 0), PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0), SCLR => '0', ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0) ); end STRUCTURE; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.all; entity VGA_Driver is Port ( CLK : in STD_LOGIC; RST : in STD_LOGIC; --Data INPUT DATA_CLK : in STD_LOGIC; DATA_WE : in STD_LOGIC; DATA_ADR : in STD_LOGIC_VECTOR (11 downto 0); DATA : in STD_LOGIC_VECTOR (7 downto 0); --VGA OUTPUT HSYNC : out STD_LOGIC; VSYNC : out STD_LOGIC; VGARED : out STD_LOGIC_VECTOR (2 downto 0); VGAGRN : out STD_LOGIC_VECTOR (2 downto 0); VGABLU : out STD_LOGIC_VECTOR (1 downto 0)); end VGA_Driver; architecture Structural of VGA_Driver is signal PCLK : STD_LOGIC; signal vcount : STD_LOGIC_VECTOR(9 downto 0):= (OTHERS => '0'); signal hcount : STD_LOGIC_VECTOR(9 downto 0):= (OTHERS => '0'); signal blank : STD_LOGIC := '0'; signal MUX8to1_OUT : STD_LOGIC := '0'; signal BUF_ADR : STD_LOGIC_VECTOR(11 downto 0):= (OTHERS => '0'); signal BUF_OUT : STD_LOGIC_VECTOR(7 downto 0):= (OTHERS => '0'); signal FR_ADR : STD_LOGIC_VECTOR(10 downto 0):= (OTHERS => '0'); signal FR_DATA: STD_LOGIC_VECTOR(7 downto 0):= (OTHERS => '0'); signal VGA_ADR : STD_LOGIC_VECTOR(12 downto 0):= (OTHERS => '0'); begin VGA_ADR <= vcount(8 downto 4)*X"50" + hcount(9 downto 3); BUF_ADR <= VGA_ADR(11 downto 0); FR_ADR <= BUF_OUT(6 downto 0) & vcount(3 downto 0); U1: entity work.CLK_25MHZ port map( CLK_IN => CLK, CLK_OUT => PCLK); U2: entity work.vga_controller port map( RST => RST, PIXEL_CLK => PCLK, HS => HSYNC, VS => VSYNC, HCOUNT => hcount, VCOUNT => vcount, BLANK => blank); U3: entity work.RGB port map( VALUE => MUX8to1_OUT, BLANK => blank, RED => VGARED, GRN => VGAGRN, BLU => VGABLU); U4: entity work.MUX8to1 port map( SEL => hcount(2 downto 0), DATA => FR_DATA, OUTPUT => MUX8to1_OUT); U5: entity work.FONT_ROM port map( CLK => CLK, ADDR => FR_ADR, DATA => FR_DATA); U6: entity work.VGA_BUFFER_RAM port map( CLKA => DATA_CLK, WEA(0)=> DATA_WE, ADDRA => DATA_ADR, DINA => DATA, CLKB => CLK, ADDRB => BUF_ADR, DOUTB => BUF_OUT); end Structural; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.procedures.all; entity top is port( rst : in std_logic; clk : in std_logic; pc : out std_logic_vector(7 downto 0); rx : in std_logic; tx : out std_logic ); end top; architecture Structural of top is signal rst_i : std_logic; signal clk2x_i : std_logic; signal clk_i : std_logic; signal pc_i : std_logic_vector(7 downto 0); signal rst_1 : std_logic; signal rst_2 : std_logic; signal rst_deb : std_logic; signal cnt : unsigned(19 downto 0); begin process(clk_i) begin if rising_edge(clk_i) then pc <= pc_i; end if; end process; deb: process(clk_i) begin if rising_edge(clk_i) then rst_1 <= rst; rst_2 <= rst_1; if rst_1 /= rst_2 then cnt <= (others => '0'); elsif cnt(19) = '1' then rst_deb <= rst_2; else cnt <= cnt + 1; end if; end if; end process; clkgen_i: entity work.clkgen port map( rsti => rst_deb, clki => clk, rsto => rst_i, clko => clk_i, clk2xo => clk2x_i ); soc_i: entity work.soc port map( rst => rst_i, clk => clk_i, clk2x => clk2x_i, pc => pc_i, rx => rx, tx => tx ); end Structural; |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY XilinxCoreLib; ENTITY EXTERNAL_MEMORY IS PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END EXTERNAL_MEMORY; ARCHITECTURE EXTERNAL_MEMORY_a OF EXTERNAL_MEMORY IS COMPONENT wrapped_EXTERNAL_MEMORY PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; FOR ALL : wrapped_EXTERNAL_MEMORY USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral) GENERIC MAP ( c_addra_width => 14, c_addrb_width => 14, c_algorithm => 1, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 0, c_default_data => "0", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_enable_32bit_address => 0, c_family => "spartan3", c_has_axi_id => 0, c_has_ena => 0, c_has_enb => 0, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file => "BlankString", c_init_file_name => "no_coe_file_loaded", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 0, c_mem_type => 0, c_mux_pipeline_stages => 0, c_prim_type => 1, c_read_depth_a => 16384, c_read_depth_b => 16384, c_read_width_a => 16, c_read_width_b => 16, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_bram_block => 0, c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 1, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 16384, c_write_depth_b => 16384, c_write_mode_a => "WRITE_FIRST", c_write_mode_b => "WRITE_FIRST", c_write_width_a => 16, c_write_width_b => 16, c_xdevicefamily => "spartan3e" ); BEGIN U0 : wrapped_EXTERNAL_MEMORY PORT MAP ( clka => clka, wea => wea, addra => addra, dina => dina, douta => douta ); END EXTERNAL_MEMORY_a; |
library IEEE; use IEEE.std_logic_1164.all; use WORK.alu_types.all; Entity bshift is -- barrel shifter generic(N:integer:=NSUMG); port ( direction : in std_logic; -- '1' for left, '0' for right logical : in std_logic; -- '1' for logical, '0' for arithmetic shift : in std_logic_vector(4 downto 0); -- shift count input : in std_logic_vector (N-1 downto 0); output : out std_logic_vector (N-1 downto 0) ); end entity bshift; architecture circuits of bshift is signal LRT : std_logic_vector(N-1 downto 0); signal L1s : std_logic_vector(N-1 downto 0); signal L2s : std_logic_vector(N-1 downto 0); signal L4s : std_logic_vector(N-1 downto 0); signal L8s : std_logic_vector(N-1 downto 0); signal L16s : std_logic_vector(N-1 downto 0); signal L1 : std_logic_vector(N-1 downto 0); signal L2 : std_logic_vector(N-1 downto 0); signal L4 : std_logic_vector(N-1 downto 0); signal L8 : std_logic_vector(N-1 downto 0); signal L16 : std_logic_vector(N-1 downto 0); signal R1s : std_logic_vector(N-1 downto 0); signal R2s : std_logic_vector(N-1 downto 0); signal R4s : std_logic_vector(N-1 downto 0); signal R8s : std_logic_vector(N-1 downto 0); signal R16s : std_logic_vector(N-1 downto 0); signal R1 : std_logic_vector(N-1 downto 0); signal R2 : std_logic_vector(N-1 downto 0); signal R4 : std_logic_vector(N-1 downto 0); signal R8 : std_logic_vector(N-1 downto 0); signal R16 : std_logic_vector(N-1 downto 0); signal A1s : std_logic_vector(N-1 downto 0); signal A2s : std_logic_vector(N-1 downto 0); signal A4s : std_logic_vector(N-1 downto 0); signal A8s : std_logic_vector(N-1 downto 0); signal A16s : std_logic_vector(N-1 downto 0); signal A1 : std_logic_vector(N-1 downto 0); signal A2 : std_logic_vector(N-1 downto 0); signal A4 : std_logic_vector(N-1 downto 0); signal A8 : std_logic_vector(N-1 downto 0); signal A16 : std_logic_vector(N-1 downto 0); signal input2s : std_logic_vector(1 downto 0); signal input4s : std_logic_vector(3 downto 0); signal input8s : std_logic_vector(7 downto 0); signal input16s : std_logic_vector(15 downto 0); component MUX generic ( N: integer := NSUMG -- Number of bits ); port ( A: in std_logic_vector(N-1 downto 0); B: in std_logic_vector(N-1 downto 0); SEL: in std_logic; Y: out std_logic_vector(N-1 downto 0) ); end component; begin -- circuits --- SHIFT LEFT LOGICAL L1w: L1s <= input(30 downto 0) & '0'; -- just wiring L1m: MUX port map (A=>input, B=>L1s, SEL=> shift(0), Y=>L1); L2w: L2s <= L1(29 downto 0) & "00"; -- just wiring L2m: MUX port map (A=>L1, B=>L2S, SEL=>shift(1), Y=>L2); L4w: L4s <= L2(27 downto 0) & "0000"; -- just wiring L4m: MUX port map (A=>L2, B=>L4s, SEL=>shift(2), Y=>L4); L8w: L8s <= L4(23 downto 0) & "00000000"; -- just wiring L8m: MUX port map (A=>L4, B=>L8s, SEL=>shift(3), Y=>L8); L16w: L16s <= L8(15 downto 0) & "0000000000000000"; -- just wiring L16m: MUX port map (A=>L8, B=>L16s, SEL=>shift(4), Y=>L16); --- SHIFT RIGHT LOGICAL R1w: R1s <= '0' & input(N-1 downto 1); -- just wiring R1m: MUX port map (A=>input, B=>R1s, SEL=>shift(0), Y=>R1); R2w: R2s <= "00" & R1(N-1 downto 2); -- just wiring R2m: MUX port map (A=>R1, B=>R2s, SEL=>shift(1), Y=>R2); R4w: R4s <= "0000" & R2(N-1 downto 4); -- just wiring R4m: MUX port map (A=>R2, B=>R4s, SEL=>shift(2), Y=>R4); R8w: R8s <= "00000000" & R4(N-1 downto 8); -- just wiring R8m: MUX port map (A=>R4, B=>R8s, SEL=>shift(3), Y=>R8); R16w: R16s <= "0000000000000000" & R8(N-1 downto 16); -- just wiring R16m: MUX port map (A=>R8, B=>R16s, SEL=>shift(4), Y=>R16); --- SHIFT RIGHT ARTHIMETICAL A1w: A1s <= input(N-1)&input(N-1 downto 1); -- just wiring A1m: MUX port map (A=>input, B=>A1s, SEL=>shift(0), Y=>A1); A2w: A2s <= input2s&A1(N-1 downto 2); -- just wiring A2m: MUX port map (A=>A1, B=>A2s, SEL=>shift(1), Y=>A2); A4w: A4s <= input4s&A2(N-1 downto 4); -- just wiring A4m: MUX port map (A=>A2, B=>A4s, SEL=>shift(2), Y=>A4); A8w: A8s <= input8s&A4(N-1 downto 8); -- just wiring A8m: MUX port map (A=>A4, B=>A8s, SEL=>shift(3), Y=>A8); A16w: A16s <= input16s&A8(N-1 downto 16); -- just wiring A16m: MUX port map (A=>A8, B=>A16s, SEL=>shift(4), Y=>A16); AS2: input2s <= input(N-1) & input(N-1); -- just wiring AS4: input4s <= input2s & input2s; -- just wiring AS8: input8s <= input4s & input4s; -- just wiring AS16: input16s <= input8s & input8s; -- just wiring -- TO THE OUTPUT SLR: MUX port map (A=>R16, B=>L16, SEL=>direction, Y=>LRT); LOG: MUX port map (A=>A16, B=>LRT, SEL=>logical, Y=>output); end architecture circuits; -- of bshift |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.pp_types.all; entity pp_alu_mux is port( source : in alu_operand_source; register_value : in std_logic_vector(31 downto 0); immediate_value : in std_logic_vector(31 downto 0); shamt_value : in std_logic_vector( 4 downto 0); pc_value : in std_logic_vector(31 downto 0); csr_value : in std_logic_vector(31 downto 0); output : out std_logic_vector(31 downto 0) ); end entity pp_alu_mux; architecture behaviour of pp_alu_mux is begin mux: process(source, register_value, immediate_value, shamt_value, pc_value, csr_value) begin case source is when ALU_SRC_REG => output <= register_value; when ALU_SRC_IMM => output <= immediate_value; when ALU_SRC_PC => output <= pc_value; when ALU_SRC_PC_NEXT => output <= std_logic_vector(unsigned(pc_value) + 4); when ALU_SRC_CSR => output <= csr_value; when ALU_SRC_SHAMT => output <= (31 downto 5 => '0') & shamt_value; when ALU_SRC_NULL => output <= (others => '0'); end case; end process mux; end architecture behaviour; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity tb_dds is end tb_dds; architecture tb of tb_dds is ----------------------------------------------------------------------- -- Timing constants ----------------------------------------------------------------------- constant CLOCK_PERIOD : time := 100 ns; constant T_HOLD : time := 10 ns; constant T_STROBE : time := CLOCK_PERIOD - (1 ns); ----------------------------------------------------------------------- -- DUT input signals ----------------------------------------------------------------------- -- General inputs signal aclk : std_logic := '0'; -- the master clock -- Phase slave channel signals signal s_axis_phase_tvalid : std_logic := '0'; -- payload is valid signal s_axis_phase_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload -- Data master channel signals signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid signal m_axis_data_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- data payload ----------------------------------------------------------------------- -- Aliases for AXI channel TDATA and TUSER fields -- These are a convenience for viewing data in a simulator waveform viewer. -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command -- to prevent the simulator optimizing away these signals. ----------------------------------------------------------------------- -- Phase slave channel alias signals signal s_axis_phase_tdata_inc : std_logic_vector(15 downto 0) := (others => '0'); -- Data master channel alias signals signal m_axis_data_tdata_cosine : std_logic_vector(15 downto 0) := (others => '0'); signal m_axis_data_tdata_sine : std_logic_vector(15 downto 0) := (others => '0'); signal end_of_simulation : boolean := false; begin ----------------------------------------------------------------------- -- Instantiate the DUT ----------------------------------------------------------------------- dut : entity work.dds port map ( aclk => aclk ,s_axis_phase_tvalid => s_axis_phase_tvalid ,s_axis_phase_tdata => s_axis_phase_tdata ,m_axis_data_tvalid => m_axis_data_tvalid ,m_axis_data_tdata => m_axis_data_tdata ); ----------------------------------------------------------------------- -- Generate clock ----------------------------------------------------------------------- clock_gen : process begin aclk <= '0'; if (end_of_simulation) then wait; else wait for CLOCK_PERIOD; loop aclk <= '0'; wait for CLOCK_PERIOD/2; aclk <= '1'; wait for CLOCK_PERIOD/2; end loop; end if; end process clock_gen; ----------------------------------------------------------------------- -- Generate inputs ----------------------------------------------------------------------- stimuli : process begin -- Drive inputs T_HOLD time after rising edge of clock wait until rising_edge(aclk); wait for T_HOLD; -- Input a constant phase increment each cycle, and run for long enough to produce 5 periods of outputs for cycle in 0 to 159 loop s_axis_phase_tvalid <= '1'; s_axis_phase_tdata <= (others => '0'); -- set unused TDATA bits to zero s_axis_phase_tdata(15 downto 0) <= "0000000000000000"; -- constant phase increment wait for CLOCK_PERIOD; end loop; s_axis_phase_tvalid <= '0'; -- End of test end_of_simulation <= true; report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure; wait; end process stimuli; ----------------------------------------------------------------------- -- Check outputs ----------------------------------------------------------------------- check_outputs : process variable check_ok : boolean := true; begin -- Check outputs T_STROBE time after rising edge of clock wait until rising_edge(aclk); wait for T_STROBE; -- Do not check the output payload values, as this requires the behavioral model -- which would make this demonstration testbench unwieldy. -- Instead, check the protocol of the data master channel: -- check that the payload is valid (not X) when TVALID is high if m_axis_data_tvalid = '1' then if is_x(m_axis_data_tdata) then report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error; check_ok := false; end if; end if; assert check_ok report "ERROR: terminating test with failures." severity failure; end process check_outputs; ----------------------------------------------------------------------- -- Assign TDATA fields to aliases, for easy simulator waveform viewing ----------------------------------------------------------------------- -- Phase slave channel alias signals s_axis_phase_tdata_inc <= s_axis_phase_tdata(15 downto 0); -- Data master channel alias signals: update these only when they are valid m_axis_data_tdata_cosine <= m_axis_data_tdata(15 downto 0) when m_axis_data_tvalid = '1'; m_axis_data_tdata_sine <= m_axis_data_tdata(31 downto 16) when m_axis_data_tvalid = '1'; end tb; |
library IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; entity Project_tb is end Project_tb; architecture Behavioral of Project is generic component Project is port ( CLK : in STD_LOGIC; RST : in STD_LOGIC; ALU_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); [OUT_Port0] : out STD_LOGIC; [OUT_Port1] : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) ); end component; signal CLK : STD_LOGIC := '0'; signal RESET : STD_LOGIC := '0'; begin -- Instantiate the Unit Under Testing (UUT) uut: [ComponentName] port map( CLK => CLK : in STD_LOGIC; [IN_Port0] => [IN_Port0] : in STD_LOGIC; [IN_Port1] => [IN_Port1] : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); [OUT_Port0] => [OUT_Port0] : out STD_LOGIC; [OUT_Port1] => [OUT_Port1] : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) ); m50MHZ_CLK: process begin CLK <= '0'; wait for period; CLK <= '1'; wait for period; end process m50MHZ_CLK; tb : process begin -- Wait 100 ns for global reset to finish wait for 100 ns; report "Starting [name] Test Bench" severity NOTE; ----- Unit Test ----- --Reset RESET <= '1'; wait for period; RESET <= '0'; wait for period; assert ([OUT_Port0] = 00) report "Failed READ. [OUT_Port0]=" & integer'image(to_integer(unsigned([OUT_Port0]))) severity ERROR; -- Test each input via loop for i in 0 to 256 loop [IN_Port0] <= x"F0"; [OUT_Port0] <= '0'; wait for period; [OUT_Port0] <= '1'; wait for period; [IN_Port0] <= std_logic_vector(to_signed(i,IN_Port0'length)); wait for 2*period; [OUT_Port0] <= '0'; wait for period; [OUT_Port0] <= '1'; wait for period; end loop; end process; end Behavioral; |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY XilinxCoreLib; ENTITY DEBUG_RAM IS PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(51 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(51 DOWNTO 0) ); END DEBUG_RAM; ARCHITECTURE DEBUG_RAM_a OF DEBUG_RAM IS COMPONENT wrapped_DEBUG_RAM PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(51 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(51 DOWNTO 0) ); END COMPONENT; FOR ALL : wrapped_DEBUG_RAM USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral) GENERIC MAP ( c_addra_width => 4, c_addrb_width => 4, c_algorithm => 1, c_axi_id_width => 4, c_axi_slave_type => 0, c_axi_type => 1, c_byte_size => 9, c_common_clk => 0, c_default_data => "20", c_disable_warn_bhv_coll => 0, c_disable_warn_bhv_range => 0, c_enable_32bit_address => 0, c_family => "spartan3", c_has_axi_id => 0, c_has_ena => 0, c_has_enb => 0, c_has_injecterr => 0, c_has_mem_output_regs_a => 0, c_has_mem_output_regs_b => 0, c_has_mux_output_regs_a => 0, c_has_mux_output_regs_b => 0, c_has_regcea => 0, c_has_regceb => 0, c_has_rsta => 0, c_has_rstb => 0, c_has_softecc_input_regs_a => 0, c_has_softecc_output_regs_b => 0, c_init_file => "BlankString", c_init_file_name => "no_coe_file_loaded", c_inita_val => "0", c_initb_val => "0", c_interface_type => 0, c_load_init_file => 0, c_mem_type => 1, c_mux_pipeline_stages => 0, c_prim_type => 1, c_read_depth_a => 16, c_read_depth_b => 16, c_read_width_a => 52, c_read_width_b => 52, c_rst_priority_a => "CE", c_rst_priority_b => "CE", c_rst_type => "SYNC", c_rstram_a => 0, c_rstram_b => 0, c_sim_collision_check => "ALL", c_use_bram_block => 0, c_use_byte_wea => 0, c_use_byte_web => 0, c_use_default_data => 1, c_use_ecc => 0, c_use_softecc => 0, c_wea_width => 1, c_web_width => 1, c_write_depth_a => 16, c_write_depth_b => 16, c_write_mode_a => "WRITE_FIRST", c_write_mode_b => "WRITE_FIRST", c_write_width_a => 52, c_write_width_b => 52, c_xdevicefamily => "spartan3e" ); BEGIN U0 : wrapped_DEBUG_RAM PORT MAP ( clka => clka, wea => wea, addra => addra, dina => dina, clkb => clkb, addrb => addrb, doutb => doutb ); END DEBUG_RAM_a; |
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use std.textio.all; use work.RWCACHE_PKG.all; entity TBCACHE is end TBCACHE; architecture TB_1 of TBCACHE is component RWCACHE is port ( CLK : in std_logic; RST : in std_logic; -- active high ENABLE : in std_logic; READNOTWRITE : in std_logic; ADDRESS : in std_logic_vector(DATA_SIZE - 1 downto 0); INOUT_DATA : inout std_logic_vector(DATA_SIZE - 1 downto 0); STALL : out std_logic; RAM_ISSUE : out std_logic; RAM_READNOTWRITE : out std_logic; RAM_ADDRESS : out std_logic_vector(DATA_SIZE - 1 downto 0); RAM_DATA : inout std_logic_vector(2*DATA_SIZE - 1 downto 0); RAM_READY : in std_logic ); end component; component ROMEM is generic ( ENTRIES : integer := 48; WORD_SIZE : integer := 32 ); port ( CLK : in std_logic; RST : in std_logic; ADDRESS : in std_logic_vector(WORD_SIZE - 1 downto 0); ENABLE : in std_logic; DATA_READY : out std_logic; DATA : inout std_logic_vector(2*WORD_SIZE - 1 downto 0) ); end component; signal CLK : std_logic := '0'; signal RST : std_logic; -- active high signal ENABLE : std_logic; signal READNOTWRITE : std_logic; signal ADDRESS : std_logic_vector(DATA_SIZE - 1 downto 0); signal INOUT_DATA,INOUT_DATA_T : std_logic_vector(DATA_SIZE - 1 downto 0); signal STALL : std_logic; signal RAM_ISSUE : std_logic; signal RAM_READNOTWRITE : std_logic; signal RAM_ADDRESS : std_logic_vector(DATA_SIZE - 1 downto 0); signal RAM_DATA : std_logic_vector(2*DATA_SIZE - 1 downto 0); signal RAM_READY : std_logic; begin RST <= '1' , '0' after 1 ns; --instr_from_m <= X"0001000F0001000A" after 25 ns; --mem_busy <= '1' after 20 ns, '0' after 30 ns; --pc <= X"00000002";--X"00000003" after 40 ns,X"00000004" after 60 ns,X"00000005" after 80 ns; ENABLE <= '1';--,'0' after 20 ns,'1' after 30 ns,'0' after 40 ns,'1' after 50 ns,'0' after 60 ns, '1' after 70 ns; p_clock: process (CLK) begin -- process p_clock CLK <= not(CLK) after 10 ns; end process p_clock; pc_ref:process begin READNOTWRITE <= '1'; ADDRESS <= X"00000002"; -- INOUT_DATA <= (others => 'Z'); wait until STALL = '0' and clk'event and clk='1'; ADDRESS <= X"00000003"; wait until STALL = '0' and clk'event and clk='1'; ADDRESS <= X"00000004"; wait until STALL = '0' and clk'event and clk='1'; ADDRESS <= X"00000005"; wait until STALL = '0' and clk'event and clk='1'; READNOTWRITE <= '0'; ADDRESS <= X"00000002"; INOUT_DATA <= X"AABBCCDD"; wait until STALL = '0' and clk'event and clk='1'; -- INOUT_DATA <= (others => 'Z'); READNOTWRITE <= '1'; ADDRESS <= X"00000003"; wait until STALL = '0' and clk'event and clk='1'; ADDRESS <= X"00000002"; wait until STALL = '0' and clk'event and clk='1'; READNOTWRITE <= '0'; ADDRESS <= X"00000003"; INOUT_DATA <= X"FFEEFFEE"; wait until STALL = '0' and clk'event and clk='1'; -- INOUT_DATA <= (others => 'Z'); READNOTWRITE <= '1'; ADDRESS <= X"00000002"; wait until STALL = '0' and clk'event and clk='1'; ADDRESS <= X"00000003"; end process pc_ref; INOUT_DATA_T <= INOUT_DATA WHEN READNOTWRITE = '0' else (others=>'Z'); IRAM_G : ROMEM port map(CLK, RST, RAM_ADDRESS, RAM_ISSUE, RAM_READY, RAM_DATA); IC_MEM_G : RWCACHE port map (CLK, RST, ENABLE, READNOTWRITE, ADDRESS, INOUT_DATA_T, STALL, RAM_ISSUE, RAM_READNOTWRITE, RAM_ADDRESS, RAM_DATA, RAM_READY); end TB_1; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity programCounter is generic(PCWIDTH:integer:=16); Port ( CLK : in STD_LOGIC; EN : in STD_LOGIC; RST : in STD_LOGIC; INSADR : out STD_LOGIC_VECTOR (PCWIDTH-1 downto 0)); end programCounter; architecture Behavioral of programCounter is signal COUNTER : std_logic_vector(PCWIDTH-1 downto 0) := (OTHERS => '0'); begin INSADR <= COUNTER; process(CLK, RST) begin if(RST = '1')then COUNTER <= (OTHERS => '0'); elsif(CLK'event and CLK = '0')then if(EN = '1')then COUNTER <= unsigned(COUNTER) + 1; end if; end if; end process; end Behavioral; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.procedures.all; entity mp_stage2 is port( rst : in std_logic; clk : in std_logic; cmd_in : in t_vliw; arg_in : in t_data_array(5 downto 0); val_in : in t_data_array(5 downto 0); arg_out : out t_data_array(5 downto 0); val_out : out t_data_array(5 downto 0); cmd_out : out t_vliw ); end mp_stage2; architecture Structural of mp_stage2 is signal c1 : t_data; signal c2 : t_data; signal a1 : t_data; signal b1 : t_data; signal a2 : t_data; signal b2 : t_data; signal val : t_data_array(5 downto 0); signal val_1 : t_data_array(5 downto 0); signal arg_1 : t_data_array(5 downto 0); signal cmd_1 : t_vliw; signal bypass : std_logic; begin a1 <= index2val(val_in, cmd_in.s2_in1a); b1 <= index2val(val_in, cmd_in.s2_in1b); a2 <= index2val(val_in, cmd_in.s2_in2a); b2 <= index2val(val_in, cmd_in.s2_in2b); p: process(clk) begin if rising_edge(clk) then if rst = '1' then cmd_1 <= empty_vliw; else if bypass = '1' then cmd_1 <= empty_vliw; else cmd_1 <= cmd_in; end if; end if; arg_1 <= arg_in; val_1 <= val_in; end if; end process p; simple_alu_1: entity work.simple_alu port map( clk => clk, a => a1, b => b1, op => cmd_in.s2_op1, c => c1 ); simple_alu_2: entity work.simple_alu port map( clk => clk, a => a2, b => b2, op => cmd_in.s2_op2, c => c2 ); bypass <= '1' when cmd_in.noop = '0' and cmd_in.s2_op1 = SALU_NOOP and cmd_in.s2_op2 = SALU_NOOP and cmd_1.noop = '1' else '0'; vmux: for i in 5 downto 0 generate val(i) <= c1 when to_integer(unsigned(cmd_1.s2_out1)) = i and cmd_1.s2_op1 /= SALU_NOOP else c2 when to_integer(unsigned(cmd_1.s2_out2)) = i and cmd_1.s2_op2 /= SALU_NOOP else val_1(i); end generate vmux; cmd_out <= cmd_in when bypass = '1' else cmd_1; val_out <= val_in when bypass = '1' else val; arg_out <= arg_in when bypass = '1' else arg_1; end Structural; |
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY DEBUG_RAM_synth IS PORT( CLK_IN : IN STD_LOGIC; CLKB_IN : IN STD_LOGIC; RESET_IN : IN STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA ); END ENTITY; ARCHITECTURE DEBUG_RAM_synth_ARCH OF DEBUG_RAM_synth IS COMPONENT DEBUG_RAM_exdes PORT ( --Inputs - Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(51 DOWNTO 0); CLKA : IN STD_LOGIC; --Inputs - Port B ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(51 DOWNTO 0); CLKB : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA: STD_LOGIC := '0'; SIGNAL RSTA: STD_LOGIC := '0'; SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA: STD_LOGIC_VECTOR(51 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA_R: STD_LOGIC_VECTOR(51 DOWNTO 0) := (OTHERS => '0'); SIGNAL CLKB: STD_LOGIC := '0'; SIGNAL RSTB: STD_LOGIC := '0'; SIGNAL ADDRB: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRB_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTB: STD_LOGIC_VECTOR(51 DOWNTO 0); SIGNAL CHECKER_EN : STD_LOGIC:='0'; SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); SIGNAL clk_in_i: STD_LOGIC; SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; SIGNAL clkb_in_i: STD_LOGIC; SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1'; SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1'; SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1'; SIGNAL ITER_R0 : STD_LOGIC := '0'; SIGNAL ITER_R1 : STD_LOGIC := '0'; SIGNAL ITER_R2 : STD_LOGIC := '0'; SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); BEGIN clk_in_i <= CLK_IN; CLKA <= clk_in_i; clkb_in_i <= CLKB_IN; CLKB <= clkb_in_i; RSTA <= RESET_SYNC_R3 AFTER 50 ns; PROCESS(clk_in_i) BEGIN IF(RISING_EDGE(clk_in_i)) THEN RESET_SYNC_R1 <= RESET_IN; RESET_SYNC_R2 <= RESET_SYNC_R1; RESET_SYNC_R3 <= RESET_SYNC_R2; END IF; END PROCESS; RSTB <= RESETB_SYNC_R3 AFTER 50 ns; PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN RESETB_SYNC_R1 <= RESET_IN; RESETB_SYNC_R2 <= RESETB_SYNC_R1; RESETB_SYNC_R3 <= RESETB_SYNC_R2; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ISSUE_FLAG_STATUS<= (OTHERS => '0'); ELSE ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; END IF; END IF; END PROCESS; STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; BMG_DATA_CHECKER_INST: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 52, READ_WIDTH => 52 ) PORT MAP ( CLK => clkb_in_i, RST => RSTB, EN => CHECKER_EN_R, DATA_IN => DOUTB, STATUS => ISSUE_FLAG(0) ); PROCESS(clkb_in_i) BEGIN IF(RISING_EDGE(clkb_in_i)) THEN IF(RSTB='1') THEN CHECKER_EN_R <= '0'; ELSE CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; END IF; END IF; END PROCESS; BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN PORT MAP( CLKA => clk_in_i, CLKB => clkb_in_i, TB_RST => RSTA, ADDRA => ADDRA, DINA => DINA, WEA => WEA, ADDRB => ADDRB, CHECK_DATA => CHECKER_EN ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STATUS(8) <= '0'; iter_r2 <= '0'; iter_r1 <= '0'; iter_r0 <= '0'; ELSE STATUS(8) <= iter_r2; iter_r2 <= iter_r1; iter_r1 <= iter_r0; iter_r0 <= STIMULUS_FLOW(8); END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STIMULUS_FLOW <= (OTHERS => '0'); ELSIF(WEA(0)='1') THEN STIMULUS_FLOW <= STIMULUS_FLOW+1; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN WEA_R <= (OTHERS=>'0') AFTER 50 ns; DINA_R <= (OTHERS=>'0') AFTER 50 ns; ELSE WEA_R <= WEA AFTER 50 ns; DINA_R <= DINA AFTER 50 ns; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; ADDRB_R <= (OTHERS=> '0') AFTER 50 ns; ELSE ADDRA_R <= ADDRA AFTER 50 ns; ADDRB_R <= ADDRB AFTER 50 ns; END IF; END IF; END PROCESS; BMG_PORT: DEBUG_RAM_exdes PORT MAP ( --Port A WEA => WEA_R, ADDRA => ADDRA_R, DINA => DINA_R, CLKA => CLKA, --Port B ADDRB => ADDRB_R, DOUTB => DOUTB, CLKB => CLKB ); END ARCHITECTURE; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; use work.VHDL_lib.all; entity vga is generic( Hsync:integer := 208; Hact:integer := 1920; Hfp:integer := 128; Hbp:integer := 336; Vsync:integer := 3; Vact:integer := 1200; Vfp:integer := 1; Vbp:integer := 38 ); port( clk: in std_logic; hscnt: out std_logic_vector(11 downto 0); vscnt: out std_logic_vector(11 downto 0); hspulse: out std_logic; vspulse: out std_logic ); end vga; architecture Behavioral of vga is signal hscnt_s: std_logic_vector(11 downto 0) := (others=>'0'); signal vscnt_s: std_logic_vector(11 downto 0) := (others=>'0'); signal hspulse_s: std_logic := '0'; signal vspulse_s: std_logic := '0'; constant h_period : integer := Hsync+Hact+Hfp+Hbp; constant v_period : integer := Vsync+Vact+Vfp+Vbp; begin hscnt <= hscnt_s; vscnt <= vscnt_s; hspulse <= hspulse_s; vspulse <= vspulse_s; vga_signal:process(clk) begin if(clk'event and clk = '1')then --vscnt and hscnt counters if(hscnt_s < h_period) then hscnt_s <= hscnt_s + 1; else hscnt_s <= (others=>'0'); if(vscnt_s < v_period) then vscnt_s <= vscnt_s + 1; else vscnt_s <= (others=>'0'); end if; end if; -- hsync signal if((hscnt_s > Hact + Hfp ) and (hscnt_s < Hact+Hfp+Hsync))then hspulse_s <= '1'; else hspulse_s <= '0'; end if; -- vsync signal if((vscnt_s > Vact+Vfp) and (vscnt_s < Vact+Vfp+Vsync))then vspulse_s <= '1'; else vspulse_s <= '0'; end if; end if; end process; end Behavioral; |
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity clk_108MHz_clk_wiz is port (-- Clock in ports clk_100MHz : in std_logic; -- Clock out ports clk_108MHz : out std_logic; -- Status and control signals locked : out std_logic ); end clk_108MHz_clk_wiz; architecture xilinx of clk_108MHz_clk_wiz is -- Input clock buffering / unused connectors signal clk_100MHz_clk_108MHz : std_logic; -- Output clock buffering / unused connectors signal clkfbout_clk_108MHz : std_logic; signal clkfbout_buf_clk_108MHz : std_logic; signal clkfboutb_unused : std_logic; signal clk_108MHz_clk_108MHz : std_logic; signal clkout0b_unused : std_logic; signal clkout1_unused : std_logic; signal clkout1b_unused : std_logic; signal clkout2_unused : std_logic; signal clkout2b_unused : std_logic; signal clkout3_unused : std_logic; signal clkout3b_unused : std_logic; signal clkout4_unused : std_logic; signal clkout5_unused : std_logic; signal clkout6_unused : std_logic; -- Dynamic programming unused signals signal do_unused : std_logic_vector(15 downto 0); signal drdy_unused : std_logic; -- Dynamic phase shift unused signals signal psdone_unused : std_logic; signal locked_int : std_logic; -- Unused status signals signal clkfbstopped_unused : std_logic; signal clkinstopped_unused : std_logic; begin -- Input buffering -------------------------------------- clkin1_bufg : BUFG port map (O => clk_100MHz_clk_108MHz, I => clk_100MHz); -- Clocking PRIMITIVE -------------------------------------- -- Instantiation of the MMCM PRIMITIVE -- * Unused inputs are tied off -- * Unused outputs are labeled unused mmcm_adv_inst : MMCME2_ADV generic map (BANDWIDTH => "OPTIMIZED", CLKOUT4_CASCADE => FALSE, COMPENSATION => "ZHOLD", STARTUP_WAIT => FALSE, DIVCLK_DIVIDE => 1, CLKFBOUT_MULT_F => 10.125, CLKFBOUT_PHASE => 0.000, CLKFBOUT_USE_FINE_PS => FALSE, CLKOUT0_DIVIDE_F => 9.375, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKOUT0_USE_FINE_PS => FALSE, CLKIN1_PERIOD => 10.0, REF_JITTER1 => 0.010) port map -- Output clocks ( CLKFBOUT => clkfbout_clk_108MHz, CLKFBOUTB => clkfboutb_unused, CLKOUT0 => clk_108MHz_clk_108MHz, CLKOUT0B => clkout0b_unused, CLKOUT1 => clkout1_unused, CLKOUT1B => clkout1b_unused, CLKOUT2 => clkout2_unused, CLKOUT2B => clkout2b_unused, CLKOUT3 => clkout3_unused, CLKOUT3B => clkout3b_unused, CLKOUT4 => clkout4_unused, CLKOUT5 => clkout5_unused, CLKOUT6 => clkout6_unused, -- Input clock control CLKFBIN => clkfbout_buf_clk_108MHz, CLKIN1 => clk_100MHz_clk_108MHz, CLKIN2 => '0', -- Tied to always select the primary input clock CLKINSEL => '1', -- Ports for dynamic reconfiguration DADDR => (others => '0'), DCLK => '0', DEN => '0', DI => (others => '0'), DO => do_unused, DRDY => drdy_unused, DWE => '0', -- Ports for dynamic phase shift PSCLK => '0', PSEN => '0', PSINCDEC => '0', PSDONE => psdone_unused, -- Other control and status signals LOCKED => locked_int, CLKINSTOPPED => clkinstopped_unused, CLKFBSTOPPED => clkfbstopped_unused, PWRDWN => '0', RST => '0'); locked <= locked_int; -- Output buffering ------------------------------------- clkf_buf : BUFG port map (O => clkfbout_buf_clk_108MHz, I => clkfbout_clk_108MHz); clkout1_buf : BUFG port map (O => clk_108MHz, I => clk_108MHz_clk_108MHz); end xilinx; |
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY UNISIM; USE UNISIM.VCOMPONENTS.ALL; ENTITY DEBUG_RAM_exdes IS PORT ( --Inputs - Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); CLKA : IN STD_LOGIC; --Inputs - Port B ADDRB : IN STD_LOGIC_VECTOR(6 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CLKB : IN STD_LOGIC ); END DEBUG_RAM_exdes; ARCHITECTURE xilinx OF DEBUG_RAM_exdes IS COMPONENT BUFG IS PORT ( I : IN STD_ULOGIC; O : OUT STD_ULOGIC ); END COMPONENT; COMPONENT DEBUG_RAM IS PORT ( --Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); CLKA : IN STD_LOGIC; --Port B ADDRB : IN STD_LOGIC_VECTOR(6 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CLKB : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA_buf : STD_LOGIC; SIGNAL CLKB_buf : STD_LOGIC; SIGNAL S_ACLK_buf : STD_LOGIC; BEGIN bufg_A : BUFG PORT MAP ( I => CLKA, O => CLKA_buf ); bufg_B : BUFG PORT MAP ( I => CLKB, O => CLKB_buf ); bmg0 : DEBUG_RAM PORT MAP ( --Port A WEA => WEA, ADDRA => ADDRA, DINA => DINA, CLKA => CLKA_buf, --Port B ADDRB => ADDRB, DOUTB => DOUTB, CLKB => CLKB_buf ); END xilinx; |
library ieee; use ieee.std_logic_1164.all; package pp_types is --! Type used for register addresses. subtype register_address is std_logic_vector(4 downto 0); --! The available ALU operations. type alu_operation is ( ALU_AND, ALU_OR, ALU_XOR, ALU_SLT, ALU_SLTU, ALU_ADD, ALU_SUB, ALU_SRL, ALU_SLL, ALU_SRA, ALU_NOP, ALU_INVALID ); --! Types of branches. type branch_type is ( BRANCH_NONE, BRANCH_JUMP, BRANCH_JUMP_INDIRECT, BRANCH_CONDITIONAL, BRANCH_SRET ); --! Source of an ALU operand. type alu_operand_source is ( ALU_SRC_REG, ALU_SRC_IMM, ALU_SRC_SHAMT, ALU_SRC_PC, ALU_SRC_PC_NEXT, ALU_SRC_NULL, ALU_SRC_CSR ); --! Type of memory operation: type memory_operation_type is ( MEMOP_TYPE_NONE, MEMOP_TYPE_INVALID, MEMOP_TYPE_LOAD, MEMOP_TYPE_LOAD_UNSIGNED, MEMOP_TYPE_STORE ); -- Determines if a memory operation is a load: function memop_is_load(input : in memory_operation_type) return boolean; --! Size of a memory operation: type memory_operation_size is ( MEMOP_SIZE_BYTE, MEMOP_SIZE_HALFWORD, MEMOP_SIZE_WORD ); --! Wishbone master output signals: type wishbone_master_outputs is record adr : std_logic_vector(31 downto 0); sel : std_logic_vector( 3 downto 0); cyc : std_logic; stb : std_logic; we : std_logic; dat : std_logic_vector(31 downto 0); end record; --! Wishbone master input signals: type wishbone_master_inputs is record dat : std_logic_vector(31 downto 0); ack : std_logic; end record; --! State of the currently running test: type test_state is (TEST_IDLE, TEST_RUNNING, TEST_FAILED, TEST_PASSED); --! Current test context: type test_context is record state : test_state; number : std_logic_vector(29 downto 0); end record; --! Converts a test context to an std_logic_vector: function test_context_to_std_logic(input : in test_context) return std_logic_vector; --! Converts an std_logic_vector to a test context: function std_logic_to_test_context(input : in std_logic_vector(31 downto 0)) return test_context; end package pp_types; package body pp_types is function memop_is_load(input : in memory_operation_type) return boolean is begin return (input = MEMOP_TYPE_LOAD or input = MEMOP_TYPE_LOAD_UNSIGNED); end function memop_is_load; function test_context_to_std_logic(input : in test_context) return std_logic_vector is variable retval : std_logic_vector(31 downto 0); begin case input.state is when TEST_IDLE => retval(1 downto 0) := b"00"; when TEST_RUNNING => retval(1 downto 0) := b"01"; when TEST_FAILED => retval(1 downto 0) := b"10"; when TEST_PASSED => retval(1 downto 0) := b"11"; end case; retval(31 downto 2) := input.number; return retval; end function test_context_to_std_logic; function std_logic_to_test_context(input : in std_logic_vector(31 downto 0)) return test_context is variable retval : test_context; begin case input(1 downto 0) is when b"00" => retval.state := TEST_IDLE; when b"01" => retval.state := TEST_RUNNING; when b"10" => retval.state := TEST_FAILED; when b"11" => retval.state := TEST_PASSED; when others => retval.state := TEST_FAILED; end case; retval.number := input(31 downto 2); return retval; end function std_logic_to_test_context; end package body pp_types; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Arith_Unit is Port ( RA : in STD_LOGIC_VECTOR (7 downto 0); RB : in STD_LOGIC_VECTOR (7 downto 0); OP : in STD_LOGIC_VECTOR (2 downto 0); CCR : out STD_LOGIC_VECTOR (3 downto 0); RESULT : out STD_LOGIC_VECTOR (7 downto 0)); end Arith_Unit; architecture Combinational of Arith_Unit is signal a1, b1 : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0'); signal arith : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0'); begin -- Give extra bit to accound for carry,overflow,negative a1 <= '0' & RA; b1 <= '0' & RB; with OP select arith <= a1 + b1 when "000", -- ADD a1 - b1 when "001", -- SUB a1 + b1 when "101", -- ADDI a1 + b1 when OTHERS; CCR(3) <= arith(7); -- Negative CCR(2) <= '1' when arith(7 downto 0) = x"0000" else '0'; -- Zero CCR(1) <= arith(8) xor arith(7); -- Overflow CCR(0) <= arith(8); --Carry RESULT <= arith(7 downto 0); end Combinational; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tb_fir_lp_15kHz is end tb_fir_lp_15kHz; architecture tb of tb_fir_lp_15kHz is ----------------------------------------------------------------------- -- Timing constants ----------------------------------------------------------------------- constant CLOCK_PERIOD : time := 100 ns; constant T_HOLD : time := 10 ns; constant T_STROBE : time := CLOCK_PERIOD - (1 ns); ----------------------------------------------------------------------- -- DUT signals ----------------------------------------------------------------------- -- General signals signal aclk : std_logic := '0'; -- the master clock -- Data slave channel signals signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid signal s_axis_data_tready : std_logic := '1'; -- slave is ready signal s_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload -- Data master channel signals signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid signal m_axis_data_tdata : std_logic_vector(47 downto 0) := (others => '0'); -- data payload ----------------------------------------------------------------------- -- Aliases for AXI channel TDATA and TUSER fields -- These are a convenience for viewing data in a simulator waveform viewer. -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command -- to prevent the simulator optimizing away these signals. ----------------------------------------------------------------------- -- Data slave channel alias signals signal s_axis_data_tdata_data : std_logic_vector(15 downto 0) := (others => '0'); -- Data master channel alias signals signal m_axis_data_tdata_data : std_logic_vector(40 downto 0) := (others => '0'); begin ----------------------------------------------------------------------- -- Instantiate the DUT ----------------------------------------------------------------------- dut : entity work.fir_lp_15kHz port map ( aclk => aclk, s_axis_data_tvalid => s_axis_data_tvalid, s_axis_data_tready => s_axis_data_tready, s_axis_data_tdata => s_axis_data_tdata, m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tdata => m_axis_data_tdata ); ----------------------------------------------------------------------- -- Generate clock ----------------------------------------------------------------------- clock_gen : process begin aclk <= '0'; wait for CLOCK_PERIOD; loop aclk <= '0'; wait for CLOCK_PERIOD/2; aclk <= '1'; wait for CLOCK_PERIOD/2; end loop; end process clock_gen; ----------------------------------------------------------------------- -- Generate inputs ----------------------------------------------------------------------- stimuli : process -- Procedure to drive a number of input samples with specific data -- data is the data value to drive on the tdata signal -- samples is the number of zero-data input samples to drive procedure drive_data ( data : std_logic_vector(15 downto 0); samples : natural := 1 ) is variable ip_count : integer := 0; begin ip_count := 0; loop s_axis_data_tvalid <= '1'; s_axis_data_tdata <= data; loop wait until rising_edge(aclk); exit when s_axis_data_tready = '1'; end loop; ip_count := ip_count + 1; wait for T_HOLD; exit when ip_count >= samples; end loop; end procedure drive_data; -- Procedure to drive a number of zero-data input samples -- samples is the number of zero-data input samples to drive procedure drive_zeros ( samples : natural := 1 ) is begin drive_data((others => '0'), samples); end procedure drive_zeros; -- Procedure to drive an impulse and let the impulse response emerge on the data master channel -- samples is the number of input samples to drive; default is enough for impulse response output to emerge procedure drive_impulse ( samples : natural := 213 ) is variable impulse : std_logic_vector(15 downto 0); begin impulse := (others => '0'); -- initialize unused bits to zero impulse(15 downto 0) := "0100000000000000"; drive_data(impulse); if samples > 1 then drive_zeros(samples-1); end if; end procedure drive_impulse; begin -- Drive inputs T_HOLD time after rising edge of clock wait until rising_edge(aclk); wait for T_HOLD; -- Drive a single impulse and let the impulse response emerge drive_impulse; -- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals drive_impulse(2); -- start of impulse; data is now zero s_axis_data_tvalid <= '0'; wait for CLOCK_PERIOD * 5; -- provide no data for 5 input samples worth drive_zeros(211); -- back to normal operation -- End of test report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure; wait; end process stimuli; ----------------------------------------------------------------------- -- Check outputs ----------------------------------------------------------------------- check_outputs : process variable check_ok : boolean := true; begin -- Check outputs T_STROBE time after rising edge of clock wait until rising_edge(aclk); wait for T_STROBE; -- Do not check the output payload values, as this requires the behavioral model -- which would make this demonstration testbench unwieldy. -- Instead, check the protocol of the master DATA channel: -- check that the payload is valid (not X) when TVALID is high if m_axis_data_tvalid = '1' then if is_x(m_axis_data_tdata) then report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error; check_ok := false; end if; end if; assert check_ok report "ERROR: terminating test with failures." severity failure; end process check_outputs; ----------------------------------------------------------------------- -- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing ----------------------------------------------------------------------- -- Data slave channel alias signals s_axis_data_tdata_data <= s_axis_data_tdata(15 downto 0); -- Data master channel alias signals: update these only when they are valid m_axis_data_tdata_data <= m_axis_data_tdata(40 downto 0) when m_axis_data_tvalid = '1'; end tb; |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_0; USE floating_point_v7_0.floating_point_v7_0; ENTITY HLS_accel_ap_faddfsub_3_full_dsp_32 IS PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END HLS_accel_ap_faddfsub_3_full_dsp_32; ARCHITECTURE HLS_accel_ap_faddfsub_3_full_dsp_32_arch OF HLS_accel_ap_faddfsub_3_full_dsp_32 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF HLS_accel_ap_faddfsub_3_full_dsp_32_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_0 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF HLS_accel_ap_faddfsub_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2014.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF HLS_accel_ap_faddfsub_3_full_dsp_32_arch : ARCHITECTURE IS "HLS_accel_ap_faddfsub_3_full_dsp_32,floating_point_v7_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF HLS_accel_ap_faddfsub_3_full_dsp_32_arch: ARCHITECTURE IS "HLS_accel_ap_faddfsub_3_full_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=1,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=1,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_0 GENERIC MAP ( C_XDEVICEFAMILY => "virtex7", C_HAS_ADD => 1, C_HAS_SUBTRACT => 1, C_HAS_MULTIPLY => 0, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 24, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 24, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 24, C_RESULT_WIDTH => 32, C_RESULT_FRACTION_WIDTH => 24, C_COMPARE_OPERATION => 8, C_LATENCY => 3, C_OPTIMIZATION => 1, C_MULT_USAGE => 2, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 1, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 1, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 1, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 32, C_RESULT_TUSER_WIDTH => 1 ) PORT MAP ( aclk => aclk, aclken => aclken, aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => s_axis_b_tvalid, s_axis_b_tdata => s_axis_b_tdata, s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => s_axis_operation_tvalid, s_axis_operation_tdata => s_axis_operation_tdata, s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END HLS_accel_ap_faddfsub_3_full_dsp_32_arch; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library std; use std.textio.all; library work; use work.all; use work.procedures.all; entity tb_serial is end tb_serial; architecture behav of tb_serial is signal rst : std_logic := '1'; signal clk : std_logic := '0'; signal rx : std_logic := '1'; signal tx : std_logic := '1'; signal ena : std_logic := '0'; signal wea : std_logic := '0'; signal dia : std_logic_vector(7 downto 0) := (others => '0'); signal doa : std_logic_vector(7 downto 0) := (others => '0'); signal busy : std_logic := '0'; begin process begin clk <= '1'; wait for 10 ns; clk <= '0'; wait for 10 ns; end process; process variable l : line; begin wait for 61 ns; rst <= '0'; wait for 20 ns; ena <= '1'; wea <= '1'; dia <= X"A1"; wait for 20 ns; dia <= X"A2"; wait for 20 ns; dia <= X"A3"; wait for 20 ns; wea <= '0'; wait for 300 us; assert false report "stop" severity failure; end process; aserial: entity work.serial port map( rst => rst, clk => clk, rx => rx, tx => tx, ena => ena, wea => wea, dia => dia, doa => doa, busy => busy ); rx <= tx; end behav; |
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_misc.all; use work.alu_types.all; use work.cu.all; entity CU_UP is generic ( MICROCODE_MEM_SIZE : integer := 57; -- U Microcode Memory Size ALU_OPC_SIZE : integer := 2; -- ALU Op Code Word Size CW_SIZE : integer := 13 -- U Control Word Size ); port ( -- Inputs CLK : in std_logic; -- Clock RST : in std_logic; -- Reset:Active-High IR : in std_logic_vector(31 downto 0); JMP_PREDICT : in std_logic; -- Jump Prediction ICACHE_STALL: in std_logic; -- The instruction cache is in stall DCACHE_STALL: in std_logic; -- The rwcache is busy ISZERO : in std_logic; -- Needed for condizional jumps JMP_ADDRESS : in std_logic_vector(31 downto 0); NPC_ADDRESS : in std_logic_vector(31 downto 0); PC : out std_logic_vector(31 downto 0); -- Outputs JUMP: out std_logic; LATCHER: out std_logic; MUXIMMEDIATE_CTR: out std_logic; MUXJMPADDRESS_CTR: out std_logic; MUXRD0_CTR: out std_logic; MUXRD_CTR: out std_logic; WRF_ENABLE: out std_logic; WRF_CALL: out std_logic; WRF_RET: out std_logic; WRF_RS1_ENABLE: out std_logic; WRF_RS2_ENABLE: out std_logic; MUXALUOUT_CTR: out std_logic; MUXALU_CTR: out std_logic; ALU_FUNC: out std_logic_vector(4 downto 0); MEMORY_ENABLE: out std_logic; MEMORY_RNOTW: out std_logic; WRF_RD_ENABLE: out std_logic; ID_STALL: out std_logic; EXE_STALL: out std_logic; MEM_STALL: out std_logic; WB_STALL: out std_logic ); end CU_UP; architecture RTL of CU_UP is signal LUTOUT : std_logic_vector(18 downto 0); signal PIPE1 : std_logic_vector(18 downto 0) := (others => '0'); signal PIPE2 : std_logic_vector(9 downto 0) := (others => '0'); signal PIPE3 : std_logic_vector(2 downto 0) := (others => '0'); signal PIPE4 : std_logic := '0'; signal JUMPER : std_logic_vector(1 downto 0); signal JUMPER_DELAYED : std_logic_vector(1 downto 0); signal PIPEREG12 : std_logic_vector(9 downto 0) := (others => '0'); signal PIPEREG23 : std_logic_vector(2 downto 0) := (others => '0'); signal PIPEREG34 : std_logic := '0'; signal PIPE1_STALL : std_logic; signal PIPE2_STALL : std_logic; signal PIPE3_STALL : std_logic; signal PIPE4_STALL : std_logic; signal OPCODE : OPCODE_TYPE; signal FUNC : FUNC_TYPE; signal JMP_PREDICT_DELAYED : std_logic; signal STALL_DELAYED : std_logic; begin -- -- LUTOUT bits -- EN1 | RF1 | RF2 | EN2 | S1 | S2 | ALU1 | ALU2 | EN3 | RM | WM | S3 | WF1 -- -- Link the outputs of the pipeline registers to the single control signals. -- -- Pipelines PIPEREG12 <= PIPE1(9 downto 0); PIPEREG23 <= PIPE2(2 downto 0); PIPEREG34 <= PIPE3(0); -- -- Outputs -- ID_STALL <= PIPE1_STALL; EXE_STALL <= PIPE2_STALL; MEM_STALL <= PIPE3_STALL; WB_STALL <= PIPE4_STALL; -- STAGE ID MUXIMMEDIATE_CTR <= PIPE1(18); MUXJMPADDRESS_CTR <= PIPE1(17); MUXRD0_CTR <= PIPE1(16); MUXRD_CTR <= PIPE1(15); WRF_ENABLE <= PIPE1(14); WRF_CALL <= PIPE1(13); WRF_RET <= PIPE1(12); WRF_RS1_ENABLE <= PIPE1(11); WRF_RS2_ENABLE <= PIPE1(10); --Stage EXE MUXALUOUT_CTR <= PIPE2(9); MUXALU_CTR <= PIPE2(8); ALU_FUNC <= PIPE2(7 downto 3); -- Stage MEM MEMORY_ENABLE <= PIPE2(2); MEMORY_RNOTW <= PIPE2(1); -- Stage WB WRF_RD_ENABLE <= PIPE4; -- -- Inputs -- OPCODE <= IR(31 downto 31-OPCODE_SIZE+1); FUNC <= IR(FUNC_SIZE-1 downto 0); -- -- Look Up Table -- -- Implements the instruction decode logic -- PROCESS_LUT: process(RST, CLK) variable JMP_REAL : std_logic; variable JMP_REAL_LATCHED : std_logic; variable JMP_ADDRESS_LATCHED : std_logic_vector( 31 downto 0 ); variable INT_LUTOUT : std_logic_vector( 18 downto 0 ); begin -- If reset OR stall -> feed NOPS if RST = '1' then INT_LUTOUT := "000000000" & "0000000" & "00" & "0"; PIPE2 <= (others => '0'); PIPE3 <= (others => '0'); PIPE4 <= '0'; PC <= (others => '0'); JUMPER <= "00"; JUMP <= '0'; JMP_REAL := '0'; JMP_REAL_LATCHED := '0'; JMP_PREDICT_DELAYED <= '0'; elsif clk'event and clk = '1' then JUMPER <= "00"; case (OPCODE) is -- Register - Register [ OPCODE(6) - RS1(5) - RS2(5) - RD(5) - FUNC(11) ] when RTYPE => --report "RTYPE, Bitch!"; case (FUNC) is when RTYPE_NOP => INT_LUTOUT := "000000000" & "0000000" & "00" & "0"; when RTYPE_ADD => INT_LUTOUT := "000110011" & "01" & ALUADD & "00" & "1"; when RTYPE_AND => INT_LUTOUT := "000110011" & "01" & ALUAND & "00" & "1"; when RTYPE_OR => INT_LUTOUT := "000110011" & "01" & ALUOR & "00" & "1"; when RTYPE_SUB => INT_LUTOUT := "000110011" & "01" & ALUSUB & "00" & "1"; when RTYPE_XOR => INT_LUTOUT := "000110011" & "01" & ALUXOR & "00" & "1"; when RTYPE_SLL => INT_LUTOUT := "000110011" & "01" & ALUSLL & "00" & "1"; when RTYPE_SRL => INT_LUTOUT := "000110011" & "01" & ALUSRL & "00" & "1"; when RTYPE_SRA => INT_LUTOUT := "000110011" & "01" & ALUSRA & "00" & "1"; when RTYPE_SEQ => INT_LUTOUT := "000110011" & "01" & ALUSEQ & "00" & "1"; when RTYPE_SNE => INT_LUTOUT := "000110011" & "01" & ALUSNE & "00" & "1"; when RTYPE_SGE => INT_LUTOUT := "000110011" & "01" & ALUSGE & "00" & "1"; when RTYPE_SGT => INT_LUTOUT := "000110011" & "01" & ALUSGT & "00" & "1"; when RTYPE_SLE => INT_LUTOUT := "000110011" & "01" & ALUSLE & "00" & "1"; when RTYPE_SLT => INT_LUTOUT := "000110011" & "01" & ALUSLT & "00" & "1"; when RTYPE_SGEU => INT_LUTOUT := "000110011" & "01" & ALUSGEU & "00" & "1"; when RTYPE_SGTU => INT_LUTOUT := "000110011" & "01" & ALUSGTU & "00" & "1"; when RTYPE_SLEU => INT_LUTOUT := "000110011" & "01" & ALUSLEU & "00" & "1"; when RTYPE_SLTU => INT_LUTOUT := "000110011" & "01" & ALUSLTU & "00" & "1"; when others => --report "I don't know how to handle this Rtype function!"; null; end case; when NOP => INT_LUTOUT := "000000000" & "0000000" & "00" & "0"; -- Jump [ OPCODE(6) - PCOFFSET(26) ] when JTYPE_J => INT_LUTOUT := "000000000" & "0000000" & "00" & "0"; JUMPER <= "11"; when JTYPE_JAL => INT_LUTOUT := "101001000" & "1000000" & "00" & "1"; JUMPER <= "11"; when JTYPE_JR => INT_LUTOUT := "010010110" & "0000000" & "00" & "0"; JUMPER <= "11"; -- Branch [ OPCODE(6) - REG(5) - PCOFFSET(21) ] when BTYPE_BEQZ => INT_LUTOUT := "000010011" & "0000000" & "00" & "0"; JUMPER <= "01"; when BTYPE_BNEZ => INT_LUTOUT := "000010011" & "0000000" & "00" & "0"; JUMPER <= "10"; -- Memory [ OPCODE(6) - RDISPLACEMENT(5) - REG(5) - DISPLACEMENT(16) ] when MTYPE_LW => INT_LUTOUT := "000010010" & "00" & ALUADD & "11" & "1"; when MTYPE_SW => INT_LUTOUT := "000010011" & "00" & ALUADD & "10" & "0"; -- Immediate [ OPCODE(6) - RS1(5) - RD(5) - IMMEDIATE(16) ] when ITYPE_ADD => INT_LUTOUT := "000010010" & "00" & ALUADD & "00" & "1"; when ITYPE_AND => INT_LUTOUT := "000010010" & "00" & ALUAND & "00" & "1"; when ITYPE_OR => INT_LUTOUT := "000010010" & "00" & ALUOR & "00" & "1"; when ITYPE_SUB => INT_LUTOUT := "000010010" & "00" & ALUSUB & "00" & "1"; when ITYPE_XOR => INT_LUTOUT := "000010010" & "00" & ALUXOR & "00" & "1"; when ITYPE_SLL => INT_LUTOUT := "000010010" & "00" & ALUSLL & "00" & "1"; when ITYPE_SRL => INT_LUTOUT := "000010010" & "00" & ALUSRL & "00" & "1"; when ITYPE_SRA => INT_LUTOUT := "000010010" & "00" & ALUSRA & "00" & "1"; when ITYPE_SEQ => INT_LUTOUT := "000010010" & "00" & ALUSEQ & "00" & "1"; when ITYPE_SNE => INT_LUTOUT := "000010010" & "00" & ALUSNE & "00" & "1"; when ITYPE_SGE => INT_LUTOUT := "000010010" & "00" & ALUSGE & "00" & "1"; when ITYPE_SGT => INT_LUTOUT := "000010010" & "00" & ALUSGT & "00" & "1"; when ITYPE_SLE => INT_LUTOUT := "000010010" & "00" & ALUSLE & "00" & "1"; when ITYPE_SLT => INT_LUTOUT := "000010010" & "00" & ALUSLT & "00" & "1"; when ITYPE_SGEU => INT_LUTOUT := "000010010" & "00" & ALUSGEU & "00" & "1"; when ITYPE_SGTU => INT_LUTOUT := "000010010" & "00" & ALUSGTU & "00" & "1"; when ITYPE_SLEU => INT_LUTOUT := "000010010" & "00" & ALUSLEU & "00" & "1"; when ITYPE_SLTU => INT_LUTOUT := "000010010" & "00" & ALUSLTU & "00" & "1"; -- Eh boh! when others => null; end case; -- JUMPS AND STALLS JUMPER_DELAYED <= JUMPER; STALL_DELAYED <= ICACHE_STALL or DCACHE_STALL; JMP_REAL := ( ( not or_reduce(JUMPER xor "01") and ISZERO ) or ( not or_reduce(JUMPER xor "10") and not ISZERO ) or ( not or_reduce(JUMPER xor "11") ) ) xor JMP_PREDICT_DELAYED; if STALL_DELAYED = '0' then JMP_REAL_LATCHED := JMP_REAL; JMP_ADDRESS_LATCHED := JMP_ADDRESS; end if; JUMP <= JMP_REAL_LATCHED; JMP_PREDICT_DELAYED <= JMP_PREDICT; -- Any stall? Don't update PC, feed NOPS if ICACHE_STALL = '0' and DCACHE_STALL = '0' then if JMP_REAL_LATCHED = '1' then PC <= JMP_ADDRESS_LATCHED; else PC <= NPC_ADDRESS; end if; end if; -- If there is a stall later on in the pipe, freeze everything if DCACHE_STALL = '0' then -- Bubble propagation in stage 2 when -- 1) Mispredicted branch -- 2) Instruction cache stall if JMP_REAL_LATCHED = '1' or ICACHE_STALL = '1' then PIPE1 <= (others => '0'); PIPE1_STALL <= '1'; else PIPE1 <= INT_LUTOUT; PIPE1_STALL <= '0'; end if; PIPE2 <= PIPEREG12; PIPE2_STALL <= PIPE1_STALL; PIPE3 <= PIPEREG23; PIPE3_STALL <= PIPE2_STALL; PIPE4 <= PIPEREG34; else PIPE1_STALL <= '1'; PIPE2_STALL <= '1'; PIPE3_STALL <= '1'; PIPE4 <= '0'; end if; PIPE4_STALL <= PIPE3_STALL; LATCHER <= not DCACHE_STALL ; end if; end process; end RTL; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bramblk_mem_gen_prim_wrapper is port ( doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); end bramblk_mem_gen_prim_wrapper; architecture STRUCTURE of bramblk_mem_gen_prim_wrapper is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal _74_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : STD_LOGIC; signal _75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => 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X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 18, READ_WIDTH_B => 18, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "READ_FIRST", WRITE_MODE_B => "READ_FIRST", WRITE_WIDTH_A => 18, WRITE_WIDTH_B => 18 ) port map ( ADDRARDADDR(15) => \<const1>\, ADDRARDADDR(14 downto 4) => addra(10 downto 0), ADDRARDADDR(3) => \<const1>\, ADDRARDADDR(2) => \<const1>\, ADDRARDADDR(1) => \<const1>\, ADDRARDADDR(0) => \<const1>\, ADDRBWRADDR(15) => \<const1>\, ADDRBWRADDR(14 downto 4) => addrb(10 downto 0), ADDRBWRADDR(3) => \<const1>\, ADDRBWRADDR(2) => \<const1>\, ADDRBWRADDR(1) => \<const1>\, ADDRBWRADDR(0) => \<const1>\, CASCADEINA => \<const0>\, CASCADEINB => \<const0>\, CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clkb, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31) => \<const0>\, DIADI(30) => \<const0>\, DIADI(29) => \<const0>\, DIADI(28) => \<const0>\, DIADI(27) => \<const0>\, DIADI(26) => \<const0>\, DIADI(25) => \<const0>\, DIADI(24) => \<const0>\, DIADI(23) => \<const0>\, DIADI(22) => \<const0>\, DIADI(21) => \<const0>\, DIADI(20) => \<const0>\, DIADI(19) => \<const0>\, DIADI(18) => \<const0>\, DIADI(17) => \<const0>\, DIADI(16) => \<const0>\, DIADI(15 downto 0) => dina(15 downto 0), DIBDI(31) => \<const0>\, DIBDI(30) => \<const0>\, DIBDI(29) => \<const0>\, DIBDI(28) => \<const0>\, DIBDI(27) => \<const0>\, DIBDI(26) => \<const0>\, DIBDI(25) => \<const0>\, DIBDI(24) => \<const0>\, DIBDI(23) => \<const0>\, DIBDI(22) => \<const0>\, DIBDI(21) => \<const0>\, DIBDI(20) => \<const0>\, DIBDI(19) => \<const0>\, DIBDI(18) => \<const0>\, DIBDI(17) => \<const0>\, DIBDI(16) => \<const0>\, DIBDI(15) => \<const0>\, DIBDI(14) => \<const0>\, DIBDI(13) => \<const0>\, DIBDI(12) => \<const0>\, DIBDI(11) => \<const0>\, DIBDI(10) => \<const0>\, DIBDI(9) => \<const0>\, DIBDI(8) => \<const0>\, DIBDI(7) => \<const0>\, DIBDI(6) => \<const0>\, DIBDI(5) => \<const0>\, DIBDI(4) => \<const0>\, DIBDI(3) => \<const0>\, DIBDI(2) => \<const0>\, DIBDI(1) => \<const0>\, DIBDI(0) => \<const0>\, DIPADIP(3) => \<const0>\, DIPADIP(2) => \<const0>\, DIPADIP(1) => \<const0>\, DIPADIP(0) => \<const0>\, DIPBDIP(3) => \<const0>\, DIPBDIP(2) => \<const0>\, DIPBDIP(1) => \<const0>\, DIPBDIP(0) => \<const0>\, DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0), DOBDO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 16), DOBDO(15 downto 0) => doutb(15 downto 0), DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 2), DOPBDOP(1) => _74_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\, DOPBDOP(0) => _75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\, ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => wea(0), ENBWREN => \<const1>\, INJECTDBITERR => \<const0>\, INJECTSBITERR => \<const0>\, RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => \<const0>\, REGCEB => \<const1>\, RSTRAMARSTRAM => \<const0>\, RSTRAMB => \<const0>\, RSTREGARSTREG => \<const0>\, RSTREGB => \<const0>\, SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => \<const1>\, WEA(2) => \<const1>\, WEA(1) => \<const1>\, WEA(0) => \<const1>\, WEBWE(7) => \<const0>\, WEBWE(6) => \<const0>\, WEBWE(5) => \<const0>\, WEBWE(4) => \<const0>\, WEBWE(3) => \<const0>\, WEBWE(2) => \<const0>\, WEBWE(1) => \<const0>\, WEBWE(0) => \<const0>\ ); GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bramblk_mem_gen_prim_width is port ( doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); end bramblk_mem_gen_prim_width; architecture STRUCTURE of bramblk_mem_gen_prim_width is begin \prim_noinit.ram\: entity work.bramblk_mem_gen_prim_wrapper port map ( addra(10 downto 0) => addra(10 downto 0), addrb(10 downto 0) => addrb(10 downto 0), clka => clka, clkb => clkb, dina(15 downto 0) => dina(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bramblk_mem_gen_generic_cstr is port ( doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); end bramblk_mem_gen_generic_cstr; architecture STRUCTURE of bramblk_mem_gen_generic_cstr is begin \ramloop[0].ram.r\: entity work.bramblk_mem_gen_prim_width port map ( addra(10 downto 0) => addra(10 downto 0), addrb(10 downto 0) => addrb(10 downto 0), clka => clka, clkb => clkb, dina(15 downto 0) => dina(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bramblk_mem_gen_top is port ( doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); end bramblk_mem_gen_top; architecture STRUCTURE of bramblk_mem_gen_top is begin \valid.cstr\: entity work.bramblk_mem_gen_generic_cstr port map ( addra(10 downto 0) => addra(10 downto 0), addrb(10 downto 0) => addrb(10 downto 0), clka => clka, clkb => clkb, dina(15 downto 0) => dina(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bramblk_mem_gen_v8_1_synth is port ( doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); end bramblk_mem_gen_v8_1_synth; architecture STRUCTURE of bramblk_mem_gen_v8_1_synth is begin \gnativebmg.native_blk_mem_gen\: entity work.bramblk_mem_gen_top port map ( addra(10 downto 0) => addra(10 downto 0), addrb(10 downto 0) => addrb(10 downto 0), clka => clka, clkb => clkb, dina(15 downto 0) => dina(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \bramblk_mem_gen_v8_1__parameterized0\ is port ( doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \bramblk_mem_gen_v8_1__parameterized0\ : entity is "blk_mem_gen_v8_1"; end \bramblk_mem_gen_v8_1__parameterized0\; architecture STRUCTURE of \bramblk_mem_gen_v8_1__parameterized0\ is begin inst_blk_mem_gen: entity work.bramblk_mem_gen_v8_1_synth port map ( addra(10 downto 0) => addra(10 downto 0), addrb(10 downto 0) => addrb(10 downto 0), clka => clka, clkb => clkb, dina(15 downto 0) => dina(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity bram is port ( clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); dina : in STD_LOGIC_VECTOR ( 15 downto 0 ); clkb : in STD_LOGIC; addrb : in STD_LOGIC_VECTOR ( 10 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of bram : entity is true; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of bram : entity is "yes"; attribute x_core_info : string; attribute x_core_info of bram : entity is "blk_mem_gen_v8_1,Vivado 2013.4"; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of bram : entity is "bram,blk_mem_gen_v8_1,{}"; attribute core_generation_info : string; attribute core_generation_info of bram : entity is "bram,blk_mem_gen_v8_1,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.1,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=bram.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_RST_TYPE=SYNC,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=READ_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=1,C_ENABLE_32BIT_ADDRESS=0,C_DISABLE_WARN_BHV_COLL=0,C_DISABLE_WARN_BHV_RANGE=0,C_USE_BRAM_BLOCK=0,C_CTRL_ECC_ALGO=NONE}"; end bram; architecture STRUCTURE of bram is begin U0: entity work.\bramblk_mem_gen_v8_1__parameterized0\ port map ( addra(10 downto 0) => addra(10 downto 0), addrb(10 downto 0) => addrb(10 downto 0), clka => clka, clkb => clkb, dina(15 downto 0) => dina(15 downto 0), doutb(15 downto 0) => doutb(15 downto 0), wea(0) => wea(0) ); end STRUCTURE; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity RegisterBank is Port ( RST : in STD_LOGIC; RAddr : in STD_LOGIC_VECTOR (3 downto 0); -- RBddr : in STD_LOGIC_VECTOR (3 downto 0); -- RWddr : in STD_LOGIC_VECTOR (3 downto 0); DATAIN : in STD_LOGIC_VECTOR (15 downto 0); clk : in STD_LOGIC; R : in STD_LOGIC; W : in STD_LOGIC; RAout : out STD_LOGIC_VECTOR (15 downto 0); -- RBout : out STD_LOGIC_VECTOR (15 downto 0)); -- end RegisterBank; architecture Behavioral of RegisterBank is signal R0dat, R1dat, R2dat, R3dat, R4dat, R5dat, R6dat, R7dat, R8dat, R9dat, R10dat, R11dat, R12dat, R13dat, R14dat, R15dat : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0'); begin process(clk,RST) -- Synchronous register bank begin if(rising_edge(clk) and R = '1') then -- Synchronous data read when read line enabled on rising edge (before write back) case RAddr is when x"0" => RAout <= R0dat; when x"1" => RAout <= R1dat; when x"2" => RAout <= R2dat; when x"3" => RAout <= R3dat; when x"4" => RAout <= R4dat; when x"5" => RAout <= R5dat; when x"6" => RAout <= R6dat; when x"7" => RAout <= R7dat; when x"8" => RAout <= R8dat; when x"9" => RAout <= R9dat; when x"A" => RAout <= R10dat; when x"B" => RAout <= R11dat; when x"C" => RAout <= R12dat; when x"D" => RAout <= R13dat; when x"E" => RAout <= R14dat; when x"F" => RAout <= R15dat; when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS end case; case RBddr is when x"0" => RBout <= R0dat; when x"1" => RBout <= R1dat; when x"2" => RBout <= R2dat; when x"3" => RBout <= R3dat; when x"4" => RBout <= R4dat; when x"5" => RBout <= R5dat; when x"6" => RBout <= R6dat; when x"7" => RBout <= R7dat; when x"8" => RBout <= R8dat; when x"9" => RBout <= R9dat; when x"A" => RBout <= R10dat; when x"B" => RBout <= R11dat; when x"C" => RBout <= R12dat; when x"D" => RBout <= R13dat; when x"E" => RBout <= R14dat; when x"F" => RBout <= R15dat; when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS end case; end if; if(falling_edge(clk) and W = '1') then -- Synchronous data latching when write line enabled (after data read) case RWddr is when x"0" => R0dat <= DATAIN; when x"1" => R1dat <= DATAIN; when x"2" => R2dat <= DATAIN; when x"3" => R3dat <= DATAIN; when x"4" => R4dat <= DATAIN; when x"5" => R5dat <= DATAIN; when x"6" => R6dat <= DATAIN; when x"7" => R7dat <= DATAIN; when x"8" => R8dat <= DATAIN; when x"9" => R9dat <= DATAIN; when x"A" => R10dat <= DATAIN; when x"B" => R11dat <= DATAIN; when x"C" => R12dat <= DATAIN; when x"D" => R13dat <= DATAIN; when x"E" => R14dat <= DATAIN; when x"F" => R15dat <= DATAIN; when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS end case; end if; end process; end Behavioral; |
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY instruction_memory_synth IS PORT( CLK_IN : IN STD_LOGIC; RESET_IN : IN STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA ); END ENTITY; ARCHITECTURE instruction_memory_synth_ARCH OF instruction_memory_synth IS COMPONENT instruction_memory_exdes PORT ( --Inputs - Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); CLKA : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA: STD_LOGIC := '0'; SIGNAL RSTA: STD_LOGIC := '0'; SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA_R: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL CHECKER_EN : STD_LOGIC:='0'; SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); SIGNAL clk_in_i: STD_LOGIC; SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; SIGNAL ITER_R0 : STD_LOGIC := '0'; SIGNAL ITER_R1 : STD_LOGIC := '0'; SIGNAL ITER_R2 : STD_LOGIC := '0'; SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); BEGIN clk_in_i <= CLK_IN; CLKA <= clk_in_i; RSTA <= RESET_SYNC_R3 AFTER 50 ns; PROCESS(clk_in_i) BEGIN IF(RISING_EDGE(clk_in_i)) THEN RESET_SYNC_R1 <= RESET_IN; RESET_SYNC_R2 <= RESET_SYNC_R1; RESET_SYNC_R3 <= RESET_SYNC_R2; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ISSUE_FLAG_STATUS<= (OTHERS => '0'); ELSE ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; END IF; END IF; END PROCESS; STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; BMG_DATA_CHECKER_INST: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 16, READ_WIDTH => 16 ) PORT MAP ( CLK => CLKA, RST => RSTA, EN => CHECKER_EN_R, DATA_IN => DOUTA, STATUS => ISSUE_FLAG(0) ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RSTA='1') THEN CHECKER_EN_R <= '0'; ELSE CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; END IF; END IF; END PROCESS; BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN PORT MAP( CLK => clk_in_i, RST => RSTA, ADDRA => ADDRA, DINA => DINA, WEA => WEA, CHECK_DATA => CHECKER_EN ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STATUS(8) <= '0'; iter_r2 <= '0'; iter_r1 <= '0'; iter_r0 <= '0'; ELSE STATUS(8) <= iter_r2; iter_r2 <= iter_r1; iter_r1 <= iter_r0; iter_r0 <= STIMULUS_FLOW(8); END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STIMULUS_FLOW <= (OTHERS => '0'); ELSIF(WEA(0)='1') THEN STIMULUS_FLOW <= STIMULUS_FLOW+1; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN WEA_R <= (OTHERS=>'0') AFTER 50 ns; DINA_R <= (OTHERS=>'0') AFTER 50 ns; ELSE WEA_R <= WEA AFTER 50 ns; DINA_R <= DINA AFTER 50 ns; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; ELSE ADDRA_R <= ADDRA AFTER 50 ns; END IF; END IF; END PROCESS; BMG_PORT: instruction_memory_exdes PORT MAP ( --Port A WEA => WEA_R, ADDRA => ADDRA_R, DINA => DINA_R, DOUTA => DOUTA, CLKA => CLKA ); END ARCHITECTURE; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.procedures.all; entity cpu is port( rst : in std_logic; clk : in std_logic; clk2x : in std_logic; ena : out std_logic; addra : out t_data2; doa : in t_data2; enb : out std_logic; addrb : out t_data2; dob : in t_data2; web : out std_logic_vector(1 downto 0); dib : out t_data2; bbusy : in std_logic ); end cpu; architecture Structural of cpu is signal PC : unsigned(t_data2'range); type t_cmd is (CMD_NOOP, CMD_ADD, CMD_ADDC, CMD_SUB, CMD_SUBB, CMD_AND, CMD_OR, CMD_XOR, CMD_SHL, CMD_SHR, CMD_SAR, CMD_MOV, CMD_MOVM, CMD_CMP, CMD_JMP); type t_cmp is (CMP_NONE, CMP_Z, CMP_NZ, CMP_LE, CMP_LT, CMP_GE, CMP_GT, CMP_ULE, CMP_ULT, CMP_UGE, CMP_UGT); type t_ctrl is record cmd : t_cmd; l : std_logic; h : std_logic; mov : std_logic_vector(1 downto 0); cmp : t_cmp; A : std_logic_vector(3 downto 0); A_d : t_data2; B : std_logic_vector(3 downto 0); B_d : t_data2; arg : t_data2; C : std_logic_vector(3 downto 0); end record; constant ctrl_noop : t_ctrl := ( cmd => CMD_NOOP, l => '0', h => '0', mov => (others => '0'), cmp => CMP_NONE, A => (others => '0'), A_d => (others => '0'), B => (others => '0'), B_d => (others => '0'), arg => (others => '0'), C => (others => '0')); signal decoded_cmd : t_ctrl; attribute INIT : t_ctrl; attribute INIT of decoded_cmd : signal is ctrl_noop; signal regH : t_data_array(15 downto 0); signal regL : t_data_array(15 downto 0); signal reg_A_d : t_data2; signal reg_B_d : t_data2; signal reg_C_d : t_data2; signal reg_C : std_logic_vector(3 downto 0); signal wb_C : std_logic_vector(1 downto 0); type wb_which_t is (WB_REG, WB_MEM, WB_MPMEM); signal wb_which : wb_which_t; signal A_d : signed(15 downto 0); signal B_d : signed(15 downto 0); signal C_flag : std_logic; signal V_flag : std_logic; signal Z_flag : std_logic; signal S_flag : std_logic; signal do_jmp : std_logic; type t_fetch is (FETCH_CMD, FETCH_A, FETCH_B, FETCH_BOTH, FETCH_ARG); signal fetch_state : t_fetch; signal C_result : std_logic_vector(t_data2'range); signal pdata_rd : std_logic; signal mp_busy : std_logic; signal mp_start : std_logic; signal reg_doa : t_data; signal reg_dob : t_data; signal reg_ena : std_logic; signal reg_enb : std_logic; signal reg_addra : t_data; signal reg_addrb : t_data; signal mpmem_addra : std_logic_vector(9 downto 0); signal mpmem_ena : std_logic; signal mpmem_doa : t_data; signal mpmem_addrb : std_logic_vector(9 downto 0); signal mpmem_enb : std_logic; signal mpmem_dob : t_data; signal rst_1 : std_logic; signal A_hold : std_logic_vector(3 downto 0); signal B_hold : std_logic_vector(3 downto 0); signal suspend : std_logic; begin suspend <= '1' when (fetch_state = FETCH_CMD and doa(15 downto 4) = "000000001100" and mp_busy = '1') or bbusy = '1' else '0'; process(clk) begin if rising_edge(clk) then rst_1 <= rst; end if; end process; mem_fetch: process(clk) begin if rising_edge(clk) then if rst = '1' then PC <= (others => '0'); elsif suspend = '0' then if do_jmp = '1' then PC <= unsigned(std_logic_vector(B_d)) + 1; else PC <= PC + 1; end if; end if; end if; end process mem_fetch; ena <= not suspend; addra <= std_logic_vector(PC) when do_jmp = '0' else std_logic_vector(B_d); register_file: process(clk) begin if rising_edge(clk) then if wb_C(1) = '1' then regH(to_integer(unsigned(reg_C))) <= reg_C_d(15 downto 8); end if; if wb_C(0) = '1' then regL(to_integer(unsigned(reg_C))) <= reg_C_d(7 downto 0); end if; if (wb_C(1) = '1' or wb_C(0) = '1') and ((reg_C = doa(7 downto 4) and fetch_state = FETCH_CMD) or (reg_C = A_hold and fetch_state /= FETCH_CMD)) then if wb_C(1) = '1' then reg_A_d(15 downto 8) <= reg_C_d(15 downto 8); else reg_A_d(15 downto 8) <= regH(to_integer(unsigned(reg_C))); end if; if wb_C(0) = '1' then reg_A_d(7 downto 0) <= reg_C_d(7 downto 0); else reg_A_d(7 downto 0) <= regL(to_integer(unsigned(reg_C))); end if; elsif fetch_state = FETCH_CMD then reg_A_d(15 downto 8) <= regH(to_integer(unsigned(doa(7 downto 4)))); reg_A_d(7 downto 0) <= regL(to_integer(unsigned(doa(7 downto 4)))); end if; if (wb_C(1) = '1' or wb_C(0) = '1') and ((reg_C = doa(3 downto 0) and fetch_state = FETCH_CMD) or (reg_C = B_hold and fetch_state /= FETCH_CMD)) then if wb_C(1) = '1' then reg_B_d(15 downto 8) <= reg_C_d(15 downto 8); else reg_B_d(15 downto 8) <= regH(to_integer(unsigned(reg_C))); end if; if wb_C(0) = '1' then reg_B_d(7 downto 0) <= reg_C_d(7 downto 0); else reg_B_d(7 downto 0) <= regL(to_integer(unsigned(reg_C))); end if; elsif fetch_state = FETCH_CMD then reg_B_d(15 downto 8) <= regH(to_integer(unsigned(doa(3 downto 0)))); reg_B_d(7 downto 0) <= regL(to_integer(unsigned(doa(3 downto 0)))); end if; if reg_ena = '1' then if reg_addra(4) = '1' then reg_doa <= regH(to_integer(unsigned(reg_addra(3 downto 0)))); else reg_doa <= regL(to_integer(unsigned(reg_addra(3 downto 0)))); end if; end if; if reg_enb = '1' then if reg_addrb(4) = '1' then reg_dob <= regH(to_integer(unsigned(reg_addrb(3 downto 0)))); else reg_dob <= regL(to_integer(unsigned(reg_addrb(3 downto 0)))); end if; end if; end if; end process register_file; decode_fetch: process(clk) variable hold_cmd : t_ctrl; begin if rising_edge(clk) then if rst = '1' or rst_1 = '1' or do_jmp = '1' or pdata_rd = '1' then decoded_cmd <= ctrl_noop; hold_cmd := ctrl_noop; fetch_state <= FETCH_CMD; A_hold <= (others => '0'); B_hold <= (others => '0'); elsif suspend = '0' then case fetch_state is when FETCH_CMD => hold_cmd := ctrl_noop; hold_cmd.A := doa(7 downto 4); A_hold <= hold_cmd.A; hold_cmd.B := doa(3 downto 0); B_hold <= hold_cmd.B; hold_cmd.C := doa(11 downto 8); hold_cmd.l := doa(8); hold_cmd.h := doa(9); hold_cmd.mov := doa(11 downto 10); case doa(15 downto 12) is when "0001" => hold_cmd.cmd := CMD_ADD; when "0010" => hold_cmd.cmd := CMD_ADDC; when "0011" => hold_cmd.cmd := CMD_SUB; when "0100" => hold_cmd.cmd := CMD_SUBB; when "0101" => hold_cmd.cmd := CMD_AND; when "0110" => hold_cmd.cmd := CMD_OR; when "0111" => hold_cmd.cmd := CMD_XOR; when "1000" => hold_cmd.cmd := CMD_SHL; when "1001" => hold_cmd.cmd := CMD_SHR; when "1010" => hold_cmd.cmd := CMD_SAR; when "1100" => if doa(11 downto 10) = "00" then hold_cmd.cmd := CMD_MOV; else hold_cmd.cmd := CMD_MOVM; end if; when others => end case; if doa(15 downto 8) = "00000001" then hold_cmd.cmd := CMD_CMP; end if; if doa(15 downto 8) = "00000000" then case doa(7 downto 4) is when "0001" => hold_cmd.cmd := CMD_JMP; when "0010" => hold_cmd.cmd := CMD_JMP; hold_cmd.cmp := CMP_Z; when "0011" => hold_cmd.cmd := CMD_JMP; hold_cmd.cmp := CMP_NZ; when "0100" => hold_cmd.cmd := CMD_JMP; hold_cmd.cmp := CMP_LE; when "0101" => hold_cmd.cmd := CMD_JMP; hold_cmd.cmp := CMP_LT; when "0110" => hold_cmd.cmd := CMD_JMP; hold_cmd.cmp := CMP_GE; when "0111" => hold_cmd.cmd := CMD_JMP; hold_cmd.cmp := CMP_GT; when "1000" => hold_cmd.cmd := CMD_JMP; hold_cmd.cmp := CMP_ULE; when "1001" => hold_cmd.cmd := CMD_JMP; hold_cmd.cmp := CMP_ULT; when "1010" => hold_cmd.cmd := CMD_JMP; hold_cmd.cmp := CMP_UGE; when "1011" => hold_cmd.cmd := CMD_JMP; hold_cmd.cmp := CMP_UGT; when others => end case; end if; decoded_cmd <= ctrl_noop; if doa(7 downto 0) = "11111111" then fetch_state <= FETCH_BOTH; elsif doa(7 downto 4) = "1111" and hold_cmd.cmd /= CMD_MOV then fetch_state <= FETCH_A; elsif doa(3 downto 0) = "1111" then fetch_state <= FETCH_B; elsif hold_cmd.cmd = CMD_MOVM then fetch_state <= FETCH_ARG; elsif doa(15 downto 4) /= "000000001100" then decoded_cmd <= hold_cmd; end if; when FETCH_BOTH => hold_cmd.A_d := doa; fetch_state <= FETCH_B; when FETCH_A => hold_cmd.A_d := doa; decoded_cmd <= hold_cmd; fetch_state <= FETCH_CMD; when FETCH_B => if hold_cmd.cmd = CMD_MOVM then hold_cmd.B_d := doa; fetch_state <= FETCH_ARG; else hold_cmd.B_d := doa; decoded_cmd <= hold_cmd; fetch_state <= FETCH_CMD; end if; when FETCH_ARG => hold_cmd.arg := doa; decoded_cmd <= hold_cmd; fetch_state <= FETCH_CMD; end case; end if; end if; end process decode_fetch; mp_start <= '0' when rst = '1' or rst_1 = '1' or do_jmp = '1' or pdata_rd = '1' or suspend = '1' else '1' when fetch_state = FETCH_CMD and doa(15 downto 4) = "000000001100" else '0'; mpmem_addra <= decoded_cmd.arg(1 downto 0) & std_logic_vector(B_d(7 downto 1)) & "0"; mpmem_addrb <= decoded_cmd.arg(1 downto 0) & std_logic_vector(B_d(7 downto 1)) & "1"; mpmem_ena <= decoded_cmd.l when decoded_cmd.mov = "11" and decoded_cmd.cmd = CMD_MOVM else '0'; mpmem_enb <= decoded_cmd.h when decoded_cmd.mov = "11" and decoded_cmd.cmd = CMD_MOVM else '0'; mp_i: entity work.mp port map ( rst => rst, clk => clk, clk2x => clk2x, pdata => doa, pdata_rd => pdata_rd, start => mp_start, busy => mp_busy, mem_addra => mpmem_addra, mem_ena => mpmem_ena, mem_doa => mpmem_doa, mem_addrb => mpmem_addrb, mem_enb => mpmem_enb, mem_dob => mpmem_dob, reg_addra => reg_addra, reg_ena => reg_ena, reg_doa => reg_doa, reg_addrb => reg_addrb, reg_enb => reg_enb, reg_dob => reg_dob ); A_d <= signed(decoded_cmd.A_d) when decoded_cmd.A = "1111" else (0 => '1', others => '0') when decoded_cmd.A = "1110" and (decoded_cmd.cmd = CMD_SHL or decoded_cmd.cmd = CMD_SHR or decoded_cmd.cmd = CMD_SAR) else (others => '0') when decoded_cmd.A = "1110" else signed(reg_C_d) when decoded_cmd.A = reg_C and (wb_C(1) = '1' or wb_C(0) = '1') else signed(reg_A_d); B_d <= signed(decoded_cmd.B_d) when decoded_cmd.B = "1111" else (0 => '1', others => '0') when decoded_cmd.B = "1110" and (decoded_cmd.cmd = CMD_SHL or decoded_cmd.cmd = CMD_SHR or decoded_cmd.cmd = CMD_SAR) else signed(reg_C_d) when decoded_cmd.B = reg_C and (wb_C(1) = '1' or wb_C(0) = '1') else (others => '0') when decoded_cmd.B = "1110" else signed(reg_B_d); execute: process(clk) variable C_d : signed(16 downto 0); begin if rising_edge(clk) then if suspend = '0' then wb_which <= WB_REG; wb_C <= "00"; reg_C <= decoded_cmd.C; C_d := (others => '0'); if do_jmp = '0' then case decoded_cmd.cmd is when CMD_ADD | CMD_ADDC | CMD_SUB | CMD_CMP | CMD_SUBB => if decoded_cmd.cmd /= CMD_CMP then wb_C <= "11"; end if; if decoded_cmd.cmd = CMD_ADD then C_d := to_signed(to_integer(A_d) + to_integer(B_d), 17); elsif decoded_cmd.cmd = CMD_ADDC then C_d := to_signed(to_integer(A_d) + to_integer(B_d) + to_integer(unsigned'("" & C_flag)), 17); elsif decoded_cmd.cmd = CMD_SUB or decoded_cmd.cmd = CMD_CMP then C_d := to_signed(to_integer(A_d) - to_integer(B_d), 17); else C_d := to_signed(to_integer(A_d) - to_integer(B_d) - to_integer(unsigned'("" & C_flag)), 17); end if; when CMD_AND => C_d := "0" & signed(A_d and B_d); wb_C <= "11"; when CMD_OR => C_d := "0" & signed(A_d or B_d); wb_C <= "11"; when CMD_XOR => C_d := "0" & signed(A_d xor B_d); wb_C <= "11"; when CMD_SHL => if B_d(15 downto 4) /= "000000000000" then C_d := (others => '0'); else C_d := "0" & signed(shift_left(A_d, to_integer(unsigned(std_logic_vector(B_d(3 downto 0)))))); end if; wb_C <= "11"; when CMD_SHR => if B_d(15 downto 4) /= "000000000000" then C_d := (others => '0'); else C_d := "0" & signed(shift_right(unsigned(std_logic_vector(A_d)), to_integer(unsigned(std_logic_vector(B_d(3 downto 0)))))); end if; wb_C <= "11"; when CMD_SAR => if B_d(15 downto 4) /= "000000000000" then C_d := (others => '0'); else C_d := "0" & signed(std_logic_vector(shift_right(A_d, to_integer(unsigned(std_logic_vector(B_d(3 downto 0))))))); end if; wb_C <= "11"; when CMD_MOV => C_d := "0" & B_d; reg_C <= decoded_cmd.A; wb_C <= "11"; when CMD_MOVM => reg_C <= decoded_cmd.A; if decoded_cmd.mov(1) = '1' then wb_C <= decoded_cmd.h & decoded_cmd.l; if decoded_cmd.mov(0) = '0' then wb_which <= WB_MEM; else wb_which <= WB_MPMEM; end if; end if; when others => end case; case decoded_cmd.cmd is when CMD_ADD | CMD_ADDC | CMD_SUB | CMD_SUBB | CMD_CMP => S_flag <= C_d(15); C_flag <= C_d(16); if C_d(15 downto 0) = "0000000000000000" then Z_flag <= '1'; else Z_flag <= '0'; end if; V_flag <= C_d(15) xor C_d(16) xor A_d(15) xor B_d(15); when CMD_AND | CMD_OR | CMD_XOR | CMD_SHL | CMD_SHR | CMD_SAR => if C_d(15 downto 0) = "0000000000000000" then Z_flag <= '1'; else Z_flag <= '0'; end if; when others => end case; end if; C_result <= std_logic_vector(C_d(15 downto 0)); end if; end if; end process execute; do_jmp <= '0' when decoded_cmd.cmd /= CMD_JMP or suspend = '1' else '1' when decoded_cmd.cmp = CMP_NONE or (decoded_cmd.cmp = CMP_Z and Z_flag = '1') or (decoded_cmd.cmp = CMP_NZ and Z_flag = '0') or (decoded_cmd.cmp = CMP_LE and (Z_flag = '1' or S_flag /= V_flag)) or (decoded_cmd.cmp = CMP_LT and S_flag /= V_flag) or (decoded_cmd.cmp = CMP_GE and S_flag = V_flag) or (decoded_cmd.cmp = CMP_GT and (Z_flag = '0' and S_flag = V_flag)) or (decoded_cmd.cmp = CMP_ULE and (C_flag = '1' or Z_flag = '1')) or (decoded_cmd.cmp = CMP_ULT and C_flag = '1') or (decoded_cmd.cmp = CMP_UGE and C_flag = '0') or (decoded_cmd.cmp = CMP_UGT and (C_flag = '0' and Z_flag = '0')) else '0'; web(0) <= decoded_cmd.l when decoded_cmd.mov = "01" and decoded_cmd.cmd = CMD_MOVM else '0'; web(1) <= decoded_cmd.h when decoded_cmd.mov = "01" and decoded_cmd.cmd = CMD_MOVM else '0'; enb <= '1' when (decoded_cmd.mov = "01" or decoded_cmd.mov = "10") and decoded_cmd.cmd = CMD_MOVM else '0'; addrb <= std_logic_vector(unsigned(decoded_cmd.arg) + unsigned(std_logic_vector(A_d))) when decoded_cmd.mov = "01" else -- write std_logic_vector(unsigned(decoded_cmd.arg) + unsigned(std_logic_vector(B_d))); --read dib <= std_logic_vector(B_d); reg_C_d <= dob when wb_which = WB_MEM else mpmem_dob & mpmem_doa when wb_which = WB_MPMEM else C_result; end Structural; |
library ieee; use ieee.std_logic_1164.all; entity tb_soc_gpio is end entity tb_soc_gpio; architecture testbench of tb_soc_gpio is -- Clock signal: signal clk : std_logic := '0'; constant clk_period : time := 10 ns; -- Reset signal: signal reset : std_logic := '1'; -- GPIOs: signal gpio : std_logic_vector(31 downto 0); -- Wishbone bus: signal wb_adr_in : std_logic_vector(11 downto 0) := (others => '0'); signal wb_dat_in : std_logic_vector(31 downto 0) := (others => '0'); signal wb_dat_out : std_logic_vector(31 downto 0); signal wb_cyc_in : std_logic := '0'; signal wb_stb_in : std_logic := '0'; signal wb_we_in : std_logic := '0'; signal wb_ack_out : std_logic; begin uut: entity work.pp_soc_gpio generic map( NUM_GPIOS => 32 ) port map( clk => clk, reset => reset, gpio => gpio, wb_adr_in => wb_adr_in, wb_dat_in => wb_dat_in, wb_dat_out => wb_dat_out, wb_cyc_in => wb_cyc_in, wb_stb_in => wb_stb_in, wb_we_in => wb_we_in, wb_ack_out => wb_ack_out ); clock: process begin clk <= '1'; wait for clk_period / 2; clk <= '0'; wait for clk_period / 2; end process clock; stimulus: process begin wait for clk_period * 2; reset <= '0'; -- Set the upper half of the GPIOs as inputs, the rest as outputs: wb_dat_in <= x"0000ffff"; wb_adr_in <= x"008"; wb_we_in <= '1'; wb_cyc_in <= '1'; wb_stb_in <= '1'; wait until wb_ack_out = '1'; wait for clk_period; wb_stb_in <= '0'; wb_cyc_in <= '0'; wb_we_in <= '0'; wait for clk_period; -- Set the outputs to aa, see if the upper half gets ignored correctly: wb_dat_in <= x"aaaaaaaa"; wb_adr_in <= x"004"; wb_we_in <= '1'; wb_cyc_in <= '1'; wb_stb_in <= '1'; wait until wb_ack_out = '1'; wait for clk_period; wb_stb_in <= '0'; wb_cyc_in <= '0'; wb_we_in <= '0'; wait for clk_period; wait; end process stimulus; end architecture testbench; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SC0720 is Port ( -- -- External I2C -- ext_sda_i : in std_logic; ext_sda_o : out std_logic; ext_sda_t : out std_logic; ext_scl_i : in std_logic; ext_scl_o : out std_logic; ext_scl_t : out std_logic; -- -- -- PHY_LED0: out std_logic; PHY_LED1: out std_logic; PHY_LED2: out std_logic; -- -- Connect to same name PL pin -- PL_pin_K16 : in std_logic; -- PUDC PL_pin_K19 : in std_logic; -- XCLK PL_pin_L16 : out std_logic; -- X1 SCL out PL_pin_M15 : in std_logic; -- X2 PL_pin_N15 : in std_logic; -- X3 PL_pin_P16 : in std_logic; -- X4 PL_pin_P22 : in std_logic; -- X5 SDA in PL_pin_K20 : out std_logic; -- X6 PL_pin_N22 : out std_logic; -- X7 SDA out -- -- Connect to EMIO I2C1 -- sda_i : out std_logic; sda_o : in std_logic; sda_t : in std_logic; scl_i : out std_logic; scl_o : in std_logic; scl_t : in std_logic ); end SC0720; architecture Behavioral of SC0720 is signal sda: std_logic; signal scl: std_logic; begin PL_pin_K20 <= '0'; -- TE0720-00 compat! -- I2C bus merger ext_sda_o <= sda_o; ext_sda_t <= sda_t; ext_scl_t <= scl_t; -- SDA readback from SC to I2C core sda_i <= PL_pin_P22 and ext_sda_i; -- SDA/SCL pass through to SC PL_pin_N22 <= sda; PL_pin_L16 <= scl; -- internal signals sda <= sda_o or sda_t; scl <= scl_o or scl_t; -- SCL feedback to I2C core scl_i <= scl; -- -- -- PHY_LED0 <= PL_pin_M15; PHY_LED1 <= PL_pin_N15; PHY_LED2 <= PL_pin_P16; end Behavioral; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity clk_baseclk_base_clk_wiz is port ( clk_raw : in STD_LOGIC; clk_250MHz : out STD_LOGIC; locked : out STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of clk_baseclk_base_clk_wiz : entity is "clk_base_clk_wiz"; end clk_baseclk_base_clk_wiz; architecture STRUCTURE of clk_baseclk_base_clk_wiz is signal clk_250MHz_clk_base : STD_LOGIC; signal clk_raw_clk_base : STD_LOGIC; signal clkfbout_buf_clk_base : STD_LOGIC; signal clkfbout_clk_base : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); attribute box_type : string; attribute box_type of clkf_buf : label is "PRIMITIVE"; attribute CAPACITANCE : string; attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; attribute IBUF_DELAY_VALUE : string; attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; attribute IFD_DELAY_VALUE : string; attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; attribute box_type of clkin1_ibufg : label is "PRIMITIVE"; attribute box_type of clkout1_buf : label is "PRIMITIVE"; attribute box_type of mmcm_adv_inst : label is "PRIMITIVE"; begin clkf_buf: unisim.vcomponents.BUFG port map ( I => clkfbout_clk_base, O => clkfbout_buf_clk_base ); clkin1_ibufg: unisim.vcomponents.IBUF generic map( IOSTANDARD => "DEFAULT" ) port map ( I => clk_raw, O => clk_raw_clk_base ); clkout1_buf: unisim.vcomponents.BUFG port map ( I => clk_250MHz_clk_base, O => clk_250MHz ); mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV generic map( BANDWIDTH => "OPTIMIZED", CLKFBOUT_MULT_F => 10.000000, CLKFBOUT_PHASE => 0.000000, CLKFBOUT_USE_FINE_PS => false, CLKIN1_PERIOD => 10.000000, CLKIN2_PERIOD => 0.000000, CLKOUT0_DIVIDE_F => 4.000000, CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, CLKOUT0_USE_FINE_PS => false, CLKOUT1_DIVIDE => 1, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, CLKOUT1_USE_FINE_PS => false, CLKOUT2_DIVIDE => 1, CLKOUT2_DUTY_CYCLE => 0.500000, CLKOUT2_PHASE => 0.000000, CLKOUT2_USE_FINE_PS => false, CLKOUT3_DIVIDE => 1, CLKOUT3_DUTY_CYCLE => 0.500000, CLKOUT3_PHASE => 0.000000, CLKOUT3_USE_FINE_PS => false, CLKOUT4_CASCADE => false, CLKOUT4_DIVIDE => 1, CLKOUT4_DUTY_CYCLE => 0.500000, CLKOUT4_PHASE => 0.000000, CLKOUT4_USE_FINE_PS => false, CLKOUT5_DIVIDE => 1, CLKOUT5_DUTY_CYCLE => 0.500000, CLKOUT5_PHASE => 0.000000, CLKOUT5_USE_FINE_PS => false, CLKOUT6_DIVIDE => 1, CLKOUT6_DUTY_CYCLE => 0.500000, CLKOUT6_PHASE => 0.000000, CLKOUT6_USE_FINE_PS => false, COMPENSATION => "ZHOLD", DIVCLK_DIVIDE => 1, IS_CLKINSEL_INVERTED => '0', IS_PSEN_INVERTED => '0', IS_PSINCDEC_INVERTED => '0', IS_PWRDWN_INVERTED => '0', IS_RST_INVERTED => '0', REF_JITTER1 => 0.010000, REF_JITTER2 => 0.000000, SS_EN => "FALSE", SS_MODE => "CENTER_HIGH", SS_MOD_PERIOD => 10000, STARTUP_WAIT => false ) port map ( CLKFBIN => clkfbout_buf_clk_base, CLKFBOUT => clkfbout_clk_base, CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, CLKIN1 => clk_raw_clk_base, CLKIN2 => '0', CLKINSEL => '1', CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, CLKOUT0 => clk_250MHz_clk_base, CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, DADDR(6) => '0', DADDR(5) => '0', DADDR(4) => '0', DADDR(3) => '0', DADDR(2) => '0', DADDR(1) => '0', DADDR(0) => '0', DCLK => '0', DEN => '0', DI(15) => '0', DI(14) => '0', DI(13) => '0', DI(12) => '0', DI(11) => '0', DI(10) => '0', DI(9) => '0', DI(8) => '0', DI(7) => '0', DI(6) => '0', DI(5) => '0', DI(4) => '0', DI(3) => '0', DI(2) => '0', DI(1) => '0', DI(0) => '0', DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, DWE => '0', LOCKED => locked, PSCLK => '0', PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, PSEN => '0', PSINCDEC => '0', PWRDWN => '0', RST => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity clk_base is port ( clk_raw : in STD_LOGIC; clk_250MHz : out STD_LOGIC; locked : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of clk_base : entity is true; attribute core_generation_info : string; attribute core_generation_info of clk_base : entity is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; end clk_base; architecture STRUCTURE of clk_base is begin U0: entity work.clk_baseclk_base_clk_wiz port map ( clk_250MHz => clk_250MHz, clk_raw => clk_raw, locked => locked ); end STRUCTURE; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library std; use std.textio.all; library work; use work.all; use work.procedures.all; entity tb_mp_indirect_fetch is end tb_mp_indirect_fetch; architecture behav of tb_mp_indirect_fetch is signal rst : std_logic := '1'; signal clk : std_logic := '0'; signal start : std_logic := '0'; signal cmd_in : t_vliw := empty_vliw; signal arg_in : t_data_array(4 downto 0) := (others => (others => '0')); signal mem_addr : std_logic_vector(9 downto 0) := (others => '0'); signal mem_rd : std_logic := '0'; signal mem_data : t_data := (others => '0'); signal arg_out : t_data_array(4 downto 0) := (others => (others => '0')); signal val_out : t_data_array(4 downto 0) := (others => (others => '0')); signal cmd_out : t_vliw := empty_vliw; signal busy : std_logic := '0'; signal finished : std_logic := '0'; begin clock: process begin clk <= '0', '1' after 10 ns; wait for 20 ns; end process clock; process(clk) variable i : unsigned(7 downto 0) := (others => '0'); begin if rising_edge(clk) then if rst = '1' then i := (others => '0'); else i := i + 1; mem_data <= std_logic_vector(i); end if; end if; end process; process variable l : line; begin wait for 10 ns; wait for 40 ns; rst <= '0'; cmd_in.last_val <= '0'; cmd_in.arg_assign <= (0 => "000", 1 => "001", 2 => "010", 3 => "011", 4 => "100"); cmd_in.mem_fetch <= (others => '0'); cmd_in.mem_memchunk <= (others => "00"); arg_in <= ( X"01", X"02", X"03", X"04", X"05"); start <= '1'; wait for 20 ns; start <= '0'; wait for 40 ns; arg_in <= ( X"02", X"03", X"04", X"05", X"06"); start <= '1'; wait for 20 ns; arg_in <= ( X"03", X"04", X"05", X"06", X"07"); wait for 20 ns; start <= '0'; wait for 80 ns; cmd_in.last_val <= '0'; cmd_in.arg_assign <= (0 => "000", 1 => "001", 2 => "010", 3 => "011", 4 => "100"); cmd_in.mem_fetch <= (others => '1'); cmd_in.mem_memchunk <= (0 => "00", 1 => "01", 2 => "10", 3 => "11", 4 => "00"); arg_in <= ( X"01", X"02", X"03", X"04", X"05"); start <= '1'; wait for 20 ns; start <= '0'; wait for 160 ns; cmd_in.last_val <= '1'; cmd_in.arg_assign <= (0 => "000", 1 => "001", 2 => "010", 3 => "011", 4 => "100"); cmd_in.mem_fetch <= (others => '0'); cmd_in.mem_memchunk <= (others => "00"); arg_in <= ( X"01", X"02", X"03", X"04", X"05"); start <= '1'; wait for 20 ns; start <= '0'; wait for 160 ns; cmd_in.last_val <= '0'; cmd_in.arg_assign <= (3 => "000", 0 => "001", 2 => "010", 1 => "011", 4 => "100"); cmd_in.mem_fetch <= (0 => '1', 1 => '1', others => '0'); cmd_in.mem_memchunk <= (0 => "00", 1 => "01", others => "00"); arg_in <= ( X"01", X"02", X"03", X"04", X"05"); start <= '1'; wait for 20 ns; start <= '0'; wait for 160 ns; assert false report "stop" severity failure; end process; mp_indirect_fetch_i: entity work.mp_indirect_fetch port map( rst => rst, clk => clk, start => start, cmd_in => cmd_in, arg_in => arg_in, mem_addr => mem_addr, mem_rd => mem_rd, mem_data => mem_data, arg_out => arg_out, val_out => val_out, cmd_out => cmd_out, busy => busy, finished => finished ); end behav; |
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned; use IEEE.NUMERIC_STD.ALL; package VHDL_lib is function next_power_2(len: positive) return positive; function char2int(arg : character) return natural; function test_factor(input:std_logic_vector; value: integer; factor: integer) return boolean; function char2std(arg : character) return std_logic_vector; function log2 (x : positive) return natural; function scale_log(input:std_logic_vector; max: integer) return std_logic_vector; component fft is generic( vga_width:integer := 1920; vga_height:integer := 1200; input_size:integer := 16 ); port( clk: in std_logic; input: in std_logic_vector(input_size-1 downto 0); valid: out std_logic; index: out std_logic_vector(log2(vga_width)-1 downto 0); output: out std_logic_vector(log2(vga_height)-1 downto 0) ); end component; component prn32 is generic( n: integer:= 4; seed: std_logic_vector:= X"12345678" ); port( clk: in std_logic; pn_val: out std_logic_vector(n-1 downto 0) ); end component; component audio is generic( bits_per_ch:integer := 24 ); port( clk: in std_logic; mclk: out std_logic; bclk: out std_logic; lrclk: out std_logic; adc_sdata: in std_logic; dac_sdata: out std_logic; input: in std_logic_vector(bits_per_ch-1 downto 0) ); end component; component pwm is Generic ( width:integer := 25; size:integer := 50000000 ); Port ( clk: in std_logic; duty: in std_logic_vector(width-1 downto 0); output: out std_logic ); end component; component audio_i2c_drv is port( clk: in std_logic; data: out std_logic_vector(31 downto 0); ready: in std_logic; valid: out std_logic ); end component; component spi is port( clk: in std_logic; data: in std_logic_vector(31 downto 0); ready: out std_logic; valid: in std_logic; clatch: out std_logic; cclk: out std_logic; cdata: out std_logic ); end component; component i2c is port( clk: in std_logic; data: in std_logic_vector(31 downto 0); ready: out std_logic; valid: in std_logic; sck: inout std_logic; sda: inout std_logic ); end component; component mux is generic( size:integer := 4 ); port ( s : in std_logic_vector(log2(size)-1 downto 0); input : in std_logic_vector(size-1 downto 0); output : out std_logic ); end component; component delayer is generic( width:integer := 8; stages:integer := 2 ); port( clk: in std_logic; input: in std_logic_vector(width-1 downto 0); output: out std_logic_vector(width-1 downto 0) ); end component; component truncate is generic( size_in:integer := 10; size_out:integer := 10 ); port( clk: std_logic; input: in std_logic_vector(size_in-1 downto 0); output: out std_logic_vector(size_out-1 downto 0) ); end component; component pulser is generic( delay:integer := 500000 ); port( clk: in std_logic; enable: in std_logic; output: out std_logic ); end component; component xor_gate is generic ( width:integer := 2 ); port ( input : in std_logic_vector(width-1 downto 0); output : out std_logic ); end component; component ascii_table is port( input: in std_logic_vector(7 downto 0); output: out std_logic_vector(40-1 downto 0) ); end component; component cro is generic( vga_width:integer := 1920; vga_height:integer := 1200 ); Port ( clk_250MHz : in std_logic; clk_100MHz : in STD_LOGIC; ch1_x: in STD_LOGIC_VECTOR(log2(vga_width)-1 downto 0); ch1_y: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0); ch1_update: in STD_LOGIC; ch2_x: in STD_LOGIC_VECTOR(log2(vga_width)-1 downto 0); ch2_y: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0); ch2_update: in STD_LOGIC; VGA_DATA : out STD_LOGIC_VECTOR (11 downto 0); VGA_HSYNC : out STD_LOGIC; VGA_VSYNC : out STD_LOGIC ); end component; component and_gate is generic ( width:integer := 2 ); port ( input : in std_logic_vector(width-1 downto 0); output : out std_logic ); end component; component multi_mux is generic( size:integer := 4; width:integer := 2 ); port ( s : in std_logic_vector(log2(size)-1 downto 0); input : in std_logic_vector((width*size)-1 downto 0); output : out std_logic_vector(width-1 downto 0) ); end component; component running_avg is generic( size:integer := 11 ); port( clk: in std_logic; input: in std_logic_vector(size-1 downto 0); output: out std_logic_vector(size-1 downto 0) ); end component; component FULL_ADDER is port ( A,B,CIN : in std_logic; SUM,CARRY : out std_logic ); end component; component debounce is generic( delay:integer := 50000 ); port( clk: in std_logic; input: in std_logic; output: out std_logic ); end component; component n_register is generic ( width:integer := 8 ); port ( input : in std_logic_vector(width-1 downto 0); output : out std_logic_vector(width-1 downto 0); clk : in std_logic; rst : in std_logic ); end component; component clk_div is generic( div:integer := 8 ); port( input: in std_logic; output: out std_logic; state: out std_logic_vector(log2(div/2)-1 downto 0) ); end component; component adc is port ( clk_250MHz : in std_logic; adc_clk_in_p: in std_logic; adc_clk_in_n: in std_logic; adc_data_in_p: in std_logic_vector(7 downto 0); adc_data_in_n: in std_logic_vector(7 downto 0); adc_data: out std_logic_vector(15 downto 0) ); end component; component vga is generic( Hsync:integer := 208; Hact:integer := 1920; Hfp:integer := 128; Hbp:integer := 336; Vsync:integer := 3; Vact:integer := 1200; Vfp:integer := 1; Vbp:integer := 38 ); port( clk: in std_logic; hscnt: out std_logic_vector(11 downto 0); vscnt: out std_logic_vector(11 downto 0); hspulse: out std_logic; vspulse: out std_logic ); end component; component bitshift_div is generic( scale_size:integer := 3; size:integer := 10 ); port( scale: in std_logic_vector(scale_size-1 downto 0); input: in std_logic_vector(size-1 downto 0); output: out std_logic_vector(size-1 downto 0) ); end component; component HALF_ADDER is port ( A,B : in std_logic; SUM,CARRY : out std_logic ); end component; component dmod is generic( width:integer := 16 ); port( clk: in std_logic; I: in std_logic_vector(width-1 downto 0); Q: in std_logic_vector(width-1 downto 0); output: out std_logic_vector(width-1 downto 0) ); end component; component audio_spi_drv is port( clk: in std_logic; data: out std_logic_vector(31 downto 0); ready: in std_logic; valid: out std_logic ); end component; component or_gate is generic ( width:integer := 2 ); port ( input : in std_logic_vector(width-1 downto 0); output : out std_logic ); end component; component modn is generic( size:integer := 4 ); port ( clk : in std_logic; output : out std_logic_vector(log2(size)-1 downto 0) ); end component; component trigger is generic( vga_width:integer := 1280; vga_height:integer := 1024 ); Port ( clk : in STD_LOGIC; input: in STD_LOGIC_VECTOR(log2(vga_height)-1 downto 0); valid: out STD_LOGIC; output: out STD_LOGIC_VECTOR(log2(vga_width)-1 downto 0) ); end component; end; package body VHDL_lib is function next_power_2(len: positive) return positive is variable n: positive; begin n := 1; while n <= len loop n := n * 2; end loop; return n; end; function char2int(arg : character) return natural is begin return character'pos(arg); end char2int; function test_factor(input:std_logic_vector; value: integer; factor: integer) return boolean is variable result: boolean := false; begin for f in 0 to factor loop if(to_integer(unsigned(input)) = (f*value)/factor )then result := true; end if; end loop; return result; end; function char2std(arg : character) return std_logic_vector is begin return std_logic_vector(to_unsigned(char2int(arg), 8)); end char2std; function log2 (x : positive) return natural is variable i : natural; begin i := 0; while (2**i < x) and i < 31 loop i := i + 1; end loop; return i; end function; function scale_log(input:std_logic_vector; max: integer) return std_logic_vector is constant level : integer := max/input'high; variable result: integer := 0; begin for i in input'range loop if input(i) = '1' then result := i; exit; end if; end loop; return std_logic_vector(to_signed(result*level,log2(max))); end; end; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library uvvm_util; context uvvm_util.uvvm_util_context; library uvvm_vvc_framework; use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all; library bitvis_vip_scoreboard; use bitvis_vip_scoreboard.generic_sb_support_pkg.all; use work.axilite_bfm_pkg.all; use work.vvc_cmd_pkg.all; use work.td_target_support_pkg.all; use work.transaction_pkg.all; package vvc_methods_pkg is --=============================================================================================== -- Types and constants for the AXILITE VVC --=============================================================================================== constant C_VVC_NAME : string := "AXILITE_VVC"; signal AXILITE_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME); alias THIS_VVCT : t_vvc_target_record is AXILITE_VVCT; alias t_bfm_config is t_axilite_bfm_config; type t_executor_result is record cmd_idx : natural; -- from UVVM handshake mechanism data : std_logic_vector(127 downto 0); value_is_new : boolean; -- turn true/false for put/fetch fetch_is_accepted : boolean; end record; type t_executor_result_array is array (natural range <>) of t_executor_result; -- Type found in UVVM-Util types_pkg constant C_AXILITE_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := ( delay_type => NO_DELAY, delay_in_time => 0 ns, inter_bfm_delay_violation_severity => WARNING ); type t_vvc_config is record inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay. cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR. cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if command queue is almost full. Will be ignored if set to 0. cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full. result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if result queue is almost full. Will be ignored if set to 0. result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold bfm_config : t_axilite_bfm_config; -- Configuration for AXI4-Lite BFM. See quick reference for AXI4-Lite BFM msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel parent_msg_id_panel : t_msg_id_panel; -- UVVM: temporary fix for HVVC, remove in v3.0 force_single_pending_transaction : boolean; -- Waits until the previous transaction is completed before starting the next one end record; type t_vvc_config_array is array (natural range <>) of t_vvc_config; constant C_AXILITE_VVC_CONFIG_DEFAULT : t_vvc_config := ( inter_bfm_delay => C_AXILITE_INTER_BFM_DELAY_DEFAULT, cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX, cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD, cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY, result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX, result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY, result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD, bfm_config => C_AXILITE_BFM_CONFIG_DEFAULT, msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT, parent_msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT, force_single_pending_transaction => false ); type t_vvc_status is record current_cmd_idx : natural; previous_cmd_idx : natural; pending_cmd_cnt : natural; end record; type t_vvc_status_array is array (natural range <>) of t_vvc_status; constant C_VVC_STATUS_DEFAULT : t_vvc_status := ( current_cmd_idx => 0, previous_cmd_idx => 0, pending_cmd_cnt => 0 ); -- Transaction information for the wave view during simulation type t_transaction_info is record operation : t_operation; addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0); data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0); byte_enable : std_logic_vector(C_VVC_CMD_BYTE_ENABLE_MAX_LENGTH-1 downto 0); msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH); end record; type t_transaction_info_array is array (natural range <>) of t_transaction_info; constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := ( operation => NO_OPERATION, addr => (others => '0'), data => (others => '0'), byte_enable => (others => '1'), msg => (others => ' ') ); shared variable shared_axilite_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_AXILITE_VVC_CONFIG_DEFAULT); shared variable shared_axilite_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_VVC_STATUS_DEFAULT); shared variable shared_axilite_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_TRANSACTION_INFO_DEFAULT); -- Scoreboard package axilite_sb_pkg is new bitvis_vip_scoreboard.generic_sb_pkg generic map (t_element => std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0), element_match => std_match, to_string_element => to_string); use axilite_sb_pkg.all; shared variable AXILITE_VVC_SB : axilite_sb_pkg.t_generic_sb; --========================================================================================== -- Methods dedicated to this VVC -- - These procedures are called from the testbench in order for the VVC to execute -- BFM calls towards the given interface. The VVC interpreter will queue these calls -- and then the VVC executor will fetch the commands from the queue and handle the -- actual BFM execution. -- For details on how the BFM procedures work, see the QuickRef. --========================================================================================== procedure axilite_write( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant addr : in unsigned; constant data : in std_logic_vector; constant byte_enable : in std_logic_vector; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ); procedure axilite_write( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant addr : in unsigned; constant data : in std_logic_vector; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ); procedure axilite_read( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant addr : in unsigned; constant data_routing : in t_data_routing; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ); procedure axilite_read( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant addr : in unsigned; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ); procedure axilite_check( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant addr : in unsigned; constant data : in std_logic_vector; constant msg : in string; constant alert_level : in t_alert_level := ERROR; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ); --============================================================================== -- Transaction info methods --============================================================================== procedure set_global_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ); procedure set_arw_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ); procedure set_w_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ); procedure set_b_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ); procedure set_r_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ); procedure reset_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record ); procedure reset_arw_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record ); procedure reset_w_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group ); procedure reset_b_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group ); procedure reset_r_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group ); --============================================================================== -- VVC Activity --============================================================================== procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic; variable vvc_status : inout t_vvc_status; constant activity : in t_activity; constant entry_num_in_vvc_activity_register : in integer; constant last_cmd_idx_executed : in natural; constant command_queue_is_empty : in boolean; constant scope : in string := C_VVC_NAME); --============================================================================== -- VVC Scoreboard helper method --============================================================================== function pad_axilite_sb( constant data : in std_logic_vector ) return std_logic_vector; end package vvc_methods_pkg; package body vvc_methods_pkg is --============================================================================== -- Methods dedicated to this VVC -- Notes: -- - shared_vvc_cmd is initialised to C_VVC_CMD_DEFAULT, and also reset to this after every command --============================================================================== procedure axilite_write( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant addr : in unsigned; constant data : in std_logic_vector; constant byte_enable : in std_logic_vector; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all & ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ", " & to_string(byte_enable, BIN, AS_IS, INCL_RADIX) & ")"; variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) := normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg)); variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); variable v_normalised_byte_ena : std_logic_vector(shared_vvc_cmd.byte_enable'length-1 downto 0) := normalize_and_check(byte_enable, shared_vvc_cmd.byte_enable, ALLOW_WIDER_NARROWER, "byte_enable", "shared_vvc_cmd.byte_enable", proc_call & " called with to wide byte_enable. " & add_msg_delimiter(msg)); variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, WRITE); shared_vvc_cmd.addr := v_normalised_addr; shared_vvc_cmd.data := v_normalised_data; shared_vvc_cmd.byte_enable := v_normalised_byte_ena; shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then v_msg_id_panel := parent_msg_id_panel; end if; send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel); end procedure; procedure axilite_write( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant addr : in unsigned; constant data : in std_logic_vector; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all & ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")"; variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) := normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg)); variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, WRITE); shared_vvc_cmd.addr := v_normalised_addr; shared_vvc_cmd.data := v_normalised_data; shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then v_msg_id_panel := parent_msg_id_panel; end if; send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel); end procedure; procedure axilite_read( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant addr : in unsigned; constant data_routing : in t_data_routing; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all & ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ")"; variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) := normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", msg); variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, READ); shared_vvc_cmd.addr := v_normalised_addr; shared_vvc_cmd.data_routing := data_routing; shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then v_msg_id_panel := parent_msg_id_panel; end if; send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel); end procedure; procedure axilite_read( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant addr : in unsigned; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ) is begin axilite_read(VVCT, vvc_instance_idx, addr, NA, msg, scope, parent_msg_id_panel); end procedure; procedure axilite_check( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant addr : in unsigned; constant data : in std_logic_vector; constant msg : in string; constant alert_level : in t_alert_level := ERROR; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all & ", " & to_string(addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")"; variable v_normalised_addr : unsigned(shared_vvc_cmd.addr'length-1 downto 0) := normalize_and_check(addr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", proc_call & " called with to wide address. " & add_msg_delimiter(msg)); variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) := normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg)); variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel; begin -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, CHECK); shared_vvc_cmd.addr := v_normalised_addr; shared_vvc_cmd.data := v_normalised_data; shared_vvc_cmd.alert_level := alert_level; shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then v_msg_id_panel := parent_msg_id_panel; end if; send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel); end procedure; --============================================================================== -- Transaction info methods --============================================================================== procedure set_global_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT) is begin case vvc_cmd.operation is when WRITE => vvc_transaction_info_group.bt_wr.operation := vvc_cmd.operation; vvc_transaction_info_group.bt_wr.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg; vvc_transaction_info_group.bt_wr.vvc_meta.cmd_idx := vvc_cmd.cmd_idx; vvc_transaction_info_group.bt_wr.transaction_status := IN_PROGRESS; when READ | CHECK => vvc_transaction_info_group.bt_rd.operation := vvc_cmd.operation; vvc_transaction_info_group.bt_rd.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg; vvc_transaction_info_group.bt_rd.vvc_meta.cmd_idx := vvc_cmd.cmd_idx; vvc_transaction_info_group.bt_rd.transaction_status := IN_PROGRESS; when others => alert(TB_ERROR, "VVC operation not recognized"); end case; gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER); wait for 0 ns; end procedure set_global_vvc_transaction_info; procedure set_arw_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ) is begin case vvc_cmd.operation is when WRITE => vvc_transaction_info_group.st_aw.operation := vvc_cmd.operation; vvc_transaction_info_group.st_aw.arwaddr := vvc_cmd.addr; vvc_transaction_info_group.st_aw.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg; vvc_transaction_info_group.st_aw.vvc_meta.cmd_idx := vvc_cmd.cmd_idx; vvc_transaction_info_group.st_aw.transaction_status := IN_PROGRESS; when READ | CHECK => vvc_transaction_info_group.st_ar.operation := vvc_cmd.operation; vvc_transaction_info_group.st_ar.arwaddr := vvc_cmd.addr; vvc_transaction_info_group.st_ar.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg; vvc_transaction_info_group.st_ar.vvc_meta.cmd_idx := vvc_cmd.cmd_idx; vvc_transaction_info_group.st_ar.transaction_status := IN_PROGRESS; when others => alert(TB_ERROR, "VVC operation not recognized"); end case; gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER); wait for 0 ns; end procedure set_arw_vvc_transaction_info; procedure set_w_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ) is begin vvc_transaction_info_group.st_w.operation := vvc_cmd.operation; vvc_transaction_info_group.st_w.wdata := vvc_cmd.data; vvc_transaction_info_group.st_w.wstrb := vvc_cmd.byte_enable; vvc_transaction_info_group.st_w.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg; vvc_transaction_info_group.st_w.vvc_meta.cmd_idx := vvc_cmd.cmd_idx; vvc_transaction_info_group.st_w.transaction_status := IN_PROGRESS; gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER); wait for 0 ns; end procedure set_w_vvc_transaction_info; procedure set_b_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ) is begin vvc_transaction_info_group.st_b.operation := vvc_cmd.operation; vvc_transaction_info_group.st_b.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg; vvc_transaction_info_group.st_b.vvc_meta.cmd_idx := vvc_cmd.cmd_idx; vvc_transaction_info_group.st_b.transaction_status := IN_PROGRESS; gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER); wait for 0 ns; end procedure set_b_vvc_transaction_info; procedure set_r_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ) is begin vvc_transaction_info_group.st_r.operation := vvc_cmd.operation; vvc_transaction_info_group.st_r.rdata := vvc_cmd.data; vvc_transaction_info_group.st_r.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg; vvc_transaction_info_group.st_r.vvc_meta.cmd_idx := vvc_cmd.cmd_idx; vvc_transaction_info_group.st_r.transaction_status := IN_PROGRESS; gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER); wait for 0 ns; end procedure set_r_vvc_transaction_info; procedure reset_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record) is begin case vvc_cmd.operation is when WRITE => if vvc_cmd.cmd_idx = vvc_transaction_info_group.bt_wr.vvc_meta.cmd_idx then vvc_transaction_info_group.bt_wr := C_BASE_TRANSACTION_SET_DEFAULT; end if; when READ | CHECK => if vvc_cmd.cmd_idx = vvc_transaction_info_group.bt_rd.vvc_meta.cmd_idx then vvc_transaction_info_group.bt_rd := C_BASE_TRANSACTION_SET_DEFAULT; end if; when others => null; end case; wait for 0 ns; end procedure reset_vvc_transaction_info; procedure reset_arw_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record ) is begin case vvc_cmd.operation is when WRITE => vvc_transaction_info_group.st_aw := C_ARW_TRANSACTION_DEFAULT; when READ | CHECK => vvc_transaction_info_group.st_ar := C_ARW_TRANSACTION_DEFAULT; when others => null; end case; wait for 0 ns; end procedure reset_arw_vvc_transaction_info; procedure reset_w_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group ) is begin vvc_transaction_info_group.st_w := C_W_TRANSACTION_DEFAULT; end procedure reset_w_vvc_transaction_info; procedure reset_b_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group ) is begin vvc_transaction_info_group.st_b := C_B_TRANSACTION_DEFAULT; end procedure reset_b_vvc_transaction_info; procedure reset_r_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group ) is begin vvc_transaction_info_group.st_r := C_R_TRANSACTION_DEFAULT; end procedure reset_r_vvc_transaction_info; --============================================================================== -- VVC Activity --============================================================================== procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic; variable vvc_status : inout t_vvc_status; constant activity : in t_activity; constant entry_num_in_vvc_activity_register : in integer; constant last_cmd_idx_executed : in natural; constant command_queue_is_empty : in boolean; constant scope : in string := C_VVC_NAME) is variable v_activity : t_activity := activity; begin -- Update vvc_status after a command has finished (during same delta cycle the activity register is updated) if activity = INACTIVE then vvc_status.previous_cmd_idx := last_cmd_idx_executed; vvc_status.current_cmd_idx := 0; end if; if v_activity = INACTIVE and not(command_queue_is_empty) then v_activity := ACTIVE; end if; shared_vvc_activity_register.priv_report_vvc_activity(vvc_idx => entry_num_in_vvc_activity_register, activity => v_activity, last_cmd_idx_executed => last_cmd_idx_executed); if global_trigger_vvc_activity_register /= 'L' then wait until global_trigger_vvc_activity_register = 'L'; end if; gen_pulse(global_trigger_vvc_activity_register, 0 ns, "pulsing global trigger for vvc activity register", scope, ID_NEVER); end procedure; --============================================================================== -- VVC Scoreboard helper method --============================================================================== function pad_axilite_sb( constant data : in std_logic_vector ) return std_logic_vector is begin return pad_sb_slv(data, C_VVC_CMD_DATA_MAX_LENGTH); end function pad_axilite_sb; end package body vvc_methods_pkg; |
library ieee; use ieee.std_logic_1164.all; library work; use work.fifo_synchronizer; use work.i2s_clkgen; use work.i2s_tx; use work.i2s_rx; entity i2s_controller is generic( C_SLOT_WIDTH : integer := 24; -- Width of one Slot C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge) C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge) C_NUM_CH : integer := 1; C_HAS_TX : integer := 1; C_HAS_RX : integer := 1 ); port( clk : in std_logic; -- System clock resetn : in std_logic; -- System reset data_clk : in std_logic; -- Data clock should be less than clk / 4 BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Bit Clock LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Frame Clock SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Output SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Input tx_enable : in Boolean; -- Enable TX tx_ack : out std_logic; -- Request new Slot Data tx_stb : in std_logic; -- Request new Slot Data tx_data : in std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data in rx_enable : in Boolean; -- Enable RX rx_ack : in std_logic; rx_stb : out std_logic; -- Valid Slot Data rx_data : out std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data out -- Runtime parameter bclk_div_rate : in natural range 0 to 255; lrclk_div_rate : in natural range 0 to 255 ); end i2s_controller; architecture Behavioral of i2s_controller is constant NUM_TX : integer := C_HAS_TX * C_NUM_CH; constant NUM_RX : integer := C_HAS_RX * C_NUM_CH; signal enable : Boolean; signal cdc_sync_stage0_tick : std_logic; signal cdc_sync_stage1_tick : std_logic; signal cdc_sync_stage2_tick : std_logic; signal cdc_sync_stage3_tick : std_logic; signal BCLK_O_int : std_logic; signal LRCLK_O_int : std_logic; signal tx_bclk : std_logic; signal tx_lrclk : std_logic; signal tx_sdata : std_logic_vector(C_NUM_CH - 1 downto 0); signal tx_tick : std_logic; signal tx_channel_sync : std_logic; signal tx_frame_sync : std_logic; signal const_1 : std_logic; signal bclk_tick : std_logic; signal rx_bclk : std_logic; signal rx_lrclk : std_logic; signal rx_sdata : std_logic_vector(NUM_RX - 1 downto 0); signal rx_channel_sync : std_logic; signal rx_frame_sync : std_logic; signal tx_sync_fifo_out : std_logic_vector(3 + NUM_TX downto 0); signal tx_sync_fifo_in : std_logic_vector(3 + NUM_TX downto 0); signal rx_sync_fifo_out : std_logic_vector(3 + NUM_RX downto 0); signal rx_sync_fifo_in : std_logic_vector(3 + NUM_RX downto 0); signal data_resetn : std_logic; signal data_reset_vec : std_logic_vector(2 downto 0); begin enable <= rx_enable or tx_enable; const_1 <= '1'; process (data_clk, resetn) begin if resetn = '0' then data_reset_vec <= (others => '1'); elsif rising_edge(data_clk) then data_reset_vec(2 downto 1) <= data_reset_vec(1 downto 0); data_reset_vec(0) <= '0'; end if; end process; data_resetn <= not data_reset_vec(2); -- Generate tick signal in the DATA_CLK_I domain process (data_clk) begin if rising_edge(data_clk) then cdc_sync_stage0_tick <= not cdc_sync_stage0_tick; end if; end process; process (clk) begin if rising_edge(clk) then cdc_sync_stage1_tick <= cdc_sync_stage0_tick; cdc_sync_stage2_tick <= cdc_sync_stage1_tick; cdc_sync_stage3_tick <= cdc_sync_stage2_tick; end if; end process; tx_tick <= cdc_sync_stage2_tick xor cdc_sync_stage3_tick; tx_sync_fifo_in(0) <= tx_channel_sync; tx_sync_fifo_in(1) <= tx_frame_sync; tx_sync_fifo_in(2) <= tx_bclk; tx_sync_fifo_in(3) <= tx_lrclk; tx_sync_fifo_in(3 + NUM_TX downto 4) <= tx_sdata; process (data_clk) begin if rising_edge(data_clk) then if data_resetn = '0' then BCLK_O <= (others => '1'); LRCLK_O <= (others => '1'); SDATA_O <= (others => '0'); else if C_BCLK_POL = 0 then BCLK_O <= (others => tx_sync_fifo_out(2)); else BCLK_O <= (others => not tx_sync_fifo_out(2)); end if; if C_LRCLK_POL = 0 then LRCLK_O <= (others => tx_sync_fifo_out(3)); else LRCLK_O <= (others => not tx_sync_fifo_out(3)); end if; if C_HAS_TX = 1 then SDATA_O <= tx_sync_fifo_out(3 + NUM_TX downto 4); end if; if C_HAS_RX = 1 then rx_sync_fifo_in(3 downto 0) <= tx_sync_fifo_out(3 downto 0); rx_sync_fifo_in(3 + NUM_RX downto 4) <= SDATA_I; end if; end if; end if; end process; tx_sync: entity fifo_synchronizer generic map ( DEPTH => 4, WIDTH => NUM_TX + 4 ) port map ( in_resetn => resetn, in_clk => clk, in_data => tx_sync_fifo_in, in_tick => tx_tick, out_resetn => data_resetn, out_clk => data_clk, out_data => tx_sync_fifo_out ); clkgen: entity i2s_clkgen port map( clk => clk, resetn => resetn, enable => enable, tick => tx_tick, bclk_div_rate => bclk_div_rate, lrclk_div_rate => lrclk_div_rate, channel_sync => tx_channel_sync, frame_sync => tx_frame_sync, bclk => tx_bclk, lrclk => tx_lrclk ); tx_gen: if C_HAS_TX = 1 generate tx: entity i2s_tx generic map ( C_SLOT_WIDTH => C_SLOT_WIDTH, C_NUM => NUM_TX ) port map ( clk => clk, resetn => resetn, enable => tx_enable, channel_sync => tx_channel_sync, frame_sync => tx_frame_sync, bclk => tx_bclk, sdata => tx_sdata, ack => tx_ack, stb => tx_stb, data => tx_data ); end generate; rx_gen: if C_HAS_RX = 1 generate rx: entity i2s_rx generic map ( C_SLOT_WIDTH => C_SLOT_WIDTH, C_NUM => NUM_RX ) port map ( clk => clk, resetn => resetn, enable => rx_enable, channel_sync => rx_channel_sync, frame_sync => rx_frame_sync, bclk => rx_bclk, sdata => rx_sdata, ack => rx_ack, stb => rx_stb, data => rx_data ); rx_channel_sync <= rx_sync_fifo_out(0); rx_frame_sync <= rx_sync_fifo_out(1); rx_bclk <= rx_sync_fifo_out(2); rx_lrclk <= rx_sync_fifo_out(3); rx_sdata <= rx_sync_fifo_out(3 + NUM_RX downto 4); rx_sync: entity fifo_synchronizer generic map ( DEPTH => 4, WIDTH => NUM_RX + 4 ) port map ( in_resetn => data_resetn, in_clk => data_clk, in_data => rx_sync_fifo_in, in_tick => const_1, out_resetn => resetn, out_clk => clk, out_data => rx_sync_fifo_out ); end generate; end Behavioral; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity RegisterBank is Port ( RAddr : in STD_LOGIC_VECTOR (3 downto 0); -- RBddr : in STD_LOGIC_VECTOR (3 downto 0); -- RWddr : in STD_LOGIC_VECTOR (3 downto 0); DATAIN : in STD_LOGIC_VECTOR (15 downto 0); clk : in STD_LOGIC; R : in STD_LOGIC; W : in STD_LOGIC; RAout : out STD_LOGIC_VECTOR (15 downto 0); -- RBout : out STD_LOGIC_VECTOR (15 downto 0)); -- end RegisterBank; architecture Behavioral of RegisterBank is signal R0dat, R1dat, R2dat, R3dat, R4dat, R5dat, R6dat, R7dat, R8dat, R9dat, R10dat, R11dat, R12dat, R13dat, R14dat, R15dat : STD_LOGIC_VECTOR(15 downto 0) := x"0000"; begin process(clk) -- Synchronous register bank begin if(rising_edge(clk) and R = '1') then -- Synchronous data read when read line enabled on rising edge (before write back) case RAddr is when x"0" => RAout <= R0dat; when x"1" => RAout <= R1dat; when x"2" => RAout <= R2dat; when x"3" => RAout <= R3dat; when x"4" => RAout <= R4dat; when x"5" => RAout <= R5dat; when x"6" => RAout <= R6dat; when x"7" => RAout <= R7dat; when x"8" => RAout <= R8dat; when x"9" => RAout <= R9dat; when x"A" => RAout <= R10dat; when x"B" => RAout <= R11dat; when x"C" => RAout <= R12dat; when x"D" => RAout <= R13dat; when x"E" => RAout <= R14dat; when x"F" => RAout <= R15dat; when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS end case; case RBddr is when x"0" => RBout <= R0dat; when x"1" => RBout <= R1dat; when x"2" => RBout <= R2dat; when x"3" => RBout <= R3dat; when x"4" => RBout <= R4dat; when x"5" => RBout <= R5dat; when x"6" => RBout <= R6dat; when x"7" => RBout <= R7dat; when x"8" => RBout <= R8dat; when x"9" => RBout <= R9dat; when x"A" => RBout <= R10dat; when x"B" => RBout <= R11dat; when x"C" => RBout <= R12dat; when x"D" => RBout <= R13dat; when x"E" => RBout <= R14dat; when x"F" => RBout <= R15dat; when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS end case; end if; if(falling_edge(clk) and W = '1') then -- Synchronous data latching when write line enabled (after data read) case RWddr is when x"0" => R0dat <= DATAIN; when x"1" => R1dat <= DATAIN; when x"2" => R2dat <= DATAIN; when x"3" => R3dat <= DATAIN; when x"4" => R4dat <= DATAIN; when x"5" => R5dat <= DATAIN; when x"6" => R6dat <= DATAIN; when x"7" => R7dat <= DATAIN; when x"8" => R8dat <= DATAIN; when x"9" => R9dat <= DATAIN; when x"A" => R10dat <= DATAIN; when x"B" => R11dat <= DATAIN; when x"C" => R12dat <= DATAIN; when x"D" => R13dat <= DATAIN; when x"E" => R14dat <= DATAIN; when x"F" => R15dat <= DATAIN; when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS end case; end if; end process; end Behavioral; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity tb_dds is end tb_dds; architecture tb of tb_dds is ----------------------------------------------------------------------- -- Timing constants ----------------------------------------------------------------------- constant CLOCK_PERIOD : time := 100 ns; constant T_HOLD : time := 10 ns; constant T_STROBE : time := CLOCK_PERIOD - (1 ns); ----------------------------------------------------------------------- -- DUT input signals ----------------------------------------------------------------------- -- General inputs signal aclk : std_logic := '0'; -- the master clock -- Phase slave channel signals signal s_axis_phase_tvalid : std_logic := '0'; -- payload is valid signal s_axis_phase_tdata : std_logic_vector(23 downto 0) := (others => '0'); -- data payload -- Data master channel signals signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid signal m_axis_data_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- data payload ----------------------------------------------------------------------- -- Aliases for AXI channel TDATA and TUSER fields -- These are a convenience for viewing data in a simulator waveform viewer. -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command -- to prevent the simulator optimizing away these signals. ----------------------------------------------------------------------- -- Phase slave channel alias signals signal s_axis_phase_tdata_inc : std_logic_vector(21 downto 0) := (others => '0'); -- Data master channel alias signals signal m_axis_data_tdata_cosine : std_logic_vector(15 downto 0) := (others => '0'); signal m_axis_data_tdata_sine : std_logic_vector(15 downto 0) := (others => '0'); signal end_of_simulation : boolean := false; begin ----------------------------------------------------------------------- -- Instantiate the DUT ----------------------------------------------------------------------- dut : entity work.dds port map ( aclk => aclk ,s_axis_phase_tvalid => s_axis_phase_tvalid ,s_axis_phase_tdata => s_axis_phase_tdata ,m_axis_data_tvalid => m_axis_data_tvalid ,m_axis_data_tdata => m_axis_data_tdata ); ----------------------------------------------------------------------- -- Generate clock ----------------------------------------------------------------------- clock_gen : process begin aclk <= '0'; if (end_of_simulation) then wait; else wait for CLOCK_PERIOD; loop aclk <= '0'; wait for CLOCK_PERIOD/2; aclk <= '1'; wait for CLOCK_PERIOD/2; end loop; end if; end process clock_gen; ----------------------------------------------------------------------- -- Generate inputs ----------------------------------------------------------------------- stimuli : process begin -- Drive inputs T_HOLD time after rising edge of clock wait until rising_edge(aclk); wait for T_HOLD; -- Input a constant phase increment each cycle, and run for long enough to produce 5 periods of outputs for cycle in 0 to 159 loop s_axis_phase_tvalid <= '1'; s_axis_phase_tdata <= (others => '0'); -- set unused TDATA bits to zero s_axis_phase_tdata(21 downto 0) <= "0000000000000000000000"; -- constant phase increment wait for CLOCK_PERIOD; end loop; s_axis_phase_tvalid <= '0'; -- End of test end_of_simulation <= true; report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure; wait; end process stimuli; ----------------------------------------------------------------------- -- Check outputs ----------------------------------------------------------------------- check_outputs : process variable check_ok : boolean := true; begin -- Check outputs T_STROBE time after rising edge of clock wait until rising_edge(aclk); wait for T_STROBE; -- Do not check the output payload values, as this requires the behavioral model -- which would make this demonstration testbench unwieldy. -- Instead, check the protocol of the data master channel: -- check that the payload is valid (not X) when TVALID is high if m_axis_data_tvalid = '1' then if is_x(m_axis_data_tdata) then report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error; check_ok := false; end if; end if; assert check_ok report "ERROR: terminating test with failures." severity failure; end process check_outputs; ----------------------------------------------------------------------- -- Assign TDATA fields to aliases, for easy simulator waveform viewing ----------------------------------------------------------------------- -- Phase slave channel alias signals s_axis_phase_tdata_inc <= s_axis_phase_tdata(21 downto 0); -- Data master channel alias signals: update these only when they are valid m_axis_data_tdata_cosine <= m_axis_data_tdata(15 downto 0) when m_axis_data_tvalid = '1'; m_axis_data_tdata_sine <= m_axis_data_tdata(31 downto 16) when m_axis_data_tvalid = '1'; end tb; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library uvvm_util; context uvvm_util.uvvm_util_context; package transaction_pkg is --=============================================================================================== -- t_operation -- - Bitvis defined operations --=============================================================================================== type t_operation is ( -- UVVM common NO_OPERATION, AWAIT_COMPLETION, AWAIT_ANY_COMPLETION, ENABLE_LOG_MSG, DISABLE_LOG_MSG, FLUSH_COMMAND_QUEUE, FETCH_RESULT, INSERT_DELAY, TERMINATE_CURRENT_COMMAND, -- Transaction WRITE, READ, CHECK, POLL_UNTIL); constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 32; constant C_VVC_CMD_ADDR_MAX_LENGTH : natural := 32; constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300; --========================================================================================== -- -- Transaction Info types, constants and global signal -- --========================================================================================== -- Transaction status type t_transaction_status is (INACTIVE, IN_PROGRESS, FAILED, SUCCEEDED); constant C_TRANSACTION_STATUS_DEFAULT : t_transaction_status := INACTIVE; -- VVC Meta type t_vvc_meta is record msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH); cmd_idx : integer; end record; constant C_VVC_META_DEFAULT : t_vvc_meta := ( msg => (others => ' '), cmd_idx => -1 ); -- Base transaction type type t_base_transaction is record operation : t_operation; address : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0); -- Max width may be increased if required data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0); vvc_meta : t_vvc_meta; transaction_status : t_transaction_status; end record; constant C_BASE_TRANSACTION_SET_DEFAULT : t_base_transaction := ( operation => NO_OPERATION, address => (others => '0'), data => (others => '0'), vvc_meta => C_VVC_META_DEFAULT, transaction_status => C_TRANSACTION_STATUS_DEFAULT ); -- Compound transaction type type t_compound_transaction is record operation : t_operation; address : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0); -- Max width may be increased if required data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0); randomisation : t_randomisation; num_words : natural; max_polls : integer; vvc_meta : t_vvc_meta; transaction_status : t_transaction_status; end record; constant C_COMPOUND_TRANSACTION_SET_DEFAULT : t_compound_transaction := ( operation => NO_OPERATION, address => (others => '0'), data => (others => '0'), randomisation => NA, num_words => 1, max_polls => 1, vvc_meta => C_VVC_META_DEFAULT, transaction_status => C_TRANSACTION_STATUS_DEFAULT ); -- Transaction group type t_transaction_group is record bt : t_base_transaction; ct : t_compound_transaction; end record; constant C_TRANSACTION_GROUP_DEFAULT : t_transaction_group := ( bt => C_BASE_TRANSACTION_SET_DEFAULT, ct => C_COMPOUND_TRANSACTION_SET_DEFAULT ); -- Global transaction info trigger signal type t_sbi_transaction_trigger_array is array (natural range <>) of std_logic; signal global_sbi_vvc_transaction_trigger : t_sbi_transaction_trigger_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => '0'); -- Type is defined as array to coincide with channel based VVCs type t_sbi_transaction_group_array is array (natural range <>) of t_transaction_group; -- Shared transaction info variable shared variable shared_sbi_vvc_transaction_info : t_sbi_transaction_group_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_TRANSACTION_GROUP_DEFAULT); end package transaction_pkg; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use work.VHDL_lib.all; entity prn32 is generic( n: integer:= 4; seed: std_logic_vector:= X"12345678" ); port( clk: in std_logic; pn_val: out std_logic_vector(n-1 downto 0) ); end prn32; architecture break_out of prn32 is signal pn: std_logic_vector(31 downto 0):= seed; begin pn_val <= pn(n-1 downto 0); random_gen: process(clk) variable fb: std_logic; variable fix: std_logic; begin if (clk'event and clk = '1') then fix := '1'; for i in 30 downto 0 loop fix := (not pn(i)) and fix; end loop; fb := pn(0) xor pn(1) xor pn(21) xor pn(31) xor fix; pn <= pn(30 downto 0) & fb; end if; end process; end break_out; |
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity contact_discoverybkb_ram is generic( mem_type : string := "block"; dwidth : integer := 8; awidth : integer := 13; mem_size : integer := 8192 ); port ( addr0 : in std_logic_vector(awidth-1 downto 0); ce0 : in std_logic; d0 : in std_logic_vector(dwidth-1 downto 0); we0 : in std_logic; q0 : out std_logic_vector(dwidth-1 downto 0); clk : in std_logic ); end entity; architecture rtl of contact_discoverybkb_ram is signal addr0_tmp : std_logic_vector(awidth-1 downto 0); type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0); shared variable ram : mem_array := (others=>(others=>'0')); attribute syn_ramstyle : string; attribute syn_ramstyle of ram : variable is "block_ram"; attribute ram_style : string; attribute ram_style of ram : variable is mem_type; attribute EQUIVALENT_REGISTER_REMOVAL : string; begin memory_access_guard_0: process (addr0) begin addr0_tmp <= addr0; if (CONV_INTEGER(addr0) > mem_size-1) then addr0_tmp <= (others => '0'); else addr0_tmp <= addr0; end if; end process; p_memory_access_0: process (clk) begin if (clk'event and clk = '1') then if (ce0 = '1') then if (we0 = '1') then ram(CONV_INTEGER(addr0_tmp)) := d0; end if; q0 <= ram(CONV_INTEGER(addr0_tmp)); end if; end if; end process; end rtl; Library IEEE; use IEEE.std_logic_1164.all; entity contact_discoverybkb is generic ( DataWidth : INTEGER := 8; AddressRange : INTEGER := 8192; AddressWidth : INTEGER := 13); port ( reset : IN STD_LOGIC; clk : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce0 : IN STD_LOGIC; we0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0); q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0)); end entity; architecture arch of contact_discoverybkb is component contact_discoverybkb_ram is port ( clk : IN STD_LOGIC; addr0 : IN STD_LOGIC_VECTOR; ce0 : IN STD_LOGIC; d0 : IN STD_LOGIC_VECTOR; we0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR); end component; begin contact_discoverybkb_ram_U : component contact_discoverybkb_ram port map ( clk => clk, addr0 => address0, ce0 => ce0, d0 => d0, we0 => we0, q0 => q0); end architecture; |
library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; entity light8080_tb0 is end entity light8080_tb0; architecture behavior of light8080_tb0 is constant T : time := 100 ns; constant MAX_SIM_LENGTH : time := T*7000; -- enough for the tb0 -- Component Declaration for the Unit Under Test (UUT) component light8080 port ( addr_out : out std_logic_vector(15 downto 0); inta : out std_logic; inte : out std_logic; halt : out std_logic; intr : in std_logic; vma : out std_logic; io : out std_logic; rd : out std_logic; wr : out std_logic; fetch : out std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); clk : in std_logic; reset : in std_logic ); end component; signal data_i : std_logic_vector(7 downto 0) := (others=>'0'); signal vma_o : std_logic; signal rd_o : std_logic; signal wr_o : std_logic; signal io_o : std_logic; signal data_o : std_logic_vector(7 downto 0); signal data_mem : std_logic_vector(7 downto 0); signal addr_o : std_logic_vector(15 downto 0); signal fetch_o : std_logic; signal inta_o : std_logic; signal inte_o : std_logic; signal intr_i : std_logic := '0'; signal halt_o : std_logic; signal reset : std_logic := '0'; signal clk : std_logic := '1'; signal done : std_logic := '0'; type t_rom is array(0 to 2047) of std_logic_vector(7 downto 0); signal rom : t_rom := ( X"31",X"f3",X"05",X"3e",X"77",X"e6",X"00",X"ca", X"0d",X"00",X"cd",X"e0",X"04",X"d2",X"13",X"00", X"cd",X"e0",X"04",X"ea",X"19",X"00",X"cd",X"e0", X"04",X"f2",X"1f",X"00",X"cd",X"e0",X"04",X"c2", X"2e",X"00",X"da",X"2e",X"00",X"e2",X"2e",X"00", X"fa",X"2e",X"00",X"c3",X"31",X"00",X"cd",X"e0", X"04",X"c6",X"06",X"c2",X"39",X"00",X"cd",X"e0", X"04",X"da",X"42",X"00",X"e2",X"42",X"00",X"f2", X"45",X"00",X"cd",X"e0",X"04",X"c6",X"70",X"e2", X"4d",X"00",X"cd",X"e0",X"04",X"fa",X"56",X"00", X"ca",X"56",X"00",X"d2",X"59",X"00",X"cd",X"e0", X"04",X"c6",X"81",X"fa",X"61",X"00",X"cd",X"e0", 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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00", X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00" ); signal irq_vector_byte: std_logic_vector(7 downto 0); signal irq_source : integer range 0 to 7; signal cycles_to_intr : integer range -10 to 255; signal int_vector_index : integer range 0 to 3; signal addr_vector_table: integer range 0 to 65535; begin -- Instantiate the Unit Under Test (UUT) uut: light8080 PORT MAP( clk => clk, reset => reset, vma => vma_o, rd => rd_o, wr => wr_o, io => io_o, fetch => fetch_o, addr_out => addr_o, data_in => data_i, data_out => data_o, intr => intr_i, inte => inte_o, inta => inta_o, halt => halt_o ); clock: process(done, clk) begin if done = '0' then clk <= not clk after T/2; end if; end process clock; main_test: process begin -- Assert reset for at least one full clk period reset <= '1'; wait until clk = '1'; wait for T/2; reset <= '0'; -- Remember to 'cut away' the preceding 3 clk semiperiods from -- the wait statement... wait for (MAX_SIM_LENGTH - T*1.5); -- Maximum sim time elapsed, assume the program ran away and -- stop the clk process asserting 'done' (which will stop the simulation) done <= '1'; assert (done = '1') report "Test timed out." severity failure; wait; end process main_test; synchronous_ram: process(clk) begin if (clk'event and clk='1') then data_mem <= rom(conv_integer(addr_o(10 downto 0))); if wr_o = '1' and addr_o(15 downto 11)="00000" then rom(conv_integer(addr_o(10 downto 0))) <= data_o; end if; end if; end process synchronous_ram; irq_trigger_register: process(clk) begin if (clk'event and clk='1') then if reset='1' then cycles_to_intr <= -10; -- meaning no interrupt pending intr_i <= '0'; else if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"11" then cycles_to_intr <= conv_integer(data_o) + 1; else if cycles_to_intr >= 0 then cycles_to_intr <= cycles_to_intr - 1; end if; if cycles_to_intr = 0 then intr_i <= '1'; else intr_i <= '0'; end if; end if; end if; end if; end process irq_trigger_register; irq_source_register: process(clk) begin if (clk'event and clk='1') then if reset='1' then irq_source <= 0; else if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"10" then irq_source <= conv_integer(data_o(2 downto 0)); end if; end if; end if; end process irq_source_register; irq_vector_table: process(clk) begin if (clk'event and clk='1') then if vma_o = '1' and rd_o='1' then if inta_o = '1' then int_vector_index <= int_vector_index + 1; else int_vector_index <= 0; end if; end if; -- this is the address of the byte we'll feed to the CPU addr_vector_table <= 64+irq_source*4+int_vector_index; end if; end process irq_vector_table; irq_vector_byte <= rom(addr_vector_table); data_i <= data_mem when inta_o='0' else irq_vector_byte; test_outcome_register: process(clk) variable outcome : std_logic_vector(7 downto 0); begin if (clk'event and clk='1') then if io_o='1' and wr_o='1' and addr_o(7 downto 0)=X"20" then assert (data_o /= X"55") report "Software reports SUCCESS" severity failure; assert (data_o /= X"aa") report "Software reports FAILURE" severity failure; assert ((data_o = X"aa") or (data_o = X"55")) report "Software reports unexpected outcome value." severity failure; end if; end if; end process test_outcome_register; end; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.VHDL_lib.all; entity mux is generic( size:integer := 4 ); port ( s : in std_logic_vector(log2(size)-1 downto 0); input : in std_logic_vector(size-1 downto 0); output : out std_logic ); end mux; architecture arch of mux is signal y : std_logic_vector(size-1 downto 0); signal z : std_logic_vector( ( size * (s'length+1) ) -1 downto 0); component or_gate is generic ( width:integer := 2 ); port ( input : in std_logic_vector(width-1 downto 0); output : out std_logic ); end component; component and_gate is generic ( width:integer := 2 ); port ( input : in std_logic_vector(width-1 downto 0); output : out std_logic ); end component; begin ORX: or_gate generic map(width=>size) port map(y,output); GEN_REG: for I in 0 to size-1 generate z(I*(s'length+1)+s'length downto I*(s'length+1)) <= (s xor std_logic_vector(to_unsigned(I,s'length))) & input(size-1-I); REGX : and_gate generic map(width=> s'length+1 ) port map ( z(I*(s'length+1)+s'length downto I*(s'length+1)) ,y(I) ); end generate ; end arch; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library uvvm_util; context uvvm_util.uvvm_util_context; library uvvm_vvc_framework; use uvvm_vvc_framework.ti_data_queue_pkg.all; package ti_data_fifo_pkg is shared variable shared_data_fifo : t_data_queue; ------------------------------------------ -- uvvm_fifo_init ------------------------------------------ -- This function allocates space in the buffer and returns an index that -- must be used to access the FIFO. -- -- - Parameters: -- - buffer_size_in_bits (natural) - The size of the FIFO -- -- - Returns: The index of the initiated FIFO (natural). -- Returns 0 on error. -- impure function uvvm_fifo_init( buffer_size_in_bits : natural ) return natural; ------------------------------------------ -- uvvm_fifo_init ------------------------------------------ -- This procedure allocates space in the buffer at the given buffer_idx. -- -- - Parameters: -- - buffer_idx - The index of the FIFO (natural) -- that shall be initialized. -- - buffer_size_in_bits (natural) - The size of the FIFO -- procedure uvvm_fifo_init( buffer_idx : natural; buffer_size_in_bits : natural ); ------------------------------------------ -- uvvm_fifo_put ------------------------------------------ -- This procedure puts data into a FIFO with index buffer_idx. -- The size of the data is unconstrained, meaning that -- it can be any size. Pushing data with a size that is -- larger than the FIFO size results in wrapping, i.e., -- that when reaching the end the data remaining will over- -- write the data that was written first. -- -- - Parameters: -- - buffer_idx - The index of the FIFO (natural) -- that shall be pushed to. -- - data - The data that shall be pushed (slv) -- procedure uvvm_fifo_put( buffer_idx : natural; data : std_logic_vector ); ------------------------------------------ -- uvvm_fifo_get ------------------------------------------ -- This function returns the data from the FIFO -- and removes the returned data from the FIFO. -- -- - Parameters: -- - buffer_idx - The index of the FIFO (natural) -- that shall be read. -- - entry_size_in_bits - The size of the returned slv (natural) -- -- - Returns: Data from the FIFO (slv). The size of the -- return data is given by the entry_size_in_bits parameter. -- Attempting to get() from an empty FIFO is allowed but triggers a -- TB_WARNING and returns garbage. -- Attempting to get() a larger value than the FIFO size is allowed -- but triggers a TB_WARNING. -- -- impure function uvvm_fifo_get( buffer_idx : natural; entry_size_in_bits : natural ) return std_logic_vector; ------------------------------------------ -- uvvm_fifo_flush ------------------------------------------ -- This procedure empties the FIFO given -- by buffer_idx. -- -- - Parameters: -- - buffer_idx - The index of the FIFO (natural) -- that shall be flushed. -- procedure uvvm_fifo_flush( buffer_idx : natural ); ------------------------------------------ -- uvvm_fifo_peek ------------------------------------------ -- This function returns the data from the FIFO -- without removing it. -- -- - Parameters: -- - buffer_idx - The index of the FIFO (natural) -- that shall be read. -- - entry_size_in_bits - The size of the returned slv (natural) -- -- - Returns: Data from the FIFO. The size of the -- return data is given by the entry_size_in_bits parameter. -- Attempting to peek from an empty FIFO is allowed but triggers a -- TB_WARNING and returns garbage. -- Attempting to peek a larger value than the FIFO size is allowed -- but triggers a TB_WARNING. Will wrap. -- -- impure function uvvm_fifo_peek( buffer_idx : natural; entry_size_in_bits : natural ) return std_logic_vector; ------------------------------------------ -- uvvm_fifo_get_count ------------------------------------------ -- This function returns a natural indicating the number of elements -- currently occupying the FIFO given by buffer_idx. -- -- - Parameters: -- - buffer_idx - The index of the FIFO (natural) -- -- - Returns: The number of elements occupying the FIFO (natural). -- -- impure function uvvm_fifo_get_count( buffer_idx : natural ) return natural; ------------------------------------------ -- uvvm_fifo_get_max_count ------------------------------------------ -- This function returns a natural indicating the maximum number -- of elements that can occupy the FIFO given by buffer_idx. -- -- - Parameters: -- - buffer_idx - The index of the FIFO (natural) -- -- - Returns: The maximum number of elements that can be placed -- in the FIFO (natural). -- -- impure function uvvm_fifo_get_max_count( buffer_idx : natural ) return natural; ------------------------------------------ -- uvvm_fifo_is_full ------------------------------------------ -- This function returns a boolean indicating if -- the FIFO is full or not. -- -- - Parameters: -- - buffer_idx - The index of the FIFO (natural) -- -- - Returns: TRUE if FIFO is full, else FALSE. -- -- impure function uvvm_fifo_is_full( buffer_idx : natural ) return boolean; end package ti_data_fifo_pkg; package body ti_data_fifo_pkg is impure function uvvm_fifo_init( buffer_size_in_bits : natural ) return natural is begin return shared_data_fifo.init_queue(buffer_size_in_bits, "UVVM_FIFO"); end function; procedure uvvm_fifo_init( buffer_idx : natural; buffer_size_in_bits : natural ) is begin shared_data_fifo.init_queue(buffer_idx, buffer_size_in_bits, "UVVM_FIFO"); end procedure; procedure uvvm_fifo_put( buffer_idx : natural; data : std_logic_vector ) is begin shared_data_fifo.push_back(buffer_idx, data); end procedure; impure function uvvm_fifo_get( buffer_idx : natural; entry_size_in_bits : natural ) return std_logic_vector is begin return shared_data_fifo.pop_front(buffer_idx, entry_size_in_bits); end function; procedure uvvm_fifo_flush( buffer_idx : natural ) is begin shared_data_fifo.flush(buffer_idx); end procedure; impure function uvvm_fifo_peek( buffer_idx : natural; entry_size_in_bits : natural ) return std_logic_vector is begin return shared_data_fifo.peek_front(buffer_idx, entry_size_in_bits); end function; impure function uvvm_fifo_get_count( buffer_idx : natural ) return natural is begin return shared_data_fifo.get_count(buffer_idx); end function; impure function uvvm_fifo_get_max_count( buffer_idx : natural ) return natural is begin return shared_data_fifo.get_queue_count_max(buffer_idx); end function; impure function uvvm_fifo_is_full( buffer_idx : natural ) return boolean is begin return shared_data_fifo.get_queue_is_full(buffer_idx); end function; end package body ti_data_fifo_pkg; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library std; use std.textio.all; library work; use work.all; use work.procedures.all; entity tb_mp_stage3 is end tb_mp_stage3; architecture behav of tb_mp_stage3 is signal clk : std_logic := '0'; signal rst : std_logic := '1'; signal cmd_in : t_vliw := empty_vliw; signal arg_in : t_data_array(4 downto 0) := (others => (others => '0')); signal val_in : t_data_array(4 downto 0) := (others => (others => '0')); signal arg_out : t_data_array(4 downto 0) := (others => (others => '0')); signal val_out : t_data_array(4 downto 0) := (others => (others => '0')); signal cmd_out : t_vliw := empty_vliw; type op_type is (op_noop, op_add, op_sub, op_sar, op_slr, op_and, op_or, op_xor); type op_arr is array(natural range <>) of op_type; signal op_lut : op_arr(7 downto 0) := ( 0 => op_noop, 1 => op_add, 2 => op_sub, 3 => op_sar, 4 => op_slr, 5 => op_and, 6 => op_or, 7 => op_xor); procedure prime_inputs(a0, a1, a2, a3, a4 : in integer; in1a, in1b, out1, in2a, in2b, out2: in integer; op1, op2 : in op_type; signal args : out t_data_array(4 downto 0); signal cmd : out t_vliw) is begin args(0) <= std_logic_vector(to_signed(a0, t_data'length)); args(1) <= std_logic_vector(to_signed(a1, t_data'length)); args(2) <= std_logic_vector(to_signed(a2, t_data'length)); args(3) <= std_logic_vector(to_signed(a3, t_data'length)); args(4) <= std_logic_vector(to_signed(a4, t_data'length)); for i in 7 downto 0 loop if op1 = op_lut(i) then cmd.s3_op1 <= std_logic_vector(to_unsigned(i, cmd.s3_op1'length)); end if; if op2 = op_lut(i) then cmd.s3_op2 <= std_logic_vector(to_unsigned(i, cmd.s3_op1'length)); end if; end loop; cmd.s3_in1a <= std_logic_vector(to_unsigned(in1a, cmd.s3_in1a'length)); cmd.s3_in1b <= std_logic_vector(to_unsigned(in1b, cmd.s3_in1b'length)); cmd.s3_out1 <= std_logic_vector(to_unsigned(out1, cmd.s3_out1'length)); cmd.s3_in2a <= std_logic_vector(to_unsigned(in2a, cmd.s3_in2a'length)); cmd.s3_in2b <= std_logic_vector(to_unsigned(in2b, cmd.s3_in2b'length)); cmd.s3_out2 <= std_logic_vector(to_unsigned(out2, cmd.s3_out2'length)); end procedure; begin clock: process begin clk <= '0', '1' after 10 ns; wait for 20 ns; end process clock; process variable l : line; begin wait for 10 ns; wait for 60 ns; rst <= '0'; prime_inputs(64, 10, 64, 0, 0, 0, 1, 0, 2, 3, 1, op_add, op_add, val_in, cmd_in); wait for 20 ns; prime_inputs(0, 45, 64, -64, 64, 4, 3, 0, 2, 1, 4, op_add, op_add, val_in, cmd_in); wait for 20 ns; prime_inputs(-15, 11, -45, 0, 0, 2, 0, 3, 2, 1, 4, op_add, op_add, val_in, cmd_in); -- 74 64 64 0 0 -- 0 45 64 -64 109 -- -15 11 -45 -60 -34 wait for 80 ns; assert false report "stop" severity failure; end process; mp_stage3_i: entity work.mp_stage3 port map( rst => rst, clk => clk, cmd_in => cmd_in, arg_in => arg_in, val_in => val_in, arg_out => arg_out, val_out => val_out, cmd_out => cmd_out ); end behav; |
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.pp_types.all; use work.pp_constants.all; use work.pp_utilities.all; use work.pp_csr.all; entity pp_core is generic( PROCESSOR_ID : std_logic_vector(31 downto 0) := x"00000000"; --! Processor ID. RESET_ADDRESS : std_logic_vector(31 downto 0) := x"00000000"; --! Address of the first instruction to execute. MTIME_DIVIDER : positive := 5; --! Divider for the clock driving the MTIME counter TIME_DIVIDER : positive := 5 --! Divider for the clock dirivng the TIME counter ); port( -- Control inputs: clk : in std_logic; --! Processor clock reset : in std_logic; --! Reset signal -- Instruction memory interface: imem_address : out std_logic_vector(31 downto 0); --! Address of the next instruction imem_data_in : in std_logic_vector(31 downto 0); --! Instruction input imem_req : out std_logic; imem_ack : in std_logic; -- Data memory interface: dmem_address : out std_logic_vector(31 downto 0); --! Data address dmem_data_in : in std_logic_vector(31 downto 0); --! Input from the data memory dmem_data_out : out std_logic_vector(31 downto 0); --! Ouptut to the data memory dmem_data_size : out std_logic_vector( 1 downto 0); --! Size of the data, 1 = 8 bits, 2 = 16 bits, 0 = 32 bits. dmem_read_req : out std_logic; --! Data memory read request dmem_read_ack : in std_logic; --! Data memory read acknowledge dmem_write_req : out std_logic; --! Data memory write request dmem_write_ack : in std_logic; --! Data memory write acknowledge -- Test interface: test_context_out : out test_context; --! Test context output. -- External interrupt input: irq : in std_logic_vector(7 downto 0) --! IRQ inputs. ); end entity pp_core; architecture behaviour of pp_core is ------- Flush signals ------- signal flush_if, flush_id, flush_ex : std_logic; ------- Stall signals ------- signal stall_if, stall_id, stall_ex, stall_mem : std_logic; -- Signals used to determine if an instruction should be counted -- by the instret counter: signal if_count_instruction, id_count_instruction : std_logic; signal ex_count_instruction, mem_count_instruction : std_logic; signal wb_count_instruction : std_logic; -- CSR read port signals: signal csr_read_data : std_logic_vector(31 downto 0); signal csr_read_address, csr_read_address_p : csr_address; -- Status register outputs: signal mtvec : std_logic_vector(31 downto 0); signal mie : std_logic_vector(31 downto 0); signal ie, ie1 : std_logic; -- Internal interrupt signals: signal software_interrupt, timer_interrupt : std_logic; -- Hazard detected in the execute stage: signal hazard_detected : std_logic; -- Branch targets: signal exception_target, branch_target : std_logic_vector(31 downto 0); signal branch_taken, exception_taken : std_logic; -- Register file read ports: signal rs1_address_p, rs2_address_p : register_address; signal rs1_address, rs2_address : register_address; signal rs1_data, rs2_data : std_logic_vector(31 downto 0); -- Data memory signals: signal dmem_address_p : std_logic_vector(31 downto 0); signal dmem_data_size_p : std_logic_vector(1 downto 0); signal dmem_data_out_p : std_logic_vector(31 downto 0); signal dmem_read_req_p : std_logic; signal dmem_write_req_p : std_logic; -- Fetch stage signals: signal if_instruction, if_pc : std_logic_vector(31 downto 0); signal if_instruction_ready : std_logic; -- Decode stage signals: signal id_funct3 : std_logic_vector(2 downto 0); signal id_rd_address : register_address; signal id_rd_write : std_logic; signal id_rs1_address : register_address; signal id_rs2_address : register_address; signal id_csr_address : csr_address; signal id_csr_write : csr_write_mode; signal id_csr_use_immediate : std_logic; signal id_shamt : std_logic_vector(4 downto 0); signal id_immediate : std_logic_vector(31 downto 0); signal id_branch : branch_type; signal id_alu_x_src, id_alu_y_src : alu_operand_source; signal id_alu_op : alu_operation; signal id_mem_op : memory_operation_type; signal id_mem_size : memory_operation_size; signal id_pc : std_logic_vector(31 downto 0); signal id_exception : std_logic; signal id_exception_cause : csr_exception_cause; -- Execute stage signals: signal ex_dmem_address : std_logic_vector(31 downto 0); signal ex_dmem_data_size : std_logic_vector(1 downto 0); signal ex_dmem_data_out : std_logic_vector(31 downto 0); signal ex_dmem_read_req : std_logic; signal ex_dmem_write_req : std_logic; signal ex_rd_address : register_address; signal ex_rd_data : std_logic_vector(31 downto 0); signal ex_rd_write : std_logic; signal ex_pc : std_logic_vector(31 downto 0); signal ex_csr_address : csr_address; signal ex_csr_write : csr_write_mode; signal ex_csr_data : std_logic_vector(31 downto 0); signal ex_branch : branch_type; signal ex_mem_op : memory_operation_type; signal ex_mem_size : memory_operation_size; signal ex_exception_context : csr_exception_context; -- Memory stage signals: signal mem_rd_write : std_logic; signal mem_rd_address : register_address; signal mem_rd_data : std_logic_vector(31 downto 0); signal mem_csr_address : csr_address; signal mem_csr_write : csr_write_mode; signal mem_csr_data : std_logic_vector(31 downto 0); signal mem_mem_op : memory_operation_type; signal mem_exception : std_logic; signal mem_exception_context : csr_exception_context; -- Writeback signals: signal wb_rd_address : register_address; signal wb_rd_data : std_logic_vector(31 downto 0); signal wb_rd_write : std_logic; signal wb_csr_address : csr_address; signal wb_csr_write : csr_write_mode; signal wb_csr_data : std_logic_vector(31 downto 0); signal wb_exception : std_logic; signal wb_exception_context : csr_exception_context; begin stall_if <= stall_id; stall_id <= stall_ex; stall_ex <= hazard_detected or stall_mem; stall_mem <= to_std_logic(memop_is_load(mem_mem_op) and dmem_read_ack = '0') or to_std_logic(mem_mem_op = MEMOP_TYPE_STORE and dmem_write_ack = '0'); flush_if <= (branch_taken or exception_taken) and not stall_if; flush_id <= (branch_taken or exception_taken) and not stall_id; flush_ex <= (branch_taken or exception_taken) and not stall_ex; ------- Control and status module ------- csr_unit: entity work.pp_csr_unit generic map( PROCESSOR_ID => PROCESSOR_ID, MTIME_DIVIDER => MTIME_DIVIDER, TIME_DIVIDER => TIME_DIVIDER ) port map( clk => clk, reset => reset, irq => irq, count_instruction => wb_count_instruction, test_context_out => test_context_out, read_address => csr_read_address, read_data_out => csr_read_data, write_address => wb_csr_address, write_data_in => wb_csr_data, write_mode => wb_csr_write, exception_context => wb_exception_context, exception_context_write => wb_exception, mie_out => mie, mtvec_out => mtvec, ie_out => ie, ie1_out => ie1, software_interrupt_out => software_interrupt, timer_interrupt_out => timer_interrupt ); csr_read_address <= id_csr_address when stall_ex = '0' else csr_read_address_p; store_previous_csr_addr: process(clk, stall_ex) begin if rising_edge(clk) and stall_ex = '0' then csr_read_address_p <= id_csr_address; end if; end process store_previous_csr_addr; ------- Register file ------- regfile: entity work.pp_register_file port map( clk => clk, rs1_addr => rs1_address, rs2_addr => rs2_address, rs1_data => rs1_data, rs2_data => rs2_data, rd_addr => wb_rd_address, rd_data => wb_rd_data, rd_write => wb_rd_write ); rs1_address <= id_rs1_address when stall_ex = '0' else rs1_address_p; rs2_address <= id_rs2_address when stall_ex = '0' else rs2_address_p; store_previous_rsaddr: process(clk, stall_ex) begin if rising_edge(clk) and stall_ex = '0' then rs1_address_p <= id_rs1_address; rs2_address_p <= id_rs2_address; end if; end process store_previous_rsaddr; ------- Instruction Fetch (IF) Stage ------- fetch: entity work.pp_fetch generic map( RESET_ADDRESS => RESET_ADDRESS ) port map( clk => clk, reset => reset, imem_address => imem_address, imem_data_in => imem_data_in, imem_req => imem_req, imem_ack => imem_ack, stall => stall_if, flush => flush_if, branch => branch_taken, exception => exception_taken, branch_target => branch_target, evec => exception_target, instruction_data => if_instruction, instruction_address => if_pc, instruction_ready => if_instruction_ready ); if_count_instruction <= if_instruction_ready; ------- Instruction Decode (ID) Stage ------- decode: entity work.pp_decode generic map( RESET_ADDRESS => RESET_ADDRESS, PROCESSOR_ID => PROCESSOR_ID ) port map( clk => clk, reset => reset, flush => flush_id, stall => stall_id, instruction_data => if_instruction, instruction_address => if_pc, instruction_ready => if_instruction_ready, instruction_count => if_count_instruction, funct3 => id_funct3, rs1_addr => id_rs1_address, rs2_addr => id_rs2_address, rd_addr => id_rd_address, csr_addr => id_csr_address, shamt => id_shamt, immediate => id_immediate, rd_write => id_rd_write, branch => id_branch, alu_x_src => id_alu_x_src, alu_y_src => id_alu_y_src, alu_op => id_alu_op, mem_op => id_mem_op, mem_size => id_mem_size, count_instruction => id_count_instruction, pc => id_pc, csr_write => id_csr_write, csr_use_imm => id_csr_use_immediate, decode_exception => id_exception, decode_exception_cause => id_exception_cause ); ------- Execute (EX) Stage ------- execute: entity work.pp_execute port map( clk => clk, reset => reset, stall => stall_ex, flush => flush_ex, irq => irq, software_interrupt => software_interrupt, timer_interrupt => timer_interrupt, dmem_address => ex_dmem_address, dmem_data_size => ex_dmem_data_size, dmem_data_out => ex_dmem_data_out, dmem_read_req => ex_dmem_read_req, dmem_write_req => ex_dmem_write_req, rs1_addr_in => rs1_address, rs2_addr_in => rs2_address, rd_addr_in => id_rd_address, rd_addr_out => ex_rd_address, rs1_data_in => rs1_data, rs2_data_in => rs2_data, shamt_in => id_shamt, immediate_in => id_immediate, funct3_in => id_funct3, pc_in => id_pc, pc_out => ex_pc, csr_addr_in => csr_read_address, csr_addr_out => ex_csr_address, csr_write_in => id_csr_write, csr_write_out => ex_csr_write, csr_value_in => csr_read_data, csr_value_out => ex_csr_data, csr_use_immediate_in => id_csr_use_immediate, alu_op_in => id_alu_op, alu_x_src_in => id_alu_x_src, alu_y_src_in => id_alu_y_src, rd_write_in => id_rd_write, rd_write_out => ex_rd_write, rd_data_out => ex_rd_data, branch_in => id_branch, branch_out => ex_branch, mem_op_in => id_mem_op, mem_op_out => ex_mem_op, mem_size_in => id_mem_size, mem_size_out => ex_mem_size, count_instruction_in => id_count_instruction, count_instruction_out => ex_count_instruction, ie_in => ie, ie1_in => ie1, mie_in => mie, mtvec_in => mtvec, mtvec_out => exception_target, decode_exception_in => id_exception, decode_exception_cause_in => id_exception_cause, exception_out => exception_taken, exception_context_out => ex_exception_context, jump_out => branch_taken, jump_target_out => branch_target, mem_rd_write => mem_rd_write, mem_rd_addr => mem_rd_address, mem_rd_value => mem_rd_data, mem_csr_addr => mem_csr_address, mem_csr_write => mem_csr_write, mem_exception => mem_exception, wb_rd_write => wb_rd_write, wb_rd_addr => wb_rd_address, wb_rd_value => wb_rd_data, wb_csr_addr => wb_csr_address, wb_csr_write => wb_csr_write, wb_exception => wb_exception, mem_mem_op => mem_mem_op, hazard_detected => hazard_detected ); dmem_address <= ex_dmem_address when stall_mem = '0' else dmem_address_p; dmem_data_size <= ex_dmem_data_size when stall_mem = '0' else dmem_data_size_p; dmem_data_out <= ex_dmem_data_out when stall_mem = '0' else dmem_data_out_p; dmem_read_req <= ex_dmem_read_req when stall_mem = '0' else dmem_read_req_p; dmem_write_req <= ex_dmem_write_req when stall_mem = '0' else dmem_write_req_p; store_previous_dmem_address: process(clk, stall_mem) begin if rising_edge(clk) and stall_mem = '0' then dmem_address_p <= ex_dmem_address; dmem_data_size_p <= ex_dmem_data_size; dmem_data_out_p <= ex_dmem_data_out; dmem_read_req_p <= ex_dmem_read_req; dmem_write_req_p <= ex_dmem_write_req; end if; end process store_previous_dmem_address; ------- Memory (MEM) Stage ------- memory: entity work.pp_memory port map( clk => clk, reset => reset, stall => stall_mem, dmem_data_in => dmem_data_in, dmem_read_ack => dmem_read_ack, dmem_write_ack => dmem_write_ack, pc => ex_pc, rd_write_in => ex_rd_write, rd_write_out => mem_rd_write, rd_data_in => ex_rd_data, rd_data_out => mem_rd_data, rd_addr_in => ex_rd_address, rd_addr_out => mem_rd_address, branch => ex_branch, mem_op_in => ex_mem_op, mem_op_out => mem_mem_op, mem_size_in => ex_mem_size, count_instr_in => ex_count_instruction, count_instr_out => mem_count_instruction, exception_in => exception_taken, exception_out => mem_exception, exception_context_in => ex_exception_context, exception_context_out => mem_exception_context, csr_addr_in => ex_csr_address, csr_addr_out => mem_csr_address, csr_write_in => ex_csr_write, csr_write_out => mem_csr_write, csr_data_in => ex_csr_data, csr_data_out => mem_csr_data ); ------- Writeback (WB) Stage ------- writeback: entity work.pp_writeback port map( clk => clk, reset => reset, count_instr_in => mem_count_instruction, count_instr_out => wb_count_instruction, exception_ctx_in => mem_exception_context, exception_ctx_out => wb_exception_context, exception_in => mem_exception, exception_out => wb_exception, csr_write_in => mem_csr_write, csr_write_out => wb_csr_write, csr_data_in => mem_csr_data, csr_data_out => wb_csr_data, csr_addr_in => mem_csr_address, csr_addr_out => wb_csr_address, rd_addr_in => mem_rd_address, rd_addr_out => wb_rd_address, rd_write_in => mem_rd_write, rd_write_out => wb_rd_write, rd_data_in => mem_rd_data, rd_data_out => wb_rd_data ); end architecture behaviour; |
use std.textio.all ; use work.OsvvmGlobalPkg.all ; use work.TranscriptPkg.all ; use work.TextUtilPkg.all ; library IEEE ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; package AlertLogPkg is subtype AlertLogIDType is integer ; type AlertLogIDVectorType is array (integer range <>) of AlertLogIDType ; type AlertType is (FAILURE, ERROR, WARNING) ; -- NEVER subtype AlertIndexType is AlertType range FAILURE to WARNING ; type AlertCountType is array (AlertIndexType) of integer ; type AlertEnableType is array(AlertIndexType) of boolean ; type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER -- See function IsLogEnableType subtype LogIndexType is LogType range DEBUG to PASSED ; type LogEnableType is array (LogIndexType) of boolean ; constant ALERTLOG_BASE_ID : AlertLogIDType := 0 ; -- Careful as some code may assume this is 0. constant ALERTLOG_DEFAULT_ID : AlertLogIDType := 1 ; constant ALERT_DEFAULT_ID : AlertLogIDType := ALERTLOG_DEFAULT_ID ; constant LOG_DEFAULT_ID : AlertLogIDType := ALERTLOG_DEFAULT_ID ; constant OSVVM_ALERTLOG_ID : AlertLogIDType := 2 ; constant OSVVM_SCOREBOARD_ALERTLOG_ID : AlertLogIDType := OSVVM_ALERTLOG_ID ; -- NUM_PREDEFINED_AL_IDS intended to be local, but depends on others -- constant NUM_PREDEFINED_AL_IDS : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID - ALERTLOG_BASE_ID ; -- Not including base constant ALERTLOG_ID_NOT_FOUND : AlertLogIDType := -1 ; -- alternately integer'right constant ALERTLOG_ID_NOT_ASSIGNED : AlertLogIDType := -1 ; constant MIN_NUM_AL_IDS : AlertLogIDType := 32 ; -- Number IDs initially allocated alias AlertLogOptionsType is work.OsvvmGlobalPkg.OsvvmOptionsType ; ------------------------------------------------------------ -- Alert always goes to the transcript file procedure Alert( AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ; procedure Alert( Message : string ; Level : AlertType := ERROR ) ; ------------------------------------------------------------ procedure IncAlertCount( -- A silent form of alert AlertLogID : AlertLogIDType ; Level : AlertType := ERROR ) ; procedure IncAlertCount( Level : AlertType := ERROR ) ; ------------------------------------------------------------ -- Similar to assert, except condition is positive procedure AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) ; impure function AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ; impure function AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ; ------------------------------------------------------------ -- Direct replacement for assert procedure AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) ; impure function AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ; impure function AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ; ------------------------------------------------------------ -- overloading for common functionality procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) ; procedure AlertIfNotEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) ; ------------------------------------------------------------ -- Simple Diff for file comparisons procedure AlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) ; procedure AlertIfDiff (Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) ; procedure AlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) ; procedure AlertIfDiff (file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) ; ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ procedure AffirmIf( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage : string ; ExpectedMessage : string ; Enable : boolean := FALSE -- override internal enable ) ; procedure AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ; impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ; impure function AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ; procedure AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE -- override internal enable ) ; procedure AffirmIf(condition : boolean ; Message : string ; Enable : boolean := FALSE ) ; impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ; impure function AffirmIf( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ; ------------------------------------------------------------ procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ; procedure AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ; impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ; impure function AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ; ------------------------------------------------------------ procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) ; procedure AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) ; impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ; impure function AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ; ------------------------------------------------------------ procedure AffirmPassed( AlertLogID : AlertLogIDType ; Message : string ; Enable : boolean := FALSE ) ; procedure AffirmPassed( Message : string ; Enable : boolean := FALSE ) ; procedure AffirmError( AlertLogID : AlertLogIDType ; Message : string ) ; procedure AffirmError( Message : string ) ; ------------------------------------------------------------ procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE ); procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) ; -- Without AlertLogID ------------------------------------------------------------ procedure AffirmIfEqual( Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfEqual( Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfEqual( Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfEqual( Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfEqual( Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfEqual( Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfEqual( Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfEqual( Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfEqual( Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) ; ------------------------------------------------------------ procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfDiff (Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) ; procedure AffirmIfDiff (file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) ; ------------------------------------------------------------ procedure SetAlertLogJustify ; procedure ReportAlerts ( Name : String ; AlertCount : AlertCountType ) ; procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) ; procedure ReportNonZeroAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) ; procedure ClearAlerts ; function "ABS" (L : AlertCountType) return AlertCountType ; function "+" (L, R : AlertCountType) return AlertCountType ; function "-" (L, R : AlertCountType) return AlertCountType ; function "-" (R : AlertCountType) return AlertCountType ; impure function SumAlertCount(AlertCount: AlertCountType) return integer ; impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ; impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer ; impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ; impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer ; impure function GetDisabledAlertCount return AlertCountType ; impure function GetDisabledAlertCount return integer ; impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType ; impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return integer ; ------------------------------------------------------------ -- log filtering for verbosity control, optionally has a separate file parameter procedure Log( AlertLogID : AlertLogIDType ; Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE -- override internal enable ) ; procedure Log( Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE) ; ------------------------------------------------------------ -- Accessor Methods procedure SetAlertLogName(Name : string ) ; impure function GetAlertLogName(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return string ; procedure DeallocateAlertLogStruct ; procedure InitializeAlertLogStruct ; impure function FindAlertLogID(Name : string ) return AlertLogIDType ; impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType ; impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType ; impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType ; ------------------------------------------------------------ -- Accessor Methods procedure SetGlobalAlertEnable (A : boolean := TRUE) ; impure function SetGlobalAlertEnable (A : boolean := TRUE) return boolean ; impure function GetGlobalAlertEnable return boolean ; procedure IncAffirmCount ; impure function GetAffirmCount return natural ; procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ; procedure SetAlertStopCount(Level : AlertType ; Count : integer) ; impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ; impure function GetAlertStopCount(Level : AlertType) return integer ; procedure SetAlertEnable(Level : AlertType ; Enable : boolean) ; procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ; impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean ; impure function GetAlertEnable(Level : AlertType) return boolean ; alias IsAlertEnabled is GetAlertEnable[AlertLogIDType, AlertType return boolean] ; alias IsAlertEnabled is GetAlertEnable[AlertType return boolean] ; procedure SetLogEnable(Level : LogType ; Enable : boolean) ; procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ; impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ; impure function GetLogEnable(Level : LogType) return boolean ; alias IsLogEnabled is GetLogEnable [AlertLogIDType, LogType return boolean] ; -- same as GetLogEnable alias IsLogEnabled is GetLogEnable [LogType return boolean] ; -- same as GetLogEnable procedure ReportLogEnables ; ------------------------------------------------------------ procedure SetAlertLogOptions ( FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) ; procedure ReportAlertLogOptions ; impure function GetAlertLogFailOnWarning return AlertLogOptionsType ; impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType ; impure function GetAlertLogReportHierarchy return AlertLogOptionsType ; impure function GetAlertLogFoundReportHier return boolean ; impure function GetAlertLogFoundAlertHier return boolean ; impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType ; impure function GetAlertLogWriteAlertName return AlertLogOptionsType ; impure function GetAlertLogWriteAlertTime return AlertLogOptionsType ; impure function GetAlertLogWriteLogLevel return AlertLogOptionsType ; impure function GetAlertLogWriteLogName return AlertLogOptionsType ; impure function GetAlertLogWriteLogTime return AlertLogOptionsType ; impure function GetAlertLogAlertPrefix return string ; impure function GetAlertLogLogPrefix return string ; impure function GetAlertLogReportPrefix return string ; impure function GetAlertLogDoneName return string ; impure function GetAlertLogPassName return string ; impure function GetAlertLogFailName return string ; -- File Reading Utilities function IsLogEnableType (Name : String) return boolean ; procedure ReadLogEnables (file AlertLogInitFile : text) ; procedure ReadLogEnables (FileName : string) ; -- String Helper Functions -- This should be in a more general string package function PathTail (A : string) return string ; -- ------------------------------------------------------------ -- Deprecated -- -- deprecated procedure AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ; impure function AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean ; -- deprecated procedure AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ; impure function AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean ; -- deprecated procedure AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; LogLevel : LogType ; -- := PASSED AlertLevel : AlertType := ERROR ) ; procedure AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; AlertLevel : AlertType ) ; procedure AffirmIf(condition : boolean ; Message : string ; LogLevel : LogType ; AlertLevel : AlertType := ERROR) ; procedure AffirmIf(condition : boolean ; Message : string ; AlertLevel : AlertType ) ; alias IncAffirmCheckCount is IncAffirmCount [] ; alias GetAffirmCheckCount is GetAffirmCount [return natural] ; alias IsLoggingEnabled is GetLogEnable [AlertLogIDType, LogType return boolean] ; -- same as IsLogEnabled alias IsLoggingEnabled is GetLogEnable [LogType return boolean] ; -- same as IsLogEnabled end AlertLogPkg ; use work.NamePkg.all ; package body AlertLogPkg is -- instead of justify(to_upper(to_string())), just look up the upper case, left justified values type AlertNameType is array(AlertType) of string(1 to 7) ; constant ALERT_NAME : AlertNameType := (WARNING => "WARNING", ERROR => "ERROR ", FAILURE => "FAILURE") ; -- , NEVER => "NEVER " type LogNameType is array(LogType) of string(1 to 7) ; constant LOG_NAME : LogNameType := (DEBUG => "DEBUG ", FINAL => "FINAL ", INFO => "INFO ", ALWAYS => "ALWAYS ", PASSED => "PASSED ") ; -- , NEVER => "NEVER " type AlertLogStructPType is protected ------------------------------------------------------------ procedure alert ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; message : string ; level : AlertType := ERROR ) ; ------------------------------------------------------------ procedure IncAlertCount ( AlertLogID : AlertLogIDType ; level : AlertType := ERROR ) ; procedure SetJustify ; procedure ReportAlerts ( Name : string ; AlertCount : AlertCountType ) ; procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (0,0,0) ; ReportAll : boolean := TRUE ) ; procedure ClearAlerts ; impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ; impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ; impure function GetDisabledAlertCount return AlertCountType ; impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType ; ------------------------------------------------------------ procedure log ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE -- override internal enable ) ; ------------------------------------------------------------ -- FILE IO Controls ------------------------------------------------------------ ------------------------------------------------------------ -- AlertLog Structure Creation and Interaction Methods ------------------------------------------------------------ procedure SetAlertLogName(Name : string ) ; procedure SetNumAlertLogIDs (NewNumAlertLogIDs : AlertLogIDType) ; impure function FindAlertLogID(Name : string ) return AlertLogIDType ; impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType ; impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType ; impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType ; procedure Initialize(NewNumAlertLogIDs : AlertLogIDType := MIN_NUM_AL_IDS) ; procedure Deallocate ; ------------------------------------------------------------ ------------------------------------------------------------ -- Accessor Methods ------------------------------------------------------------ procedure SetGlobalAlertEnable (A : boolean := TRUE) ; impure function GetAlertLogName(AlertLogID : AlertLogIDType) return string ; impure function GetGlobalAlertEnable return boolean ; procedure IncAffirmCount ; impure function GetAffirmCount return natural ; procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ; impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ; procedure SetAlertEnable(Level : AlertType ; Enable : boolean) ; procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ; impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean ; procedure SetLogEnable(Level : LogType ; Enable : boolean) ; procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ; impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ; procedure ReportLogEnables ; ------------------------------------------------------------ -- Reporting Accessor procedure SetAlertLogOptions ( FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) ; procedure ReportAlertLogOptions ; impure function GetAlertLogFailOnWarning return AlertLogOptionsType ; impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType ; impure function GetAlertLogReportHierarchy return AlertLogOptionsType ; impure function GetAlertLogFoundReportHier return boolean ; impure function GetAlertLogFoundAlertHier return boolean ; impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType ; impure function GetAlertLogWriteAlertName return AlertLogOptionsType ; impure function GetAlertLogWriteAlertTime return AlertLogOptionsType ; impure function GetAlertLogWriteLogLevel return AlertLogOptionsType ; impure function GetAlertLogWriteLogName return AlertLogOptionsType ; impure function GetAlertLogWriteLogTime return AlertLogOptionsType ; impure function GetAlertLogAlertPrefix return string ; impure function GetAlertLogLogPrefix return string ; impure function GetAlertLogReportPrefix return string ; impure function GetAlertLogDoneName return string ; impure function GetAlertLogPassName return string ; impure function GetAlertLogFailName return string ; end protected AlertLogStructPType ; --- /////////////////////////////////////////////////////////////////////////// type AlertLogStructPType is protected body variable GlobalAlertEnabledVar : boolean := TRUE ; -- Allows turn off and on variable AffirmCheckCountVar : natural := 0 ; ------------------------------------------------------------ type AlertLogRecType is record ------------------------------------------------------------ Name : Line ; ParentID : AlertLogIDType ; AlertCount : AlertCountType ; AlertStopCount : AlertCountType ; AlertEnabled : AlertEnableType ; LogEnabled : LogEnableType ; end record AlertLogRecType ; ------------------------------------------------------------ -- Basis for AlertLog Data Structure variable NumAlertLogIDsVar : AlertLogIDType := 0 ; -- defined by initialize variable NumAllocatedAlertLogIDsVar : AlertLogIDType := 0 ; type AlertLogRecPtrType is access AlertLogRecType ; type AlertLogArrayType is array (AlertLogIDType range <>) of AlertLogRecPtrType ; type AlertLogArrayPtrType is access AlertLogArrayType ; variable AlertLogPtr : AlertLogArrayPtrType ; ------------------------------------------------------------ -- Report formatting settings, with defaults variable FailOnWarningVar : boolean := TRUE ; variable FailOnDisabledErrorsVar : boolean := TRUE ; variable ReportHierarchyVar : boolean := TRUE ; variable FoundReportHierVar : boolean := FALSE ; variable FoundAlertHierVar : boolean := FALSE ; variable WriteAlertLevelVar : boolean := TRUE ; variable WriteAlertNameVar : boolean := TRUE ; variable WriteAlertTimeVar : boolean := TRUE ; variable WriteLogLevelVar : boolean := TRUE ; variable WriteLogNameVar : boolean := TRUE ; variable WriteLogTimeVar : boolean := TRUE ; variable AlertPrefixVar : NamePType ; variable LogPrefixVar : NamePType ; variable ReportPrefixVar : NamePType ; variable DoneNameVar : NamePType ; variable PassNameVar : NamePType ; variable FailNameVar : NamePType ; variable AlertLogJustifyAmountVar : integer := 0 ; variable ReportJustifyAmountVar : integer := 0 ; ------------------------------------------------------------ -- PT Local impure function LeftJustify(A : String; Amount : integer) return string is ------------------------------------------------------------ constant Spaces : string(1 to maximum(1, Amount)) := (others => ' ') ; begin if A'length >= Amount then return A ; else return A & Spaces(1 to Amount - A'length) ; end if ; end function LeftJustify ; ------------------------------------------------------------ -- PT Local procedure IncrementAlertCount( ------------------------------------------------------------ constant AlertLogID : in AlertLogIDType ; constant Level : in AlertType ; variable StopDueToCount : inout boolean ) is begin -- Always Count at this level AlertLogPtr(AlertLogID).AlertCount(Level) := AlertLogPtr(AlertLogID).AlertCount(Level) + 1 ; -- Only do remaining actions if enabled if AlertLogPtr(AlertLogID).AlertEnabled(Level) then -- Exceeded Stop Count at this level? if AlertLogPtr(AlertLogID).AlertCount(Level) >= AlertLogPtr(AlertLogID).AlertStopCount(Level) then StopDueToCount := TRUE ; end if ; -- Propagate counts to parent(s) -- Ascend Hierarchy if AlertLogID /= ALERTLOG_BASE_ID then IncrementAlertCount(AlertLogPtr(AlertLogID).ParentID, Level, StopDueToCount) ; end if ; end if ; end procedure IncrementAlertCount ; ------------------------------------------------------------ procedure alert ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; message : string ; level : AlertType := ERROR ) is variable buf : Line ; constant AlertPrefix : string := AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ; variable StopDueToCount : boolean := FALSE ; begin if GlobalAlertEnabledVar then -- Do not write or count when GlobalAlertEnabledVar is disabled if AlertLogPtr(AlertLogID).AlertEnabled(Level) then -- do not write when disabled write(buf, AlertPrefix) ; if WriteAlertLevelVar then -- write(buf, " " & to_string(Level) ) ; write(buf, " " & ALERT_NAME(Level)) ; -- uses constant lookup end if ; if FoundAlertHierVar and WriteAlertNameVar then write(buf, " in " & LeftJustify(AlertLogPtr(AlertLogID).Name.all & ",", AlertLogJustifyAmountVar) ) ; end if ; write(buf, " " & Message) ; if WriteAlertTimeVar then write(buf, " at " & to_string(NOW, 1 ns)) ; end if ; writeline(buf) ; end if ; -- Always Count IncrementAlertCount(AlertLogID, Level, StopDueToCount) ; if StopDueToCount then write(buf, LF & AlertPrefix & " Stop Count on " & ALERT_NAME(Level) & " reached") ; if FoundAlertHierVar then write(buf, " in " & AlertLogPtr(AlertLogID).Name.all) ; end if ; write(buf, " at " & to_string(NOW, 1 ns) & " ") ; writeline(buf) ; ReportAlerts(ReportAll => TRUE) ; std.env.stop(1) ; end if ; end if ; end procedure alert ; ------------------------------------------------------------ procedure IncAlertCount ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; level : AlertType := ERROR ) is variable buf : Line ; constant AlertPrefix : string := AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ; variable StopDueToCount : boolean := FALSE ; begin if GlobalAlertEnabledVar then IncrementAlertCount(AlertLogID, Level, StopDueToCount) ; if StopDueToCount then write(buf, LF & AlertPrefix & " Stop Count on " & ALERT_NAME(Level) & " reached") ; if FoundAlertHierVar then write(buf, " in " & AlertLogPtr(AlertLogID).Name.all) ; end if ; write(buf, " at " & to_string(NOW, 1 ns) & " ") ; writeline(buf) ; ReportAlerts(ReportAll => TRUE) ; std.env.stop ; end if ; end if ; end procedure IncAlertCount ; ------------------------------------------------------------ -- PT Local impure function CalcJustify (AlertLogID : AlertLogIDType ; CurrentLength : integer ; IndentAmount : integer) return integer_vector is ------------------------------------------------------------ variable ResultValues, LowerLevelValues : integer_vector(1 to 2) ; -- 1 = Max, 2 = Indented begin ResultValues(1) := CurrentLength + 1 ; -- AlertLogJustifyAmountVar ResultValues(2) := CurrentLength + IndentAmount ; -- ReportJustifyAmountVar for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then LowerLevelValues := CalcJustify(i, AlertLogPtr(i).Name'length, IndentAmount + 2) ; ResultValues(1) := maximum(ResultValues(1), LowerLevelValues(1)) ; ResultValues(2) := maximum(ResultValues(2), LowerLevelValues(2)) ; end if ; end loop ; return ResultValues ; end function CalcJustify ; ------------------------------------------------------------ procedure SetJustify is ------------------------------------------------------------ variable ResultValues : integer_vector(1 to 2) ; -- 1 = Max, 2 = Indented begin ResultValues := CalcJustify(ALERTLOG_BASE_ID, 0, 0) ; AlertLogJustifyAmountVar := ResultValues(1) ; ReportJustifyAmountVar := ResultValues(2) ; end procedure SetJustify ; ------------------------------------------------------------ -- PT Local impure function GetEnabledAlertCount(AlertCount: AlertCountType; AlertEnabled : AlertEnableType) return AlertCountType is ------------------------------------------------------------ variable Count : AlertCountType := (others => 0) ; begin if AlertEnabled(FAILURE) then Count(FAILURE) := AlertCount(FAILURE) ; end if ; if AlertEnabled(ERROR) then Count(ERROR) := AlertCount(ERROR) ; end if ; if FailOnWarningVar and AlertEnabled(WARNING) then Count(WARNING) := AlertCount(WARNING) ; end if ; return Count ; end function GetEnabledAlertCount ; ------------------------------------------------------------ impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is ------------------------------------------------------------ variable AlertCount : AlertCountType ; begin return AlertLogPtr(AlertLogID).AlertCount ; end function GetAlertCount ; ------------------------------------------------------------ impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is ------------------------------------------------------------ variable AlertCount : AlertCountType ; begin return GetEnabledAlertCount(AlertLogPtr(AlertLogID).AlertCount, AlertLogPtr(AlertLogID).AlertEnabled) ; end function GetEnabledAlertCount ; ------------------------------------------------------------ -- PT Local impure function GetDisabledAlertCount(AlertCount: AlertCountType; AlertEnabled : AlertEnableType) return AlertCountType is ------------------------------------------------------------ variable Count : AlertCountType := (others => 0) ; begin if not AlertEnabled(FAILURE) then Count(FAILURE) := AlertCount(FAILURE) ; end if ; if not AlertEnabled(ERROR) then Count(ERROR) := AlertCount(ERROR) ; end if ; if FailOnWarningVar and not AlertEnabled(WARNING) then Count(WARNING) := AlertCount(WARNING) ; end if ; return Count ; end function GetDisabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount return AlertCountType is ------------------------------------------------------------ variable Count : AlertCountType := (others => 0) ; begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop Count := Count + GetDisabledAlertCount(AlertLogPtr(i).AlertCount, AlertLogPtr(i).AlertEnabled) ; end loop ; return Count ; end function GetDisabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is ------------------------------------------------------------ variable Count : AlertCountType := (others => 0) ; begin Count := GetDisabledAlertCount(AlertLogPtr(AlertLogID).AlertCount, AlertLogPtr(AlertLogID).AlertEnabled) ; for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then Count := Count + GetDisabledAlertCount(i) ; end if ; end loop ; return Count ; end function GetDisabledAlertCount ; ------------------------------------------------------------ -- PT Local procedure PrintTopAlerts ( ------------------------------------------------------------ NumErrors : integer ; AlertCount : AlertCountType ; Name : string ; NumDisabledErrors : integer ) is constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) ; constant DoneName : string := ResolveOsvvmDoneName(DoneNameVar.GetOpt ) ; constant PassName : string := ResolveOsvvmPassName(PassNameVar.GetOpt ) ; constant FailName : string := ResolveOsvvmFailName(FailNameVar.GetOpt ) ; variable buf : line ; begin if NumErrors = 0 then if NumDisabledErrors = 0 then -- Passed write(buf, ReportPrefix & DoneName & " " & PassName & " " & Name) ; if AffirmCheckCountVar > 0 then write(buf, " Affirmations Checked: " & to_string(AffirmCheckCountVar)) ; end if ; write(buf, " at " & to_string(NOW, 1 ns)) ; WriteLine(buf) ; else -- Failed Due to Disabled Errors write(buf, ReportPrefix & DoneName & " " & FailName & " " & Name) ; write(buf, " Failed Due to Disabled Error(s) = " & to_string(NumDisabledErrors)) ; if AffirmCheckCountVar > 0 then write(buf, " Affirmations Checked: " & to_string(AffirmCheckCountVar)) ; end if ; write(buf, " at " & to_string(NOW, 1 ns)) ; WriteLine(buf) ; end if ; else -- Failed write(buf, ReportPrefix & DoneName & " " & FailName & " "& Name) ; write(buf, " Total Error(s) = " & to_string(NumErrors) ) ; write(buf, " Failures: " & to_string(AlertCount(FAILURE)) ) ; write(buf, " Errors: " & to_string(AlertCount(ERROR) ) ) ; write(buf, " Warnings: " & to_string(AlertCount(WARNING) ) ) ; if AffirmCheckCountVar > 0 then write(buf, " Affirmations Checked: " & to_string(AffirmCheckCountVar)) ; end if ; Write(buf, " at " & to_string(NOW, 1 ns)) ; WriteLine(buf) ; end if ; end procedure PrintTopAlerts ; ------------------------------------------------------------ -- PT Local procedure PrintChild( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Prefix : string ; IndentAmount : integer ; ReportAll : boolean ) is variable buf : line ; begin for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then if ReportAll or SumAlertCount(AlertLogPtr(i).AlertCount) > 0 then Write(buf, Prefix & " " & LeftJustify(AlertLogPtr(i).Name.all, ReportJustifyAmountVar - IndentAmount)) ; write(buf, " Failures: " & to_string(AlertLogPtr(i).AlertCount(FAILURE) ) ) ; write(buf, " Errors: " & to_string(AlertLogPtr(i).AlertCount(ERROR) ) ) ; write(buf, " Warnings: " & to_string(AlertLogPtr(i).AlertCount(WARNING) ) ) ; WriteLine(buf) ; end if ; PrintChild( AlertLogID => i, Prefix => Prefix & " ", IndentAmount => IndentAmount + 2, ReportAll => ReportAll ) ; end if ; end loop ; end procedure PrintChild ; ------------------------------------------------------------ procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (0,0,0) ; ReportAll : boolean := TRUE) is ------------------------------------------------------------ variable NumErrors : integer ; variable NumDisabledErrors : integer ; constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ; begin if ReportJustifyAmountVar <= 0 then SetJustify ; end if ; NumErrors := SumAlertCount( ExternalErrors + GetEnabledAlertCount(AlertLogPtr(AlertLogID).AlertCount, AlertLogPtr(AlertLogID).AlertEnabled) ) ; if FailOnDisabledErrorsVar then NumDisabledErrors := SumAlertCount( GetDisabledAlertCount(AlertLogID) ) ; else NumDisabledErrors := 0 ; end if ; if IsOsvvmStringSet(Name) then PrintTopAlerts ( NumErrors => NumErrors, AlertCount => AlertLogPtr(AlertLogID).AlertCount + ExternalErrors, Name => Name, NumDisabledErrors => NumDisabledErrors ) ; else PrintTopAlerts ( NumErrors => NumErrors, AlertCount => AlertLogPtr(AlertLogID).AlertCount + ExternalErrors, Name => AlertLogPtr(AlertLogID).Name.all, NumDisabledErrors => NumDisabledErrors ) ; end if ; --Print Hierarchy when enabled and error or disabled error if (FoundReportHierVar and ReportHierarchyVar) and (NumErrors /= 0 or NumDisabledErrors /=0) then PrintChild( AlertLogID => AlertLogID, Prefix => ReportPrefix & " ", IndentAmount => 2, ReportAll => ReportAll ) ; end if ; end procedure ReportAlerts ; ------------------------------------------------------------ procedure ReportAlerts ( Name : string ; AlertCount : AlertCountType ) is ------------------------------------------------------------ begin PrintTopAlerts ( NumErrors => SumAlertCount(AlertCount), AlertCount => AlertCount, Name => Name, NumDisabledErrors => 0 ) ; end procedure ReportAlerts ; ------------------------------------------------------------ procedure ClearAlerts is ------------------------------------------------------------ begin AffirmCheckCountVar := 0 ; AlertLogPtr(ALERTLOG_BASE_ID).AlertCount := (0, 0, 0) ; AlertLogPtr(ALERTLOG_BASE_ID).AlertStopCount := (FAILURE => 0, ERROR => integer'right, WARNING => integer'right) ; for i in ALERTLOG_BASE_ID + 1 to NumAlertLogIDsVar loop AlertLogPtr(i).AlertCount := (0, 0, 0) ; AlertLogPtr(i).AlertStopCount := (FAILURE => integer'right, ERROR => integer'right, WARNING => integer'right) ; end loop ; end procedure ClearAlerts ; ------------------------------------------------------------ -- PT Local procedure LocalLog ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Message : string ; Level : LogType ) is variable buf : line ; constant LogPrefix : string := LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX) ; begin write(buf, LogPrefix) ; if WriteLogLevelVar then write(buf, " " & LOG_NAME(Level) ) ; end if ; if FoundAlertHierVar and WriteLogNameVar then write(buf, " in " & LeftJustify(AlertLogPtr(AlertLogID).Name.all & ",", AlertLogJustifyAmountVar) ) ; end if ; write(buf, " " & Message) ; if WriteLogTimeVar then write(buf, " at " & to_string(NOW, 1 ns)) ; end if ; writeline(buf) ; end procedure LocalLog ; ------------------------------------------------------------ procedure log ( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE -- override internal enable ) is begin if Level = ALWAYS or Enable then LocalLog(AlertLogID, Message, Level) ; elsif AlertLogPtr(AlertLogID).LogEnabled(Level) then LocalLog(AlertLogID, Message, Level) ; end if ; end procedure log ; ------------------------------------------------------------ ------------------------------------------------------------ -- AlertLog Structure Creation and Interaction Methods ------------------------------------------------------------ procedure SetAlertLogName(Name : string ) is ------------------------------------------------------------ begin Deallocate(AlertLogPtr(ALERTLOG_BASE_ID).Name) ; AlertLogPtr(ALERTLOG_BASE_ID).Name := new string'(Name) ; end procedure SetAlertLogName ; ------------------------------------------------------------ impure function GetAlertLogName(AlertLogID : AlertLogIDType) return string is ------------------------------------------------------------ begin return AlertLogPtr(AlertLogID).Name.all ; end function GetAlertLogName ; ------------------------------------------------------------ -- PT Local procedure NewAlertLogRec(AlertLogID : AlertLogIDType ; Name : string ; ParentID : AlertLogIDType) is ------------------------------------------------------------ variable AlertEnabled : AlertEnableType ; variable AlertStopCount : AlertCountType ; variable LogEnabled : LogEnableType ; begin if AlertLogID = ALERTLOG_BASE_ID then AlertEnabled := (TRUE, TRUE, TRUE) ; LogEnabled := (others => FALSE) ; AlertStopCount := (FAILURE => 0, ERROR => integer'right, WARNING => integer'right) ; else if ParentID < ALERTLOG_BASE_ID then AlertEnabled := AlertLogPtr(ALERTLOG_BASE_ID).AlertEnabled ; LogEnabled := AlertLogPtr(ALERTLOG_BASE_ID).LogEnabled ; else AlertEnabled := AlertLogPtr(ParentID).AlertEnabled ; LogEnabled := AlertLogPtr(ParentID).LogEnabled ; end if ; AlertStopCount := (FAILURE => integer'right, ERROR => integer'right, WARNING => integer'right) ; end if ; AlertLogPtr(AlertLogID) := new AlertLogRecType ; AlertLogPtr(AlertLogID).Name := new string'(NAME) ; AlertLogPtr(AlertLogID).ParentID := ParentID ; AlertLogPtr(AlertLogID).AlertCount := (0, 0, 0) ; AlertLogPtr(AlertLogID).AlertEnabled := AlertEnabled ; AlertLogPtr(AlertLogID).AlertStopCount := AlertStopCount ; AlertLogPtr(AlertLogID).LogEnabled := LogEnabled ; end procedure NewAlertLogRec ; ------------------------------------------------------------ -- PT Local -- Construct initial data structure procedure LocalInitialize(NewNumAlertLogIDs : AlertLogIDType := MIN_NUM_AL_IDS) is ------------------------------------------------------------ begin if NumAllocatedAlertLogIDsVar /= 0 then Alert(ALERT_DEFAULT_ID, "AlertLogPkg: Initialize, data structure already initialized", FAILURE) ; return ; end if ; -- Initialize Pointer AlertLogPtr := new AlertLogArrayType(ALERTLOG_BASE_ID to ALERTLOG_BASE_ID + NewNumAlertLogIDs) ; NumAllocatedAlertLogIDsVar := NewNumAlertLogIDs ; -- Create BASE AlertLogID (if it differs from DEFAULT if ALERTLOG_BASE_ID /= ALERT_DEFAULT_ID then NewAlertLogRec(ALERTLOG_BASE_ID, "AlertLogTop", ALERTLOG_BASE_ID) ; end if ; -- Create DEFAULT AlertLogID NewAlertLogRec(ALERT_DEFAULT_ID, "Default", ALERTLOG_BASE_ID) ; NumAlertLogIDsVar := ALERT_DEFAULT_ID ; -- Create OSVVM AlertLogID (if it differs from DEFAULT if OSVVM_ALERTLOG_ID /= ALERT_DEFAULT_ID then NewAlertLogRec(OSVVM_ALERTLOG_ID, "OSVVM", ALERTLOG_BASE_ID) ; NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ; end if ; if OSVVM_SCOREBOARD_ALERTLOG_ID /= OSVVM_ALERTLOG_ID then NewAlertLogRec(OSVVM_SCOREBOARD_ALERTLOG_ID, "OSVVM Scoreboard", ALERTLOG_BASE_ID) ; NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ; end if ; end procedure LocalInitialize ; ------------------------------------------------------------ -- Construct initial data structure procedure Initialize(NewNumAlertLogIDs : AlertLogIDType := MIN_NUM_AL_IDS) is ------------------------------------------------------------ begin LocalInitialize(NewNumAlertLogIDs) ; end procedure Initialize ; ------------------------------------------------------------ -- PT Local -- Constructs initial data structure using constant below impure function LocalInitialize return boolean is ------------------------------------------------------------ begin LocalInitialize(MIN_NUM_AL_IDS) ; return TRUE ; end function LocalInitialize ; constant CONSTRUCT_ALERT_DATA_STRUCTURE : boolean := LocalInitialize ; ------------------------------------------------------------ procedure Deallocate is ------------------------------------------------------------ begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop Deallocate(AlertLogPtr(i).Name) ; Deallocate(AlertLogPtr(i)) ; end loop ; deallocate(AlertLogPtr) ; -- Free up space used by protected types within AlertLogPkg AlertPrefixVar.Deallocate ; LogPrefixVar.Deallocate ; ReportPrefixVar.Deallocate ; DoneNameVar.Deallocate ; PassNameVar.Deallocate ; FailNameVar.Deallocate ; -- Restore variables to their initial state NumAlertLogIDsVar := 0 ; NumAllocatedAlertLogIDsVar := 0 ; GlobalAlertEnabledVar := TRUE ; -- Allows turn off and on AffirmCheckCountVar := 0 ; FailOnWarningVar := TRUE ; FailOnDisabledErrorsVar := TRUE ; ReportHierarchyVar := TRUE ; FoundReportHierVar := FALSE ; FoundAlertHierVar := FALSE ; WriteAlertLevelVar := TRUE ; WriteAlertNameVar := TRUE ; WriteAlertTimeVar := TRUE ; WriteLogLevelVar := TRUE ; WriteLogNameVar := TRUE ; WriteLogTimeVar := TRUE ; end procedure Deallocate ; ------------------------------------------------------------ -- PT Local. procedure GrowAlertStructure (NewNumAlertLogIDs : AlertLogIDType) is ------------------------------------------------------------ variable oldAlertLogPtr : AlertLogArrayPtrType ; begin if NumAllocatedAlertLogIDsVar = 0 then Initialize (NewNumAlertLogIDs) ; -- Construct initial structure else oldAlertLogPtr := AlertLogPtr ; AlertLogPtr := new AlertLogArrayType(ALERTLOG_BASE_ID to NewNumAlertLogIDs) ; AlertLogPtr(ALERTLOG_BASE_ID to NumAlertLogIDsVar) := oldAlertLogPtr(ALERTLOG_BASE_ID to NumAlertLogIDsVar) ; deallocate(oldAlertLogPtr) ; end if ; NumAllocatedAlertLogIDsVar := NewNumAlertLogIDs ; end procedure GrowAlertStructure ; ------------------------------------------------------------ -- Sets a AlertLogPtr to a particular size -- Use for small bins to save space or large bins to -- suppress the resize and copy as a CovBin autosizes. procedure SetNumAlertLogIDs (NewNumAlertLogIDs : AlertLogIDType) is ------------------------------------------------------------ variable oldAlertLogPtr : AlertLogArrayPtrType ; begin if NewNumAlertLogIDs > NumAllocatedAlertLogIDsVar then GrowAlertStructure(NewNumAlertLogIDs) ; end if; end procedure SetNumAlertLogIDs ; ------------------------------------------------------------ -- PT Local impure function GetNextAlertLogID return AlertLogIDType is ------------------------------------------------------------ variable NewNumAlertLogIDs : AlertLogIDType ; begin NewNumAlertLogIDs := NumAlertLogIDsVar + 1 ; if NewNumAlertLogIDs > NumAllocatedAlertLogIDsVar then GrowAlertStructure(NumAllocatedAlertLogIDsVar + MIN_NUM_AL_IDS) ; end if ; NumAlertLogIDsVar := NewNumAlertLogIDs ; return NumAlertLogIDsVar ; end function GetNextAlertLogID ; ------------------------------------------------------------ impure function FindAlertLogID(Name : string ) return AlertLogIDType is ------------------------------------------------------------ begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop if Name = AlertLogPtr(i).Name.all then return i ; end if ; end loop ; return ALERTLOG_ID_NOT_FOUND ; -- not found end function FindAlertLogID ; ------------------------------------------------------------ impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is ------------------------------------------------------------ variable CurParentID : AlertLogIDType ; begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop CurParentID := AlertLogPtr(i).ParentID ; if Name = AlertLogPtr(i).Name.all and (CurParentID = ParentID or CurParentID = ALERTLOG_ID_NOT_ASSIGNED or ParentID = ALERTLOG_ID_NOT_ASSIGNED) then return i ; end if ; end loop ; return ALERTLOG_ID_NOT_FOUND ; -- not found end function FindAlertLogID ; ------------------------------------------------------------ impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType is ------------------------------------------------------------ variable ResultID : AlertLogIDType ; begin ResultID := FindAlertLogID(Name, ParentID) ; if ResultID /= ALERTLOG_ID_NOT_FOUND then -- found it, set ParentID if AlertLogPtr(ResultID).ParentID = ALERTLOG_ID_NOT_ASSIGNED then AlertLogPtr(ResultID).ParentID := ParentID ; -- else -- do not update as ParentIDs are either same or input ParentID = ALERTLOG_ID_NOT_ASSIGNED end if ; else ResultID := GetNextAlertLogID ; NewAlertLogRec(ResultID, Name, ParentID) ; FoundAlertHierVar := TRUE ; if CreateHierarchy then FoundReportHierVar := TRUE ; end if ; end if ; return ResultID ; end function GetAlertLogID ; ------------------------------------------------------------ impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType is ------------------------------------------------------------ begin return AlertLogPtr(AlertLogID).ParentID ; end function GetAlertLogParentID ; ------------------------------------------------------------ ------------------------------------------------------------ -- Accessor Methods ------------------------------------------------------------ ------------------------------------------------------------ procedure SetGlobalAlertEnable (A : boolean := TRUE) is ------------------------------------------------------------ begin GlobalAlertEnabledVar := A ; end procedure SetGlobalAlertEnable ; ------------------------------------------------------------ impure function GetGlobalAlertEnable return boolean is ------------------------------------------------------------ begin return GlobalAlertEnabledVar ; end function GetGlobalAlertEnable ; ------------------------------------------------------------ procedure IncAffirmCount is ------------------------------------------------------------ begin if GlobalAlertEnabledVar then AffirmCheckCountVar := AffirmCheckCountVar + 1 ; end if ; end procedure IncAffirmCount ; ------------------------------------------------------------ impure function GetAffirmCount return natural is ------------------------------------------------------------ begin return AffirmCheckCountVar ; end function GetAffirmCount ; ------------------------------------------------------------ -- PT LOCAL procedure SetOneStopCount( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer ) is begin if AlertLogPtr(AlertLogID).AlertStopCount(Level) = integer'right then AlertLogPtr(AlertLogID).AlertStopCount(Level) := Count ; else AlertLogPtr(AlertLogID).AlertStopCount(Level) := AlertLogPtr(AlertLogID).AlertStopCount(Level) + Count ; end if ; end procedure SetOneStopCount ; ------------------------------------------------------------ procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is ------------------------------------------------------------ begin SetOneStopCount(AlertLogID, Level, Count) ; if AlertLogID /= ALERTLOG_BASE_ID then SetAlertStopCount(AlertLogPtr(AlertLogID).ParentID, Level, Count) ; end if ; end procedure SetAlertStopCount ; ------------------------------------------------------------ impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is ------------------------------------------------------------ begin return AlertLogPtr(AlertLogID).AlertStopCount(Level) ; end function GetAlertStopCount ; ------------------------------------------------------------ procedure SetAlertEnable(Level : AlertType ; Enable : boolean) is ------------------------------------------------------------ begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop AlertLogPtr(i).AlertEnabled(Level) := Enable ; end loop ; end procedure SetAlertEnable ; ------------------------------------------------------------ procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is ------------------------------------------------------------ begin AlertLogPtr(AlertLogID).AlertEnabled(Level) := Enable ; if DescendHierarchy then for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then SetAlertEnable(i, Level, Enable, DescendHierarchy) ; end if ; end loop ; end if ; end procedure SetAlertEnable ; ------------------------------------------------------------ impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean is ------------------------------------------------------------ begin return AlertLogPtr(AlertLogID).AlertEnabled(Level) ; end function GetAlertEnable ; ------------------------------------------------------------ procedure SetLogEnable(Level : LogType ; Enable : boolean) is ------------------------------------------------------------ begin for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop AlertLogPtr(i).LogEnabled(Level) := Enable ; end loop ; end procedure SetLogEnable ; ------------------------------------------------------------ procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is ------------------------------------------------------------ begin AlertLogPtr(AlertLogID).LogEnabled(Level) := Enable ; if DescendHierarchy then for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then SetLogEnable(i, Level, Enable, DescendHierarchy) ; end if ; end loop ; end if ; end procedure SetLogEnable ; ------------------------------------------------------------ impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is ------------------------------------------------------------ begin if Level = ALWAYS then return TRUE ; else return AlertLogPtr(AlertLogID).LogEnabled(Level) ; end if ; end function GetLogEnable ; ------------------------------------------------------------ -- PT Local procedure PrintLogLevels( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Prefix : string ; IndentAmount : integer ) is variable buf : line ; begin write(buf, Prefix & " " & LeftJustify(AlertLogPtr(AlertLogID).Name.all, ReportJustifyAmountVar - IndentAmount)) ; for i in LogIndexType loop if AlertLogPtr(AlertLogID).LogEnabled(i) then write(buf, " " & to_string(i)) ; end if ; end loop ; WriteLine(buf) ; for i in AlertLogID+1 to NumAlertLogIDsVar loop if AlertLogID = AlertLogPtr(i).ParentID then PrintLogLevels( AlertLogID => i, Prefix => Prefix & " ", IndentAmount => IndentAmount + 2 ) ; end if ; end loop ; end procedure PrintLogLevels ; ------------------------------------------------------------ procedure ReportLogEnables is ------------------------------------------------------------ begin if ReportJustifyAmountVar <= 0 then SetJustify ; end if ; PrintLogLevels(ALERTLOG_BASE_ID, "", 0) ; end procedure ReportLogEnables ; ------------------------------------------------------------ procedure SetAlertLogOptions ( ------------------------------------------------------------ FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) is begin if FailOnWarning /= OPT_INIT_PARM_DETECT then FailOnWarningVar := IsEnabled(FailOnWarning) ; end if ; if FailOnDisabledErrors /= OPT_INIT_PARM_DETECT then FailOnDisabledErrorsVar := IsEnabled(FailOnDisabledErrors) ; end if ; if ReportHierarchy /= OPT_INIT_PARM_DETECT then ReportHierarchyVar := IsEnabled(ReportHierarchy) ; end if ; if WriteAlertLevel /= OPT_INIT_PARM_DETECT then WriteAlertLevelVar := IsEnabled(WriteAlertLevel) ; end if ; if WriteAlertName /= OPT_INIT_PARM_DETECT then WriteAlertNameVar := IsEnabled(WriteAlertName) ; end if ; if WriteAlertTime /= OPT_INIT_PARM_DETECT then WriteAlertTimeVar := IsEnabled(WriteAlertTime) ; end if ; if WriteLogLevel /= OPT_INIT_PARM_DETECT then WriteLogLevelVar := IsEnabled(WriteLogLevel) ; end if ; if WriteLogName /= OPT_INIT_PARM_DETECT then WriteLogNameVar := IsEnabled(WriteLogName) ; end if ; if WriteLogTime /= OPT_INIT_PARM_DETECT then WriteLogTimeVar := IsEnabled(WriteLogTime) ; end if ; if AlertPrefix /= OSVVM_STRING_INIT_PARM_DETECT then AlertPrefixVar.Set(AlertPrefix) ; end if ; if LogPrefix /= OSVVM_STRING_INIT_PARM_DETECT then LogPrefixVar.Set(LogPrefix) ; end if ; if ReportPrefix /= OSVVM_STRING_INIT_PARM_DETECT then ReportPrefixVar.Set(ReportPrefix) ; end if ; if DoneName /= OSVVM_STRING_INIT_PARM_DETECT then DoneNameVar.Set(DoneName) ; end if ; if PassName /= OSVVM_STRING_INIT_PARM_DETECT then PassNameVar.Set(PassName) ; end if ; if FailName /= OSVVM_STRING_INIT_PARM_DETECT then FailNameVar.Set(FailName) ; end if ; end procedure SetAlertLogOptions ; ------------------------------------------------------------ procedure ReportAlertLogOptions is ------------------------------------------------------------ variable buf : line ; begin -- Boolean Values swrite(buf, "ReportAlertLogOptions" & LF ) ; swrite(buf, "---------------------" & LF ) ; swrite(buf, "FailOnWarningVar: " & to_string(FailOnWarningVar ) & LF ) ; swrite(buf, "FailOnDisabledErrorsVar: " & to_string(FailOnDisabledErrorsVar ) & LF ) ; swrite(buf, "ReportHierarchyVar: " & to_string(ReportHierarchyVar ) & LF ) ; swrite(buf, "FoundReportHierVar: " & to_string(FoundReportHierVar ) & LF ) ; -- Not set by user swrite(buf, "FoundAlertHierVar: " & to_string(FoundAlertHierVar ) & LF ) ; -- Not set by user swrite(buf, "WriteAlertLevelVar: " & to_string(WriteAlertLevelVar ) & LF ) ; swrite(buf, "WriteAlertNameVar: " & to_string(WriteAlertNameVar ) & LF ) ; swrite(buf, "WriteAlertTimeVar: " & to_string(WriteAlertTimeVar ) & LF ) ; swrite(buf, "WriteLogLevelVar: " & to_string(WriteLogLevelVar ) & LF ) ; swrite(buf, "WriteLogNameVar: " & to_string(WriteLogNameVar ) & LF ) ; swrite(buf, "WriteLogTimeVar: " & to_string(WriteLogTimeVar ) & LF ) ; -- String swrite(buf, "AlertPrefixVar: " & string'(AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX)) & LF ) ; swrite(buf, "LogPrefixVar: " & string'(LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX)) & LF ) ; swrite(buf, "ReportPrefixVar: " & ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & LF ) ; swrite(buf, "DoneNameVar: " & ResolveOsvvmDoneName(DoneNameVar.GetOpt) & LF ) ; swrite(buf, "PassNameVar: " & ResolveOsvvmPassName(PassNameVar.GetOpt) & LF ) ; swrite(buf, "FailNameVar: " & ResolveOsvvmFailName(FailNameVar.GetOpt) & LF ) ; writeline(buf) ; end procedure ReportAlertLogOptions ; ------------------------------------------------------------ impure function GetAlertLogFailOnWarning return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(FailOnWarningVar) ; end function GetAlertLogFailOnWarning ; ------------------------------------------------------------ impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(FailOnDisabledErrorsVar) ; end function GetAlertLogFailOnDisabledErrors ; ------------------------------------------------------------ impure function GetAlertLogReportHierarchy return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(ReportHierarchyVar) ; end function GetAlertLogReportHierarchy ; ------------------------------------------------------------ impure function GetAlertLogFoundReportHier return boolean is ------------------------------------------------------------ begin return FoundReportHierVar ; end function GetAlertLogFoundReportHier ; ------------------------------------------------------------ impure function GetAlertLogFoundAlertHier return boolean is ------------------------------------------------------------ begin return FoundAlertHierVar ; end function GetAlertLogFoundAlertHier ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteAlertLevelVar) ; end function GetAlertLogWriteAlertLevel ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertName return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteAlertNameVar) ; end function GetAlertLogWriteAlertName ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertTime return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteAlertTimeVar) ; end function GetAlertLogWriteAlertTime ; ------------------------------------------------------------ impure function GetAlertLogWriteLogLevel return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteLogLevelVar) ; end function GetAlertLogWriteLogLevel ; ------------------------------------------------------------ impure function GetAlertLogWriteLogName return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteLogNameVar) ; end function GetAlertLogWriteLogName ; ------------------------------------------------------------ impure function GetAlertLogWriteLogTime return AlertLogOptionsType is ------------------------------------------------------------ begin return to_OsvvmOptionsType(WriteLogTimeVar) ; end function GetAlertLogWriteLogTime ; ------------------------------------------------------------ impure function GetAlertLogAlertPrefix return string is ------------------------------------------------------------ begin return AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ; end function GetAlertLogAlertPrefix ; ------------------------------------------------------------ impure function GetAlertLogLogPrefix return string is ------------------------------------------------------------ begin return LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX) ; end function GetAlertLogLogPrefix ; ------------------------------------------------------------ impure function GetAlertLogReportPrefix return string is ------------------------------------------------------------ begin return ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ; end function GetAlertLogReportPrefix ; ------------------------------------------------------------ impure function GetAlertLogDoneName return string is ------------------------------------------------------------ begin return ResolveOsvvmDoneName(DoneNameVar.GetOpt) ; end function GetAlertLogDoneName ; ------------------------------------------------------------ impure function GetAlertLogPassName return string is ------------------------------------------------------------ begin return ResolveOsvvmPassName(PassNameVar.GetOpt) ; end function GetAlertLogPassName ; ------------------------------------------------------------ impure function GetAlertLogFailName return string is ------------------------------------------------------------ begin return ResolveOsvvmFailName(FailNameVar.GetOpt) ; end function GetAlertLogFailName ; end protected body AlertLogStructPType ; shared variable AlertLogStruct : AlertLogStructPType ; ------------------------------------------------------------ procedure Alert( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is begin AlertLogStruct.Alert(AlertLogID, Message, Level) ; end procedure alert ; ------------------------------------------------------------ procedure Alert( Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ; end procedure alert ; ------------------------------------------------------------ procedure IncAlertCount( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; Level : AlertType := ERROR ) is begin AlertLogStruct.IncAlertCount(AlertLogID, Level) ; end procedure IncAlertCount ; ------------------------------------------------------------ procedure IncAlertCount( Level : AlertType := ERROR ) is ------------------------------------------------------------ begin AlertLogStruct.IncAlertCount(ALERT_DEFAULT_ID, Level) ; end procedure IncAlertCount ; ------------------------------------------------------------ procedure AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if condition then AlertLogStruct.Alert(AlertLogID , Message, Level) ; end if ; end procedure AlertIf ; ------------------------------------------------------------ procedure AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if condition then AlertLogStruct.Alert(ALERT_DEFAULT_ID , Message, Level) ; end if ; end procedure AlertIf ; ------------------------------------------------------------ -- useful in a loop: exit when AlertIf( not ReadValid, failure, "Read Failed") ; impure function AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is ------------------------------------------------------------ begin if condition then AlertLogStruct.Alert(AlertLogID , Message, Level) ; end if ; return condition ; end function AlertIf ; ------------------------------------------------------------ impure function AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is ------------------------------------------------------------ begin if condition then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ; end if ; return condition ; end function AlertIf ; ------------------------------------------------------------ procedure AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if not condition then AlertLogStruct.Alert(AlertLogID, Message, Level) ; end if ; end procedure AlertIfNot ; ------------------------------------------------------------ procedure AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if not condition then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ; end if ; end procedure AlertIfNot ; ------------------------------------------------------------ -- useful in a loop: exit when AlertIfNot( not ReadValid, failure, "Read Failed") ; impure function AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is ------------------------------------------------------------ begin if not condition then AlertLogStruct.Alert(AlertLogID, Message, Level) ; end if ; return not condition ; end function AlertIfNot ; ------------------------------------------------------------ impure function AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is ------------------------------------------------------------ begin if not condition then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ; end if ; return not condition ; end function AlertIfNot ; ------------------------------------------------------------ -- AlertIfEqual with AlertLogID ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ -- AlertIfEqual without AlertLogID ------------------------------------------------------------ procedure AlertIfEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ procedure AlertIfEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L = R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfEqual ; ------------------------------------------------------------ -- AlertIfNotEqual with AlertLogID ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ -- AlertIfNotEqual without AlertLogID ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L ?/= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & L & " R = " & R, Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ procedure AlertIfNotEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) is ------------------------------------------------------------ begin if L /= R then AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ; end if ; end procedure AlertIfNotEqual ; ------------------------------------------------------------ -- Local procedure LocalAlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string ; Level : AlertType ; Valid : out boolean ) is -- Simple diff. ------------------------------------------------------------ variable Buf1, Buf2 : line ; variable File1Done, File2Done : boolean ; variable LineCount : integer := 0 ; begin ReadLoop : loop File1Done := EndFile(File1) ; File2Done := EndFile(File2) ; exit ReadLoop when File1Done or File2Done ; ReadLine(File1, Buf1) ; ReadLine(File2, Buf2) ; LineCount := LineCount + 1 ; if Buf1.all /= Buf2.all then AlertLogStruct.Alert(AlertLogID , Message & " File miscompare on line " & to_string(LineCount), Level) ; exit ReadLoop ; end if ; end loop ReadLoop ; if File1Done /= File2Done then if not File1Done then AlertLogStruct.Alert(AlertLogID , Message & " File1 longer than File2 " & to_string(LineCount), Level) ; end if ; if not File2Done then AlertLogStruct.Alert(AlertLogID , Message & " File2 longer than File1 " & to_string(LineCount), Level) ; end if ; end if; if File1Done and File2Done then Valid := TRUE ; else Valid := FALSE ; end if ; end procedure LocalAlertIfDiff ; ------------------------------------------------------------ -- Local procedure LocalAlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string ; Level : AlertType ; Valid : out boolean ) is -- Open files and call AlertIfDiff[text, ...] ------------------------------------------------------------ file FileID1, FileID2 : text ; variable status1, status2 : file_open_status ; begin Valid := FALSE ; file_open(status1, FileID1, Name1, READ_MODE) ; file_open(status2, FileID2, Name2, READ_MODE) ; if status1 = OPEN_OK and status2 = OPEN_OK then LocalAlertIfDiff (AlertLogID, FileID1, FileID2, Message & " " & Name1 & " /= " & Name2 & ", ", Level, Valid) ; else if status1 /= OPEN_OK then AlertLogStruct.Alert(AlertLogID , Message & " File, " & Name1 & ", did not open", Level) ; end if ; if status2 /= OPEN_OK then AlertLogStruct.Alert(AlertLogID , Message & " File, " & Name2 & ", did not open", Level) ; end if ; end if; end procedure LocalAlertIfDiff ; ------------------------------------------------------------ procedure AlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) is -- Open files and call AlertIfDiff[text, ...] ------------------------------------------------------------ variable Valid : boolean ; begin LocalAlertIfDiff (AlertLogID, Name1, Name2, Message, Level, Valid) ; end procedure AlertIfDiff ; ------------------------------------------------------------ procedure AlertIfDiff (Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) is ------------------------------------------------------------ variable Valid : boolean ; begin LocalAlertIfDiff (ALERT_DEFAULT_ID, Name1, Name2, Message, Level, Valid) ; end procedure AlertIfDiff ; ------------------------------------------------------------ procedure AlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) is -- Simple diff. ------------------------------------------------------------ variable Valid : boolean ; begin LocalAlertIfDiff (AlertLogID, File1, File2, Message, Level, Valid ) ; end procedure AlertIfDiff ; ------------------------------------------------------------ procedure AlertIfDiff (file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) is ------------------------------------------------------------ variable Valid : boolean ; begin LocalAlertIfDiff (ALERT_DEFAULT_ID, File1, File2, Message, Level, Valid ) ; end procedure AlertIfDiff ; ------------------------------------------------------------ procedure AffirmIf( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage : string ; ExpectedMessage : string ; Enable : boolean := FALSE -- override internal enable ) is begin AlertLogStruct.IncAffirmCount ; -- increment check count if condition then -- passed AlertLogStruct.Log(AlertLogID, ReceivedMessage, PASSED, Enable) ; else AlertLogStruct.Alert(AlertLogID, ReceivedMessage & ExpectedMessage, ERROR) ; end if ; end procedure AffirmIf ; ------------------------------------------------------------ procedure AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, condition, ReceivedMessage, ExpectedMessage, Enable) ; end procedure AffirmIf ; ------------------------------------------------------------ impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is ------------------------------------------------------------ begin AffirmIf(AlertLogID, condition, ReceivedMessage, ExpectedMessage, Enable) ; return condition ; end function AffirmIf ; ------------------------------------------------------------ impure function AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, condition, ReceivedMessage, ExpectedMessage, Enable) ; return condition ; end function AffirmIf ; ------------------------------------------------------------ procedure AffirmIf( ------------------------------------------------------------ AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE -- override internal enable ) is begin AlertLogStruct.IncAffirmCount ; -- increment check count if condition then -- passed AlertLogStruct.Log(AlertLogID, Message, PASSED, Enable) ; else AlertLogStruct.Alert(AlertLogID, Message, ERROR) ; end if ; end procedure AffirmIf ; ------------------------------------------------------------ procedure AffirmIf(condition : boolean ; Message : string ; Enable : boolean := FALSE) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, condition, Message, Enable) ; end procedure AffirmIf; ------------------------------------------------------------ -- useful in a loop: exit when AffirmIf( ID, not ReadValid, "Read Failed") ; impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is ------------------------------------------------------------ begin AffirmIf(AlertLogID, condition, Message, Enable) ; return condition ; end function AffirmIf ; ------------------------------------------------------------ impure function AffirmIf( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, condition, Message, Enable) ; return condition ; end function AffirmIf ; ------------------------------------------------------------ ------------------------------------------------------------ procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(AlertLogID, not condition, ReceivedMessage, ExpectedMessage, Enable) ; end procedure AffirmIfNot ; ------------------------------------------------------------ procedure AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, not condition, ReceivedMessage, ExpectedMessage, Enable) ; end procedure AffirmIfNot ; ------------------------------------------------------------ -- useful in a loop: exit when AffirmIfNot( not ReadValid, failure, "Read Failed") ; impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is ------------------------------------------------------------ begin AffirmIf(AlertLogID, not condition, ReceivedMessage, ExpectedMessage, Enable) ; return not condition ; end function AffirmIfNot ; ------------------------------------------------------------ impure function AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, not condition, ReceivedMessage, ExpectedMessage, Enable) ; return not condition ; end function AffirmIfNot ; ------------------------------------------------------------ procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(AlertLogID, not condition, Message, Enable) ; end procedure AffirmIfNot ; ------------------------------------------------------------ procedure AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, not condition, Message, Enable) ; end procedure AffirmIfNot ; ------------------------------------------------------------ -- useful in a loop: exit when AffirmIfNot( not ReadValid, failure, "Read Failed") ; impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is ------------------------------------------------------------ begin AffirmIf(AlertLogID, not condition, Message, Enable) ; return not condition ; end function AffirmIfNot ; ------------------------------------------------------------ impure function AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, not condition, Message, Enable) ; return not condition ; end function AffirmIfNot ; ------------------------------------------------------------ ------------------------------------------------------------ procedure AffirmPassed( AlertLogID : AlertLogIDType ; Message : string ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(AlertLogID, TRUE, Message, Enable) ; end procedure AffirmPassed ; ------------------------------------------------------------ procedure AffirmPassed( Message : string ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, TRUE, Message, Enable) ; end procedure AffirmPassed ; ------------------------------------------------------------ procedure AffirmError( AlertLogID : AlertLogIDType ; Message : string ) is ------------------------------------------------------------ begin AffirmIf(AlertLogID, FALSE, Message, FALSE) ; end procedure AffirmError ; ------------------------------------------------------------ procedure AffirmError( Message : string ) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, FALSE, Message, FALSE) ; end procedure AffirmError ; -- With AlertLogID ------------------------------------------------------------ procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(AlertLogID, ??(Received ?= Expected), Message & " Received : " & to_string(Received), " ?= Expected : " & to_string(Expected), Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(AlertLogID, ??(Received ?= Expected), Message & " Received : " & to_hstring(Received), " ?= Expected : " & to_hstring(Expected), Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(AlertLogID, ??(Received ?= Expected), Message & " Received : " & to_hstring(Received), " ?= Expected : " & to_hstring(Expected), Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(AlertLogID, ??(Received ?= Expected), Message & " Received : " & to_hstring(Received), " ?= Expected : " & to_hstring(Expected), Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(AlertLogID, Received = Expected, Message & " Received : " & to_string(Received), " = Expected : " & to_string(Expected), Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(AlertLogID, Received = Expected, Message & " Received : " & to_string(Received, 4), " = Expected : " & to_string(Expected, 4), Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(AlertLogID, Received = Expected, Message & " Received : " & to_string(Received), " = Expected : " & to_string(Expected), Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(AlertLogID, Received = Expected, Message & " Received : " & Received, " = Expected : " & Expected, Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(AlertLogID, Received = Expected, Message & " Received : " & to_string(Received), " = Expected : " & to_string(Expected), Enable) ; end procedure AffirmIfEqual ; -- Without AlertLogID ------------------------------------------------------------ procedure AffirmIfEqual( Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, ??(Received ?= Expected), Message & " Received : " & to_string(Received), " ?= Expected : " & to_string(Expected), Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfEqual( Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, ??(Received ?= Expected), Message & " Received : " & to_string(Received), " ?= Expected : " & to_string(Expected), Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfEqual( Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, ??(Received ?= Expected), Message & " Received : " & to_string(Received), " ?= Expected : " & to_string(Expected), Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfEqual( Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, ??(Received ?= Expected), Message & " Received : " & to_string(Received), " ?= Expected : " & to_string(Expected), Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfEqual( Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, Received = Expected, Message & " Received : " & to_string(Received), " = Expected : " & to_string(Expected), Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfEqual( Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, Received = Expected, Message & " Received : " & to_string(Received, 4), " = Expected : " & to_string(Expected, 4), Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfEqual( Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, Received = Expected, Message & " Received : " & to_string(Received), " = Expected : " & to_string(Expected), Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfEqual( Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, Received = Expected, Message & " Received : " & Received, " = Expected : " & Expected, Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfEqual( Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ begin AffirmIf(ALERT_DEFAULT_ID, Received = Expected, Message & " Received : " & to_string(Received), " = Expected : " & to_string(Expected), Enable) ; end procedure AffirmIfEqual ; ------------------------------------------------------------ procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) is -- Open files and call AffirmIfDiff[text, ...] ------------------------------------------------------------ variable Valid : boolean ; begin LocalAlertIfDiff (AlertLogID, Name1, Name2, Message, ERROR, Valid) ; if Valid then AlertLogStruct.Log(AlertLogID, Message & " " & Name1 & " = " & Name2, PASSED, Enable) ; end if ; end procedure AffirmIfDiff ; ------------------------------------------------------------ procedure AffirmIfDiff (Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ variable Valid : boolean ; begin LocalAlertIfDiff (ALERT_DEFAULT_ID, Name1, Name2, Message, ERROR, Valid) ; if Valid then AlertLogStruct.Log(ALERT_DEFAULT_ID, Message & " " & Name1 & " = " & Name2, PASSED, Enable) ; end if ; end procedure AffirmIfDiff ; ------------------------------------------------------------ procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) is -- Simple diff. ------------------------------------------------------------ variable Valid : boolean ; begin LocalAlertIfDiff (AlertLogID, File1, File2, Message, ERROR, Valid ) ; if Valid then AlertLogStruct.Log(AlertLogID, Message, PASSED, Enable) ; end if ; end procedure AffirmIfDiff ; ------------------------------------------------------------ procedure AffirmIfDiff (file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) is ------------------------------------------------------------ variable Valid : boolean ; begin LocalAlertIfDiff (ALERT_DEFAULT_ID, File1, File2, Message, ERROR, Valid ) ; if Valid then AlertLogStruct.Log(ALERT_DEFAULT_ID, Message, PASSED, Enable) ; end if ; end procedure AffirmIfDiff ; ------------------------------------------------------------ procedure SetAlertLogJustify is ------------------------------------------------------------ begin AlertLogStruct.SetJustify ; end procedure SetAlertLogJustify ; ------------------------------------------------------------ procedure ReportAlerts ( Name : String ; AlertCount : AlertCountType ) is ------------------------------------------------------------ begin AlertLogStruct.ReportAlerts(Name, AlertCount) ; end procedure ReportAlerts ; ------------------------------------------------------------ procedure ReportAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) is ------------------------------------------------------------ begin AlertLogStruct.ReportAlerts(Name, AlertLogID, ExternalErrors, TRUE) ; end procedure ReportAlerts ; ------------------------------------------------------------ procedure ReportNonZeroAlerts ( Name : string := OSVVM_STRING_INIT_PARM_DETECT ; AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ; ExternalErrors : AlertCountType := (others => 0) ) is ------------------------------------------------------------ begin AlertLogStruct.ReportAlerts(Name, AlertLogID, ExternalErrors, FALSE) ; end procedure ReportNonZeroAlerts ; ------------------------------------------------------------ procedure ClearAlerts is ------------------------------------------------------------ begin AlertLogStruct.ClearAlerts ; end procedure ClearAlerts ; ------------------------------------------------------------ function "ABS" (L : AlertCountType) return AlertCountType is ------------------------------------------------------------ variable Result : AlertCountType ; begin Result(FAILURE) := ABS( L(FAILURE) ) ; Result(ERROR) := ABS( L(ERROR) ) ; Result(WARNING) := ABS( L(WARNING) ); return Result ; end function "ABS" ; ------------------------------------------------------------ function "+" (L, R : AlertCountType) return AlertCountType is ------------------------------------------------------------ variable Result : AlertCountType ; begin Result(FAILURE) := L(FAILURE) + R(FAILURE) ; Result(ERROR) := L(ERROR) + R(ERROR) ; Result(WARNING) := L(WARNING) + R(WARNING) ; return Result ; end function "+" ; ------------------------------------------------------------ function "-" (L, R : AlertCountType) return AlertCountType is ------------------------------------------------------------ variable Result : AlertCountType ; begin Result(FAILURE) := L(FAILURE) - R(FAILURE) ; Result(ERROR) := L(ERROR) - R(ERROR) ; Result(WARNING) := L(WARNING) - R(WARNING) ; return Result ; end function "-" ; ------------------------------------------------------------ function "-" (R : AlertCountType) return AlertCountType is ------------------------------------------------------------ variable Result : AlertCountType ; begin Result(FAILURE) := - R(FAILURE) ; Result(ERROR) := - R(ERROR) ; Result(WARNING) := - R(WARNING) ; return Result ; end function "-" ; ------------------------------------------------------------ impure function SumAlertCount(AlertCount: AlertCountType) return integer is ------------------------------------------------------------ begin -- Using ABS ensures correct expected error handling. return abs(AlertCount(FAILURE)) + abs(AlertCount(ERROR)) + abs(AlertCount(WARNING)) ; end function SumAlertCount ; ------------------------------------------------------------ impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertCount(AlertLogID) ; end function GetAlertCount ; ------------------------------------------------------------ impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer is ------------------------------------------------------------ begin return SumAlertCount(AlertLogStruct.GetAlertCount(AlertLogID)) ; end function GetAlertCount ; ------------------------------------------------------------ impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is ------------------------------------------------------------ begin return AlertLogStruct.GetEnabledAlertCount(AlertLogID) ; end function GetEnabledAlertCount ; ------------------------------------------------------------ impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer is ------------------------------------------------------------ begin return SumAlertCount(AlertLogStruct.GetEnabledAlertCount(AlertLogID)) ; end function GetEnabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount return AlertCountType is ------------------------------------------------------------ begin return AlertLogStruct.GetDisabledAlertCount ; end function GetDisabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount return integer is ------------------------------------------------------------ begin return SumAlertCount(AlertLogStruct.GetDisabledAlertCount) ; end function GetDisabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is ------------------------------------------------------------ begin return AlertLogStruct.GetDisabledAlertCount(AlertLogID) ; end function GetDisabledAlertCount ; ------------------------------------------------------------ impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return integer is ------------------------------------------------------------ begin return SumAlertCount(AlertLogStruct.GetDisabledAlertCount(AlertLogID)) ; end function GetDisabledAlertCount ; ------------------------------------------------------------ procedure Log( AlertLogID : AlertLogIDType ; Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE -- override internal enable ) is begin AlertLogStruct.Log(AlertLogID, Message, Level, Enable) ; end procedure log ; ------------------------------------------------------------ procedure Log( Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE) is ------------------------------------------------------------ begin AlertLogStruct.Log(LOG_DEFAULT_ID, Message, Level, Enable) ; end procedure log ; ------------------------------------------------------------ procedure SetAlertLogName(Name : string ) is ------------------------------------------------------------ begin AlertLogStruct.SetAlertLogName(Name) ; end procedure SetAlertLogName ; ------------------------------------------------------------ impure function GetAlertLogName(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogName(AlertLogID) ; end GetAlertLogName ; ------------------------------------------------------------ procedure DeallocateAlertLogStruct is ------------------------------------------------------------ begin AlertLogStruct.Deallocate ; end procedure DeallocateAlertLogStruct ; ------------------------------------------------------------ procedure InitializeAlertLogStruct is ------------------------------------------------------------ begin AlertLogStruct.Initialize ; end procedure InitializeAlertLogStruct ; ------------------------------------------------------------ impure function FindAlertLogID(Name : string ) return AlertLogIDType is ------------------------------------------------------------ begin return AlertLogStruct.FindAlertLogID(Name) ; end function FindAlertLogID ; ------------------------------------------------------------ impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is ------------------------------------------------------------ begin return AlertLogStruct.FindAlertLogID(Name, ParentID) ; end function FindAlertLogID ; ------------------------------------------------------------ impure function GetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogID(Name, ParentID, CreateHierarchy ) ; end function GetAlertLogID ; ------------------------------------------------------------ impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogParentID(AlertLogID) ; end function GetAlertLogParentID ; ------------------------------------------------------------ procedure SetGlobalAlertEnable (A : boolean := TRUE) is ------------------------------------------------------------ begin AlertLogStruct.SetGlobalAlertEnable(A) ; end procedure SetGlobalAlertEnable ; ------------------------------------------------------------ -- Set using constant. Set before code runs. impure function SetGlobalAlertEnable (A : boolean := TRUE) return boolean is ------------------------------------------------------------ begin AlertLogStruct.SetGlobalAlertEnable(A) ; return A ; end function SetGlobalAlertEnable ; ------------------------------------------------------------ impure function GetGlobalAlertEnable return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetGlobalAlertEnable ; end function GetGlobalAlertEnable ; ------------------------------------------------------------ procedure IncAffirmCount is ------------------------------------------------------------ begin AlertLogStruct.IncAffirmCount ; end procedure IncAffirmCount ; ------------------------------------------------------------ impure function GetAffirmCount return natural is ------------------------------------------------------------ begin return AlertLogStruct.GetAffirmCount ; end function GetAffirmCount ; ------------------------------------------------------------ procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is ------------------------------------------------------------ begin AlertLogStruct.SetAlertStopCount(AlertLogID, Level, Count) ; end procedure SetAlertStopCount ; ------------------------------------------------------------ procedure SetAlertStopCount(Level : AlertType ; Count : integer) is ------------------------------------------------------------ begin AlertLogStruct.SetAlertStopCount(ALERTLOG_BASE_ID, Level, Count) ; end procedure SetAlertStopCount ; ------------------------------------------------------------ impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertStopCount(AlertLogID, Level) ; end function GetAlertStopCount ; ------------------------------------------------------------ impure function GetAlertStopCount(Level : AlertType) return integer is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertStopCount(ALERTLOG_BASE_ID, Level) ; end function GetAlertStopCount ; ------------------------------------------------------------ procedure SetAlertEnable(Level : AlertType ; Enable : boolean) is ------------------------------------------------------------ begin AlertLogStruct.SetAlertEnable(Level, Enable) ; end procedure SetAlertEnable ; ------------------------------------------------------------ procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is ------------------------------------------------------------ begin AlertLogStruct.SetAlertEnable(AlertLogID, Level, Enable, DescendHierarchy) ; end procedure SetAlertEnable ; ------------------------------------------------------------ impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertEnable(AlertLogID, Level) ; end function GetAlertEnable ; ------------------------------------------------------------ impure function GetAlertEnable(Level : AlertType) return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertEnable(ALERT_DEFAULT_ID, Level) ; end function GetAlertEnable ; ------------------------------------------------------------ procedure SetLogEnable(Level : LogType ; Enable : boolean) is ------------------------------------------------------------ begin AlertLogStruct.SetLogEnable(Level, Enable) ; end procedure SetLogEnable ; ------------------------------------------------------------ procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is ------------------------------------------------------------ begin AlertLogStruct.SetLogEnable(AlertLogID, Level, Enable, DescendHierarchy) ; end procedure SetLogEnable ; ------------------------------------------------------------ impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetLogEnable(AlertLogID, Level) ; end function GetLogEnable ; ------------------------------------------------------------ impure function GetLogEnable(Level : LogType) return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetLogEnable(LOG_DEFAULT_ID, Level) ; end function GetLogEnable ; ------------------------------------------------------------ procedure ReportLogEnables is ------------------------------------------------------------ begin AlertLogStruct.ReportLogEnables ; end ReportLogEnables ; ------------------------------------------------------------ procedure SetAlertLogOptions ( ------------------------------------------------------------ FailOnWarning : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; FailOnDisabledErrors : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; ReportHierarchy : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteAlertTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogLevel : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogName : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; WriteLogTime : AlertLogOptionsType := OPT_INIT_PARM_DETECT ; AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ; DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ; PassName : string := OSVVM_STRING_INIT_PARM_DETECT ; FailName : string := OSVVM_STRING_INIT_PARM_DETECT ) is begin AlertLogStruct.SetAlertLogOptions ( FailOnWarning => FailOnWarning , FailOnDisabledErrors => FailOnDisabledErrors, ReportHierarchy => ReportHierarchy , WriteAlertLevel => WriteAlertLevel , WriteAlertName => WriteAlertName , WriteAlertTime => WriteAlertTime , WriteLogLevel => WriteLogLevel , WriteLogName => WriteLogName , WriteLogTime => WriteLogTime , AlertPrefix => AlertPrefix , LogPrefix => LogPrefix , ReportPrefix => ReportPrefix , DoneName => DoneName , PassName => PassName , FailName => FailName ); end procedure SetAlertLogOptions ; ------------------------------------------------------------ procedure ReportAlertLogOptions is ------------------------------------------------------------ begin AlertLogStruct.ReportAlertLogOptions ; end procedure ReportAlertLogOptions ; ------------------------------------------------------------ impure function GetAlertLogFailOnWarning return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogFailOnWarning ; end function GetAlertLogFailOnWarning ; ------------------------------------------------------------ impure function GetAlertLogFailOnDisabledErrors return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogFailOnDisabledErrors ; end function GetAlertLogFailOnDisabledErrors ; ------------------------------------------------------------ impure function GetAlertLogReportHierarchy return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogReportHierarchy ; end function GetAlertLogReportHierarchy ; ------------------------------------------------------------ impure function GetAlertLogFoundReportHier return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogFoundReportHier ; end function GetAlertLogFoundReportHier ; ------------------------------------------------------------ impure function GetAlertLogFoundAlertHier return boolean is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogFoundAlertHier ; end function GetAlertLogFoundAlertHier ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertLevel return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteAlertLevel ; end function GetAlertLogWriteAlertLevel ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertName return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteAlertName ; end function GetAlertLogWriteAlertName ; ------------------------------------------------------------ impure function GetAlertLogWriteAlertTime return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteAlertTime ; end function GetAlertLogWriteAlertTime ; ------------------------------------------------------------ impure function GetAlertLogWriteLogLevel return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteLogLevel ; end function GetAlertLogWriteLogLevel ; ------------------------------------------------------------ impure function GetAlertLogWriteLogName return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteLogName ; end function GetAlertLogWriteLogName ; ------------------------------------------------------------ impure function GetAlertLogWriteLogTime return AlertLogOptionsType is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogWriteLogTime ; end function GetAlertLogWriteLogTime ; ------------------------------------------------------------ impure function GetAlertLogAlertPrefix return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogAlertPrefix ; end function GetAlertLogAlertPrefix ; ------------------------------------------------------------ impure function GetAlertLogLogPrefix return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogLogPrefix ; end function GetAlertLogLogPrefix ; ------------------------------------------------------------ impure function GetAlertLogReportPrefix return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogReportPrefix ; end function GetAlertLogReportPrefix ; ------------------------------------------------------------ impure function GetAlertLogDoneName return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogDoneName ; end function GetAlertLogDoneName ; ------------------------------------------------------------ impure function GetAlertLogPassName return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogPassName ; end function GetAlertLogPassName ; ------------------------------------------------------------ impure function GetAlertLogFailName return string is ------------------------------------------------------------ begin return AlertLogStruct.GetAlertLogFailName ; end function GetAlertLogFailName ; ------------------------------------------------------------ function IsLogEnableType (Name : String) return boolean is ------------------------------------------------------------ -- type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER begin if Name = "PASSED" then return TRUE ; elsif Name = "DEBUG" then return TRUE ; elsif Name = "FINAL" then return TRUE ; elsif Name = "INFO" then return TRUE ; end if ; return FALSE ; end function IsLogEnableType ; ------------------------------------------------------------ procedure ReadLogEnables (file AlertLogInitFile : text) is -- Preferred Read format -- Line 1: instance1_name log_enable log_enable log_enable -- Line 2: instance2_name log_enable log_enable log_enable -- when reading multiple log_enables on a line, they must be separated by a space -- --- Also supports alternate format from Lyle/.... -- Line 1: instance1_name -- Line 2: log enable -- Line 3: instance2_name -- Line 4: log enable -- ------------------------------------------------------------ type ReadStateType is (GET_ID, GET_ENABLE) ; variable ReadState : ReadStateType := GET_ID ; variable buf : line ; variable Empty : boolean ; variable MultiLineComment : boolean := FALSE ; variable Name : string(1 to 80) ; variable NameLen : integer ; variable AlertLogID : AlertLogIDType ; variable ReadAnEnable : boolean ; variable LogLevel : LogType ; begin ReadState := GET_ID ; ReadLineLoop : while not EndFile(AlertLogInitFile) loop ReadLine(AlertLogInitFile, buf) ; if ReadAnEnable then -- Read one or more enable values, next line read AlertLog name -- Note that any newline with ReadAnEnable TRUE will result in -- searching for another AlertLogID name - this includes multi-line comments. ReadState := GET_ID ; end if ; ReadNameLoop : loop EmptyOrCommentLine(buf, Empty, MultiLineComment) ; next ReadLineLoop when Empty ; case ReadState is when GET_ID => sread(buf, Name, NameLen) ; exit ReadNameLoop when NameLen = 0 ; AlertLogID := GetAlertLogID(Name(1 to NameLen), ALERTLOG_ID_NOT_ASSIGNED) ; ReadState := GET_ENABLE ; ReadAnEnable := FALSE ; when GET_ENABLE => sread(buf, Name, NameLen) ; exit ReadNameLoop when NameLen = 0 ; ReadAnEnable := TRUE ; if not IsLogEnableType(Name(1 to NameLen)) then Alert(OSVVM_ALERTLOG_ID, "AlertLogPkg.ReadLogEnables: Found Invalid LogEnable: " & Name(1 to NameLen)) ; exit ReadNameLoop ; end if ; LogLevel := LogType'value(Name(1 to NameLen)) ; SetLogEnable(AlertLogID, LogLevel, TRUE) ; end case ; end loop ReadNameLoop ; end loop ReadLineLoop ; end procedure ReadLogEnables ; ------------------------------------------------------------ procedure ReadLogEnables (FileName : string) is ------------------------------------------------------------ file AlertLogInitFile : text open READ_MODE is FileName ; begin ReadLogEnables(AlertLogInitFile) ; end procedure ReadLogEnables ; ------------------------------------------------------------ function PathTail (A : string) return string is ------------------------------------------------------------ alias aA : string(1 to A'length) is A ; variable LenA : integer := A'length ; begin if aA(LenA) = ':' then LenA := LenA - 1 ; end if ; for i in LenA downto 1 loop if aA(i) = ':' then return aA(i+1 to LenA) ; end if ; end loop ; return aA(1 to LenA) ; end function PathTail ; -- ------------------------------------------------------------ -- Deprecated -- ------------------------------------------------------------ -- deprecated procedure AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is begin AlertIf( AlertLogID, condition, Message, Level) ; end procedure AlertIf ; ------------------------------------------------------------ -- deprecated impure function AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean is begin return AlertIf( AlertLogID, condition, Message, Level) ; end function AlertIf ; ------------------------------------------------------------ -- deprecated procedure AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is begin AlertIfNot( AlertLogID, condition, Message, Level) ; end procedure AlertIfNot ; ------------------------------------------------------------ -- deprecated impure function AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean is begin return AlertIfNot( AlertLogID, condition, Message, Level) ; end function AlertIfNot ; ------------------------------------------------------------ -- deprecated procedure AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; LogLevel : LogType ; -- := PASSED AlertLevel : AlertType := ERROR ) is begin AlertLogStruct.IncAffirmCount ; -- increment check count if condition then -- passed AlertLogStruct.Log(AlertLogID, Message, LogLevel) ; -- call log else AlertLogStruct.Alert(AlertLogID, Message, AlertLevel) ; -- signal failure end if ; end procedure AffirmIf ; ------------------------------------------------------------ -- deprecated procedure AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; AlertLevel : AlertType ) is begin AffirmIf(AlertLogID, condition, Message, PASSED, AlertLevel) ; end procedure AffirmIf ; ------------------------------------------------------------ -- deprecated procedure AffirmIf(condition : boolean ; Message : string ; LogLevel : LogType ; AlertLevel : AlertType := ERROR) is begin AffirmIf(ALERT_DEFAULT_ID, condition, Message, LogLevel, AlertLevel) ; end procedure AffirmIf; ------------------------------------------------------------ -- deprecated procedure AffirmIf(condition : boolean ; Message : string ; AlertLevel : AlertType ) is begin AffirmIf(ALERT_DEFAULT_ID, condition, Message, PASSED, AlertLevel) ; end procedure AffirmIf; end package body AlertLogPkg ; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \ddspipe_add__parameterized0\ is port ( temp : out STD_LOGIC_VECTOR ( 16 downto 0 ); L : in STD_LOGIC_VECTOR ( 15 downto 0 ); reg_s_phase_fifo_din : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axis_phase_tvalid : in STD_LOGIC; s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \ddspipe_add__parameterized0\ : entity is "pipe_add"; end \ddspipe_add__parameterized0\; architecture STRUCTURE of \ddspipe_add__parameterized0\ is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[11]_i_2\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[11]_i_3\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[11]_i_4\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[11]_i_5\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[15]_i_2\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[15]_i_3\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[15]_i_4\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[15]_i_5\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[3]_i_2\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[3]_i_3\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[3]_i_4\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[3]_i_5\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[7]_i_2\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[7]_i_3\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[7]_i_4\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[7]_i_5\ : STD_LOGIC; signal _0_opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC; signal _0_opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC; signal _0_opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC; signal _0_opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC; signal _1_opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC; signal _1_opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC; signal _1_opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC; signal _1_opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC; signal _2_opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC; signal _2_opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC; signal _2_opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC; signal _2_opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC; signal _3_opt_has_pipe.first_q_reg[11]_i_1\ : STD_LOGIC; signal _3_opt_has_pipe.first_q_reg[15]_i_1\ : STD_LOGIC; signal _3_opt_has_pipe.first_q_reg[3]_i_1\ : STD_LOGIC; signal _3_opt_has_pipe.first_q_reg[7]_i_1\ : STD_LOGIC; signal \NLW_opt_has_pipe.first_q_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_opt_has_pipe.first_q_reg[16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \opt_has_pipe.first_q[11]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"56A6" ) port map ( I0 => L(11), I1 => reg_s_phase_fifo_din(11), I2 => s_axis_phase_tvalid, I3 => s_axis_phase_tdata(11), O => _0_opt_has_pipe.first_q[11]_i_2\ ); \opt_has_pipe.first_q[11]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"56A6" ) port map ( I0 => L(10), I1 => reg_s_phase_fifo_din(10), I2 => s_axis_phase_tvalid, I3 => s_axis_phase_tdata(10), O => _0_opt_has_pipe.first_q[11]_i_3\ ); \opt_has_pipe.first_q[11]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"56A6" ) port map ( I0 => L(9), I1 => reg_s_phase_fifo_din(9), I2 => s_axis_phase_tvalid, I3 => s_axis_phase_tdata(9), O => _0_opt_has_pipe.first_q[11]_i_4\ ); \opt_has_pipe.first_q[11]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"56A6" ) port map ( I0 => L(8), I1 => reg_s_phase_fifo_din(8), I2 => s_axis_phase_tvalid, I3 => s_axis_phase_tdata(8), O => _0_opt_has_pipe.first_q[11]_i_5\ ); \opt_has_pipe.first_q[15]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"56A6" ) port map ( I0 => L(15), I1 => reg_s_phase_fifo_din(15), I2 => s_axis_phase_tvalid, I3 => s_axis_phase_tdata(15), O => _0_opt_has_pipe.first_q[15]_i_2\ ); \opt_has_pipe.first_q[15]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"56A6" ) port map ( I0 => L(14), I1 => reg_s_phase_fifo_din(14), I2 => s_axis_phase_tvalid, I3 => s_axis_phase_tdata(14), O => _0_opt_has_pipe.first_q[15]_i_3\ ); \opt_has_pipe.first_q[15]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"56A6" ) port map ( I0 => L(13), I1 => reg_s_phase_fifo_din(13), I2 => s_axis_phase_tvalid, I3 => s_axis_phase_tdata(13), O => _0_opt_has_pipe.first_q[15]_i_4\ ); \opt_has_pipe.first_q[15]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"56A6" ) port map ( I0 => L(12), I1 => reg_s_phase_fifo_din(12), I2 => s_axis_phase_tvalid, I3 => s_axis_phase_tdata(12), O => _0_opt_has_pipe.first_q[15]_i_5\ ); \opt_has_pipe.first_q[3]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"56A6" ) port map ( I0 => L(3), I1 => reg_s_phase_fifo_din(3), I2 => s_axis_phase_tvalid, I3 => s_axis_phase_tdata(3), O => _0_opt_has_pipe.first_q[3]_i_2\ ); \opt_has_pipe.first_q[3]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"56A6" ) port map ( I0 => L(2), I1 => reg_s_phase_fifo_din(2), I2 => s_axis_phase_tvalid, I3 => s_axis_phase_tdata(2), O => _0_opt_has_pipe.first_q[3]_i_3\ ); \opt_has_pipe.first_q[3]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"56A6" ) port map ( I0 => L(1), I1 => reg_s_phase_fifo_din(1), I2 => s_axis_phase_tvalid, I3 => s_axis_phase_tdata(1), O => _0_opt_has_pipe.first_q[3]_i_4\ ); \opt_has_pipe.first_q[3]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"56A6" ) port map ( I0 => L(0), I1 => reg_s_phase_fifo_din(0), I2 => s_axis_phase_tvalid, I3 => s_axis_phase_tdata(0), O => _0_opt_has_pipe.first_q[3]_i_5\ ); \opt_has_pipe.first_q[7]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"56A6" ) port map ( I0 => L(7), I1 => reg_s_phase_fifo_din(7), I2 => s_axis_phase_tvalid, I3 => s_axis_phase_tdata(7), O => _0_opt_has_pipe.first_q[7]_i_2\ ); \opt_has_pipe.first_q[7]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"56A6" ) port map ( I0 => L(6), I1 => reg_s_phase_fifo_din(6), I2 => s_axis_phase_tvalid, I3 => s_axis_phase_tdata(6), O => _0_opt_has_pipe.first_q[7]_i_3\ ); \opt_has_pipe.first_q[7]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"56A6" ) port map ( I0 => L(5), I1 => reg_s_phase_fifo_din(5), I2 => s_axis_phase_tvalid, I3 => s_axis_phase_tdata(5), O => _0_opt_has_pipe.first_q[7]_i_4\ ); \opt_has_pipe.first_q[7]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"56A6" ) port map ( I0 => L(4), I1 => reg_s_phase_fifo_din(4), I2 => s_axis_phase_tvalid, I3 => s_axis_phase_tdata(4), O => _0_opt_has_pipe.first_q[7]_i_5\ ); \opt_has_pipe.first_q_reg[11]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => _0_opt_has_pipe.first_q_reg[7]_i_1\, CO(3) => _0_opt_has_pipe.first_q_reg[11]_i_1\, CO(2) => _1_opt_has_pipe.first_q_reg[11]_i_1\, CO(1) => _2_opt_has_pipe.first_q_reg[11]_i_1\, CO(0) => _3_opt_has_pipe.first_q_reg[11]_i_1\, CYINIT => \<const0>\, DI(3 downto 0) => L(11 downto 8), O(3 downto 0) => temp(11 downto 8), S(3) => _0_opt_has_pipe.first_q[11]_i_2\, S(2) => _0_opt_has_pipe.first_q[11]_i_3\, S(1) => _0_opt_has_pipe.first_q[11]_i_4\, S(0) => _0_opt_has_pipe.first_q[11]_i_5\ ); \opt_has_pipe.first_q_reg[15]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => _0_opt_has_pipe.first_q_reg[11]_i_1\, CO(3) => _0_opt_has_pipe.first_q_reg[15]_i_1\, CO(2) => _1_opt_has_pipe.first_q_reg[15]_i_1\, CO(1) => _2_opt_has_pipe.first_q_reg[15]_i_1\, CO(0) => _3_opt_has_pipe.first_q_reg[15]_i_1\, CYINIT => \<const0>\, DI(3 downto 0) => L(15 downto 12), O(3 downto 0) => temp(15 downto 12), S(3) => _0_opt_has_pipe.first_q[15]_i_2\, S(2) => _0_opt_has_pipe.first_q[15]_i_3\, S(1) => _0_opt_has_pipe.first_q[15]_i_4\, S(0) => _0_opt_has_pipe.first_q[15]_i_5\ ); \opt_has_pipe.first_q_reg[16]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => _0_opt_has_pipe.first_q_reg[15]_i_1\, CO(3 downto 1) => \NLW_opt_has_pipe.first_q_reg[16]_i_1_CO_UNCONNECTED\(3 downto 1), CO(0) => temp(16), CYINIT => \<const0>\, DI(3) => \<const0>\, DI(2) => \<const0>\, DI(1) => \<const0>\, DI(0) => \<const0>\, O(3 downto 0) => \NLW_opt_has_pipe.first_q_reg[16]_i_1_O_UNCONNECTED\(3 downto 0), S(3) => \<const0>\, S(2) => \<const0>\, S(1) => \<const0>\, S(0) => \<const1>\ ); \opt_has_pipe.first_q_reg[3]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \<const0>\, CO(3) => _0_opt_has_pipe.first_q_reg[3]_i_1\, CO(2) => _1_opt_has_pipe.first_q_reg[3]_i_1\, CO(1) => _2_opt_has_pipe.first_q_reg[3]_i_1\, CO(0) => _3_opt_has_pipe.first_q_reg[3]_i_1\, CYINIT => \<const0>\, DI(3 downto 0) => L(3 downto 0), O(3 downto 0) => temp(3 downto 0), S(3) => _0_opt_has_pipe.first_q[3]_i_2\, S(2) => _0_opt_has_pipe.first_q[3]_i_3\, S(1) => _0_opt_has_pipe.first_q[3]_i_4\, S(0) => _0_opt_has_pipe.first_q[3]_i_5\ ); \opt_has_pipe.first_q_reg[7]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => _0_opt_has_pipe.first_q_reg[3]_i_1\, CO(3) => _0_opt_has_pipe.first_q_reg[7]_i_1\, CO(2) => _1_opt_has_pipe.first_q_reg[7]_i_1\, CO(1) => _2_opt_has_pipe.first_q_reg[7]_i_1\, CO(0) => _3_opt_has_pipe.first_q_reg[7]_i_1\, CYINIT => \<const0>\, DI(3 downto 0) => L(7 downto 4), O(3 downto 0) => temp(7 downto 4), S(3) => _0_opt_has_pipe.first_q[7]_i_2\, S(2) => _0_opt_has_pipe.first_q[7]_i_3\, S(1) => _0_opt_has_pipe.first_q[7]_i_4\, S(0) => _0_opt_has_pipe.first_q[7]_i_5\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ddsxbip_pipe_v3_0_viv is port ( m_axis_data_tvalid : out STD_LOGIC; aclk : in STD_LOGIC; s_axis_phase_tvalid : in STD_LOGIC ); end ddsxbip_pipe_v3_0_viv; architecture STRUCTURE of ddsxbip_pipe_v3_0_viv is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal first_q : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of first_q : signal is "true"; signal _0_opt_has_pipe.first_q[0]_i_1__0\ : STD_LOGIC; signal _0_opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\ : STD_LOGIC; signal rdy_stream_i : STD_LOGIC; attribute keep : string; attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes"; attribute srl_bus_name : string; attribute srl_bus_name of \opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\ : label is "\U0/i_synth /\i_has_nd_rdy_pipe.valid_phase_read_del/opt_has_pipe.i_pipe[6].pipe_reg[6] "; attribute srl_name : string; attribute srl_name of \opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\ : label is "\U0/i_synth /\i_has_nd_rdy_pipe.valid_phase_read_del/opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5 "; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); m_axis_data_tvalid_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => s_axis_phase_tvalid, I1 => rdy_stream_i, O => m_axis_data_tvalid ); \opt_has_pipe.first_q[0]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => s_axis_phase_tvalid, I1 => first_q, O => _0_opt_has_pipe.first_q[0]_i_1__0\ ); \opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \<const1>\, D => _0_opt_has_pipe.first_q[0]_i_1__0\, Q => first_q, R => \<const0>\ ); \opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \<const0>\, A1 => \<const0>\, A2 => \<const1>\, A3 => \<const0>\, CE => s_axis_phase_tvalid, CLK => aclk, D => first_q, Q => _0_opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\ ); \opt_has_pipe.i_pipe[7].pipe_reg[7][0]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => _0_opt_has_pipe.i_pipe[6].pipe_reg[6][0]_srl5\, Q => rdy_stream_i, R => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ddsxbip_pipe_v3_0_viv_0 is port ( s_axis_phase_tvalid : in STD_LOGIC; aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of ddsxbip_pipe_v3_0_viv_0 : entity is "xbip_pipe_v3_0_viv"; end ddsxbip_pipe_v3_0_viv_0; architecture STRUCTURE of ddsxbip_pipe_v3_0_viv_0 is signal \<const0>\ : STD_LOGIC; signal first_q : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of first_q : signal is "true"; attribute keep : string; attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes"; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \<const0>\, Q => first_q, R => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \ddsxbip_pipe_v3_0_viv__parameterized0\ is port ( aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized0\ : entity is "xbip_pipe_v3_0_viv"; end \ddsxbip_pipe_v3_0_viv__parameterized0\; architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized0\ is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal first_q : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of first_q : signal is "true"; attribute keep : string; attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes"; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \<const1>\, D => \<const1>\, Q => first_q, R => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \ddsxbip_pipe_v3_0_viv__parameterized12\ is port ( invert_sin : out STD_LOGIC; O1 : out STD_LOGIC; O2 : out STD_LOGIC; O3 : out STD_LOGIC; O4 : out STD_LOGIC; O5 : out STD_LOGIC; O6 : out STD_LOGIC; O7 : out STD_LOGIC; O8 : out STD_LOGIC; O9 : out STD_LOGIC; O10 : out STD_LOGIC; O11 : out STD_LOGIC; O12 : out STD_LOGIC; O13 : out STD_LOGIC; O14 : out STD_LOGIC; O15 : out STD_LOGIC; O16 : out STD_LOGIC; O17 : out STD_LOGIC; O18 : out STD_LOGIC; O19 : out STD_LOGIC; O20 : out STD_LOGIC; O21 : out STD_LOGIC; O22 : out STD_LOGIC; O23 : out STD_LOGIC; O24 : out STD_LOGIC; O25 : out STD_LOGIC; O26 : out STD_LOGIC; O27 : out STD_LOGIC; O28 : out STD_LOGIC; O29 : out STD_LOGIC; O30 : out STD_LOGIC; O31 : out STD_LOGIC; s_axis_phase_tvalid : in STD_LOGIC; aclk : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 14 downto 0 ); \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\ : in STD_LOGIC_VECTOR ( 14 downto 0 ); L : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized12\ : entity is "xbip_pipe_v3_0_viv"; end \ddsxbip_pipe_v3_0_viv__parameterized12\; architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized12\ is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal \^o18\ : STD_LOGIC; signal first_q : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^invert_sin\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[8]_i_2\ : STD_LOGIC; signal _0_opt_has_pipe.first_q[8]_i_2__0\ : STD_LOGIC; signal _0_opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\ : STD_LOGIC; signal _0_opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\ : STD_LOGIC; signal _0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[0]_i_1__1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[0]_i_1__2\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[1]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[1]_i_1__0\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[1]_i_1__1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[1]_i_1__2\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[2]_i_1__0\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[2]_i_1__1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[2]_i_1__2\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[3]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[3]_i_1__1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[3]_i_1__4\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[4]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[4]_i_1__2\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[5]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[5]_i_1__0\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[5]_i_1__1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[5]_i_1__2\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[6]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[6]_i_1__0\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[6]_i_1__2\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[7]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[7]_i_1__1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \opt_has_pipe.first_q[8]_i_1\ : label is "soft_lutpair0"; attribute keep : string; attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes"; attribute srl_bus_name : string; attribute srl_bus_name of \opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\ : label is "\U0/i_synth /\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3] "; attribute srl_name : string; attribute srl_name of \opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\ : label is "\U0/i_synth /\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2 "; attribute srl_bus_name of \opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\ : label is "\U0/i_synth /\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3] "; attribute srl_name of \opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\ : label is "\U0/i_synth /\i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2 "; begin O18 <= \^o18\; invert_sin <= \^invert_sin\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \opt_has_pipe.first_q[0]_i_1__1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^invert_sin\, I1 => \out\(8), O => O7 ); \opt_has_pipe.first_q[0]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(8), I1 => _0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\, I2 => \^invert_sin\, O => O24 ); \opt_has_pipe.first_q[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^invert_sin\, I1 => \out\(9), O => O6 ); \opt_has_pipe.first_q[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \out\(1), I1 => \out\(0), I2 => \^invert_sin\, O => O14 ); \opt_has_pipe.first_q[1]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"D728" ) port map ( I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0), I1 => \^invert_sin\, I2 => _0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\, I3 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1), O => O23 ); \opt_has_pipe.first_q[1]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(9), I1 => _0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\, I2 => \^invert_sin\, O => O25 ); \opt_has_pipe.first_q[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^invert_sin\, I1 => \out\(10), O => O5 ); \opt_has_pipe.first_q[2]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"1EF0" ) port map ( I0 => \out\(0), I1 => \out\(1), I2 => \out\(2), I3 => \^invert_sin\, O => O12 ); \opt_has_pipe.first_q[2]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"F11F0EE0" ) port map ( I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1), I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0), I2 => \^invert_sin\, I3 => _0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\, I4 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(2), O => O15 ); \opt_has_pipe.first_q[2]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(10), I1 => _0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\, I2 => \^invert_sin\, O => O26 ); \opt_has_pipe.first_q[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^invert_sin\, I1 => \out\(11), O => O4 ); \opt_has_pipe.first_q[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0101FF00FEFE00" ) port map ( I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0), I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1), I2 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(2), I3 => \^invert_sin\, I4 => _0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\, I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(3), O => O16 ); \opt_has_pipe.first_q[3]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(11), I1 => _0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\, I2 => \^invert_sin\, O => O27 ); \opt_has_pipe.first_q[3]_i_1__4\: unisim.vcomponents.LUT5 generic map( INIT => X"01FEFF00" ) port map ( I0 => \out\(1), I1 => \out\(0), I2 => \out\(2), I3 => \out\(3), I4 => \^invert_sin\, O => O31 ); \opt_has_pipe.first_q[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^invert_sin\, I1 => \out\(12), O => O3 ); \opt_has_pipe.first_q[4]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0001FFFFFFFE0000" ) port map ( I0 => \out\(1), I1 => \out\(0), I2 => \out\(2), I3 => \out\(3), I4 => \^invert_sin\, I5 => \out\(4), O => O13 ); \opt_has_pipe.first_q[4]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"0001FFFFFFFE0000" ) port map ( I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(3), I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(2), I2 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1), I3 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0), I4 => \^o18\, I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4), O => O17 ); \opt_has_pipe.first_q[4]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(12), I1 => _0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\, I2 => \^invert_sin\, O => O28 ); \opt_has_pipe.first_q[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^invert_sin\, I1 => \out\(13), O => O2 ); \opt_has_pipe.first_q[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => _0_opt_has_pipe.first_q[8]_i_2\, I1 => \out\(5), I2 => \^invert_sin\, O => O11 ); \opt_has_pipe.first_q[5]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"D11D2EE2" ) port map ( I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4), I1 => _0_opt_has_pipe.first_q[8]_i_2__0\, I2 => \^invert_sin\, I3 => _0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\, I4 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5), O => O19 ); \opt_has_pipe.first_q[5]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(13), I1 => _0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\, I2 => \^invert_sin\, O => O29 ); \opt_has_pipe.first_q[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^invert_sin\, I1 => \out\(14), O => O1 ); \opt_has_pipe.first_q[6]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"4B78" ) port map ( I0 => \out\(5), I1 => _0_opt_has_pipe.first_q[8]_i_2\, I2 => \out\(6), I3 => \^invert_sin\, O => O10 ); \opt_has_pipe.first_q[6]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"DF0101DF20FEFE20" ) port map ( I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5), I1 => _0_opt_has_pipe.first_q[8]_i_2__0\, I2 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4), I3 => \^invert_sin\, I4 => _0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\, I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(6), O => O20 ); \opt_has_pipe.first_q[6]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(14), I1 => _0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\, I2 => \^invert_sin\, O => O30 ); \opt_has_pipe.first_q[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"04FB7F80" ) port map ( I0 => \out\(6), I1 => _0_opt_has_pipe.first_q[8]_i_2\, I2 => \out\(5), I3 => \out\(7), I4 => \^invert_sin\, O => O8 ); \opt_has_pipe.first_q[7]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0001F7FFFFFE0800" ) port map ( I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(6), I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4), I2 => _0_opt_has_pipe.first_q[8]_i_2__0\, I3 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5), I4 => \^o18\, I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(7), O => O21 ); \opt_has_pipe.first_q[7]_i_1__1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^invert_sin\, I1 => _0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\, O => \^o18\ ); \opt_has_pipe.first_q[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00048000" ) port map ( I0 => \out\(6), I1 => _0_opt_has_pipe.first_q[8]_i_2\, I2 => \out\(5), I3 => \out\(7), I4 => \^invert_sin\, O => O9 ); \opt_has_pipe.first_q[8]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000080000010000" ) port map ( I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(6), I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(4), I2 => _0_opt_has_pipe.first_q[8]_i_2__0\, I3 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5), I4 => \^o18\, I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(7), O => O22 ); \opt_has_pipe.first_q[8]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000100000000" ) port map ( I0 => \out\(3), I1 => \out\(2), I2 => \out\(0), I3 => \out\(1), I4 => \out\(4), I5 => \^invert_sin\, O => _0_opt_has_pipe.first_q[8]_i_2\ ); \opt_has_pipe.first_q[8]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFEFEFF" ) port map ( I0 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0), I1 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1), I2 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(2), I3 => \^invert_sin\, I4 => _0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\, I5 => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(3), O => _0_opt_has_pipe.first_q[8]_i_2__0\ ); \opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => L(0), Q => first_q(0), R => \<const0>\ ); \opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => L(1), Q => first_q(1), R => \<const0>\ ); \opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \<const1>\, A1 => \<const0>\, A2 => \<const0>\, A3 => \<const0>\, CE => s_axis_phase_tvalid, CLK => aclk, D => first_q(0), Q => _0_opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\ ); \opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \<const1>\, A1 => \<const0>\, A2 => \<const0>\, A3 => \<const0>\, CE => s_axis_phase_tvalid, CLK => aclk, D => first_q(1), Q => _0_opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\ ); \opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => _0_opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2\, Q => _0_opt_has_pipe.i_pipe[4].pipe_reg[4][0]__0\, R => \<const0>\ ); \opt_has_pipe.i_pipe[4].pipe_reg[4][1]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => _0_opt_has_pipe.i_pipe[3].pipe_reg[3][1]_srl2\, Q => \^invert_sin\, R => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \ddsxbip_pipe_v3_0_viv__parameterized14\ is port ( m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); s_axis_phase_tvalid : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14\ : entity is "xbip_pipe_v3_0_viv"; end \ddsxbip_pipe_v3_0_viv__parameterized14\; architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14\ is signal \<const0>\ : STD_LOGIC; signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute keep : string; attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes"; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(7), O => m_axis_data_tdata(7) ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(6), O => m_axis_data_tdata(6) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(5), O => m_axis_data_tdata(5) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(4), O => m_axis_data_tdata(4) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(3), O => m_axis_data_tdata(3) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(2), O => m_axis_data_tdata(2) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(1), O => m_axis_data_tdata(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(0), O => m_axis_data_tdata(0) ); \opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \out\(0), Q => first_q(0), R => \<const0>\ ); \opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \out\(1), Q => first_q(1), R => \<const0>\ ); \opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \out\(2), Q => first_q(2), R => \<const0>\ ); \opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \out\(3), Q => first_q(3), R => \<const0>\ ); \opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \out\(4), Q => first_q(4), R => \<const0>\ ); \opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \out\(5), Q => first_q(5), R => \<const0>\ ); \opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \out\(6), Q => first_q(6), R => \<const0>\ ); \opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \out\(7), Q => first_q(7), R => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \ddsxbip_pipe_v3_0_viv__parameterized14_1\ is port ( O1 : out STD_LOGIC; O2 : out STD_LOGIC; O3 : out STD_LOGIC; O4 : out STD_LOGIC; O5 : out STD_LOGIC; O6 : out STD_LOGIC; O7 : out STD_LOGIC; O8 : out STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_phase_tvalid : in STD_LOGIC; I1 : in STD_LOGIC; aclk : in STD_LOGIC; I2 : in STD_LOGIC; I3 : in STD_LOGIC; I4 : in STD_LOGIC; I5 : in STD_LOGIC; I6 : in STD_LOGIC; I7 : in STD_LOGIC; I8 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_1\ : entity is "xbip_pipe_v3_0_viv"; end \ddsxbip_pipe_v3_0_viv__parameterized14_1\; architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_1\ is signal \<const0>\ : STD_LOGIC; signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 ); signal _0_opt_has_pipe.first_q[7]_i_2__0\ : STD_LOGIC; attribute keep : string; attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes"; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \opt_has_pipe.first_q[0]_i_1__4\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => first_q(0), I1 => \out\(0), O => O8 ); \opt_has_pipe.first_q[1]_i_1__4\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => first_q(1), I1 => first_q(0), I2 => \out\(0), O => O1 ); \opt_has_pipe.first_q[2]_i_1__4\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => first_q(2), I1 => \out\(0), I2 => first_q(0), I3 => first_q(1), O => O2 ); \opt_has_pipe.first_q[3]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => first_q(1), I1 => first_q(0), I2 => \out\(0), I3 => first_q(2), I4 => first_q(3), O => O3 ); \opt_has_pipe.first_q[4]_i_1__4\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAAAAAAAAAA" ) port map ( I0 => first_q(4), I1 => first_q(1), I2 => first_q(0), I3 => \out\(0), I4 => first_q(2), I5 => first_q(3), O => O4 ); \opt_has_pipe.first_q[5]_i_1__4\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => first_q(5), I1 => _0_opt_has_pipe.first_q[7]_i_2__0\, I2 => first_q(4), O => O5 ); \opt_has_pipe.first_q[6]_i_1__4\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => first_q(6), I1 => first_q(4), I2 => _0_opt_has_pipe.first_q[7]_i_2__0\, I3 => first_q(5), O => O6 ); \opt_has_pipe.first_q[7]_i_1__3\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => first_q(7), I1 => first_q(5), I2 => _0_opt_has_pipe.first_q[7]_i_2__0\, I3 => first_q(4), I4 => first_q(6), O => O7 ); \opt_has_pipe.first_q[7]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"80000000" ) port map ( I0 => first_q(3), I1 => first_q(2), I2 => \out\(0), I3 => first_q(0), I4 => first_q(1), O => _0_opt_has_pipe.first_q[7]_i_2__0\ ); \opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I8, Q => first_q(0), R => \<const0>\ ); \opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I7, Q => first_q(1), R => \<const0>\ ); \opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I6, Q => first_q(2), R => \<const0>\ ); \opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I5, Q => first_q(3), R => \<const0>\ ); \opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I4, Q => first_q(4), R => \<const0>\ ); \opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I3, Q => first_q(5), R => \<const0>\ ); \opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I2, Q => first_q(6), R => \<const0>\ ); \opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1, Q => first_q(7), R => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \ddsxbip_pipe_v3_0_viv__parameterized14_2\ is port ( m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); s_axis_phase_tvalid : in STD_LOGIC; I1 : in STD_LOGIC; aclk : in STD_LOGIC; I2 : in STD_LOGIC; I3 : in STD_LOGIC; I4 : in STD_LOGIC; I5 : in STD_LOGIC; I6 : in STD_LOGIC; I7 : in STD_LOGIC; I8 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_2\ : entity is "xbip_pipe_v3_0_viv"; end \ddsxbip_pipe_v3_0_viv__parameterized14_2\; architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_2\ is signal \<const0>\ : STD_LOGIC; signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute keep : string; attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes"; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(7), O => m_axis_data_tdata(7) ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(6), O => m_axis_data_tdata(6) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(5), O => m_axis_data_tdata(5) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(4), O => m_axis_data_tdata(4) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(3), O => m_axis_data_tdata(3) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(2), O => m_axis_data_tdata(2) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(1), O => m_axis_data_tdata(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(0), O => m_axis_data_tdata(0) ); \opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I8, Q => first_q(0), R => \<const0>\ ); \opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I7, Q => first_q(1), R => \<const0>\ ); \opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I6, Q => first_q(2), R => \<const0>\ ); \opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I5, Q => first_q(3), R => \<const0>\ ); \opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I4, Q => first_q(4), R => \<const0>\ ); \opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I3, Q => first_q(5), R => \<const0>\ ); \opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I2, Q => first_q(6), R => \<const0>\ ); \opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1, Q => first_q(7), R => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \ddsxbip_pipe_v3_0_viv__parameterized14_3\ is port ( m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); s_axis_phase_tvalid : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_3\ : entity is "xbip_pipe_v3_0_viv"; end \ddsxbip_pipe_v3_0_viv__parameterized14_3\; architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_3\ is signal \<const0>\ : STD_LOGIC; signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute keep : string; attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes"; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(7), O => m_axis_data_tdata(7) ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(6), O => m_axis_data_tdata(6) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(5), O => m_axis_data_tdata(5) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(4), O => m_axis_data_tdata(4) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(3), O => m_axis_data_tdata(3) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(2), O => m_axis_data_tdata(2) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(1), O => m_axis_data_tdata(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(0), O => m_axis_data_tdata(0) ); \opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \out\(0), Q => first_q(0), R => \<const0>\ ); \opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \out\(1), Q => first_q(1), R => \<const0>\ ); \opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \out\(2), Q => first_q(2), R => \<const0>\ ); \opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \out\(3), Q => first_q(3), R => \<const0>\ ); \opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \out\(4), Q => first_q(4), R => \<const0>\ ); \opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \out\(5), Q => first_q(5), R => \<const0>\ ); \opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \out\(6), Q => first_q(6), R => \<const0>\ ); \opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => \out\(7), Q => first_q(7), R => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \ddsxbip_pipe_v3_0_viv__parameterized14_4\ is port ( m_axis_data_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); s_axis_phase_tvalid : in STD_LOGIC; I1 : in STD_LOGIC; aclk : in STD_LOGIC; I2 : in STD_LOGIC; I3 : in STD_LOGIC; I4 : in STD_LOGIC; I5 : in STD_LOGIC; I6 : in STD_LOGIC; I7 : in STD_LOGIC; I8 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_4\ : entity is "xbip_pipe_v3_0_viv"; end \ddsxbip_pipe_v3_0_viv__parameterized14_4\; architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_4\ is signal \<const0>\ : STD_LOGIC; signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute keep : string; attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes"; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(7), O => m_axis_data_tdata(7) ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(6), O => m_axis_data_tdata(6) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(5), O => m_axis_data_tdata(5) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(4), O => m_axis_data_tdata(4) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(3), O => m_axis_data_tdata(3) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(2), O => m_axis_data_tdata(2) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(1), O => m_axis_data_tdata(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(0), O => m_axis_data_tdata(0) ); \opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I8, Q => first_q(0), R => \<const0>\ ); \opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I7, Q => first_q(1), R => \<const0>\ ); \opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I6, Q => first_q(2), R => \<const0>\ ); \opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I5, Q => first_q(3), R => \<const0>\ ); \opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I4, Q => first_q(4), R => \<const0>\ ); \opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I3, Q => first_q(5), R => \<const0>\ ); \opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I2, Q => first_q(6), R => \<const0>\ ); \opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1, Q => first_q(7), R => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \ddsxbip_pipe_v3_0_viv__parameterized14_6\ is port ( O1 : out STD_LOGIC; O2 : out STD_LOGIC; O3 : out STD_LOGIC; O4 : out STD_LOGIC; O5 : out STD_LOGIC; O6 : out STD_LOGIC; O7 : out STD_LOGIC; O8 : out STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_phase_tvalid : in STD_LOGIC; I1 : in STD_LOGIC; aclk : in STD_LOGIC; I2 : in STD_LOGIC; I3 : in STD_LOGIC; I4 : in STD_LOGIC; I5 : in STD_LOGIC; I6 : in STD_LOGIC; I7 : in STD_LOGIC; invert_sin : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized14_6\ : entity is "xbip_pipe_v3_0_viv"; end \ddsxbip_pipe_v3_0_viv__parameterized14_6\; architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized14_6\ is signal \<const0>\ : STD_LOGIC; signal first_q : STD_LOGIC_VECTOR ( 7 downto 0 ); signal _0_opt_has_pipe.first_q[7]_i_2\ : STD_LOGIC; attribute keep : string; attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes"; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \opt_has_pipe.first_q[0]_i_1__3\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => first_q(0), I1 => \out\(0), O => O8 ); \opt_has_pipe.first_q[1]_i_1__3\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => first_q(1), I1 => first_q(0), I2 => \out\(0), O => O1 ); \opt_has_pipe.first_q[2]_i_1__3\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => first_q(2), I1 => \out\(0), I2 => first_q(0), I3 => first_q(1), O => O2 ); \opt_has_pipe.first_q[3]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => first_q(1), I1 => first_q(0), I2 => \out\(0), I3 => first_q(2), I4 => first_q(3), O => O3 ); \opt_has_pipe.first_q[4]_i_1__3\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAAAAAAAAAA" ) port map ( I0 => first_q(4), I1 => first_q(1), I2 => first_q(0), I3 => \out\(0), I4 => first_q(2), I5 => first_q(3), O => O4 ); \opt_has_pipe.first_q[5]_i_1__3\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => first_q(5), I1 => _0_opt_has_pipe.first_q[7]_i_2\, I2 => first_q(4), O => O5 ); \opt_has_pipe.first_q[6]_i_1__3\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => first_q(6), I1 => first_q(4), I2 => _0_opt_has_pipe.first_q[7]_i_2\, I3 => first_q(5), O => O6 ); \opt_has_pipe.first_q[7]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => first_q(7), I1 => first_q(5), I2 => _0_opt_has_pipe.first_q[7]_i_2\, I3 => first_q(4), I4 => first_q(6), O => O7 ); \opt_has_pipe.first_q[7]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"80000000" ) port map ( I0 => first_q(3), I1 => first_q(2), I2 => \out\(0), I3 => first_q(0), I4 => first_q(1), O => _0_opt_has_pipe.first_q[7]_i_2\ ); \opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I7, Q => first_q(0), R => \<const0>\ ); \opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I6, Q => first_q(1), R => \<const0>\ ); \opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I5, Q => first_q(2), R => \<const0>\ ); \opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I4, Q => first_q(3), R => \<const0>\ ); \opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I3, Q => first_q(4), R => \<const0>\ ); \opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I2, Q => first_q(5), R => \<const0>\ ); \opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1, Q => first_q(6), R => \<const0>\ ); \opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => invert_sin, Q => first_q(7), R => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \ddsxbip_pipe_v3_0_viv__parameterized16\ is port ( \out\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); s_axis_phase_tvalid : in STD_LOGIC; I1 : in STD_LOGIC; aclk : in STD_LOGIC; I2 : in STD_LOGIC; I3 : in STD_LOGIC; I4 : in STD_LOGIC; I5 : in STD_LOGIC; I6 : in STD_LOGIC; I7 : in STD_LOGIC; I8 : in STD_LOGIC; DOBDO : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized16\ : entity is "xbip_pipe_v3_0_viv"; end \ddsxbip_pipe_v3_0_viv__parameterized16\; architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized16\ is signal \<const0>\ : STD_LOGIC; signal first_q : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute keep : string; attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[8]\ : label is "yes"; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(8), O => \out\(8) ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(7), O => \out\(7) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(6), O => \out\(6) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(5), O => \out\(5) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(4), O => \out\(4) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(3), O => \out\(3) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(2), O => \out\(2) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(1), O => \out\(1) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(0), O => \out\(0) ); \opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => DOBDO(0), Q => first_q(0), R => \<const0>\ ); \opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I8, Q => first_q(1), R => \<const0>\ ); \opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I7, Q => first_q(2), R => \<const0>\ ); \opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I6, Q => first_q(3), R => \<const0>\ ); \opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I5, Q => first_q(4), R => \<const0>\ ); \opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I4, Q => first_q(5), R => \<const0>\ ); \opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I3, Q => first_q(6), R => \<const0>\ ); \opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I2, Q => first_q(7), R => \<const0>\ ); \opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1, Q => first_q(8), R => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \ddsxbip_pipe_v3_0_viv__parameterized16_5\ is port ( \out\ : out STD_LOGIC_VECTOR ( 8 downto 0 ); s_axis_phase_tvalid : in STD_LOGIC; I1 : in STD_LOGIC; aclk : in STD_LOGIC; I2 : in STD_LOGIC; I3 : in STD_LOGIC; I4 : in STD_LOGIC; I5 : in STD_LOGIC; I6 : in STD_LOGIC; I7 : in STD_LOGIC; I8 : in STD_LOGIC; I9 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized16_5\ : entity is "xbip_pipe_v3_0_viv"; end \ddsxbip_pipe_v3_0_viv__parameterized16_5\; architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized16_5\ is signal \<const0>\ : STD_LOGIC; signal first_q : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute keep : string; attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[8]\ : label is "yes"; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(8), O => \out\(8) ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(7), O => \out\(7) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(6), O => \out\(6) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(5), O => \out\(5) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(4), O => \out\(4) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(3), O => \out\(3) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(2), O => \out\(2) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(1), O => \out\(1) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(0), O => \out\(0) ); \opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I9(0), Q => first_q(0), R => \<const0>\ ); \opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I8, Q => first_q(1), R => \<const0>\ ); \opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I7, Q => first_q(2), R => \<const0>\ ); \opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I6, Q => first_q(3), R => \<const0>\ ); \opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I5, Q => first_q(4), R => \<const0>\ ); \opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I4, Q => first_q(5), R => \<const0>\ ); \opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I3, Q => first_q(6), R => \<const0>\ ); \opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I2, Q => first_q(7), R => \<const0>\ ); \opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1, Q => first_q(8), R => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \ddsxbip_pipe_v3_0_viv__parameterized2\ is port ( s_axis_phase_tvalid : in STD_LOGIC; aclk : in STD_LOGIC; mutant_x_op : in STD_LOGIC_VECTOR ( 2 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized2\ : entity is "xbip_pipe_v3_0_viv"; end \ddsxbip_pipe_v3_0_viv__parameterized2\; architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized2\ is signal \<const0>\ : STD_LOGIC; signal first_q : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of first_q : signal is "true"; signal _0_opt_has_pipe.first_q[0]_i_1\ : STD_LOGIC; attribute keep : string; attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes"; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \opt_has_pipe.first_q[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"01" ) port map ( I0 => mutant_x_op(1), I1 => mutant_x_op(0), I2 => mutant_x_op(2), O => _0_opt_has_pipe.first_q[0]_i_1\ ); \opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => _0_opt_has_pipe.first_q[0]_i_1\, Q => first_q, R => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \ddsxbip_pipe_v3_0_viv__parameterized8\ is port ( \out\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); D : out STD_LOGIC_VECTOR ( 13 downto 0 ); I1 : out STD_LOGIC_VECTOR ( 13 downto 0 ); s_axis_phase_tvalid : in STD_LOGIC; temp : in STD_LOGIC_VECTOR ( 16 downto 0 ); aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \ddsxbip_pipe_v3_0_viv__parameterized8\ : entity is "xbip_pipe_v3_0_viv"; end \ddsxbip_pipe_v3_0_viv__parameterized8\; architecture STRUCTURE of \ddsxbip_pipe_v3_0_viv__parameterized8\ is signal \<const0>\ : STD_LOGIC; signal first_q : STD_LOGIC_VECTOR ( 16 downto 0 ); attribute keep : string; attribute keep of \opt_has_pipe.first_q_reg[0]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[10]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[11]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[12]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[13]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[14]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[15]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[16]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[1]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[2]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[3]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[4]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[5]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[6]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[7]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[8]\ : label is "yes"; attribute keep of \opt_has_pipe.first_q_reg[9]\ : label is "yes"; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(15), O => \out\(15) ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(14), O => \out\(14) ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(5), O => \out\(5) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(4), O => \out\(4) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(3), O => \out\(3) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(2), O => \out\(2) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(1), O => \out\(1) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(0), O => \out\(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(13), O => \out\(13) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(12), O => \out\(12) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(11), O => \out\(11) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(10), O => \out\(10) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(9), O => \out\(9) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(8), O => \out\(8) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(7), O => \out\(7) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => first_q(6), O => \out\(6) ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => first_q(14), I1 => first_q(0), O => I1(0) ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[10]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => first_q(14), I1 => first_q(10), O => I1(10) ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[11]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => first_q(14), I1 => first_q(11), O => I1(11) ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[12]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => first_q(14), I1 => first_q(12), O => I1(12) ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[13]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => first_q(14), I1 => first_q(13), O => I1(13) ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => first_q(14), I1 => first_q(1), O => I1(1) ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => first_q(14), I1 => first_q(2), O => I1(2) ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => first_q(14), I1 => first_q(3), O => I1(3) ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => first_q(14), I1 => first_q(4), O => I1(4) ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => first_q(14), I1 => first_q(5), O => I1(5) ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => first_q(14), I1 => first_q(6), O => I1(6) ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => first_q(14), I1 => first_q(7), O => I1(7) ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[8]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => first_q(14), I1 => first_q(8), O => I1(8) ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr[9]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => first_q(14), I1 => first_q(9), O => I1(9) ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => first_q(0), I1 => first_q(14), O => D(0) ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[10]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => first_q(10), I1 => first_q(14), O => D(10) ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[11]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => first_q(11), I1 => first_q(14), O => D(11) ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[12]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => first_q(12), I1 => first_q(14), O => D(12) ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[13]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => first_q(13), I1 => first_q(14), O => D(13) ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => first_q(1), I1 => first_q(14), O => D(1) ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => first_q(2), I1 => first_q(14), O => D(2) ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => first_q(3), I1 => first_q(14), O => D(3) ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => first_q(4), I1 => first_q(14), O => D(4) ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => first_q(5), I1 => first_q(14), O => D(5) ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => first_q(6), I1 => first_q(14), O => D(6) ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => first_q(7), I1 => first_q(14), O => D(7) ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[8]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => first_q(8), I1 => first_q(14), O => D(8) ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr[9]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => first_q(9), I1 => first_q(14), O => D(9) ); \opt_has_pipe.first_q_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(0), Q => first_q(0), R => \<const0>\ ); \opt_has_pipe.first_q_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(10), Q => first_q(10), R => \<const0>\ ); \opt_has_pipe.first_q_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(11), Q => first_q(11), R => \<const0>\ ); \opt_has_pipe.first_q_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(12), Q => first_q(12), R => \<const0>\ ); \opt_has_pipe.first_q_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(13), Q => first_q(13), R => \<const0>\ ); \opt_has_pipe.first_q_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(14), Q => first_q(14), R => \<const0>\ ); \opt_has_pipe.first_q_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(15), Q => first_q(15), R => \<const0>\ ); \opt_has_pipe.first_q_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(16), Q => first_q(16), R => \<const0>\ ); \opt_has_pipe.first_q_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(1), Q => first_q(1), R => \<const0>\ ); \opt_has_pipe.first_q_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(2), Q => first_q(2), R => \<const0>\ ); \opt_has_pipe.first_q_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(3), Q => first_q(3), R => \<const0>\ ); \opt_has_pipe.first_q_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(4), Q => first_q(4), R => \<const0>\ ); \opt_has_pipe.first_q_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(5), Q => first_q(5), R => \<const0>\ ); \opt_has_pipe.first_q_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(6), Q => first_q(6), R => \<const0>\ ); \opt_has_pipe.first_q_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(7), Q => first_q(7), R => \<const0>\ ); \opt_has_pipe.first_q_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(8), Q => first_q(8), R => \<const0>\ ); \opt_has_pipe.first_q_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => temp(9), Q => first_q(9), R => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ddsaccum is port ( L : out STD_LOGIC_VECTOR ( 1 downto 0 ); D : out STD_LOGIC_VECTOR ( 13 downto 0 ); I1 : out STD_LOGIC_VECTOR ( 13 downto 0 ); s_axis_phase_tvalid : in STD_LOGIC; aclk : in STD_LOGIC; reg_s_phase_fifo_din : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); end ddsaccum; architecture STRUCTURE of ddsaccum is signal \^l\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal acc_phase_shaped : STD_LOGIC_VECTOR ( 13 downto 0 ); signal temp : STD_LOGIC_VECTOR ( 16 downto 0 ); begin L(1 downto 0) <= \^l\(1 downto 0); \i_fabric.i_common.i_phase_acc\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized8\ port map ( D(13 downto 0) => D(13 downto 0), I1(13 downto 0) => I1(13 downto 0), aclk => aclk, \out\(15 downto 14) => \^l\(1 downto 0), \out\(13 downto 0) => acc_phase_shaped(13 downto 0), s_axis_phase_tvalid => s_axis_phase_tvalid, temp(16 downto 0) => temp(16 downto 0) ); \i_fabric.i_one_channel.i_accum\: entity work.\ddspipe_add__parameterized0\ port map ( L(15 downto 14) => \^l\(1 downto 0), L(13 downto 0) => acc_phase_shaped(13 downto 0), reg_s_phase_fifo_din(15 downto 0) => reg_s_phase_fifo_din(15 downto 0), s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0), s_axis_phase_tvalid => s_axis_phase_tvalid, temp(16 downto 0) => temp(16 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ddsdds_compiler_v6_0_rdy is port ( s_axis_phase_tvalid : in STD_LOGIC; aclk : in STD_LOGIC ); end ddsdds_compiler_v6_0_rdy; architecture STRUCTURE of ddsdds_compiler_v6_0_rdy is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal mutant_x_op : STD_LOGIC_VECTOR ( 2 downto 0 ); signal _0_mutant_x_op[0]_i_1\ : STD_LOGIC; signal _0_mutant_x_op[1]_i_1\ : STD_LOGIC; signal _0_mutant_x_op[2]_i_1\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \mutant_x_op[1]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \mutant_x_op[2]_i_1\ : label is "soft_lutpair12"; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \i_single_channel.i_non_trivial_lat.i_rdy\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized2\ port map ( aclk => aclk, mutant_x_op(2 downto 0) => mutant_x_op(2 downto 0), s_axis_phase_tvalid => s_axis_phase_tvalid ); \mutant_x_op[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"5A58" ) port map ( I0 => s_axis_phase_tvalid, I1 => mutant_x_op(2), I2 => mutant_x_op(0), I3 => mutant_x_op(1), O => _0_mutant_x_op[0]_i_1\ ); \mutant_x_op[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"F508" ) port map ( I0 => s_axis_phase_tvalid, I1 => mutant_x_op(2), I2 => mutant_x_op(0), I3 => mutant_x_op(1), O => _0_mutant_x_op[1]_i_1\ ); \mutant_x_op[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CCC4" ) port map ( I0 => s_axis_phase_tvalid, I1 => mutant_x_op(2), I2 => mutant_x_op(0), I3 => mutant_x_op(1), O => _0_mutant_x_op[2]_i_1\ ); \mutant_x_op_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => \<const1>\, D => _0_mutant_x_op[0]_i_1\, Q => mutant_x_op(0), R => \<const0>\ ); \mutant_x_op_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => aclk, CE => \<const1>\, D => _0_mutant_x_op[1]_i_1\, Q => mutant_x_op(1), R => \<const0>\ ); \mutant_x_op_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => aclk, CE => \<const1>\, D => _0_mutant_x_op[2]_i_1\, Q => mutant_x_op(2), R => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \ddssin_cos__parameterized0\ is port ( m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axis_phase_tvalid : in STD_LOGIC; aclk : in STD_LOGIC; L : in STD_LOGIC_VECTOR ( 1 downto 0 ); D : in STD_LOGIC_VECTOR ( 13 downto 0 ); I1 : in STD_LOGIC_VECTOR ( 13 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \ddssin_cos__parameterized0\ : entity is "sin_cos"; end \ddssin_cos__parameterized0\; architecture STRUCTURE of \ddssin_cos__parameterized0\ is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal cos_addr : STD_LOGIC_VECTOR ( 13 downto 0 ); signal cos_ls1 : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\ : STD_LOGIC_VECTOR ( 14 downto 0 ); signal \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal invert_sin : STD_LOGIC; signal mod_cos_addr : STD_LOGIC_VECTOR ( 13 downto 0 ); signal mod_sin_addr : STD_LOGIC_VECTOR ( 13 downto 0 ); signal _0_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC; signal _0_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC; signal _10_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _11_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _12_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _13_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _14_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _15_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _16_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _17_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _18_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _19_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _1_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _1_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC; signal _1_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC; signal _20_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _21_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _22_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _23_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _24_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _25_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _26_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _27_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _28_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _29_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _2_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _2_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC; signal _2_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC; signal _30_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _31_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _3_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _3_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC; signal _3_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC; signal _4_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _4_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC; signal _4_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC; signal _5_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _5_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC; signal _5_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC; signal _6_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _6_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC; signal _6_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC; signal _7_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _7_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\ : STD_LOGIC; signal _7_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\ : STD_LOGIC; signal _8_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal _9_i_rtl.i_quarter_table.i_addr_reg_c\ : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 0 ); signal sin_addr : STD_LOGIC_VECTOR ( 13 downto 0 ); signal sin_ls1 : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is ""; attribute bram_addr_begin : integer; attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is 0; attribute bram_addr_end : integer; attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is 16383; attribute bram_slice_begin : integer; attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is 0; attribute bram_slice_end : integer; attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\ : label is 1; attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is ""; attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is 0; attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is 16383; attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is 2; attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\ : label is 3; attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is ""; attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is 0; attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is 16383; attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is 4; attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\ : label is 5; attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is ""; attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is 0; attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is 16383; attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is 6; attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\ : label is 7; attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is ""; attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is 0; attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is 16383; attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is 8; attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\ : label is 9; attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is ""; attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is 0; attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is 16383; attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is 10; attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\ : label is 11; attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is ""; attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is 0; attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is 16383; attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is 12; attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\ : label is 13; attribute METHODOLOGY_DRC_VIOS of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is ""; attribute bram_addr_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is 0; attribute bram_addr_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is 16383; attribute bram_slice_begin of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is 14; attribute bram_slice_end of \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\ : label is 15; attribute use_sync_reset : string; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[0]\ : label is "no"; attribute use_sync_set : string; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[0]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[10]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[10]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[11]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[11]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[12]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[12]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[13]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[13]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[1]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[1]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[2]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[2]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[3]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[3]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[4]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[4]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[5]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[5]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[6]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[6]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[7]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[7]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[8]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[8]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[9]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[9]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[0]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[0]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[10]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[10]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[11]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[11]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[12]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[12]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[13]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[13]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[1]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[1]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[2]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[2]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[3]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[3]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[4]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[4]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[5]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[5]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[6]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[6]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[7]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[7]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[8]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[8]\ : label is "no"; attribute use_sync_reset of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[9]\ : label is "no"; attribute use_sync_set of \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[9]\ : label is "no"; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \i_rtl.i_quarter_table.i_addr_reg_c\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized12\ port map ( L(1 downto 0) => L(1 downto 0), O1 => _1_i_rtl.i_quarter_table.i_addr_reg_c\, O10 => _10_i_rtl.i_quarter_table.i_addr_reg_c\, O11 => _11_i_rtl.i_quarter_table.i_addr_reg_c\, O12 => _12_i_rtl.i_quarter_table.i_addr_reg_c\, O13 => _13_i_rtl.i_quarter_table.i_addr_reg_c\, O14 => _14_i_rtl.i_quarter_table.i_addr_reg_c\, O15 => _15_i_rtl.i_quarter_table.i_addr_reg_c\, O16 => _16_i_rtl.i_quarter_table.i_addr_reg_c\, O17 => _17_i_rtl.i_quarter_table.i_addr_reg_c\, O18 => _18_i_rtl.i_quarter_table.i_addr_reg_c\, O19 => _19_i_rtl.i_quarter_table.i_addr_reg_c\, O2 => _2_i_rtl.i_quarter_table.i_addr_reg_c\, O20 => _20_i_rtl.i_quarter_table.i_addr_reg_c\, O21 => _21_i_rtl.i_quarter_table.i_addr_reg_c\, O22 => _22_i_rtl.i_quarter_table.i_addr_reg_c\, O23 => _23_i_rtl.i_quarter_table.i_addr_reg_c\, O24 => _24_i_rtl.i_quarter_table.i_addr_reg_c\, O25 => _25_i_rtl.i_quarter_table.i_addr_reg_c\, O26 => _26_i_rtl.i_quarter_table.i_addr_reg_c\, O27 => _27_i_rtl.i_quarter_table.i_addr_reg_c\, O28 => _28_i_rtl.i_quarter_table.i_addr_reg_c\, O29 => _29_i_rtl.i_quarter_table.i_addr_reg_c\, O3 => _3_i_rtl.i_quarter_table.i_addr_reg_c\, O30 => _30_i_rtl.i_quarter_table.i_addr_reg_c\, O31 => _31_i_rtl.i_quarter_table.i_addr_reg_c\, O4 => _4_i_rtl.i_quarter_table.i_addr_reg_c\, O5 => _5_i_rtl.i_quarter_table.i_addr_reg_c\, O6 => _6_i_rtl.i_quarter_table.i_addr_reg_c\, O7 => _7_i_rtl.i_quarter_table.i_addr_reg_c\, O8 => _8_i_rtl.i_quarter_table.i_addr_reg_c\, O9 => _9_i_rtl.i_quarter_table.i_addr_reg_c\, aclk => aclk, \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(14 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(14 downto 0), invert_sin => invert_sin, \out\(14 downto 8) => p_0_in(6 downto 0), \out\(7 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(7 downto 0), s_axis_phase_tvalid => s_axis_phase_tvalid ); \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 1, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"5B1BC6C5B1BC6C5B1BC6C5B1BC6C5B1BC6C5B1BC6C6B1B06C6B1B06C6B1B06C6", INIT_01 => X"F1B16C6F1B16C6F1B16C6C1B1AC6C1B1AC6C1B1AC6C1B1AC6C1B1AC6C1B1BC6C", INIT_02 => X"1B1AC6C5B1BC6C5B1BC6C5B1BC6C5B1B06C6B1B06C6B1B06C6B1B06C6F1B16C6", INIT_03 => X"B1AC6C5B1BC6C5B1BC6C6B1B06C6B1B06C6F1B16C6F1B16C6F1B1AC6C1B1AC6C", INIT_04 => X"16C6F1B16C6C1B1AC6C5B1BC6C5B1B06C6B1B06C6B1B16C6F1B16C6C1B1AC6C1", INIT_05 => X"6F1B1AC6C1B1BC6C5B1B06C6B1B16C6F1B16C6C1B1AC6C5B1BC6C6B1B06C6B1B", INIT_06 => X"BC6C6B1B06C6F1B1AC6C1B1BC6C5B1B06C6F1B16C6C1B1AC6C5B1B06C6B1B16C", INIT_07 => X"B1AC6C5B1B06C6F1B1AC6C1B1BC6C6B1B16C6C1B1AC6C5B1B06C6F1B16C6C1B1", INIT_08 => X"B16C6C5B1B06C6F1B1AC6C5B1B06C6F1B1AC6C5B1B06C6F1B1AC6C5B1B06C6F1", INIT_09 => X"6C6C1B1BC6C6F1B1AC6C5B1B16C6C1B1BC6C6F1B1AC6C5B1B16C6C1B1BC6C6B1", INIT_0A => X"1B16C6C5B1B16C6C1B1B06C6C1B1B06C6F1B1BC6C6B1B1AC6C6B1B16C6C5B1B0", INIT_0B => X"B1B06C6C1B1B16C6C5B1B16C6C5B1B16C6C5B1B16C6C5B1B16C6C5B1B16C6C5B", INIT_0C => X"06C6C5B1B1AC6C6F1B1BC6C6C1B1B16C6C5B1B1AC6C6B1B1BC6C6F1B1B06C6C1", INIT_0D => X"1B1BC6C6C1B1B1AC6C6F1B1B06C6C5B1B1BC6C6C1B1B16C6C6B1B1BC6C6C1B1B", INIT_0E => X"1B06C6C6F1B1B16C6C6F1B1B16C6C6F1B1B16C6C6F1B1B06C6C6B1B1B06C6C5B", INIT_0F => X"C6B1B1B16C6C6C1B1B1BC6C6C6B1B1B16C6C6C1B1B1BC6C6C5B1B1B06C6C6B1B", INIT_10 => X"6F1B1B1BC6C6C6C1B1B1B06C6C6C1B1B1B06C6C6C1B1B1B06C6C6F1B1B1BC6C6", INIT_11 => X"AC6C6C6C1B1B1B1AC6C6C6C1B1B1B1AC6C6C6F1B1B1B06C6C6C5B1B1B1AC6C6C", INIT_12 => X"6C6C6C6F1B1B1B1BC6C6C6C6F1B1B1B1BC6C6C6C6B1B1B1B16C6C6C6C1B1B1B1", INIT_13 => X"1B1B16C6C6C6C6C5B1B1B1B1B06C6C6C6C6B1B1B1B1B06C6C6C6C5B1B1B1B1AC", INIT_14 => X"6C6C6C6C6C6C1B1B1B1B1B1B06C6C6C6C6C6B1B1B1B1B1B06C6C6C6C6C5B1B1B", INIT_15 => X"B16C6C6C6C6C6C6C6C6B1B1B1B1B1B1B1B06C6C6C6C6C6C6C5B1B1B1B1B1B1BC", INIT_16 => X"1B1B1B1B1B1B1B1B1B1B1B1B1AC6C6C6C6C6C6C6C6C6C6C1B1B1B1B1B1B1B1B1", INIT_17 => X"B1B1B1B1B1B1B1B1B1B1B1B1B1B06C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6F", INIT_18 => X"B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1", INIT_19 => X"6C6C6C6C6C6C6C6C6C6C6C6C6C6C6C6CB1B1B1B1B1B1B1B1B1B1B1B1B1B1B1B1", INIT_1A => X"B1B1B1B1B1B1B1B1C6C6C6C6C6C6C6C6C6C6DB1B1B1B1B1B1B1B1B1B1B1B1C6C", INIT_1B => X"6C6C6DB1B1B1B1B1B1C6C6C6C6C6C6C71B1B1B1B1B1B1B6C6C6C6C6C6C6C6CB1", INIT_1C => X"C6C6C6DB1B1B1B1B6C6C6C6C6DB1B1B1B1B1C6C6C6C6C6DB1B1B1B1B1B6C6C6C", INIT_1D => X"C6C6CB1B1B1B2C6C6C6CB1B1B1B1C6C6C6C61B1B1B1B6C6C6C6C71B1B1B1B2C6", INIT_1E => X"6C71B1B186C6C6CB1B1B1C6C6C6DB1B1B1C6C6C6CB1B1B186C6C6C71B1B1B2C6", INIT_1F => X"B1B1B6C6C6DB1B186C6C61B1B186C6C61B1B186C6C61B1B1B6C6C6DB1B1B2C6C", INIT_20 => X"1B6C6C71B1B6C6C71B1B6C6C61B1B2C6C6DB1B1C6C6CB1B1B6C6C61B1B1C6C6C", INIT_21 => X"6C6DB1B2C6C71B186C6DB1B2C6C71B186C6CB1B1C6C6DB1B2C6C61B1B6C6C71B", INIT_22 => X"CB1B2C6CB1B2C6CB1B2C6CB1B1C6C71B1C6C61B186C6DB1B6C6CB1B2C6C71B18", INIT_23 => X"1B2C6DB186C61B1C6CB1B2C6DB1B6C61B186C71B1C6C71B1C6CB1B2C6CB1B2C6", INIT_24 => X"B6C71B2C6DB186CB1B6C61B1C6CB1B6C71B2C6DB186C71B1C6CB1B6C61B1C6CB", INIT_25 => X"C6DB186CB186CB186C71B6C71B2C61B2C6DB1C6CB186C71B6C61B2C6DB1C6CB1", INIT_26 => X"6C7186CB186CB186DB1C6DB1C6DB1C6DB1C6DB1C6DB1C6DB1C6DB1C6DB1C6DB1", INIT_27 => X"2C71B6CB1C6DB2C61B6C7186CB1C6DB2C61B6C7186CB186DB1C61B2C61B2C71B", INIT_28 => X"B2C7186DB2C71B6CB1C61B6CB1C61B2C7186DB2C61B6CB1C6DB2C71B6CB1C6DB", INIT_29 => X"6DB6CB1C6186DB2C7186DB6CB1C61B6CB1C6186DB2C7186DB2C7186DB2C7186D", INIT_2A => X"B1C71861B6DB2CB1C6186DB6CB2C71861B6CB2C71C61B6DB2C71861B6CB2C718", INIT_2B => X"1861B6DB6DB2CB2C71C7186186DB6CB2CB1C71C6186DB6CB2CB1C71861B6DB2C", INIT_2C => X"DB6DB6DB6DB2CB2CB2CB2CB1C71C71C71C61861861B6DB6DB6CB2CB2C71C71C6", INIT_2D => X"2CB2DB6DB6DB6DB6DB6DB6DB6D861861861861861861861861861B6DB6DB6DB6", INIT_2E => X"CB2CB2DB6DB61861871C71C72CB2CB6DB6DB6D861861861C71C71C72CB2CB2CB", INIT_2F => X"C71CB2DB6D861C71CB2DB6D861871C72CB6DB61861C71C72CB2DB6D861861C71", INIT_30 => X"D871CB2DB61871CB2D861C72CB6D861C72CB6D861871CB2DB61871C72CB6D861", INIT_31 => X"B6D871CB6D871CB6D861CB2D861CB2DB61C72DB61872CB6D871CB2DB61C72CB6", INIT_32 => X"61CB61872DB61CB6D872CB61C72D861CB6D872CB61872DB61C72D861CB2D861C", INIT_33 => X"72D872D871CB61CB61872D872DB61CB61872D872CB61CB6D872DB61CB61872D8", INIT_34 => X"CB61CB61CB61CB61CB61CB61CB61CB61CB2D872D872D872D871CB61CB61CB618", INIT_35 => X"721CB61CB61CB72D872D872D872D8761CB61CB61CB61CB61CB61CB61CB61CB61", INIT_36 => X"62D872DCB61C872D8761CB61D872D8721CB61C872D872D8B61CB61C872D872D8", INIT_37 => X"721CB72D8B61D8721CB62D8761CB72D8B61C872D8B61C872D8B61CB72D8761CB", INIT_38 => X"CB72DCB72D8B62D8B62D8761D8721C8721CB72D8B62D8761D8721CB72D8B61D8", INIT_39 => X"62D8B62DCB721C8721D8761D8762D8B62D8B62DCB72DCB72DCB72DCB72DCB72D", INIT_3A => X"1C8762DC8721D8B62DC8761D8B72DC8761D8B62DC8721D8762D8B72DC8721D87", INIT_3B => X"D8B762DC8762DC8762DC8762D8B721D8B721D8B721D8B62DC8762DC8721D8B72", INIT_3C => X"DD8B721DC87621D8B722DC8762DD8B721D8B762DC8762DC8B721D8B721D8B721", INIT_3D => X"22DC8B722DD8B762DD8B762DD8B762DD8B762DD8B722DC8B721DC87721D88762", INIT_3E => X"87722DD887722DD887722DC8B7621DC8B722DD887721DC8B762DD887621DC877", INIT_3F => X"21DC887722DDC8B7722DD88B7621DD887722DDC8B7621DC8B7722DD887722DD8", INIT_40 => X"C8877622DDC8877622DDC8877622DDC8B77221DD8877622DD88B7722DDC8B772", INIT_41 => X"B776221DDC88B77622DDD888776221DDC88777221DD888776221DD88B77222DD", INIT_42 => X"776222DDDC8887776222DDD888B777222DDDC88B777222DDD888B776221DDC88", INIT_43 => X"7762222DDDD8888B77772222DDDD888877772222DDDD888877762221DDD888B7", INIT_44 => X"7777622222DDDDDD88888B77777222221DDDDC8888B7777622221DDDD8888B77", INIT_45 => X"88777777777222222221DDDDDDDC888888877777776222222DDDDDDD88888877", INIT_46 => X"888888888888888888777777777777777222222222222DDDDDDDDDDD88888888", INIT_47 => X"DDD2222222222222222222222221DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDC", INIT_48 => X"77777777777748888888888888888889DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD", INIT_49 => X"8888DDDDDDDD222222223777777774888888888DDDDDDDDDDD22222222222277", INIT_4A => X"E2222377777888889DDDDD2222227777778888889DDDDDD22222237777774888", INIT_4B => X"7748889DDDE222377748889DDDD22223777788889DDDD222237777488889DDDD", INIT_4C => X"DDDE223774888DDD22237778889DDE2227774888DDDD22237778888DDDE22237", INIT_4D => X"2377889DDE22774889DD222774889DDE22777888DDD222777888DDD222777888", INIT_4E => X"889DE2277889DE2277489DD2237788DDE2277488DDE2277488DDE2277488DDE2", INIT_4F => X"D227788DD227788DD227788DDE237489DE237788DD2237489DE2277889DE2277", INIT_50 => X"3788DE23788DE23748DD237489D227789DE23748DD227789DE237489DE27788D", INIT_51 => X"89D22748DE27489D23789DE27489D23788DE27789D22748DD23748DE23788DE2", INIT_52 => X"DE2749D23789D23789E2748DE2748DE2748DE2748DE2748DE2748DE23789D237", INIT_53 => X"2378DE3789E2749D2348DE3789E2749D2378DE2749D2378DE2749D23789E2748", INIT_54 => X"378DE348D2349D2749D2749E2789E2789E2789E2789E2789D2749D2749D2348D", INIT_55 => X"349E378D2749E378D2749E378D2349E278DE348D2749E278DE348D2749E2789E", INIT_56 => X"789E349E349E349D278D278D2349E349E278D278DE349E378D278DE349E278D2", INIT_57 => X"349E34D278D278D278D278D278D278D278D278D278D278D278D278D278D278D2", INIT_58 => X"278E349E38D279E349E78D278E349E34D278D279E349E349278D278D249E349E", INIT_59 => X"D249E78D349278E349279E34D279E34D279E34D279E349278E349E78D249E34D", INIT_5A => X"4D249E79E38E34D249E79E38D349249E78E34D249E78E34D249E78D349279E38", INIT_5B => X"E79E79E79E78E38E38E34D34D34D249249E79E78E38E34D349249279E78E38D3", INIT_5C => X"4D34D34D38E38E38E79E79E79E79E79249249249249249249249249249249E79", INIT_5D => X"934D38E79E4924D34E38E7924924D34E38E79E4924934D34E38E39E79E492492", INIT_5E => X"E7924D38E7934E39E4934E39E4934E39E4924D38E7924D34E39E4934D38E79E4", INIT_5F => X"E4938E4938E4934E7934E3924E39E4D38E4938E7924E39E4D38E7934E39E4938", INIT_60 => X"E7938E4939E4E3934E7938E4D39E4E3924E7934E7934E4938E4938E4938E4938", INIT_61 => X"924E4D3934E4E3938E4E3938E4E3938E4D3934E4D3924E4939E4E3934E493924", INIT_62 => X"393924E4E793938E4E4D3939E4E4D3939E4E4D3938E4E493934E4E3939E4E493", INIT_63 => X"9393924E4E4E4939393924E4E4E79393934E4E4E79393924E4E49393934E4E49", INIT_64 => X"E4E4E4E4E4E4E4D39393939393939E4E4E4E4E4E493939393938E4E4E4E4E393", INIT_65 => X"393939393939393939393939393939393939393939393939393939393924E4E4", INIT_66 => X"39393939394E4E4E4E4E4E93939393939393A4E4E4E4E4E4E4E4E4E4E9393939", INIT_67 => X"E4E4E939393E4E4E4F939393E4E4E4E93939394E4E4E4E93939393A4E4E4E4E5", INIT_68 => X"4E9393E4E4F9390E4E439390E4E439390E4E4F9393E4E4E539390E4E4E939390", INIT_69 => X"E4E9394E4393A4E5393E4E9390E4E9390E4E9390E4E9393E4E5393A4E439394E", INIT_6A => X"390E4390E4F93E4F93E4E93A4E9394E5390E4F93E4E9394E5390E4F93A4E5390", INIT_6B => X"394E93A4F90E4394E93A4F93E4390E5394E93A4E93E4F93E4F93E4390E4390E4", INIT_6C => X"E93E43A4F90E53E4394E93E53A4F90E53A4F90E53A4F90E53A4F90E53A4F93E4", INIT_6D => X"93E53E53A43A4394F94E90E93E53A43A4F94E90E53E53A4394E90E53E43A4F90", INIT_6E => X"F94F94F94F943A43A43A43A43A43A43A43A43A43A4394F94F94F94F90E90E90E", INIT_6F => X"3E90F94FA43E53E90E94F943A43E53E90E90F94F943A43A53E53E50E90E90E94", INIT_70 => X"0E943A53E94FA53E90F943E50E94FA53E90F943A53E90F943A53E90E94FA43E5", INIT_71 => X"FA50E943E94FA50F943E94FA50E943E50FA43E94FA53E943A50E943A50E943A5", INIT_72 => X"943E943E943E943E943A50FA50FA50FA50F943E943E943A50FA50F943E943E50", INIT_73 => X"FA50FE943E940FA50FA50FE943E943E950FA50FA50FA50FA543E943E943E943E", INIT_74 => X"3EA50FE940FA543EA50FE943FA503E940FA503E940FA503E943FA50FA943E950", INIT_75 => X"FE9503EA503EA543FA543FA543FA543FA543FA503EA503E950FE950FA943FA54", INIT_76 => X"A540FEA540FA9503FA940FEA503FA940FEA503FA940FE9503EA543FA940FA950", INIT_77 => X"0FFA9503FAA540FEA5403FA9503FA9503FA9503FA9503FA9503FA9503FA9503F", INIT_78 => X"540FFAA5403FAA5503FEA5503FEA5503FEA5503FEA5403FA9540FEA9503FEA54", INIT_79 => X"5403FFAA5500FFEA95403FEA95403FEA95403FEA95403FEA9500FFAA5503FEA9", INIT_7A => X"00FFEAA955003FFAA95400FFEAA55403FFAA95500FFEA95500FFEA95500FFAA9", INIT_7B => X"AAA9554003FFFAAA555000FFFAAA554003FFEAA955000FFEAA955003FFEAA554", INIT_7C => X"03FFFEAAA955550000FFFEAAA95554000FFFEAAA95550003FFFAAA5554000FFF", INIT_7D => X"0000FFFFFFAAAAAA55555400000FFFFFEAAAA95555400003FFFFAAAA95555000", INIT_7E => X"3FFFFFFFFFFFAAAAAAAAAA955555555400000000FFFFFFFEAAAAAAA555555400", INIT_7F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555500000000000000", INIT_A => X"000000000", INIT_B => X"000000000", RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", READ_WIDTH_A => 2, READ_WIDTH_B => 2, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 2, WRITE_WIDTH_B => 0 ) port map ( ADDRARDADDR(15) => \<const1>\, ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0), ADDRARDADDR(0) => \<const0>\, ADDRBWRADDR(15) => \<const1>\, ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0), ADDRBWRADDR(0) => \<const0>\, CASCADEINA => \<const1>\, CASCADEINB => \<const0>\, CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => aclk, CLKBWRCLK => aclk, DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DBITERR_UNCONNECTED\, DIADI(31) => \<const0>\, DIADI(30) => \<const0>\, DIADI(29) => \<const0>\, DIADI(28) => \<const0>\, DIADI(27) => \<const0>\, DIADI(26) => \<const0>\, DIADI(25) => \<const0>\, DIADI(24) => \<const0>\, DIADI(23) => \<const0>\, DIADI(22) => \<const0>\, DIADI(21) => \<const0>\, DIADI(20) => \<const0>\, DIADI(19) => \<const0>\, DIADI(18) => \<const0>\, DIADI(17) => \<const0>\, DIADI(16) => \<const0>\, DIADI(15) => \<const0>\, DIADI(14) => \<const0>\, DIADI(13) => \<const0>\, DIADI(12) => \<const0>\, DIADI(11) => \<const0>\, DIADI(10) => \<const0>\, DIADI(9) => \<const0>\, DIADI(8) => \<const0>\, DIADI(7) => \<const0>\, DIADI(6) => \<const0>\, DIADI(5) => \<const0>\, DIADI(4) => \<const0>\, DIADI(3) => \<const0>\, DIADI(2) => \<const0>\, DIADI(1) => \<const1>\, DIADI(0) => \<const1>\, DIBDI(31) => \<const1>\, DIBDI(30) => \<const1>\, DIBDI(29) => \<const1>\, DIBDI(28) => \<const1>\, DIBDI(27) => \<const1>\, DIBDI(26) => \<const1>\, DIBDI(25) => \<const1>\, DIBDI(24) => \<const1>\, DIBDI(23) => \<const1>\, DIBDI(22) => \<const1>\, DIBDI(21) => \<const1>\, DIBDI(20) => \<const1>\, DIBDI(19) => \<const1>\, DIBDI(18) => \<const1>\, DIBDI(17) => \<const1>\, DIBDI(16) => \<const1>\, DIBDI(15) => \<const1>\, DIBDI(14) => \<const1>\, DIBDI(13) => \<const1>\, DIBDI(12) => \<const1>\, DIBDI(11) => \<const1>\, DIBDI(10) => \<const1>\, DIBDI(9) => \<const1>\, DIBDI(8) => \<const1>\, DIBDI(7) => \<const1>\, DIBDI(6) => \<const1>\, DIBDI(5) => \<const1>\, DIBDI(4) => \<const1>\, DIBDI(3) => \<const1>\, DIBDI(2) => \<const1>\, DIBDI(1) => \<const1>\, DIBDI(0) => \<const1>\, DIPADIP(3) => \<const0>\, DIPADIP(2) => \<const0>\, DIPADIP(1) => \<const0>\, DIPADIP(0) => \<const0>\, DIPBDIP(3) => \<const1>\, DIPBDIP(2) => \<const1>\, DIPBDIP(1) => \<const1>\, DIPBDIP(0) => \<const1>\, DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOADO_UNCONNECTED\(31 downto 2), DOADO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(1 downto 0), DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOBDO_UNCONNECTED\(31 downto 2), DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(1 downto 0), DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => s_axis_phase_tvalid, ENBWREN => s_axis_phase_tvalid, INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_INJECTDBITERR_UNCONNECTED\, INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_INJECTSBITERR_UNCONNECTED\, RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => s_axis_phase_tvalid, REGCEB => s_axis_phase_tvalid, RSTRAMARSTRAM => \<const0>\, RSTRAMB => \<const0>\, RSTREGARSTREG => \<const0>\, RSTREGB => \<const0>\, SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0_SBITERR_UNCONNECTED\, WEA(3) => \<const0>\, WEA(2) => \<const0>\, WEA(1) => \<const0>\, WEA(0) => \<const0>\, WEBWE(7) => \<const0>\, WEBWE(6) => \<const0>\, WEBWE(5) => \<const0>\, WEBWE(4) => \<const0>\, WEBWE(3) => \<const0>\, WEBWE(2) => \<const0>\, WEBWE(1) => \<const0>\, WEBWE(0) => \<const0>\ ); \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 1, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"394E53A4E93A4F93E4F90E4390E5394E53A4E93A4F93E4390E4394E5394E93A4", INIT_01 => X"3E4390E4394E5394E93A4F93E4F90E4390E5394E53A4E93A4F93E4F90E4390E5", INIT_02 => X"4E93A4F93E4F90E4390E5394E53A4E93E4F93E4390E4394E5394E93A4E93E4F9", INIT_03 => X"4390E5394E53A4E93A4F93E4390E4394E5394E93A4E93E4F93E4390E5394E53A", INIT_04 => X"93A4E93E4F90E4390E5394E53A4E93E4F93E4390E4394E5394E93A4F93E4F90E", INIT_05 => X"93E4390E5394E53A4E93E4F93E4390E4394E53A4E93A4F93E4F90E4394E5394E", INIT_06 => X"90E5394E93A4E93E4F90E4390E5394E93A4E93E4F90E4390E5394E93A4E93E4F", INIT_07 => X"94E53A4E93E4F93E4390E5394E53A4E93E4F90E4390E5394E93A4E93E4F90E43", INIT_08 => X"94E53A4E93E4F93E4390E5394E93A4E93E4F90E4394E5394E93A4F93E4390E43", INIT_09 => X"90E5394E53A4E93E4F90E4394E53A4E93A4F93E4390E5394E93A4F93E4F90E43", INIT_0A => X"93E4F90E4394E53A4E93E4F90E4394E5394E93A4F93E4390E5394E93A4F93E43", INIT_0B => X"4394E53A4E93E4F90E4394E53A4E93E4F90E4394E53A4E93E4F90E4394E53A4E", INIT_0C => X"4E53A4E93E4F90E4394E53A4F93E4390E5394E93A4F93E4390E5394E93E4F90E", INIT_0D => X"394E53A4F93E4390E5394E93E4F90E4394E53A4F93E4390E5394E93A4F90E439", INIT_0E => X"E4390E5394E93E4F90E4394E93A4F93E4394E53A4E93E4390E5394E93E4F90E4", INIT_0F => X"5394E93E4F90E5394E93A4F90E4394E93A4F90E4394E53A4F93E4394E53A4E93", INIT_10 => X"394E93E4F90E53A4E93E4390E53A4E93E4390E53A4E93E4390E5394E93E4F90E", INIT_11 => X"90E53A4F93E4394E53A4F90E4394E93A4F90E4394E93E4F90E5394E93E4F90E5", INIT_12 => X"3A4F90E4394E93E4F90E53A4E93E4394E53A4F90E4394E93E4F90E53A4E93E43", INIT_13 => X"93E4390E53A4F90E4394E93E4390E53A4F93E4394E93E4F90E53A4E93E4394E5", INIT_14 => X"E53A4F90E53A4E93E4394E93E4F90E53A4F93E4394E93E4390E53A4F90E4394E", INIT_15 => X"3E4F90E53A4F90E53A4E93E4394E93E4394E53A4F90E53A4F93E4394E93E4390", INIT_16 => X"4E93E4394E93E4394E93E4394E53A4F90E53A4F90E53A4F93E4394E93E4394E9", INIT_17 => X"4394E93E4394E93E4394E93E4394E53A4F90E53A4F90E53A4F90E53A4F90E539", INIT_18 => X"4394E93E4394E93E4394E93E4394E93E4394E93E4394E93E4394E93E4394E93E", INIT_19 => X"4F90E53A4F90E53A4F90E53A4F90E53A4394E93E4394E93E4394E93E4394E93E", INIT_1A => X"3E4394E93E4394E90E53A4F90E53A4F90E53A4394E93E4394E93E4394E93E53A", INIT_1B => X"E53A4F94E93E4394E90E53A4F90E53A4394E93E4394E93E53A4F90E53A4F90E9", INIT_1C => X"53A4F90E93E4394E90E53A4F90E93E4394E90E53A4F90E53E4394E93E43A4F90", INIT_1D => X"F90E53E4394E90E53A4F94E93E43A4F90E53E4394E93E53A4F90E93E4394E90E", INIT_1E => X"4F94E93E53A4F90E93E43A4F90E53E4394F90E53A4394E90E53A4F94E93E43A4", INIT_1F => X"94E93E53A4F94E90E53A4394E90E53A4394E90E53A4394E93E53A4F94E93E53A", INIT_20 => X"E43A4F94E93E53A4394E90E53E4394F90E53E43A4F90E93E43A4F94E93E53A4F", INIT_21 => X"E53A4394F90E93E53A4F94E90E53E43A4F90E93E53A4F94E90E53E4394F90E93", INIT_22 => X"A4394F90E93E53A4394F90E93E53A4394F90E93E53A4F94E90E53E43A4F94E90", INIT_23 => X"93E53A43A4F94E90E53E43A4F94E90E93E53A4394F90E93E53A4394F90E93E53", INIT_24 => X"3E53E43A4F94F90E93E53E43A4F94E90E93E53A43A4F94E90E53E43A4394F90E", INIT_25 => X"A4F94F90E90E53E53A4394F94E90E93E53A43A4F94F90E93E53E43A4F94F90E9", INIT_26 => X"3A43A4F94F90E90E53E53A43A4F94F90E90E53E53A43A4F94F90E90E53E53A43", INIT_27 => X"4F94E90E90E53E53E43A43A4F94F90E90E93E53E53A43A4F94F94E90E93E53E4", INIT_28 => X"43A43A4F94F94E90E90E93E53E53E43A43A4F94F94E90E90E53E53E43A43A4F9", INIT_29 => X"4F94F94F94F90E90E90E53E53E53E43A43A43A4F94F94F90E90E90E53E53E53A", INIT_2A => X"3E53E53E43A43A43A43A4F94F94F94F94E90E90E90E93E53E53E53E43A43A43A", INIT_2B => X"E53E43A43A43A43A43A43A43A4F94F94F94F94F94F90E90E90E90E90E93E53E5", INIT_2C => X"0E90E90E90E90E90E90E90E90E90E90E90E90E90E93E53E53E53E53E53E53E53", INIT_2D => X"90E90E90E90E90E90E90E90E90F94F94F94F94F94F94F94F94F94E90E90E90E9", INIT_2E => X"A43A43A43A43E53E53E53E53E53E53E53E53E50E90E90E90E90E90E90E90E90E", INIT_2F => X"A43A43A43A53E53E53E53E50E90E90E90E90E94F94F94F94F94F94FA43A43A43", INIT_30 => X"50E90E90E94F94F94FA43A43A43A53E53E53E50E90E90E90E94F94F94F94FA43", INIT_31 => X"3E50E90E90F94F94FA43A43A53E53E53E90E90E94F94F94FA43A43A43E53E53E", INIT_32 => X"94F943A43A43E53E50E90E94F94FA43A43A53E53E90E90E94F94FA43A43A53E5", INIT_33 => X"E90F94FA43A43E53E90E90F94F943A43E53E50E90E94F94FA43A43E53E90E90F", INIT_34 => X"F943A43E53E90E94F943A43E53E90E94F94FA43A53E50E90F94F943A43E53E90", INIT_35 => X"E94F943A43E53E90F94FA43A53E50E94F943A43E53E90E94F943A43E53E90E94", INIT_36 => X"94FA43A53E90F94FA43E53E90F94FA43E53E90F94FA43A53E90E94FA43A53E50", INIT_37 => X"3E90E94FA43E50E94F943A53E90E94FA43E50E90F943A53E50E94F943A53E90E", INIT_38 => X"53E90F943A53E90F943A53E90F943A53E90E94FA43E50E94FA43E53E90F943A5", INIT_39 => X"94FA43E50E943A53E90F943A53E90F943A53E90F943A53E90F943A53E90F943A", INIT_3A => X"90F943A50E94FA43E50F943A53E90FA43E50E94FA53E90F943A53E90FA43E50E", INIT_3B => X"0F943E50F943A50E94FA53E90F943E50E943A53E94FA43E50F943A50E94FA43E", INIT_3C => X"A50E943A50E943A53E94FA53E90FA43E90F943E50F943A50E943A53E94FA43E9", INIT_3D => X"3E50F943E50F943E50F943E50F943E50F943E50F943E50F943E50F943E50F943", INIT_3E => X"0E943A50F943E50FA43E90FA43E94FA53E94FA50E943A50E943A50F943E50F94", INIT_3F => X"3E50FA43E90FA53E943A50F943E90FA53E94FA50E943E50F943E90FA53E94FA5", INIT_40 => X"A50E943E50FA53E943A50FA43E94FA50E943E90FA53E943A50F943E90FA53E94", INIT_41 => X"3E943E90FA50E943E90FA50F943E94FA50F943E94FA50F943E94FA50E943E90F", INIT_42 => X"43E943A50FA50E943E94FA50FA43E943E50FA50E943E94FA50FA43E943E50FA5", INIT_43 => X"43E943E50FA50FA43E943E94FA50FA50E943E943A50FA50F943E943E50FA50E9", INIT_44 => X"3E943E943E50FA50FA50F943E943E943E50FA50FA53E943E943E90FA50FA53E9", INIT_45 => X"A53E943E943E943E943E50FA50FA50FA50F943E943E943E94FA50FA50FA50F94", INIT_46 => X"FA50FA50FA50FA50FA43E943E943E943E943E943E943E50FA50FA50FA50FA50F", INIT_47 => X"FA543E943E943E943E943E943E94FA50FA50FA50FA50FA50FA50FA50FA50FA50", INIT_48 => X"E943E943E943FA50FA50FA50FA50FA50FA50FA50FA50FA50FA50FA50FA50FA50", INIT_49 => X"50FA50FA50FA943E943E943E943E950FA50FA50FA50FA50FA543E943E943E943", INIT_4A => X"A943E943E940FA50FA50FA943E943E943EA50FA50FA50FA943E943E943E950FA", INIT_4B => X"E950FA50FA543E943EA50FA50FA943E943E950FA50FA543E943E940FA50FA50F", INIT_4C => X"A50FE943EA50FA503E943E950FA50FE943E950FA50FA943E943FA50FA503E943", INIT_4D => X"43E950FA503E940FA50FE943EA50FA503E943FA50FA943E940FA50FE943E950F", INIT_4E => X"A50FA943EA50FA943EA50FA943E950FA543E950FA503E940FA50FE943FA50FA9", INIT_4F => X"A943EA50FE943FA503E940FA503E950FA543E950FA943EA50FA943EA50FA943E", INIT_50 => X"940FA543EA50FE940FA543EA50FE943FA503E950FA943EA50FE940FA503E950F", INIT_51 => X"0FA943FA503EA50FE940FA543FA503E950FA943FA543EA50FE940FA543EA50FE", INIT_52 => X"503EA503E950FE940FA940FA543FA503EA50FE950FA940FA543FA503E950FE94", INIT_53 => X"943FA543FA543FA543FA503EA503EA503E950FE950FE940FA940FA943FA543FA", INIT_54 => X"43FA540FA940FA940FA940FA940FA940FA940FA940FA940FA940FA940FA940FA", INIT_55 => X"EA503EA543FA543FA940FA940FE950FE950FEA503EA503EA503FA543FA543FA5", INIT_56 => X"3FA540FA950FEA503EA543FA940FA950FE9503EA503FA543FA940FA950FE9503", INIT_57 => X"3FA540FE9503EA543FA940FE9503EA543FA940FE9503EA543FA940FE9503EA54", INIT_58 => X"E9503FA540FE9503FA540FE9503FA540FE9503EA540FA9503EA543FA950FEA50", INIT_59 => X"03FA540FEA543FA9503EA540FE9503FA940FEA543FA9503EA540FA9503FA540F", INIT_5A => X"503FA540FEA540FEA503FA9503FA950FEA540FEA503FA9503FA540FEA543FA95", INIT_5B => X"03FA9503FA9503FA9503FA9503FA9503FA540FEA540FEA540FEA543FA9503FA9", INIT_5C => X"FA9503FA9503FA9503FA9503FA9503FEA540FEA540FEA540FEA540FEA540FA95", INIT_5D => X"03FA9503FAA540FEA540FEA9503FA9503FA9500FEA540FEA540FEA540FFA9503", INIT_5E => X"03FEA540FEA9503FAA540FEA5503FA9500FEA540FEA9503FA9500FEA540FEA55", INIT_5F => X"FFA9500FEA5503FA9540FEA9503FAA540FFA9503FEA540FFA9503FEA540FFA95", INIT_60 => X"5403FAA540FFA9540FEA9500FEA5503FEA5403FA9540FFA9500FEA5503FAA540", INIT_61 => X"A9500FEA9500FEA9500FEA9500FEA9500FEA9500FEA9500FEA5503FEA5503FEA", INIT_62 => X"95403FAA5403FEA5500FEA9500FFA9540FFAA5403FAA5503FEA5503FEA5500FE", INIT_63 => X"03FEA9500FFAA5403FEA9500FFA95403FEA5500FEA95403FAA5503FEA9500FFA", INIT_64 => X"5500FFAA5500FFA95403FEA95403FAA5500FFAA5503FEA95403FAA5500FFA954", INIT_65 => X"95403FEA95403FEA95403FEA95403FEA95403FEA95403FEA95403FEA9540FFAA", INIT_66 => X"403FEA95400FFAA5500FFAA95403FEA95403FFAA5500FFAA5500FFAA55403FEA", INIT_67 => X"AA55003FEA95500FFAA95403FFAA55003FEA95500FFAA55403FEA95500FFAA55", INIT_68 => X"FAA95400FFAA95500FFEA95500FFEA95500FFAA95400FFAA95400FFAA55403FF", INIT_69 => X"AA55400FFEA955003FEAA55400FFAA95500FFEAA55003FEAA55403FFAA95400F", INIT_6A => X"400FFEAA55003FFAA955003FFAA955003FFAA55400FFEAA55400FFAA955003FF", INIT_6B => X"955003FFAAA55400FFEAA554003FFAA955003FFAA955003FFAA955400FFEAA55", INIT_6C => X"554003FFAAA554003FFAA955400FFFAA955000FFEAA555003FFAAA55400FFEAA", INIT_6D => X"03FFEAA9554003FFAAA555003FFEAA955000FFFAA9554003FFAAA554003FFAAA", INIT_6E => X"555000FFFAAA9554003FFEAA9554003FFEAA9554003FFAAA555000FFFAAA5550", INIT_6F => X"9555000FFFEAA9555000FFFEAA9554000FFFAAA5554003FFEAA9555000FFFAAA", INIT_70 => X"50003FFEAAA5554000FFFEAAA5550003FFFAAA9554000FFFEAA9555000FFFEAA", INIT_71 => X"AAAA5554000FFFFAAA95550000FFFEAAA5554000FFFEAAA95550003FFFAAA955", INIT_72 => X"FFEAAA955540003FFFEAAA55550000FFFFAAA955540003FFFAAAA55540003FFF", INIT_73 => X"AAAA555540000FFFFAAAA555540003FFFFAAAA55550000FFFFEAAA955540003F", INIT_74 => X"40000FFFFFAAAA9555500003FFFFEAAAA555540000FFFFEAAA9555500003FFFF", INIT_75 => X"55555400003FFFFEAAAA95555400003FFFFEAAAA9555540000FFFFFAAAA95555", INIT_76 => X"5555000000FFFFFEAAAAA55555400000FFFFFEAAAAA55555400003FFFFFAAAAA", INIT_77 => X"0FFFFFFEAAAAAA5555554000003FFFFFEAAAAA9555554000003FFFFFEAAAAA95", INIT_78 => X"55500000003FFFFFFEAAAAAA955555540000003FFFFFFEAAAAAA555555400000", INIT_79 => X"555400000000FFFFFFFFEAAAAAAA95555555400000003FFFFFFFAAAAAAA95555", INIT_7A => X"00FFFFFFFFFFEAAAAAAAAA5555555554000000000FFFFFFFFFAAAAAAAAA55555", INIT_7B => X"5555555554000000000000FFFFFFFFFFFEAAAAAAAAAAA5555555555400000000", INIT_7C => X"A95555555555555555000000000000000FFFFFFFFFFFFFFEAAAAAAAAAAAAA555", INIT_7D => X"555500000000000000000000000FFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAA", INIT_7E => X"EAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555555555", INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_A => X"000000000", INIT_B => X"000000000", RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", READ_WIDTH_A => 2, READ_WIDTH_B => 2, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 2, WRITE_WIDTH_B => 0 ) port map ( ADDRARDADDR(15) => \<const1>\, ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0), ADDRARDADDR(0) => \<const0>\, ADDRBWRADDR(15) => \<const1>\, ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0), ADDRBWRADDR(0) => \<const0>\, CASCADEINA => \<const1>\, CASCADEINB => \<const0>\, CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => aclk, CLKBWRCLK => aclk, DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DBITERR_UNCONNECTED\, DIADI(31) => \<const0>\, DIADI(30) => \<const0>\, DIADI(29) => \<const0>\, DIADI(28) => \<const0>\, DIADI(27) => \<const0>\, DIADI(26) => \<const0>\, DIADI(25) => \<const0>\, DIADI(24) => \<const0>\, DIADI(23) => \<const0>\, DIADI(22) => \<const0>\, DIADI(21) => \<const0>\, DIADI(20) => \<const0>\, DIADI(19) => \<const0>\, DIADI(18) => \<const0>\, DIADI(17) => \<const0>\, DIADI(16) => \<const0>\, DIADI(15) => \<const0>\, DIADI(14) => \<const0>\, DIADI(13) => \<const0>\, DIADI(12) => \<const0>\, DIADI(11) => \<const0>\, DIADI(10) => \<const0>\, DIADI(9) => \<const0>\, DIADI(8) => \<const0>\, DIADI(7) => \<const0>\, DIADI(6) => \<const0>\, DIADI(5) => \<const0>\, DIADI(4) => \<const0>\, DIADI(3) => \<const0>\, DIADI(2) => \<const0>\, DIADI(1) => \<const1>\, DIADI(0) => \<const1>\, DIBDI(31) => \<const1>\, DIBDI(30) => \<const1>\, DIBDI(29) => \<const1>\, DIBDI(28) => \<const1>\, DIBDI(27) => \<const1>\, DIBDI(26) => \<const1>\, DIBDI(25) => \<const1>\, DIBDI(24) => \<const1>\, DIBDI(23) => \<const1>\, DIBDI(22) => \<const1>\, DIBDI(21) => \<const1>\, DIBDI(20) => \<const1>\, DIBDI(19) => \<const1>\, DIBDI(18) => \<const1>\, DIBDI(17) => \<const1>\, DIBDI(16) => \<const1>\, DIBDI(15) => \<const1>\, DIBDI(14) => \<const1>\, DIBDI(13) => \<const1>\, DIBDI(12) => \<const1>\, DIBDI(11) => \<const1>\, DIBDI(10) => \<const1>\, DIBDI(9) => \<const1>\, DIBDI(8) => \<const1>\, DIBDI(7) => \<const1>\, DIBDI(6) => \<const1>\, DIBDI(5) => \<const1>\, DIBDI(4) => \<const1>\, DIBDI(3) => \<const1>\, DIBDI(2) => \<const1>\, DIBDI(1) => \<const1>\, DIBDI(0) => \<const1>\, DIPADIP(3) => \<const0>\, DIPADIP(2) => \<const0>\, DIPADIP(1) => \<const0>\, DIPADIP(0) => \<const0>\, DIPBDIP(3) => \<const1>\, DIPBDIP(2) => \<const1>\, DIPBDIP(1) => \<const1>\, DIPBDIP(0) => \<const1>\, DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOADO_UNCONNECTED\(31 downto 2), DOADO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(3 downto 2), DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOBDO_UNCONNECTED\(31 downto 2), DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(3 downto 2), DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => s_axis_phase_tvalid, ENBWREN => s_axis_phase_tvalid, INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_INJECTDBITERR_UNCONNECTED\, INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_INJECTSBITERR_UNCONNECTED\, RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => s_axis_phase_tvalid, REGCEB => s_axis_phase_tvalid, RSTRAMARSTRAM => \<const0>\, RSTRAMB => \<const0>\, RSTREGARSTREG => \<const0>\, RSTREGB => \<const0>\, SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_1_SBITERR_UNCONNECTED\, WEA(3) => \<const0>\, WEA(2) => \<const0>\, WEA(1) => \<const0>\, WEA(0) => \<const0>\, WEBWE(7) => \<const0>\, WEBWE(6) => \<const0>\, WEBWE(5) => \<const0>\, WEBWE(4) => \<const0>\, WEBWE(3) => \<const0>\, WEBWE(2) => \<const0>\, WEBWE(1) => \<const0>\, WEBWE(0) => \<const0>\ ); \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 1, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"400FFEAA55400FFEAA555003FFAA955003FFAA955003FFEAA55400FFEAA55400", INIT_01 => X"955400FFEAA55400FFEAA55400FFFAA955003FFAA955003FFAA955000FFEAA55", INIT_02 => X"FAA955003FFAAA55400FFEAA55400FFEAA554003FFAA955003FFAA955003FFAA", INIT_03 => X"03FFAA955003FFAA955003FFEAA55400FFEAA55400FFEAA554003FFAA955003F", INIT_04 => X"5400FFEAA555003FFAA955003FFAA955003FFEAA55400FFEAA55400FFEAA5550", INIT_05 => X"A955400FFEAA55400FFEAA554003FFAA955003FFAA955003FFAAA55400FFEAA5", INIT_06 => X"FFAA955003FFAA955000FFEAA55400FFEAA55400FFFAA955003FFAA955003FFA", INIT_07 => X"00FFEAA55400FFEAA955003FFAA955003FFAAA55400FFEAA55400FFEAA555003", INIT_08 => X"55003FFAA955003FFEAA55400FFEAA55400FFFAA955003FFAA955003FFEAA554", INIT_09 => X"AA55400FFEAA55400FFFAA955003FFAA955003FFEAA55400FFEAA55400FFFAA9", INIT_0A => X"FEAA555003FFAA955003FFAAA55400FFEAA55400FFEAA955003FFAA955003FFE", INIT_0B => X"03FFAA955003FFAAA55400FFEAA55400FFFAA955003FFAA955000FFEAA55400F", INIT_0C => X"5003FFAA955000FFEAA55400FFEAA955003FFAA955003FFEAA55400FFEAA5550", INIT_0D => X"955003FFAA955400FFEAA55400FFFAA955003FFAA955400FFEAA55400FFFAA95", INIT_0E => X"AA955003FFAA955000FFEAA55400FFEAA955003FFAA955400FFEAA55400FFFAA", INIT_0F => X"FEAA55400FFFAA955003FFAAA55400FFEAA555003FFAA955003FFEAA55400FFE", INIT_10 => X"3FFAA955000FFEAA554003FFAA955003FFEAA55400FFEAA955003FFAA955000F", INIT_11 => X"00FFEAA554003FFAA955000FFEAA55400FFFAA955003FFAAA55400FFEAA55500", INIT_12 => X"400FFFAA955003FFAAA55400FFEAA955003FFAAA55400FFEAA555003FFAA9554", INIT_13 => X"54003FFAA955000FFEAA554003FFAA955003FFEAA55400FFFAA955003FFEAA55", INIT_14 => X"55400FFFAA955003FFEAA55400FFFAA955003FFEAA554003FFAA955000FFEAA5", INIT_15 => X"955000FFEAA555003FFAA955400FFEAA955003FFAAA55400FFEAA955003FFEAA", INIT_16 => X"A554003FFAA955400FFEAA955003FFAAA55400FFFAA955003FFEAA554003FFAA", INIT_17 => X"A955003FFEAA554003FFAA955400FFEAA555003FFAAA55400FFFAA955000FFEA", INIT_18 => X"A955003FFEAA554003FFAA955400FFEAA955003FFEAA554003FFAA955400FFEA", INIT_19 => X"A555003FFAAA55400FFFAA955000FFEAA955003FFEAA554003FFAA955400FFEA", INIT_1A => X"955400FFEAA955000FFEAA555003FFAAA554003FFAA955400FFEAA955003FFEA", INIT_1B => X"55400FFFAA955400FFFAA955000FFEAA955003FFEAA554003FFAAA55400FFFAA", INIT_1C => X"5400FFFAA955400FFFAA955000FFEAA955000FFEAA555003FFEAA554003FFAAA", INIT_1D => X"000FFEAA955000FFEAA555003FFEAA555003FFEAA554003FFAAA554003FFAAA5", INIT_1E => X"0FFFAA955400FFFAA955400FFFAA955400FFFAA955400FFFAA955000FFEAA955", INIT_1F => X"FFAA955400FFFAAA554003FFAAA554003FFAAA554003FFAA955400FFFAA95540", INIT_20 => X"AA955000FFEAA955400FFFAA955400FFFAA955400FFFAA955400FFFAA955400F", INIT_21 => X"554003FFAAA554003FFAAA555003FFEAA555003FFEAA555000FFEAA955000FFE", INIT_22 => X"003FFAAA554003FFEAA555003FFEAA955000FFEAA955000FFFAA955400FFFAAA", INIT_23 => X"FEAA955400FFFAAA554003FFAAA555003FFEAA955000FFEAA955400FFFAA9554", INIT_24 => X"9554003FFAAA555003FFEAA955000FFFAA9554003FFAAA555003FFEAA955000F", INIT_25 => X"00FFFAAA555003FFEAA955000FFFAA9554003FFAAA555003FFEAA955000FFFAA", INIT_26 => X"EAA955000FFFAAA554003FFEAA555000FFFAA9554003FFAAA555000FFEAA9554", INIT_27 => X"5000FFFAAA554003FFEAA955000FFFAAA554003FFEAA955000FFFAAA554003FF", INIT_28 => X"FEAA955000FFFAAA555003FFEAA9554003FFAAA555000FFFAA9554003FFEAA55", INIT_29 => X"5000FFFAAA555000FFFAA9554003FFEAA955400FFFAAA555000FFFAA9554003F", INIT_2A => X"EAA9554003FFEAA955400FFFAAA555000FFFAAA555003FFEAA9554003FFEAA95", INIT_2B => X"003FFEAA9554003FFEAA955400FFFAAA555000FFFAAA555000FFFAAA554003FF", INIT_2C => X"A555000FFFAAA555000FFFAAA555000FFFAAA555003FFEAA9554003FFEAA9554", INIT_2D => X"FFAAA555000FFFAAA555000FFFAAA555000FFFAAA555000FFFAAA555000FFFAA", INIT_2E => X"003FFEAA9554003FFEAA9554003FFEAA9554000FFFAAA555000FFFAAA555000F", INIT_2F => X"554003FFEAA9554003FFEAAA555000FFFAAA555000FFFAAA555000FFFEAA9554", INIT_30 => X"AA555000FFFAAA5550003FFEAA9554003FFEAAA555000FFFAAA555000FFFAAA9", INIT_31 => X"EAAA555000FFFAAA5554003FFEAA9554000FFFAAA555000FFFEAA9554003FFEA", INIT_32 => X"FFAAA9554003FFEAAA555000FFFAAA9554003FFEAAA555000FFFAAA9554003FF", INIT_33 => X"FFFAAA5554003FFEAAA555000FFFEAA9554000FFFAAA5550003FFEAA9555000F", INIT_34 => X"FFFEAA9554000FFFAAA9554003FFFAAA5550003FFEAAA555000FFFEAA9554000", INIT_35 => X"FFFAAA9554003FFFAAA5554003FFFAAA5554003FFEAAA5550003FFEAA9555000", INIT_36 => X"FFAAA9554000FFFAAA9554000FFFAAA9554000FFFAAA9554000FFFAAA9554000", INIT_37 => X"EAAA5550003FFFAAA5554003FFFAAA5554000FFFAAA9554000FFFAAA9554000F", INIT_38 => X"A95550003FFEAAA5554003FFFAAA9554000FFFAAA9555000FFFEAA95550003FF", INIT_39 => X"550003FFFAAA9554000FFFEAA95550003FFEAAA5554003FFFAAA9554000FFFEA", INIT_3A => X"00FFFEAAA5550003FFFAAA9554000FFFEAAA5550003FFFAAA9554000FFFEAAA5", INIT_3B => X"FAAA95550003FFFAAA5554000FFFEAAA5554003FFFAAA95550003FFFAAA55540", INIT_3C => X"5550003FFFAAA9554000FFFEAAA5554000FFFEAAA5554000FFFEAA95550003FF", INIT_3D => X"3FFFAAA95550003FFFAAA95550003FFFAAA95550003FFFAAA95550003FFFAAA9", INIT_3E => X"A5554000FFFEAAA5554000FFFEAAA5554000FFFFAAA95550003FFFAAA9555000", INIT_3F => X"3FFFAAA95550003FFFEAAA5554000FFFEAAA55550003FFFAAA95550003FFFAAA", INIT_40 => X"5550003FFFAAA95554000FFFEAAA55550003FFFAAA95554000FFFEAAA5554000", INIT_41 => X"EAAA95550000FFFEAAA55550003FFFAAAA5554000FFFFAAA95550000FFFEAAA5", INIT_42 => X"03FFFEAAA55550003FFFAAAA55540003FFFAAAA5554000FFFFAAA95554000FFF", INIT_43 => X"540003FFFAAAA55540003FFFAAAA55550003FFFEAAA55550003FFFEAAA555500", INIT_44 => X"955540003FFFAAAA55550003FFFEAAA95550000FFFEAAA95554000FFFFAAA955", INIT_45 => X"AA955540003FFFEAAA95550000FFFFAAAA55540003FFFEAAA55550000FFFFAAA", INIT_46 => X"AAAA55550000FFFFAAA955540003FFFEAAA955540003FFFAAAA55550000FFFFA", INIT_47 => X"AAAA955540003FFFEAAA95554000FFFFAAAA55550000FFFFAAAA55550000FFFF", INIT_48 => X"AAA955540003FFFFAAAA55550000FFFFAAAA55550000FFFFAAAA55550000FFFF", INIT_49 => X"AA55550000FFFFEAAA955540003FFFFAAAA55550000FFFFAAAA955540003FFFE", INIT_4A => X"55540003FFFFAAAA555500003FFFEAAA955550000FFFFAAAA955540003FFFFAA", INIT_4B => X"0000FFFFAAAA955540000FFFFAAAA955540000FFFFAAAA955540000FFFFAAAA5", INIT_4C => X"FFFAAAA9555500003FFFEAAAA555500003FFFFAAAA555540003FFFFAAAA95554", INIT_4D => X"A9555500003FFFFAAAA555540000FFFFEAAA9555500003FFFFAAAA555540000F", INIT_4E => X"000FFFFEAAAA555540000FFFFEAAAA555540000FFFFEAAAA555500003FFFFAAA", INIT_4F => X"AAA9555500003FFFFEAAAA555540000FFFFEAAAA555540000FFFFEAAAA555540", INIT_50 => X"000FFFFEAAAA5555500003FFFFAAAA9555540000FFFFEAAAA5555500003FFFFA", INIT_51 => X"A5555400003FFFFAAAAA5555400003FFFFAAAA9555540000FFFFFAAAA9555500", INIT_52 => X"FFEAAAA9555500000FFFFFAAAA9555540000FFFFFAAAAA5555400003FFFFAAAA", INIT_53 => X"003FFFFEAAAA95555400003FFFFEAAAA9555500000FFFFFAAAAA5555400003FF", INIT_54 => X"5400000FFFFFAAAAA5555500000FFFFFAAAAA5555500000FFFFFAAAAA5555500", INIT_55 => X"5555400003FFFFEAAAAA5555500000FFFFFAAAAA95555400003FFFFEAAAA9555", INIT_56 => X"95555500000FFFFFEAAAA95555500000FFFFFEAAAA95555400000FFFFFAAAAA9", INIT_57 => X"955555000003FFFFEAAAAA55555400003FFFFFAAAAA95555400000FFFFFEAAAA", INIT_58 => X"5555400000FFFFFEAAAAA55555400000FFFFFEAAAAA55555400003FFFFFAAAAA", INIT_59 => X"5400000FFFFFEAAAAA955555000003FFFFFAAAAA955555400000FFFFFEAAAAA5", INIT_5A => X"003FFFFFAAAAAA555554000003FFFFFAAAAAA555554000003FFFFFAAAAA95555", INIT_5B => X"FEAAAAA9555554000003FFFFFEAAAAA955555000000FFFFFFAAAAA9555554000", INIT_5C => X"555554000003FFFFFEAAAAA9555554000000FFFFFFAAAAAA555555000000FFFF", INIT_5D => X"03FFFFFEAAAAAA5555550000003FFFFFEAAAAAA555555000000FFFFFFAAAAAA9", INIT_5E => X"A95555550000003FFFFFFAAAAAA9555555000000FFFFFFEAAAAAA55555500000", INIT_5F => X"FFFFFFFAAAAAA95555550000003FFFFFFAAAAAA95555550000003FFFFFFAAAAA", INIT_60 => X"5554000000FFFFFFFAAAAAAA55555540000003FFFFFFAAAAAAA5555554000000", INIT_61 => X"AAAAA55555550000000FFFFFFFAAAAAAA55555550000000FFFFFFEAAAAAA9555", INIT_62 => X"FFFFEAAAAAA955555550000000FFFFFFFAAAAAAA955555540000003FFFFFFFAA", INIT_63 => X"03FFFFFFFAAAAAAA9555555500000003FFFFFFFAAAAAAA955555540000000FFF", INIT_64 => X"0000FFFFFFFFAAAAAAA9555555540000000FFFFFFFEAAAAAAA95555555000000", INIT_65 => X"00003FFFFFFFEAAAAAAA95555555400000003FFFFFFFEAAAAAAA955555550000", INIT_66 => X"003FFFFFFFFAAAAAAAA55555555400000003FFFFFFFFAAAAAAAA555555554000", INIT_67 => X"FFFFFFEAAAAAAAA555555554000000003FFFFFFFFAAAAAAAA955555555000000", INIT_68 => X"AAAAAAAA555555555000000000FFFFFFFFFAAAAAAAAA555555555000000003FF", INIT_69 => X"55555550000000003FFFFFFFFFAAAAAAAAA5555555554000000003FFFFFFFFFA", INIT_6A => X"000FFFFFFFFFEAAAAAAAAA95555555554000000000FFFFFFFFFFAAAAAAAAA955", INIT_6B => X"AAAAA9555555555500000000003FFFFFFFFFEAAAAAAAAA955555555550000000", INIT_6C => X"000003FFFFFFFFFFEAAAAAAAAAA5555555555500000000003FFFFFFFFFFAAAAA", INIT_6D => X"A955555555555400000000003FFFFFFFFFFFAAAAAAAAAAA95555555555400000", INIT_6E => X"FFFFFFAAAAAAAAAAAA9555555555554000000000003FFFFFFFFFFFAAAAAAAAAA", INIT_6F => X"0000000FFFFFFFFFFFFFAAAAAAAAAAAAA5555555555554000000000000FFFFFF", INIT_70 => X"555540000000000000FFFFFFFFFFFFFEAAAAAAAAAAAAA5555555555555000000", INIT_71 => X"55555555555000000000000000FFFFFFFFFFFFFFAAAAAAAAAAAAAA9555555555", INIT_72 => X"555555555555554000000000000000FFFFFFFFFFFFFFFEAAAAAAAAAAAAAA9555", INIT_73 => X"555555555555500000000000000003FFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAA95", INIT_74 => X"555550000000000000000003FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAA95555", INIT_75 => X"00000000003FFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAA55555555555555", INIT_76 => X"FFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAA55555555555555555555540000000000", INIT_77 => X"A55555555555555555555555554000000000000000000000003FFFFFFFFFFFFF", INIT_78 => X"00000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_79 => X"AAAAAAAAAAAA5555555555555555555555555555555540000000000000000000", INIT_7A => X"00FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAA", INIT_7B => X"5555555555555555555555000000000000000000000000000000000000000000", INIT_7C => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555555555555555555555555555", INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_A => X"000000000", INIT_B => X"000000000", RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", READ_WIDTH_A => 2, READ_WIDTH_B => 2, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 2, WRITE_WIDTH_B => 0 ) port map ( ADDRARDADDR(15) => \<const1>\, ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0), ADDRARDADDR(0) => \<const0>\, ADDRBWRADDR(15) => \<const1>\, ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0), ADDRBWRADDR(0) => \<const0>\, CASCADEINA => \<const1>\, CASCADEINB => \<const0>\, CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => aclk, CLKBWRCLK => aclk, DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DBITERR_UNCONNECTED\, DIADI(31) => \<const0>\, DIADI(30) => \<const0>\, DIADI(29) => \<const0>\, DIADI(28) => \<const0>\, DIADI(27) => \<const0>\, DIADI(26) => \<const0>\, DIADI(25) => \<const0>\, DIADI(24) => \<const0>\, DIADI(23) => \<const0>\, DIADI(22) => \<const0>\, DIADI(21) => \<const0>\, DIADI(20) => \<const0>\, DIADI(19) => \<const0>\, DIADI(18) => \<const0>\, DIADI(17) => \<const0>\, DIADI(16) => \<const0>\, DIADI(15) => \<const0>\, DIADI(14) => \<const0>\, DIADI(13) => \<const0>\, DIADI(12) => \<const0>\, DIADI(11) => \<const0>\, DIADI(10) => \<const0>\, DIADI(9) => \<const0>\, DIADI(8) => \<const0>\, DIADI(7) => \<const0>\, DIADI(6) => \<const0>\, DIADI(5) => \<const0>\, DIADI(4) => \<const0>\, DIADI(3) => \<const0>\, DIADI(2) => \<const0>\, DIADI(1) => \<const1>\, DIADI(0) => \<const1>\, DIBDI(31) => \<const1>\, DIBDI(30) => \<const1>\, DIBDI(29) => \<const1>\, DIBDI(28) => \<const1>\, DIBDI(27) => \<const1>\, DIBDI(26) => \<const1>\, DIBDI(25) => \<const1>\, DIBDI(24) => \<const1>\, DIBDI(23) => \<const1>\, DIBDI(22) => \<const1>\, DIBDI(21) => \<const1>\, DIBDI(20) => \<const1>\, DIBDI(19) => \<const1>\, DIBDI(18) => \<const1>\, DIBDI(17) => \<const1>\, DIBDI(16) => \<const1>\, DIBDI(15) => \<const1>\, DIBDI(14) => \<const1>\, DIBDI(13) => \<const1>\, DIBDI(12) => \<const1>\, DIBDI(11) => \<const1>\, DIBDI(10) => \<const1>\, DIBDI(9) => \<const1>\, DIBDI(8) => \<const1>\, DIBDI(7) => \<const1>\, DIBDI(6) => \<const1>\, DIBDI(5) => \<const1>\, DIBDI(4) => \<const1>\, DIBDI(3) => \<const1>\, DIBDI(2) => \<const1>\, DIBDI(1) => \<const1>\, DIBDI(0) => \<const1>\, DIPADIP(3) => \<const0>\, DIPADIP(2) => \<const0>\, DIPADIP(1) => \<const0>\, DIPADIP(0) => \<const0>\, DIPBDIP(3) => \<const1>\, DIPBDIP(2) => \<const1>\, DIPBDIP(1) => \<const1>\, DIPBDIP(0) => \<const1>\, DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOADO_UNCONNECTED\(31 downto 2), DOADO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(5 downto 4), DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOBDO_UNCONNECTED\(31 downto 2), DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(5 downto 4), DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => s_axis_phase_tvalid, ENBWREN => s_axis_phase_tvalid, INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_INJECTDBITERR_UNCONNECTED\, INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_INJECTSBITERR_UNCONNECTED\, RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => s_axis_phase_tvalid, REGCEB => s_axis_phase_tvalid, RSTRAMARSTRAM => \<const0>\, RSTRAMB => \<const0>\, RSTREGARSTREG => \<const0>\, RSTREGB => \<const0>\, SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_2_SBITERR_UNCONNECTED\, WEA(3) => \<const0>\, WEA(2) => \<const0>\, WEA(1) => \<const0>\, WEA(0) => \<const0>\, WEBWE(7) => \<const0>\, WEBWE(6) => \<const0>\, WEBWE(5) => \<const0>\, WEBWE(4) => \<const0>\, WEBWE(3) => \<const0>\, WEBWE(2) => \<const0>\, WEBWE(1) => \<const0>\, WEBWE(0) => \<const0>\ ); \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 1, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"AAA555555555500000000003FFFFFFFFFEAAAAAAAAA955555555550000000000", INIT_01 => X"000000FFFFFFFFFFAAAAAAAAAA555555555540000000003FFFFFFFFFFAAAAAAA", INIT_02 => X"AAAAAAAA955555555550000000000FFFFFFFFFFEAAAAAAAAA955555555540000", INIT_03 => X"540000000003FFFFFFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFEA", INIT_04 => X"FFFFAAAAAAAAAA955555555540000000003FFFFFFFFFFAAAAAAAAAA555555555", INIT_05 => X"55555550000000000FFFFFFFFFFEAAAAAAAAA955555555540000000000FFFFFF", INIT_06 => X"FFFFFFFFFEAAAAAAAAAA55555555550000000000FFFFFFFFFFEAAAAAAAAA9555", INIT_07 => X"AA555555555500000000003FFFFFFFFFEAAAAAAAAAA555555555500000000003", INIT_08 => X"00003FFFFFFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFEAAAAAAAA", INIT_09 => X"AAAAAAA555555555500000000003FFFFFFFFFEAAAAAAAAAA5555555555000000", INIT_0A => X"0000000003FFFFFFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFEAAA", INIT_0B => X"FEAAAAAAAAA955555555550000000000FFFFFFFFFFEAAAAAAAAAA55555555550", INIT_0C => X"55540000000000FFFFFFFFFFAAAAAAAAAA955555555540000000000FFFFFFFFF", INIT_0D => X"FFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFFAAAAAAAAAA5555555", INIT_0E => X"555555540000000000FFFFFFFFFFAAAAAAAAAA955555555550000000000FFFFF", INIT_0F => X"FFFFFFFFFAAAAAAAAAA9555555555500000000003FFFFFFFFFEAAAAAAAAAA555", INIT_10 => X"9555555555500000000003FFFFFFFFFEAAAAAAAAAA555555555540000000000F", INIT_11 => X"00FFFFFFFFFFEAAAAAAAAAA555555555500000000003FFFFFFFFFFAAAAAAAAAA", INIT_12 => X"AAA555555555540000000000FFFFFFFFFFEAAAAAAAAAA5555555555400000000", INIT_13 => X"00003FFFFFFFFFFAAAAAAAAAA955555555540000000000FFFFFFFFFFEAAAAAAA", INIT_14 => X"AAAAA555555555540000000000FFFFFFFFFFEAAAAAAAAAA95555555555000000", INIT_15 => X"000000FFFFFFFFFFEAAAAAAAAAA555555555540000000000FFFFFFFFFFEAAAAA", INIT_16 => X"AAAAAA9555555555500000000003FFFFFFFFFFAAAAAAAAAA9555555555540000", INIT_17 => X"0000003FFFFFFFFFFEAAAAAAAAAA555555555540000000000FFFFFFFFFFFAAAA", INIT_18 => X"AAAAAA9555555555540000000000FFFFFFFFFFEAAAAAAAAAA955555555550000", INIT_19 => X"0000003FFFFFFFFFFAAAAAAAAAAA5555555555400000000003FFFFFFFFFFAAAA", INIT_1A => X"AAAAAA5555555555500000000003FFFFFFFFFFEAAAAAAAAAA555555555540000", INIT_1B => X"00000FFFFFFFFFFFAAAAAAAAAAA5555555555400000000003FFFFFFFFFFAAAAA", INIT_1C => X"AAAA5555555555500000000000FFFFFFFFFFFAAAAAAAAAA95555555555400000", INIT_1D => X"000FFFFFFFFFFFAAAAAAAAAA95555555555400000000003FFFFFFFFFFEAAAAAA", INIT_1E => X"A5555555555500000000000FFFFFFFFFFFAAAAAAAAAAA5555555555500000000", INIT_1F => X"FFFFFFFFFFAAAAAAAAAAA95555555555400000000003FFFFFFFFFFAAAAAAAAAA", INIT_20 => X"5555555500000000000FFFFFFFFFFFAAAAAAAAAAA5555555555500000000000F", INIT_21 => X"FFFFFEAAAAAAAAAA95555555555400000000003FFFFFFFFFFFAAAAAAAAAAA555", INIT_22 => X"55400000000003FFFFFFFFFFEAAAAAAAAAAA5555555555500000000000FFFFFF", INIT_23 => X"AAAAAAAAAA55555555555400000000003FFFFFFFFFFFAAAAAAAAAAA555555555", INIT_24 => X"0000003FFFFFFFFFFEAAAAAAAAAAA55555555555400000000003FFFFFFFFFFFA", INIT_25 => X"AA55555555555400000000000FFFFFFFFFFFEAAAAAAAAAA95555555555500000", INIT_26 => X"FFFFFFFFFAAAAAAAAAAA955555555555000000000003FFFFFFFFFFFAAAAAAAAA", INIT_27 => X"5555000000000003FFFFFFFFFFFAAAAAAAAAAA955555555555000000000003FF", INIT_28 => X"AAAAAAAAAA555555555554000000000003FFFFFFFFFFFAAAAAAAAAAA95555555", INIT_29 => X"0000FFFFFFFFFFFFAAAAAAAAAAA955555555555000000000000FFFFFFFFFFFEA", INIT_2A => X"555555555400000000000FFFFFFFFFFFFAAAAAAAAAAA95555555555540000000", INIT_2B => X"FFEAAAAAAAAAAA955555555555000000000000FFFFFFFFFFFFAAAAAAAAAAA955", INIT_2C => X"0000000FFFFFFFFFFFFAAAAAAAAAAAA555555555554000000000003FFFFFFFFF", INIT_2D => X"55555555555000000000000FFFFFFFFFFFFAAAAAAAAAAAA55555555555500000", INIT_2E => X"FFEAAAAAAAAAAA9555555555554000000000000FFFFFFFFFFFFAAAAAAAAAAAA5", INIT_2F => X"000003FFFFFFFFFFFEAAAAAAAAAAAA555555555555000000000000FFFFFFFFFF", INIT_30 => X"555555550000000000003FFFFFFFFFFFEAAAAAAAAAAAA5555555555550000000", INIT_31 => X"AAAAAAAAAA5555555555554000000000000FFFFFFFFFFFFAAAAAAAAAAAA95555", INIT_32 => X"FFFFFFFFFFFEAAAAAAAAAAAA5555555555554000000000000FFFFFFFFFFFFEAA", INIT_33 => X"0000000000003FFFFFFFFFFFFAAAAAAAAAAAAA5555555555554000000000000F", INIT_34 => X"55555555555550000000000003FFFFFFFFFFFFEAAAAAAAAAAAA5555555555555", INIT_35 => X"AAAAAAAAAAAA955555555555540000000000003FFFFFFFFFFFFEAAAAAAAAAAAA", INIT_36 => X"FFFFFFFFFFFFAAAAAAAAAAAAA55555555555550000000000000FFFFFFFFFFFFF", INIT_37 => X"00000000003FFFFFFFFFFFFEAAAAAAAAAAAAA55555555555550000000000000F", INIT_38 => X"5555555540000000000003FFFFFFFFFFFFFAAAAAAAAAAAAA5555555555555400", INIT_39 => X"AAAAA9555555555555500000000000003FFFFFFFFFFFFEAAAAAAAAAAAAA55555", INIT_3A => X"FFAAAAAAAAAAAAA9555555555555500000000000003FFFFFFFFFFFFFAAAAAAAA", INIT_3B => X"FFFFFFFFFFFEAAAAAAAAAAAAA5555555555555400000000000003FFFFFFFFFFF", INIT_3C => X"0000003FFFFFFFFFFFFFAAAAAAAAAAAAAA5555555555555500000000000003FF", INIT_3D => X"400000000000003FFFFFFFFFFFFFEAAAAAAAAAAAAA9555555555555540000000", INIT_3E => X"5555555500000000000000FFFFFFFFFFFFFFAAAAAAAAAAAAAA95555555555555", INIT_3F => X"95555555555555400000000000000FFFFFFFFFFFFFFEAAAAAAAAAAAAA9555555", INIT_40 => X"AAAAAA955555555555555000000000000003FFFFFFFFFFFFFFAAAAAAAAAAAAAA", INIT_41 => X"AAAAAAAAAAAA55555555555555400000000000000FFFFFFFFFFFFFFFAAAAAAAA", INIT_42 => X"FEAAAAAAAAAAAAAA955555555555555400000000000000FFFFFFFFFFFFFFFAAA", INIT_43 => X"FFFFFEAAAAAAAAAAAAAA9555555555555554000000000000003FFFFFFFFFFFFF", INIT_44 => X"FFFFFFFFEAAAAAAAAAAAAAA9555555555555555000000000000000FFFFFFFFFF", INIT_45 => X"FFFFFFFFFFEAAAAAAAAAAAAAAA5555555555555554000000000000000FFFFFFF", INIT_46 => X"FFFFFFFFFFFFAAAAAAAAAAAAAAA95555555555555554000000000000000FFFFF", INIT_47 => X"FFFFFFFFFFFFEAAAAAAAAAAAAAAA55555555555555550000000000000000FFFF", INIT_48 => X"FFFFFFFFFFFEAAAAAAAAAAAAAAAA55555555555555550000000000000000FFFF", INIT_49 => X"FFFFFFFFFFAAAAAAAAAAAAAAAA9555555555555555500000000000000003FFFF", INIT_4A => X"FFFFFFFEAAAAAAAAAAAAAAAA9555555555555555500000000000000003FFFFFF", INIT_4B => X"FFFFAAAAAAAAAAAAAAAAA5555555555555555500000000000000000FFFFFFFFF", INIT_4C => X"AAAAAAAAAAAAAAAA95555555555555555400000000000000003FFFFFFFFFFFFF", INIT_4D => X"AAAAAAAAAA955555555555555555000000000000000003FFFFFFFFFFFFFFFFFA", INIT_4E => X"AAA555555555555555555000000000000000000FFFFFFFFFFFFFFFFFEAAAAAAA", INIT_4F => X"5555555555554000000000000000000FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAA", INIT_50 => X"5550000000000000000003FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAA955555", INIT_51 => X"00000000003FFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAA5555555555555555", INIT_52 => X"FFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAA5555555555555555555400000000", INIT_53 => X"FFEAAAAAAAAAAAAAAAAAAA9555555555555555555500000000000000000003FF", INIT_54 => X"AAAAAAA5555555555555555555500000000000000000000FFFFFFFFFFFFFFFFF", INIT_55 => X"555555555400000000000000000000FFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAA", INIT_56 => X"00000000000FFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAA55555555555", INIT_57 => X"FFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAA95555555555555555555550000000000", INIT_58 => X"AAAAAAAAAA55555555555555555555550000000000000000000003FFFFFFFFFF", INIT_59 => X"555555500000000000000000000003FFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAA", INIT_5A => X"003FFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAA9555555555555555", INIT_5B => X"AAAAAAAAAAAAAAAAAAA955555555555555555555555000000000000000000000", INIT_5C => X"555555555554000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFAAAA", INIT_5D => X"03FFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAA5555555555555", INIT_5E => X"AAAAAAAAAAAAAA95555555555555555555555555000000000000000000000000", INIT_5F => X"000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAA", INIT_60 => X"FFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAA955555555555555555555555555", INIT_61 => X"55555555555555555550000000000000000000000000000FFFFFFFFFFFFFFFFF", INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAA9555555555", INIT_63 => X"A955555555555555555555555555555400000000000000000000000000000FFF", INIT_64 => X"0000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_65 => X"AAAA955555555555555555555555555555554000000000000000000000000000", INIT_66 => X"003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_67 => X"5555555555555555555555555555555540000000000000000000000000000000", INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955", INIT_69 => X"555555555555555540000000000000000000000000000000000003FFFFFFFFFF", INIT_6A => X"FFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555555555555555555", INIT_6B => X"000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_6C => X"AAAAA95555555555555555555555555555555555555555554000000000000000", INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_6E => X"0000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFF", INIT_6F => X"AAAAAAA555555555555555555555555555555555555555555555555555000000", INIT_70 => X"FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_71 => X"00000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_72 => X"5555555555555555555555555555550000000000000000000000000000000000", INIT_73 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555555", INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_75 => X"00000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_77 => X"5555555555555555555555555555555555555555555555555540000000000000", INIT_78 => X"AAAAAAAAAA955555555555555555555555555555555555555555555555555555", INIT_79 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_7A => X"FFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_A => X"000000000", INIT_B => X"000000000", RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", READ_WIDTH_A => 2, READ_WIDTH_B => 2, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 2, WRITE_WIDTH_B => 0 ) port map ( ADDRARDADDR(15) => \<const1>\, ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0), ADDRARDADDR(0) => \<const0>\, ADDRBWRADDR(15) => \<const1>\, ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0), ADDRBWRADDR(0) => \<const0>\, CASCADEINA => \<const1>\, CASCADEINB => \<const0>\, CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => aclk, CLKBWRCLK => aclk, DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DBITERR_UNCONNECTED\, DIADI(31) => \<const0>\, DIADI(30) => \<const0>\, DIADI(29) => \<const0>\, DIADI(28) => \<const0>\, DIADI(27) => \<const0>\, DIADI(26) => \<const0>\, DIADI(25) => \<const0>\, DIADI(24) => \<const0>\, DIADI(23) => \<const0>\, DIADI(22) => \<const0>\, DIADI(21) => \<const0>\, DIADI(20) => \<const0>\, DIADI(19) => \<const0>\, DIADI(18) => \<const0>\, DIADI(17) => \<const0>\, DIADI(16) => \<const0>\, DIADI(15) => \<const0>\, DIADI(14) => \<const0>\, DIADI(13) => \<const0>\, DIADI(12) => \<const0>\, DIADI(11) => \<const0>\, DIADI(10) => \<const0>\, DIADI(9) => \<const0>\, DIADI(8) => \<const0>\, DIADI(7) => \<const0>\, DIADI(6) => \<const0>\, DIADI(5) => \<const0>\, DIADI(4) => \<const0>\, DIADI(3) => \<const0>\, DIADI(2) => \<const0>\, DIADI(1) => \<const1>\, DIADI(0) => \<const1>\, DIBDI(31) => \<const1>\, DIBDI(30) => \<const1>\, DIBDI(29) => \<const1>\, DIBDI(28) => \<const1>\, DIBDI(27) => \<const1>\, DIBDI(26) => \<const1>\, DIBDI(25) => \<const1>\, DIBDI(24) => \<const1>\, DIBDI(23) => \<const1>\, DIBDI(22) => \<const1>\, DIBDI(21) => \<const1>\, DIBDI(20) => \<const1>\, DIBDI(19) => \<const1>\, DIBDI(18) => \<const1>\, DIBDI(17) => \<const1>\, DIBDI(16) => \<const1>\, DIBDI(15) => \<const1>\, DIBDI(14) => \<const1>\, DIBDI(13) => \<const1>\, DIBDI(12) => \<const1>\, DIBDI(11) => \<const1>\, DIBDI(10) => \<const1>\, DIBDI(9) => \<const1>\, DIBDI(8) => \<const1>\, DIBDI(7) => \<const1>\, DIBDI(6) => \<const1>\, DIBDI(5) => \<const1>\, DIBDI(4) => \<const1>\, DIBDI(3) => \<const1>\, DIBDI(2) => \<const1>\, DIBDI(1) => \<const1>\, DIBDI(0) => \<const1>\, DIPADIP(3) => \<const0>\, DIPADIP(2) => \<const0>\, DIPADIP(1) => \<const0>\, DIPADIP(0) => \<const0>\, DIPBDIP(3) => \<const1>\, DIPBDIP(2) => \<const1>\, DIPBDIP(1) => \<const1>\, DIPBDIP(0) => \<const1>\, DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOADO_UNCONNECTED\(31 downto 2), DOADO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(7 downto 6), DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOBDO_UNCONNECTED\(31 downto 2), DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(7 downto 6), DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => s_axis_phase_tvalid, ENBWREN => s_axis_phase_tvalid, INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_INJECTDBITERR_UNCONNECTED\, INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_INJECTSBITERR_UNCONNECTED\, RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => s_axis_phase_tvalid, REGCEB => s_axis_phase_tvalid, RSTRAMARSTRAM => \<const0>\, RSTRAMB => \<const0>\, RSTREGARSTREG => \<const0>\, RSTREGB => \<const0>\, SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_3_SBITERR_UNCONNECTED\, WEA(3) => \<const0>\, WEA(2) => \<const0>\, WEA(1) => \<const0>\, WEA(0) => \<const0>\, WEBWE(7) => \<const0>\, WEBWE(6) => \<const0>\, WEBWE(5) => \<const0>\, WEBWE(4) => \<const0>\, WEBWE(3) => \<const0>\, WEBWE(2) => \<const0>\, WEBWE(1) => \<const0>\, WEBWE(0) => \<const0>\ ); \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 1, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"5555555555555555555555540000000000000000000000000000000000000000", INIT_01 => X"FFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955555555555555555", INIT_02 => X"00000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_03 => X"AAAAAAAAAAA95555555555555555555555555555555555555555400000000000", INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_05 => X"5555555555555555500000000000000000000000000000000000000000FFFFFF", INIT_06 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555555555", INIT_07 => X"00000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE", INIT_08 => X"AAAA955555555555555555555555555555555555555554000000000000000000", INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_0A => X"555555555400000000000000000000000000000000000000003FFFFFFFFFFFFF", INIT_0B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555555555555555", INIT_0C => X"00000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAA", INIT_0D => X"5555555555555555555555555555555555554000000000000000000000000000", INIT_0E => X"FFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555", INIT_0F => X"00000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFF", INIT_10 => X"AAAAAAAAAAAAAAAAAAAAA9555555555555555555555555555555555555555550", INIT_11 => X"00FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAA", INIT_12 => X"5555555555555555555555550000000000000000000000000000000000000000", INIT_13 => X"FFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555", INIT_14 => X"00000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_15 => X"AAAAAA5555555555555555555555555555555555555555550000000000000000", INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_17 => X"5555554000000000000000000000000000000000000000000FFFFFFFFFFFFFFF", INIT_18 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555555555555555555555", INIT_19 => X"0000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAA", INIT_1A => X"5555555555555555555555555554000000000000000000000000000000000000", INIT_1B => X"FFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA9555555555555555", INIT_1C => X"00000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_1D => X"AAA5555555555555555555555555555555555555555555400000000000000000", INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_1F => X"00000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFF", INIT_20 => X"AAAAAAAAAAAAAAAAAAA555555555555555555555555555555555555555555550", INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_22 => X"5555555555555400000000000000000000000000000000000000000000FFFFFF", INIT_23 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555", INIT_24 => X"0000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAA", INIT_25 => X"5555555555555555555555555000000000000000000000000000000000000000", INIT_26 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955555555555555555555", INIT_27 => X"0000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAA", INIT_28 => X"5555555555555555555555555555555554000000000000000000000000000000", INIT_29 => X"FFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555555555", INIT_2A => X"000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_2B => X"5555555555555555555555555555555555555500000000000000000000000000", INIT_2C => X"FFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA9555555555", INIT_2D => X"00000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_2E => X"5555555555555555555555555555555555555550000000000000000000000000", INIT_2F => X"FFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555555", INIT_30 => X"000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_31 => X"5555555555555555555555555555555555500000000000000000000000000000", INIT_32 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555", INIT_33 => X"0000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA", INIT_34 => X"5555555555555555555555555400000000000000000000000000000000000000", INIT_35 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555", INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAA", INIT_37 => X"555555555540000000000000000000000000000000000000000000000000000F", INIT_38 => X"AAAAAAAAAAAAAAAAAAAAA9555555555555555555555555555555555555555555", INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_3A => X"0000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFF", INIT_3B => X"5555555555555555555555555555555555555555555555555555400000000000", INIT_3C => X"FFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955", INIT_3D => X"000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_3E => X"5555555555555555555555000000000000000000000000000000000000000000", INIT_3F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555555555555555555", INIT_40 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_41 => X"00000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFF", INIT_42 => X"5555555555555555555555555555555555555555555555000000000000000000", INIT_43 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555", INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAA", INIT_45 => X"000000000000000000000000000000000000000000000000000000000FFFFFFF", INIT_46 => X"5555555555555555555555555555555555555555555555555555555555500000", INIT_47 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555", INIT_48 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAA", INIT_49 => X"000000000000000000000000000000000000000000000000000000000003FFFF", INIT_4A => X"5555555555555555555555555555555555555555555555555555555554000000", INIT_4B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555", INIT_4C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAA", INIT_4D => X"0000000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFF", INIT_4E => X"5555555555555555555555555555555555555550000000000000000000000000", INIT_4F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555555555555555555555555555555", INIT_50 => X"FFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_51 => X"00000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_53 => X"5555555555555555555555555555555555555555555555555555555555555400", INIT_54 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555", INIT_55 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_56 => X"00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"5555555555555555555555555555555555555555555555555555540000000000", INIT_59 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555555", INIT_5A => X"FFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_5C => X"000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_5D => X"5400000000000000000000000000000000000000000000000000000000000000", INIT_5E => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_5F => X"AAAAAAAAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555555555", INIT_60 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_61 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAA", INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000FFF", INIT_64 => X"5555000000000000000000000000000000000000000000000000000000000000", INIT_65 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_66 => X"AA95555555555555555555555555555555555555555555555555555555555555", INIT_67 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_68 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAA", INIT_6A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_6B => X"000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_6E => X"5555555555555555555555555555555555555555554000000000000000000000", INIT_6F => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_70 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_71 => X"AAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555555555555555555555", INIT_72 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_73 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_74 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_75 => X"FFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_A => X"000000000", INIT_B => X"000000000", RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", READ_WIDTH_A => 2, READ_WIDTH_B => 2, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 2, WRITE_WIDTH_B => 0 ) port map ( ADDRARDADDR(15) => \<const1>\, ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0), ADDRARDADDR(0) => \<const0>\, ADDRBWRADDR(15) => \<const1>\, ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0), ADDRBWRADDR(0) => \<const0>\, CASCADEINA => \<const1>\, CASCADEINB => \<const0>\, CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => aclk, CLKBWRCLK => aclk, DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DBITERR_UNCONNECTED\, DIADI(31) => \<const0>\, DIADI(30) => \<const0>\, DIADI(29) => \<const0>\, DIADI(28) => \<const0>\, DIADI(27) => \<const0>\, DIADI(26) => \<const0>\, DIADI(25) => \<const0>\, DIADI(24) => \<const0>\, DIADI(23) => \<const0>\, DIADI(22) => \<const0>\, DIADI(21) => \<const0>\, DIADI(20) => \<const0>\, DIADI(19) => \<const0>\, DIADI(18) => \<const0>\, DIADI(17) => \<const0>\, DIADI(16) => \<const0>\, DIADI(15) => \<const0>\, DIADI(14) => \<const0>\, DIADI(13) => \<const0>\, DIADI(12) => \<const0>\, DIADI(11) => \<const0>\, DIADI(10) => \<const0>\, DIADI(9) => \<const0>\, DIADI(8) => \<const0>\, DIADI(7) => \<const0>\, DIADI(6) => \<const0>\, DIADI(5) => \<const0>\, DIADI(4) => \<const0>\, DIADI(3) => \<const0>\, DIADI(2) => \<const0>\, DIADI(1) => \<const1>\, DIADI(0) => \<const1>\, DIBDI(31) => \<const1>\, DIBDI(30) => \<const1>\, DIBDI(29) => \<const1>\, DIBDI(28) => \<const1>\, DIBDI(27) => \<const1>\, DIBDI(26) => \<const1>\, DIBDI(25) => \<const1>\, DIBDI(24) => \<const1>\, DIBDI(23) => \<const1>\, DIBDI(22) => \<const1>\, DIBDI(21) => \<const1>\, DIBDI(20) => \<const1>\, DIBDI(19) => \<const1>\, DIBDI(18) => \<const1>\, DIBDI(17) => \<const1>\, DIBDI(16) => \<const1>\, DIBDI(15) => \<const1>\, DIBDI(14) => \<const1>\, DIBDI(13) => \<const1>\, DIBDI(12) => \<const1>\, DIBDI(11) => \<const1>\, DIBDI(10) => \<const1>\, DIBDI(9) => \<const1>\, DIBDI(8) => \<const1>\, DIBDI(7) => \<const1>\, DIBDI(6) => \<const1>\, DIBDI(5) => \<const1>\, DIBDI(4) => \<const1>\, DIBDI(3) => \<const1>\, DIBDI(2) => \<const1>\, DIBDI(1) => \<const1>\, DIBDI(0) => \<const1>\, DIPADIP(3) => \<const0>\, DIPADIP(2) => \<const0>\, DIPADIP(1) => \<const0>\, DIPADIP(0) => \<const0>\, DIPBDIP(3) => \<const1>\, DIPBDIP(2) => \<const1>\, DIPBDIP(1) => \<const1>\, DIPBDIP(0) => \<const1>\, DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOADO_UNCONNECTED\(31 downto 2), DOADO(1 downto 0) => p_0_in(1 downto 0), DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOBDO_UNCONNECTED\(31 downto 2), DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(9 downto 8), DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => s_axis_phase_tvalid, ENBWREN => s_axis_phase_tvalid, INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_INJECTDBITERR_UNCONNECTED\, INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_INJECTSBITERR_UNCONNECTED\, RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => s_axis_phase_tvalid, REGCEB => s_axis_phase_tvalid, RSTRAMARSTRAM => \<const0>\, RSTRAMB => \<const0>\, RSTREGARSTREG => \<const0>\, RSTREGB => \<const0>\, SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_4_SBITERR_UNCONNECTED\, WEA(3) => \<const0>\, WEA(2) => \<const0>\, WEA(1) => \<const0>\, WEA(0) => \<const0>\, WEBWE(7) => \<const0>\, WEBWE(6) => \<const0>\, WEBWE(5) => \<const0>\, WEBWE(4) => \<const0>\, WEBWE(3) => \<const0>\, WEBWE(2) => \<const0>\, WEBWE(1) => \<const0>\, WEBWE(0) => \<const0>\ ); \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 1, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"5555555555555555555555555555500000000000000000000000000000000000", INIT_03 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_04 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_05 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555555", INIT_06 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_0A => X"000000000000000000000000000000000000000000000000003FFFFFFFFFFFFF", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"5555555555555500000000000000000000000000000000000000000000000000", INIT_0D => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_0E => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_0F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA955555555555555555555555", INIT_10 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_11 => X"FFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_13 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_14 => X"00000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"5555555555555555555555555555555555555555555555555000000000000000", INIT_18 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_19 => X"AAAAAA9555555555555555555555555555555555555555555555555555555555", INIT_1A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_1B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_1F => X"00000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFF", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"5555555555555555555555555555555555555555555555555555555555000000", INIT_23 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_24 => X"AAAAAA9555555555555555555555555555555555555555555555555555555555", INIT_25 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_26 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_27 => X"FFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_2A => X"000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"5555555555555555555555500000000000000000000000000000000000000000", INIT_2E => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_2F => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_30 => X"AAAAAAAAAAAAAAAAAAAA95555555555555555555555555555555555555555555", INIT_31 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_32 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_33 => X"FFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_37 => X"000000000000000000000000000000000000000000000000000000000000000F", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"5555555555555555555555555555555555555555554000000000000000000000", INIT_3B => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_3C => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_3D => X"AAAAAAAAAAAAAA95555555555555555555555555555555555555555555555555", INIT_3E => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_3F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_40 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_41 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAA", INIT_42 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_43 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_44 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_45 => X"000000000000000000000000000000000000000000000000000000000FFFFFFF", INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_49 => X"5555555555555555555555555555555555555555555555555555555555540000", INIT_4A => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_4B => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_4C => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_4D => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA9555555555555555555", INIT_4E => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_4F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_50 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_51 => X"FFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_52 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_53 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_54 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_55 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_56 => X"00000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_5C => X"5555555555555555555555555555555555550000000000000000000000000000", INIT_5D => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_5E => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_5F => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_60 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_61 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_62 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_63 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA555", INIT_64 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_65 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_66 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_67 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_68 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_69 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_6A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_6B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_6C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_70 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_71 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_73 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_75 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_A => X"000000000", INIT_B => X"000000000", RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", READ_WIDTH_A => 2, READ_WIDTH_B => 2, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 2, WRITE_WIDTH_B => 0 ) port map ( ADDRARDADDR(15) => \<const1>\, ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0), ADDRARDADDR(0) => \<const0>\, ADDRBWRADDR(15) => \<const1>\, ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0), ADDRBWRADDR(0) => \<const0>\, CASCADEINA => \<const1>\, CASCADEINB => \<const0>\, CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => aclk, CLKBWRCLK => aclk, DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DBITERR_UNCONNECTED\, DIADI(31) => \<const0>\, DIADI(30) => \<const0>\, DIADI(29) => \<const0>\, DIADI(28) => \<const0>\, DIADI(27) => \<const0>\, DIADI(26) => \<const0>\, DIADI(25) => \<const0>\, DIADI(24) => \<const0>\, DIADI(23) => \<const0>\, DIADI(22) => \<const0>\, DIADI(21) => \<const0>\, DIADI(20) => \<const0>\, DIADI(19) => \<const0>\, DIADI(18) => \<const0>\, DIADI(17) => \<const0>\, DIADI(16) => \<const0>\, DIADI(15) => \<const0>\, DIADI(14) => \<const0>\, DIADI(13) => \<const0>\, DIADI(12) => \<const0>\, DIADI(11) => \<const0>\, DIADI(10) => \<const0>\, DIADI(9) => \<const0>\, DIADI(8) => \<const0>\, DIADI(7) => \<const0>\, DIADI(6) => \<const0>\, DIADI(5) => \<const0>\, DIADI(4) => \<const0>\, DIADI(3) => \<const0>\, DIADI(2) => \<const0>\, DIADI(1) => \<const1>\, DIADI(0) => \<const1>\, DIBDI(31) => \<const1>\, DIBDI(30) => \<const1>\, DIBDI(29) => \<const1>\, DIBDI(28) => \<const1>\, DIBDI(27) => \<const1>\, DIBDI(26) => \<const1>\, DIBDI(25) => \<const1>\, DIBDI(24) => \<const1>\, DIBDI(23) => \<const1>\, DIBDI(22) => \<const1>\, DIBDI(21) => \<const1>\, DIBDI(20) => \<const1>\, DIBDI(19) => \<const1>\, DIBDI(18) => \<const1>\, DIBDI(17) => \<const1>\, DIBDI(16) => \<const1>\, DIBDI(15) => \<const1>\, DIBDI(14) => \<const1>\, DIBDI(13) => \<const1>\, DIBDI(12) => \<const1>\, DIBDI(11) => \<const1>\, DIBDI(10) => \<const1>\, DIBDI(9) => \<const1>\, DIBDI(8) => \<const1>\, DIBDI(7) => \<const1>\, DIBDI(6) => \<const1>\, DIBDI(5) => \<const1>\, DIBDI(4) => \<const1>\, DIBDI(3) => \<const1>\, DIBDI(2) => \<const1>\, DIBDI(1) => \<const1>\, DIBDI(0) => \<const1>\, DIPADIP(3) => \<const0>\, DIPADIP(2) => \<const0>\, DIPADIP(1) => \<const0>\, DIPADIP(0) => \<const0>\, DIPBDIP(3) => \<const1>\, DIPBDIP(2) => \<const1>\, DIPBDIP(1) => \<const1>\, DIPBDIP(0) => \<const1>\, DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOADO_UNCONNECTED\(31 downto 2), DOADO(1 downto 0) => p_0_in(3 downto 2), DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOBDO_UNCONNECTED\(31 downto 2), DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(11 downto 10), DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => s_axis_phase_tvalid, ENBWREN => s_axis_phase_tvalid, INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_INJECTDBITERR_UNCONNECTED\, INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_INJECTSBITERR_UNCONNECTED\, RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => s_axis_phase_tvalid, REGCEB => s_axis_phase_tvalid, RSTRAMARSTRAM => \<const0>\, RSTRAMB => \<const0>\, RSTREGARSTREG => \<const0>\, RSTREGB => \<const0>\, SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_5_SBITERR_UNCONNECTED\, WEA(3) => \<const0>\, WEA(2) => \<const0>\, WEA(1) => \<const0>\, WEA(0) => \<const0>\, WEBWE(7) => \<const0>\, WEBWE(6) => \<const0>\, WEBWE(5) => \<const0>\, WEBWE(4) => \<const0>\, WEBWE(3) => \<const0>\, WEBWE(2) => \<const0>\, WEBWE(1) => \<const0>\, WEBWE(0) => \<const0>\ ); \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 1, DOB_REG => 1, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"5555555555555555555555555555555555555555555555555540000000000000", INIT_0B => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_0C => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_0D => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_0E => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_0F => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_10 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_11 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_12 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_13 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_14 => X"AAAAAAAAAAAAAAAAAAAAAAAAAA55555555555555555555555555555555555555", INIT_15 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_16 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_17 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_18 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_19 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_1A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_1B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_1C => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_1D => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_1E => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEAAAAAAAAAAAAAAAAAAAA", INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_2A => X"000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"5555555555555555555555555555555555555555555555555555555555555550", INIT_38 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_39 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_3A => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_3B => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_3C => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_3D => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_3E => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_3F => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_40 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_41 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_42 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_43 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_44 => X"5555555555555555555555555555555555555555555555555555555555555555", INIT_45 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA5555555", INIT_46 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_47 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_48 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_49 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_4A => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_4B => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_4C => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_4D => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_4E => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_4F => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_50 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_51 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_52 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_53 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_54 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_55 => X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_56 => X"FFFFFFFFFFFAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA", INIT_57 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_58 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_59 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_5A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_5C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_5D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_5E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_5F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_60 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_61 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_62 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_63 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_64 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_65 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_66 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_67 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_68 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_69 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_6A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_6B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_6C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_6E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_6F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_70 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_71 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_72 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_73 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_74 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_75 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_76 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_77 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_78 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_79 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_7F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_A => X"000000000", INIT_B => X"000000000", RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", READ_WIDTH_A => 2, READ_WIDTH_B => 2, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 2, WRITE_WIDTH_B => 0 ) port map ( ADDRARDADDR(15) => \<const1>\, ADDRARDADDR(14 downto 1) => sin_addr(13 downto 0), ADDRARDADDR(0) => \<const0>\, ADDRBWRADDR(15) => \<const1>\, ADDRBWRADDR(14 downto 1) => cos_addr(13 downto 0), ADDRBWRADDR(0) => \<const0>\, CASCADEINA => \<const1>\, CASCADEINB => \<const0>\, CASCADEOUTA => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => aclk, CLKBWRCLK => aclk, DBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DBITERR_UNCONNECTED\, DIADI(31) => \<const0>\, DIADI(30) => \<const0>\, DIADI(29) => \<const0>\, DIADI(28) => \<const0>\, DIADI(27) => \<const0>\, DIADI(26) => \<const0>\, DIADI(25) => \<const0>\, DIADI(24) => \<const0>\, DIADI(23) => \<const0>\, DIADI(22) => \<const0>\, DIADI(21) => \<const0>\, DIADI(20) => \<const0>\, DIADI(19) => \<const0>\, DIADI(18) => \<const0>\, DIADI(17) => \<const0>\, DIADI(16) => \<const0>\, DIADI(15) => \<const0>\, DIADI(14) => \<const0>\, DIADI(13) => \<const0>\, DIADI(12) => \<const0>\, DIADI(11) => \<const0>\, DIADI(10) => \<const0>\, DIADI(9) => \<const0>\, DIADI(8) => \<const0>\, DIADI(7) => \<const0>\, DIADI(6) => \<const0>\, DIADI(5) => \<const0>\, DIADI(4) => \<const0>\, DIADI(3) => \<const0>\, DIADI(2) => \<const0>\, DIADI(1) => \<const1>\, DIADI(0) => \<const1>\, DIBDI(31) => \<const1>\, DIBDI(30) => \<const1>\, DIBDI(29) => \<const1>\, DIBDI(28) => \<const1>\, DIBDI(27) => \<const1>\, DIBDI(26) => \<const1>\, DIBDI(25) => \<const1>\, DIBDI(24) => \<const1>\, DIBDI(23) => \<const1>\, DIBDI(22) => \<const1>\, DIBDI(21) => \<const1>\, DIBDI(20) => \<const1>\, DIBDI(19) => \<const1>\, DIBDI(18) => \<const1>\, DIBDI(17) => \<const1>\, DIBDI(16) => \<const1>\, DIBDI(15) => \<const1>\, DIBDI(14) => \<const1>\, DIBDI(13) => \<const1>\, DIBDI(12) => \<const1>\, DIBDI(11) => \<const1>\, DIBDI(10) => \<const1>\, DIBDI(9) => \<const1>\, DIBDI(8) => \<const1>\, DIBDI(7) => \<const1>\, DIBDI(6) => \<const1>\, DIBDI(5) => \<const1>\, DIBDI(4) => \<const1>\, DIBDI(3) => \<const1>\, DIBDI(2) => \<const1>\, DIBDI(1) => \<const1>\, DIBDI(0) => \<const1>\, DIPADIP(3) => \<const0>\, DIPADIP(2) => \<const0>\, DIPADIP(1) => \<const0>\, DIPADIP(0) => \<const0>\, DIPBDIP(3) => \<const1>\, DIPBDIP(2) => \<const1>\, DIPBDIP(1) => \<const1>\, DIPBDIP(0) => \<const1>\, DOADO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOADO_UNCONNECTED\(31 downto 2), DOADO(1 downto 0) => p_0_in(5 downto 4), DOBDO(31 downto 2) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOBDO_UNCONNECTED\(31 downto 2), DOBDO(1 downto 0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(13 downto 12), DOPADOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => s_axis_phase_tvalid, ENBWREN => s_axis_phase_tvalid, INJECTDBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_INJECTDBITERR_UNCONNECTED\, INJECTSBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_INJECTSBITERR_UNCONNECTED\, RDADDRECC(8 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => s_axis_phase_tvalid, REGCEB => s_axis_phase_tvalid, RSTRAMARSTRAM => \<const0>\, RSTRAMB => \<const0>\, RSTREGARSTREG => \<const0>\, RSTREGB => \<const0>\, SBITERR => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_6_SBITERR_UNCONNECTED\, WEA(3) => \<const0>\, WEA(2) => \<const0>\, WEA(1) => \<const0>\, WEA(0) => \<const0>\, WEBWE(7) => \<const0>\, WEBWE(6) => \<const0>\, WEBWE(5) => \<const0>\, WEBWE(4) => \<const0>\, WEBWE(3) => \<const0>\, WEBWE(2) => \<const0>\, WEBWE(1) => \<const0>\, WEBWE(0) => \<const0>\ ); \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7\: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 1, DOB_REG => 1, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000000000000000000", INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_17 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_18 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_1A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_1B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_1C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_1F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_20 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_21 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_23 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_24 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_25 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_26 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_28 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_29 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_2A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_2B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_2C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_2D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_2E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_2F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_30 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_31 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_32 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_33 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_34 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_35 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_36 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_37 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_38 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_39 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_3B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_3C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_3D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_3E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_3F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_A => X"00000", INIT_B => X"00000", RAM_MODE => "TDP", READ_WIDTH_A => 1, READ_WIDTH_B => 1, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 0 ) port map ( ADDRARDADDR(13 downto 0) => sin_addr(13 downto 0), ADDRBWRADDR(13 downto 0) => cos_addr(13 downto 0), CLKARDCLK => aclk, CLKBWRCLK => aclk, DIADI(15) => \<const0>\, DIADI(14) => \<const0>\, DIADI(13) => \<const0>\, DIADI(12) => \<const0>\, DIADI(11) => \<const0>\, DIADI(10) => \<const0>\, DIADI(9) => \<const0>\, DIADI(8) => \<const0>\, DIADI(7) => \<const0>\, DIADI(6) => \<const0>\, DIADI(5) => \<const0>\, DIADI(4) => \<const0>\, DIADI(3) => \<const0>\, DIADI(2) => \<const0>\, DIADI(1) => \<const0>\, DIADI(0) => \<const1>\, DIBDI(15) => \<const1>\, DIBDI(14) => \<const1>\, DIBDI(13) => \<const1>\, DIBDI(12) => \<const1>\, DIBDI(11) => \<const1>\, DIBDI(10) => \<const1>\, DIBDI(9) => \<const1>\, DIBDI(8) => \<const1>\, DIBDI(7) => \<const1>\, DIBDI(6) => \<const1>\, DIBDI(5) => \<const1>\, DIBDI(4) => \<const1>\, DIBDI(3) => \<const1>\, DIBDI(2) => \<const1>\, DIBDI(1) => \<const1>\, DIBDI(0) => \<const1>\, DIPADIP(1) => \<const0>\, DIPADIP(0) => \<const0>\, DIPBDIP(1) => \<const1>\, DIPBDIP(0) => \<const1>\, DOADO(15 downto 1) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOADO_UNCONNECTED\(15 downto 1), DOADO(0) => p_0_in(6), DOBDO(15 downto 1) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOBDO_UNCONNECTED\(15 downto 1), DOBDO(0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(14), DOPADOP(1 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOPADOP_UNCONNECTED\(1 downto 0), DOPBDOP(1 downto 0) => \NLW_i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_7_DOPBDOP_UNCONNECTED\(1 downto 0), ENARDEN => s_axis_phase_tvalid, ENBWREN => s_axis_phase_tvalid, REGCEAREGCE => s_axis_phase_tvalid, REGCEB => s_axis_phase_tvalid, RSTRAMARSTRAM => \<const0>\, RSTRAMB => \<const0>\, RSTREGARSTREG => \<const0>\, RSTREGB => \<const0>\, WEA(1) => \<const0>\, WEA(0) => \<const0>\, WEBWE(3) => \<const0>\, WEBWE(2) => \<const0>\, WEBWE(1) => \<const0>\, WEBWE(0) => \<const0>\ ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1(0), Q => mod_cos_addr(0), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1(10), Q => mod_cos_addr(10), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1(11), Q => mod_cos_addr(11), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1(12), Q => mod_cos_addr(12), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1(13), Q => mod_cos_addr(13), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1(1), Q => mod_cos_addr(1), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1(2), Q => mod_cos_addr(2), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1(3), Q => mod_cos_addr(3), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1(4), Q => mod_cos_addr(4), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1(5), Q => mod_cos_addr(5), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1(6), Q => mod_cos_addr(6), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1(7), Q => mod_cos_addr(7), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1(8), Q => mod_cos_addr(8), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_cos.i_addr_mod_stage1.mod_cos_addr_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => I1(9), Q => mod_cos_addr(9), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => D(0), Q => mod_sin_addr(0), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => D(10), Q => mod_sin_addr(10), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => D(11), Q => mod_sin_addr(11), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => D(12), Q => mod_sin_addr(12), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => D(13), Q => mod_sin_addr(13), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => D(1), Q => mod_sin_addr(1), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => D(2), Q => mod_sin_addr(2), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => D(3), Q => mod_sin_addr(3), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => D(4), Q => mod_sin_addr(4), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => D(5), Q => mod_sin_addr(5), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => D(6), Q => mod_sin_addr(6), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => D(7), Q => mod_sin_addr(7), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => D(8), Q => mod_sin_addr(8), R => \<const0>\ ); \i_rtl.i_quarter_table.i_has_sin.i_addr_mod_stage1.mod_sin_addr_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => D(9), Q => mod_sin_addr(9), R => \<const0>\ ); \i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ls\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_3\ port map ( aclk => aclk, m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(7 downto 0), \out\(7 downto 0) => cos_ls1(7 downto 0), s_axis_phase_tvalid => s_axis_phase_tvalid ); \i_rtl.i_quarter_table.i_piped_map.i_cardinal_cos_ms\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_4\ port map ( I1 => _6_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\, I2 => _5_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\, I3 => _4_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\, I4 => _3_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\, I5 => _2_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\, I6 => _1_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\, I7 => _0_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\, I8 => _7_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\, aclk => aclk, m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(15 downto 8), s_axis_phase_tvalid => s_axis_phase_tvalid ); \i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14\ port map ( aclk => aclk, m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(23 downto 16), \out\(7 downto 0) => sin_ls1(7 downto 0), s_axis_phase_tvalid => s_axis_phase_tvalid ); \i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_2\ port map ( I1 => _6_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\, I2 => _5_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\, I3 => _4_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\, I4 => _3_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\, I5 => _2_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\, I6 => _1_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\, I7 => _0_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\, I8 => _7_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\, aclk => aclk, m_axis_data_tdata(7 downto 0) => m_axis_data_tdata(31 downto 24), s_axis_phase_tvalid => s_axis_phase_tvalid ); \i_rtl.i_quarter_table.i_piped_map.i_original_cos_ls\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized16\ port map ( DOBDO(0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_cos_RAM_op_reg\(0), I1 => _22_i_rtl.i_quarter_table.i_addr_reg_c\, I2 => _21_i_rtl.i_quarter_table.i_addr_reg_c\, I3 => _20_i_rtl.i_quarter_table.i_addr_reg_c\, I4 => _19_i_rtl.i_quarter_table.i_addr_reg_c\, I5 => _17_i_rtl.i_quarter_table.i_addr_reg_c\, I6 => _16_i_rtl.i_quarter_table.i_addr_reg_c\, I7 => _15_i_rtl.i_quarter_table.i_addr_reg_c\, I8 => _23_i_rtl.i_quarter_table.i_addr_reg_c\, aclk => aclk, \out\(8 downto 0) => cos_ls1(8 downto 0), s_axis_phase_tvalid => s_axis_phase_tvalid ); \i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_1\ port map ( I1 => _18_i_rtl.i_quarter_table.i_addr_reg_c\, I2 => _30_i_rtl.i_quarter_table.i_addr_reg_c\, I3 => _29_i_rtl.i_quarter_table.i_addr_reg_c\, I4 => _28_i_rtl.i_quarter_table.i_addr_reg_c\, I5 => _27_i_rtl.i_quarter_table.i_addr_reg_c\, I6 => _26_i_rtl.i_quarter_table.i_addr_reg_c\, I7 => _25_i_rtl.i_quarter_table.i_addr_reg_c\, I8 => _24_i_rtl.i_quarter_table.i_addr_reg_c\, O1 => _0_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\, O2 => _1_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\, O3 => _2_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\, O4 => _3_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\, O5 => _4_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\, O6 => _5_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\, O7 => _6_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\, O8 => _7_i_rtl.i_quarter_table.i_piped_map.i_original_cos_ms\, aclk => aclk, \out\(0) => cos_ls1(8), s_axis_phase_tvalid => s_axis_phase_tvalid ); \i_rtl.i_quarter_table.i_piped_map.i_original_sin_ls\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized16_5\ port map ( I1 => _9_i_rtl.i_quarter_table.i_addr_reg_c\, I2 => _8_i_rtl.i_quarter_table.i_addr_reg_c\, I3 => _10_i_rtl.i_quarter_table.i_addr_reg_c\, I4 => _11_i_rtl.i_quarter_table.i_addr_reg_c\, I5 => _13_i_rtl.i_quarter_table.i_addr_reg_c\, I6 => _31_i_rtl.i_quarter_table.i_addr_reg_c\, I7 => _12_i_rtl.i_quarter_table.i_addr_reg_c\, I8 => _14_i_rtl.i_quarter_table.i_addr_reg_c\, I9(0) => \i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg\(0), aclk => aclk, \out\(8 downto 0) => sin_ls1(8 downto 0), s_axis_phase_tvalid => s_axis_phase_tvalid ); \i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized14_6\ port map ( I1 => _1_i_rtl.i_quarter_table.i_addr_reg_c\, I2 => _2_i_rtl.i_quarter_table.i_addr_reg_c\, I3 => _3_i_rtl.i_quarter_table.i_addr_reg_c\, I4 => _4_i_rtl.i_quarter_table.i_addr_reg_c\, I5 => _5_i_rtl.i_quarter_table.i_addr_reg_c\, I6 => _6_i_rtl.i_quarter_table.i_addr_reg_c\, I7 => _7_i_rtl.i_quarter_table.i_addr_reg_c\, O1 => _0_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\, O2 => _1_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\, O3 => _2_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\, O4 => _3_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\, O5 => _4_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\, O6 => _5_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\, O7 => _6_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\, O8 => _7_i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms\, aclk => aclk, invert_sin => invert_sin, \out\(0) => sin_ls1(8), s_axis_phase_tvalid => s_axis_phase_tvalid ); \i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_cos_addr(0), Q => cos_addr(0), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_cos_addr(10), Q => cos_addr(10), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_cos_addr(11), Q => cos_addr(11), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_cos_addr(12), Q => cos_addr(12), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_cos_addr(13), Q => cos_addr(13), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_cos_addr(1), Q => cos_addr(1), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_cos_addr(2), Q => cos_addr(2), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_cos_addr(3), Q => cos_addr(3), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_cos_addr(4), Q => cos_addr(4), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_cos_addr(5), Q => cos_addr(5), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_cos_addr(6), Q => cos_addr(6), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_cos_addr(7), Q => cos_addr(7), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_cos_addr(8), Q => cos_addr(8), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.cos_addr_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_cos_addr(9), Q => cos_addr(9), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_sin_addr(0), Q => sin_addr(0), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_sin_addr(10), Q => sin_addr(10), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_sin_addr(11), Q => sin_addr(11), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_sin_addr(12), Q => sin_addr(12), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_sin_addr(13), Q => sin_addr(13), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_sin_addr(1), Q => sin_addr(1), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_sin_addr(2), Q => sin_addr(2), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_sin_addr(3), Q => sin_addr(3), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_sin_addr(4), Q => sin_addr(4), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_sin_addr(5), Q => sin_addr(5), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_sin_addr(6), Q => sin_addr(6), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_sin_addr(7), Q => sin_addr(7), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_sin_addr(8), Q => sin_addr(8), R => \<const0>\ ); \i_rtl.i_quarter_table.i_rom_addr_stage1.sin_addr_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => mod_sin_addr(9), Q => sin_addr(9), R => \<const0>\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ddsdds_compiler_v6_0_core is port ( m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axis_phase_tvalid : in STD_LOGIC; aclk : in STD_LOGIC; reg_s_phase_fifo_din : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); end ddsdds_compiler_v6_0_core; architecture STRUCTURE of ddsdds_compiler_v6_0_core is signal acc_phase_shaped : STD_LOGIC_VECTOR ( 15 downto 14 ); signal asyn_mod_sin_addr : STD_LOGIC_VECTOR ( 13 downto 0 ); signal _16_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC; signal _17_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC; signal _18_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC; signal _19_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC; signal _20_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC; signal _21_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC; signal _22_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC; signal _23_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC; signal _24_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC; signal _25_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC; signal _26_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC; signal _27_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC; signal _28_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC; signal _29_I_PHASEGEN.i_conventional_accum.i_accum\ : STD_LOGIC; begin \I_PHASEGEN.i_conventional_accum.i_accum\: entity work.ddsaccum port map ( D(13 downto 0) => asyn_mod_sin_addr(13 downto 0), I1(13) => _16_I_PHASEGEN.i_conventional_accum.i_accum\, I1(12) => _17_I_PHASEGEN.i_conventional_accum.i_accum\, I1(11) => _18_I_PHASEGEN.i_conventional_accum.i_accum\, I1(10) => _19_I_PHASEGEN.i_conventional_accum.i_accum\, I1(9) => _20_I_PHASEGEN.i_conventional_accum.i_accum\, I1(8) => _21_I_PHASEGEN.i_conventional_accum.i_accum\, I1(7) => _22_I_PHASEGEN.i_conventional_accum.i_accum\, I1(6) => _23_I_PHASEGEN.i_conventional_accum.i_accum\, I1(5) => _24_I_PHASEGEN.i_conventional_accum.i_accum\, I1(4) => _25_I_PHASEGEN.i_conventional_accum.i_accum\, I1(3) => _26_I_PHASEGEN.i_conventional_accum.i_accum\, I1(2) => _27_I_PHASEGEN.i_conventional_accum.i_accum\, I1(1) => _28_I_PHASEGEN.i_conventional_accum.i_accum\, I1(0) => _29_I_PHASEGEN.i_conventional_accum.i_accum\, L(1 downto 0) => acc_phase_shaped(15 downto 14), aclk => aclk, reg_s_phase_fifo_din(15 downto 0) => reg_s_phase_fifo_din(15 downto 0), s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0), s_axis_phase_tvalid => s_axis_phase_tvalid ); \I_SINCOS.i_std_rom.i_rom\: entity work.\ddssin_cos__parameterized0\ port map ( D(13 downto 0) => asyn_mod_sin_addr(13 downto 0), I1(13) => _16_I_PHASEGEN.i_conventional_accum.i_accum\, I1(12) => _17_I_PHASEGEN.i_conventional_accum.i_accum\, I1(11) => _18_I_PHASEGEN.i_conventional_accum.i_accum\, I1(10) => _19_I_PHASEGEN.i_conventional_accum.i_accum\, I1(9) => _20_I_PHASEGEN.i_conventional_accum.i_accum\, I1(8) => _21_I_PHASEGEN.i_conventional_accum.i_accum\, I1(7) => _22_I_PHASEGEN.i_conventional_accum.i_accum\, I1(6) => _23_I_PHASEGEN.i_conventional_accum.i_accum\, I1(5) => _24_I_PHASEGEN.i_conventional_accum.i_accum\, I1(4) => _25_I_PHASEGEN.i_conventional_accum.i_accum\, I1(3) => _26_I_PHASEGEN.i_conventional_accum.i_accum\, I1(2) => _27_I_PHASEGEN.i_conventional_accum.i_accum\, I1(1) => _28_I_PHASEGEN.i_conventional_accum.i_accum\, I1(0) => _29_I_PHASEGEN.i_conventional_accum.i_accum\, L(1 downto 0) => acc_phase_shaped(15 downto 14), aclk => aclk, m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0), s_axis_phase_tvalid => s_axis_phase_tvalid ); \i_rdy.rdy_logic\: entity work.ddsdds_compiler_v6_0_rdy port map ( aclk => aclk, s_axis_phase_tvalid => s_axis_phase_tvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \ddsdds_compiler_v6_0_viv__parameterized0\ is port ( aclk : in STD_LOGIC; aclken : in STD_LOGIC; aresetn : in STD_LOGIC; s_axis_phase_tvalid : in STD_LOGIC; s_axis_phase_tready : out STD_LOGIC; s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axis_phase_tlast : in STD_LOGIC; s_axis_phase_tuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_config_tvalid : in STD_LOGIC; s_axis_config_tready : out STD_LOGIC; s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axis_config_tlast : in STD_LOGIC; m_axis_data_tvalid : out STD_LOGIC; m_axis_data_tready : in STD_LOGIC; m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axis_data_tlast : out STD_LOGIC; m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_phase_tvalid : out STD_LOGIC; m_axis_phase_tready : in STD_LOGIC; m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axis_phase_tlast : out STD_LOGIC; m_axis_phase_tuser : out STD_LOGIC_VECTOR ( 0 to 0 ); event_pinc_invalid : out STD_LOGIC; event_poff_invalid : out STD_LOGIC; event_phase_in_invalid : out STD_LOGIC; event_s_phase_tlast_missing : out STD_LOGIC; event_s_phase_tlast_unexpected : out STD_LOGIC; event_s_phase_chanid_incorrect : out STD_LOGIC; event_s_config_tlast_missing : out STD_LOGIC; event_s_config_tlast_unexpected : out STD_LOGIC; debug_axi_pinc_in : out STD_LOGIC_VECTOR ( 15 downto 0 ); debug_axi_poff_in : out STD_LOGIC_VECTOR ( 15 downto 0 ); debug_axi_resync_in : out STD_LOGIC; debug_axi_chan_in : out STD_LOGIC_VECTOR ( 0 to 0 ); debug_core_nd : out STD_LOGIC; debug_phase : out STD_LOGIC_VECTOR ( 15 downto 0 ); debug_phase_nd : out STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "dds_compiler_v6_0_viv"; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "zynq"; attribute C_MODE_OF_OPERATION : integer; attribute C_MODE_OF_OPERATION of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_MODULUS : integer; attribute C_MODULUS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 9; attribute C_ACCUMULATOR_WIDTH : integer; attribute C_ACCUMULATOR_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16; attribute C_CHANNELS : integer; attribute C_CHANNELS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1; attribute C_HAS_PHASE_OUT : integer; attribute C_HAS_PHASE_OUT of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_HAS_PHASEGEN : integer; attribute C_HAS_PHASEGEN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1; attribute C_HAS_SINCOS : integer; attribute C_HAS_SINCOS of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1; attribute C_LATENCY : integer; attribute C_LATENCY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 7; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1; attribute C_NEGATIVE_COSINE : integer; attribute C_NEGATIVE_COSINE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_NEGATIVE_SINE : integer; attribute C_NEGATIVE_SINE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_NOISE_SHAPING : integer; attribute C_NOISE_SHAPING of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_OUTPUTS_REQUIRED : integer; attribute C_OUTPUTS_REQUIRED of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 2; attribute C_OUTPUT_FORM : integer; attribute C_OUTPUT_FORM of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_OUTPUT_WIDTH : integer; attribute C_OUTPUT_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16; attribute C_PHASE_ANGLE_WIDTH : integer; attribute C_PHASE_ANGLE_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16; attribute C_PHASE_INCREMENT : integer; attribute C_PHASE_INCREMENT of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 3; attribute C_PHASE_INCREMENT_VALUE : string; attribute C_PHASE_INCREMENT_VALUE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0"; attribute C_RESYNC : integer; attribute C_RESYNC of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_PHASE_OFFSET : integer; attribute C_PHASE_OFFSET of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_PHASE_OFFSET_VALUE : string; attribute C_PHASE_OFFSET_VALUE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0"; attribute C_OPTIMISE_GOAL : integer; attribute C_OPTIMISE_GOAL of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_USE_DSP48 : integer; attribute C_USE_DSP48 of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_POR_MODE : integer; attribute C_POR_MODE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_AMPLITUDE : integer; attribute C_AMPLITUDE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_HAS_ACLKEN : integer; attribute C_HAS_ACLKEN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_HAS_ARESETN : integer; attribute C_HAS_ARESETN of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_HAS_TLAST : integer; attribute C_HAS_TLAST of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_HAS_TREADY : integer; attribute C_HAS_TREADY of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_HAS_S_PHASE : integer; attribute C_HAS_S_PHASE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1; attribute C_S_PHASE_TDATA_WIDTH : integer; attribute C_S_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 16; attribute C_S_PHASE_HAS_TUSER : integer; attribute C_S_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_S_PHASE_TUSER_WIDTH : integer; attribute C_S_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1; attribute C_HAS_S_CONFIG : integer; attribute C_HAS_S_CONFIG of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_S_CONFIG_SYNC_MODE : integer; attribute C_S_CONFIG_SYNC_MODE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_S_CONFIG_TDATA_WIDTH : integer; attribute C_S_CONFIG_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1; attribute C_HAS_M_DATA : integer; attribute C_HAS_M_DATA of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1; attribute C_M_DATA_TDATA_WIDTH : integer; attribute C_M_DATA_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 32; attribute C_M_DATA_HAS_TUSER : integer; attribute C_M_DATA_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_M_DATA_TUSER_WIDTH : integer; attribute C_M_DATA_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1; attribute C_HAS_M_PHASE : integer; attribute C_HAS_M_PHASE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_M_PHASE_TDATA_WIDTH : integer; attribute C_M_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1; attribute C_M_PHASE_HAS_TUSER : integer; attribute C_M_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_M_PHASE_TUSER_WIDTH : integer; attribute C_M_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1; attribute C_DEBUG_INTERFACE : integer; attribute C_DEBUG_INTERFACE of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 0; attribute C_CHAN_WIDTH : integer; attribute C_CHAN_WIDTH of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is 1; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of \ddsdds_compiler_v6_0_viv__parameterized0\ : entity is "yes"; end \ddsdds_compiler_v6_0_viv__parameterized0\; architecture STRUCTURE of \ddsdds_compiler_v6_0_viv__parameterized0\ is signal \<const0>\ : STD_LOGIC; signal reg_s_phase_fifo_din : STD_LOGIC_VECTOR ( 15 downto 0 ); begin debug_axi_chan_in(0) <= \<const0>\; debug_axi_pinc_in(15) <= \<const0>\; debug_axi_pinc_in(14) <= \<const0>\; debug_axi_pinc_in(13) <= \<const0>\; debug_axi_pinc_in(12) <= \<const0>\; debug_axi_pinc_in(11) <= \<const0>\; debug_axi_pinc_in(10) <= \<const0>\; debug_axi_pinc_in(9) <= \<const0>\; debug_axi_pinc_in(8) <= \<const0>\; debug_axi_pinc_in(7) <= \<const0>\; debug_axi_pinc_in(6) <= \<const0>\; debug_axi_pinc_in(5) <= \<const0>\; debug_axi_pinc_in(4) <= \<const0>\; debug_axi_pinc_in(3) <= \<const0>\; debug_axi_pinc_in(2) <= \<const0>\; debug_axi_pinc_in(1) <= \<const0>\; debug_axi_pinc_in(0) <= \<const0>\; debug_axi_poff_in(15) <= \<const0>\; debug_axi_poff_in(14) <= \<const0>\; debug_axi_poff_in(13) <= \<const0>\; debug_axi_poff_in(12) <= \<const0>\; debug_axi_poff_in(11) <= \<const0>\; debug_axi_poff_in(10) <= \<const0>\; debug_axi_poff_in(9) <= \<const0>\; debug_axi_poff_in(8) <= \<const0>\; debug_axi_poff_in(7) <= \<const0>\; debug_axi_poff_in(6) <= \<const0>\; debug_axi_poff_in(5) <= \<const0>\; debug_axi_poff_in(4) <= \<const0>\; debug_axi_poff_in(3) <= \<const0>\; debug_axi_poff_in(2) <= \<const0>\; debug_axi_poff_in(1) <= \<const0>\; debug_axi_poff_in(0) <= \<const0>\; debug_axi_resync_in <= \<const0>\; debug_core_nd <= \<const0>\; debug_phase(15) <= \<const0>\; debug_phase(14) <= \<const0>\; debug_phase(13) <= \<const0>\; debug_phase(12) <= \<const0>\; debug_phase(11) <= \<const0>\; debug_phase(10) <= \<const0>\; debug_phase(9) <= \<const0>\; debug_phase(8) <= \<const0>\; debug_phase(7) <= \<const0>\; debug_phase(6) <= \<const0>\; debug_phase(5) <= \<const0>\; debug_phase(4) <= \<const0>\; debug_phase(3) <= \<const0>\; debug_phase(2) <= \<const0>\; debug_phase(1) <= \<const0>\; debug_phase(0) <= \<const0>\; debug_phase_nd <= \<const0>\; event_phase_in_invalid <= \<const0>\; event_pinc_invalid <= \<const0>\; event_poff_invalid <= \<const0>\; event_s_config_tlast_missing <= \<const0>\; event_s_config_tlast_unexpected <= \<const0>\; event_s_phase_chanid_incorrect <= \<const0>\; event_s_phase_tlast_missing <= \<const0>\; event_s_phase_tlast_unexpected <= \<const0>\; m_axis_data_tlast <= \<const0>\; m_axis_data_tuser(0) <= \<const0>\; m_axis_phase_tdata(0) <= \<const0>\; m_axis_phase_tlast <= \<const0>\; m_axis_phase_tuser(0) <= \<const0>\; m_axis_phase_tvalid <= \<const0>\; s_axis_config_tready <= \<const0>\; s_axis_phase_tready <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \has_s_phase.ce_i_delay\: entity work.\ddsxbip_pipe_v3_0_viv__parameterized0\ port map ( aclk => aclk ); \has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => s_axis_phase_tdata(0), Q => reg_s_phase_fifo_din(0), R => \<const0>\ ); \has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => s_axis_phase_tdata(10), Q => reg_s_phase_fifo_din(10), R => \<const0>\ ); \has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => s_axis_phase_tdata(11), Q => reg_s_phase_fifo_din(11), R => \<const0>\ ); \has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => s_axis_phase_tdata(12), Q => reg_s_phase_fifo_din(12), R => \<const0>\ ); \has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => s_axis_phase_tdata(13), Q => reg_s_phase_fifo_din(13), R => \<const0>\ ); \has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => s_axis_phase_tdata(14), Q => reg_s_phase_fifo_din(14), R => \<const0>\ ); \has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => s_axis_phase_tdata(15), Q => reg_s_phase_fifo_din(15), R => \<const0>\ ); \has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => s_axis_phase_tdata(1), Q => reg_s_phase_fifo_din(1), R => \<const0>\ ); \has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => s_axis_phase_tdata(2), Q => reg_s_phase_fifo_din(2), R => \<const0>\ ); \has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => s_axis_phase_tdata(3), Q => reg_s_phase_fifo_din(3), R => \<const0>\ ); \has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => s_axis_phase_tdata(4), Q => reg_s_phase_fifo_din(4), R => \<const0>\ ); \has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => s_axis_phase_tdata(5), Q => reg_s_phase_fifo_din(5), R => \<const0>\ ); \has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => s_axis_phase_tdata(6), Q => reg_s_phase_fifo_din(6), R => \<const0>\ ); \has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => s_axis_phase_tdata(7), Q => reg_s_phase_fifo_din(7), R => \<const0>\ ); \has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => s_axis_phase_tdata(8), Q => reg_s_phase_fifo_din(8), R => \<const0>\ ); \has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => s_axis_phase_tvalid, D => s_axis_phase_tdata(9), Q => reg_s_phase_fifo_din(9), R => \<const0>\ ); i_dds: entity work.ddsdds_compiler_v6_0_core port map ( aclk => aclk, m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0), reg_s_phase_fifo_din(15 downto 0) => reg_s_phase_fifo_din(15 downto 0), s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0), s_axis_phase_tvalid => s_axis_phase_tvalid ); \i_has_nd_rdy_pipe.channel_pipe\: entity work.ddsxbip_pipe_v3_0_viv_0 port map ( aclk => aclk, s_axis_phase_tvalid => s_axis_phase_tvalid ); \i_has_nd_rdy_pipe.valid_phase_read_del\: entity work.ddsxbip_pipe_v3_0_viv port map ( aclk => aclk, m_axis_data_tvalid => m_axis_data_tvalid, s_axis_phase_tvalid => s_axis_phase_tvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \ddsdds_compiler_v6_0__parameterized0\ is port ( m_axis_data_tvalid : out STD_LOGIC; m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); aclk : in STD_LOGIC; s_axis_phase_tvalid : in STD_LOGIC; s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \ddsdds_compiler_v6_0__parameterized0\ : entity is "dds_compiler_v6_0"; end \ddsdds_compiler_v6_0__parameterized0\; architecture STRUCTURE of \ddsdds_compiler_v6_0__parameterized0\ is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal NLW_i_synth_debug_axi_resync_in_UNCONNECTED : STD_LOGIC; signal NLW_i_synth_debug_core_nd_UNCONNECTED : STD_LOGIC; signal NLW_i_synth_debug_phase_nd_UNCONNECTED : STD_LOGIC; signal NLW_i_synth_event_phase_in_invalid_UNCONNECTED : STD_LOGIC; signal NLW_i_synth_event_pinc_invalid_UNCONNECTED : STD_LOGIC; signal NLW_i_synth_event_poff_invalid_UNCONNECTED : STD_LOGIC; signal NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC; signal NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC; signal NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC; signal NLW_i_synth_event_s_phase_tlast_missing_UNCONNECTED : STD_LOGIC; signal NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC; signal NLW_i_synth_m_axis_data_tlast_UNCONNECTED : STD_LOGIC; signal NLW_i_synth_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC; signal NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC; signal NLW_i_synth_s_axis_config_tready_UNCONNECTED : STD_LOGIC; signal NLW_i_synth_s_axis_phase_tready_UNCONNECTED : STD_LOGIC; signal NLW_i_synth_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_i_synth_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_i_synth_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_i_synth_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_i_synth_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_i_synth_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_i_synth_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_ACCUMULATOR_WIDTH : integer; attribute C_ACCUMULATOR_WIDTH of i_synth : label is 16; attribute C_AMPLITUDE : integer; attribute C_AMPLITUDE of i_synth : label is 0; attribute C_CHANNELS : integer; attribute C_CHANNELS of i_synth : label is 1; attribute C_CHAN_WIDTH : integer; attribute C_CHAN_WIDTH of i_synth : label is 1; attribute C_DEBUG_INTERFACE : integer; attribute C_DEBUG_INTERFACE of i_synth : label is 0; attribute C_HAS_ACLKEN : integer; attribute C_HAS_ACLKEN of i_synth : label is 0; attribute C_HAS_ARESETN : integer; attribute C_HAS_ARESETN of i_synth : label is 0; attribute C_HAS_M_DATA : integer; attribute C_HAS_M_DATA of i_synth : label is 1; attribute C_HAS_M_PHASE : integer; attribute C_HAS_M_PHASE of i_synth : label is 0; attribute C_HAS_PHASEGEN : integer; attribute C_HAS_PHASEGEN of i_synth : label is 1; attribute C_HAS_PHASE_OUT : integer; attribute C_HAS_PHASE_OUT of i_synth : label is 0; attribute C_HAS_SINCOS : integer; attribute C_HAS_SINCOS of i_synth : label is 1; attribute C_HAS_S_CONFIG : integer; attribute C_HAS_S_CONFIG of i_synth : label is 0; attribute C_HAS_S_PHASE : integer; attribute C_HAS_S_PHASE of i_synth : label is 1; attribute C_HAS_TLAST : integer; attribute C_HAS_TLAST of i_synth : label is 0; attribute C_HAS_TREADY : integer; attribute C_HAS_TREADY of i_synth : label is 0; attribute C_LATENCY : integer; attribute C_LATENCY of i_synth : label is 7; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of i_synth : label is 1; attribute C_MODE_OF_OPERATION : integer; attribute C_MODE_OF_OPERATION of i_synth : label is 0; attribute C_MODULUS : integer; attribute C_MODULUS of i_synth : label is 9; attribute C_M_DATA_HAS_TUSER : integer; attribute C_M_DATA_HAS_TUSER of i_synth : label is 0; attribute C_M_DATA_TDATA_WIDTH : integer; attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 32; attribute C_M_DATA_TUSER_WIDTH : integer; attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1; attribute C_M_PHASE_HAS_TUSER : integer; attribute C_M_PHASE_HAS_TUSER of i_synth : label is 0; attribute C_M_PHASE_TDATA_WIDTH : integer; attribute C_M_PHASE_TDATA_WIDTH of i_synth : label is 1; attribute C_M_PHASE_TUSER_WIDTH : integer; attribute C_M_PHASE_TUSER_WIDTH of i_synth : label is 1; attribute C_NEGATIVE_COSINE : integer; attribute C_NEGATIVE_COSINE of i_synth : label is 0; attribute C_NEGATIVE_SINE : integer; attribute C_NEGATIVE_SINE of i_synth : label is 0; attribute C_NOISE_SHAPING : integer; attribute C_NOISE_SHAPING of i_synth : label is 0; attribute C_OPTIMISE_GOAL : integer; attribute C_OPTIMISE_GOAL of i_synth : label is 0; attribute C_OUTPUTS_REQUIRED : integer; attribute C_OUTPUTS_REQUIRED of i_synth : label is 2; attribute C_OUTPUT_FORM : integer; attribute C_OUTPUT_FORM of i_synth : label is 0; attribute C_OUTPUT_WIDTH : integer; attribute C_OUTPUT_WIDTH of i_synth : label is 16; attribute C_PHASE_ANGLE_WIDTH : integer; attribute C_PHASE_ANGLE_WIDTH of i_synth : label is 16; attribute C_PHASE_INCREMENT : integer; attribute C_PHASE_INCREMENT of i_synth : label is 3; attribute C_PHASE_INCREMENT_VALUE : string; attribute C_PHASE_INCREMENT_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0"; attribute C_PHASE_OFFSET : integer; attribute C_PHASE_OFFSET of i_synth : label is 0; attribute C_PHASE_OFFSET_VALUE : string; attribute C_PHASE_OFFSET_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0"; attribute C_POR_MODE : integer; attribute C_POR_MODE of i_synth : label is 0; attribute C_RESYNC : integer; attribute C_RESYNC of i_synth : label is 0; attribute C_S_CONFIG_SYNC_MODE : integer; attribute C_S_CONFIG_SYNC_MODE of i_synth : label is 0; attribute C_S_CONFIG_TDATA_WIDTH : integer; attribute C_S_CONFIG_TDATA_WIDTH of i_synth : label is 1; attribute C_S_PHASE_HAS_TUSER : integer; attribute C_S_PHASE_HAS_TUSER of i_synth : label is 0; attribute C_S_PHASE_TDATA_WIDTH : integer; attribute C_S_PHASE_TDATA_WIDTH of i_synth : label is 16; attribute C_S_PHASE_TUSER_WIDTH : integer; attribute C_S_PHASE_TUSER_WIDTH of i_synth : label is 1; attribute C_USE_DSP48 : integer; attribute C_USE_DSP48 of i_synth : label is 0; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of i_synth : label is "zynq"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of i_synth : label is "yes"; begin GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); i_synth: entity work.\ddsdds_compiler_v6_0_viv__parameterized0\ port map ( aclk => aclk, aclken => \<const1>\, aresetn => \<const1>\, debug_axi_chan_in(0) => NLW_i_synth_debug_axi_chan_in_UNCONNECTED(0), debug_axi_pinc_in(15 downto 0) => NLW_i_synth_debug_axi_pinc_in_UNCONNECTED(15 downto 0), debug_axi_poff_in(15 downto 0) => NLW_i_synth_debug_axi_poff_in_UNCONNECTED(15 downto 0), debug_axi_resync_in => NLW_i_synth_debug_axi_resync_in_UNCONNECTED, debug_core_nd => NLW_i_synth_debug_core_nd_UNCONNECTED, debug_phase(15 downto 0) => NLW_i_synth_debug_phase_UNCONNECTED(15 downto 0), debug_phase_nd => NLW_i_synth_debug_phase_nd_UNCONNECTED, event_phase_in_invalid => NLW_i_synth_event_phase_in_invalid_UNCONNECTED, event_pinc_invalid => NLW_i_synth_event_pinc_invalid_UNCONNECTED, event_poff_invalid => NLW_i_synth_event_poff_invalid_UNCONNECTED, event_s_config_tlast_missing => NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED, event_s_config_tlast_unexpected => NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED, event_s_phase_chanid_incorrect => NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED, event_s_phase_tlast_missing => NLW_i_synth_event_s_phase_tlast_missing_UNCONNECTED, event_s_phase_tlast_unexpected => NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED, m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0), m_axis_data_tlast => NLW_i_synth_m_axis_data_tlast_UNCONNECTED, m_axis_data_tready => \<const0>\, m_axis_data_tuser(0) => NLW_i_synth_m_axis_data_tuser_UNCONNECTED(0), m_axis_data_tvalid => m_axis_data_tvalid, m_axis_phase_tdata(0) => NLW_i_synth_m_axis_phase_tdata_UNCONNECTED(0), m_axis_phase_tlast => NLW_i_synth_m_axis_phase_tlast_UNCONNECTED, m_axis_phase_tready => \<const0>\, m_axis_phase_tuser(0) => NLW_i_synth_m_axis_phase_tuser_UNCONNECTED(0), m_axis_phase_tvalid => NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED, s_axis_config_tdata(0) => \<const0>\, s_axis_config_tlast => \<const0>\, s_axis_config_tready => NLW_i_synth_s_axis_config_tready_UNCONNECTED, s_axis_config_tvalid => \<const0>\, s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0), s_axis_phase_tlast => \<const0>\, s_axis_phase_tready => NLW_i_synth_s_axis_phase_tready_UNCONNECTED, s_axis_phase_tuser(0) => \<const0>\, s_axis_phase_tvalid => s_axis_phase_tvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity dds is port ( aclk : in STD_LOGIC; s_axis_phase_tvalid : in STD_LOGIC; s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); m_axis_data_tvalid : out STD_LOGIC; m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of dds : entity is true; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of dds : entity is "yes"; attribute x_core_info : string; attribute x_core_info of dds : entity is "dds_compiler_v6_0,Vivado 2013.4"; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of dds : entity is "dds,dds_compiler_v6_0,{}"; attribute core_generation_info : string; attribute core_generation_info of dds : entity is "dds,dds_compiler_v6_0,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=16,C_CHANNELS=1,C_HAS_PHASE_OUT=0,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=7,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=2,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=16,C_PHASE_ANGLE_WIDTH=16,C_PHASE_INCREMENT=3,C_PHASE_INCREMENT_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=1,C_S_PHASE_TDATA_WIDTH=16,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=32,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=0,C_M_PHASE_TDATA_WIDTH=1,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=1}"; end dds; architecture STRUCTURE of dds is begin U0: entity work.\ddsdds_compiler_v6_0__parameterized0\ port map ( aclk => aclk, m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0), m_axis_data_tvalid => m_axis_data_tvalid, s_axis_phase_tdata(15 downto 0) => s_axis_phase_tdata(15 downto 0), s_axis_phase_tvalid => s_axis_phase_tvalid ); end STRUCTURE; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity logical_unit is Port ( RA : in STD_LOGIC_VECTOR (15 downto 0); RB : in STD_LOGIC_VECTOR (15 downto 0); OP : in STD_LOGIC_VECTOR (2 downto 0); LOG_OUT : out STD_LOGIC_VECTOR (15 downto 0); SREG_OUT : out STD_LOGIC_VECTOR (3 downto 0)); end logical_unit; architecture Combinational of logical_unit is signal result : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); signal zro : STD_LOGIC := '0'; begin with OP select result <= RA or RB when "011", -- OR RA and RB when "010", -- AND RA and RB when "110", -- ANDI RB when "100", -- MOV RA or RB when OTHERS; -- SAFE (I guess) zro <= '1' when result(15 downto 0) = x"00000000" else '1'; -- Zero LOG_OUT <= result; SREG_OUT(2) <= zro; end Combinational; |
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use WORK.alu_types.all; entity P4ADDER is generic( N: integer:= NSUMG ); port ( A: in std_logic_vector(N-1 downto 0); B: in std_logic_vector(N-1 downto 0); Cin: in std_logic; S: out std_logic_vector(N-1 downto 0); OVERFLOW: out std_logic; -- In case we need it,and it is only used for debugging the correct behaviour of the adder Cout: out std_logic ); end P4ADDER; architecture structural of P4ADDER is signal CARRY, Ci: std_logic_vector(N/4 - 1 downto 0); component TREE generic( N: integer := NSUMG; LOGN: integer := LOG(NSUMG) -- For the LOG function refers to the P4ADDER_constants ); port( A: in std_logic_vector(N-1 downto 0); -- N bit input B: in std_logic_vector(N-1 downto 0); -- N bit input Cin: in std_logic; C: out std_logic_vector(N/4-1 downto 0) -- Generate a carry every fourth bit ); end component; component SUMGENERATOR generic( NBIT: integer := NSUMG; --32 NCSB: integer := NCSUMG --8 ); port ( A: in std_logic_vector(NBIT-1 downto 0); B: in std_logic_vector(NBIT-1 downto 0); Ci: in std_logic_vector(NCSB-1 downto 0); S: out std_logic_vector(NBIT-1 downto 0) ); end component; begin SPARSE_TREE: TREE generic map(N , LOG(N)) port map(A, B, Cin ,CARRY); -- As C32 is not needed/ '0' is the first carry in (without propagate) Ci <= CARRY((N/4)-2 downto 0) & Cin; Cout <= CARRY((N/4)-1); OVERFLOW <= CARRY((N/4)-1) XOR CARRY((N/4)-2); SUM_GENERATOR: SUMGENERATOR generic map(N , N/4) port map(A,B,Ci,S); end structural; |
library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity clk_baseclk_base_clk_wiz is port ( clk_raw : in STD_LOGIC; clk_250MHz : out STD_LOGIC; locked : out STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of clk_baseclk_base_clk_wiz : entity is "clk_base_clk_wiz"; end clk_baseclk_base_clk_wiz; architecture STRUCTURE of clk_baseclk_base_clk_wiz is signal clk_250MHz_clk_base : STD_LOGIC; signal clk_raw_clk_base : STD_LOGIC; signal clkfbout_buf_clk_base : STD_LOGIC; signal clkfbout_clk_base : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); attribute box_type : string; attribute box_type of clkf_buf : label is "PRIMITIVE"; attribute CAPACITANCE : string; attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; attribute IBUF_DELAY_VALUE : string; attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; attribute IFD_DELAY_VALUE : string; attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; attribute box_type of clkin1_ibufg : label is "PRIMITIVE"; attribute box_type of clkout1_buf : label is "PRIMITIVE"; attribute box_type of mmcm_adv_inst : label is "PRIMITIVE"; begin clkf_buf: unisim.vcomponents.BUFG port map ( I => clkfbout_clk_base, O => clkfbout_buf_clk_base ); clkin1_ibufg: unisim.vcomponents.IBUF generic map( IOSTANDARD => "DEFAULT" ) port map ( I => clk_raw, O => clk_raw_clk_base ); clkout1_buf: unisim.vcomponents.BUFG port map ( I => clk_250MHz_clk_base, O => clk_250MHz ); mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV generic map( BANDWIDTH => "OPTIMIZED", CLKFBOUT_MULT_F => 10.000000, CLKFBOUT_PHASE => 0.000000, CLKFBOUT_USE_FINE_PS => false, CLKIN1_PERIOD => 10.000000, CLKIN2_PERIOD => 0.000000, CLKOUT0_DIVIDE_F => 4.000000, CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, CLKOUT0_USE_FINE_PS => false, CLKOUT1_DIVIDE => 1, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, CLKOUT1_USE_FINE_PS => false, CLKOUT2_DIVIDE => 1, CLKOUT2_DUTY_CYCLE => 0.500000, CLKOUT2_PHASE => 0.000000, CLKOUT2_USE_FINE_PS => false, CLKOUT3_DIVIDE => 1, CLKOUT3_DUTY_CYCLE => 0.500000, CLKOUT3_PHASE => 0.000000, CLKOUT3_USE_FINE_PS => false, CLKOUT4_CASCADE => false, CLKOUT4_DIVIDE => 1, CLKOUT4_DUTY_CYCLE => 0.500000, CLKOUT4_PHASE => 0.000000, CLKOUT4_USE_FINE_PS => false, CLKOUT5_DIVIDE => 1, CLKOUT5_DUTY_CYCLE => 0.500000, CLKOUT5_PHASE => 0.000000, CLKOUT5_USE_FINE_PS => false, CLKOUT6_DIVIDE => 1, CLKOUT6_DUTY_CYCLE => 0.500000, CLKOUT6_PHASE => 0.000000, CLKOUT6_USE_FINE_PS => false, COMPENSATION => "ZHOLD", DIVCLK_DIVIDE => 1, IS_CLKINSEL_INVERTED => '0', IS_PSEN_INVERTED => '0', IS_PSINCDEC_INVERTED => '0', IS_PWRDWN_INVERTED => '0', IS_RST_INVERTED => '0', REF_JITTER1 => 0.010000, REF_JITTER2 => 0.000000, SS_EN => "FALSE", SS_MODE => "CENTER_HIGH", SS_MOD_PERIOD => 10000, STARTUP_WAIT => false ) port map ( CLKFBIN => clkfbout_buf_clk_base, CLKFBOUT => clkfbout_clk_base, CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, CLKIN1 => clk_raw_clk_base, CLKIN2 => '0', CLKINSEL => '1', CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, CLKOUT0 => clk_250MHz_clk_base, CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, DADDR(6) => '0', DADDR(5) => '0', DADDR(4) => '0', DADDR(3) => '0', DADDR(2) => '0', DADDR(1) => '0', DADDR(0) => '0', DCLK => '0', DEN => '0', DI(15) => '0', DI(14) => '0', DI(13) => '0', DI(12) => '0', DI(11) => '0', DI(10) => '0', DI(9) => '0', DI(8) => '0', DI(7) => '0', DI(6) => '0', DI(5) => '0', DI(4) => '0', DI(3) => '0', DI(2) => '0', DI(1) => '0', DI(0) => '0', DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, DWE => '0', LOCKED => locked, PSCLK => '0', PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, PSEN => '0', PSINCDEC => '0', PWRDWN => '0', RST => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity clk_base is port ( clk_raw : in STD_LOGIC; clk_250MHz : out STD_LOGIC; locked : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of clk_base : entity is true; attribute core_generation_info : string; attribute core_generation_info of clk_base : entity is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; end clk_base; architecture STRUCTURE of clk_base is begin U0: entity work.clk_baseclk_base_clk_wiz port map ( clk_250MHz => clk_250MHz, clk_raw => clk_raw, locked => locked ); end STRUCTURE; |
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY STD; USE STD.TEXTIO.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY EXTERNAL_MEMORY_synth IS PORT( CLK_IN : IN STD_LOGIC; RESET_IN : IN STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA ); END ENTITY; ARCHITECTURE EXTERNAL_MEMORY_synth_ARCH OF EXTERNAL_MEMORY_synth IS COMPONENT EXTERNAL_MEMORY_exdes PORT ( --Inputs - Port A WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); CLKA : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA: STD_LOGIC := '0'; SIGNAL RSTA: STD_LOGIC := '0'; SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0'); SIGNAL ADDRA_R: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0'); SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL CHECKER_EN : STD_LOGIC:='0'; SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); SIGNAL clk_in_i: STD_LOGIC; SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; SIGNAL ITER_R0 : STD_LOGIC := '0'; SIGNAL ITER_R1 : STD_LOGIC := '0'; SIGNAL ITER_R2 : STD_LOGIC := '0'; SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); BEGIN clk_in_i <= CLK_IN; CLKA <= clk_in_i; RSTA <= RESET_SYNC_R3 AFTER 50 ns; PROCESS(clk_in_i) BEGIN IF(RISING_EDGE(clk_in_i)) THEN RESET_SYNC_R1 <= RESET_IN; RESET_SYNC_R2 <= RESET_SYNC_R1; RESET_SYNC_R3 <= RESET_SYNC_R2; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ISSUE_FLAG_STATUS<= (OTHERS => '0'); ELSE ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; END IF; END IF; END PROCESS; STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; BMG_DATA_CHECKER_INST: ENTITY work.CHECKER GENERIC MAP ( WRITE_WIDTH => 16, READ_WIDTH => 16 ) PORT MAP ( CLK => CLKA, RST => RSTA, EN => CHECKER_EN_R, DATA_IN => DOUTA, STATUS => ISSUE_FLAG(0) ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RSTA='1') THEN CHECKER_EN_R <= '0'; ELSE CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; END IF; END IF; END PROCESS; BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN PORT MAP( CLK => clk_in_i, RST => RSTA, ADDRA => ADDRA, DINA => DINA, WEA => WEA, CHECK_DATA => CHECKER_EN ); PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STATUS(8) <= '0'; iter_r2 <= '0'; iter_r1 <= '0'; iter_r0 <= '0'; ELSE STATUS(8) <= iter_r2; iter_r2 <= iter_r1; iter_r1 <= iter_r0; iter_r0 <= STIMULUS_FLOW(8); END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN STIMULUS_FLOW <= (OTHERS => '0'); ELSIF(WEA(0)='1') THEN STIMULUS_FLOW <= STIMULUS_FLOW+1; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN WEA_R <= (OTHERS=>'0') AFTER 50 ns; DINA_R <= (OTHERS=>'0') AFTER 50 ns; ELSE WEA_R <= WEA AFTER 50 ns; DINA_R <= DINA AFTER 50 ns; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(RESET_SYNC_R3='1') THEN ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; ELSE ADDRA_R <= ADDRA AFTER 50 ns; END IF; END IF; END PROCESS; BMG_PORT: EXTERNAL_MEMORY_exdes PORT MAP ( --Port A WEA => WEA_R, ADDRA => ADDRA_R, DINA => DINA_R, DOUTA => DOUTA, CLKA => CLKA ); END ARCHITECTURE; |
Subsets and Splits