Module Import alias ImportFrom alias ImportFrom alias ClassDef bases NameLoad body FunctionDef arguments args NameParam defaults body Assign AttributeStore NameLoad attr ListComp Call NameLoad BinOpAdd NameLoad Num keyword Call AttributeLoad Str attr NameLoad comprehension NameStore Call NameLoad Num Assign AttributeStore NameLoad attr ListComp Call NameLoad BinOpAdd NameLoad Num comprehension NameStore Call NameLoad Num Assign AttributeStore NameLoad attr ListComp Call NameLoad BinOpAdd NameLoad Num keyword Call AttributeLoad Str attr NameLoad comprehension NameStore Call NameLoad Num Assign AttributeStore NameLoad attr BinOpBitOr Call NameLoad AttributeLoad NameLoad attr Call NameLoad AttributeLoad NameLoad attr Assign NameStore Call NameLoad Str keyword Call NameLoad keyword Call NameLoad keyword SubscriptLoad AttributeLoad NameLoad attr Index Num keyword SubscriptLoad AttributeLoad NameLoad attr Index Num keyword SubscriptLoad AttributeLoad NameLoad attr Index Num keyword SubscriptLoad AttributeLoad NameLoad attr Index Num keyword SubscriptLoad AttributeLoad NameLoad attr Index Num keyword SubscriptLoad AttributeLoad NameLoad attr Index Num keyword SubscriptLoad AttributeLoad NameLoad attr Index Num keyword SubscriptLoad AttributeLoad NameLoad attr Index Num Assign NameStore Call NameLoad Str keyword Call NameLoad keyword Call NameLoad keyword SubscriptLoad AttributeLoad NameLoad attr Index Num keyword SubscriptLoad AttributeLoad NameLoad attr Index Num keyword SubscriptLoad AttributeLoad NameLoad attr Index Num keyword SubscriptLoad AttributeLoad NameLoad attr Index Num keyword SubscriptLoad AttributeLoad NameLoad attr Index Num keyword SubscriptLoad AttributeLoad NameLoad attr Index Num keyword SubscriptLoad AttributeLoad NameLoad attr Index Num keyword SubscriptLoad AttributeLoad NameLoad attr Index Num AugAssignAdd AttributeStore NameLoad attr TupleLoad NameLoad NameLoad decorator_list decorator_list ClassDef bases NameLoad body FunctionDef arguments args NameParam defaults body Assign AttributeStore NameLoad attr ListComp Call NameLoad BinOpAdd NameLoad Num keyword Call AttributeLoad Str attr NameLoad comprehension NameStore Call NameLoad Num Assign AttributeStore NameLoad attr ListComp Call NameLoad BinOpAdd NameLoad Num keyword Call AttributeLoad Str attr NameLoad comprehension NameStore Call NameLoad Num Assign AttributeStore NameLoad attr Call NameLoad For NameStore Call NameLoad Num body AugAssignAdd AttributeStore AttributeLoad NameLoad attr attr Call AttributeLoad SubscriptLoad AttributeLoad NameLoad attr Index NameLoad attr SubscriptLoad AttributeLoad NameLoad attr Index NameLoad Assign AttributeStore NameLoad attr Call AttributeLoad AttributeLoad NameLoad attr attr AttributeLoad NameLoad attr Assign AttributeStore NameLoad attr Call AttributeLoad AttributeLoad NameLoad attr attr AttributeLoad NameLoad attr decorator_list decorator_list FunctionDef arguments args defaults body Assign NameStore Call NameLoad Expr Call AttributeLoad Call NameLoad NameLoad AttributeLoad NameLoad attr keyword Str attr Str Assign NameStore Call NameLoad Expr Call AttributeLoad Call NameLoad NameLoad AttributeLoad NameLoad attr keyword Str attr Str Expr Call AttributeLoad NameLoad attr ListLoad Str Str Str Str Str decorator_list If CompareEq NameLoad Str body Expr Call NameLoad
N/A N/A subprocess migen * migen.fhdl.verilog convert ParentModule N/A Module N/A __init__ N/A N/A self N/A N/A N/A N/A self inputs N/A N/A Signal N/A x 1 name N/A N/A input{} format x N/A x N/A range 4 N/A N/A self trans N/A N/A Signal N/A x 1 N/A x N/A range 4 N/A N/A self outputs N/A N/A Signal N/A x 1 name N/A N/A output{} format x N/A x N/A range 4 N/A N/A self io N/A N/A set N/A self inputs N/A set N/A self outputs N/A i N/A Instance ChildModule i_master_clk N/A ClockSignal i_master_rst N/A ResetSignal i_input0 N/A N/A self inputs N/A 0 i_input1 N/A N/A self inputs N/A 1 i_input2 N/A N/A self inputs N/A 2 i_input3 N/A N/A self inputs N/A 3 o_output0 N/A N/A self trans N/A 0 o_output1 N/A N/A self trans N/A 1 o_output2 N/A N/A self trans N/A 2 o_output3 N/A N/A self trans N/A 3 N/A j N/A Instance ChildModule i_master_clk N/A ClockSignal i_master_rst N/A ResetSignal i_input0 N/A N/A self trans N/A 0 i_input1 N/A N/A self trans N/A 1 i_input2 N/A N/A self trans N/A 2 i_input3 N/A N/A self trans N/A 3 o_output0 N/A N/A self outputs N/A 0 o_output1 N/A N/A self outputs N/A 1 o_output2 N/A N/A self outputs N/A 2 o_output3 N/A N/A self outputs N/A 3 N/A N/A self specials N/A i j N/A N/A ChildModule N/A Module N/A __init__ N/A N/A self N/A N/A N/A N/A self inputs N/A N/A Signal N/A x 1 name_override N/A N/A input{} format x N/A x N/A range 4 N/A N/A self outputs N/A N/A Signal N/A x 1 name_override N/A N/A output{} format x N/A x N/A range 4 N/A N/A self io N/A set N/A x N/A range 4 N/A N/A N/A N/A self sync master N/A N/A N/A N/A self outputs N/A x eq N/A N/A self inputs N/A x N/A N/A self io N/A N/A N/A self io union N/A self inputs N/A N/A self io N/A N/A N/A self io union N/A self outputs N/A N/A test_instance_module N/A N/A N/A N/A N/A sub N/A ChildModule N/A N/A N/A N/A convert sub N/A sub io name ChildModule write ChildModule.v N/A im N/A ParentModule N/A N/A N/A N/A convert im N/A im io name ParentModule write ParentModule.v N/A N/A N/A subprocess check_call N/A iverilog -W all ParentModule.v ChildModule.v N/A N/A N/A __name__ __main__ N/A N/A N/A test_instance_module