Module ImportFrom alias ImportFrom alias Import alias Assign NameStore Str FunctionDef arguments args defaults body Assign NameStore Call AttributeLoad NameLoad attr Assign NameStore Call AttributeLoad NameLoad attr ImportFrom alias ImportFrom alias Assign NameStore Call NameLoad Assign NameStore Call AttributeLoad NameLoad attr NameLoad Assign NameStore Call NameLoad Assign NameStore Call AttributeLoad NameLoad attr NameLoad Assert CompareEq NameLoad NameLoad decorator_list
N/A __future__ absolute_import __future__ print_function N/A fsm_make_if N/A expected_verilog 
module blinkled #
  (
   parameter WIDTH = 8
   )
  (
   input CLK, 
   input RST, 
   output reg [WIDTH-1:0] LED
   );
  reg [32-1:0] count;
  reg [32-1:0] fsm;
  localparam fsm_init = 0;
  localparam fsm_1 = 1;
  localparam fsm_2 = 2;
  localparam fsm_3 = 3;
  localparam fsm_4 = 4;

  always @(posedge CLK) begin
    if(RST) begin
      fsm <= fsm_init;
      count <= 0;
      LED <= 0;
    end else begin
      if(fsm == fsm_init) begin
        count <= count + 1;
        fsm <= fsm_1;
      end
      if(fsm == fsm_1) begin
        count <= count + 2;
        fsm <= fsm_2;
      end 
      if(fsm == fsm_2) begin
        count <= count + 3;
        fsm <= fsm_3;
      end 
      if(fsm == fsm_3) begin
        if(count < 1024) begin
          fsm <= fsm_init;
        end else begin
          fsm <= fsm_4;
        end
      end 
      if(fsm == fsm_4) begin
        LED <= LED + 1;
        fsm <= fsm_2;
      end
    end
  end
endmodule
 test N/A N/A N/A N/A N/A test_module N/A N/A fsm_make_if mkLed N/A code N/A N/A test_module to_verilog pyverilog.vparser.parser VerilogParser pyverilog.ast_code_generator.codegen ASTCodeGenerator N/A parser N/A VerilogParser N/A expected_ast N/A N/A parser parse expected_verilog N/A codegen N/A ASTCodeGenerator N/A expected_code N/A N/A codegen visit expected_ast N/A N/A expected_code code N/A