Module ImportFrom alias ImportFrom alias Assign NameStore ListLoad TupleLoad Str Num Call NameLoad Str Call NameLoad Str TupleLoad Str Num Call NameLoad Str Call NameLoad Str Call NameLoad Str TupleLoad Str Num Call NameLoad Str Call NameLoad Str Call NameLoad Str TupleLoad Str Num Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Call NameLoad Str Assign NameStore ListLoad TupleLoad Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str Str ClassDef bases NameLoad body Assign NameStore Str Assign NameStore Num FunctionDef arguments args NameParam defaults body Expr Call AttributeLoad NameLoad attr NameLoad Str NameLoad NameLoad decorator_list decorator_list
N/A migen.build.generic_platform * migen.build.xilinx XilinxPlatform N/A _ios N/A N/A clk0 0 N/A Pins N9 N/A IOStandard LVCMOS18 N/A fpga_reset 0 N/A Pins T9 N/A IOStandard LVCMOS18 N/A Drive 8 N/A fpga_initb 0 N/A Pins T12 N/A IOStandard LVCMOS18 N/A Drive 8 N/A weim 0 N/A Subsignal cs4_dtack N/A Pins R3 N/A IOStandard LVCMOS18 N/A Drive 8 N/A Subsignal cs5n N/A Pins P10 N/A IOStandard LVCMOS18 N/A Subsignal eb0n N/A Pins P9 N/A IOStandard LVCMOS18 N/A Subsignal oen N/A Pins R9 N/A IOStandard LVCMOS18 N/A Subsignal data N/A Pins T5 T6 P7 N8 P12 T13 R13 T14 P5 N6 T3 T11 T4 R5 M10 T10 N/A IOStandard LVCMOS18 N/A Drive 8 N/A Subsignal addr N/A Pins N5 L7 M7 M8 L8 L9 L10 M11 P11 N11 N12 P13 N/A IOStandard LVCMOS18 N/A _connectors N/A N/A J2 None None None None None None None None None None None None None None None None None None None None None None C16 C15 D16 None B14 B15 A13 A14 D11 C12 A10 B10 A9 C9 B8 A8 B6 A6 B4 A4 None N3 R1 P1 N1 M1 H3 K1 J1 H1 G1 F1 E1 D1 C1 None None None None None None None C2 D3 D4 F4 G2 J2 K3 J3 N2 P2 M4 L6 None None A3 B3 A5 C5 D7 C6 C8 D8 C10 D9 C11 A11 D13 C13 None None None D15 E13 D14 E14 F13 None None None None None None None None None None None None None None None None None Platform N/A XilinxPlatform N/A N/A default_clk_name clk0 N/A default_clk_period 10 __init__ N/A N/A self N/A N/A N/A N/A N/A XilinxPlatform __init__ self xc3s200a-ft256-4 _ios _connectors N/A N/A