Module ImportFrom alias ImportFrom alias Import alias Import alias ImportFrom alias Assign NameStore BinOpAdd Call AttributeLoad AttributeLoad NameLoad attr attr Call AttributeLoad AttributeLoad NameLoad attr attr Call AttributeLoad AttributeLoad NameLoad attr attr Call AttributeLoad AttributeLoad NameLoad attr attr NameLoad Str Assign NameStore Str FunctionDef arguments args defaults body Assign NameStore ListLoad BinOpAdd NameLoad Str Assign NameStore Str Assign NameStore NameLoad Assign NameStore NameLoad Assign NameStore NameLoad Assign NameStore NameLoad Assign NameStore Call NameLoad NameLoad NameLoad keyword NameLoad keyword NameLoad keyword NameLoad keyword NameLoad Expr Call AttributeLoad NameLoad attr Assign NameStore Call AttributeLoad NameLoad attr Assign NameStore Call AttributeLoad NameLoad attr Assign NameStore Call AttributeLoad NameLoad attr Assign NameStore Call AttributeLoad NameLoad attr Assign NameStore ListLoad Expr Call AttributeLoad NameLoad attr Call AttributeLoad SubscriptLoad SubscriptLoad Call NameLoad Call AttributeLoad NameLoad attr Index Num Index Num attr Expr Call AttributeLoad NameLoad attr Str Assign NameStore Call AttributeLoad Str attr NameLoad Expr Call NameLoad NameLoad Assert CompareEq NameLoad NameLoad Assert CompareEq Call AttributeLoad SubscriptLoad SubscriptLoad Call NameLoad Call AttributeLoad NameLoad attr Index Num Index Num attr Num Assert CompareEq Call AttributeLoad SubscriptLoad SubscriptLoad Call NameLoad Call AttributeLoad NameLoad attr Index Num Index Num attr Num decorator_list If CompareEq NameLoad Str body Expr Call NameLoad
N/A __future__ absolute_import __future__ print_function N/A os N/A sys pyverilog.dataflow.dataflow_analyzer VerilogDataflowAnalyzer N/A codedir N/A N/A N/A N/A os path dirname N/A N/A N/A os path dirname N/A N/A N/A os path dirname N/A N/A N/A os path abspath __file__ /verilogcode/ N/A expected (Bind dest:TOP.cnt tree:(Branch Cond:(Partselect Var:(Terminal TOP.RST) MSB:(IntConst 0) LSB:(IntConst 0)) True:(IntConst 'd0)))
 test N/A N/A N/A N/A N/A filelist N/A N/A codedir ptr_clock_reset.v N/A topmodule TOP N/A noreorder False N/A nobind False N/A include None N/A define None N/A analyzer N/A VerilogDataflowAnalyzer filelist topmodule noreorder noreorder nobind nobind preprocess_include include preprocess_define define N/A N/A N/A analyzer generate N/A directives N/A N/A analyzer get_directives N/A instances N/A N/A analyzer getInstances N/A terms N/A N/A analyzer getTerms N/A binddict N/A N/A analyzer getBinddict N/A output N/A N/A N/A N/A output append N/A N/A N/A N/A N/A list N/A N/A binddict values N/A 0 N/A 0 tostr N/A N/A N/A output append N/A rslt N/A N/A join output N/A N/A print rslt N/A N/A rslt expected N/A N/A N/A N/A N/A N/A N/A list N/A N/A binddict values N/A 0 N/A 0 getClockBit 2 N/A N/A N/A N/A N/A N/A N/A list N/A N/A binddict values N/A 0 N/A 0 getResetBit 0 N/A N/A N/A __name__ __main__ N/A N/A N/A test