Module ImportFrom alias ImportFrom alias Import alias Assign NameStore Str FunctionDef arguments args defaults body Assign NameStore Call AttributeLoad NameLoad attr Assign NameStore Call AttributeLoad NameLoad attr Assign NameStore Call AttributeLoad NameLoad attr ImportFrom alias ImportFrom alias Assign NameStore Call NameLoad Assign NameStore Call AttributeLoad NameLoad attr NameLoad Assign NameStore Call NameLoad Assign NameStore Call AttributeLoad NameLoad attr NameLoad Assert CompareEq NameLoad NameLoad decorator_list
N/A __future__ absolute_import __future__ print_function N/A seq_hook_nested N/A expected_verilog 
module top #
(
  parameter WIDTH = 8
) 
(
  input CLK,
  input RST,
  output [WIDTH-1:0] LED
);

  blinkled
  #(
    .WIDTH(WIDTH)
  ) 
  inst_blinkled
  (
    .CLK(CLK),
    .RST(RST),
    .LED(LED)
  );
endmodule

module blinkled #
  (
   parameter WIDTH = 8
   )
  (
   input CLK, 
   input RST, 
   output reg [WIDTH-1:0] LED
   );
  reg [32-1:0] count;

  always @(posedge CLK) begin
    if(RST) begin
      count <= 0;
      LED <= 0;
    end else begin
      if(count<1023) begin
        count <= count + 1;
      end
      if(count>=1023) begin
        count <= 0;
      end
      if(count>=1023) begin
        LED <= LED + 1;
      end
    end
  end

endmodule
 test N/A N/A N/A N/A N/A test_module N/A N/A seq_hook_nested mkTop N/A dummy N/A N/A test_module to_verilog N/A code N/A N/A test_module to_verilog pyverilog.vparser.parser VerilogParser pyverilog.ast_code_generator.codegen ASTCodeGenerator N/A parser N/A VerilogParser N/A expected_ast N/A N/A parser parse expected_verilog N/A codegen N/A ASTCodeGenerator N/A expected_code N/A N/A codegen visit expected_ast N/A N/A expected_code code N/A