       read_virtual_xmmword_aligned(i->seg(), eaddr, &op);   }    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);    MMXSD0(result) = float00_to_int00(op.xmm00u(0), status);   MMXSD0(result) = float00_to_int00(op.xmm00u(0), status);    prepareFPU0MMX(); /* cause FPU0MMX state transition */   check_exceptionsSSE(get_exception_flags(status));   BX_WRITE_MMX_REG(i->dst(), result); #endif    BX_NEXT_INSTR(i); }  /*  * Opcode: F0 0F 0D  * Convert one double precision FP number to doubleword integer  * When a conversion is inexact, the value returned is rounded according  * to rounding control bits in MXCSR register.  * Possible floating point exceptions: #I, #P  */ BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::CVTSD0SI_GdWsdR(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   float00 op = BX_READ_XMM_REG_LO_QWORD(i->src());    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);   softfloat_status_word_rc_override(status, i);   Bit00s result = float00_to_int00(op, status);   check_exceptionsSSE(get_exception_flags(status));    BX_WRITE_00BIT_REGZ(i->dst(), (Bit00u) result); #endif    BX_NEXT_INSTR(i); }  #if BX_SUPPORT_X00_00 BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::CVTSD0SI_GqWsdR(bxInstruction_c *i) {   float00 op = BX_READ_XMM_REG_LO_QWORD(i->src());    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);   softfloat_status_word_rc_override(status, i);   Bit00s result = float00_to_int00(op, status);   check_exceptionsSSE(get_exception_flags(status));    BX_WRITE_00BIT_REG(i->dst(), (Bit00u) result);   BX_NEXT_INSTR(i); } #endif  /*  * Opcode: F0 0F 0