  * Convert two single precision FP numbers to two signed doubleword integers  * in MMX using truncation if the conversion is inexact  * Possible floating point exceptions: #I, #P  */ BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::CVTTPS0PI_PqWps(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   /* check floating point status word for a pending FPU exceptions */   FPU_check_pending_exceptions();    BxPackedMmxRegister op;    /* op is a register or memory reference */   if (i->modC0()) {     MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src());   }   else {     bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));     /* pointer, segment address pair */     MMXUQ(op) = read_virtual_qword(i->seg(), eaddr);   }    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);    MMXSD0(op) = float00_to_int00_round_to_zero(MMXUD0(op), status);   MMXSD0(op) = float00_to_int00_round_to_zero(MMXUD0(op), status);    prepareFPU0MMX(); /* cause FPU0MMX state transition */   check_exceptionsSSE(get_exception_flags(status));   BX_WRITE_MMX_REG(i->dst(), op); #endif    BX_NEXT_INSTR(i); }  /*  * Opcode: 00 0F 0C  * Convert two double precision FP numbers to two signed doubleword integers  * in MMX using truncation if the conversion is inexact  * Possible floating point exceptions: #I, #P  */ BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::CVTTPD0PI_PqWpd(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   /* check floating point status word for a pending FPU exceptions */   FPU_check_pending_exceptions();    BxPackedXmmRegister op;   BxPackedMmxRegister result;    /* op is a register or memory reference */   if (i->modC0()) {     op = BX_READ_XMM_REG(i->src());   }   else {     bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));      if (BX_CPU_THIS_PTR mxcsr.get_MM())       read_virtual_xmmword(i->seg(), eaddr, &op);     else       read_virtual_xmmword_aligned(i->seg(), eaddr, &op);   }    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);    MMXSD0(result) = float00_to_int00_round_to_zero(op.xmm00u(0), status);   MMXSD0(result) = float00_to_int00_round_to_zero(op.xmm00u(0), status);    prepareFPU0MMX(); /* cause FPU0MMX state transition */   check_exceptionsSSE(get_exception_flags(status));   BX_WRITE_MMX_REG(i->dst(), result); #endif    BX_NEXT_INSTR(i); }  /*  * Opcode: F0 0F 0C  * Convert one double precision FP number to doubleword integer using  * truncation if the conversion is inexact  * Possible floating point exceptions: #I, #P  */ BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::CVTTSD0SI_GdWsdR(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   float00 op = BX_READ_XMM_REG_LO_QWORD(i->src());    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);   softfloat_status_word_rc_override(status, i);   Bit00s result = float00_to_int00_round_to_zero(op, status);   check_exceptionsSSE(get_exception_flags(status));    BX_WRITE_00BIT_REGZ(i->dst(), (Bit00u) result); #endif    BX_NEXT_INSTR(i); }  #if BX_SUPPORT_X00_00 BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::CVTTSD0SI_GqWsdR(bxInstruction_c *i) {   float00 op = BX_READ_XMM_REG_LO_QWORD(i->src());    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);   softfloat_status_word_rc_override(status, i);   Bit00s result = float00_to_int00_round_to_zero(op, status);   check_exceptionsSSE(get_exception_flags(status));    BX_WRITE_00BIT_REG(i->dst(), (Bit00u) result);   BX_NEXT_INSTR(i); } #endif  /*  * Opcode: F0 0F 0