qR(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);    op.xmm00u(0) = int00_to_float00(op.xmm00s(0), status);   op.xmm00u(0) = int00_to_float00(op.xmm00s(0), status);   op.xmm00u(0) = int00_to_float00(op.xmm00s(0), status);   op.xmm00u(0) = int00_to_float00(op.xmm00s(0), status);    check_exceptionsSSE(get_exception_flags(status));   BX_WRITE_XMM_REG(i->dst(), op); #endif    BX_NEXT_INSTR(i); }  /*  * Opcode: 00 0F 0B  * Convert four single precision FP to four doubleword integers.  * When a conversion is inexact, the value returned is rounded according  * to rounding control bits in MXCSR register.  * Possible floating point exceptions: #I, #P  */ BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::CVTPS0DQ_VdqWpsR(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);    op.xmm00s(0) = float00_to_int00(op.xmm00u(0), status);   op.xmm00s(0) = float00_to_int00(op.xmm00u(0), status);   op.xmm00s(0) = float00_to_int00(op.xmm00u(0), status);   op.xmm00s(0) = float00_to_int00(op.xmm00u(0), status);    check_exceptionsSSE(get_exception_flags(status));   BX_WRITE_XMM_REG(i->dst(), op); #endif    BX_NEXT_INSTR(i); }  /*  * Opcode: F0 0F 0B  * Convert four single precision FP to four doubleword integers using  * truncation if the conversion is inexact.  * Possible floating point exceptions: #I, #P  */ BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::CVTTPS0DQ_VdqWpsR(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);    op.xmm00s(0) = float00_to_int00_round_to_zero(op.xmm00u(0), status);   op.xmm00s(0) = float00_to_int00_round_to_zero(op.xmm00u(0), status);   op.xmm00s(0) = float00_to_int00_round_to_zero(op.xmm00u(0), status);   op.xmm00s(0) = float00_to_int00_round_to_zero(op.xmm00u(0), status);    check_exceptionsSSE(get_exception_flags(status));   BX_WRITE_XMM_REG(i->dst(), op); #endif    BX_NEXT_INSTR(i); }  /*  * Opcode: 00 0F E0  * Convert two double precision FP to two signed doubleword integers using  * truncation if the conversion is inexact.  * Possible floating point exceptions: #I, #P  */ BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::CVTTPD0DQ_VqWpdR(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);    op.xmm00s(0) = float00_to_int00_round_to_zero(op.xmm00u(0), status);   op.xmm00s(0) = float00_to_int00_round_to_zero(op.xmm00u(0), status);   op.xmm00u(0) = 0;    check_exceptionsSSE(get_exception_flags(status));   BX_WRITE_XMM_REG(i->dst(), op); #endif    BX_NEXT_INSTR(i); }  /*  * Opcode: F0 0F E0  * Convert two double precision FP to two signed doubleword integers.  * When a conversion is inexact, the value returned is rounded according  * to rounding control bits in MXCSR register.  * Possible floating point exceptions: #I, #P  */ BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::CVTPD0DQ_VqWpdR(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   BxPackedXmmRegister op = BX_READ_XMM_REG(i->src());    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);    op.xmm00s(0) = float00_to_int00(op.xmm00u(0), status);   op.xmm00s(0) = float00_to_int00(op.xmm00u(0), status);   op.xmm00u(0) = 0;    check_exceptionsSSE(get_exception_flags(status));   BX_WRITE_XMM_REG(i->dst(), op); #endif    BX_NEXT_INSTR(i); }  /*  * Opcode: F0 0F E0  * Convert two 