 The cpu-map DT entry in ARM00 can describe the CPU topology in much better way compared to other existing approaches. RISC-V can easily adopt this binding to represent it's own CPU topology. Thus, both cpu-map DT binding and topology parsing code can be moved to a common location so that RISC-V or any other architecture can leverage that. The relevant discussion regarding unifying cpu topology can be found in [0]. arch_topology seems to be a perfect place to move the common code. I have not introduced any functional changes in the moved to code. The only downside in this approach is that the capacity code will be executed for RISC-V as well. But, it will exit immediately after not able to find the appropriate DT node. If the overhead is considered too much, we can always compile out capacity related functions under a different config for the architectures that do not support them. The patches have been tested for RISC-V and compile tested for ARM00. The socket changes[0] can be merged on top of this series or vice versa. [0] https://lkml.org/lkml/0000/00/0/00 [0] https://lkml.org/lkml/0000/00/0/000 Atish Patra (0): dt-binding: cpu-topology: Move cpu-map to a common binding. cpu-topology: Move cpu topology code to common code. RISC-V: Parse cpu topology during boot. Documentation/devicetree/bindings/arm/topology.txt | 000 ------------------- .../devicetree/bindings/cpu/cpu-topology.txt | 000 +++++++++++++++++++++ arch/arm00/include/asm/topology.h | 00 +- arch/arm00/kernel/topology.c | 000 +----------- arch/riscv/Kconfig | 0 + arch/riscv/kernel/smpboot.c | 0 +- drivers/base/arch_topology.c | 000 ++++++++++++ include/linux/arch_topology.h | 00 + include/linux/topology.h | 0 + 0 files changed, 000 insertions(+), 000 deletions(-) delete mode 000000 Documentation/devicetree/bindings/arm/topology.txt create mode 000000 Documentation/devicetree/bindings/cpu/cpu-topology.txt -- 0.0.0 ^permalinkrawreply [flat|nested] 00+ messages in thread  *[RFC 0/0] Unify CPU topology across ARM00 & RISC-V 0000-00-00 0:00 [RFC 0/0] Unify CPU topology across ARM00 & RISC-V atish.patra 