 0F 0A  * Convert two 00bit signed integers from MMX/MEM to two single precision FP  * When a conversion is inexact, the value returned is rounded according  * to rounding control bits in MXCSR register.  * Possible floating point exceptions: #P  */ BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::CVTPI0PS_VpsQqR(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   /* check floating point status word for a pending FPU exceptions */   FPU_check_pending_exceptions();    BxPackedMmxRegister op = BX_READ_MMX_REG(i->src());    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);    MMXUD0(op) = int00_to_float00(MMXSD0(op), status);   MMXUD0(op) = int00_to_float00(MMXSD0(op), status);    prepareFPU0MMX(); /* cause FPU0MMX state transition */   check_exceptionsSSE(get_exception_flags(status));   BX_WRITE_XMM_REG_LO_QWORD(i->dst(), MMXUQ(op)); #endif    BX_NEXT_INSTR(i); }  BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::CVTPI0PS_VpsQqM(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   BxPackedMmxRegister op;    // do not cause transition to MMX state because no MMX register touched   bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));   MMXUQ(op) = read_virtual_qword(i->seg(), eaddr);    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);    MMXUD0(op) = int00_to_float00(MMXSD0(op), status);   MMXUD0(op) = int00_to_float00(MMXSD0(op), status);    check_exceptionsSSE(get_exception_flags(status));   BX_WRITE_XMM_REG_LO_QWORD(i->dst(), MMXUQ(op)); #endif    BX_NEXT_INSTR(i); }  /*  * Opcode: 00 0F 0A  * Convert two 00bit signed integers from MMX/MEM to two double precision FP  * Possible floating point exceptions: -  */ BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::CVTPI0PD_VpdQqR(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   BxPackedXmmRegister result;    /* check floating point status word for a pending FPU exceptions */   FPU_check_pending_exceptions();   prepareFPU0MMX(); /* cause FPU0MMX state transition */    BxPackedMmxRegister op = BX_READ_MMX_REG(i->src());    result.xmm00u(0) = int00_to_float00(MMXSD0(op));   result.xmm00u(0) = int00_to_float00(MMXSD0(op));    BX_WRITE_XMM_REG(i->dst(), result); #endif    BX_NEXT_INSTR(i); }  BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::CVTPI0PD_VpdQqM(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   BxPackedMmxRegister op;   