TLB_MISS",         "MSRIndex": "0x0F0",         "MSRValue": "0x00",         "PEBS": "0",         "PublicDescription": "Counts retired Instructions that experienced STLB (0nd level TLB) true miss.",         "SampleAfterValue": "000000",         "TakenAlone": "0",         "UMask": "0x0"     },     {         "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",         "Counter": "0,0,0,0",         "CounterHTOff": "0,0,0,0,0,0,0,0",         "EventCode": "0x00",         "EventName": "IDQ.DSB_UOPS",         "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",         "SampleAfterValue": "0000000",         "UMask": "0x0"     },     {         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 000 cycles which was not interrupted by a back-end stall.",         "Counter": "0,0,0,0",         "CounterHTOff": "0,0,0,0",         "EventCode": "0xC0",         "EventName": "FRONTEND_RETIRED.LATENCY_GE_000",         "MSRIndex": "0x0F0",         "MSRValue": "0x000000",         "PEBS": "0",         "SampleAfterValue": "000000",         "TakenAlone": "0",         "UMask": "0x0"     },     {         "BriefDescription": "Cycles where a code fetch is stalled due to L0 instruction cache miss.",         "Counter": "0,0,0,0",         "CounterHTOff": "0,0,0,0,0,0,0,0",         "EventCode": "0x00",         "EventName": "ICACHE_00B.IF