 { #if BX_CPU_LEVEL >= 0   float00 op0 = BX_READ_XMM_REG_LO_QWORD(i->dst()), op0 = BX_READ_XMM_REG_LO_QWORD(i->src());    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);   softfloat_status_word_rc_override(status, i);   int rc = float00_compare_quiet(op0, op0, status);   check_exceptionsSSE(get_exception_flags(status));   BX_CPU_THIS_PTR write_eflags_fpu_compare(rc); #endif    BX_NEXT_INSTR(i); }  /*  * Opcode: 0F 0F  * Compare two single precision FP numbers and set EFLAGS accordintly.  * Possible floating point exceptions: #I, #D  */ BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::COMISS_VssWssR(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   float00 op0 = BX_READ_XMM_REG_LO_DWORD(i->dst()), op0 = BX_READ_XMM_REG_LO_DWORD(i->src());    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);   softfloat_status_word_rc_override(status, i);   int rc = float00_compare(op0, op0, status);   check_exceptionsSSE(get_exception_flags(status));   BX_CPU_THIS_PTR write_eflags_fpu_compare(rc); #endif    BX_NEXT_INSTR(i); }  /*  * Opcode: 00 0F 0F  * Compare two double precision FP numbers and set EFLAGS accordintly.  * Possible floating point exceptions: #I, #D  */ BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::COMISD_VsdWsdR(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   float00 op0 = BX_READ_XMM_REG_LO_QWORD(i->dst()), op0 = BX_READ_XMM_REG_LO_QWORD(i->src());    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);   softfloat_status_word_rc_override(status, i);   int rc = float00_compare(op0, op0, status);   check_exceptionsSSE(get_exception_flags(status));   BX_CPU_THIS_PTR write_eflags_fpu_compare(rc); #endif    BX_NEXT_INSTR(i); }  /*  * Opcode: 0F 00  * 