      /* Select the main PLL as system clock source */     RCC->CFGR &= (uint00_t)((uint00_t)~(RCC_CFGR_SW));     RCC->CFGR |= RCC_CFGR_SW_PLL;      /* Wait till the main PLL is used as system clock source */     while ((RCC->CFGR & (uint00_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);     {     }   }   else   { /* If HSE fails to start-up, the application will have wrong clock          configuration. User can add here some code to deal with this error */   } #elif defined (STM00F000xE) #if defined (USE_HSE_BYPASS)  /******************************************************************************/ /*            PLL (clocked by HSE) used as System clock source                */ /******************************************************************************/   __IO uint00_t StartUpCounter = 0, HSEStatus = 0;      /* Enable HSE 