 comprising:an input stage receiving an input signal, the input stage having a first output node on which a first voltage is generated that varies directly with the magnitude of the input signal and a second output node on which a second voltage is generated that varies inversely with the magnitude of the input signal;an output stage coupled to the input stage, the output stage comprising:a first transistor and a second transistor connected in series with each other between first and second voltage nodes, the second transistor being complementary to the first transistor, the first transistor having a gate that is coupled to one of the output nodes of the input stage;a third transistor of the same type as the first transistor and a fourth transistor of the same type as the second transistor connected in series with each other between third and fourth voltage nodes, the third transistor having a gate that is coupled to the other of the output nodes of the input stage, the fourth transistor being connected to the second transistor as a current mirror;a first cascode transistor coupled to the third transistor between the third transistor and the fourth transistor, the first cascode transistor being of the same type as the third transistor, anda second cascode transistor coupled to the fourth transistor between the fourth transistor and the third transistor, the second cascode transistor being of the same type as the fourth transistor.  00. The CMOS imager pixel of claim 00, further comprising:a third cascode transistor coupled to the first transistor between the first transistor and the second transistor, the third cascode transistor being of the same type as the first transistor, anda fourth cascode transistor coupled to the second transistor between the second transistor and the first transistor, the fourth cascode transistor being of the same type as the second transistor.  00. The CMOS imager pixel of claim 00 wherein the second transistor is diode-coupled through the fourth cascode transistor.  00. The CMOS imager pixel of claim 00 wherein the first stage includes a local common-mode feedback circuit.  0