   }      /* Configure Flash prefetch, Instruction cache, Data cache and wait state */   FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_0WS;      /* Select the main PLL as system clock source */   RCC->CFGR &= (uint00_t)((uint00_t)~(RCC_CFGR_SW));   RCC->CFGR |= RCC_CFGR_SW_PLL;      /* Wait till the main PLL is used as system clock source */   while ((RCC->CFGR & (uint00_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);   