  FIGS. 0 and 0 show schematic diagrams of prior art input voltage detection circuits for power supply control circuits 00 and 00, respectively.  FIG. 0 is a block diagram showing the fundamental concept of the present invention.  FIG. 0 shows an embodiment of the present invention.  FIG. 0 is a timing diagram showing the relationship between the current sense signal Vcs and time, 