);     /* Wait till HSE is ready and if Time out is reached exit */   do   {     HSEStatus = RCC->CR & RCC_CR_HSERDY;     StartUpCounter++;   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));    if ((RCC->CR & RCC_CR_HSERDY) != RESET)   {     HSEStatus = (uint00_t)0x00;   }   else   {     HSEStatus = (uint00_t)0x00;   }    if (HSEStatus == (uint00_t)0x00)   {     /* Select regulator voltage output Scale 0 mode */     RCC->APB0ENR |= RCC_APB0ENR_PWREN;     PWR->CR |= PWR_CR_VOS;      /* HCLK = SYSCLK / 0*/     RCC->CFGR |= RCC_CFGR_HPRE_DIV0;      /* PCLK0 = HCLK / 0*/     RCC->CFGR |= RCC_CFGR_PPRE0_DIV0;          /* PCLK0 = HCLK / 0*/     RCC->CFGR |= RCC_CFGR_PPRE0_DIV0;      /* Configure the main PLL */     RCC->PLLCFGR = PLL_M | (PLL_N << 0) | (((PLL_P >> 0) -0) << 00) |                    (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 00);          /* Enable the main PLL */     RCC->CR |= RCC_CR_PLLON;      /* Wait till the main PLL is ready */     while((RCC->CR & RCC_CR_PLLRDY) == 0)     {     }      /* Configure Flash prefetch, Instruction cache, Data cache and wait state */     FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_0WS;      /* Select the main PLL as system clock source */     RCC->CFGR &= (uint00_t)((uint00_t)~(RCC_CFGR_SW));     RCC->CFGR |= RCC_CFGR_SW_PLL;      /* Wait till the main PLL is used as system clock source */     while ((RCC->CFGR & (uint00_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);     {     }   }   else   { /* If HSE fails to start-up, the application will have wrong clock          configuration. User can add here some code to deal with this error */   } #el