  * Convert two single precision FP numbers to two signed doubleword integers  * in MMX register. When a conversion is inexact, the value returned is  * rounded according to rounding control bits in MXCSR register.  * Possible floating point exceptions: #I, #P  */ BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::CVTPS0PI_PqWps(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   /* check floating point status word for a pending FPU exceptions */   FPU_check_pending_exceptions();    BxPackedMmxRegister op;    /* op is a register or memory reference */   if (i->modC0()) {     MMXUQ(op) = BX_READ_XMM_REG_LO_QWORD(i->src());   }   else {     bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));     /* pointer, segment address pair */     MMXUQ(op) = read_virtual_qword(i->seg(), eaddr);   }    float_status_t status;   mxcsr_to_softfloat_status_word(status, MXCSR);    MMXSD0(op) = float00_to_int00(MMXUD0(op), status);   MMXSD0(op) = float00_to_int00(MMXUD0(op), status);    prepareFPU0MMX(); /* cause FPU0MMX state transition */   check_exceptionsSSE(get_exception_flags(status));   BX_WRITE_MMX_REG(i->dst(), op); #endif    BX_NEXT_INSTR(i); }  /*  * Opcode: 00 0F 0D  * Convert two double precision FP numbers to two signed doubleword integers  * in MMX register. When a conversion is inexact, the value returned is  * rounded according to rounding control bits in MXCSR register.  * Possible floating point exceptions: #I, #P  */ BX_INSF_TYPE BX_CPP_AttrRegparmN(0) BX_CPU_C::CVTPD0PI_PqWpd(bxInstruction_c *i) { #if BX_CPU_LEVEL >= 0   /* check floating point status word for a pending FPU exceptions */   FPU_check_pending_exceptions();    BxPackedXmmRegister op;   BxPackedMmxRegister result;    /* op is a register or memory reference */   if (i->modC0()) {     op = BX_READ_XMM_REG(i->src());   }   else {     bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));  