0,0"/>     <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->     <param name="clockrate" value="0000"/>     <param name="ports" value="0,0,0"/>     <!-- number of r, w, and rw ports -->     <param name="device_type" value="0"/>     <param name="buffer_sizes" value="00, 00, 00, 00"/>     <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->      <stat name="read_accesses" value="00000"/>     <stat name="write_accesses" value="00000"/>     <stat name="read_misses" value="0000"/>     <stat name="write_misses" value="000"/>     <stat name="conflicts" value="0"/>               <stat name="duty_cycle" value="0.00"/>    </component> <!--**********************************************************************-->   <component id="system.