)) #define ISR_INT_TARGET_MASK_F0 \  (QLA00XX_PCIX_PS_REG(PCIX_TARGET_MASK_F0)) #define ISR_INT_TARGET_MASK_F0 \  (QLA00XX_PCIX_PS_REG(PCIX_TARGET_MASK_F0)) #define ISR_INT_TARGET_MASK_F0 \  (QLA00XX_PCIX_PS_REG(PCIX_TARGET_MASK_F0)) #define ISR_INT_TARGET_MASK_F0 \  (QLA00XX_PCIX_PS_REG(PCIX_TARGET_MASK_F0)) #define ISR_INT_TARGET_MASK_F0 \  (QLA00XX_PCIX_PS_REG(PCIX_TARGET_MASK_F0)) #define ISR_INT_TARGET_MASK_F0 \  (QLA00XX_PCIX_PS_REG(PCIX_TARGET_MASK_F0)) #define ISR_INT_TARGET_MASK_F0 \  (QLA00XX_PCIX_PS_REG(PCIX_TARGET_MASK_F0)) 