 TLB) true miss.",         "SampleAfterValue": "000000",         "TakenAlone": "0",         "UMask": "0x0"     },     {         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",         "Counter": "0,0,0,0",         "CounterHTOff": "0,0,0,0,0,0,0,0",         "CounterMask": "0",         "EventCode": "0x00",         "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",         "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.",         "SampleAfterValue": "0000000",         "UMask": "0x00"     },     {         "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 000 cycles which was not interrupted by a back-end stall.",         "Counter": "0,0,0,0",         "CounterHTOff": "0,0,0,0",         "EventCode": "0xC0",         "EventName": "FRONTEND_RETIRED.LATENCY_GE_000",         "MSRIndex": "0x0F0",         "MSRValue": "0x000000",         "PEBS": "0",         "SampleAfterValue": "000000",         "TakenAlone": "0",         "UMask": "0x0"     },     {         "BriefDescription": "Cycles MITE is delivering 0 Uops",         "Counter": "0,0,0,0",         "CounterHTOff": "0,0,0,0,0,0,0,0",         "CounterMask": "0",         "EventCode": "0x00",         "EventName": "IDQ.ALL_MITE_CYCLES_0_UOPS",         "PublicDescription": "Counts the number of cycles 0 uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",         "SampleAfterValue": "0000000",         "UMask": "0x00"     },     {         "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 0 Uops",         "Counter": "0,0,0,0",         "CounterHTOff": "0,0,0,0,0,0,0,0",         "CounterMask": "0",         "EventCode": "0x00",         "EventName": "IDQ.ALL_DSB_CYCLES_0_UOPS",         "PublicDescription": "Counts the number of cycles 0 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.",         "SampleAfterValue": "0000000",         "UMask": "0x00"     },     {         "BriefDescription": "Cycles where a code fetch is stalled due to L0 instruction cache 