);     /* Wait till HSE is ready and if Time out is reached exit */   do   {     HSEStatus = RCC->CR & RCC_CR_HSERDY;     StartUpCounter++;   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));    if ((RCC->CR & RCC_CR_HSERDY) != RESET)   {     HSEStatus = (uint00_t)0x00;   }   else   {     HSEStatus = (uint00_t)0x00;   }    if (HSEStatus == (uint00_t)0x00)   {     /* Select regulator voltage output Scale 0 mode */     RCC->APB0ENR |= RCC_APB0ENR_PWREN;     PWR->CR |= PWR_CR_VOS;      /* HCLK = SYSCLK / 0*/     RCC->CFGR |= RCC_CFGR_HPRE_DIV0;  #if defined (STM00F00_00xxx) || defined (STM00F000_000xx) || defined (STM00F000_000xx)           /* PCLK0 = HCLK / 0*/     RCC->CFGR |= RCC_CFGR_PPRE0_DIV0;          /* PCLK0 = HCLK / 0*/     RCC->CFGR |= RCC_CFGR_PPRE0_DIV0; #endif /* STM00F00_00xxx || STM00F000_000x || STM00F000_000xx */  #if defined (STM00F000xx)     /* PCLK0 = HCLK / 0*/     RCC->CFGR |= RCC_CFGR_PPRE0_DIV0;          /* PCLK0 = HCLK / 0*/     RCC->CFGR |= RCC_CFGR_PPRE0_DIV0; #endif /* STM00F00