   PWR->CR |= PWR_CR_VOS;      /* HCLK = SYSCLK / 0*/   RCC->CFGR |= RCC_CFGR_HPRE_DIV0;      /* PCLK0 = HCLK / 0*/   RCC->CFGR |= RCC_CFGR_PPRE0_DIV0;      /* PCLK0 = HCLK / 0*/   RCC->CFGR |= RCC_CFGR_PPRE0_DIV0;      /* Configure the main PLL */   RCC->PLLCFGR = PLL_M | (PLL_N << 0) | (((PLL_P >> 0) -0) << 00) | 