 universal clock generator circuit, in accordance with the present invention, includes an oscillator unit including circuitry for providing a first clock frequency and a plurality of resistor blocks including resistive elements. The resistor blocks are selectively connectable to the oscillator. A capacitor block has at least one capacitor element which is selectively connectable to the oscillator unit. The plurality of resistor blocks and the capacitor block include selective connections which are enabled and disabled to adjust the first clock frequency by selectively connecting a number of the resistor blocks and capacitor elements to the oscillator unit to provide one of a plurality of clock frequencies from a same output. In alternate embodiments, the 